repo_name
stringlengths 6
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snow4life/PipelinedDLX
|
alu/shifter_generic.vhd
|
2
|
1363
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity SHIFTER_GENERIC is
generic(N: integer);
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(4 downto 0);
LOGIC_ARITH: in std_logic; -- 1 = logic, 0 = arith
LEFT_RIGHT: in std_logic; -- 1 = left, 0 = right
SHIFT_ROTATE: in std_logic; -- 1 = shift, 0 = rotate
OUTPUT: out std_logic_vector(N-1 downto 0)
);
end entity SHIFTER_GENERIC;
architecture BEHAVIORAL of SHIFTER_GENERIC is
begin
SHIFT: process (A, B, LOGIC_ARITH, LEFT_RIGHT, SHIFT_ROTATE) is
begin
if SHIFT_ROTATE = '0' then
if LEFT_RIGHT = '0' then
OUTPUT <= to_StdLogicVector((to_bitvector(A)) ror (conv_integer(B)));
else
OUTPUT <= to_StdLogicVector((to_bitvector(A)) rol (conv_integer(B)));
end if;
else
if LEFT_RIGHT = '0' then
if LOGIC_ARITH = '0' then
OUTPUT <= to_StdLogicVector((to_bitvector(A)) sra (conv_integer(B)));
else
OUTPUT <= to_StdLogicVector((to_bitvector(A)) srl (conv_integer(B)));
end if;
else
if LOGIC_ARITH = '0' then
OUTPUT <= to_StdLogicVector((to_bitvector(A)) sla (conv_integer(B)));
else
OUTPUT <= to_StdLogicVector((to_bitvector(A)) sll (conv_integer(B)));
end if;
end if;
end if;
end process;
end architecture BEHAVIORAL;
|
lgpl-2.1
|
snow4life/PipelinedDLX
|
booth.vhd
|
1
|
2941
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity BOOTH is
generic(N: integer);
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
P: out std_logic_vector((2*N)-1 downto 0));
end entity BOOTH;
architecture BEHAVIORAL of BOOTH is
signal A_ext: std_logic_vector((2*N)-1 downto 0);
signal B_ext: std_logic_vector(N+1 downto 0);
type operands_array is array (0 to N/2) of std_logic_vector((2*N)-1 downto 0);
signal operand: operands_array;
signal operand_inverted: operands_array;
signal operand_doubled: operands_array;
signal operand_doubled_inverted: operands_array;
type decoded_array is array (0 to (N/2)) of std_logic_vector((2*N)-1 downto 0);
signal decoded: decoded_array;
type partial_products_array is array (2 to (N/2)+1) of std_logic_vector((2*N)-1 downto 0);
signal partial_products: partial_products_array;
begin
A_ext((2*N)-1 downto N) <= (others => '0');
A_ext(N-1 downto 0) <= A;
B_ext(N+1 downto N) <= "00";
B_ext(N-1 downto 0) <= B;
operand(0) <= A_ext;
operand_inverted(0) <= (not A_ext) + '1';
operand_doubled(0) <= to_StdLogicVector((to_bitvector(A_ext)) sll 1);
operand_doubled_inverted(0) <= to_StdLogicVector((to_bitvector(operand_inverted(0))) sll 1);
SHIFTS: for i in 1 to N/2 generate
operand(i) <= to_StdLogicVector((to_bitvector(operand(i-1))) sll 2);
operand_inverted(i) <= to_StdLogicVector((to_bitvector(operand_inverted(i-1))) sll 2);
operand_doubled(i) <= to_StdLogicVector((to_bitvector(operand_doubled(i-1))) sll 2);
operand_doubled_inverted(i) <= to_StdLogicVector((to_bitvector(operand_doubled_inverted(i-1))) sll 2);
end generate SHIFTS;
partial_products(2) <= decoded(0) + decoded(1);
PARTIAL_PRODUCT_GENERATOR: for i in 3 to (N/2)+1 generate
partial_products(i) <= partial_products(i-1) + decoded(i-1);
end generate PARTIAL_PRODUCT_GENERATOR;
decoded(0) <= conv_std_logic_vector(0, 2*N) when B_ext(1 downto 0) = "00" else
operand(0) when B_ext(1 downto 0) = "01" else
operand_doubled_inverted(0) when B_ext(1 downto 0) = "10" else
operand_inverted(0) when B_ext(1 downto 0) = "11";
ENCODER: for i in 1 to N/2 generate
decoded(i) <= conv_std_logic_vector(0, 2*N) when B_ext((i*2)+1 downto (i*2)-1) = "000" else
operand(i) when B_ext((i*2)+1 downto (i*2)-1) = "001" else
operand(i) when B_ext((i*2)+1 downto (i*2)-1) = "010" else
operand_doubled(i) when B_ext((i*2)+1 downto (i*2)-1) = "011" else
operand_doubled_inverted(i) when B_ext((i*2)+1 downto (i*2)-1) = "100" else
operand_inverted(i) when B_ext((i*2)+1 downto (i*2)-1) = "101" else
operand_inverted(i) when B_ext((i*2)+1 downto (i*2)-1) = "110" else
conv_std_logic_vector(0, 2*N) when B_ext((i*2)+1 downto (i*2)-1) = "111";
end generate ENCODER;
P <= partial_products((N/2)+1);
end architecture BEHAVIORAL;
|
lgpl-2.1
|
jaruiz/light8080
|
boards/de1/de1_top.vhdl
|
1
|
10933
|
--##############################################################################
-- Light8080 MPU demo on Terasic's DE-1 board.
--##############################################################################
--
-- This is a minimal demo of the light8080 MPU wrapper targetting Terasic's DE-1
-- development board for Cyclone-2 FPGAs.
-- Since the demo uses little board resources other than the serial port it
-- should be easy to port it to other platforms.
--
-- The MPU entity contains a block of RAM that is used for both program and
-- data. The BRAM is initialized at synthesis time with a constant taken from
-- package 'obj_code_pkg'. This package can be built from an object code file
-- in Intel HEX format with utility '/tools/build_rom' included with this
-- project. There's an example of this in the TB makefiles.
--
-- This demo has been built from a generic template for designs targetting the
-- DE-1 development board. The entity defines all the inputs and outputs present
-- in the actual board, whether or not they are used in the design at hand.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Package that contains the program object code in VHDL constant format.
use work.obj_code_pkg.all;
-- Define the entity outputs as they are connected in the DE-1 development
-- board. Many of the outputs will be left unused in this demo.
entity DE1_TOP is
port (
-- ***** Clocks
clk_50MHz : in std_logic;
-- ***** Flash 4MB
flash_addr : out std_logic_vector(21 downto 0);
flash_data : in std_logic_vector(7 downto 0);
flash_oe_n : out std_logic;
flash_we_n : out std_logic;
flash_reset_n : out std_logic;
-- ***** SRAM 256K x 16
sram_addr : out std_logic_vector(17 downto 0);
sram_data : inout std_logic_vector(15 downto 0);
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_ce_n : out std_logic;
sram_we_n : out std_logic;
-- ***** RS-232
rxd : in std_logic;
txd : out std_logic;
-- ***** Switches and buttons
switches : in std_logic_vector(9 downto 0);
buttons : in std_logic_vector(3 downto 0);
-- ***** Quad 7-seg displays
hex0 : out std_logic_vector(0 to 6);
hex1 : out std_logic_vector(0 to 6);
hex2 : out std_logic_vector(0 to 6);
hex3 : out std_logic_vector(0 to 6);
-- ***** Leds
red_leds : out std_logic_vector(9 downto 0);
green_leds : out std_logic_vector(7 downto 0);
-- ***** SD Card
sd_data : in std_logic;
sd_cs : out std_logic;
sd_cmd : out std_logic;
sd_clk : out std_logic
);
end DE1_TOP;
architecture minimal of DE1_TOP is
--##############################################################################
-- MCU and immediate glue logic.
-- light8080 MCU signals -------------------------------------------------------
signal p1in : std_logic_vector(7 downto 0);
signal p2out : std_logic_vector(7 downto 0);
signal uart_txd : std_logic;
signal uart_rxd : std_logic;
signal extint : std_logic_vector(3 downto 0);
-- Signals for external SRAM synchronization -----------------------------------
signal sram_data_out : std_logic_vector(7 downto 0); -- sram output reg
signal sram_write : std_logic; -- sram we register
signal address_reg : std_logic_vector(15 downto 0); -- registered addr bus
--##############################################################################
-- On-board device interface signals.
-- Quad 7-segment display (non multiplexed) & LEDS -----------------------------
signal display_data : std_logic_vector(15 downto 0);
-- Clock & reset signals -------------------------------------------------------
signal clk_1hz : std_logic;
signal clk_master : std_logic;
signal reset : std_logic;
signal clk : std_logic;
signal counter_1hz : unsigned(25 downto 0);
-- SD control signals ----------------------------------------------------------
-- SD connector unused, unconnected
--## Functions #################################################################
-- Converts hex nibble to 7-segment (sinthesizable).
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
function nibble_to_7seg(nibble : std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case nibble is
when X"0" => return "0000001";
when X"1" => return "1001111";
when X"2" => return "0010010";
when X"3" => return "0000110";
when X"4" => return "1001100";
when X"5" => return "0100100";
when X"6" => return "0100000";
when X"7" => return "0001111";
when X"8" => return "0000000";
when X"9" => return "0000100";
when X"a" => return "0001000";
when X"b" => return "1100000";
when X"c" => return "0110001";
when X"d" => return "1000010";
when X"e" => return "0110000";
when X"f" => return "0111000";
when others => return "0111111"; -- can't happen
end case;
end function nibble_to_7seg;
begin
-- MCU instantiation.
mcu: entity work.mcu80
generic map (
OBJ_CODE => work.obj_code_pkg.object_code,
UART_HARDWIRED => false, -- UART baud rate NOT run-time programmable.
UART_IRQ_LINE => 3, -- UART uses IRQ3 line of irq controller.
BAUD_RATE => 115200, -- UART baud rate.
CLOCK_FREQ => 125E6 -- Clock frequency in Hz.
)
port map (
clk => clk,
reset => reset,
p1_i => p1in,
p2_o => p2out,
extint_i => extint,
txd_o => uart_txd,
rxd_i => uart_rxd
);
-- Input port connected to switches for lack of better use
p1in <= switches(7 downto 0);
--##### Input ports ###########################################################
--##############################################################################
-- terasIC Cyclone II STARTER KIT BOARD
--##############################################################################
--##############################################################################
-- FLASH (flash is unused in this demo)
--##############################################################################
flash_addr <= (others => '0');
flash_we_n <= '1'; -- all enable signals inactive
flash_oe_n <= '1';
flash_reset_n <= '1';
--##############################################################################
-- SRAM (wired as 64K x 8)
-- The SRAM is unused in this demo.
--##############################################################################
-- These registera make the external, asynchronous SRAM behave like an
-- internal syncronous BRAM, except for the timing.
-- Since the SoC has no wait state capability, the SoC clock rate must
-- accomodate the SRAM timing -- including FPGA clock-to-output, RAM delays
-- and FPGA input setup and hold times. Setting up the synthesis constraints
-- is left to the user too.
sram_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
sram_addr <= "000000000000000000";
address_reg <= "0000000000000000";
sram_data_out <= X"00";
sram_write <= '0';
else
end if;
end if;
end process sram_registers;
sram_data(15 downto 8) <= "ZZZZZZZZ"; -- high byte unused
sram_data(7 downto 0) <= "ZZZZZZZZ" when sram_write='0' else sram_data_out;
-- (the X"ZZ" will physically be the read input data)
-- sram access controlled by WE_N
sram_oe_n <= '0';
sram_ce_n <= '0';
sram_we_n <= not sram_write;
sram_ub_n <= '1'; -- always disable
sram_lb_n <= '0';
--##############################################################################
-- RESET, CLOCK
--##############################################################################
-- Use button 0 as reset
reset <= not buttons(0);
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
process(clk_50MHz)
begin
if clk_50MHz'event and clk_50MHz='1' then
if reset = '1' then
clk_1hz <= '0';
counter_1hz <= (others => '0');
else
if to_integer(counter_1hz) = 50000000 then
counter_1hz <= (others => '0');
clk_1hz <= not clk_1hz;
else
counter_1hz <= counter_1hz + 1;
end if;
end if;
end if;
end process;
-- Master clock is external 50MHz oscillator
clk <= clk_50MHz;
--##############################################################################
-- LEDS, SWITCHES
--##############################################################################
-- Display the contents of an output port at the green leds bar
green_leds <= p2out;
-- Red leds unused except for 1-Hz clock
red_leds(9 downto 1) <= (others => '0');
red_leds(0) <= clk_1hz;
--##############################################################################
-- QUAD 7-SEGMENT DISPLAYS
--##############################################################################
-- Display the contents of the output port at the hex displays.
--display_data <= X"42" & switches(7 downto 0); --p2out & p1in;
display_data <= p2out & p1in;
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
hex3 <= nibble_to_7seg(display_data(15 downto 12));
hex2 <= nibble_to_7seg(display_data(11 downto 8));
hex1 <= nibble_to_7seg(display_data( 7 downto 4));
hex0 <= nibble_to_7seg(display_data( 3 downto 0));
--##############################################################################
-- SD card interface
--##############################################################################
-- SD card unused in this demo
sd_cs <= '0';
sd_cmd <= '0';
sd_clk <= '0';
--sd_in <= '0';
--##############################################################################
-- SERIAL
--##############################################################################
-- Txd & rxd connected straight to the SoC
txd <= uart_txd;
uart_rxd <= rxd;
end minimal;
|
lgpl-2.1
|
jaruiz/light8080
|
boards/zybo/zybo_top.vhdl
|
1
|
2197
|
--
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Package that contains the program object code in VHDL constant format.
use work.obj_code_pkg.all;
entity ZYBO_TOP is
port(
-- Clock from Ethernet PHY. @note1.
clk_125MHz_i : in std_logic;
-- Pushbuttons.
buttons_i : in std_logic_vector(3 downto 0);
-- Switches.
switches_i : in std_logic_vector(3 downto 0);
-- LEDs.
leds_o : out std_logic_vector(3 downto 0);
-- PMOD E (Std) connector -- PMOD UART (Digilent).
pmod_e_2_txd_o : out std_logic;
pmod_e_3_rxd_i : in std_logic
);
end entity ZYBO_TOP;
architecture rtl of ZYBO_TOP is
signal clk : std_logic;
signal reset : std_logic;
signal extint : std_logic_vector(3 downto 0);
signal iop1 : std_logic_vector(7 downto 0);
signal iop2 : std_logic_vector(7 downto 0);
begin
clk <= clk_125MHz_i;
reset <= buttons_i(3);
-- Light8080 MCU and glue logic ----------------------------------------------
mcu: entity work.mcu80
generic map (
OBJ_CODE => work.obj_code_pkg.object_code,
UART_HARDWIRED => false, -- UART baud rate NOT run-time programmable.
UART_IRQ_LINE => 3, -- UART uses IRQ3 line of irq controller.
BAUD_RATE => 115200, -- UART baud rate.
CLOCK_FREQ => 125E6 -- Clock frequency in Hz.
)
port map (
clk => clk,
reset => reset,
p1_i => iop1,
p2_o => iop2,
extint_i => extint,
txd_o => pmod_e_2_txd_o,
rxd_i => pmod_e_3_rxd_i
);
extint <= iop2(7 downto 4);
iop1(3 downto 0) <= switches_i;
iop1(7 downto 4) <= buttons_i;
-- Smoke test logic (to be removed when up and running) ----------------------
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
leds_o <= "1010";
else
leds_o <= iop2(3 downto 0);
end if;
end if;
end process;
end;
-- @note1: Clock active if PHYRSTB is high. PHYRSTB pin unused, pulled high.
|
lgpl-2.1
|
yishinli/emc2
|
src/hal/drivers/mesa-hostmot2/firmware/src/d8o8.vhd
|
1
|
16530
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Small 8 bit Harvard Arch accumulator oriented processor ~150 slices:
-- 1 clk/inst, >120 MHz operation in Spartan3 >60 MHz in Spartan2
-- 8 bit data, 16 bit instruction width
-- 6 JMP instructions:
-- JMP, JMPNZ, JMPZ, JMPNC, JMPC, JSR
-- 9 basic memory reference instructions:
-- OR, XOR, AND, ADD, ADDC, SUB, SUBB, LDA, STA
-- 13 operate instructions, load immediate, rotate, index load/store:
-- LDI, RCL, RCR, LDYL, LDXL, STYL, STXL, LDYH, LDXH, STYL, STXH, RTT, TTR
-- 1K or 2K words instruction space
-- 4K words data space
-- 2 index registers for indirect memory access
-- 8 bit offset for indirect addressing (ADD sinetable(6) etc)
-- 11 bit direct memory addressing range
-- 12 bit indirect addressing range with 8 bit offset range
-- 2 levels of subroutine call/return
-- Starts at address 0 from reset
-- THE BAD NEWS: pipelined processor with no locks so --->
-- Instruction hazards:
-- 2 instructions following conditional jumps always executed
-- TTR must precede JSR by at least 2 instructions
-- RTT must precede JSR by at least 2 instructions
-- TTR must precede JMP@R by at least 2 instructions
-- Data hazards:
-- Stored data requires 3 instructions before fetch
-- Address hazards:
-- Fetches via index register require 2 instructions from ST(X,Y) or ADDI(X,Y)
-- to actual fetch (STA via index takes no extra delay)
-------------------------------------------------------------------------------
entity DumbAss8 is
generic(
width : integer := 8; -- data width
iwidth : integer := 16; -- instruction width
maddwidth : integer := 12; -- memory address width
paddwidth : integer := 10 -- program counter width
);
port (
clk : in std_logic;
reset : in std_logic;
iabus : out std_logic_vector(paddwidth-1 downto 0); -- program address bus
idbus : in std_logic_vector(iwidth-1 downto 0); -- program data bus
mradd : out std_logic_vector(maddwidth-1 downto 0); -- memory read address
mwadd : out std_logic_vector(maddwidth-1 downto 0); -- memory write address
mibus : in std_logic_vector(width-1 downto 0); -- memory data in bus
mobus : out std_logic_vector(width-1 downto 0); -- memory data out bus
mwrite: out std_logic; -- memory write signal
mread: out std_logic; -- memory read signal
carryflg : out std_logic -- carry flag
);
end DumbAss8;
architecture Behavioral of DumbAss8 is
constant carrymask : std_logic_vector := b"0_1111_1111"; -- mask to drop carry bit
constant ProcVersion : std_logic_vector (width downto 0) := conv_std_logic_vector(12,width);
-- basic op codes
-- Beware, certain bits are used to simpilfy decoding - dont change without knowing what you are doing...
constant opr : std_logic_vector (3 downto 0) := x"0";
constant jmp : std_logic_vector (3 downto 0) := x"1";
constant jmpnz : std_logic_vector (3 downto 0) := x"2";
constant jmpz : std_logic_vector (3 downto 0) := x"3";
constant jmpnc : std_logic_vector (3 downto 0) := x"4";
constant jmpc : std_logic_vector (3 downto 0) := x"5";
constant jsr : std_logic_vector (3 downto 0) := x"6";
constant lda : std_logic_vector (3 downto 0) := x"7";
constant lor : std_logic_vector (3 downto 0) := x"8";
constant lxor : std_logic_vector (3 downto 0) := x"9";
constant land : std_logic_vector (3 downto 0) := x"A";
constant sta : std_logic_vector (3 downto 0) := x"B";
constant add : std_logic_vector (3 downto 0) := x"C";
constant addc : std_logic_vector (3 downto 0) := x"D";
constant sub : std_logic_vector (3 downto 0) := x"E";
constant subc : std_logic_vector (3 downto 0) := x"F";
-- operate instructions
constant nop : std_logic_vector (3 downto 0) := x"0";
-- immediate load type
constant ldi : std_logic_vector (3 downto 0) := x"1";
-- accumulator operate type
constant rotcl : std_logic_vector (3 downto 0) := x"2";
constant rotcr : std_logic_vector (3 downto 0) := x"3";
-- index register load/store in address order
constant ldxl : std_logic_vector (3 downto 0) := x"4";
constant ldyl : std_logic_vector (3 downto 0) := x"5";
constant ldxh : std_logic_vector (3 downto 0) := x"6";
constant ldyh : std_logic_vector (3 downto 0) := x"7";
constant stxl : std_logic_vector (3 downto 0) := x"8";
constant styl : std_logic_vector (3 downto 0) := x"9";
constant stxh : std_logic_vector (3 downto 0) := x"A";
constant styh : std_logic_vector (3 downto 0) := x"B";
constant addix : std_logic_vector (3 downto 0) := x"C";
constant addiy : std_logic_vector (3 downto 0) := x"D";
-- return register save/restore
constant rtt : std_logic_vector (3 downto 0) := x"E";
constant ttr : std_logic_vector (3 downto 0) := x"F";
-- basic signals
signal accumcar : std_logic_vector (width downto 0) := ProcVersion; -- accumulator+carry
alias accum : std_logic_vector (width-1 downto 0) is accumcar(width-1 downto 0);
alias carrybit : std_logic is accumcar(width);
signal maskedcarry : std_logic;
signal pc : std_logic_vector (paddwidth -1 downto 0); -- program counter - 10 bits = 1k
signal mra : std_logic_vector (maddwidth -1 downto 0); -- memory read address - 11 bits = 2k
signal mwa : std_logic_vector (maddwidth -1 downto 0); -- memory write address - 11 bits = 2k
signal id1 : std_logic_vector (iwidth -1 downto 0); -- instruction pipeline 1
signal id2 : std_logic_vector (iwidth -1 downto 0); -- instruction pipeline 2
alias opcode0 : std_logic_vector (3 downto 0) is idbus (iwidth-1 downto iwidth-4); -- main opcode at pipe0
alias opcode2 : std_logic_vector (3 downto 0) is id2 (iwidth-1 downto iwidth-4); -- main opcode at pipe2
alias Arith : std_logic_vector (1 downto 0) is id2 (iwidth-1 downto iwidth-2);
alias WithCarry : std_logic is id2(iwidth-4); -- indicates add with carry or subtract with borrow
alias Minus is id2(iwidth-3); -- indicates subtract
alias opradd0 : std_logic_vector (maddwidth -1 downto 0) is idbus (maddwidth -1 downto 0); -- operand address at pipe0
alias opradd2 : std_logic_vector (maddwidth -1 downto 0) is id2 (maddwidth -1 downto 0); -- operand address at pipe2
alias ind0 : std_logic is idbus(iwidth -5);
alias ind2 : std_logic is id2(iwidth -5);
alias ireg0 : std_logic is idbus(iwidth -8);
alias ireg2 : std_logic is id2(iwidth -8);
alias offset0 : std_logic_vector (iwidth-9 downto 0) is idbus(iwidth-9 downto 0);
alias offset2 : std_logic_vector (iwidth-9 downto 0) is id2(iwidth-9 downto 0);
alias opropcode0 : std_logic_vector (3 downto 0) is idbus(iwidth-5 downto iwidth-8); -- operate opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
alias opropcode2 : std_logic_vector (3 downto 0) is id2(iwidth-5 downto iwidth-8); -- operate opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
signal oprr : std_logic_vector (width -1 downto 0); -- operand register
signal idx : std_logic_vector (maddwidth -1 downto 0);
signal idy : std_logic_vector (maddwidth -1 downto 0);
signal idn0 : std_logic_vector (maddwidth -1 downto 0);
signal idn2 : std_logic_vector (maddwidth -1 downto 0);
signal maddpipe1 : std_logic_vector (maddwidth -1 downto 0);
signal maddpipe2 : std_logic_vector (maddwidth -1 downto 0);
signal maddpipe3 : std_logic_vector (maddwidth -1 downto 0);
signal idr : std_logic_vector (paddwidth -1 downto 0);
signal idt : std_logic_vector (paddwidth -1 downto 0);
signal nextpc : std_logic_vector (paddwidth -1 downto 0);
signal pcplus1 : std_logic_vector (paddwidth -1 downto 0);
signal zero : std_logic;
function rotcleft(v : std_logic_vector ) return std_logic_vector is
variable result : std_logic_vector(width downto 0);
begin
result(width downto 1) := v(width-1 downto 0);
result(0) := v(width);
return result;
end rotcleft;
function rotcright(v : std_logic_vector ) return std_logic_vector is
variable result : std_logic_vector(width downto 0);
begin
result(width -1 downto 0) := v(width downto 1);
result(width) := v(0);
return result;
end rotcright;
begin -- the CPU
idproc : process (clk) -- instruction data pipeline
begin
if clk'event and clk = '1' then
id1 <= idbus;
id2 <= id1;
if reset = '1' then
id1 <= x"0000"; -- fill pipeline with 0 (nop)
end if;
end if; -- if clk
end process idproc;
nextpcproc : process (clk, reset, pc, zero, nextpc, id2,
ind0, ind2,idr, idbus, opcode0,
opcode2, carrybit) -- next pc calculation - jump decode
begin
pcplus1 <= pc + '1';
iabus <= nextpc; -- program memory address from combinatorial
if reset = '1' then -- nextpc since blockram has built in addr register
nextpc <= (others => '0');
else
if (opcode0 = jmp) or (opcode0 = jsr) then
if ind0 = '1' then -- indirect
nextpc <= idr;
else -- direct
nextpc <= idbus(paddwidth -1 downto 0);
end if;
elsif
((opcode2 = jmpnz) and (zero = '0')) or
((opcode2 = jmpz) and (zero = '1')) or
((opcode2 = jmpnc) and (carrybit = '0')) or
((opcode2 = jmpc) and (carrybit = '1')) then
if ind2 = '1' then -- indirect
nextpc <= idr;
else -- direct
nextpc <= id2(paddwidth -1 downto 0);
end if;
else
nextpc <= pcplus1;
end if; -- opcode = jmp
end if; -- no reset
if clk'event and clk = '1' then
pc <= nextpc;
end if;
end process nextpcproc;
mraproc : process (idbus, idx, idy, mra, ind0,
ireg0,
offset0, opcode0, opradd0, clk) -- memory read address generation
begin
mradd <= mra;
case ireg0 is
when '0' => idn0 <= idx;
when '1' => idn0 <= idy;
when others => null;
end case;
-- mux
if ((opcode0 /= opr) and (ind0 = '0')) then
mra <= opradd0;
else
mra <= idn0 + (x"0"&offset0);
end if;
if clk'event and clk = '1' then
maddpipe3 <= maddpipe2;
maddpipe2 <= maddpipe1;
maddpipe1 <= mra;
if (opcode0 = lda) or (opcode0 = lor) or (opcode0 = lxor) or (opcode0 = land)
or (opcode0 = add) or (opcode0 = addc) or (opcode0 = sub) or (opcode0 = subc) then
mread <= '1';
else
mread <= '0';
end if;
end if;
end process mraproc;
mwaproc : process (maddpipe3) -- memory write address generation
begin
mwadd <= maddpipe3;
end process mwaproc;
oprrproc : process (clk) -- memory operand register -- could remove to
begin -- reduce pipelining depth but would impact I/O read
if clk'event and clk = '1' then -- access time --> not good for larger systems
oprr <= mibus;
end if;
end process oprrproc;
accumproc : process (clk, accum, carrybit) -- accumulator instruction decode - operate
begin
carryflg <= carrybit;
if accum = x"00" then
zero <= '1';
else
zero <= '0';
end if;
maskedcarry <= carrybit and WithCarry;
if clk'event and clk = '1' then
case opcode2 is -- memory reference first
when land => accum <= accum and oprr;
when lor => accum <= accum or oprr;
when lxor => accum <= accum xor oprr;
when lda => accum <= oprr;
when opr => -- operate
case opropcode2 is
when ldi => accum <= iopr2; -- load immediate byte
when rotcl => accumcar <= rotcleft(accumcar); -- rotate left through carry
when rotcr => accumcar <= rotcright(accumcar); -- rotate right through carry
when ldxl => accum <= idx(width-1 downto 0);
when ldyl => accum <= idy(width-1 downto 0);
when stxl => idx(width-1 downto 0) <= accum;
when styl => idy(width-1 downto 0) <= accum;
when ldxh => accum((maddwidth-width)-1 downto 0) <= idx(maddwidth-1 downto width);
accum(width-1 downto maddwidth-width) <= (others => '0');
when ldyh => accum((maddwidth-width)-1 downto 0) <= idy(maddwidth-1 downto width);
accum(width-1 downto maddwidth-width) <= (others => '0');
when stxh => idx(maddwidth-1 downto width) <= accum((maddwidth-width)-1 downto 0);
when styh => idy(maddwidth-1 downto width) <= accum((maddwidth-width)-1 downto 0);
when rtt => idt <= idr;
when ttr => idr <= idt;
when addix => idx <= maddpipe2;
when addiy => idy <= maddpipe2;
when others => null;
end case;
when others => null;
end case;
if Arith = "11" then
if Minus = '0' then
accumcar <= '0'&accum + oprr + maskedcarry; -- add/addc
else
accumcar <= '0'&accum - oprr - maskedcarry; -- sub/subc
end if;
end if;
if (opcode0 = jsr) then -- save return address -- note priority over ttr!
idr <= pcplus1;
end if;
-- if opcode0 = opr then -- this can be done at pipe 0 at the cost of 6 or so slices
-- if opropcode0 = addix then
-- idx <= mra;
-- end if;
-- if opropcode0 = addiy then
-- idy <= mra;
-- end if;
-- end if;
end if; -- clk
end process accumproc;
staproc : process (clk, accum) -- sta decode -- not much to do but enable mwrite
begin
mobus <= accum;
if clk'event and clk = '1' then
if opcode2 = sta then
mwrite <= '1';
else
mwrite <= '0';
end if;
end if;
end process staproc;
end Behavioral;
|
lgpl-2.1
|
pwsoft/fpga_examples
|
quartus/chameleon/chameleon1_gigatron/pll8.vhd
|
1
|
19669
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll8.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll8 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll8;
ARCHITECTURE SYN OF pll8 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 25,
clk1_phase_shift => "5000",
clk2_divide_by => 4,
clk2_duty_cycle => 50,
clk2_multiply_by => 75,
clk2_phase_shift => "0",
clk3_divide_by => 4,
clk3_duty_cycle => 50,
clk3_multiply_by => 75,
clk3_phase_shift => "3333",
compensate_clock => "CLK0",
inclk0_input_frequency => 125000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll8",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "8.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll8.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "3333"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "125000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
lgpl-2.1
|
yishinli/emc2
|
src/hal/drivers/mesa-hostmot2/firmware/src/simplespix.vhd
|
1
|
6387
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity simplespi is
generic (
buswidth : integer
);
port (
clk : in std_logic;
ibus : in std_logic_vector(buswidth-1 downto 0);
obus : out std_logic_vector(buswidth-1 downto 0);
loadbitcount : in std_logic;
loadbitrate : in std_logic;
loaddata : in std_logic;
readdata : in std_logic;
readbitcount : in std_logic;
readbitrate : in std_logic;
spiclk : out std_logic;
spiin : in std_logic;
spiout: out std_logic;
spiframe: out std_logic;
davout: out std_logic
);
end simplespi;
architecture behavioral of simplespi is
constant DivWidth: integer := 8;
-- ssi interface related signals
signal RateDivReg : std_logic_vector(DivWidth -1 downto 0);
signal RateDiv : std_logic_vector(DivWidth -1 downto 0);
signal ModeReg : std_logic_vector(8 downto 0);
alias BitcountReg : std_logic_vector(5 downto 0) is ModeReg(5 downto 0);
alias CPOL : std_logic is ModeReg(6);
alias CPHA : std_logic is ModeReg(7);
alias DontClearFrame : std_logic is ModeReg(8);
signal BitCount : std_logic_vector(5 downto 0);
signal ClockFF: std_logic;
signal SPISreg: std_logic_vector(buswidth-1 downto 0);
signal Frame: std_logic;
signal EFrame: std_logic;
signal Dav: std_logic;
signal SPIInLatch: std_logic;
signal FirstLeadingEdge: std_logic;
begin
aspiinterface: process (clk, readdata, ModeReg, ClockFF, Frame,
SPISreg, readbitcount, BitcountReg,
Dav, readbitrate, RateDivReg)
begin
if rising_edge(clk) then
if loaddata = '1' then
SPISreg <= ibus;
BitCount <= BitCountReg;
Frame <= '1';
EFrame <= '1';
Dav <= '0';
ClockFF <= '0';
FirstLeadingEdge <= '1';
RateDiv <= RateDivReg;
end if;
if Frame = '1' then
if RateDiv = 0 then
RateDiv <= RateDivReg;
SPIInLatch <= spiin;
if ClockFF = '0' then
if BitCount(5) = '1' then
Frame <= '0'; -- frame cleared 1/2 SPI clock after GO
if DontClearFrame = '0' then
EFrame <= '0';
end if;
Dav <= '1';
else
ClockFF <= '1';
end if;
if CPHA = '1' and FirstLeadingEdge = '0' then -- shift out on leading edge for CPHA = 1 case
SPISreg <= SPISreg(30 downto 0) & (SPIInLatch);
end if;
FirstLeadingEdge <= '0';
else
ClockFF <= '0';
BitCount <= BitCount -1;
if CPHA = '0' then -- shift out on trailing edge for CPHA = 0 case
SPISreg <= SPISreg(30 downto 0) & (SPIInLatch);
end if;
end if;
else
RateDiv <= RateDiv -1;
end if;
end if;
if loadbitcount = '1' then
ModeReg <= ibus(8 downto 0);
end if;
if loadbitrate = '1' then
RateDivReg <= ibus(DivWidth -1 downto 0);
end if;
end if; -- clk
obus <= (others => 'Z');
if readdata = '1' then
obus <= SPISReg;
end if;
if readbitcount = '1' then
obus(8 downto 0) <= ModeReg;
obus(buswidth -1) <= Dav;
end if;
if readbitrate = '1' then
obus(DivWidth-1 downto 0) <= RateDivReg;
end if;
spiclk <= ClockFF xor CPOL;
spiframe <= not EFrame;
davout <= Dav;
-- for i in 0 to buswidth -1 loop
-- if i = BitCountReg then
-- spiout <= SPISReg(i);
-- end if;
-- end loop;
spiout <= SPISReg(conv_integer(BitCountReg(4 downto 0))); -- select the MSB of the current size
end process aspiinterface;
end Behavioral;
|
lgpl-2.1
|
yishinli/emc2
|
src/hal/drivers/m5i20/hostmot5_src/countere.vhd
|
1
|
8938
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end counter;
architecture behavioral of counter is
signal count: STD_LOGIC_VECTOR (31 downto 0);
signal up: STD_LOGIC;
signal down: STD_LOGIC;
signal countoutlatch: STD_LOGIC_VECTOR (31 downto 0);
signal outlatchdel1: STD_LOGIC;
signal outlatchdel2: STD_LOGIC;
signal quada1: STD_LOGIC;
signal quada2: STD_LOGIC;
signal quadacnt: STD_LOGIC_VECTOR (3 downto 0);
signal quadafilt: STD_LOGIC;
signal quadb1: STD_LOGIC;
signal quadb2: STD_LOGIC;
signal quadbcnt: STD_LOGIC_VECTOR (3 downto 0);
signal quadbfilt: STD_LOGIC;
signal index1: STD_LOGIC;
signal index2: STD_LOGIC;
signal indexcnt: STD_LOGIC_VECTOR (3 downto 0);
signal indexfilt: STD_LOGIC;
signal qcountup: STD_LOGIC;
signal qcountdown: STD_LOGIC;
signal udcountup: STD_LOGIC;
signal udcountdown: STD_LOGIC;
signal autocount: STD_LOGIC;
signal doclear: STD_LOGIC;
signal clearonindex: STD_LOGIC; -- ccr register bits...
signal clearonce: STD_LOGIC;
signal indexgate: STD_LOGIC;
signal indexsrc: STD_LOGIC;
signal latchonread: STD_LOGIC;
signal quadfilter: STD_LOGIC;
signal countermode: STD_LOGIC;
signal indexpol: STD_LOGIC;
signal ccrloadcmd1: STD_LOGIC;
signal ccrloadcmd2: STD_LOGIC;
signal localhold: STD_LOGIC;
signal localclear: STD_LOGIC;
signal indexmaskenable: STD_LOGIC;
signal indexmaskpol: STD_LOGIC;
signal fixedindexmask: STD_LOGIC;
signal latchonce: STD_LOGIC;
signal latchonindex: STD_LOGIC;
signal flimit: STD_LOGIC_VECTOR (3 downto 0);
begin
acounter: process (clk, countoutlatch)
begin
if clk'event and clk = '1' then
outlatchdel1 <= countlatchcmd;
outlatchdel2 <= outlatchdel1;
if indexgate = '0' then
indexsrc <= index;
else
if indexpol = '1' then
indexsrc <= not quada and not quadb and index;
else
indexsrc <= (quada or quadb) and index;
end if;
end if;
if indexmaskpol = '1' then
fixedindexmask <= indexmask;
else
fixedindexmask <= not indexmask;
end if;
if quadfilter = '1' then
flimit <= "1111";
else
flimit <= "0011";
end if;
quada1 <= quadafilt;
quada2 <= quada1;
quadb1 <= quadbfilt;
quadb2 <= quadb1;
index1 <= indexfilt;
index2 <= index1;
-- deadended counter for A input filter --
if (quada = '1') and (quadacnt < flimit) then
quadacnt <= quadacnt + 1;
end if;
if (quada = '0') and (quadacnt /= 0) then
quadacnt <= quadacnt -1;
end if;
if quadacnt >= flimit then
quadafilt<= '1';
end if;
if quadacnt = 0 then
quadafilt<= '0';
end if;
-- deadended counter for B input filter --
if (quadb = '1') and (quadbcnt < flimit ) then
quadbcnt <= quadbcnt + 1;
end if;
if (quadb = '0') and (quadbcnt /= 0) then
quadbcnt <= quadbcnt -1;
end if;
if quadbcnt >= flimit then
quadbfilt<= '1';
end if;
if quadbcnt = 0 then
quadbfilt <= '0';
end if;
-- deadended counter for index input filter --
if (indexsrc = '1') and (indexcnt < flimit ) then
indexcnt <= indexcnt + 1;
end if;
if (indexsrc = '0') and (indexcnt /= 0) then
indexcnt <= indexcnt -1;
end if;
if indexcnt >= flimit then
indexfilt<= '1';
end if;
if indexcnt = 0 then
indexfilt<= '0';
end if;
if (countclearcmd = '1') or (localclear = '1') or
((clearonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '0')) or -- rising edge of index
((clearonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '0')) or -- falling edge of index
((clearonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '1') and (fixedindexmask = '1')) or -- rising edge of index when masked
((clearonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '1') and (fixedindexmask = '1')) then -- falling edge of index when masked
doclear <= '1';
if clearonce = '1' then
clearonindex <= '0';
end if;
else
doclear <= '0';
end if;
if ((latchonread = '1') and (nads = '0')) or -- (let the synthesizer factor this out...)
((outlatchdel2 = '0') and (outlatchdel1 = '1') and (latchonindex = '0')) or
((latchonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '0')) or -- rising edge of index
((latchonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '0')) or -- falling edge of index
((latchonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '1') and (fixedindexmask = '1')) or -- rising edge of index when masked
((latchonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '1') and (fixedindexmask = '1')) then -- falling edge of index when masked
countoutlatch <= count;
if latchonce = '1' then
latchonindex <= '0';
end if;
end if;
if countermode = '0' and countenable = '1' and localhold ='0' and doclear = '0' and (
(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '0' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '1')) then
qcountup <= '1';
else
qcountup <= '0';
end if;
if (countermode = '1' and countenable = '1' and localhold ='0' and doclear = '0' and
quadb2 = '1' and quada2 = '0' and quada1 = '1') then
udcountup <= '1';
else
udcountup <= '0';
end if;
if countermode = '0' and countenable = '1' and localhold ='0' and doclear = '0' and (
(quada2 = '0' and quada1 = '0' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '1' and quadb1 = '0')) then
qcountdown <= '1';
else
qcountdown <= '0';
end if;
if (countermode = '1' and countenable = '1' and localhold ='0' and doclear = '0' and
quadb2 = '0' and quada2 = '0' and quada1 = '1') then
udcountdown <= '1';
else
udcountdown <= '0';
end if;
if up /= down then
if up = '1' then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
if doclear = '1' then
count <= x"00000000";
end if;
if ccrloadcmd = '1' then -- load ccr
indexmaskpol <= ibus(15);
indexmaskenable <= ibus(14);
latchonce <= ibus(13);
latchonindex <= ibus(12);
autocount <= ibus(11);
countermode <= ibus(10);
quadfilter <= ibus(9);
localhold <= ibus(8);
indexgate <= ibus(7);
clearonce <= ibus(6);
clearonindex <= ibus(5);
indexpol <= ibus(4);
latchonread <= ibus(3);
localclear <= ibus(2);
end if;
if localclear = '1' then -- once were done clearing,, dont stick around
localclear <= '0';
end if;
end if; --(clock edge)
if (qcountup = '1' or udcountup = '1' or Autocount = '1') and localhold= '0' and doclear = '0' then
up <= '1';
else
up <= '0';
end if;
if (qcountdown = '1' or udcountdown = '1' ) and Autocount = '0' and localhold ='0' and doclear = '0' then
down <= '1';
else
down <= '0';
end if;
obus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if (countoutreadcmd = '1') and (ccrreadcmd = '0') then
obus <= countoutlatch;
end if;
if (ccrreadcmd = '1') and (countoutreadcmd = '0') then
obus(15) <= indexmaskpol;
obus(14) <= indexmask;
obus(13) <= latchonce;
obus(12) <= latchonindex;
obus(11) <= autocount;
obus(10) <= countermode;
obus(9) <= quadfilter;
obus(8) <= localhold;
obus(7) <= indexgate;
obus(6) <= clearonce;
obus(5) <= clearonindex;
obus(4) <= indexpol;
obus(3) <= latchonread;
obus(2) <= index1;
obus(1) <= quadb1;
obus(0) <= quada1;
end if;
end process;
end behavioral;
|
lgpl-2.1
|
yishinli/emc2
|
src/hal/drivers/mesa-hostmot2/firmware/src/usbram.vhd
|
1
|
18614
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Created from usbram.obj
-- On 6/ 5/2008
entity usbram is
port (
addra: in std_logic_vector(10 downto 0);
addrb: in std_logic_vector(10 downto 0);
clk: in std_logic;
dina: in std_logic_vector(7 downto 0);
douta: out std_logic_vector(7 downto 0);
doutb: out std_logic_vector(7 downto 0);
wea: in std_logic);
end usbram;
architecture syn of usbram is
type ram_type is array (0 to 2047) of std_logic_vector(7 downto 0);
signal RAM : ram_type :=
(
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
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x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00");
signal daddra: std_logic_vector(10 downto 0);
signal daddrb: std_logic_vector(10 downto 0);
begin
ausbram: process (clk)
begin
if (clk'event and clk = '1') then
if (wea = '1') then
RAM(conv_integer(addra)) <= dina;
end if;
daddra <= addra;
daddrb <= addrb;
end if; -- clk
end process;
douta <= RAM(conv_integer(daddra));
doutb <= RAM(conv_integer(daddrb));
end;
|
lgpl-2.1
|
pwsoft/fpga_examples
|
rtl/ttl/ttl_74573.vhd
|
1
|
4117
|
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Octal D-type transparent latch; 3-state
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74573 is
generic (
latency : integer := 2
);
port (
emuclk : in std_logic;
p1 : in ttl_t; -- OEn
p2 : in ttl_t; -- D0
p3 : in ttl_t; -- D1
p4 : in ttl_t; -- D2
p5 : in ttl_t; -- D3
p6 : in ttl_t; -- D4
p7 : in ttl_t; -- D5
p8 : in ttl_t; -- D6
p9 : in ttl_t; -- D7
p11 : in ttl_t; -- LE
p12 : out ttl_t; -- Q7
p13 : out ttl_t; -- Q6
p14 : out ttl_t; -- Q5
p15 : out ttl_t; -- Q4
p16 : out ttl_t; -- Q3
p17 : out ttl_t; -- Q2
p18 : out ttl_t; -- Q1
p19 : out ttl_t -- Q0
);
end entity;
architecture rtl of ttl_74573 is
signal p12_loc : ttl_t;
signal p13_loc : ttl_t;
signal p14_loc : ttl_t;
signal p15_loc : ttl_t;
signal p16_loc : ttl_t;
signal p17_loc : ttl_t;
signal p18_loc : ttl_t;
signal p19_loc : ttl_t;
signal latch_reg : unsigned(7 downto 0) := (others => '0');
begin
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p12_loc, q => p12);
p13_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p13_loc, q => p13);
p14_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p14_loc, q => p14);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p15_loc, q => p15);
p16_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p16_loc, q => p16);
p17_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p17_loc, q => p17);
p18_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p18_loc, q => p18);
p19_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p19_loc, q => p19);
p12_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(7));
p13_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(6));
p14_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(5));
p15_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(4));
p16_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(3));
p17_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(2));
p18_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(1));
p19_loc <= FLOAT when is_high(p1) else std2ttl(latch_reg(0));
process(emuclk)
begin
if rising_edge(emuclk) then
if is_high(p11) then
latch_reg(0) <= ttl2std(p2);
latch_reg(1) <= ttl2std(p3);
latch_reg(2) <= ttl2std(p4);
latch_reg(3) <= ttl2std(p5);
latch_reg(4) <= ttl2std(p6);
latch_reg(5) <= ttl2std(p7);
latch_reg(6) <= ttl2std(p8);
latch_reg(7) <= ttl2std(p9);
end if;
end if;
end process;
end architecture;
|
lgpl-2.1
|
estadofinito/biblioteca-vhdl
|
todos-los-archivos/clk4Hz.vhd
|
2
|
1252
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/13 08:21:52
-- Nombre del módulo: clk4Hz - Behavioral
-- Comentarios adicionales:
-- Implementación de forma exacta, a caso con escala par.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk4Hz is
Port (
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC;
clk_out : out STD_LOGIC -- Reloj de salida de 4Hz.
);
end clk4Hz;
architecture Behavioral of clk4Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 6249999 := 0;
begin
divisor_frecuencia: process (clk, reset) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(clk) then
if (contador = 6249999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;
|
lgpl-2.1
|
estadofinito/biblioteca-vhdl
|
otros-proyectos/pjt001-mux-freq/clk1Hz.vhd
|
3
|
1395
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2012/10/26 09:35:12
-- Nombre del módulo: clk1Hz - Behavioral
-- Descripción:
-- Divisor de frecuencia implementado con contadores. Este divisor de frecuencia
-- reduce la escala en un factor de 25000000 veces. En este caso, la frecuencia se
-- reduce de 50MHz de entrada a 1Hz a la salida.
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk1Hz is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk1Hz;
architecture Behavioral of clk1Hz is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 24999999 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 24999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <= temporal;
end Behavioral;
|
lgpl-2.1
|
estadofinito/biblioteca-vhdl
|
todos-los-archivos/bin7seg.vhd
|
2
|
1286
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/16 00:35:30
-- Nombre del módulo: bin7seg - Behavioral
-- Comentarios adicionales:
-- Recibe un valor de 9 bits y lo convierte a BCD para enviarlo como dato a los
-- visualizadores de una tarjeta Basys2.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bin7seg is
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC; -- Señal de reset.
num_bin : in STD_LOGIC_VECTOR(8 downto 0);
d7s : out STD_LOGIC_VECTOR(7 downto 0);
MUX : out STD_LOGIC_VECTOR(3 downto 0)
);
end bin7seg;
architecture Behavioral of bin7seg is
signal num_bcd: STD_LOGIC_VECTOR(10 downto 0);
signal D0, D1, D2, D3: STD_LOGIC_VECTOR(3 downto 0);
begin
d7s_i: entity work.siete_segmentos_4bits_completo(Behavioral)
PORT MAP(clk, reset, D0, D1, D2, D3, d7s, MUX);
bin2bcd9_i: entity bin2bcd9(Behavioral)
PORT MAP(num_bin, num_bcd);
D3 <= "0000";
D2 <= "0" & num_bcd(10 downto 8);
D1 <= num_bcd(7 downto 4);
D0 <= num_bcd(3 downto 0);
end Behavioral;
|
lgpl-2.1
|
freecores/grain
|
src/VHDL/grain_datapath_fast.vhd
|
1
|
3694
|
--
-- Grain datapath, faster but larger implementation
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain_datapath_fast is
generic (
DEBUG : boolean := false -- output debug information
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INJECT_INPUT_I : in std_logic;
PAD_IV_I : in std_logic;
ADD_OUTPUT_I : in std_logic;
H_O : out std_logic
);
end entity;
architecture behav of grain_datapath_fast is
-- On Altera devices, this will make things bigger but also faster
-- by stopping Quartus from using memories instead of shift registers
-- (since Altera lacks SLR16 primitives, puh!)
attribute altera_attribute : string;
attribute altera_attribute of behav : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
signal lfsr, nfsr : unsigned(0 to 79);
signal func_h, func_g, func_f : std_logic;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7 : std_logic;
begin
-- outputs:
H_O <= func_h;
-- register balancing:
--
-- this is just a dumb example I made up, you should instead
-- use your synthesizer which does a much better job!
--
func_h <= tmp1 xor tmp2;
func_g <= tmp3 xor tmp4 xor tmp5 xor tmp6;
func_f <= tmp7;
retime_proc: process(CLK_I)
variable nfsr_e, lfsr_e : unsigned(0 to 79);
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
nfsr_e := nfsr sll 1;
lfsr_e := lfsr sll 1;
-- H (well, Z really)
tmp1 <=
nfsr_e(1) xor nfsr_e(2) xor nfsr_e(4) xor nfsr_e(10) xor nfsr_e(31) xor nfsr_e(43) xor nfsr_e(56) xor
lfsr_e(25) xor nfsr_e(63);
tmp2 <=
(lfsr_e(3) and lfsr_e(64)) xor
(lfsr_e(46) and lfsr_e(64)) xor
(lfsr_e(64) and nfsr_e(63)) xor
(lfsr_e(3) and lfsr_e(25) and lfsr_e(46)) xor
(lfsr_e(3) and lfsr_e(46) and lfsr_e(64)) xor
(lfsr_e(3) and lfsr_e(46) and nfsr_e(63)) xor
(lfsr_e(25) and lfsr_e(46) and nfsr_e(63)) xor
(lfsr_e(46) and lfsr_e(64) and nfsr_e(63));
-- G
tmp3 <=
lfsr_e(0) xor nfsr_e(37) xor
nfsr_e(33) xor nfsr_e(28) xor nfsr_e(21) xor nfsr_e(14) xor nfsr_e(9) xor nfsr_e(0);
tmp4 <=
(nfsr_e(63) and nfsr_e(60)) xor (nfsr_e(37) and nfsr_e(33)) xor
(nfsr_e(15) and nfsr_e(9)) xor
(nfsr_e(60) and nfsr_e(52) and nfsr_e(45));
tmp5<=
(nfsr_e(33) and nfsr_e(28) and nfsr_e(21)) xor
(nfsr_e(63) and nfsr_e(45) and nfsr_e(28) and nfsr_e(9)) xor
(nfsr_e(60) and nfsr_e(52) and nfsr_e(37) and nfsr_e(33)) xor
(nfsr_e(63) and nfsr_e(60) and nfsr_e(21) and nfsr_e(15));
tmp6 <=
nfsr_e(62) xor nfsr_e(60) xor nfsr_e(52) xor nfsr_e(45) xor
(nfsr_e(63) and nfsr_e(60) and nfsr_e(52) and nfsr_e(45) and nfsr_e(37)) xor
(nfsr_e(33) and nfsr_e(28) and nfsr_e(21) and nfsr_e(15) and nfsr_e(9)) xor
(nfsr_e(52) and nfsr_e(45) and nfsr_e(37) and nfsr_e(33) and nfsr_e(28) and nfsr_e(21));
-- F
tmp7 <=
lfsr_e(62) xor lfsr_e(51) xor lfsr_e(38) xor lfsr_e(23) xor lfsr_e(13) xor lfsr_e(0);
end if;
end if;
end process;
-- the shift registers:
sr_proc : process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
lfsr <= lfsr sll 1;
nfsr <= nfsr sll 1;
if INJECT_INPUT_I = '1' then
lfsr(79) <= IV_I or PAD_IV_I;
nfsr(79) <= KEY_I;
else
lfsr(79) <= func_f xor (ADD_OUTPUT_I and func_h);
nfsr(79) <= func_g xor (ADD_OUTPUT_I and func_h);
end if;
end if;
end if;
end process;
end behav;
|
lgpl-3.0
|
a4a881d4/ringbus
|
V3.0/pcie/EPTLPIn.vhd
|
1
|
3907
|
---------------------------------------------------------------------------------------------------
--
-- Title : Bus End Point Recieve to TLP interface
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : EPTLPIn.vhd
-- Generated : 2013/9/15
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Ring Bus End Point Recieve to TLP interface
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.rb_config.all;
entity EPTLPIN is
generic(
Awidth : natural:= 64;
Bwidth : natural:= 128;
PCIwidth : natural:= 64;
BUFAWidth : natural := 4;
BUFSIZE : natural := 2**BUFAWidth
);
port(
-- system interface
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- bus interface
rx_sop : in std_logic;
rx: in std_logic_vector(Bwidth-1 downto 0);
-- TLP interface
clk_pci : in std_logic;
rst_pci : in std_logic;
trn_td : out std_logic_vector( PCIwidth-1 downto 0);
trn_tsrc_rdy_n : out std_logic;
trn_select_n : in std_logic;
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic
--
completer_id_i : in std_logic_vector(15 downto 0)
);
end EPTLPIN;
architecture behave of EPTLPIN is
type state is (
IDLE,
QW0DW1,
QWXDW0,
QWXDW1
);
type TLP is array of ( BUFSIZE*33-1 downto 0 ) of std_logic_vector( Bwidth-1 downto 0 );
--type TLPH is array of ( BUFSIZE-1 downto 0 ) of std_logic_vector( Bwidth-1 downto 0 );
signal wraddr_i, rdaddr_i : std_logic_vector( 4 downto 0 ) := (others => '0');
signal wrid_i, rdid_i : std_logic_vector( BUFAwidth-1 downto 0 ) := (others => '0');
signal tlpstate : state := IDLE;
signal TLP_i : TLP := (others =>(others => '0'));
signal lenc : std_logic_vector( len_length-1 downto 0 ) := (others => '0');
signal errcnt : std_logic_vector( 15 downto 0 ) := (others => '0');
signal hold : std_logic := '0';
begin
sopWRP:process(clk,rst)
begin
if rst='1' then
wraddr_i<=(others => '0');
wrid_i<=(others => '0');
lenc<=(others => '0');
errcnt<=(others => '0');
elsif rising_edge(clk) then
if rx_sop='1'
and rx( command_end downto command_start )=command_write
then
wraddr_i<=zeros(4 downto 0);
TLP_i(conv_integer("100000"&wrid_i))<='0' &
RX_MEM_WR64_FMT_TYPE &
'0' &
Device_TC &
"0000" &
Device_TD &
Device_EP &
Device_ATTR &
"00" &
rx( len_end downto len_start )&"0000" &
completer_id_i &
Device_WR_TAG &
"11111111" &
rx( addr_start+Awidth-1 downto addr_start )
;
lenc<=rx( len_end downto len_start )-1;
hold<='1';
elsif lenc/=zeros( len_length-1 downto 0 ) then
lenc<=lenc-1;
wraddr_i<=addr_i+1;
THP_i(conv_integer(wraddr_i&wrid_i))<=rx;
else
if wrid_i+1 /= rdid_i then
wrid_i<=wrid_i+1;
else
errcnt<=errcnt+1;
end if
end if;
end if;
end process;
sofRRP:process(clk_pci,rst_pci)
begin
if rst_pci='1' then
rdaddr_i<=(others => '0');
rdid_i<=(others => '0');
tlpstate<=IDLE;
elsif rising_edge(clk_pci) then
if trn_select_n='1' then
case tlpstate is
when IDLE =>
if trn_tsof_n='1' then
tlpstate<=QW0DW1;
rdaddr_i<=(others => '0');
end if;
when QW0DW1 =>
end if;
end if;
end process;
end behave;
|
lgpl-3.0
|
a4a881d4/ringbus
|
common/ShiftReg.vhd
|
2
|
1643
|
---------------------------------------------------------------------------------------------------
--
-- Title : Shift Reg
-- Design : Common Module
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : shiftReg.vhd
-- Generated : 2013/9/4
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : shift reg
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--Library synplify;
entity ShiftReg is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector(width-1 downto 0);
Q : out std_logic_vector(width-1 downto 0) := ( others => '0' );
S : out std_logic_vector(width-1 downto 0)
);
end ShiftReg;
architecture behave of ShiftReg is
type ram_memtype is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal mem : ram_memtype := (others => (others => '0'));
-- attribute syn_srlstyle of mem : signal is "no_rw_check";
-- attribute syn_srlstyle of mem : signal is "select_srl";
-- synthesis syn_ramstyle = "no_rw_check";
begin
mem(0) <= D;
process(clk)
begin
if rising_edge(clk) then
if ce = '1' then
mem(depth downto 1) <= mem(depth-1 downto 0);
Q <= mem (depth-1);
end if;
end if;
end process;
S <= mem(depth);
end behave;
|
lgpl-3.0
|
a4a881d4/ringbus
|
simio/ademulator.vhd
|
1
|
1716
|
-- This unit will simulate a DSP
-- It will read form a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity ADemulator is
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : out std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' ));
end ADemulator;
architecture behavior of ADemulator is
signal state: integer:=0;
constant StrLength : integer :=(DATA_WIDTH+1)/4;
begin
process( clk )
variable buf: line ;
variable lineno:integer:=0;
FILE data_file: TEXT IS IN AD_FILE;
variable dataTemp: std_logic_vector(15 downto 0):="0000000000000000";
variable booval: boolean :=false;
variable strData : string(StrLength downto 1);
begin
if(AD_FILE = "UNUSED") then
ASSERT FALSE
REPORT "file not found!"
SEVERITY WARNING;
end if;
if clk'event and clk='1' then
if ce='1' then
if NOT ENDFILE(data_file) then
booval := true;
READLINE(data_file, buf);
lineno:=lineno+1;
READ(L=>buf, VALUE=>strData, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no time domain "
SEVERITY ERROR;
end if;
dataTemp:=CONV_STD_LOGIC_VECTOR(hex_str_to_int(strData),16);
data<=dataTemp(DATA_WIDTH-1 downto 0 );
else
data <= ( others => '0' );
end if;
end if;
end if;
end process;
end behavior;
|
lgpl-3.0
|
a4a881d4/ringbus
|
simio/simio.vhd
|
1
|
6897
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
package SIMIO_PACKAGE is
component dspemulator
generic ( DSP_INC_FILE : string := "UNUSED";
ABUS_WIDTH : integer := 16;
DBUS_WIDTH : integer := 16 );
port (
clk : in std_logic;
dspce : out std_logic;
dspa : out std_logic_vector( ABUS_WIDTH-1 downto 0);
data : out std_logic_vector( DBUS_WIDTH-1 downto 0);
wr : out std_logic;
IOstb : out std_logic);
end component ;
component probe
generic ( PROBE_FILE : string := "UNUSED";
SIGNAL1_WIDTH : NATURAL:=6;
SIGNAL1_MASK : integer:=0;
SIGNAL1_TRG : integer:=0;
SIGNAL2_WIDTH : NATURAL:=6;
SIGNAL2_MASK : integer:=0;
SIGNAL2_TRG : integer:=0;
SIGNAL3_WIDTH : NATURAL:=6;
SIGNAL3_MASK : integer:=0;
SIGNAL3_TRG : integer:=0;
SIGNAL4_WIDTH : NATURAL:=6;
SIGNAL4_MASK : integer:=0;
SIGNAL4_TRG : integer:=0);
port (
clk : in std_logic;
signal1 : in std_logic_vector(SIGNAL1_WIDTH-1 downto 0);
signal2 : in std_logic_vector(SIGNAL2_WIDTH-1 downto 0);
signal3 : in std_logic_vector(SIGNAL3_WIDTH-1 downto 0);
signal4 : in std_logic_vector(SIGNAL4_WIDTH-1 downto 0));
end component;
component ADemulator
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component DAemulator
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component IQADemulator
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iout : out std_logic_vector(DATA_WIDTH-1 downto 0);
Qout : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
component IQDAemulator
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iin : in std_logic_vector(DATA_WIDTH-1 downto 0);
Qin : in std_logic_vector(DATA_WIDTH-1 downto 0));
end component ;
function int_to_str( value : integer ) return string;
function hex_str_to_int( str : string ) return integer;
function hex_to_str( value : integer ) return string;
procedure Shrink_line(L : inout LINE; pos : in integer);
end SIMIO_PACKAGE;
package body SIMIO_PACKAGE is
function int_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0 ) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 => line_no(index) := '0';
when 1 => line_no(index) := '1';
when 2 => line_no(index) := '2';
when 3 => line_no(index) := '3';
when 4 => line_no(index) := '4';
when 5 => line_no(index) := '5';
when 6 => line_no(index) := '6';
when 7 => line_no(index) := '7';
when 8 => line_no(index) := '8';
when 9 => line_no(index) := '9';
when others => ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function hex_str_to_int( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'A' => digit := 10;
when 'a' => digit := 10;
when 'B' => digit := 11;
when 'b' => digit := 11;
when 'C' => digit := 12;
when 'c' => digit := 12;
when 'D' => digit := 13;
when 'd' => digit := 13;
when 'E' => digit := 14;
when 'e' => digit := 14;
when 'F' => digit := 15;
when 'f' => digit := 15;
when others=>
ASSERT FALSE
REPORT "Illegal character "& str(i) & "in Intel Hex File! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
function hex_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while ( index<=8 ) loop
digit := ivalue MOD 16;
ivalue := ivalue/16;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when 10 =>
line_no(index) := 'A';
when 11 =>
line_no(index) := 'B';
when 12 =>
line_no(index) := 'C';
when 13 =>
line_no(index) := 'D';
when 14 =>
line_no(index) := 'E';
when 15 =>
line_no(index) := 'F';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
procedure Shrink_line(L : inout LINE; pos : in integer) is
subtype nstring is string(1 to pos);
variable stmp : nstring;
begin
if pos >= 1 then
read(l,stmp);
end if;
end;
end SIMIO_PACKAGE;
|
lgpl-3.0
|
Hyperion302/omega-cpu
|
Hardware/Omega/MemoryController.vhdl
|
1
|
14939
|
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.constants.all;
use IEEE.Numeric_std.all;
entity MemoryController is
port (
CLK : in std_logic;
Address : in word;
Enable : in std_logic;
ToWrite : in word;
FromRead : out word;
Instruction : in word;
Reset : in std_logic;
Done : out std_logic;
SRAM_addr : out std_logic_vector(20 downto 0);
SRAM_OE : out std_logic;
SRAM_CE : out std_logic;
SRAM_WE : out std_logic;
SRAM_data : inout std_logic_vector(7 downto 0);
Status_Debug : out std_logic_vector(7 downto 0)
);
end MemoryController;
architecture Behavioral of MemoryController is
constant LoadByteUnsigned : Operator := "000";
constant LoadByteSigned : Operator := "001";
constant LoadHalfWordUnsigned : Operator := "010";
constant LoadHalfWordSigned : Operator := "011";
constant LoadWord : Operator := "100";
constant StoreByte : Operator := "101";
constant StoreHalfWord : Operator := "110";
constant StoreWord : Operator := "111";
-- outputTest (absolute jump)
--constant BootImage : MemoryArray := ("01000001","00000000","00100000","00100100","00000000","00000000","00100001","10110100","00000001","00000000","00000000","11000100","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000");
-- outputTest (relative jump)
constant BootImage : MemoryArray := ("01000001","00000000","00100000","00100100","00000000","00000000","00100001","10110100","11111111","11111111","11111111","11001011","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000");
-- ROT13
--constant BootImage : MemoryArray := ("00000000","00000000","10000001","10100100","01000001","00000000","00100100","01110100","00001010","00000000","00100000","11011000","01011011","00000000","00100100","01110100","00001001","00000000","00100000","11011000","01100001","00000000","00100100","01110100","00000110","00000000","00100000","11011000","01111011","00000000","00100100","01110100","00001100","00000000","00100000","11011000","00000011","00000000","00000000","11001000","00000000","00000000","10000001","10110100","11110101","11111111","11111111","11001011","11111110","11111111","11111111","11001011","10111111","11111111","10000100","00100100","00001101","00000000","10000100","00100100","00011010","00000000","00100100","01110100","00000010","00000000","00100000","11011000","11100110","11111111","10000100","00100100","01000001","00000000","10000100","00100100","11110111","11111111","11111111","11001011","10011111","11111111","10000100","00100100","00001101","00000000","10000100","00100100","00011010","00000000","00100100","01110100","00000010","00000000","00100000","11011000","11100110","11111111","10000100","00100100","01100001","00000000","10000100","00100100","11110000","11111111","11111111","11001011","00000000","00000000","00000000");--(others => (others => '0'));
signal FromRead_S : Word := (others => '0');
signal NeedsInit : std_logic := '1';
signal BootImageIndex : Integer := 0;
signal Done_s : std_logic := '0';
signal SRAM_addr_s : std_logic_vector(20 downto 0) := (others => '0');
signal SRAM_data_s : std_logic_vector(7 downto 0); --:= (others => 'Z');
signal SRAM_OE_s : std_logic := '1';
signal SRAM_WE_s : std_logic := '1';
signal SRAM_CE_s : std_logic := '1';
signal AddressOffset : integer := 0;
signal Status_Debug_s : std_logic_vector(7 downto 0) := (others => '0');
begin -- Behavioral
SRAM_addr <= SRAM_addr_s;
SRAM_data <= SRAM_data_s when SRAM_OE_s = '1' else (others => 'Z');
SRAM_OE <= SRAM_OE_s;
SRAM_WE <= SRAM_WE_s;
SRAM_CE <= '0';
FromRead <= FromRead_S;
Done <= Done_s;
Status_Debug <= Status_Debug_S;
process (CLK)--(Enable, Instruction, Address, Reset)
-- procedure initialize is begin
-- Memory(0) <= "00000000";
-- Memory(1) <= "00000000";
-- Memory(2) <= "10000001";
-- Memory(3) <= "10100100";
-- Memory(4) <= "01000001";
-- Memory(5) <= "00000000";
-- Memory(6) <= "00100100";
-- Memory(7) <= "01110100";
-- Memory(8) <= "00001010";
-- Memory(9) <= "00000000";
-- Memory(10) <= "00100000";
-- Memory(11) <= "11011000";
-- Memory(12) <= "01011011";
-- Memory(13) <= "00000000";
-- Memory(14) <= "00100100";
-- Memory(15) <= "01110100";
---- Memory(16) <= "00001001";
---- Memory(17) <= "00000000";
---- Memory(18) <= "00100000";
---- Memory(19) <= "11011000";
---- Memory(20) <= "01100001";
---- Memory(21) <= "00000000";
---- Memory(22) <= "00100100";
---- Memory(23) <= "01110100";
---- Memory(24) <= "00000110";
---- Memory(25) <= "00000000";
---- Memory(26) <= "00100000";
---- Memory(27) <= "11011000";
---- Memory(28) <= "01111011";
---- Memory(29) <= "00000000";
---- Memory(30) <= "00100100";
---- Memory(31) <= "01110100";
---- Memory(32) <= "00001100";
---- Memory(33) <= "00000000";
---- Memory(34) <= "00100000";
---- Memory(35) <= "11011000";
---- Memory(36) <= "00000011";
---- Memory(37) <= "00000000";
---- Memory(38) <= "00000000";
---- Memory(39) <= "11001000";
---- Memory(40) <= "00000000";
---- Memory(41) <= "00000000";
---- Memory(42) <= "10000001";
---- Memory(43) <= "10110100";
---- Memory(44) <= "11110101";
---- Memory(45) <= "11111111";
---- Memory(46) <= "11111111";
---- Memory(47) <= "11001011";
---- Memory(48) <= "11111110";
---- Memory(49) <= "11111111";
---- Memory(50) <= "11111111";
---- Memory(51) <= "11001011";
---- Memory(52) <= "10111111";
---- Memory(53) <= "11111111";
---- Memory(54) <= "10000100";
---- Memory(55) <= "00100100";
---- Memory(56) <= "00001101";
---- Memory(57) <= "00000000";
---- Memory(58) <= "10000100";
---- Memory(59) <= "00100100";
---- Memory(60) <= "00011010";
---- Memory(61) <= "00000000";
---- Memory(62) <= "00100100";
---- Memory(63) <= "01110100";
---- Memory(64) <= "00000010";
---- Memory(65) <= "00000000";
---- Memory(66) <= "00100000";
---- Memory(67) <= "11011000";
---- Memory(68) <= "11100110";
---- Memory(69) <= "11111111";
---- Memory(70) <= "10000100";
---- Memory(71) <= "00100100";
---- Memory(72) <= "01000001";
---- Memory(73) <= "00000000";
---- Memory(74) <= "10000100";
---- Memory(75) <= "00100100";
---- Memory(76) <= "11110111";
---- Memory(77) <= "11111111";
---- Memory(78) <= "11111111";
---- Memory(79) <= "11001011";
---- Memory(80) <= "10011111";
---- Memory(81) <= "11111111";
---- Memory(82) <= "10000100";
---- Memory(83) <= "00100100";
---- Memory(84) <= "00001101";
---- Memory(85) <= "00000000";
---- Memory(86) <= "10000100";
---- Memory(87) <= "00100100";
---- Memory(88) <= "00011010";
---- Memory(89) <= "00000000";
---- Memory(90) <= "00100100";
---- Memory(91) <= "01110100";
---- Memory(92) <= "00000010";
---- Memory(93) <= "00000000";
---- Memory(94) <= "00100000";
---- Memory(95) <= "11011000";
---- Memory(96) <= "11100110";
---- Memory(97) <= "11111111";
---- Memory(98) <= "10000100";
---- Memory(99) <= "00100100";
---- Memory(100) <= "01100001";
---- Memory(101) <= "00000000";
---- Memory(102) <= "10000100";
---- Memory(103) <= "00100100";
---- Memory(104) <= "11110000";
---- Memory(105) <= "11111111";
---- Memory(106) <= "11111111";
---- Memory(107) <= "11001011";
-- --for I in 100 to 4095 loop
-- -- Memory(I) <= "00000000";
-- --end loop;
-- end procedure initialize;
variable current_operator : std_logic_vector(2 downto 0);
begin -- process
if rising_edge(CLK) then
if NeedsInit = '1' then
if BootImageIndex = BootImage'Length then
SRAM_we_s <= '1';
-- SRAM_addr_s <= "000000000000001101011";
-- SRAM_oe_s <= '0';
-- BootImageIndex <= BootImageIndex + 1;
-- elsif BootImageIndex = (BootImage'Length + 1) then
NeedsInit <= '0';
-- Status_Debug_S <= SRAM_data xor "11111111";
SRAM_oe_s <= '1';
else
SRAM_data_s <= BootImage(BootImageIndex);
SRAM_addr_s <= std_logic_vector(to_unsigned(BootImageIndex,21));
SRAM_we_s <= '0';
BootImageIndex <= BootImageIndex + 1;
end if;
--Memory <= (others => (others => '0'));
-- initialize;
elsif Enable = '1' then
current_operator := GetOperator(Instruction);
case current_operator is
when LoadByteUnsigned =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
Done_s <= '0';
else
FromRead_S <= "000000000000000000000000" & SRAM_data;
SRAM_oe_s <= '1';
Done_s <= '1';
end if;
when LoadByteSigned =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
Done_s <= '0';
else
FromRead_S <= std_logic_vector(resize(signed(SRAM_data),32));
SRAM_oe_s <= '1';
Done_s <= '1';
end if;
when LoadHalfWordUnsigned =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
AddressOffset <= 0;
Done_s <= '0';
elsif AddressOffset < 1 then
SRAM_addr_s <= std_logic_vector(unsigned(Address(20 downto 0)) + to_unsigned(AddressOffset + 1,20));
AddressOffset <= AddressOffset + 1;
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
else
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
FromRead_S(31 downto 16) <= (others => '0');
AddressOffset <= 0;
SRAM_oe_s <= '1';
Done_s <= '1';
end if;
when LoadHalfWordSigned =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
AddressOffset <= 0;
Done_s <= '0';
elsif AddressOffset < 1 then
SRAM_addr_s <= std_logic_vector(unsigned(Address(20 downto 0)) + to_unsigned(AddressOffset + 1,20));
AddressOffset <= AddressOffset + 1;
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
else
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
if SRAM_data(7) = '1' then
FromRead_S(31 downto 16) <= "1111111111111111";
else
FromRead_S(31 downto 16) <= "0000000000000000";
end if;
AddressOffset <= 0;
SRAM_oe_s <= '1';
Done_s <= '1';
end if;
when LoadWord =>
if SRAM_oe_s = '1' then
SRAM_addr_s <= Address(20 downto 0);
SRAM_oe_s <= '0';
AddressOffset <= 0;
Done_s <= '0';
elsif AddressOffset < 3 then
SRAM_addr_s <= std_logic_vector(unsigned(Address(20 downto 0)) + to_unsigned(AddressOffset+1,20));
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
AddressOffset <= AddressOffset + 1;
else
FromRead_S(8*AddressOffset+7 downto 8*AddressOffset) <= SRAM_data;
AddressOffset <= 0;
SRAM_oe_s <= '1';
Done_s <= '1';
Status_Debug_S <= Address(9 downto 2) xor "11111111";
end if;
when StoreByte =>
-- Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
Done_s <= '1';
when StoreHalfWord =>
-- Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
-- Memory(to_integer(unsigned(Address)) + 1) <= ToWrite(15 downto 8);
Done_s <= '1';
when StoreWord =>
-- Memory(to_integer(unsigned(Address))) <= ToWrite(7 downto 0);
-- Memory(to_integer(unsigned(Address)) + 1) <= ToWrite(15 downto 8);
-- Memory(to_integer(unsigned(Address)) + 2) <= ToWrite(23 downto 16);
-- Memory(to_integer(unsigned(Address)) + 3) <= ToWrite(31 downto 24);
Done_s <= '1';
when others => null;
end case;
else
SRAM_oe_s <= '1';
SRAM_we_s <= '1';
Done_s <= '0';
end if;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
trondd/mkjpeg
|
design/quantizer/s_divider.vhd
|
2
|
6676
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : Signed Pipelined Divider core --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : S_DIVIDER.VHD --
-- Created : Sat Aug 26 2006 --
-- Modified : Thu Mar 12 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Signed Pipelined Divider --
-- --
-- dividend allowable range of -2**SIZE_C to 2**SIZE_C-1 [SIGNED number] --
-- divisor allowable range of 1 to (2**SIZE_C)/2-1 [UNSIGNED number] --
-- pipeline latency is 2*SIZE_C+2 (time from latching input to result ready) --
-- when pipeline is full new result is generated every clock cycle --
-- Non-Restoring division algorithm --
-- Use SIZE_C constant in divider entity to adjust bit width --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity s_divider is
generic
(
SIZE_C : INTEGER := 32
) ; -- SIZE_C: Number of bits
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
d : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
q : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
r : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
round : out STD_LOGIC
) ;
end s_divider ;
architecture str of s_divider is
type S_ARRAY is array(0 to SIZE_C+3) of unsigned(SIZE_C-1 downto 0);
type S2_ARRAY is array(0 to SIZE_C+1) of unsigned(2*SIZE_C-1 downto 0);
signal d_s : S_ARRAY;
signal q_s : S_ARRAY;
signal r_s : S2_ARRAY;
signal diff : S_ARRAY;
signal qu_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal ru_s : unsigned(SIZE_C-1 downto 0);
signal qu_s2 : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal ru_s2 : unsigned(SIZE_C-1 downto 0);
signal d_reg : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal pipeline_reg : STD_LOGIC_VECTOR(SIZE_C+3-1 downto 0);
signal r_reg : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
begin
pipeline : process(clk,rst)
begin
if rst = '1' then
for k in 0 to SIZE_C loop
r_s(k) <= (others => '0');
q_s(k) <= (others => '0');
d_s(k) <= (others => '0');
end loop;
pipeline_reg <= (others => '0');
elsif clk = '1' and clk'event then
-- negative number
if a(SIZE_C-1) = '1' then
-- negate negative number to create positive
r_s(0) <= unsigned(resize(unsigned(not(SIGNED(a)) + TO_SIGNED(1,SIZE_C)),2*SIZE_C));
-- left shift
pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '1';
else
r_s(0) <= resize(unsigned(a),2*SIZE_C);
-- left shift
pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '0';
end if;
d_s(0) <= unsigned(d);
q_s(0) <= (others => '0');
-- pipeline
for k in 0 to SIZE_C loop
-- test remainder if positive/negative
if r_s(k)(2*SIZE_C-1) = '0' then
-- shift r_tmp one bit left and subtract d_tmp from upper part of r_tmp
r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) - d_s(k);
else
r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) + d_s(k);
end if;
-- shift r_tmp one bit left (lower part)
r_s(k+1)(SIZE_C-1 downto 0) <= r_s(k)(SIZE_C-2 downto 0) & '0';
if diff(k)(SIZE_C-1) = '0' then
q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '1';
else
q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '0';
end if;
d_s(k+1) <= d_s(k);
end loop;
end if;
end process;
G_DIFF: for x in 0 to SIZE_C generate
diff(x) <= r_s(x)(2*SIZE_C-2 downto SIZE_C-1) - d_s(x) when r_s(x)(2*SIZE_C-1) = '0'
else r_s(x)(2*SIZE_C-2 downto SIZE_C-1) + d_s(x);
end generate G_DIFF;
qu_s <= STD_LOGIC_VECTOR( q_s(SIZE_C) );
ru_s <= r_s(SIZE_C)(2*SIZE_C-1 downto SIZE_C);
process(clk,rst)
begin
if rst = '1' then
q <= (others => '0');
r_reg <= (others => '0');
round <= '0';
elsif clk = '1' and clk'event then
if ru_s(SIZE_C-1) = '0' then
ru_s2 <= (ru_s);
else
ru_s2 <= (unsigned(ru_s) + d_s(SIZE_C));
end if;
qu_s2 <= qu_s;
-- negative number
if pipeline_reg(SIZE_C+1) = '1' then
-- negate positive number to create negative
q <= STD_LOGIC_VECTOR(not(SIGNED(qu_s2)) + TO_SIGNED(1,SIZE_C));
r_reg <= STD_LOGIC_VECTOR(not(SIGNED(ru_s2)) + TO_SIGNED(1,SIZE_C));
else
q <= STD_LOGIC_VECTOR(qu_s2);
r_reg <= STD_LOGIC_VECTOR(ru_s2);
end if;
-- if 2*remainder >= divisor then add 1 to round to nearest integer
if (ru_s2(SIZE_C-2 downto 0) & '0') >= d_s(SIZE_C+1) then
round <= '1';
else
round <= '0';
end if;
end if;
end process;
-- remainder
r <= r_reg;
end str;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_spartan6/syn/vhdl/nfa_accept_samples_generic_hw_add_14ns_14ns_14_4.vhd
|
3
|
9512
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(13 downto 0);
b: in std_logic_vector(13 downto 0);
s: out std_logic_vector(13 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(13 downto 0);
signal b_reg : std_logic_vector(13 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(13 downto 12);
signal b3_cb : std_logic_vector(13 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(13 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(13 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(13 downto 12);
b3_cb <= b_reg(13 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(13 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(13 downto 12) <= fas(13 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_U : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_kintex7/impl/vhdl/nfa_accept_samples_generic_hw.vhd
|
1
|
88720
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k325tffg676-3,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.350000,HLS_SYN_LAT=129178013,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (5 downto 0) := "101000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (5 downto 0) := "101001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal stop_on_first_read_read_fu_104_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_fu_230_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_316 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_fu_235_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_reg_321 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_fu_240_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_reg_326 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_330 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal offset_reg_336 : STD_LOGIC_VECTOR (31 downto 0);
signal or_cond_fu_247_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_341 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_done : STD_LOGIC;
signal grp_fu_252_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_reg_345 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_start : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_ap_idle : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_ap_ready : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_178_sample_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_178_sample_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_tmp_14 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_length_r : STD_LOGIC_VECTOR (15 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_return : STD_LOGIC_VECTOR (0 downto 0);
signal grp_sample_iterator_get_offset_fu_194_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_194_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_194_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_194_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_194_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_211_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_211_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_211_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_211_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_211_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_reg_146 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_156 : STD_LOGIC_VECTOR (15 downto 0);
signal p_0_reg_166 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_sample_iterator_next_fu_211_ap_start_ap_start_reg : STD_LOGIC := '0';
signal c_fu_94 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_252_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_252_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_252_ce : STD_LOGIC;
component nfa_accept_sample IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
tmp_14 : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_nfa_accept_sample_fu_178 : component nfa_accept_sample
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_accept_sample_fu_178_ap_start,
ap_done => grp_nfa_accept_sample_fu_178_ap_done,
ap_idle => grp_nfa_accept_sample_fu_178_ap_idle,
ap_ready => grp_nfa_accept_sample_fu_178_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size,
nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size,
nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address,
nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout,
nfa_forward_buckets_size => grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size,
nfa_symbols => grp_nfa_accept_sample_fu_178_nfa_symbols,
sample_req_din => grp_nfa_accept_sample_fu_178_sample_req_din,
sample_req_full_n => grp_nfa_accept_sample_fu_178_sample_req_full_n,
sample_req_write => grp_nfa_accept_sample_fu_178_sample_req_write,
sample_rsp_empty_n => grp_nfa_accept_sample_fu_178_sample_rsp_empty_n,
sample_rsp_read => grp_nfa_accept_sample_fu_178_sample_rsp_read,
sample_address => grp_nfa_accept_sample_fu_178_sample_address,
sample_datain => grp_nfa_accept_sample_fu_178_sample_datain,
sample_dataout => grp_nfa_accept_sample_fu_178_sample_dataout,
sample_size => grp_nfa_accept_sample_fu_178_sample_size,
tmp_14 => grp_nfa_accept_sample_fu_178_tmp_14,
length_r => grp_nfa_accept_sample_fu_178_length_r,
ap_return => grp_nfa_accept_sample_fu_178_ap_return);
grp_sample_iterator_get_offset_fu_194 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_194_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_194_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_194_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_194_ap_ready,
indices_stride_req_din => grp_sample_iterator_get_offset_fu_194_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_get_offset_fu_194_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_get_offset_fu_194_indices_stride_address,
indices_stride_datain => grp_sample_iterator_get_offset_fu_194_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_get_offset_fu_194_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_get_offset_fu_194_indices_stride_size,
indices_begin_req_din => grp_sample_iterator_get_offset_fu_194_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_get_offset_fu_194_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_get_offset_fu_194_indices_begin_address,
indices_begin_datain => grp_sample_iterator_get_offset_fu_194_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_get_offset_fu_194_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_get_offset_fu_194_indices_begin_size,
ap_ce => grp_sample_iterator_get_offset_fu_194_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_194_i_index,
i_sample => grp_sample_iterator_get_offset_fu_194_i_sample,
indices_samples_req_din => grp_sample_iterator_get_offset_fu_194_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_get_offset_fu_194_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_get_offset_fu_194_indices_samples_address,
indices_samples_datain => grp_sample_iterator_get_offset_fu_194_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_get_offset_fu_194_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_get_offset_fu_194_indices_samples_size,
sample_buffer_size => grp_sample_iterator_get_offset_fu_194_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_194_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_194_ap_return);
grp_sample_iterator_next_fu_211 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_211_ap_start,
ap_done => grp_sample_iterator_next_fu_211_ap_done,
ap_idle => grp_sample_iterator_next_fu_211_ap_idle,
ap_ready => grp_sample_iterator_next_fu_211_ap_ready,
indices_samples_req_din => grp_sample_iterator_next_fu_211_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_next_fu_211_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_next_fu_211_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_next_fu_211_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_next_fu_211_indices_samples_address,
indices_samples_datain => grp_sample_iterator_next_fu_211_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_next_fu_211_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_next_fu_211_indices_samples_size,
ap_ce => grp_sample_iterator_next_fu_211_ap_ce,
indices_begin_req_din => grp_sample_iterator_next_fu_211_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_next_fu_211_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_next_fu_211_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_next_fu_211_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_next_fu_211_indices_begin_address,
indices_begin_datain => grp_sample_iterator_next_fu_211_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_next_fu_211_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_next_fu_211_indices_begin_size,
indices_stride_req_din => grp_sample_iterator_next_fu_211_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_next_fu_211_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_next_fu_211_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_next_fu_211_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_next_fu_211_indices_stride_address,
indices_stride_datain => grp_sample_iterator_next_fu_211_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_next_fu_211_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_next_fu_211_indices_stride_size,
i_index => grp_sample_iterator_next_fu_211_i_index,
i_sample => grp_sample_iterator_next_fu_211_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_211_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_211_ap_return_1);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 38,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_252_p0,
din1 => grp_fu_252_p1,
ce => grp_fu_252_ce,
dout => grp_fu_252_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg assign process. --
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_178_ap_ready)) then
grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_240_p2 = ap_const_lv1_0))) then
grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_194_ap_ready)) then
grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_211_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_211_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st30_fsm_29 = ap_NS_fsm) and ((ap_ST_st22_fsm_21 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm)))) then
grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_211_ap_ready)) then
grp_sample_iterator_next_fu_211_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_fu_94 assign process. --
c_fu_94_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st30_fsm_29 = ap_CS_fsm) and (or_cond_reg_341 = ap_const_lv1_0))) then
c_fu_94 <= c_1_reg_345;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_94 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_index_reg_146 assign process. --
i_index_reg_146_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st41_fsm_40 = ap_CS_fsm)) then
i_index_reg_146 <= grp_sample_iterator_next_fu_211_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_146 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_156 assign process. --
i_sample_reg_156_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st41_fsm_40 = ap_CS_fsm)) then
i_sample_reg_156 <= grp_sample_iterator_next_fu_211_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_156 <= begin_sample;
end if;
end if;
end process;
-- p_0_reg_166 assign process. --
p_0_reg_166_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then
p_0_reg_166 <= ap_const_lv32_1;
elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_326 = ap_const_lv1_0)))) then
p_0_reg_166 <= c_fu_94;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st29_fsm_28 = ap_CS_fsm)) then
c_1_reg_345 <= grp_fu_252_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
c_load_reg_330 <= c_fu_94;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st21_fsm_20 = ap_CS_fsm)) then
offset_reg_336 <= grp_sample_iterator_get_offset_fu_194_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)))) then
or_cond_reg_341 <= or_cond_fu_247_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
tmp_i_10_reg_321 <= tmp_i_10_fu_235_p2;
tmp_i_reg_316 <= tmp_i_fu_230_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
tmp_i_11_reg_326 <= tmp_i_11_fu_240_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_104_p2 , tmp_i_11_reg_326 , or_cond_fu_247_p2 , grp_nfa_accept_sample_fu_178_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((tmp_i_11_reg_326 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st42_fsm_41;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
if ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and not((stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0)) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st42_fsm_41;
elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and (stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0) and (or_cond_fu_247_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st23_fsm_22;
elsif ((not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and not((or_cond_fu_247_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st30_fsm_29;
else
ap_NS_fsm <= ap_ST_st22_fsm_21;
end if;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st42_fsm_41 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_166;
-- grp_fu_252_ce assign process. --
grp_fu_252_ce_assign_proc : process(ap_CS_fsm, stop_on_first_read_read_fu_104_p2, or_cond_fu_247_p2, grp_nfa_accept_sample_fu_178_ap_done)
begin
if (((ap_ST_st29_fsm_28 = ap_CS_fsm) or ((ap_ST_st22_fsm_21 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_178_ap_done)) and (stop_on_first_read_read_fu_104_p2 = ap_const_lv1_0) and (or_cond_fu_247_p2 = ap_const_lv1_0)) or (ap_ST_st23_fsm_22 = ap_CS_fsm) or (ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st25_fsm_24 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm))) then
grp_fu_252_ce <= ap_const_logic_1;
else
grp_fu_252_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_252_p0 <= c_load_reg_330;
grp_fu_252_p1 <= ap_const_lv32_1;
grp_nfa_accept_sample_fu_178_ap_start <= grp_nfa_accept_sample_fu_178_ap_start_ap_start_reg;
grp_nfa_accept_sample_fu_178_length_r <= sample_length;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_datain <= nfa_forward_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_178_nfa_symbols <= nfa_symbols;
grp_nfa_accept_sample_fu_178_sample_datain <= sample_buffer_datain;
grp_nfa_accept_sample_fu_178_sample_req_full_n <= sample_buffer_req_full_n;
grp_nfa_accept_sample_fu_178_sample_rsp_empty_n <= sample_buffer_rsp_empty_n;
grp_nfa_accept_sample_fu_178_tmp_14 <= offset_reg_336;
grp_sample_iterator_get_offset_fu_194_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_194_ap_start <= grp_sample_iterator_get_offset_fu_194_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_194_i_index <= i_index_reg_146;
grp_sample_iterator_get_offset_fu_194_i_sample <= i_sample_reg_156;
grp_sample_iterator_get_offset_fu_194_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_get_offset_fu_194_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_get_offset_fu_194_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_get_offset_fu_194_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_get_offset_fu_194_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_get_offset_fu_194_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
grp_sample_iterator_get_offset_fu_194_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_194_sample_length <= sample_length;
grp_sample_iterator_next_fu_211_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_211_ap_start <= grp_sample_iterator_next_fu_211_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_211_i_index <= i_index_reg_146;
grp_sample_iterator_next_fu_211_i_sample <= i_sample_reg_156;
grp_sample_iterator_next_fu_211_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_next_fu_211_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_next_fu_211_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_next_fu_211_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_next_fu_211_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_next_fu_211_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_next_fu_211_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_next_fu_211_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_next_fu_211_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
-- indices_begin_address assign process. --
indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_address, grp_sample_iterator_next_fu_211_indices_begin_address)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_next_fu_211_indices_begin_address;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_get_offset_fu_194_indices_begin_address;
else
indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_dataout assign process. --
indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_dataout, grp_sample_iterator_next_fu_211_indices_begin_dataout)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_next_fu_211_indices_begin_dataout;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_get_offset_fu_194_indices_begin_dataout;
else
indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_req_din assign process. --
indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_req_din, grp_sample_iterator_next_fu_211_indices_begin_req_din)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_next_fu_211_indices_begin_req_din;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_din;
else
indices_begin_req_din <= 'X';
end if;
end process;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_req_write, grp_sample_iterator_next_fu_211_indices_begin_req_write)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_next_fu_211_indices_begin_req_write;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_get_offset_fu_194_indices_begin_req_write;
else
indices_begin_req_write <= 'X';
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read, grp_sample_iterator_next_fu_211_indices_begin_rsp_read)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_next_fu_211_indices_begin_rsp_read;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_begin_rsp_read;
else
indices_begin_rsp_read <= 'X';
end if;
end process;
-- indices_begin_size assign process. --
indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_begin_size, grp_sample_iterator_next_fu_211_indices_begin_size)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_next_fu_211_indices_begin_size;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_get_offset_fu_194_indices_begin_size;
else
indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_address assign process. --
indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_address, grp_sample_iterator_next_fu_211_indices_samples_address)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_next_fu_211_indices_samples_address;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_get_offset_fu_194_indices_samples_address;
else
indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_dataout assign process. --
indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_dataout, grp_sample_iterator_next_fu_211_indices_samples_dataout)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_next_fu_211_indices_samples_dataout;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_get_offset_fu_194_indices_samples_dataout;
else
indices_samples_dataout <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_req_din assign process. --
indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_req_din, grp_sample_iterator_next_fu_211_indices_samples_req_din)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_next_fu_211_indices_samples_req_din;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_din;
else
indices_samples_req_din <= 'X';
end if;
end process;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_req_write, grp_sample_iterator_next_fu_211_indices_samples_req_write)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_next_fu_211_indices_samples_req_write;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_get_offset_fu_194_indices_samples_req_write;
else
indices_samples_req_write <= 'X';
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read, grp_sample_iterator_next_fu_211_indices_samples_rsp_read)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_next_fu_211_indices_samples_rsp_read;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_samples_rsp_read;
else
indices_samples_rsp_read <= 'X';
end if;
end process;
-- indices_samples_size assign process. --
indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_samples_size, grp_sample_iterator_next_fu_211_indices_samples_size)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_next_fu_211_indices_samples_size;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_get_offset_fu_194_indices_samples_size;
else
indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_address assign process. --
indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_address, grp_sample_iterator_next_fu_211_indices_stride_address)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_next_fu_211_indices_stride_address;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_get_offset_fu_194_indices_stride_address;
else
indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_dataout assign process. --
indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_dataout, grp_sample_iterator_next_fu_211_indices_stride_dataout)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_next_fu_211_indices_stride_dataout;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_get_offset_fu_194_indices_stride_dataout;
else
indices_stride_dataout <= "XXXXXXXX";
end if;
end process;
-- indices_stride_req_din assign process. --
indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_req_din, grp_sample_iterator_next_fu_211_indices_stride_req_din)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_next_fu_211_indices_stride_req_din;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_din;
else
indices_stride_req_din <= 'X';
end if;
end process;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_req_write, grp_sample_iterator_next_fu_211_indices_stride_req_write)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_next_fu_211_indices_stride_req_write;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_get_offset_fu_194_indices_stride_req_write;
else
indices_stride_req_write <= 'X';
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read, grp_sample_iterator_next_fu_211_indices_stride_rsp_read)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_next_fu_211_indices_stride_rsp_read;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_194_indices_stride_rsp_read;
else
indices_stride_rsp_read <= 'X';
end if;
end process;
-- indices_stride_size assign process. --
indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_326, grp_sample_iterator_get_offset_fu_194_indices_stride_size, grp_sample_iterator_next_fu_211_indices_stride_size)
begin
if (((ap_ST_st41_fsm_40 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm) or (ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st40_fsm_39 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_next_fu_211_indices_stride_size;
elsif (((ap_ST_st21_fsm_20 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_326 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_get_offset_fu_194_indices_stride_size;
else
indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_finals_buckets_size;
nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_address;
nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_dataout;
nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_din;
nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_req_write;
nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_rsp_read;
nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_forward_buckets_size;
nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_178_nfa_initials_buckets_size;
or_cond_fu_247_p2 <= (grp_nfa_accept_sample_fu_178_ap_return xor accept);
sample_buffer_address <= grp_nfa_accept_sample_fu_178_sample_address;
sample_buffer_dataout <= grp_nfa_accept_sample_fu_178_sample_dataout;
sample_buffer_req_din <= grp_nfa_accept_sample_fu_178_sample_req_din;
sample_buffer_req_write <= grp_nfa_accept_sample_fu_178_sample_req_write;
sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_178_sample_rsp_read;
sample_buffer_size <= grp_nfa_accept_sample_fu_178_sample_size;
stop_on_first_read_read_fu_104_p2 <= stop_on_first;
tmp_i_10_fu_235_p2 <= "1" when (i_index_reg_146 = end_index) else "0";
tmp_i_11_fu_240_p2 <= (tmp_i_reg_316 and tmp_i_10_reg_321);
tmp_i_fu_230_p2 <= "1" when (i_sample_reg_156 = end_sample) else "0";
end behav;
|
lgpl-3.0
|
jairov4/accel-oil
|
impl/impl_test_single/hdl/system_microblaze_0_wrapper.vhd
|
1
|
93945
|
-------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_50_c;
use microblaze_v8_50_c.all;
entity system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 7);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 63);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 63);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 7);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 63);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 63);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_wrapper : entity is "microblaze_v8_50_c";
end system_microblaze_0_wrapper;
architecture STRUCTURE of system_microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_BASE_VECTORS : std_logic_vector;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_USE_REORDER_INSTR : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer;
C_PC_WIDTH : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 50000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "virtex5",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 1,
C_STREAM_INTERCONNECT => 0,
C_BASE_VECTORS => X"00000000",
C_DPLB_DWIDTH => 64,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 64,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 0,
C_D_PLB => 1,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 1,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 0,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 8192,
C_ICACHE_USE_FSL => 1,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 1,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 0,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
INTERRUPT_ADDRESS => INTERRUPT_ADDRESS,
INTERRUPT_ACK => INTERRUPT_ACK,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
WAKEUP => WAKEUP,
SLEEP => SLEEP,
DBG_WAKEUP => DBG_WAKEUP,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_AWDOMAIN => M_AXI_IC_AWDOMAIN,
M_AXI_IC_AWSNOOP => M_AXI_IC_AWSNOOP,
M_AXI_IC_AWBAR => M_AXI_IC_AWBAR,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_WACK => M_AXI_IC_WACK,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_ARDOMAIN => M_AXI_IC_ARDOMAIN,
M_AXI_IC_ARSNOOP => M_AXI_IC_ARSNOOP,
M_AXI_IC_ARBAR => M_AXI_IC_ARBAR,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_IC_RACK => M_AXI_IC_RACK,
M_AXI_IC_ACVALID => M_AXI_IC_ACVALID,
M_AXI_IC_ACADDR => M_AXI_IC_ACADDR,
M_AXI_IC_ACSNOOP => M_AXI_IC_ACSNOOP,
M_AXI_IC_ACPROT => M_AXI_IC_ACPROT,
M_AXI_IC_ACREADY => M_AXI_IC_ACREADY,
M_AXI_IC_CRREADY => M_AXI_IC_CRREADY,
M_AXI_IC_CRVALID => M_AXI_IC_CRVALID,
M_AXI_IC_CRRESP => M_AXI_IC_CRRESP,
M_AXI_IC_CDVALID => M_AXI_IC_CDVALID,
M_AXI_IC_CDREADY => M_AXI_IC_CDREADY,
M_AXI_IC_CDDATA => M_AXI_IC_CDDATA,
M_AXI_IC_CDLAST => M_AXI_IC_CDLAST,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_AWDOMAIN => M_AXI_DC_AWDOMAIN,
M_AXI_DC_AWSNOOP => M_AXI_DC_AWSNOOP,
M_AXI_DC_AWBAR => M_AXI_DC_AWBAR,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_WACK => M_AXI_DC_WACK,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_ARDOMAIN => M_AXI_DC_ARDOMAIN,
M_AXI_DC_ARSNOOP => M_AXI_DC_ARSNOOP,
M_AXI_DC_ARBAR => M_AXI_DC_ARBAR,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
M_AXI_DC_RACK => M_AXI_DC_RACK,
M_AXI_DC_ACVALID => M_AXI_DC_ACVALID,
M_AXI_DC_ACADDR => M_AXI_DC_ACADDR,
M_AXI_DC_ACSNOOP => M_AXI_DC_ACSNOOP,
M_AXI_DC_ACPROT => M_AXI_DC_ACPROT,
M_AXI_DC_ACREADY => M_AXI_DC_ACREADY,
M_AXI_DC_CRREADY => M_AXI_DC_CRREADY,
M_AXI_DC_CRVALID => M_AXI_DC_CRVALID,
M_AXI_DC_CRRESP => M_AXI_DC_CRRESP,
M_AXI_DC_CDVALID => M_AXI_DC_CDVALID,
M_AXI_DC_CDREADY => M_AXI_DC_CDREADY,
M_AXI_DC_CDDATA => M_AXI_DC_CDDATA,
M_AXI_DC_CDLAST => M_AXI_DC_CDLAST,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_spartan3/syn/vhdl/nfa_accept_samples_generic_hw_add_16ns_16ns_16_4.vhd
|
3
|
9512
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
s: out std_logic_vector(15 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2 is
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(15 downto 0);
signal b_reg : std_logic_vector(15 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(15 downto 12);
signal b3_cb : std_logic_vector(15 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(15 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(15 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(15 downto 12);
b3_cb <= b_reg(15 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(15 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(15 downto 12) <= fas(15 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 is
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_U : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
lgpl-3.0
|
lerwys/GitTest
|
hdl/modules/position_calc/generated/artix7/cntr_11_0_eb46eda57512a5a4.vhd
|
1
|
4452
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cntr_11_0_eb46eda57512a5a4.vhd when simulating
-- the core, cntr_11_0_eb46eda57512a5a4. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cntr_11_0_eb46eda57512a5a4 IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END cntr_11_0_eb46eda57512a5a4;
ARCHITECTURE cntr_11_0_eb46eda57512a5a4_a OF cntr_11_0_eb46eda57512a5a4 IS
-- synthesis translate_off
COMPONENT wrapped_cntr_11_0_eb46eda57512a5a4
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cntr_11_0_eb46eda57512a5a4 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 1,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 1,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 2,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cntr_11_0_eb46eda57512a5a4
PORT MAP (
clk => clk,
ce => ce,
sinit => sinit,
q => q
);
-- synthesis translate_on
END cntr_11_0_eb46eda57512a5a4_a;
|
lgpl-3.0
|
lerwys/GitTest
|
hdl/modules/position_calc/generated/artix7/crdc_v5_0_9d3c9eaecfab6c0c.vhd
|
1
|
5798
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file crdc_v5_0_9d3c9eaecfab6c0c.vhd when simulating
-- the core, crdc_v5_0_9d3c9eaecfab6c0c. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY crdc_v5_0_9d3c9eaecfab6c0c IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END crdc_v5_0_9d3c9eaecfab6c0c;
ARCHITECTURE crdc_v5_0_9d3c9eaecfab6c0c_a OF crdc_v5_0_9d3c9eaecfab6c0c IS
-- synthesis translate_off
COMPONENT wrapped_crdc_v5_0_9d3c9eaecfab6c0c
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_crdc_v5_0_9d3c9eaecfab6c0c USE ENTITY XilinxCoreLib.cordic_v5_0(behavioral)
GENERIC MAP (
c_architecture => 1,
c_coarse_rotate => 1,
c_cordic_function => 1,
c_data_format => 0,
c_has_aclk => 1,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_s_axis_cartesian => 1,
c_has_s_axis_cartesian_tlast => 0,
c_has_s_axis_cartesian_tuser => 1,
c_has_s_axis_phase => 0,
c_has_s_axis_phase_tlast => 0,
c_has_s_axis_phase_tuser => 0,
c_input_width => 25,
c_iterations => 0,
c_m_axis_dout_tdata_width => 48,
c_m_axis_dout_tuser_width => 1,
c_output_width => 24,
c_phase_format => 0,
c_pipeline_mode => -1,
c_precision => 0,
c_round_mode => 3,
c_s_axis_cartesian_tdata_width => 64,
c_s_axis_cartesian_tuser_width => 1,
c_s_axis_phase_tdata_width => 32,
c_s_axis_phase_tuser_width => 1,
c_scale_comp => 3,
c_throttle_scheme => 3,
c_tlast_resolution => 0,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_crdc_v5_0_9d3c9eaecfab6c0c
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tready => s_axis_cartesian_tready,
s_axis_cartesian_tuser => s_axis_cartesian_tuser,
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tuser => m_axis_dout_tuser,
m_axis_dout_tdata => m_axis_dout_tdata
);
-- synthesis translate_on
END crdc_v5_0_9d3c9eaecfab6c0c_a;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/DMA_Calculate.vhd
|
1
|
33957
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: DMA_Calculate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.20 - Taken out from the original version. 26.07.2007
--
-- Revision 1.10 - Msg inserted. 26.02.2007
--
-- Revision 1.00 - Created. 09.02.2007
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA_Calculate is
port (
-- Downstream Registers from MWr Channel
DMA_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : in std_logic;
BDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : in std_logic;
Leng_Lo7b_True : in std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : out std_logic;
DMA_Snout_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Only for downstream channel
DMA_PA_Snout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : out std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Engine control signals
DMA_Start : in std_logic;
DMA_Start2 : in std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : out std_logic; -- No more block(s) of Max_Size
ThereIs_Snout : out std_logic; -- 1st packet before Body blocks
ThereIs_Body : out std_logic; -- Block(s) of Max_Size
ThereIs_Tail : out std_logic; -- Last packet with size less than Max_Size
ThereIs_Dex : out std_logic; -- Not the last descriptor
HA64bit : out std_logic; -- Host Address is 64-bit
Addr_Inc : out std_logic; -- Peripheral Address increase token
-- FSM indicators
State_Is_LoadParam : in std_logic;
State_Is_Snout : in std_logic;
State_Is_Body : in std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : in std_logic_vector(2 downto 0);
-- Common ports
dma_clk : in std_logic;
dma_reset : in std_logic
);
end entity DMA_Calculate;
architecture Behavioral of DMA_Calculate is
-- Significant bits from the MaXSiZe parameter
signal Max_TLP_Size : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal mxsz_left : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_mid : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_right : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Signals masked by MaxSize
signal DMA_Leng_Left_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Mid_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Right_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Alias
signal Lo_Leng_Left_Msk_is_True : std_logic;
signal Lo_Leng_Mid_Msk_is_True : std_logic;
signal Lo_Leng_Right_Msk_is_True : std_logic;
-- Masked values of HA and Length
signal DMA_HA_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Length_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Indicates whether the DMA_PA is already accepted
signal PA_is_taken : std_logic;
-- Calculation for the PA of the next DMA, if UPA bit = 0
signal DMA_PA_next : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_PA_current : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- eventual PA parameter for the current DMA transaction
signal DMA_PA_Loaded_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, only for better timing
signal Carry_PA_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Carry_PAx_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Leng_Hi_plus_PA_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
signal Leng_Hi_plus_PAx_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
-- DMA parameters from the register module
signal DMA_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- delay
signal State_Is_Snout_r1 : std_logic;
signal State_Is_Body_r1 : std_logic;
-- from control word
signal Dex_is_Last : std_logic;
signal Engine_Ends : std_logic;
-- Major FSM control signals
signal ThereIs_Snout_i : std_logic;
signal ThereIs_Body_i : std_logic;
signal ThereIs_Tail_i : std_logic;
signal Snout_Only : std_logic;
signal ThereIs_Dex_i : std_logic;
signal No_More_Bodies_i : std_logic;
-- Address/Length combination
signal ALc : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Compressed ALc
-- ALc_B bit means the ALc has carry in, making an extra Body block.
signal ALc_B : std_logic;
signal ALc_B_wire : std_logic;
-- ALc_T bit means the ALc has trailer, making a final Tail block.
signal ALc_T : std_logic;
signal ALc_T_wire : std_logic;
-- Compressed Length
-- Leng_Two bit means Length >= 2 Max_Size.
signal Leng_Two : std_logic;
-- Leng_One bit means Length >= 1 Max_Size.
signal Leng_One : std_logic;
-- Leng_nint bit means Length is not integral of Max_Sizes.
signal Leng_nint : std_logic;
signal Length_analysis : std_logic_vector(2 downto 0);
signal Snout_Body_Tail : std_logic_vector(2 downto 0);
-- Byte counter
signal DMA_Byte_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- !!! Elastic
signal Length_minus : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BC_Carry : std_logic_vector(CBIT_CARRY downto 0);
-- Remote & Local Address variable
signal DMA_HA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_Carry32 : std_logic_vector(C_DBUS_WIDTH/2 downto 0);
signal DMA_PA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- BDA parameter is buffered for FSM module
signal DMA_BDA_fsm_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal BDA_is_64b_fsm_i : std_logic;
-- Token bits out of Control word
signal HA64bit_i : std_logic;
signal Addr_Inc_i : std_logic;
signal use_PA : std_logic;
-- for better timing
signal HA_gap : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
--
signal DMA_Snout_Length_i : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Tail_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- for better timing
signal raw_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal DMA_PA_Snout_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_PA_Body_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_BAR_Number_i : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
begin
-- Partition indicators
No_More_Bodies <= No_More_Bodies_i;
ThereIs_Snout <= ThereIs_Snout_i;
ThereIs_Body <= ThereIs_Body_i;
ThereIs_Tail <= ThereIs_Tail_i;
ThereIs_Dex <= ThereIs_Dex_i;
HA64bit <= HA64bit_i;
Addr_Inc <= Addr_Inc_i;
--
DMA_PA_Loaded <= DMA_PA_Loaded_i;
DMA_PA_Var <= DMA_PA_Var_i;
DMA_HA_Var <= DMA_HA_Var_i;
DMA_BDA_fsm <= DMA_BDA_fsm_i;
BDA_is_64b_fsm <= BDA_is_64b_fsm_i;
-- Only for downstream channel
DMA_PA_Snout <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number <= DMA_BAR_Number_i;
-- different lengths
DMA_Snout_Length <= DMA_Snout_Length_i;
DMA_Body_Length <= Max_TLP_Size;
DMA_Tail_Length <= DMA_Tail_Length_i;
-- Register stubs
DMA_PA_i <= DMA_PA;
DMA_HA_i <= DMA_HA;
DMA_BDA_i <= DMA_BDA;
DMA_Length_i <= DMA_Length;
DMA_Control_i <= DMA_Control;
-- ---------------------------------------------------------------
-- Parameters should be captured by the start/start2 and be kept
-- in case Pause command comes.
--
Syn_Param_Capture :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Addr_Inc_i <= '0';
use_PA <= '0';
Dex_is_Last <= '0';
Engine_Ends <= '1';
DMA_BAR_Number_i <= (others => '0');
DMA_BDA_fsm_i <= (others => '0');
BDA_is_64b_fsm_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' or DMA_Start2 = '1' then
Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
DMA_BAR_Number_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_BAR_TOP downto CINT_BIT_DMA_CTRL_BAR_BOT);
DMA_BDA_fsm_i <= DMA_BDA_i;
BDA_is_64b_fsm_i <= BDA_is_64b;
else
Addr_Inc_i <= Addr_Inc_i;
use_PA <= use_PA;
Dex_is_Last <= Dex_is_Last;
Engine_Ends <= Engine_Ends;
DMA_BAR_Number_i <= DMA_BAR_Number_i;
DMA_BDA_fsm_i <= DMA_BDA_fsm_i;
BDA_is_64b_fsm_i <= BDA_is_64b_fsm_i;
end if;
end if;
end process;
-- Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
-- use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
-- Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
-- Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
-- use_Irpt_Done <= not DMA_Control_i(CINT_BIT_DMA_CTRL_EDI);
-- Means there is consecutive descriptor(s)
ThereIs_Dex_i <= not Dex_is_Last and not Engine_Ends;
-- ---------------------------------------------------------------
-- PA_i selection
--
Syn_Calc_DMA_PA :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_current <= (others => '0');
-- DMA_BAR_Number_i <= (Others=>'0');
PA_is_taken <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken = '0' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken = '0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '1' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken = '0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '0' then
DMA_PA_current(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_next;
PA_is_taken <= '1';
else
DMA_PA_current <= DMA_PA_current;
if DMA_Start = '0' and DMA_Start2 = '0' then
PA_is_taken <= '0';
else
PA_is_taken <= PA_is_taken;
end if;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- PA_next Calculation
--
Syn_Calc_DMA_PA_next :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_next <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken = '0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PA_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PA_Hi
+ Carry_PA_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
end if;
elsif DMA_Start2 = '1' and PA_is_taken = '0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PAx_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PAx_Hi
+ Carry_PAx_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_next;
end if;
else
DMA_PA_next <= DMA_PA_next;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PA_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PA_plus_Leng :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PA_plus_Leng <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PA_plus_Leng <= ('0'& DMA_PA_i(CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PAx_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PAx_plus_Leng :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PAx_plus_Leng <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PAx_plus_Leng <= ('0'& DMA_PA_next (CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PA_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PA_Hi :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PA_Hi <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PA_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_i(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PAx_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PAx_Hi :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PAx_Hi <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PAx_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_Leng_Left_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left;
DMA_Leng_Mid_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid;
DMA_Leng_Right_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_HA_Msk <= (DMA_HA_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_HA_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
DMA_Length_Msk <= (DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_Length_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
-- -----------------------------------------------------------------------------------------------------------------------------------
Lo_Leng_Left_Msk_is_True <= '0' when DMA_Leng_Left_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Mid_Msk_is_True <= '0' when DMA_Leng_Mid_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Right_Msk_is_True <= '0' when DMA_Leng_Right_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
-- ----------------------------------------------------------
-- Synchronous Register: Leng_Info(Compressed Length Information)
---
Syn_Calc_Parameter_Leng_Info :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Two <= '0';
Leng_One <= '0';
Leng_nint <= '0';
elsif dma_clk'event and dma_clk = '1' then
Leng_Two <= Leng_Hi19b_True or Lo_Leng_Left_Msk_is_True;
Leng_One <= Lo_Leng_Mid_Msk_is_True;
Leng_nint <= Leng_Lo7b_True or Lo_Leng_Right_Msk_is_True;
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
ALc_B_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
else '1';
ALc_T_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and ALc(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)
else '1';
-- -----------------------------------------------------------------------------------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Register: ALc (Address-Length combination)
---
Syn_Calc_Parameter_ALc :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
ALc <= (others => '0');
ALc_B <= '0';
ALc_T <= '0';
elsif dma_clk'event and dma_clk = '1' then
ALc <= DMA_Length_Msk + DMA_HA_Msk;
ALc_B <= ALc_B_wire;
ALc_T <= ALc_T_wire;
end if;
end process;
-- concatenation of the Length information
Length_analysis <= Leng_Two & Leng_One & Leng_nint;
-- -------------------------------------------
-- Analysis on the DMA division
-- truth-table expressions
--
Comb_S_B_T :
process (
Length_analysis
, ALc_B
, ALc_T
)
begin
case Length_analysis is
-- Zero-length DMA, nothing to send
when "000" =>
Snout_Body_Tail <= "000";
-- Length < Max_Size. Always Snout and never Body, Tail depends on ALc.
when "001" =>
Snout_Body_Tail <= '1' & '0' & (ALc_B and ALc_T);
-- Length = Max_Size. Division depends only on ALc-Tail.
when "010" =>
Snout_Body_Tail <= ALc_T & not ALc_T & ALc_T;
-- Length = (k+1) Max_Size, k>=1. Always Body. Snout and Tail depend on ALc-Tail.
-- Body = Leng_Two or not ALc_T
when "100" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
when "110" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
-- Length = (1+d) Max_Size, 0<d<1. Always Snout. Body and Tail copy ALc.
when "011" =>
Snout_Body_Tail <= '1' & ALc_B & ALc_T;
-- Length = (k+1+d) Max_Size, k>=1, 0<d<1. Always Snout and Body. Tail copies ALc-Tail.
-- Body = Leng_Two or ALc_B
when "101" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
when "111" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
-- dealt as zero-length DMA
when others =>
Snout_Body_Tail <= "000";
end case;
end process;
-- -----------------------------------------------
-- Synchronous Register:
-- ThereIs_Snout
-- ThereIs_Body
-- ThereIs_Tail
--
Syn_Calc_Parameters_SBT :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
ThereIs_Snout_i <= '0';
ThereIs_Body_i <= '0';
ThereIs_Tail_i <= '0';
Snout_Only <= '0';
elsif dma_clk'event and dma_clk = '1' then
ThereIs_Snout_i <= Snout_Body_Tail(2);
ThereIs_Body_i <= Snout_Body_Tail(1);
ThereIs_Tail_i <= Snout_Body_Tail(0);
Snout_Only <= ALc_T and not Snout_Body_Tail(0);
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA_gap
--
Syn_Calc_HA_gap :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA_gap <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
HA_gap <= Max_TLP_Size - DMA_HA_Msk;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Snout_Carry
--
FSM_Calc_DMA_PA_Snout_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Snout_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Snout_Carry <= ('0'& DMA_PA_current(CBIT_CARRY-1 downto 0)) + HA_gap;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Body_Carry
--
FSM_Calc_DMA_PA_Body_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Body_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Body_Carry <= ('0'& DMA_PA_Var_i(CBIT_CARRY-1 downto 0)) + Max_TLP_Size;
end if;
end process;
-- ------------------------------------------------------------------
-- Synchronous Register: Length_minus
--
Sync_Calc_Length_minus :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Length_minus <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Length_minus <= DMA_Length_i - Max_TLP_Size;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_BC_Carry
--
FSM_Calc_DMA_BC_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_BC_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_BC_Carry <= ('0'& DMA_Byte_Counter(CBIT_CARRY-1 downto 0)) - Max_TLP_Size;
end if;
end process;
-- --------------------------------------------
-- Synchronous reg: DMA_Snout_Length
-- DMA_Tail_Length
--
FSM_Calc_DMA_Snout_Tail_Lengths :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Snout_Length_i <= (others => '0');
DMA_Tail_Length_i <= (others => '0');
raw_Tail_Length <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_Tail_Length_i(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= (raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
and mxsz_right(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
) & raw_Tail_Length( C_MAXSIZE_FLD_BIT_BOT-1 downto 0);
if State_Is_LoadParam = '1' then
raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= DMA_Length_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
+ DMA_HA_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
if Snout_Only = '1' then
DMA_Snout_Length_i <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto 2) &"00";
else
DMA_Snout_Length_i <= Max_TLP_Size - DMA_HA_Msk;
end if;
else
DMA_Snout_Length_i <= DMA_Snout_Length_i;
raw_Tail_Length <= raw_Tail_Length;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous Delays:
-- State_Is_Snout_r1
-- State_Is_Body_r1
--
Syn_Delay_State_is_x :
process (dma_clk)
begin
if dma_clk'event and dma_clk = '1' then
State_Is_Snout_r1 <= State_Is_Snout;
State_Is_Body_r1 <= State_Is_Body;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Carry32
--
FSM_Calc_DMA_HA_Carry32 :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Carry32 <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Carry32 <= '0' & DMA_HA_i(C_DBUS_WIDTH/2-1 downto 2) & "00"; -- temp
elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Carry32(C_DBUS_WIDTH/2 downto C_MAXSIZE_FLD_BIT_BOT) <= ('0'& DMA_HA_Var_i(C_DBUS_WIDTH/2-1 downto C_MAXSIZE_FLD_BIT_TOP+1) &
(DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right)
) + mxsz_mid;
else
DMA_HA_Carry32 <= DMA_HA_Carry32;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Var
--
FSM_Calc_DMA_HA_Var :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Var_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Var_i <= DMA_HA_i(C_DBUS_WIDTH-1 downto 2) & "00"; -- temp
elsif State_Is_Snout_r1 = '1' or State_Is_Body_r1 = '1' then
-- elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) <= DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
+ DMA_HA_Carry32(C_DBUS_WIDTH/2);
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_BOT) <= (DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
& (DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right))
+ mxsz_mid;
DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) <= (others => '0'); -- MaxSize aligned
else
DMA_HA_Var_i <= DMA_HA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA64bit
--
FSM_Calc_HA64bit :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA64bit_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
HA64bit_i <= HA_is_64b;
elsif DMA_HA_Carry32(C_DBUS_WIDTH/2) = '1' then
HA64bit_i <= '1';
else
HA64bit_i <= HA64bit_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Var
--
FSM_Calc_DMA_PA_Var :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Var_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if Addr_Inc_i = '1' and ThereIs_Snout_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_current(CBIT_CARRY-1 downto 0)
+ HA_gap(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_current(C_DBUS_WIDTH-1 downto CBIT_CARRY);
else
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
end if;
elsif State_Is_Snout_r1 = '1' then
---- elsif State_Is_Snout = '1' then
if Addr_Inc_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Var_i(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Snout_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
elsif State_Is_Body_r1 = '1' then
---- elsif State_Is_Body = '1' then
if Addr_Inc_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Body_Carry(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Body_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Loaded_i
--
FSM_Calc_DMA_PA_Loaded_i :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Loaded_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_PA_Loaded_i <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
else
DMA_PA_Loaded_i <= DMA_PA_Loaded_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: DMA_Byte_Counter
---
FSM_Calc_DMA_Byte_Counter :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Byte_Counter <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if ALc_B = '0' and ALc_T = '1' then
DMA_Byte_Counter <= Length_minus;
else
DMA_Byte_Counter <= DMA_Length_i(C_DBUS_WIDTH-1 downto 2) & "00";
end if;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY)
- DMA_BC_Carry(CBIT_CARRY);
DMA_Byte_Counter(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT) <= DMA_BC_Carry(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT);
else
DMA_Byte_Counter <= DMA_Byte_Counter;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: No_More_Bodies
---
FSM_Calc_No_More_Bodies :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
No_More_Bodies_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
No_More_Bodies_i <= not ThereIs_Body_i;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
if DMA_Byte_Counter(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1) = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid) /= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
then
No_More_Bodies_i <= '1';
else
No_More_Bodies_i <= '0';
end if;
else
No_More_Bodies_i <= No_More_Bodies_i;
end if;
end if;
end process;
-- ------------------------------------------
-- Configuration pamameters: Param_Max_Cfg
--
Syn_Config_Param_Max_Cfg :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then -- 0x0080 Bytes
mxsz_left <= "111110"; -- 6 bits
mxsz_mid <= "000001"; -- 6 bits
mxsz_right <= "000000"; -- 6 bits
elsif dma_clk'event and dma_clk = '1' then
case Param_Max_Cfg is
when "000" => -- 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
when "001" => -- 0x0100 Bytes
mxsz_left <= "111100";
mxsz_mid <= "000010";
mxsz_right <= "000001";
when "010" => -- 0x0200 Bytes
mxsz_left <= "111000";
mxsz_mid <= "000100";
mxsz_right <= "000011";
when "011" => -- 0x0400 Bytes
mxsz_left <= "110000";
mxsz_mid <= "001000";
mxsz_right <= "000111";
when "100" => -- 0x0800 Bytes
mxsz_left <= "100000";
mxsz_mid <= "010000";
mxsz_right <= "001111";
when "101" => -- 0x1000 Bytes
mxsz_left <= "000000";
mxsz_mid <= "100000";
mxsz_right <= "011111";
when others => -- as 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
end case;
end if;
end process;
Max_TLP_Size <= mxsz_mid & CONV_STD_LOGIC_VECTOR(0, C_MAXSIZE_FLD_BIT_BOT);
end architecture Behavioral;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/fmc_adc_common/fmc_adc_data.vhd
|
1
|
16946
|
------------------------------------------------------------------------------
-- Title : Wishbone FMC ADC data Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-29-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Data Interface with FMC ADC boards.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-29-10 1.0 lucas.russo Created
-- 2013-19-08 1.1 lucas.russo Refactored to enable use with other FMC ADC boards
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.genram_pkg.all;
use work.fmc_adc_pkg.all;
entity fmc_adc_data is
generic
(
g_delay_type : string := "VARIABLE";
g_default_adc_data_delay : natural := 0;
g_with_data_sdr : boolean := false;
g_with_fn_dly_select : boolean := false;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
sys_rst_n_i : in std_logic;
-----------------------------
-- External ports
-----------------------------
-- ADC data channel
adc_data_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
-----------------------------
-- Input Clocks from fmc_adc_clk signals
-----------------------------
adc_clk_chain_priv_i : in t_adc_clk_chain_priv;
adc_clk_chain_glob_i : in t_adc_clk_chain_glob;
-----------------------------
-- ADC Data Delay signals
-----------------------------
adc_data_fn_dly_i : in t_adc_data_fn_dly;
adc_data_fn_dly_o : out t_adc_data_fn_dly;
--adc_data_fe_d1_en_i : in std_logic;
--adc_data_fe_d2_en_i : in std_logic;
--
--adc_data_rg_d1_en_i : in std_logic;
--adc_data_rg_d2_en_i : in std_logic;
adc_cs_dly_i : in t_adc_cs_dly;
-----------------------------
-- ADC output signals
-----------------------------
adc_out_o : out t_adc_out;
fifo_debug_valid_o : out std_logic;
fifo_debug_full_o : out std_logic;
fifo_debug_empty_o : out std_logic
);
end fmc_adc_data;
architecture rtl of fmc_adc_data is
subtype t_adc_data_delay is std_logic_vector(1 downto 0);
type t_adc_data_delay_array is array (natural range<>) of t_adc_data_delay;
constant dummy_delay_array_low : t_adc_data_delay_array(c_num_adc_bits/2-1 downto 0) :=
("00", "00", "00", "00", "00",
"00", "00", "00");
-- Small fifo depth. This FIFO is intended just to cross phase-mismatched
-- clock domains (BUFR -> BUFG), but frequency locked
constant async_fifo_size : natural := 16;
-- Number of ADC input pins. This is differente for SDR or DDR ADCs.
constant c_num_in_adc_pins : natural := f_num_adc_pins(g_with_data_sdr);
-- Clock signals
signal adc_clk_bufio : std_logic;
signal adc_clk_bufr : std_logic;
signal adc_clk_bufg : std_logic;
signal adc_clk2x_bufg : std_logic;
-- ADC data signals
signal adc_data_ddr_ibufds : std_logic_vector(c_num_in_adc_pins-1 downto 0);
signal adc_data_ddr_dly : std_logic_vector(c_num_in_adc_pins-1 downto 0);
signal adc_data_fe_sdr : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_sdr : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ff : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ff_d1 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ff_d2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_bufg_sync : std_logic_vector(c_num_adc_bits-1 downto 0);
--attribute IOB : string;
--attribute IOB of adc_data_ff: signal is "TRUE";
-- Fine delay signals
signal iodelay_update : std_logic_vector(c_num_in_adc_pins-1 downto 0);
-- Coarse Delay signals
signal adc_data_re : std_logic_vector(c_num_adc_bits/2-1 downto 0)
:= (others => '0'); -- ADC data rising edge
signal adc_data_fe : std_logic_vector(c_num_adc_bits/2-1 downto 0)
:= (others => '0'); -- ADC data falling edge
signal adc_data_fe_d1 : std_logic_vector(c_num_adc_bits/2-1 downto 0)
:= (others => '0'); -- ADC data falling edge delayed1
signal adc_data_fe_d2 : std_logic_vector(c_num_adc_bits/2-1 downto 0)
:= (others => '0'); -- ADC data falling edge delayed2
signal adc_data_rg_d1 : std_logic_vector(c_num_adc_bits-1 downto 0)
:= (others => '0'); -- ADC data delayed1
signal adc_data_rg_d2 : std_logic_vector(c_num_adc_bits-1 downto 0)
:= (others => '0'); -- ADC data delayed2
-- Only used for DDR data channel
signal adc_data_d1 : t_adc_data_delay_array(c_num_adc_bits/2-1 downto 0)
:= dummy_delay_array_low; -- ADC data falling edge delayed1
signal adc_data_d2 : t_adc_data_delay_array(c_num_adc_bits/2-1 downto 0)
:= dummy_delay_array_low; -- ADC data falling edge delayed2
-- Used for both SDR and DDR data channel
signal adc_data_d3 : std_logic_vector(c_num_adc_bits-1 downto 0)
:= (others =>'0'); -- ADC data delayed1
signal adc_data_d4 : std_logic_vector(c_num_adc_bits-1 downto 0)
:= (others =>'0'); -- ADC data delayed1
-- FIFO signals
signal adc_fifo_full : std_logic;
signal adc_fifo_wr : std_logic;
signal adc_fifo_rd : std_logic;
signal adc_fifo_empty : std_logic;
signal adc_fifo_valid : std_logic;
-- Valid ADC signals
signal adc_data_valid : std_logic;
signal adc_data_valid_out : std_logic;
-- Delay internal signals
signal adc_data_dly_val_int : std_logic_vector(5*c_num_in_adc_pins-1 downto 0);
signal sys_rst : std_logic;
begin
--sys_rst <= not sys_rst_n_i;
adc_clk_bufio <= adc_clk_chain_priv_i.adc_clk_bufio;
adc_clk_bufr <= adc_clk_chain_priv_i.adc_clk_bufr;
adc_clk_bufg <= adc_clk_chain_glob_i.adc_clk_bufg;
adc_clk2x_bufg <= adc_clk_chain_glob_i.adc_clk2x_bufg;
-----------------------------
-- ADC data signal datapath
-----------------------------
--gen_adc_data : for i in 0 to (c_num_adc_bits/2)-1 generate
gen_adc_data : for i in 0 to c_num_in_adc_pins-1 generate
gen_adc_data_var_loadable_iodelay : if (g_delay_type = "VAR_LOADABLE") generate
cmp_adc_data_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_data_delay,
SIGNAL_PATTERN => "DATA",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
--idatain => adc_data_ddr_ibufds(i),
idatain => adc_data_i(i),
dataout => adc_data_ddr_dly(i),
c => sys_clk_i,
ce => '0',
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
rst => iodelay_update(i),
cntvaluein => adc_data_fn_dly_i.idelay.val,
cntvalueout => adc_data_dly_val_int(5*(i+1)-1 downto 5*i),
cinvctrl => '0',
t => '1'
);
end generate;
gen_adc_data_variable_iodelay : if (g_delay_type = "VARIABLE") generate
cmp_adc_data_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_data_delay,
SIGNAL_PATTERN => "DATA",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
--idatain => adc_data_ddr_ibufds(i),
idatain => adc_data_i(i),
dataout => adc_data_ddr_dly(i),
c => sys_clk_i,
--ce => adc_data_dly_pulse_i,
ce => iodelay_update(i),
inc => adc_data_fn_dly_i.idelay.incdec,
datain => '0',
odatain => '0',
clkin => '0',
rst => '0',
cntvaluein => adc_data_fn_dly_i.idelay.val,
cntvalueout => adc_data_dly_val_int(5*(i+1)-1 downto 5*i),
cinvctrl => '0',
t => '1'
);
end generate;
gen_with_fn_dly_select : if (g_with_fn_dly_select) generate
iodelay_update(i) <= '1' when adc_data_fn_dly_i.idelay.pulse = '1' and
adc_data_fn_dly_i.sel.which(i) = '1' else '0';
end generate;
gen_without_fn_dly_select : if (not g_with_fn_dly_select) generate
iodelay_update(i) <= adc_data_fn_dly_i.idelay.pulse;
end generate;
-- Data come as SDR. Just passthrough the bits
gen_with_sdr : if (g_with_data_sdr) generate
adc_data_fe_sdr(i) <= adc_data_ddr_dly(i);
end generate;
gen_with_ddr : if (not g_with_data_sdr) generate
-- DDR to SDR. This component is clocked with BUFIO clock for
-- maximum performance.
-- Note that the rising and falling edges are inverted to each other
-- as the ISLA216 codes the data in following way:
--
-- ODD1a EVEN1a ODD2a EVEN2a ...
-- ris fal ris fal
cmp_iddr : iddr
generic map(
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
)
port map(
q1 => adc_data_re(i),--adc_data_sdr(2*i+1),
q2 => adc_data_fe(i),--adc_data_sdr(2*i),
c => adc_clk_bufio,
--c => adc_clk_bufr_i,
ce => '1',
d => adc_data_ddr_dly(i),
r => '0',
s => '0'
);
-- Delay falling edge of IDDR by 1 or 2 cycles to match the transition bits
p_delay_fe_delay : process(adc_clk_bufr)
begin
if rising_edge (adc_clk_bufr) then
--if sys_rst_n_i = '0' then
-- adc_data_fe_d1(i) <= '0';
-- adc_data_fe_d2(i) <= '0';
--else
adc_data_fe_d1(i) <= adc_data_fe(i);
adc_data_fe_d2(i) <= adc_data_fe_d1(i);
--end if;
end if;
end process;
-- adc bits delay software-controlled via adc_data_fe_d1_en and adc_data_fe_d2_en
adc_data_d1(i)(1) <= adc_data_fe_d1(i) when adc_cs_dly_i.adc_data_fe_d1_en = '1' else adc_data_re(i);
adc_data_d1(i)(0) <= adc_data_re(i) when adc_cs_dly_i.adc_data_fe_d1_en = '1' else adc_data_fe(i);
adc_data_d2(i)(1) <= adc_data_fe_d2(i) when adc_cs_dly_i.adc_data_fe_d2_en = '1' else adc_data_d1(i)(1);
adc_data_d2(i)(0) <= adc_data_d1(i)(0);
-- Grorup all the falling edge delayed bits.
adc_data_fe_sdr(2*i) <= adc_data_d2(i)(0);
adc_data_fe_sdr(2*i+1) <= adc_data_d2(i)(1);
end generate;
end generate;
-- Output a single value to adc_data_dly_val_o
adc_data_fn_dly_o.idelay.val <= adc_data_dly_val_int(4 downto 0);
-- Delay the whole channel by 1 or 2 cycles
p_delay_rg_delay : process(adc_clk_bufr)
begin
if rising_edge (adc_clk_bufr) then
adc_data_rg_d1 <= adc_data_fe_sdr;
adc_data_rg_d2 <= adc_data_rg_d1;
end if;
end process;
-- adc data words delay software-controlled via adc_data_rg_d1_en and adc_data_rg_d2_en
adc_data_d3 <= adc_data_rg_d1 when adc_cs_dly_i.adc_data_rg_d1_en = '1' else adc_data_fe_sdr;
adc_data_d4 <= adc_data_rg_d2 when adc_cs_dly_i.adc_data_rg_d2_en = '1' else adc_data_d3;
adc_data_sdr <= adc_data_d4;
-- Some FF to solve timing problem
p_adc_data_ff : process(adc_clk_bufr)
begin
if rising_edge (adc_clk_bufr) then
adc_data_ff <= adc_data_sdr;
adc_data_ff_d1 <= adc_data_ff;
adc_data_ff_d2 <= adc_data_ff_d1;
end if;
end process;
-- On the other hand, BUFG and BUFR/BUFIO are not guaranteed to be phase-matched,
-- as they drive independently clock nets. Hence, a FIFO is needed to employ
-- a clock domain crossing.
cmp_adc_data_async_fifo : generic_async_fifo
generic map(
g_data_width => c_num_adc_bits,
g_size => async_fifo_size
)
port map(
--rst_n_i => sys_rst_n_i,
-- We don't need this reset as this FIFO is used for CDC only
rst_n_i => '1',
-- write port
clk_wr_i => adc_clk_bufr,
d_i => adc_data_ff_d2,
--d_i => adc_data_sdr,
we_i => adc_fifo_wr,
wr_full_o => adc_fifo_full,
-- read port
clk_rd_i => adc_clk_bufg,
q_o => adc_data_bufg_sync,
rd_i => adc_fifo_rd,
rd_empty_o => adc_fifo_empty
);
--Generate valid signal for adc_data_o.
--Just delay the valid adc_fifo_rd signal as the fifo takes
--one clock cycle, after it has registered adc_fifo_rd, to output
--data on q_o port
p_gen_valid : process (adc_clk_bufg)
begin
if rising_edge (adc_clk_bufg) then
adc_data_valid_out <= adc_fifo_rd;
if adc_fifo_empty = '1' then
adc_data_valid_out <= '0';
end if;
end if;
end process;
adc_fifo_wr <= '1';
adc_fifo_rd <= '1';
-- Convenient signal for adc capture in later FPGA logic
adc_out_o.adc_clk <= adc_clk_bufg;
adc_out_o.adc_clk2x <= adc_clk2x_bufg;
adc_out_o.adc_data <= adc_data_bufg_sync;
adc_out_o.adc_data_valid <= adc_data_valid_out;
-- Debug
fifo_debug_valid_o <= adc_data_valid_out;
fifo_debug_full_o <= adc_fifo_full;
fifo_debug_empty_o <= adc_fifo_empty;
end rtl;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd
|
1
|
26259
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_data_io.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Top-level for all data (DQ, DQS, DM) related IOB logic.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_data_io.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_data_io.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_data_io is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCK_PER_CLK : integer := 2; -- # of memory clocks per CLK
CLK_PERIOD : integer := 3000; -- Internal clock period (in ps)
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
DM_WIDTH : integer := 9; -- # of DM (data mask)
DQ_WIDTH : integer := 72; -- # of DQ (data)
DQS_WIDTH : integer := 9; -- # of DQS (strobe)
DRAM_TYPE : string := "DDR3";
nCWL : integer := 5; -- Write CAS latency (in clk cyc)
WRLVL : string := "OFF"; -- Enable write leveling
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG"; -- May be assigned unique name
-- when mult IP cores in design
nDQS_COL0 : integer := 4; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 4; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 0; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 0; -- # DQS groups in I/O column #4
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"000000000000000000000000000003020100";-- DQS grps in col #1
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000007060504";-- DQS grps in col #2
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";-- DQS grps in col #3
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";-- DQS grps in col #4
USE_DM_PORT : integer := 1 -- DM instantation enable
);
port (
clk_mem : in std_logic;
clk : in std_logic;
clk_cpt : in std_logic_vector(DQS_WIDTH - 1 downto 0);
clk_rsync : in std_logic_vector(3 downto 0);
rst : in std_logic;
rst_rsync : in std_logic_vector(3 downto 0);
-- IODELAY I/F
dlyval_dq : in std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dlyval_dqs : in std_logic_vector(5*DQS_WIDTH - 1 downto 0);
-- Write datapath I/F
inv_dqs : in std_logic_vector(DQS_WIDTH - 1 downto 0);
wr_calib_dly : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
dqs_oe_n : in std_logic_vector(4*DQS_WIDTH - 1 downto 0);
dq_oe_n : in std_logic_vector(4*DQS_WIDTH - 1 downto 0);
dqs_rst : in std_logic_vector((DQS_WIDTH * 4) - 1 downto 0);
dm_ce : in std_logic_vector(DQS_WIDTH - 1 downto 0);
mask_data_rise0 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_fall0 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_rise1 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_fall1 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
wr_data_rise0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_rise1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_fall0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_fall1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
-- Read datapath I/F
rd_bitslip_cnt : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdly_cnt : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdiv_inv : in std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_data_rise0 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall0 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_rise1 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall1 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_dqs_rise0 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_fall0 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_rise1 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_fall1 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
-- DDR3 bus signals
ddr_dm : out std_logic_vector(DM_WIDTH - 1 downto 0);
ddr_dqs_p : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dq : inout std_logic_vector(DQ_WIDTH - 1 downto 0);
-- Debug Port
dbg_dqs_tap_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_dq_tap_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0)
);
end phy_data_io;
architecture trans of phy_data_io is
-- ratio of # of physical DM outputs to bytes in data bus
-- may be different - e.g. if using x4 components
constant DM_TO_BYTE_RATIO : integer := DM_WIDTH / (DQ_WIDTH / 8);
signal clk_rsync_dqs : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dq_tap_cnt : std_logic_vector(5*DQ_WIDTH - 1 downto 0);
signal rst_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rst_rsync_dqs : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rst_dqs_r : std_logic_vector(DQS_WIDTH-1 downto 0);
signal rst_dm_r : std_logic_vector(DM_WIDTH-1 downto 0);
signal rst_dq_r : std_logic_vector(DQ_WIDTH-1 downto 0);
------- phy_dqs_iob component --------
component phy_dqs_iob
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic; -- memory-rate clock
clk : in std_logic; -- internal (logic) clock
clk_cpt : in std_logic; -- read capture clock
clk_rsync : in std_logic; -- resynchronization (read) clock
rst : in std_logic; -- reset sync'ed to CLK
rst_rsync : in std_logic; -- reset sync'ed to RSYNC
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0); -- IODELAY (DQS) parallel load value
-- Write datapath I/F
dqs_oe_n : in std_logic_vector(3 downto 0); -- DQS output enable
dqs_rst : in std_logic_vector(3 downto 0); -- D4 input of OSERDES: 1- for normal, 0- for WL
-- Read datapath I/F
rd_bitslip_cnt : in std_logic_vector(1 downto 0);
rd_clkdly_cnt : in std_logic_vector(1 downto 0);
rd_clkdiv_inv : in std_logic;
rd_dqs_rise0 : out std_logic; -- DQS captured in clk_cpt domain
rd_dqs_fall0 : out std_logic; -- used by Phase Detector. Monitor DQS
rd_dqs_rise1 : out std_logic;
rd_dqs_fall1 : out std_logic;
-- DDR3 bus signals
ddr_dqs_p : inout std_logic;
ddr_dqs_n : inout std_logic;
-- Debug Port
dqs_tap_cnt : out std_logic_vector(4 downto 0)
);
end component;
------- phy_dq_iob component --------
component phy_dq_iob
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCWL : integer := 5; -- Write CAS latency (in clk cyc)
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
WRLVL : string := "ON"; -- "OFF" for "DDR3" component interface
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic;
clk : in std_logic;
rst : in std_logic;
clk_cpt : in std_logic;
clk_rsync : in std_logic;
rst_rsync : in std_logic;
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0);
-- Write datapath I/F
inv_dqs : in std_logic;
wr_calib_dly : in std_logic_vector(1 downto 0);
dq_oe_n : in std_logic_vector(3 downto 0);
wr_data_rise0 : in std_logic;
wr_data_fall0 : in std_logic;
wr_data_rise1 : in std_logic;
wr_data_fall1 : in std_logic;
-- Read datapath I/F
rd_bitslip_cnt : in std_logic_vector(1 downto 0);
rd_clkdly_cnt : in std_logic_vector(1 downto 0);
rd_clkdiv_inv : in std_logic;
rd_data_rise0 : out std_logic;
rd_data_fall0 : out std_logic;
rd_data_rise1 : out std_logic;
rd_data_fall1 : out std_logic;
-- DDR3 bus signals
ddr_dq : inout std_logic;
dq_tap_cnt : out std_logic_vector(4 downto 0)
);
end component;
------- phy_dm_iob component --------
component phy_dm_iob
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCWL : integer := 5; -- CAS Write Latency
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
WRLVL : string := "ON"; -- "OFF" for "DDR3" component interface
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic;
clk : in std_logic;
clk_rsync : in std_logic;
rst : in std_logic;
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0);
dm_ce : in std_logic;
inv_dqs : in std_logic;
wr_calib_dly : in std_logic_vector(1 downto 0);
mask_data_rise0 : in std_logic;
mask_data_fall0 : in std_logic;
mask_data_rise1 : in std_logic;
mask_data_fall1 : in std_logic;
ddr_dm : out std_logic
);
end component;
attribute max_fanout: string;
attribute max_fanout of rst_dqs_r : signal is "1";
attribute max_fanout of rst_dm_r : signal is "1";
attribute max_fanout of rst_dq_r : signal is "1";
attribute shreg_extract: string;
attribute shreg_extract of rst_dqs_r : signal is "no";
attribute shreg_extract of rst_dm_r : signal is "no";
attribute shreg_extract of rst_dq_r : signal is "no";
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of rst_dqs_r : signal is "no";
attribute equivalent_register_removal of rst_dm_r : signal is "no";
attribute equivalent_register_removal of rst_dq_r : signal is "no";
attribute syn_maxfan : integer;
attribute syn_maxfan of rst_dqs_r : signal is 1;
attribute syn_maxfan of rst_dm_r : signal is 1;
attribute syn_maxfan of rst_dq_r : signal is 1;
attribute syn_srlstyle : string;
attribute syn_srlstyle of rst_dqs_r : signal is "noextractff_srl";
attribute syn_srlstyle of rst_dm_r : signal is "noextractff_srl";
attribute syn_srlstyle of rst_dq_r : signal is "noextractff_srl";
attribute syn_preserve : boolean;
attribute syn_preserve of rst_dqs_r : signal is true;
attribute syn_preserve of rst_dm_r : signal is true;
attribute syn_preserve of rst_dq_r : signal is true;
begin
-- XST attributes for local reset tree RST_R - prohibit equivalent
-- register removal on RST_R to prevent "sharing" w/ other local reset trees
-- synthesis attribute shreg_extract of rst_r is "no";
-- synthesis attribute equivalent_register_removal of rst_r is "no"
--
--***************************************************************************
-- Steer correct CLK_RSYNC to each DQS/DQ/DM group - different DQS groups
-- can reside on different I/O columns - each I/O column will have its
-- own CLK_RSYNC
-- Also steer correct performance path clock to each DQS/DQ/DM group -
-- different DQS groups can reside on different I/O columns - inner I/O
-- column I/Os will use clk_wr_i, other column I/O's will use clk_wr_o
-- By convention, inner columns use DQS_COL0 and DQS_COL1, and outer
-- columns use DQS_COL2 and DQS_COL3.
--***************************************************************************
gen_c0 : if (nDQS_COL0 > 0) generate
gen_loop_c0 : for c0_i in 0 to nDQS_COL0 - 1 generate
clk_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) <= clk_rsync(0);
rst_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) <= rst_rsync(0);
end generate;
end generate;
gen_c1 : if (nDQS_COL1 > 0) generate
gen_loop_c1 : for c1_i in 0 to (nDQS_COL1 - 1) generate
clk_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) <= clk_rsync(1);
rst_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) <= rst_rsync(1);
end generate;
end generate;
gen_c2 : if (nDQS_COL2 > 0) generate
gen_loop_c2 : for c2_i in 0 to (nDQS_COL2 - 1) generate
clk_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) <= clk_rsync(2);
rst_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) <= rst_rsync(2);
end generate;
end generate;
gen_c3 : if (nDQS_COL3 > 0) generate
gen_loop_c3 : for c3_i in 0 to nDQS_COL3 - 1 generate
clk_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) <= clk_rsync(3);
rst_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) <= rst_rsync(3);
end generate;
end generate;
--***************************************************************************
-- Reset pipelining - register reset signals to prevent large (and long)
-- fanouts during physical compilation of the design. Create one local reset
-- for every byte's worth of DQ/DM/DQS (this should be local since DQ/DM/DQS
-- are placed close together)
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_r <= (others => '1') after (TCQ)*1 ps;
else
rst_r <= (others => '0') after (TCQ)*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- DQS instances
--***************************************************************************
gen_dqs : for dqs_i in 0 to DQS_WIDTH - 1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_dqs_r(dqs_i) <= '1' after (TCQ)*1 ps;
else
rst_dqs_r(dqs_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
u_phy_dqs_iob : phy_dqs_iob
generic map (
DRAM_TYPE => (DRAM_TYPE),
REFCLK_FREQ => (REFCLK_FREQ),
IBUF_LPWR_MODE => (IBUF_LPWR_MODE),
IODELAY_HP_MODE => (IODELAY_HP_MODE),
IODELAY_GRP => (IODELAY_GRP)
)
port map (
clk_mem => clk_mem,
clk => clk,
clk_cpt => clk_cpt(dqs_i),
clk_rsync => clk_rsync_dqs(dqs_i),
rst => rst_dqs_r(dqs_i),
rst_rsync => rst_rsync_dqs(dqs_i),
dlyval => dlyval_dqs(5*dqs_i+4 downto 5*dqs_i),
dqs_oe_n => dqs_oe_n(4*dqs_i+3 downto 4*dqs_i),
dqs_rst => dqs_rst(4*dqs_i+3 downto 4*dqs_i),
rd_bitslip_cnt => rd_bitslip_cnt(2*dqs_i+1 downto 2*dqs_i),
rd_clkdly_cnt => rd_clkdly_cnt(2*dqs_i+1 downto 2*dqs_i),
rd_clkdiv_inv => rd_clkdiv_inv(dqs_i),
rd_dqs_rise0 => rd_dqs_rise0(dqs_i),
rd_dqs_fall0 => rd_dqs_fall0(dqs_i),
rd_dqs_rise1 => rd_dqs_rise1(dqs_i),
rd_dqs_fall1 => rd_dqs_fall1(dqs_i),
ddr_dqs_p => ddr_dqs_p(dqs_i),
ddr_dqs_n => ddr_dqs_n(dqs_i),
dqs_tap_cnt => dbg_dqs_tap_cnt(5*dqs_i+4 downto 5*dqs_i)
);
end generate;
--***************************************************************************
-- DM instances
--***************************************************************************
gen_dm_inst: if (USE_DM_PORT /= 0) generate
gen_dm : for dm_i in 0 to DM_WIDTH - 1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_dm_r(dm_i) <= '1' after (TCQ)*1 ps;
else
rst_dm_r(dm_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
u_phy_dm_iob : phy_dm_iob
generic map (
TCQ => (TCQ),
nCWL => (nCWL),
DRAM_TYPE => (DRAM_TYPE),
WRLVL => (WRLVL),
REFCLK_FREQ => (REFCLK_FREQ),
IODELAY_HP_MODE => (IODELAY_HP_MODE),
IODELAY_GRP => (IODELAY_GRP)
)
port map (
clk_mem => clk_mem,
clk => clk,
clk_rsync => clk_rsync_dqs(dm_i),
rst => rst_dm_r(dm_i),
dlyval => dlyval_dq(5*dm_i+4 downto 5*dm_i),
dm_ce => dm_ce(dm_i),
inv_dqs => inv_dqs(dm_i),
wr_calib_dly => wr_calib_dly(2*dm_i+1 downto 2*dm_i),
mask_data_rise0 => mask_data_rise0(dm_i / DM_TO_BYTE_RATIO),
mask_data_fall0 => mask_data_fall0(dm_i / DM_TO_BYTE_RATIO),
mask_data_rise1 => mask_data_rise1(dm_i / DM_TO_BYTE_RATIO),
mask_data_fall1 => mask_data_fall1(dm_i / DM_TO_BYTE_RATIO),
ddr_dm => ddr_dm(dm_i)
);
end generate;
end generate;
--***************************************************************************
-- DQ IOB instances
--***************************************************************************
gen_dq : for dq_i in 0 to DQ_WIDTH - 1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_dq_r(dq_i) <= '1' after (TCQ)*1 ps;
else
rst_dq_r(dq_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
u_iob_dq : phy_dq_iob
generic map (
tcq => (TCQ),
ncwl => (nCWL),
dram_type => (DRAM_TYPE),
wrlvl => (WRLVL),
refclk_freq => (REFCLK_FREQ),
ibuf_lpwr_mode => (IBUF_LPWR_MODE),
iodelay_hp_mode => (IODELAY_HP_MODE),
iodelay_grp => (IODELAY_GRP)
)
port map (
clk_mem => clk_mem,
clk => clk,
rst => rst_dq_r(dq_i),
clk_cpt => clk_cpt(dq_i / DRAM_WIDTH),
clk_rsync => clk_rsync_dqs(dq_i / DRAM_WIDTH),
rst_rsync => rst_rsync_dqs(dq_i / DRAM_WIDTH),
dlyval => dlyval_dq(5 * (dq_i / DRAM_WIDTH) + 4 downto 5 * (dq_i / DRAM_WIDTH)),
inv_dqs => inv_dqs(dq_i / DRAM_WIDTH),
wr_calib_dly => wr_calib_dly(2 * (dq_i / DRAM_WIDTH) + 1 downto 2 * (dq_i / DRAM_WIDTH)),
dq_oe_n => dq_oe_n(4 * (dq_i / DRAM_WIDTH) + 3 downto 4 * (dq_i / DRAM_WIDTH)),
wr_data_rise0 => wr_data_rise0(dq_i),
wr_data_fall0 => wr_data_fall0(dq_i),
wr_data_rise1 => wr_data_rise1(dq_i),
wr_data_fall1 => wr_data_fall1(dq_i),
rd_bitslip_cnt => rd_bitslip_cnt(2 * (dq_i / DRAM_WIDTH) + 1 downto 2 * (dq_i / DRAM_WIDTH)),
rd_clkdly_cnt => rd_clkdly_cnt(2 * (dq_i / DRAM_WIDTH) + 1 downto 2 * (dq_i / DRAM_WIDTH)),
rd_clkdiv_inv => rd_clkdiv_inv(dq_i / DRAM_WIDTH),
rd_data_rise0 => rd_data_rise0(dq_i),
rd_data_fall0 => rd_data_fall0(dq_i),
rd_data_rise1 => rd_data_rise1(dq_i),
rd_data_fall1 => rd_data_fall1(dq_i),
ddr_dq => ddr_dq(dq_i),
dq_tap_cnt => dq_tap_cnt(5*dq_i+4 downto 5*dq_i)
);
end generate;
-- Only use one DQ IODELAY tap per DQS group, since all DQs in the same
-- DQS group have the same delay value (because calibration for both write
-- and read timing is done on a per-DQS group basis, not a per-bit basis)
gen_dbg: for dbg_i in 0 to (DQS_WIDTH - 1) generate
dbg_dq_tap_cnt(5*dbg_i+4 downto 5*dbg_i) <= dq_tap_cnt (5*DRAM_WIDTH*dbg_i + 4 downto 5*DRAM_WIDTH*dbg_i);
end generate;
end trans;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd
|
1
|
10963
|
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
-- Modified by Lucas Russo <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
entity xwb_stream_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_i : in std_logic
);
end xwb_stream_sink;
architecture rtl of xwb_stream_sink is
-- FIFO ranges
constant c_data_lsb : natural := 0;
constant c_data_msb : natural := c_data_lsb + c_wbs_data_width - 1;
constant c_addr_lsb : natural := c_data_msb + 1;
constant c_addr_msb : natural := c_addr_lsb + c_wbs_address_width -1;
constant c_valid_bit : natural := c_addr_msb + 1;
constant c_sel_lsb : natural := c_valid_bit + 1;
constant c_sel_msb : natural := c_sel_lsb + (c_wbs_data_width/8) - 1;
constant c_eof_bit : natural := c_sel_msb + 1;
constant c_sof_bit : natural := c_eof_bit + 1;
alias c_logic_lsb is c_valid_bit;
alias c_logic_msb is c_sof_bit;
constant c_logic_width : integer := c_sof_bit - c_valid_bit + 1;
constant c_fifo_width : integer := c_sof_bit - c_data_lsb + 1;
constant c_fifo_depth : integer := 32;
constant c_logic_zeros : std_logic_vector(c_logic_msb downto c_logic_lsb)
:= std_logic_vector(to_unsigned(0, c_logic_width));
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
signal cyc_d0, rd_d0 : std_logic;
signal pre_sof, pre_eof, pre_dvalid : std_logic;
signal pre_bytesel : std_logic_vector((c_wbs_data_width/8)-1 downto 0);
signal post_sof, post_dvalid : std_logic;
signal post_addr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal post_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal post_eof : std_logic;
signal post_bytesel : std_logic_vector((c_wbs_data_width/8)-1 downto 0);
signal snk_out : t_wbs_sink_out;
begin -- rtl
p_delay_cyc_and_rd : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
rd_d0 <= '0';
else
if(full = '0') then
cyc_d0 <= snk_i.cyc;
end if;
rd_d0 <= rd;
end if;
end if;
end process;
pre_sof <= snk_i.cyc and not cyc_d0; -- sof
pre_eof <= not snk_i.cyc and cyc_d0; -- eof
--pre_bytesel <= not snk_i.sel(0); -- bytesel
pre_bytesel <= snk_i.sel; -- bytesel
pre_dvalid <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall; -- data valid
fin(c_data_msb downto c_data_lsb) <= snk_i.dat;
fin(c_addr_msb downto c_addr_lsb) <= snk_i.adr;
fin(c_logic_msb downto c_logic_lsb) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
snk_out.err <= '0';
snk_out.rty <= '0';
p_gen_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
end if;
end if;
end process;
snk_o <= snk_out;
-- FIX. Review the comparison fin(c_logic_msb downto c_logic_lsb) /= c_logic_zeros
we <= '1' when fin(c_logic_msb downto c_logic_lsb) /= c_logic_zeros
and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid
);
p_fout_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fout_reg <= (others => '0');
elsif(rd = '1') then
fout_reg <= fout;
end if;
end if;
end process;
-- Output fifo registers only when valid
--p_post_regs : process(fout_reg, q_valid)
--begin
-- if q_valid = '1' then
-- post_data <= fout_reg(c_data_msb downto c_data_lsb);
-- post_addr <= fout_reg(c_addr_msb downto c_addr_lsb);
-- post_sof <= fout_reg(c_sof_bit); --and rd_d0; --and q_valid;
-- post_dvalid <= fout_reg(c_valid_bit);
-- post_eof <= fout_reg(c_eof_bit);-- and rd_d0;
-- post_bytesel <= fout_reg(c_sel_msb downto c_sel_lsb);
-- else
-- post_data <= (others => '0');
-- post_addr <= (others => '0');
-- post_sof <= '0';
-- post_dvalid <= '0';
-- post_eof <= '0';
-- post_bytesel <= (others => '0');
-- end if;
--end process;
post_sof <= fout_reg(c_sof_bit) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(c_valid_bit);
post_eof <= fout_reg(c_eof_bit);
post_bytesel <= fout_reg(c_sel_msb downto c_sel_lsb);
post_data <= fout_reg(c_data_msb downto c_data_lsb);
post_addr <= fout_reg(c_addr_msb downto c_addr_lsb);
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = std_logic_vector(c_WBS_STATUS)) and (f_unmarshall_wbs_status(post_data).error = '1') else '0';
eof_o <= post_eof and rd_d0;
bytesel_o <= post_bytesel;
data_o <= post_data;
addr_o <= post_addr;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
entity wb_stream_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_dat_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
snk_adr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
snk_sel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end wb_stream_sink;
architecture wrapper of wb_stream_sink is
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
signal snk_in : t_wbs_sink_in;
signal snk_out : t_wbs_sink_out;
begin -- wrapper
cmp_stream_sink_wrapper : xwb_stream_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
addr_o => addr_o,
data_o => data_o,
dvalid_o => dvalid_o,
sof_o => sof_o,
eof_o => eof_o,
error_o => error_o,
bytesel_o => bytesel_o,
dreq_i => dreq_i);
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.cyc <= snk_cyc_i;
snk_in.sel <= snk_sel_i;
snk_stall_o <= snk_out.stall;
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd
|
1
|
16639
|
-------------------------------------------------------------------------------------
-- FILE NAME : amc7823_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - amc7823_ctrl
-- architecture - amc7823_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the AMC7823 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity amc7823_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end amc7823_ctrl;
architecture amc7823_ctrl_syn of amc7823_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component amc7823_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(4 downto 0);
douta : out std_logic_vector(31 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000320";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0000115"; --page 1 (0x40), reg 0x15
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"000011E"; --page 1 (0x40), reg 0x1E
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal mon_reset : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal page_reg : std_logic_vector(1 downto 0);
signal inst_reg : std_logic_vector(4 downto 0);
signal data_reg : std_logic_vector(15 downto 0);
signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(31 downto 0);
signal init_address : std_logic_vector(4 downto 0);
signal init_data : std_logic_vector(31 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(15 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
gen_serial_clk : if (g_sim = 0) generate
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the falling edge of SCLK.
-- therefore we make sure the external clock is slightly
-- before the internal clock.
sclk_ext <= clk_div(clk_div'length-1);
serial_clk <= sclk_ext;
end if;
end process;
end generate;
-- Do not divide clock. Improve simulation speed.
gen_serial_clk_sim : if (g_sim = 1) generate
serial_clk <= clk;
end generate;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the DAC state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
mon_reset <= '1';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
page_reg <= (others=> '0');
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
mon_reset <= out_reg(1);
else
mon_reset <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 28) & busy & not mon_n_int & mon_reset & init_done_prev;
-- read from serial if when address is within DAC range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 16) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within DAC range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
page_reg <= out_reg_addr(9 downto 8);
inst_reg <= out_reg_addr(4 downto 0);
data_reg <= out_reg(15 downto 0);
-- Read instruction, only when address is within DAC range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
page_reg <= in_reg_addr(9 downto 8);
inst_reg <= in_reg_addr(4 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- DAC serial interface state-machine
----------------------------------------------------------------------------------------------------
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 1;
--end generate;
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= sh_counter_gen;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus one data byte;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- DAC instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
--rw + X,PG + X,StartADR + X,EndADR+ data
shift_reg <= '0' & init_data(26 downto 24) & init_data(21 downto 16) & init_data(21 downto 16) & init_data(15 downto 0);
-- Stop when update instruction is reveived (= last instruction)
if (init_data(31 downto 16) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
-- Always access one register per cycle
shift_reg <= inst_rw & '0' & page_reg & '0' & inst_reg & '0' & inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length - 2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from DAC
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(15 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
amc7823_init_mem_inst : amc7823_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on falling edge SCLK
-- therefore pass the signal to the process that captures on the rising edge of serial clock.
----------------------------------------------------------------------------------------------------
--process (serial_clk)
--begin
-- if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
-- end if;
--end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
mon_n_reset <= not mon_reset;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end amc7823_ctrl_syn;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/7k325ffg900/bram_x64.vhd
|
1
|
365495
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.40xd
-- \ \ Application: netgen
-- / / Filename: bram_x64.vhd
-- /___/ /\ Timestamp: Wed Oct 24 18:09:27 2012
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/pcie_brazil/PC/hdlmake/ip_cores/7k325ffg900/tmp/_cg/bram_x64.ngc /home/adrian/praca/pcie_brazil/PC/hdlmake/ip_cores/7k325ffg900/tmp/_cg/bram_x64.vhd
-- Device : 7k325tffg900-2
-- Input file : /home/adrian/praca/pcie_brazil/PC/hdlmake/ip_cores/7k325ffg900/tmp/_cg/bram_x64.ngc
-- Output file : /home/adrian/praca/pcie_brazil/PC/hdlmake/ip_cores/7k325ffg900/tmp/_cg/bram_x64.vhd
-- # of Entities : 1
-- Design Name : bram_x64
-- Xilinx : /opt/Xilinx/14.3/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity bram_x64 is
port (
clka : in STD_LOGIC := 'X';
clkb : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
web : in STD_LOGIC_VECTOR ( 7 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end bram_x64;
architecture STRUCTURE of bram_x64 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => N1
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(63),
DIADI(6) => dina(62),
DIADI(5) => dina(61),
DIADI(4) => dina(60),
DIADI(3) => dina(59),
DIADI(2) => dina(58),
DIADI(1) => dina(57),
DIADI(0) => dina(56),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(63),
DIBDI(6) => dinb(62),
DIBDI(5) => dinb(61),
DIBDI(4) => dinb(60),
DIBDI(3) => dinb(59),
DIBDI(2) => dinb(58),
DIBDI(1) => dinb(57),
DIBDI(0) => dinb(56),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(63),
DOADO(6) => douta(62),
DOADO(5) => douta(61),
DOADO(4) => douta(60),
DOADO(3) => douta(59),
DOADO(2) => douta(58),
DOADO(1) => douta(57),
DOADO(0) => douta(56),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(63),
DOBDO(6) => doutb(62),
DOBDO(5) => doutb(61),
DOBDO(4) => doutb(60),
DOBDO(3) => doutb(59),
DOBDO(2) => doutb(58),
DOBDO(1) => doutb(57),
DOBDO(0) => doutb(56),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(7),
WEA(2) => wea(7),
WEA(1) => wea(7),
WEA(0) => wea(7),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(7),
WEBWE(2) => web(7),
WEBWE(1) => web(7),
WEBWE(0) => web(7)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(55),
DIADI(6) => dina(54),
DIADI(5) => dina(53),
DIADI(4) => dina(52),
DIADI(3) => dina(51),
DIADI(2) => dina(50),
DIADI(1) => dina(49),
DIADI(0) => dina(48),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(55),
DIBDI(6) => dinb(54),
DIBDI(5) => dinb(53),
DIBDI(4) => dinb(52),
DIBDI(3) => dinb(51),
DIBDI(2) => dinb(50),
DIBDI(1) => dinb(49),
DIBDI(0) => dinb(48),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(55),
DOADO(6) => douta(54),
DOADO(5) => douta(53),
DOADO(4) => douta(52),
DOADO(3) => douta(51),
DOADO(2) => douta(50),
DOADO(1) => douta(49),
DOADO(0) => douta(48),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(55),
DOBDO(6) => doutb(54),
DOBDO(5) => doutb(53),
DOBDO(4) => doutb(52),
DOBDO(3) => doutb(51),
DOBDO(2) => doutb(50),
DOBDO(1) => doutb(49),
DOBDO(0) => doutb(48),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(6),
WEA(2) => wea(6),
WEA(1) => wea(6),
WEA(0) => wea(6),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(6),
WEBWE(2) => web(6),
WEBWE(1) => web(6),
WEBWE(0) => web(6)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(47),
DIADI(6) => dina(46),
DIADI(5) => dina(45),
DIADI(4) => dina(44),
DIADI(3) => dina(43),
DIADI(2) => dina(42),
DIADI(1) => dina(41),
DIADI(0) => dina(40),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(47),
DIBDI(6) => dinb(46),
DIBDI(5) => dinb(45),
DIBDI(4) => dinb(44),
DIBDI(3) => dinb(43),
DIBDI(2) => dinb(42),
DIBDI(1) => dinb(41),
DIBDI(0) => dinb(40),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(47),
DOADO(6) => douta(46),
DOADO(5) => douta(45),
DOADO(4) => douta(44),
DOADO(3) => douta(43),
DOADO(2) => douta(42),
DOADO(1) => douta(41),
DOADO(0) => douta(40),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(47),
DOBDO(6) => doutb(46),
DOBDO(5) => doutb(45),
DOBDO(4) => doutb(44),
DOBDO(3) => doutb(43),
DOBDO(2) => doutb(42),
DOBDO(1) => doutb(41),
DOBDO(0) => doutb(40),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(5),
WEA(2) => wea(5),
WEA(1) => wea(5),
WEA(0) => wea(5),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(5),
WEBWE(2) => web(5),
WEBWE(1) => web(5),
WEBWE(0) => web(5)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(39),
DIADI(6) => dina(38),
DIADI(5) => dina(37),
DIADI(4) => dina(36),
DIADI(3) => dina(35),
DIADI(2) => dina(34),
DIADI(1) => dina(33),
DIADI(0) => dina(32),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(39),
DIBDI(6) => dinb(38),
DIBDI(5) => dinb(37),
DIBDI(4) => dinb(36),
DIBDI(3) => dinb(35),
DIBDI(2) => dinb(34),
DIBDI(1) => dinb(33),
DIBDI(0) => dinb(32),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(39),
DOADO(6) => douta(38),
DOADO(5) => douta(37),
DOADO(4) => douta(36),
DOADO(3) => douta(35),
DOADO(2) => douta(34),
DOADO(1) => douta(33),
DOADO(0) => douta(32),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(39),
DOBDO(6) => doutb(38),
DOBDO(5) => doutb(37),
DOBDO(4) => doutb(36),
DOBDO(3) => doutb(35),
DOBDO(2) => doutb(34),
DOBDO(1) => doutb(33),
DOBDO(0) => doutb(32),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(4),
WEA(2) => wea(4),
WEA(1) => wea(4),
WEA(0) => wea(4),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(4),
WEBWE(2) => web(4),
WEBWE(1) => web(4),
WEBWE(0) => web(4)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(31),
DIADI(6) => dina(30),
DIADI(5) => dina(29),
DIADI(4) => dina(28),
DIADI(3) => dina(27),
DIADI(2) => dina(26),
DIADI(1) => dina(25),
DIADI(0) => dina(24),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(31),
DIBDI(6) => dinb(30),
DIBDI(5) => dinb(29),
DIBDI(4) => dinb(28),
DIBDI(3) => dinb(27),
DIBDI(2) => dinb(26),
DIBDI(1) => dinb(25),
DIBDI(0) => dinb(24),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(31),
DOADO(6) => douta(30),
DOADO(5) => douta(29),
DOADO(4) => douta(28),
DOADO(3) => douta(27),
DOADO(2) => douta(26),
DOADO(1) => douta(25),
DOADO(0) => douta(24),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(31),
DOBDO(6) => doutb(30),
DOBDO(5) => doutb(29),
DOBDO(4) => doutb(28),
DOBDO(3) => doutb(27),
DOBDO(2) => doutb(26),
DOBDO(1) => doutb(25),
DOBDO(0) => doutb(24),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(3),
WEA(2) => wea(3),
WEA(1) => wea(3),
WEA(0) => wea(3),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(3),
WEBWE(2) => web(3),
WEBWE(1) => web(3),
WEBWE(0) => web(3)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(23),
DIADI(6) => dina(22),
DIADI(5) => dina(21),
DIADI(4) => dina(20),
DIADI(3) => dina(19),
DIADI(2) => dina(18),
DIADI(1) => dina(17),
DIADI(0) => dina(16),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(23),
DIBDI(6) => dinb(22),
DIBDI(5) => dinb(21),
DIBDI(4) => dinb(20),
DIBDI(3) => dinb(19),
DIBDI(2) => dinb(18),
DIBDI(1) => dinb(17),
DIBDI(0) => dinb(16),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(23),
DOADO(6) => douta(22),
DOADO(5) => douta(21),
DOADO(4) => douta(20),
DOADO(3) => douta(19),
DOADO(2) => douta(18),
DOADO(1) => douta(17),
DOADO(0) => douta(16),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(23),
DOBDO(6) => doutb(22),
DOBDO(5) => doutb(21),
DOBDO(4) => doutb(20),
DOBDO(3) => doutb(19),
DOBDO(2) => doutb(18),
DOBDO(1) => doutb(17),
DOBDO(0) => doutb(16),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(2),
WEA(2) => wea(2),
WEA(1) => wea(2),
WEA(0) => wea(2),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(2),
WEBWE(2) => web(2),
WEBWE(1) => web(2),
WEBWE(0) => web(2)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(15),
DIADI(6) => dina(14),
DIADI(5) => dina(13),
DIADI(4) => dina(12),
DIADI(3) => dina(11),
DIADI(2) => dina(10),
DIADI(1) => dina(9),
DIADI(0) => dina(8),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(15),
DIBDI(6) => dinb(14),
DIBDI(5) => dinb(13),
DIBDI(4) => dinb(12),
DIBDI(3) => dinb(11),
DIBDI(2) => dinb(10),
DIBDI(1) => dinb(9),
DIBDI(0) => dinb(8),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(15),
DOADO(6) => douta(14),
DOADO(5) => douta(13),
DOADO(4) => douta(12),
DOADO(3) => douta(11),
DOADO(2) => douta(10),
DOADO(1) => douta(9),
DOADO(0) => douta(8),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(15),
DOBDO(6) => doutb(14),
DOBDO(5) => doutb(13),
DOBDO(4) => doutb(12),
DOBDO(3) => doutb(11),
DOBDO(2) => doutb(10),
DOBDO(1) => doutb(9),
DOBDO(0) => doutb(8),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(1),
WEA(2) => wea(1),
WEA(1) => wea(1),
WEA(0) => wea(1),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(1),
WEBWE(2) => web(1),
WEBWE(1) => web(1),
WEBWE(0) => web(1)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(7),
DIADI(6) => dina(6),
DIADI(5) => dina(5),
DIADI(4) => dina(4),
DIADI(3) => dina(3),
DIADI(2) => dina(2),
DIADI(1) => dina(1),
DIADI(0) => dina(0),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(7),
DIBDI(6) => dinb(6),
DIBDI(5) => dinb(5),
DIBDI(4) => dinb(4),
DIBDI(3) => dinb(3),
DIBDI(2) => dinb(2),
DIBDI(1) => dinb(1),
DIBDI(0) => dinb(0),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(7),
DOADO(6) => douta(6),
DOADO(5) => douta(5),
DOADO(4) => douta(4),
DOADO(3) => douta(3),
DOADO(2) => douta(2),
DOADO(1) => douta(1),
DOADO(0) => douta(0),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(7),
DOBDO(6) => doutb(6),
DOBDO(5) => doutb(5),
DOBDO(4) => doutb(4),
DOBDO(3) => doutb(3),
DOBDO(2) => doutb(2),
DOBDO(1) => doutb(1),
DOBDO(0) => doutb(0),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
-- synthesis translate_on
|
lgpl-3.0
|
Ttl/bf_cpu
|
testbenches/cpu_mandelbrot.vhd
|
1
|
3049
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
ENTITY cpu_mandelbrot_tb IS
END cpu_mandelbrot_tb;
ARCHITECTURE behavior OF cpu_mandelbrot_tb IS
signal clk, reset, tx, rx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
signal uart_tx_req, uart_tx_end, uart_rx_ready : std_logic;
signal uart_tx_data, uart_rx_data : std_logic_vector(7 downto 0);
type testvectors is array(0 to 6191) of std_logic_vector(7 downto 0);
impure function init_mem(mif_file_name : in string) return testvectors is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(7 downto 0);
variable temp_mem : testvectors;
begin
for j in 0 to testvectors'length-1 loop
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(j) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
signal vectors : testvectors := init_mem("testbenches/mandelbrot.mif");
BEGIN
-- Component Instantiation
uut: entity work.cpu
Generic map ( INSTRUCTIONS => "scripts/mandelbrot.mif"
)
Port map(clk => clk,
reset => reset,
tx => rx,
rx => tx
);
uart1 : entity work.uart
Generic map(
CLK_FREQ => 100,
SER_FREQ => 1000000,
PARITY_BIT => false
)
Port map (
clk => clk,
rst => reset,
rx => rx,
tx => tx,
tx_req => uart_tx_req,
tx_end => uart_tx_end,
tx_data => uart_tx_data,
rx_ready => uart_rx_ready,
rx_data => uart_rx_data
);
-- Print received bytes
uart_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
if to_integer(unsigned(uart_rx_data)) > 31 and to_integer(unsigned(uart_rx_data)) < 127 then
report "Received ASCII: "&character'image(character'val(to_integer(unsigned(uart_rx_data))));
else
report "Received Dec: "&integer'image(to_integer(unsigned(uart_rx_data)));
end if;
end process;
-- Test received bytes
test_process : process
begin
for i in 0 to 6191 loop
wait until uart_rx_ready = '1';
wait for clk_period;
assert uart_rx_data = vectors(i) report "Message "&integer'image(i)&" incorrect" severity note;
end loop;
wait until uart_rx_ready = '1';
assert false report "Received too many messages" severity failure;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
reset <= '1';
uart_tx_req <= '0';
wait for 100 ns; -- wait until global set/reset completes
reset <= '0';
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
lgpl-3.0
|
Ttl/bf_cpu
|
testbenches/cpu_rot13_tb.vhd
|
1
|
2610
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
ENTITY cpu_rot13_tb IS
END cpu_rot13_tb;
ARCHITECTURE behavior OF cpu_rot13_tb IS
signal clk, reset, tx, rx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
signal uart_tx_req, uart_tx_end, uart_rx_ready : std_logic;
signal uart_tx_data, uart_rx_data : std_logic_vector(7 downto 0);
BEGIN
-- Component Instantiation
uut: entity work.cpu
Generic map ( INSTRUCTIONS => "scripts/rot13.mif"
)
Port map(clk => clk,
reset => reset,
tx => rx,
rx => tx
);
uart1 : entity work.uart
Generic map(
CLK_FREQ => 100,
SER_FREQ => 1000000,
PARITY_BIT => false
)
Port map (
clk => clk,
rst => reset,
rx => rx,
tx => tx,
tx_req => uart_tx_req,
tx_end => uart_tx_end,
tx_data => uart_tx_data,
rx_ready => uart_rx_ready,
rx_data => uart_rx_data
);
-- Print received bytes
uart_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
if to_integer(unsigned(uart_rx_data)) > 31 and to_integer(unsigned(uart_rx_data)) < 127 then
report "Received ASCII: "&character'image(character'val(to_integer(unsigned(uart_rx_data))));
else
report "Received Dec: "&integer'image(to_integer(unsigned(uart_rx_data)));
end if;
end process;
-- Test received bytes
test_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
assert uart_rx_data = x"4E" report "First msg incorrect" severity failure;
wait until uart_rx_ready = '1';
assert false report "Received too many messages" severity failure;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
reset <= '1';
uart_tx_req <= '0';
wait for 100 ns; -- wait until global set/reset completes
reset <= '0';
-- Send character
uart_tx_req <= '1';
uart_tx_data <= x"41"; -- A
wait for clk_period;
uart_tx_req <= '0';
wait until uart_tx_end = '1';
wait for 1999us;
assert uart_rx_data /= x"4E" report "Completed succesfully" severity failure;
assert false report "Invalid rx_data" severity failure;
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
lgpl-3.0
|
Ttl/bf_cpu
|
testbenches/cache_tb.vhd
|
1
|
3499
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cache_tb IS
END cache_tb;
ARCHITECTURE behavior OF cache_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cache
Generic (WIDTH : natural := 13; -- Length of address
DWIDTH : natural := 13; -- Length of one entry
ADR_LENGTH : natural := 4); -- Log2 of number of entries in the cache
PORT(
clk : IN std_logic;
reset : IN std_logic;
addr : IN std_logic_vector(12 downto 0);
din : IN std_logic_vector(12 downto 0);
push : IN std_logic;
valid : OUT std_logic;
dout : OUT std_logic_vector(12 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal addr : std_logic_vector(12 downto 0) := (others => '0');
signal din : std_logic_vector(12 downto 0) := (others => '0');
signal push : std_logic := '0';
--Outputs
signal valid : std_logic;
signal dout : std_logic_vector(12 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cache
Generic map (WIDTH => 13, -- Length of address
DWIDTH => 13, -- Length of one entry
ADR_LENGTH => 4) -- Log2 of number of entries in the cache
PORT MAP (
clk => clk,
reset => reset,
addr => addr,
din => din,
push => push,
valid => valid,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
addr <= (others => '0');
din <= "0000000000001";
-- Write one entry
push <= '1';
-- Check that valid is zero
assert valid = '0' report "valid not zero" severity failure;
wait for clk_period;
push <= '0'; -- Deassert push
wait for clk_period;
-- Test correctness
assert valid = '1' report "valid not one" severity failure;
assert dout = "0000000000001" report "Output invalid" severity failure;
-- Set addr and din for new entry
addr <= (1 => '1', others => '0');
din <= "1111111111111";
wait for clk_period;
-- Add second entry
push <= '1';
assert valid = '0' report "valid not zero" severity failure;
wait for clk_period;
push <= '0'; -- Deassert push
wait for clk_period;
-- Test correctness
assert valid = '1' report "valid not one" severity failure;
assert dout = "1111111111111" report "Output invalid" severity failure;
-- Test correctness of the first entry
addr <= (others => '0');
wait for clk_period;
assert valid = '1' report "valid not one" severity failure;
assert dout = "0000000000001" report "Output invalid" severity failure;
-- Try addr with lower bits same
addr <= "1000000000000";
wait for clk_period;
assert valid = '0' report "valid not zero, different tag bits test" severity failure;
wait for clk_period;
assert false report "Completed succesfully" severity failure;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
Ttl/bf_cpu
|
config.vhd
|
1
|
464
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package bfconfig is
-- Sizes are log2 of full sizes
constant INST_MEM_SIZE : integer := 14;
constant JUMPF_CACHE_SIZE : integer := 3;
constant STACK_SIZE : integer := 8;
constant REG_SIZE : integer := 9;
subtype pctype is std_logic_vector(INST_MEM_SIZE-1 downto 0);
subtype pointertype is std_logic_vector(REG_SIZE-1 downto 0);
end bfconfig;
package body bfconfig is
end bfconfig;
|
lgpl-3.0
|
Ttl/bf_cpu
|
memory.vhd
|
1
|
1451
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bfconfig.all;
use std.textio.all;
entity memory is
Generic (
CONTENTS : string := "scripts/instructions.mif"
);
Port ( clk : in STD_LOGIC;
a1 : in pctype;
wd : in STD_LOGIC_VECTOR (7 downto 0);
d1 : out STD_LOGIC_VECTOR (7 downto 0);
we : in STD_LOGIC);
end memory;
architecture Behavioral of memory is
type memtype is array(0 to 2**INST_MEM_SIZE-1) of std_logic_vector(7 downto 0);
impure function init_mem(mif_file_name : in string) return memtype is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(7 downto 0);
variable temp_mem : memtype;
variable i : integer := 0;
begin
for j in 0 to memtype'length-1 loop
if not endfile(mif_file) then
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(j) := to_stdlogicvector(temp_bv);
else
temp_mem(j) := (others => '0');
end if;
end loop;
return temp_mem;
end function;
signal mem : memtype := init_mem(CONTENTS);
begin
process(clk, we, a1, mem)
begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(unsigned(a1))) <= wd;
end if;
d1 <= mem(to_integer(unsigned(a1)));
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
fpga-logi/logi-hard
|
hdl/virtual_instrument/logi_virtual_pb.vhd
|
2
|
3235
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:18:41 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_pb - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_pb is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
pb : out std_logic_vector(15 downto 0)
);
end logi_virtual_pb;
architecture Behavioral of logi_virtual_pb is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
pb <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
lgpl-3.0
|
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_fifo.vhd
|
2
|
7007
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth;
BURST_SIZE : positive := 4;
B_THRESHOLD : positive := 4;
A_THRESHOLD : positive := 4;
SYNC_LOGIC_INTERFACE : boolean := false
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
write_fifo, read_fifo : in std_logic ;
fifo_input: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
fifo_output : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
read_fifo_empty, read_fifo_full, read_fifo_threshold : out std_logic ;
write_fifo_empty, write_fifo_full, write_fifo_threshold : out std_logic ;
read_fifo_reset, write_fifo_reset : out std_logic
);
end wishbone_fifo;
architecture RTL of wishbone_fifo is
constant address_space_nbit : integer := MAX((nbit(BURST_SIZE)+1), 3);
signal fifoA_wr, fifoB_rd, resetA, resetB : std_logic ;
signal fifoA_in, fifoB_out : std_logic_vector((WIDTH - 1) downto 0 );
signal nb_availableA, nb_availableB : unsigned((WIDTH - 1) downto 0 );
signal nb_availableA_latched, nb_availableB_latched : std_logic_vector((WIDTH - 1) downto 0 );
signal data_bus_out_t : std_logic_vector((WIDTH - 1) downto 0);
signal write_ack, read_ack : std_logic ;
signal gls_resetn : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data : std_logic_vector(15 downto 0) ;
signal fifo_data : std_logic_vector(15 downto 0) ;
signal data_access : std_logic ;
signal control_space_data_spacen : std_logic ;
begin
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
fifo_A : dp_fifo -- write from bus, read from logic
generic map(N => SIZE , W => WIDTH, SYNC_RD => SYNC_LOGIC_INTERFACE, SYNC_WR => false)
port map(
clk => gls_clk, resetn => gls_resetn , sraz => resetA ,
wr => fifoA_wr, rd => read_fifo,
empty => read_fifo_empty,
full => read_fifo_full ,
data_out => fifo_output ,
data_in => fifoA_in ,
nb_available => nb_availableA(nbit(SIZE) downto 0)
);
fifo_B : dp_fifo -- read from bus, write from logic
generic map(N => SIZE , W => WIDTH, SYNC_WR => SYNC_LOGIC_INTERFACE, SYNC_RD => false)
port map(
clk => gls_clk, resetn => gls_resetn , sraz => resetB ,
wr => write_fifo, rd => fifoB_rd,
empty => write_fifo_empty,
full => write_fifo_full ,
data_out => fifoB_out ,
data_in => fifo_input ,
nb_available => nb_availableB(nbit(SIZE) downto 0)
);
nb_availableB_latched <= std_logic_vector(nb_availableB) ;
nb_availableA_latched <= std_logic_vector(nb_availableA) ;
nb_availableB((WIDTH - 1) downto (nbit(SIZE) + 1)) <= (others => '0') ;
nb_availableA((WIDTH - 1) downto (nbit(SIZE) + 1)) <= (others => '0') ;
control_space_data_spacen <= wbs_address((address_space_nbit-1)) ;
control_data <= std_logic_vector(to_unsigned(SIZE, 16)) when wbs_address(1 downto 0)= "00" else
( nb_availableA_latched) when wbs_address(1 downto 0)= "01" else
( nb_availableB_latched) when wbs_address(1 downto 0)= "10" else
fifoB_out when wbs_address((address_space_nbit-1)) = '1' and wbs_address(1 downto 0)= "11" else -- peek !
(others => '0');
fifo_data <= fifoB_out ;
wbs_readdata <= control_latched when control_space_data_spacen = '1' else
fifo_data ;
fifoB_rd <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
fifoA_wr <= '1' when control_space_data_spacen = '0' and (wbs_strobe and wbs_write and wbs_cycle)= '1' else
'0' ;
resetA <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and control_space_data_spacen = '1' and wbs_address(1 downto 0) = "01" else
'0' ;
resetB <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and control_space_data_spacen = '1' and wbs_address(1 downto 0) = "10" else
'0' ;
read_fifo_reset <= resetA ;
write_fifo_reset <= resetB ;
fifoA_in <= wbs_writedata ;
write_fifo_threshold <= '1' when nb_availableB_latched > B_THRESHOLD else
'0' ;
read_fifo_threshold <= '1' when nb_availableA_latched > A_THRESHOLD else
'0' ;
end RTL;
|
lgpl-3.0
|
lnls-dig/dsp-cores
|
hdl/platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.vhd
|
1
|
1140
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon_4_port.vhd
-- /___/ /\ Timestamp : Fri Jun 13 14:36:17 BRT 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon_4_port IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0);
CONTROL3: inout std_logic_vector(35 downto 0));
END chipscope_icon_4_port;
ARCHITECTURE chipscope_icon_4_port_a OF chipscope_icon_4_port IS
BEGIN
END chipscope_icon_4_port_a;
|
lgpl-3.0
|
lnls-dig/dsp-cores
|
hdl/modules/daphine/daphine.vhd
|
1
|
15883
|
-------------------------------------------------------------------------------
-- Title : Daphine calculator
-- Project :
-------------------------------------------------------------------------------
-- File : daphine.vhd
-- Author : vfinotti
-- Company :
-- Created : 2015-07-01
-- Last update: 2015-07-01
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This module gets a,b,c and d values and calculates X and Y.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-07-01 1.0 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity ds_first_stage is
generic (
g_width : natural := 32
);
port(
a_i : in std_logic_vector(g_width-1 downto 0);
b_i : in std_logic_vector(g_width-1 downto 0);
c_i : in std_logic_vector(g_width-1 downto 0);
d_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
valid_i : in std_logic;
valid_o : out std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
-- q_o : out std_logic_vector(g_width-1 downto 0);
-- sum_o : out std_logic_vector(g_width-1 downto 0)
sum_ac_o : out std_logic_vector(g_width-1 downto 0)
sum_db_o : out std_logic_vector(g_width-1 downto 0)
);
end entity ds_first_stage;
architecture behavioral of ds_first_stage is
signal diff_ac, diff_db : signed(g_width-1 downto 0);
signal sum_ac, sum_db : signed(g_width-1 downto 0);
signal valid_d0 : std_logic := '0';
begin
-- Using these formulas to calculate delta:
-- x = (a-c) + (d-b)
-- y = (a-c) + (d-b)
-- sum_ac = a+c
-- sum_db = d+b
stage1 : process(clk_i)
variable a, b, c, d : signed(g_width-1 downto 0);
begin
-- to avoid multiple stages of combinatorial logic, divide it between difference and sum.
-- Remeber signals are only updated at the end of process
if rising_edge(clk_i) then
if ce_i = '1' then
a := signed(a_i); b := signed(b_i); c := signed(c_i); d := signed(d_i);
-- First cycle
diff_ac <= a - c;
diff_db <= d - b;
sum_ac <= a + c;
sum_db <= d + b;
valid_d0 <= valid_i;
-- Second cycle
x_o <= std_logic_vector(diff_ac + diff_bd);
y_o <= std_logic_vector(diff_ac - diff_bd);
-- q_o <= std_logic_vector(diff_cd - diff_ba);
-- sum_o <= std_logic_vector(sum_ab + sum_cd);
sum_ac_o <= std_logic_vector(sum_ac);
sum_db_o <= std_logic_vector(sum_db);
valid_o <= valid_d0;
end if;
end if;
end process;
end architecture behavioral; --ds_first_stage
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ds_output_stage is
generic (
g_width : natural := 32;
g_k_width : natural := 32
);
port(
x_i : in std_logic_vector(g_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
x_valid_i : in std_logic;
y_i : in std_logic_vector(g_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
y_valid_i : in std_logic;
-- q_i : in std_logic_vector(g_width-1 downto 0);
-- q_valid_i : in std_logic;
-- sum_i : in std_logic_vector(g_width-1 downto 0);
-- ksum_i : in std_logic_vector(g_k_width-1 downto 0);
-- sum_valid_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
-- q_o : out std_logic_vector(g_width-1 downto 0);
-- sum_o : out std_logic_vector(g_width-1 downto 0);
sum_ac_o : out std_logic_vector(g_width-1 downto 0);
sum_db_o : out std_logic_vector(g_width-1 downto 0);
valid_o : out std_logic
);
end entity ds_output_stage;
architecture structural of ds_output_stage is
-- signal x_pre, y_pre, q_pre, sum_pre : std_logic_vector(g_width-1 downto 0);
signal x_pre, y_pre : std_logic_vector(g_width-1 downto 0);
signal valid : std_logic;
-- signal x_ce_valid, y_ce_valid, q_ce_valid, sum_ce_valid : std_logic;
signal x_ce_valid, y_ce_valid : std_logic;
attribute keep : string;
-- attribute keep of x_pre, y_pre, sum_pre : signal is "true";
attribute keep of x_pre, y_pre : signal is "true";
constant c_levels : natural := 7;
component pipeline is
generic (
g_width : natural;
g_depth : natural);
port (
data_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0));
end component pipeline;
component generic_multiplier is
generic (
g_a_width : natural;
g_b_width : natural;
g_signed : boolean;
g_p_width : natural;
g_levels : natural);
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
p_o : out std_logic_vector(g_p_width-1 downto 0);
ce_i : in std_logic;
clk_i : in std_logic;
rst_i : in std_logic);
end component generic_multiplier;
begin
-- Input registers from division
x_ce_valid <= ce_i and x_valid_i;
cmp_x_input : pipeline
generic map (
g_width => g_width,
g_depth => 1)
port map (
data_i => x_i,
clk_i => clk_i,
ce_i => x_ce_valid,
data_o => x_pre);
y_ce_valid <= ce_i and y_valid_i;
cmp_y_input : pipeline
generic map (
g_width => g_width,
g_depth => 1)
port map (
data_i => y_i,
clk_i => clk_i,
ce_i => y_ce_valid,
data_o => y_pre);
-- sum_ce_valid <= ce_i and sum_valid_i;
-- cmp_sum_input : pipeline
-- generic map (
-- g_width => g_width,
-- g_depth => 1)
-- port map (
-- data_i => sum_i,
-- clk_i => clk_i,
-- ce_i => sum_ce_valid,
-- data_o => sum_pre);
-- q_ce_valid <= ce_i and q_valid_i;
-- cmp_q_input : pipeline
-- generic map (
-- g_width => g_width,
-- g_depth => 1)
-- port map (
-- data_i => q_i,
-- clk_i => clk_i,
-- ce_i => q_ce_valid,
-- data_o => q_pre);
-- q is special: it won't be multiplied. So, it must be pipelined to level
-- the delay of the other signals
-- cmp_q_pipe : pipeline
-- generic map (
-- g_width => g_width,
-- g_depth => c_levels+2)
-- port map (
-- data_i => q_pre,
-- clk_i => clk_i,
-- ce_i => ce_i,
-- data_o => q_o);
cmp_mult_x : generic_multiplier
generic map (
g_a_width => g_width,
g_b_width => g_k_width,
g_signed => true,
g_p_width => g_width,
g_levels => c_levels)
port map (
a_i => x_pre,
b_i => kx_i,
p_o => x_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
cmp_mult_y : generic_multiplier
generic map (
g_a_width => g_width,
g_b_width => g_k_width,
g_signed => true,
g_p_width => g_width,
g_levels => c_levels)
port map (
a_i => y_pre,
b_i => ky_i,
p_o => y_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
-- cmp_mult_sum : generic_multiplier
-- generic map (
-- g_a_width => g_width,
-- g_b_width => g_k_width,
-- g_signed => true,
-- g_p_width => g_width,
-- g_levels => c_levels)
-- port map (
-- a_i => sum_pre,
-- b_i => ksum_i,
-- p_o => sum_o,
-- ce_i => ce_i,
-- clk_i => clk_i,
-- rst_i => '0');
-- The valid signal must go through the same number of registers as the other
-- signals, which have the input register and through the ones inside the pipeline
-- cmp_valid_pipe : pipeline
-- generic map (
-- g_width => 1,
-- g_depth => c_levels+3)
-- port map (
-- data_i(0) => q_valid_i,
-- clk_i => clk_i,
-- ce_i => ce_i,
-- data_o(0) => valid_o);
end architecture structural; --ds_output_stage
-------------------------------------------------------------------------------
-- Top level
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity daphine is
generic (
g_width : natural := 32;
g_k_width : natural := 24
);
port (
a_i : in std_logic_vector(g_width-1 downto 0);
b_i : in std_logic_vector(g_width-1 downto 0);
c_i : in std_logic_vector(g_width-1 downto 0);
d_i : in std_logic_vector(g_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
-- ksum_i : in std_logic_vector(g_k_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
valid_o : out std_logic;
rst_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
-- q_o : out std_logic_vector(g_width-1 downto 0);
-- sum_o : out std_logic_vector(g_width-1 downto 0);
sum_ac_o : out std_logic_vector(g_width-1 downto 0);
sum_db_o : out std_logic_vector(g_width-1 downto 0);
);
end entity daphine;
-------------------------------------------------------------------------------
architecture str of daphine is
signal x_pre : std_logic_vector(g_width-1 downto 0);
signal y_pre : std_logic_vector(g_width-1 downto 0);
-- signal q_pre : std_logic_vector(g_width-1 downto 0);
signal sigma_ac : std_logic_vector(g_width-1 downto 0);
signal sigma_db : std_logic_vector(g_width-1 downto 0);
signal x_pos : std_logic_vector(g_width-1 downto 0);
signal x_rdo : std_logic;
signal y_pos : std_logic_vector(g_width-1 downto 0);
signal y_rdo : std_logic;
-- signal q_pos : std_logic_vector(g_width-1 downto 0);
-- signal q_rdo : std_logic;
signal valid_pre : std_logic;
component ds_first_stage is
generic (
g_width : natural);
port (
a_i : in std_logic_vector(g_width-1 downto 0);
b_i : in std_logic_vector(g_width-1 downto 0);
c_i : in std_logic_vector(g_width-1 downto 0);
d_i : in std_logic_vector(g_width-1 downto 0);
clk_i : in std_logic;
valid_i : in std_logic;
valid_o : out std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
-- q_o : out std_logic_vector(g_width-1 downto 0);
-- sum_o : out std_logic_vector(g_width-1 downto 0));
sum_ac_o : out std_logic_vector(g_width-1 downto 0);
sum_db_o : out std_logic_vector(g_width-1 downto 0);
end component ds_first_stage;
component div_fixedpoint is
generic (
G_DATAIN_WIDTH : integer range 2 to 48;
G_PRECISION : integer range 1 to 47);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_PRECISION downto 0);
r_o : out std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic);
end component div_fixedpoint;
component ds_output_stage is
generic (
g_width : natural;
g_k_width : natural);
port (
x_i : in std_logic_vector(g_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
x_valid_i : in std_logic;
y_i : in std_logic_vector(g_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
y_valid_i : in std_logic;
-- q_i : in std_logic_vector(g_width-1 downto 0);
-- q_valid_i : in std_logic;
-- sum_i : in std_logic_vector(g_width-1 downto 0);
-- ksum_i : in std_logic_vector(g_k_width-1 downto 0);
-- sum_valid_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out std_logic_vector(g_width-1 downto 0);
y_o : out std_logic_vector(g_width-1 downto 0);
-- q_o : out std_logic_vector(g_width-1 downto 0);
-- sum_o : out std_logic_vector(g_width-1 downto 0);
sum_ac_o : out std_logic_vector(g_width-1 downto 0);
sum_db_o : out std_logic_vector(g_width-1 downto 0);
valid_o : out std_logic);
end component ds_output_stage;
begin -- architecture str
cmp_first_stage : ds_first_stage
generic map (
g_width => g_width)
port map (
a_i => a_i,
b_i => b_i,
c_i => c_i,
d_i => d_i,
clk_i => clk_i,
valid_i => valid_i,
valid_o => valid_pre,
ce_i => ce_i,
x_o => x_pre,
y_o => y_pre,
-- q_o => q_pre,
-- sum_o => sigma);
sum_ac_o => sigma_ac,
sum_bd_o => sigma_bd);
cmp_divider_x : div_fixedpoint
generic map (
G_DATAIN_WIDTH => g_width,
G_PRECISION => g_width-1)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => x_pre,
d_i => sigma,
q_o => x_pos,
r_o => open,
trg_i => valid_pre,
rdy_o => x_rdo,
err_o => open);
cmp_divider_y : div_fixedpoint
generic map (
G_DATAIN_WIDTH => g_width,
G_PRECISION => g_width-1)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => y_pre,
d_i => sigma,
q_o => y_pos,
r_o => open,
trg_i => valid_pre,
rdy_o => y_rdo,
err_o => open);
-- --cmp_divider_q : div_fixedpoint
-- generic map (
-- G_DATAIN_WIDTH => g_width,
-- G_PRECISION => g_width-1)
-- port map (
-- clk_i => clk_i,
-- rst_i => rst_i,
-- ce_i => ce_i,
-- n_i => q_pre,
-- d_i => sigma,
-- q_o => q_pos,
-- r_o => open,
-- trg_i => valid_pre,
-- rdy_o => q_rdo,
-- err_o => open);
cmp_output_buffer : ds_output_stage
generic map (
g_width => g_width,
g_k_width => g_k_width)
port map (
x_i => x_pos,
kx_i => kx_i,
x_valid_i => x_rdo,
y_i => y_pos,
ky_i => ky_i,
y_valid_i => y_rdo,
-- q_i => q_pos,
-- q_valid_i => q_rdo,
-- sum_i => sigma,
-- ksum_i => ksum_i,
-- sum_valid_i => valid_pre,
clk_i => clk_i,
ce_i => ce_i,
x_o => x_o,
y_o => y_o,
-- q_o => q_o,
-- sum_o => sum_o,
sum_ac_o => sum_ac_o,
sum_db_o => sum_db_o,
valid_o => valid_o);
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
lnls-dig/dsp-cores
|
hdl/modules/counters_gen/counters_gen_pkg.vhd
|
1
|
3323
|
------------------------------------------------------------------------------
-- Title : Simple Position Counters package for debugging
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2017-01-20
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core for generating coutners sync'ed with each incoming data rate.
-- Used for debugging.
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-01-20 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package counters_gen_pkg is
-------------------------------------------------------------------------------
-- Constants declaration
-------------------------------------------------------------------------------
constant c_max_cnt_width : natural := 32;
-------------------------------------------------------------------------------
-- Types declaration
-------------------------------------------------------------------------------
type t_cnt_width_array is array (natural range <>) of natural;
type t_cnt_array is array (natural range <>) of unsigned(c_max_cnt_width-1 downto 0);
-------------------------------------------------------------------------------
-- Defaults
-------------------------------------------------------------------------------
constant c_default_num_counters : natural := 2;
constant c_default_cnt_width : natural := 32;
constant c_default_cnt_width_array : t_cnt_width_array(c_default_num_counters-1 downto 0) := (
c_default_cnt_width, c_default_cnt_width);
-----------------------------
-- Functions declaration
----------------------------
function f_dup_counter_array(cnt : unsigned; num_dups : natural)
return std_logic_vector;
end counters_gen_pkg;
package body counters_gen_pkg is
function f_dup_counter_array(cnt : unsigned; num_dups : natural)
return std_logic_vector
is
constant c_cnt_size : natural := cnt'length;
variable cnt_out : std_logic_vector(c_cnt_size*num_dups-1 downto 0) :=
(others => '0');
variable cnt_slice : std_logic_vector(c_cnt_size-1 downto 0) :=
(others => '0');
begin
assert (num_dups >= 1)
report "[f_dup_counter_array] num_dups must be greater or equal than 1"
severity Failure;
-- Get only the interesting part of input
cnt_slice := std_logic_vector(cnt(c_cnt_size-1 downto 0));
-- Duplicate "num_dups" times the input array
loop_dup : for i in 0 to num_dups-1 loop
cnt_out(c_cnt_size*(i+1)-1 downto c_cnt_size*i) :=
cnt_slice;
end loop;
return cnt_out;
end;
end counters_gen_pkg;
|
lgpl-3.0
|
lnls-dig/dsp-cores
|
hdl/testbench/cic/wb_bpm_swap/bpm_swap/deswap_channels.vhd
|
2
|
2028
|
------------------------------------------------------------------------------
-- Title : BPM RF channels de-swapping
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Swap data channels when the deswap input signal is high; keep
-- channels paths unchanged otherwise.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deswap_channels is
generic(
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
deswap_i : in std_logic;
ch1_i : in std_logic_vector(g_ch_width-1 downto 0);
ch2_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
ch1_o : out std_logic_vector(g_ch_width-1 downto 0);
ch2_o : out std_logic_vector(g_ch_width-1 downto 0);
deswap_o : out std_logic;
ch_valid_o : out std_logic
);
end deswap_channels;
architecture rtl of deswap_channels is
begin
deswap_proc : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
ch1_o <= (others => '0');
ch2_o <= (others => '0');
ch_valid_o <= '0';
else
ch_valid_o <= ch_valid_i;
if (ch_valid_i = '1') then
deswap_o <= deswap_i;
if (deswap_i = '1') then
ch1_o <= ch2_i;
ch2_o <= ch1_i;
else
ch1_o <= ch1_i;
ch2_o <= ch2_i;
end if;
end if;
end if;
end if;
end process deswap_proc;
end;
|
lgpl-3.0
|
lnls-dig/dsp-cores
|
hdl/testbench/divider/div_tb_float.vhd
|
1
|
2478
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.arith_dsp48e.all;
use work.utilities.all;
entity div_tb is
end div_tb;
architecture behavioral of div_tb is
constant C_DATAIN_WIDTH : integer := 27;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal trg : std_logic := '0';
signal n : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal d : std_logic_vector(C_DATAIN_WIDTH-1 downto 0) := (others => '0');
--Outputs
signal q : std_logic_vector(31 downto 0);
signal rdy : std_logic;
signal err : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant TAB : character := ht;
file test_out_data : text open write_mode is "./output.dat";
begin
uut_ieee754_single : div_ieee754_single
generic map
(
G_DATA_WIDTH => C_DATAIN_WIDTH
)
port map
(
clk_i => clk,
rst_i => rst,
n_i => n,
d_i => d,
q_o => q,
trg_i => trg,
rdy_o => rdy,
err_o => err
);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc : process
variable outline : line;
variable i : integer;
begin
rst <= '1';
wait for clk_period*10.5;
rst <= '0';
wait for clk_period*10;
for i in 0 to 5740 loop
n <= std_logic_vector(to_signed((i*i)/10, C_DATAIN_WIDTH));
d <= std_logic_vector(to_signed(32947600, C_DATAIN_WIDTH));
wait for clk_period*1;
write(outline, to_integer(signed(n)));
write(outline, TAB);
write(outline, to_integer(signed(d)));
trg <= '1';
wait for clk_period;
trg <= '0';
wait for clk_period*31;
write(outline, TAB);
write(outline, to_integer(unsigned(q(30 downto 23))));
write(outline, TAB);
if q(31) = '1' then
write(outline, string'("-"));
end if;
write(outline, to_integer(unsigned(q(22 downto 0))));
wait for clk_period*1;
writeline(test_out_data, outline); -- write row to output file
end loop;
assert (false) report "Test finished." severity failure;
wait;
end process;
end;
|
lgpl-3.0
|
lnls-dig/dsp-cores
|
hdl/modules/cic/cic_dyn.vhd
|
1
|
12052
|
-------------------------------------------------------------------------------
-- Title : CIC with dynamically-adjustable decimator
-- Project :
-------------------------------------------------------------------------------
-- File : cic.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-11
-- Last update: 2016-05-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: CIC with dinamically adjustable decimation rate
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-11 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity cic_dyn is
generic (
g_input_width : natural := 16;
g_output_width : natural := 16;
g_stages : natural := 1; -- aka "N"
g_delay : natural := 1; -- aka "M"
g_max_rate : natural := 2048; -- Max decimation rate
g_tag_desync_cnt_width : natural := 14;
g_bus_width : natural := 11; -- Decimation ratio bus width.
g_with_ce_synch : boolean := false;
g_tag_width : natural := 1; -- Input data tag width
g_data_mask_width : natural := 16; -- Input data mask width
g_round_convergent : natural := 0
);
port (
clk_i : in std_logic := '0';
rst_i : in std_logic := '0';
ce_i : in std_logic := '0';
ce_out_i : in std_logic := '0';
valid_i : in std_logic := '0';
data_i : in std_logic_vector(g_input_width-1 downto 0) := (others => '0');
data_tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
data_tag_en_i : in std_logic := '0';
data_tag_desync_cnt_rst_i : in std_logic := '0';
data_tag_desync_cnt_o : out std_logic_vector(g_tag_desync_cnt_width-1 downto 0);
data_mask_num_samples_beg_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
data_mask_num_samples_end_i : in unsigned(g_data_mask_width-1 downto 0) := (others => '0');
data_mask_en_i : in std_logic := '0';
ratio_i : in std_logic_vector(g_bus_width-1 downto 0) := (others => '0');
data_o : out std_logic_vector(g_output_width-1 downto 0) := (others => '0');
valid_o : out std_logic := '0'
);
end entity cic_dyn;
-------------------------------------------------------------------------------
architecture str of cic_dyn is
signal decimation_strobe : std_logic := '0';
signal decimation_strobe_d0 : std_logic := '0';
signal data_out : std_logic_vector(g_output_width-1 downto 0) := (others => '0');
signal valid_out : std_logic := '0';
signal synch_int : std_logic := '0';
signal desync_cnt : unsigned(g_tag_desync_cnt_width-1 downto 0) := (others => '0');
type t_fsm_cic_sync_state is (IDLE, CHECK_SYNC, START_SYNC, SYNCHING);
signal fsm_cic_sync_current_state : t_fsm_cic_sync_state := IDLE;
signal data_mask_en_d0 : std_logic := '0';
signal data_mask_beg_idx : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_end_idx : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal data_mask_counter : unsigned(g_data_mask_width-1 downto 0) :=
to_unsigned(0, g_data_mask_width);
signal valid_d0 : std_logic := '0';
signal data_d0 : std_logic_vector(g_input_width-1 downto 0) := (others => '0');
signal data_tag_input : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal data_tag_d0 : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal data_tag_d1 : std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
signal rst_modules : std_logic := '0';
signal rst_int : std_logic := '0';
signal rst_n_int : std_logic := '0';
signal data_tag_change : std_logic := '0';
signal data_tag_change_d0 : std_logic := '0';
component decimation_strober
generic (
g_maxrate : natural := 2048;
g_bus_width : natural := 11);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
ratio_i : in std_logic_vector(g_bus_width-1 downto 0);
strobe_o : out std_logic);
end component;
begin -- architecture str
-- We don't need CE here as these are user configurable registers. We will have
-- lots of clock cycles anyway
p_data_mask_limits : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
data_mask_beg_idx <= (others => '0');
data_mask_end_idx <= (others => '0');
else
-- Set beginning counter index
data_mask_beg_idx <= data_mask_num_samples_beg_i;
if data_mask_num_samples_beg_i > g_max_rate then
data_mask_beg_idx <= to_unsigned(g_max_rate, data_mask_beg_idx'length);
end if;
-- Set ending counter index
data_mask_end_idx <= g_max_rate - data_mask_num_samples_end_i;
if data_mask_num_samples_end_i > g_max_rate then
data_mask_end_idx <= to_unsigned(0, data_mask_end_idx'length);
end if;
end if;
end if;
end process;
-- Data masking logic
p_data_mask : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
data_mask_counter <= (others => '0');
valid_d0 <= '0';
data_d0 <= (others => '0');
data_mask_en_d0 <= '0';
else
if ce_i = '1' then
if valid_i = '1' then
data_mask_counter <= data_mask_counter + 1;
-- decimation_strobe always happens at g_max_rate clock
-- cycles
if decimation_strobe = '1' then
data_mask_counter <= (others => '0');
data_mask_en_d0 <= data_mask_en_i;
end if;
if data_mask_en_d0 = '1' and
(data_mask_counter < data_mask_beg_idx or
data_mask_counter >= data_mask_end_idx) then
data_d0 <= (others => '0');
else
data_d0 <= data_i;
end if;
end if;
-- We take one clock cycle to detect a transition and act on it.
-- so, delay everyone by this same amount
valid_d0 <= valid_i;
decimation_strobe_d0 <= decimation_strobe;
end if;
end if;
end if;
end process;
data_tag_change <= '1' when data_tag_i /= data_tag_d0 else '0';
data_tag_change_d0 <= '1' when data_tag_d0 /= data_tag_d1 else '0';
p_sync_cic_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
fsm_cic_sync_current_state <= IDLE;
rst_modules <= '0';
desync_cnt <= (others => '0');
data_tag_d0 <= (others => '0');
data_tag_d1 <= (others => '0');
else
if ce_i = '1' then
data_tag_d0 <= data_tag_i;
-- To check for a transition we need another clock cycle. So, use a
-- delayed version of data_tag
data_tag_d1 <= data_tag_d0;
-- Desync clear
if data_tag_desync_cnt_rst_i = '1' then
desync_cnt <= (others => '0');
end if;
-- FSM transitions
case fsm_cic_sync_current_state is
when IDLE =>
-- passthrough
rst_modules <= '0';
-- CIC synchronization is disabled
if data_tag_en_i = '0' then
fsm_cic_sync_current_state <= IDLE;
else
fsm_cic_sync_current_state <= CHECK_SYNC;
end if;
when CHECK_SYNC =>
if data_tag_en_i = '0' then
fsm_cic_sync_current_state <= IDLE;
else
-- when we decimate the CIC, check if the next sample
-- belongs to the next tag. This means that the CIC decimation
-- cycle is synched with the tag
if decimation_strobe = '1' then
-- tag transition
if data_tag_change_d0 = '1' then
-- CIC is synched with tag
fsm_cic_sync_current_state <= CHECK_SYNC;
else
fsm_cic_sync_current_state <= START_SYNC;
end if;
end if;
end if;
when START_SYNC =>
if data_tag_en_i = '0' then
fsm_cic_sync_current_state <= IDLE;
else
rst_modules <= '1';
fsm_cic_sync_current_state <= SYNCHING;
-- count desync occurence
desync_cnt <= desync_cnt + 1;
end if;
when SYNCHING =>
if data_tag_en_i = '0' then
fsm_cic_sync_current_state <= IDLE;
else
-- tag transition
if data_tag_change = '1' then
rst_modules <= '0';
fsm_cic_sync_current_state <= CHECK_SYNC;
end if;
end if;
when others =>
fsm_cic_sync_current_state <= IDLE;
end case;
end if;
end if;
end if;
end process;
data_tag_desync_cnt_o <= std_logic_vector(desync_cnt);
rst_int <= rst_i or rst_modules;
cmp_decimation_strober : decimation_strober
generic map (
g_maxrate => g_max_rate,
g_bus_width => g_bus_width)
port map (
clk_i => clk_i,
rst_i => rst_int,
ce_i => ce_i,
valid_i => valid_d0,
ratio_i => ratio_i,
strobe_o => decimation_strobe);
cmp_cic_decim : cic_decim
generic map (
DATAIN_WIDTH => g_input_width,
DATAOUT_WIDTH => g_output_width,
M => g_delay,
N => g_stages,
MAXRATE => g_max_rate,
BITGROWTH => integer(ceil(real(g_stages)*log2(real(g_delay)*real(g_max_rate)))),
ROUND_CONVERGENT => g_round_convergent)
port map (
clk_i => clk_i,
rst_i => rst_int,
en_i => ce_i,
data_i => data_d0,
data_o => data_out,
act_i => valid_d0,
act_out_i => decimation_strobe_d0,
val_o => valid_out);
gen_with_ce_sync : if g_with_ce_synch generate
cmp_ce_synch : ce_synch
generic map (
g_data_width => g_output_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_in_i => ce_i,
data_i => data_out,
valid_i => valid_out,
ce_out_i => ce_out_i,
data_o => data_o,
valid_o => valid_o);
end generate;
gen_without_ce_sync : if not(g_with_ce_synch) generate
data_o <= data_out;
valid_o <=valid_out;
end generate;
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd
|
1
|
142734
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Position Calculation Core registers
---------------------------------------------------------------------------------------
-- File : wb_pos_calc_regs.vhd
-- Author : auto-generated by wbgen2 from wb_pos_calc_regs.wb
-- Created : Tue Jul 7 10:31:54 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_pos_calc_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
-- This file was hand-modified to add switching tag / data mask
-- at the end of the regsiter file and not in the middle as
-- wbgen2 does
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.pos_calc_wbgen2_pkg.all;
entity wb_pos_calc_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk2x_i : in std_logic;
regs_i : in t_pos_calc_in_registers;
regs_o : out t_pos_calc_out_registers
);
end wb_pos_calc_regs;
architecture syn of wb_pos_calc_regs is
signal pos_calc_ds_tbt_thres_val_int : std_logic_vector(25 downto 0);
signal pos_calc_ds_tbt_thres_val_swb : std_logic ;
signal pos_calc_ds_tbt_thres_val_swb_delay : std_logic ;
signal pos_calc_ds_tbt_thres_val_swb_s0 : std_logic ;
signal pos_calc_ds_tbt_thres_val_swb_s1 : std_logic ;
signal pos_calc_ds_tbt_thres_val_swb_s2 : std_logic ;
signal pos_calc_ds_fofb_thres_val_int : std_logic_vector(25 downto 0);
signal pos_calc_ds_fofb_thres_val_swb : std_logic ;
signal pos_calc_ds_fofb_thres_val_swb_delay : std_logic ;
signal pos_calc_ds_fofb_thres_val_swb_s0 : std_logic ;
signal pos_calc_ds_fofb_thres_val_swb_s1 : std_logic ;
signal pos_calc_ds_fofb_thres_val_swb_s2 : std_logic ;
signal pos_calc_ds_monit_thres_val_int : std_logic_vector(25 downto 0);
signal pos_calc_ds_monit_thres_val_swb : std_logic ;
signal pos_calc_ds_monit_thres_val_swb_delay : std_logic ;
signal pos_calc_ds_monit_thres_val_swb_s0 : std_logic ;
signal pos_calc_ds_monit_thres_val_swb_s1 : std_logic ;
signal pos_calc_ds_monit_thres_val_swb_s2 : std_logic ;
signal pos_calc_kx_val_int : std_logic_vector(24 downto 0);
signal pos_calc_kx_val_swb : std_logic ;
signal pos_calc_kx_val_swb_delay : std_logic ;
signal pos_calc_kx_val_swb_s0 : std_logic ;
signal pos_calc_kx_val_swb_s1 : std_logic ;
signal pos_calc_kx_val_swb_s2 : std_logic ;
signal pos_calc_ky_val_int : std_logic_vector(24 downto 0);
signal pos_calc_ky_val_swb : std_logic ;
signal pos_calc_ky_val_swb_delay : std_logic ;
signal pos_calc_ky_val_swb_s0 : std_logic ;
signal pos_calc_ky_val_swb_s1 : std_logic ;
signal pos_calc_ky_val_swb_s2 : std_logic ;
signal pos_calc_ksum_val_int : std_logic_vector(24 downto 0);
signal pos_calc_ksum_val_swb : std_logic ;
signal pos_calc_ksum_val_swb_delay : std_logic ;
signal pos_calc_ksum_val_swb_s0 : std_logic ;
signal pos_calc_ksum_val_swb_s1 : std_logic ;
signal pos_calc_ksum_val_swb_s2 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr_tbt_ch01_lwb : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr_tbt_ch23_lwb : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr_fofb_ch01_lwb : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr_fofb_ch23_lwb : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr1_monit_cic_lwb : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cic_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr1_monit_cfir_lwb : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr2_monit_pfir_lwb : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_int : std_logic_vector(15 downto 0);
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 : std_logic ;
signal pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 : std_logic ;
signal pos_calc_dsp_err_clr_tbt_int : std_logic ;
signal pos_calc_dsp_err_clr_tbt_int_delay : std_logic ;
signal pos_calc_dsp_err_clr_tbt_sync0 : std_logic ;
signal pos_calc_dsp_err_clr_tbt_sync1 : std_logic ;
signal pos_calc_dsp_err_clr_tbt_sync2 : std_logic ;
signal pos_calc_dsp_err_clr_fofb_int : std_logic ;
signal pos_calc_dsp_err_clr_fofb_int_delay : std_logic ;
signal pos_calc_dsp_err_clr_fofb_sync0 : std_logic ;
signal pos_calc_dsp_err_clr_fofb_sync1 : std_logic ;
signal pos_calc_dsp_err_clr_fofb_sync2 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_int : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_int_delay : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_sync0 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_sync1 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part1_sync2 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_int : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_int_delay : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_sync0 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_sync1 : std_logic ;
signal pos_calc_dsp_err_clr_monit_part2_sync2 : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_int : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_int_delay : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_sync0 : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch0_sync2 : std_logic ;
signal pos_calc_dds_cfg_test_data_int : std_logic ;
signal pos_calc_dds_cfg_test_data_sync0 : std_logic ;
signal pos_calc_dds_cfg_test_data_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_int : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_int_delay : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_sync0 : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch1_sync2 : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_int : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_int_delay : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_sync0 : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch2_sync2 : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_int : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_int_delay : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_sync0 : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_sync1 : std_logic ;
signal pos_calc_dds_cfg_valid_ch3_sync2 : std_logic ;
signal pos_calc_dds_pinc_ch0_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_pinc_ch0_val_swb : std_logic ;
signal pos_calc_dds_pinc_ch0_val_swb_delay : std_logic ;
signal pos_calc_dds_pinc_ch0_val_swb_s0 : std_logic ;
signal pos_calc_dds_pinc_ch0_val_swb_s1 : std_logic ;
signal pos_calc_dds_pinc_ch0_val_swb_s2 : std_logic ;
signal pos_calc_dds_pinc_ch1_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_pinc_ch1_val_swb : std_logic ;
signal pos_calc_dds_pinc_ch1_val_swb_delay : std_logic ;
signal pos_calc_dds_pinc_ch1_val_swb_s0 : std_logic ;
signal pos_calc_dds_pinc_ch1_val_swb_s1 : std_logic ;
signal pos_calc_dds_pinc_ch1_val_swb_s2 : std_logic ;
signal pos_calc_dds_pinc_ch2_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_pinc_ch2_val_swb : std_logic ;
signal pos_calc_dds_pinc_ch2_val_swb_delay : std_logic ;
signal pos_calc_dds_pinc_ch2_val_swb_s0 : std_logic ;
signal pos_calc_dds_pinc_ch2_val_swb_s1 : std_logic ;
signal pos_calc_dds_pinc_ch2_val_swb_s2 : std_logic ;
signal pos_calc_dds_pinc_ch3_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_pinc_ch3_val_swb : std_logic ;
signal pos_calc_dds_pinc_ch3_val_swb_delay : std_logic ;
signal pos_calc_dds_pinc_ch3_val_swb_s0 : std_logic ;
signal pos_calc_dds_pinc_ch3_val_swb_s1 : std_logic ;
signal pos_calc_dds_pinc_ch3_val_swb_s2 : std_logic ;
signal pos_calc_dds_poff_ch0_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_poff_ch0_val_swb : std_logic ;
signal pos_calc_dds_poff_ch0_val_swb_delay : std_logic ;
signal pos_calc_dds_poff_ch0_val_swb_s0 : std_logic ;
signal pos_calc_dds_poff_ch0_val_swb_s1 : std_logic ;
signal pos_calc_dds_poff_ch0_val_swb_s2 : std_logic ;
signal pos_calc_dds_poff_ch1_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_poff_ch1_val_swb : std_logic ;
signal pos_calc_dds_poff_ch1_val_swb_delay : std_logic ;
signal pos_calc_dds_poff_ch1_val_swb_s0 : std_logic ;
signal pos_calc_dds_poff_ch1_val_swb_s1 : std_logic ;
signal pos_calc_dds_poff_ch1_val_swb_s2 : std_logic ;
signal pos_calc_dds_poff_ch2_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_poff_ch2_val_swb : std_logic ;
signal pos_calc_dds_poff_ch2_val_swb_delay : std_logic ;
signal pos_calc_dds_poff_ch2_val_swb_s0 : std_logic ;
signal pos_calc_dds_poff_ch2_val_swb_s1 : std_logic ;
signal pos_calc_dds_poff_ch2_val_swb_s2 : std_logic ;
signal pos_calc_dds_poff_ch3_val_int : std_logic_vector(29 downto 0);
signal pos_calc_dds_poff_ch3_val_swb : std_logic ;
signal pos_calc_dds_poff_ch3_val_swb_delay : std_logic ;
signal pos_calc_dds_poff_ch3_val_swb_s0 : std_logic ;
signal pos_calc_dds_poff_ch3_val_swb_s1 : std_logic ;
signal pos_calc_dds_poff_ch3_val_swb_s2 : std_logic ;
signal pos_calc_ampfifo_monit_rst_n : std_logic ;
signal pos_calc_ampfifo_monit_in_int : std_logic_vector(127 downto 0);
signal pos_calc_ampfifo_monit_out_int : std_logic_vector(127 downto 0);
signal pos_calc_ampfifo_monit_rdreq_int : std_logic ;
signal pos_calc_ampfifo_monit_rdreq_int_d0 : std_logic ;
signal pos_calc_posfifo_monit_rst_n : std_logic ;
signal pos_calc_posfifo_monit_in_int : std_logic_vector(127 downto 0);
signal pos_calc_posfifo_monit_out_int : std_logic_vector(127 downto 0);
signal pos_calc_posfifo_monit_rdreq_int : std_logic ;
signal pos_calc_posfifo_monit_rdreq_int_d0 : std_logic ;
signal pos_calc_ampfifo_monit1_rst_n : std_logic ;
signal pos_calc_ampfifo_monit1_in_int : std_logic_vector(127 downto 0);
signal pos_calc_ampfifo_monit1_out_int : std_logic_vector(127 downto 0);
signal pos_calc_ampfifo_monit1_rdreq_int : std_logic ;
signal pos_calc_ampfifo_monit1_rdreq_int_d0 : std_logic ;
signal pos_calc_posfifo_monit1_rst_n : std_logic ;
signal pos_calc_posfifo_monit1_in_int : std_logic_vector(127 downto 0);
signal pos_calc_posfifo_monit1_out_int : std_logic_vector(127 downto 0);
signal pos_calc_posfifo_monit1_rdreq_int : std_logic ;
signal pos_calc_posfifo_monit1_rdreq_int_d0 : std_logic ;
signal pos_calc_ampfifo_monit_full_int : std_logic ;
signal pos_calc_ampfifo_monit_empty_int : std_logic ;
signal pos_calc_ampfifo_monit_usedw_int : std_logic_vector(3 downto 0);
signal pos_calc_posfifo_monit_full_int : std_logic ;
signal pos_calc_posfifo_monit_empty_int : std_logic ;
signal pos_calc_posfifo_monit_usedw_int : std_logic_vector(3 downto 0);
signal pos_calc_ampfifo_monit1_full_int : std_logic ;
signal pos_calc_ampfifo_monit1_empty_int : std_logic ;
signal pos_calc_ampfifo_monit1_usedw_int : std_logic_vector(3 downto 0);
signal pos_calc_posfifo_monit1_full_int : std_logic ;
signal pos_calc_posfifo_monit1_empty_int : std_logic ;
signal pos_calc_posfifo_monit1_usedw_int : std_logic_vector(3 downto 0);
signal pos_calc_sw_tag_en_int : std_logic ;
signal pos_calc_sw_tag_en_sync0 : std_logic ;
signal pos_calc_sw_tag_en_sync1 : std_logic ;
signal pos_calc_sw_tag_desync_cnt_rst_int : std_logic ;
signal pos_calc_sw_tag_desync_cnt_rst_int_delay : std_logic ;
signal pos_calc_sw_tag_desync_cnt_rst_sync0 : std_logic ;
signal pos_calc_sw_tag_desync_cnt_rst_sync1 : std_logic ;
signal pos_calc_sw_tag_desync_cnt_rst_sync2 : std_logic ;
signal pos_calc_sw_tag_desync_cnt_int : std_logic_vector(13 downto 0);
signal pos_calc_sw_tag_desync_cnt_lwb : std_logic ;
signal pos_calc_sw_tag_desync_cnt_lwb_delay : std_logic ;
signal pos_calc_sw_tag_desync_cnt_lwb_in_progress : std_logic ;
signal pos_calc_sw_tag_desync_cnt_lwb_s0 : std_logic ;
signal pos_calc_sw_tag_desync_cnt_lwb_s1 : std_logic ;
signal pos_calc_sw_tag_desync_cnt_lwb_s2 : std_logic ;
signal pos_calc_sw_data_mask_en_int : std_logic ;
signal pos_calc_sw_data_mask_en_sync0 : std_logic ;
signal pos_calc_sw_data_mask_en_sync1 : std_logic ;
signal pos_calc_sw_data_mask_samples_int : std_logic_vector(15 downto 0);
signal pos_calc_sw_data_mask_samples_swb : std_logic ;
signal pos_calc_sw_data_mask_samples_swb_delay : std_logic ;
signal pos_calc_sw_data_mask_samples_swb_s0 : std_logic ;
signal pos_calc_sw_data_mask_samples_swb_s1 : std_logic ;
signal pos_calc_sw_data_mask_samples_swb_s2 : std_logic ;
signal pos_calc_tbt_tag_en_int : std_logic ;
signal pos_calc_tbt_tag_en_sync0 : std_logic ;
signal pos_calc_tbt_tag_en_sync1 : std_logic ;
signal pos_calc_tbt_tag_dly_int : std_logic_vector(15 downto 0);
signal pos_calc_tbt_tag_dly_swb : std_logic ;
signal pos_calc_tbt_tag_dly_swb_delay : std_logic ;
signal pos_calc_tbt_tag_dly_swb_s0 : std_logic ;
signal pos_calc_tbt_tag_dly_swb_s1 : std_logic ;
signal pos_calc_tbt_tag_dly_swb_s2 : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_rst_int : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_rst_int_delay : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_rst_sync0 : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_rst_sync1 : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_rst_sync2 : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_int : std_logic_vector(13 downto 0);
signal pos_calc_tbt_tag_desync_cnt_lwb : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_lwb_delay : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_lwb_in_progress : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_lwb_s0 : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_lwb_s1 : std_logic ;
signal pos_calc_tbt_tag_desync_cnt_lwb_s2 : std_logic ;
signal pos_calc_tbt_data_mask_ctl_en_int : std_logic ;
signal pos_calc_tbt_data_mask_ctl_en_sync0 : std_logic ;
signal pos_calc_tbt_data_mask_ctl_en_sync1 : std_logic ;
signal pos_calc_tbt_data_mask_samples_beg_int : std_logic_vector(15 downto 0);
signal pos_calc_tbt_data_mask_samples_beg_swb : std_logic ;
signal pos_calc_tbt_data_mask_samples_beg_swb_delay : std_logic ;
signal pos_calc_tbt_data_mask_samples_beg_swb_s0 : std_logic ;
signal pos_calc_tbt_data_mask_samples_beg_swb_s1 : std_logic ;
signal pos_calc_tbt_data_mask_samples_beg_swb_s2 : std_logic ;
signal pos_calc_tbt_data_mask_samples_end_int : std_logic_vector(15 downto 0);
signal pos_calc_tbt_data_mask_samples_end_swb : std_logic ;
signal pos_calc_tbt_data_mask_samples_end_swb_delay : std_logic ;
signal pos_calc_tbt_data_mask_samples_end_swb_s0 : std_logic ;
signal pos_calc_tbt_data_mask_samples_end_swb_s1 : std_logic ;
signal pos_calc_tbt_data_mask_samples_end_swb_s2 : std_logic ;
signal pos_calc_monit1_tag_en_int : std_logic ;
signal pos_calc_monit1_tag_en_sync0 : std_logic ;
signal pos_calc_monit1_tag_en_sync1 : std_logic ;
signal pos_calc_monit1_tag_dly_int : std_logic_vector(15 downto 0);
signal pos_calc_monit1_tag_dly_swb : std_logic ;
signal pos_calc_monit1_tag_dly_swb_delay : std_logic ;
signal pos_calc_monit1_tag_dly_swb_s0 : std_logic ;
signal pos_calc_monit1_tag_dly_swb_s1 : std_logic ;
signal pos_calc_monit1_tag_dly_swb_s2 : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_rst_int : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_rst_int_delay : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_rst_sync0 : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_rst_sync1 : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_rst_sync2 : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_int : std_logic_vector(13 downto 0);
signal pos_calc_monit1_tag_desync_cnt_lwb : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_lwb_delay : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_lwb_in_progress : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_lwb_s0 : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_lwb_s1 : std_logic ;
signal pos_calc_monit1_tag_desync_cnt_lwb_s2 : std_logic ;
signal pos_calc_monit1_data_mask_ctl_en_int : std_logic ;
signal pos_calc_monit1_data_mask_ctl_en_sync0 : std_logic ;
signal pos_calc_monit1_data_mask_ctl_en_sync1 : std_logic ;
signal pos_calc_monit1_data_mask_samples_beg_int : std_logic_vector(15 downto 0);
signal pos_calc_monit1_data_mask_samples_beg_swb : std_logic ;
signal pos_calc_monit1_data_mask_samples_beg_swb_delay : std_logic ;
signal pos_calc_monit1_data_mask_samples_beg_swb_s0 : std_logic ;
signal pos_calc_monit1_data_mask_samples_beg_swb_s1 : std_logic ;
signal pos_calc_monit1_data_mask_samples_beg_swb_s2 : std_logic ;
signal pos_calc_monit1_data_mask_samples_end_int : std_logic_vector(15 downto 0);
signal pos_calc_monit1_data_mask_samples_end_swb : std_logic ;
signal pos_calc_monit1_data_mask_samples_end_swb_delay : std_logic ;
signal pos_calc_monit1_data_mask_samples_end_swb_s0 : std_logic ;
signal pos_calc_monit1_data_mask_samples_end_swb_s1 : std_logic ;
signal pos_calc_monit1_data_mask_samples_end_swb_s2 : std_logic ;
signal pos_calc_monit_tag_en_int : std_logic ;
signal pos_calc_monit_tag_en_sync0 : std_logic ;
signal pos_calc_monit_tag_en_sync1 : std_logic ;
signal pos_calc_monit_tag_dly_int : std_logic_vector(15 downto 0);
signal pos_calc_monit_tag_dly_swb : std_logic ;
signal pos_calc_monit_tag_dly_swb_delay : std_logic ;
signal pos_calc_monit_tag_dly_swb_s0 : std_logic ;
signal pos_calc_monit_tag_dly_swb_s1 : std_logic ;
signal pos_calc_monit_tag_dly_swb_s2 : std_logic ;
signal pos_calc_monit_tag_desync_cnt_rst_int : std_logic ;
signal pos_calc_monit_tag_desync_cnt_rst_int_delay : std_logic ;
signal pos_calc_monit_tag_desync_cnt_rst_sync0 : std_logic ;
signal pos_calc_monit_tag_desync_cnt_rst_sync1 : std_logic ;
signal pos_calc_monit_tag_desync_cnt_rst_sync2 : std_logic ;
signal pos_calc_monit_tag_desync_cnt_int : std_logic_vector(13 downto 0);
signal pos_calc_monit_tag_desync_cnt_lwb : std_logic ;
signal pos_calc_monit_tag_desync_cnt_lwb_delay : std_logic ;
signal pos_calc_monit_tag_desync_cnt_lwb_in_progress : std_logic ;
signal pos_calc_monit_tag_desync_cnt_lwb_s0 : std_logic ;
signal pos_calc_monit_tag_desync_cnt_lwb_s1 : std_logic ;
signal pos_calc_monit_tag_desync_cnt_lwb_s2 : std_logic ;
signal pos_calc_monit_data_mask_ctl_en_int : std_logic ;
signal pos_calc_monit_data_mask_ctl_en_sync0 : std_logic ;
signal pos_calc_monit_data_mask_ctl_en_sync1 : std_logic ;
signal pos_calc_monit_data_mask_samples_beg_int : std_logic_vector(15 downto 0);
signal pos_calc_monit_data_mask_samples_beg_swb : std_logic ;
signal pos_calc_monit_data_mask_samples_beg_swb_delay : std_logic ;
signal pos_calc_monit_data_mask_samples_beg_swb_s0 : std_logic ;
signal pos_calc_monit_data_mask_samples_beg_swb_s1 : std_logic ;
signal pos_calc_monit_data_mask_samples_beg_swb_s2 : std_logic ;
signal pos_calc_monit_data_mask_samples_end_int : std_logic_vector(15 downto 0);
signal pos_calc_monit_data_mask_samples_end_swb : std_logic ;
signal pos_calc_monit_data_mask_samples_end_swb_delay : std_logic ;
signal pos_calc_monit_data_mask_samples_end_swb_s0 : std_logic ;
signal pos_calc_monit_data_mask_samples_end_swb_s1 : std_logic ;
signal pos_calc_monit_data_mask_samples_end_swb_s2 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(6 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pos_calc_ds_tbt_thres_val_int <= "00000000000000000000000000";
pos_calc_ds_tbt_thres_val_swb <= '0';
pos_calc_ds_tbt_thres_val_swb_delay <= '0';
pos_calc_ds_fofb_thres_val_int <= "00000000000000000000000000";
pos_calc_ds_fofb_thres_val_swb <= '0';
pos_calc_ds_fofb_thres_val_swb_delay <= '0';
pos_calc_ds_monit_thres_val_int <= "00000000000000000000000000";
pos_calc_ds_monit_thres_val_swb <= '0';
pos_calc_ds_monit_thres_val_swb_delay <= '0';
pos_calc_kx_val_int <= "0000000000000000000000000";
pos_calc_kx_val_swb <= '0';
pos_calc_kx_val_swb_delay <= '0';
pos_calc_ky_val_int <= "0000000000000000000000000";
pos_calc_ky_val_swb <= '0';
pos_calc_ky_val_swb_delay <= '0';
pos_calc_ksum_val_int <= "0000000000000000000000000";
pos_calc_ksum_val_swb <= '0';
pos_calc_ksum_val_swb_delay <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '0';
pos_calc_dsp_err_clr_tbt_int <= '0';
pos_calc_dsp_err_clr_tbt_int_delay <= '0';
pos_calc_dsp_err_clr_fofb_int <= '0';
pos_calc_dsp_err_clr_fofb_int_delay <= '0';
pos_calc_dsp_err_clr_monit_part1_int <= '0';
pos_calc_dsp_err_clr_monit_part1_int_delay <= '0';
pos_calc_dsp_err_clr_monit_part2_int <= '0';
pos_calc_dsp_err_clr_monit_part2_int_delay <= '0';
pos_calc_dds_cfg_valid_ch0_int <= '0';
pos_calc_dds_cfg_valid_ch0_int_delay <= '0';
pos_calc_dds_cfg_test_data_int <= '0';
pos_calc_dds_cfg_valid_ch1_int <= '0';
pos_calc_dds_cfg_valid_ch1_int_delay <= '0';
pos_calc_dds_cfg_valid_ch2_int <= '0';
pos_calc_dds_cfg_valid_ch2_int_delay <= '0';
pos_calc_dds_cfg_valid_ch3_int <= '0';
pos_calc_dds_cfg_valid_ch3_int_delay <= '0';
pos_calc_dds_pinc_ch0_val_int <= "000000000000000000000000000000";
pos_calc_dds_pinc_ch0_val_swb <= '0';
pos_calc_dds_pinc_ch0_val_swb_delay <= '0';
pos_calc_dds_pinc_ch1_val_int <= "000000000000000000000000000000";
pos_calc_dds_pinc_ch1_val_swb <= '0';
pos_calc_dds_pinc_ch1_val_swb_delay <= '0';
pos_calc_dds_pinc_ch2_val_int <= "000000000000000000000000000000";
pos_calc_dds_pinc_ch2_val_swb <= '0';
pos_calc_dds_pinc_ch2_val_swb_delay <= '0';
pos_calc_dds_pinc_ch3_val_int <= "000000000000000000000000000000";
pos_calc_dds_pinc_ch3_val_swb <= '0';
pos_calc_dds_pinc_ch3_val_swb_delay <= '0';
pos_calc_dds_poff_ch0_val_int <= "000000000000000000000000000000";
pos_calc_dds_poff_ch0_val_swb <= '0';
pos_calc_dds_poff_ch0_val_swb_delay <= '0';
pos_calc_dds_poff_ch1_val_int <= "000000000000000000000000000000";
pos_calc_dds_poff_ch1_val_swb <= '0';
pos_calc_dds_poff_ch1_val_swb_delay <= '0';
pos_calc_dds_poff_ch2_val_int <= "000000000000000000000000000000";
pos_calc_dds_poff_ch2_val_swb <= '0';
pos_calc_dds_poff_ch2_val_swb_delay <= '0';
pos_calc_dds_poff_ch3_val_int <= "000000000000000000000000000000";
pos_calc_dds_poff_ch3_val_swb <= '0';
pos_calc_dds_poff_ch3_val_swb_delay <= '0';
regs_o.dsp_monit_updt_wr_o <= '0';
regs_o.dsp_monit1_updt_wr_o <= '0';
pos_calc_ampfifo_monit_rdreq_int <= '0';
pos_calc_posfifo_monit_rdreq_int <= '0';
pos_calc_ampfifo_monit1_rdreq_int <= '0';
pos_calc_posfifo_monit1_rdreq_int <= '0';
pos_calc_sw_tag_en_int <= '0';
pos_calc_sw_tag_desync_cnt_rst_int <= '0';
pos_calc_sw_tag_desync_cnt_rst_int_delay <= '0';
pos_calc_sw_tag_desync_cnt_lwb <= '0';
pos_calc_sw_tag_desync_cnt_lwb_delay <= '0';
pos_calc_sw_tag_desync_cnt_lwb_in_progress <= '0';
pos_calc_sw_data_mask_en_int <= '0';
pos_calc_sw_data_mask_samples_int <= "0000000000000000";
pos_calc_sw_data_mask_samples_swb <= '0';
pos_calc_sw_data_mask_samples_swb_delay <= '0';
pos_calc_tbt_tag_en_int <= '0';
pos_calc_tbt_tag_dly_int <= "0000000000000000";
pos_calc_tbt_tag_dly_swb <= '0';
pos_calc_tbt_tag_dly_swb_delay <= '0';
pos_calc_tbt_tag_desync_cnt_rst_int <= '0';
pos_calc_tbt_tag_desync_cnt_rst_int_delay <= '0';
pos_calc_tbt_tag_desync_cnt_lwb <= '0';
pos_calc_tbt_tag_desync_cnt_lwb_delay <= '0';
pos_calc_tbt_tag_desync_cnt_lwb_in_progress <= '0';
pos_calc_tbt_data_mask_ctl_en_int <= '0';
pos_calc_tbt_data_mask_samples_beg_int <= "0000000000000000";
pos_calc_tbt_data_mask_samples_beg_swb <= '0';
pos_calc_tbt_data_mask_samples_beg_swb_delay <= '0';
pos_calc_tbt_data_mask_samples_end_int <= "0000000000000000";
pos_calc_tbt_data_mask_samples_end_swb <= '0';
pos_calc_tbt_data_mask_samples_end_swb_delay <= '0';
pos_calc_monit1_tag_en_int <= '0';
pos_calc_monit1_tag_dly_int <= "0000000000000000";
pos_calc_monit1_tag_dly_swb <= '0';
pos_calc_monit1_tag_dly_swb_delay <= '0';
pos_calc_monit1_tag_desync_cnt_rst_int <= '0';
pos_calc_monit1_tag_desync_cnt_rst_int_delay <= '0';
pos_calc_monit1_tag_desync_cnt_lwb <= '0';
pos_calc_monit1_tag_desync_cnt_lwb_delay <= '0';
pos_calc_monit1_tag_desync_cnt_lwb_in_progress <= '0';
pos_calc_monit1_data_mask_ctl_en_int <= '0';
pos_calc_monit1_data_mask_samples_beg_int <= "0000000000000000";
pos_calc_monit1_data_mask_samples_beg_swb <= '0';
pos_calc_monit1_data_mask_samples_beg_swb_delay <= '0';
pos_calc_monit1_data_mask_samples_end_int <= "0000000000000000";
pos_calc_monit1_data_mask_samples_end_swb <= '0';
pos_calc_monit1_data_mask_samples_end_swb_delay <= '0';
pos_calc_monit_tag_en_int <= '0';
pos_calc_monit_tag_dly_int <= "0000000000000000";
pos_calc_monit_tag_dly_swb <= '0';
pos_calc_monit_tag_dly_swb_delay <= '0';
pos_calc_monit_tag_desync_cnt_rst_int <= '0';
pos_calc_monit_tag_desync_cnt_rst_int_delay <= '0';
pos_calc_monit_tag_desync_cnt_lwb <= '0';
pos_calc_monit_tag_desync_cnt_lwb_delay <= '0';
pos_calc_monit_tag_desync_cnt_lwb_in_progress <= '0';
pos_calc_monit_data_mask_ctl_en_int <= '0';
pos_calc_monit_data_mask_samples_beg_int <= "0000000000000000";
pos_calc_monit_data_mask_samples_beg_swb <= '0';
pos_calc_monit_data_mask_samples_beg_swb_delay <= '0';
pos_calc_monit_data_mask_samples_end_int <= "0000000000000000";
pos_calc_monit_data_mask_samples_end_swb <= '0';
pos_calc_monit_data_mask_samples_end_swb_delay <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.dsp_monit_updt_wr_o <= '0';
regs_o.dsp_monit1_updt_wr_o <= '0';
ack_in_progress <= '0';
else
pos_calc_ds_tbt_thres_val_swb <= pos_calc_ds_tbt_thres_val_swb_delay;
pos_calc_ds_tbt_thres_val_swb_delay <= '0';
pos_calc_ds_fofb_thres_val_swb <= pos_calc_ds_fofb_thres_val_swb_delay;
pos_calc_ds_fofb_thres_val_swb_delay <= '0';
pos_calc_ds_monit_thres_val_swb <= pos_calc_ds_monit_thres_val_swb_delay;
pos_calc_ds_monit_thres_val_swb_delay <= '0';
pos_calc_kx_val_swb <= pos_calc_kx_val_swb_delay;
pos_calc_kx_val_swb_delay <= '0';
pos_calc_ky_val_swb <= pos_calc_ky_val_swb_delay;
pos_calc_ky_val_swb_delay <= '0';
pos_calc_ksum_val_swb <= pos_calc_ksum_val_swb_delay;
pos_calc_ksum_val_swb_delay <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb <= pos_calc_dsp_ctnr_tbt_ch01_lwb_delay;
pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr_tbt_ch01_int;
pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr_tbt_ch23_lwb <= pos_calc_dsp_ctnr_tbt_ch23_lwb_delay;
pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress = '1')) then
rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr_tbt_ch23_int;
pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr_fofb_ch01_lwb <= pos_calc_dsp_ctnr_fofb_ch01_lwb_delay;
pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr_fofb_ch01_int;
pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr_fofb_ch23_lwb <= pos_calc_dsp_ctnr_fofb_ch23_lwb_delay;
pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress = '1')) then
rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr_fofb_ch23_int;
pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr1_monit_cic_lwb <= pos_calc_dsp_ctnr1_monit_cic_lwb_delay;
pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr1_monit_cic_int;
pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr1_monit_cfir_lwb <= pos_calc_dsp_ctnr1_monit_cfir_lwb_delay;
pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress = '1')) then
rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr1_monit_cfir_int;
pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr2_monit_pfir_lwb <= pos_calc_dsp_ctnr2_monit_pfir_lwb_delay;
pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= pos_calc_dsp_ctnr2_monit_pfir_int;
pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '0';
end if;
pos_calc_dsp_ctnr2_monit_fir_01_lwb <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay;
pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress = '1')) then
rddata_reg(31 downto 16) <= pos_calc_dsp_ctnr2_monit_fir_01_int;
pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '0';
end if;
pos_calc_dsp_err_clr_tbt_int <= pos_calc_dsp_err_clr_tbt_int_delay;
pos_calc_dsp_err_clr_tbt_int_delay <= '0';
pos_calc_dsp_err_clr_fofb_int <= pos_calc_dsp_err_clr_fofb_int_delay;
pos_calc_dsp_err_clr_fofb_int_delay <= '0';
pos_calc_dsp_err_clr_monit_part1_int <= pos_calc_dsp_err_clr_monit_part1_int_delay;
pos_calc_dsp_err_clr_monit_part1_int_delay <= '0';
pos_calc_dsp_err_clr_monit_part2_int <= pos_calc_dsp_err_clr_monit_part2_int_delay;
pos_calc_dsp_err_clr_monit_part2_int_delay <= '0';
pos_calc_dds_cfg_valid_ch0_int <= pos_calc_dds_cfg_valid_ch0_int_delay;
pos_calc_dds_cfg_valid_ch0_int_delay <= '0';
pos_calc_dds_cfg_valid_ch1_int <= pos_calc_dds_cfg_valid_ch1_int_delay;
pos_calc_dds_cfg_valid_ch1_int_delay <= '0';
pos_calc_dds_cfg_valid_ch2_int <= pos_calc_dds_cfg_valid_ch2_int_delay;
pos_calc_dds_cfg_valid_ch2_int_delay <= '0';
pos_calc_dds_cfg_valid_ch3_int <= pos_calc_dds_cfg_valid_ch3_int_delay;
pos_calc_dds_cfg_valid_ch3_int_delay <= '0';
pos_calc_dds_pinc_ch0_val_swb <= pos_calc_dds_pinc_ch0_val_swb_delay;
pos_calc_dds_pinc_ch0_val_swb_delay <= '0';
pos_calc_dds_pinc_ch1_val_swb <= pos_calc_dds_pinc_ch1_val_swb_delay;
pos_calc_dds_pinc_ch1_val_swb_delay <= '0';
pos_calc_dds_pinc_ch2_val_swb <= pos_calc_dds_pinc_ch2_val_swb_delay;
pos_calc_dds_pinc_ch2_val_swb_delay <= '0';
pos_calc_dds_pinc_ch3_val_swb <= pos_calc_dds_pinc_ch3_val_swb_delay;
pos_calc_dds_pinc_ch3_val_swb_delay <= '0';
pos_calc_dds_poff_ch0_val_swb <= pos_calc_dds_poff_ch0_val_swb_delay;
pos_calc_dds_poff_ch0_val_swb_delay <= '0';
pos_calc_dds_poff_ch1_val_swb <= pos_calc_dds_poff_ch1_val_swb_delay;
pos_calc_dds_poff_ch1_val_swb_delay <= '0';
pos_calc_dds_poff_ch2_val_swb <= pos_calc_dds_poff_ch2_val_swb_delay;
pos_calc_dds_poff_ch2_val_swb_delay <= '0';
pos_calc_dds_poff_ch3_val_swb <= pos_calc_dds_poff_ch3_val_swb_delay;
pos_calc_dds_poff_ch3_val_swb_delay <= '0';
regs_o.dsp_monit_updt_wr_o <= '0';
regs_o.dsp_monit1_updt_wr_o <= '0';
pos_calc_sw_tag_desync_cnt_rst_int <= pos_calc_sw_tag_desync_cnt_rst_int_delay;
pos_calc_sw_tag_desync_cnt_rst_int_delay <= '0';
pos_calc_sw_tag_desync_cnt_lwb <= pos_calc_sw_tag_desync_cnt_lwb_delay;
pos_calc_sw_tag_desync_cnt_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_sw_tag_desync_cnt_lwb_in_progress = '1')) then
rddata_reg(22 downto 9) <= pos_calc_sw_tag_desync_cnt_int;
pos_calc_sw_tag_desync_cnt_lwb_in_progress <= '0';
end if;
pos_calc_sw_data_mask_samples_swb <= pos_calc_sw_data_mask_samples_swb_delay;
pos_calc_sw_data_mask_samples_swb_delay <= '0';
pos_calc_tbt_tag_dly_swb <= pos_calc_tbt_tag_dly_swb_delay;
pos_calc_tbt_tag_dly_swb_delay <= '0';
pos_calc_tbt_tag_desync_cnt_rst_int <= pos_calc_tbt_tag_desync_cnt_rst_int_delay;
pos_calc_tbt_tag_desync_cnt_rst_int_delay <= '0';
pos_calc_tbt_tag_desync_cnt_lwb <= pos_calc_tbt_tag_desync_cnt_lwb_delay;
pos_calc_tbt_tag_desync_cnt_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_tbt_tag_desync_cnt_lwb_in_progress = '1')) then
rddata_reg(31 downto 18) <= pos_calc_tbt_tag_desync_cnt_int;
pos_calc_tbt_tag_desync_cnt_lwb_in_progress <= '0';
end if;
pos_calc_tbt_data_mask_samples_beg_swb <= pos_calc_tbt_data_mask_samples_beg_swb_delay;
pos_calc_tbt_data_mask_samples_beg_swb_delay <= '0';
pos_calc_tbt_data_mask_samples_end_swb <= pos_calc_tbt_data_mask_samples_end_swb_delay;
pos_calc_tbt_data_mask_samples_end_swb_delay <= '0';
pos_calc_monit1_tag_dly_swb <= pos_calc_monit1_tag_dly_swb_delay;
pos_calc_monit1_tag_dly_swb_delay <= '0';
pos_calc_monit1_tag_desync_cnt_rst_int <= pos_calc_monit1_tag_desync_cnt_rst_int_delay;
pos_calc_monit1_tag_desync_cnt_rst_int_delay <= '0';
pos_calc_monit1_tag_desync_cnt_lwb <= pos_calc_monit1_tag_desync_cnt_lwb_delay;
pos_calc_monit1_tag_desync_cnt_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_monit1_tag_desync_cnt_lwb_in_progress = '1')) then
rddata_reg(31 downto 18) <= pos_calc_monit1_tag_desync_cnt_int;
pos_calc_monit1_tag_desync_cnt_lwb_in_progress <= '0';
end if;
pos_calc_monit1_data_mask_samples_beg_swb <= pos_calc_monit1_data_mask_samples_beg_swb_delay;
pos_calc_monit1_data_mask_samples_beg_swb_delay <= '0';
pos_calc_monit1_data_mask_samples_end_swb <= pos_calc_monit1_data_mask_samples_end_swb_delay;
pos_calc_monit1_data_mask_samples_end_swb_delay <= '0';
pos_calc_monit_tag_dly_swb <= pos_calc_monit_tag_dly_swb_delay;
pos_calc_monit_tag_dly_swb_delay <= '0';
pos_calc_monit_tag_desync_cnt_rst_int <= pos_calc_monit_tag_desync_cnt_rst_int_delay;
pos_calc_monit_tag_desync_cnt_rst_int_delay <= '0';
pos_calc_monit_tag_desync_cnt_lwb <= pos_calc_monit_tag_desync_cnt_lwb_delay;
pos_calc_monit_tag_desync_cnt_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (pos_calc_monit_tag_desync_cnt_lwb_in_progress = '1')) then
rddata_reg(31 downto 18) <= pos_calc_monit_tag_desync_cnt_int;
pos_calc_monit_tag_desync_cnt_lwb_in_progress <= '0';
end if;
pos_calc_monit_data_mask_samples_beg_swb <= pos_calc_monit_data_mask_samples_beg_swb_delay;
pos_calc_monit_data_mask_samples_beg_swb_delay <= '0';
pos_calc_monit_data_mask_samples_end_swb <= pos_calc_monit_data_mask_samples_end_swb_delay;
pos_calc_monit_data_mask_samples_end_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(6 downto 0) is
when "0000000" =>
if (wb_we_i = '1') then
pos_calc_ds_tbt_thres_val_int <= wrdata_reg(25 downto 0);
pos_calc_ds_tbt_thres_val_swb <= '1';
pos_calc_ds_tbt_thres_val_swb_delay <= '1';
end if;
rddata_reg(25 downto 0) <= pos_calc_ds_tbt_thres_val_int;
rddata_reg(31 downto 26) <= regs_i.ds_tbt_thres_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0000001" =>
if (wb_we_i = '1') then
pos_calc_ds_fofb_thres_val_int <= wrdata_reg(25 downto 0);
pos_calc_ds_fofb_thres_val_swb <= '1';
pos_calc_ds_fofb_thres_val_swb_delay <= '1';
end if;
rddata_reg(25 downto 0) <= pos_calc_ds_fofb_thres_val_int;
rddata_reg(31 downto 26) <= regs_i.ds_fofb_thres_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0000010" =>
if (wb_we_i = '1') then
pos_calc_ds_monit_thres_val_int <= wrdata_reg(25 downto 0);
pos_calc_ds_monit_thres_val_swb <= '1';
pos_calc_ds_monit_thres_val_swb_delay <= '1';
end if;
rddata_reg(25 downto 0) <= pos_calc_ds_monit_thres_val_int;
rddata_reg(31 downto 26) <= regs_i.ds_monit_thres_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0000011" =>
if (wb_we_i = '1') then
pos_calc_kx_val_int <= wrdata_reg(24 downto 0);
pos_calc_kx_val_swb <= '1';
pos_calc_kx_val_swb_delay <= '1';
end if;
rddata_reg(24 downto 0) <= pos_calc_kx_val_int;
rddata_reg(31 downto 25) <= regs_i.kx_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0000100" =>
if (wb_we_i = '1') then
pos_calc_ky_val_int <= wrdata_reg(24 downto 0);
pos_calc_ky_val_swb <= '1';
pos_calc_ky_val_swb_delay <= '1';
end if;
rddata_reg(24 downto 0) <= pos_calc_ky_val_int;
rddata_reg(31 downto 25) <= regs_i.ky_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0000101" =>
if (wb_we_i = '1') then
pos_calc_ksum_val_int <= wrdata_reg(24 downto 0);
pos_calc_ksum_val_swb <= '1';
pos_calc_ksum_val_swb_delay <= '1';
end if;
rddata_reg(24 downto 0) <= pos_calc_ksum_val_int;
rddata_reg(31 downto 25) <= regs_i.ksum_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0000110" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr_tbt_ch01_lwb <= '1';
pos_calc_dsp_ctnr_tbt_ch01_lwb_delay <= '1';
pos_calc_dsp_ctnr_tbt_ch01_lwb_in_progress <= '1';
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr_tbt_ch23_lwb <= '1';
pos_calc_dsp_ctnr_tbt_ch23_lwb_delay <= '1';
pos_calc_dsp_ctnr_tbt_ch23_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0000111" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr_fofb_ch01_lwb <= '1';
pos_calc_dsp_ctnr_fofb_ch01_lwb_delay <= '1';
pos_calc_dsp_ctnr_fofb_ch01_lwb_in_progress <= '1';
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr_fofb_ch23_lwb <= '1';
pos_calc_dsp_ctnr_fofb_ch23_lwb_delay <= '1';
pos_calc_dsp_ctnr_fofb_ch23_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0001000" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr1_monit_cic_lwb <= '1';
pos_calc_dsp_ctnr1_monit_cic_lwb_delay <= '1';
pos_calc_dsp_ctnr1_monit_cic_lwb_in_progress <= '1';
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr1_monit_cfir_lwb <= '1';
pos_calc_dsp_ctnr1_monit_cfir_lwb_delay <= '1';
pos_calc_dsp_ctnr1_monit_cfir_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0001001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr2_monit_pfir_lwb <= '1';
pos_calc_dsp_ctnr2_monit_pfir_lwb_delay <= '1';
pos_calc_dsp_ctnr2_monit_pfir_lwb_in_progress <= '1';
end if;
if (wb_we_i = '0') then
pos_calc_dsp_ctnr2_monit_fir_01_lwb <= '1';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_delay <= '1';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0001010" =>
if (wb_we_i = '1') then
pos_calc_dsp_err_clr_tbt_int <= wrdata_reg(0);
pos_calc_dsp_err_clr_tbt_int_delay <= wrdata_reg(0);
pos_calc_dsp_err_clr_fofb_int <= wrdata_reg(1);
pos_calc_dsp_err_clr_fofb_int_delay <= wrdata_reg(1);
pos_calc_dsp_err_clr_monit_part1_int <= wrdata_reg(2);
pos_calc_dsp_err_clr_monit_part1_int_delay <= wrdata_reg(2);
pos_calc_dsp_err_clr_monit_part2_int <= wrdata_reg(3);
pos_calc_dsp_err_clr_monit_part2_int_delay <= wrdata_reg(3);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(3) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "0001011" =>
if (wb_we_i = '1') then
pos_calc_dds_cfg_valid_ch0_int <= wrdata_reg(0);
pos_calc_dds_cfg_valid_ch0_int_delay <= wrdata_reg(0);
pos_calc_dds_cfg_test_data_int <= wrdata_reg(1);
pos_calc_dds_cfg_valid_ch1_int <= wrdata_reg(8);
pos_calc_dds_cfg_valid_ch1_int_delay <= wrdata_reg(8);
pos_calc_dds_cfg_valid_ch2_int <= wrdata_reg(16);
pos_calc_dds_cfg_valid_ch2_int_delay <= wrdata_reg(16);
pos_calc_dds_cfg_valid_ch3_int <= wrdata_reg(24);
pos_calc_dds_cfg_valid_ch3_int_delay <= wrdata_reg(24);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= pos_calc_dds_cfg_test_data_int;
rddata_reg(7 downto 2) <= regs_i.dds_cfg_reserved_ch0_i;
rddata_reg(8) <= '0';
rddata_reg(15 downto 9) <= regs_i.dds_cfg_reserved_ch1_i;
rddata_reg(16) <= '0';
rddata_reg(23 downto 17) <= regs_i.dds_cfg_reserved_ch2_i;
rddata_reg(24) <= '0';
rddata_reg(31 downto 25) <= regs_i.dds_cfg_reserved_ch3_i;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "0001100" =>
if (wb_we_i = '1') then
pos_calc_dds_pinc_ch0_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_pinc_ch0_val_swb <= '1';
pos_calc_dds_pinc_ch0_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch0_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_pinc_ch0_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0001101" =>
if (wb_we_i = '1') then
pos_calc_dds_pinc_ch1_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_pinc_ch1_val_swb <= '1';
pos_calc_dds_pinc_ch1_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch1_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_pinc_ch1_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0001110" =>
if (wb_we_i = '1') then
pos_calc_dds_pinc_ch2_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_pinc_ch2_val_swb <= '1';
pos_calc_dds_pinc_ch2_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch2_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_pinc_ch2_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0001111" =>
if (wb_we_i = '1') then
pos_calc_dds_pinc_ch3_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_pinc_ch3_val_swb <= '1';
pos_calc_dds_pinc_ch3_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_pinc_ch3_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_pinc_ch3_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010000" =>
if (wb_we_i = '1') then
pos_calc_dds_poff_ch0_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_poff_ch0_val_swb <= '1';
pos_calc_dds_poff_ch0_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch0_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_poff_ch0_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010001" =>
if (wb_we_i = '1') then
pos_calc_dds_poff_ch1_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_poff_ch1_val_swb <= '1';
pos_calc_dds_poff_ch1_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch1_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_poff_ch1_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010010" =>
if (wb_we_i = '1') then
pos_calc_dds_poff_ch2_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_poff_ch2_val_swb <= '1';
pos_calc_dds_poff_ch2_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch2_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_poff_ch2_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010011" =>
if (wb_we_i = '1') then
pos_calc_dds_poff_ch3_val_int <= wrdata_reg(29 downto 0);
pos_calc_dds_poff_ch3_val_swb <= '1';
pos_calc_dds_poff_ch3_val_swb_delay <= '1';
end if;
rddata_reg(29 downto 0) <= pos_calc_dds_poff_ch3_val_int;
rddata_reg(31 downto 30) <= regs_i.dds_poff_ch3_reserved_i;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit_amp_ch0_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit_amp_ch1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit_amp_ch2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit_amp_ch3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit_pos_x_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit_pos_y_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit_pos_q_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit_pos_sum_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011100" =>
if (wb_we_i = '1') then
regs_o.dsp_monit_updt_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit1_amp_ch0_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit1_amp_ch1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit1_amp_ch2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit1_amp_ch3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit1_pos_x_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit1_pos_y_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit1_pos_q_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dsp_monit1_pos_sum_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100101" =>
if (wb_we_i = '1') then
regs_o.dsp_monit1_updt_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100110" =>
if (wb_we_i = '1') then
end if;
if (pos_calc_ampfifo_monit_rdreq_int_d0 = '0') then
pos_calc_ampfifo_monit_rdreq_int <= not pos_calc_ampfifo_monit_rdreq_int;
else
rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "0100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= pos_calc_ampfifo_monit_full_int;
rddata_reg(17) <= pos_calc_ampfifo_monit_empty_int;
rddata_reg(3 downto 0) <= pos_calc_ampfifo_monit_usedw_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101011" =>
if (wb_we_i = '1') then
end if;
if (pos_calc_posfifo_monit_rdreq_int_d0 = '0') then
pos_calc_posfifo_monit_rdreq_int <= not pos_calc_posfifo_monit_rdreq_int;
else
rddata_reg(31 downto 0) <= pos_calc_posfifo_monit_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "0101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_posfifo_monit_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_posfifo_monit_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_posfifo_monit_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= pos_calc_posfifo_monit_full_int;
rddata_reg(17) <= pos_calc_posfifo_monit_empty_int;
rddata_reg(3 downto 0) <= pos_calc_posfifo_monit_usedw_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110000" =>
if (wb_we_i = '1') then
end if;
if (pos_calc_ampfifo_monit1_rdreq_int_d0 = '0') then
pos_calc_ampfifo_monit1_rdreq_int <= not pos_calc_ampfifo_monit1_rdreq_int;
else
rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit1_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "0110001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit1_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit1_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_ampfifo_monit1_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= pos_calc_ampfifo_monit1_full_int;
rddata_reg(17) <= pos_calc_ampfifo_monit1_empty_int;
rddata_reg(3 downto 0) <= pos_calc_ampfifo_monit1_usedw_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110101" =>
if (wb_we_i = '1') then
end if;
if (pos_calc_posfifo_monit1_rdreq_int_d0 = '0') then
pos_calc_posfifo_monit1_rdreq_int <= not pos_calc_posfifo_monit1_rdreq_int;
else
rddata_reg(31 downto 0) <= pos_calc_posfifo_monit1_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "0110110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_posfifo_monit1_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_posfifo_monit1_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pos_calc_posfifo_monit1_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= pos_calc_posfifo_monit1_full_int;
rddata_reg(17) <= pos_calc_posfifo_monit1_empty_int;
rddata_reg(3 downto 0) <= pos_calc_posfifo_monit1_usedw_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111010" =>
if (wb_we_i = '1') then
pos_calc_sw_tag_en_int <= wrdata_reg(0);
pos_calc_sw_tag_desync_cnt_rst_int <= wrdata_reg(8);
pos_calc_sw_tag_desync_cnt_rst_int_delay <= wrdata_reg(8);
end if;
rddata_reg(0) <= pos_calc_sw_tag_en_int;
rddata_reg(8) <= '0';
if (wb_we_i = '0') then
pos_calc_sw_tag_desync_cnt_lwb <= '1';
pos_calc_sw_tag_desync_cnt_lwb_delay <= '1';
pos_calc_sw_tag_desync_cnt_lwb_in_progress <= '1';
end if;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0111011" =>
if (wb_we_i = '1') then
pos_calc_sw_data_mask_en_int <= wrdata_reg(0);
pos_calc_sw_data_mask_samples_int <= wrdata_reg(16 downto 1);
pos_calc_sw_data_mask_samples_swb <= '1';
pos_calc_sw_data_mask_samples_swb_delay <= '1';
end if;
rddata_reg(0) <= pos_calc_sw_data_mask_en_int;
rddata_reg(16 downto 1) <= pos_calc_sw_data_mask_samples_int;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0111100" =>
if (wb_we_i = '1') then
pos_calc_tbt_tag_en_int <= wrdata_reg(0);
pos_calc_tbt_tag_dly_int <= wrdata_reg(16 downto 1);
pos_calc_tbt_tag_dly_swb <= '1';
pos_calc_tbt_tag_dly_swb_delay <= '1';
pos_calc_tbt_tag_desync_cnt_rst_int <= wrdata_reg(17);
pos_calc_tbt_tag_desync_cnt_rst_int_delay <= wrdata_reg(17);
end if;
rddata_reg(0) <= pos_calc_tbt_tag_en_int;
rddata_reg(16 downto 1) <= pos_calc_tbt_tag_dly_int;
rddata_reg(17) <= '0';
if (wb_we_i = '0') then
pos_calc_tbt_tag_desync_cnt_lwb <= '1';
pos_calc_tbt_tag_desync_cnt_lwb_delay <= '1';
pos_calc_tbt_tag_desync_cnt_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0111101" =>
if (wb_we_i = '1') then
pos_calc_tbt_data_mask_ctl_en_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= pos_calc_tbt_data_mask_ctl_en_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0111110" =>
if (wb_we_i = '1') then
pos_calc_tbt_data_mask_samples_beg_int <= wrdata_reg(15 downto 0);
pos_calc_tbt_data_mask_samples_beg_swb <= '1';
pos_calc_tbt_data_mask_samples_beg_swb_delay <= '1';
pos_calc_tbt_data_mask_samples_end_int <= wrdata_reg(31 downto 16);
pos_calc_tbt_data_mask_samples_end_swb <= '1';
pos_calc_tbt_data_mask_samples_end_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= pos_calc_tbt_data_mask_samples_beg_int;
rddata_reg(31 downto 16) <= pos_calc_tbt_data_mask_samples_end_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0111111" =>
if (wb_we_i = '1') then
pos_calc_monit1_tag_en_int <= wrdata_reg(0);
pos_calc_monit1_tag_dly_int <= wrdata_reg(16 downto 1);
pos_calc_monit1_tag_dly_swb <= '1';
pos_calc_monit1_tag_dly_swb_delay <= '1';
pos_calc_monit1_tag_desync_cnt_rst_int <= wrdata_reg(17);
pos_calc_monit1_tag_desync_cnt_rst_int_delay <= wrdata_reg(17);
end if;
rddata_reg(0) <= pos_calc_monit1_tag_en_int;
rddata_reg(16 downto 1) <= pos_calc_monit1_tag_dly_int;
rddata_reg(17) <= '0';
if (wb_we_i = '0') then
pos_calc_monit1_tag_desync_cnt_lwb <= '1';
pos_calc_monit1_tag_desync_cnt_lwb_delay <= '1';
pos_calc_monit1_tag_desync_cnt_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "1000000" =>
if (wb_we_i = '1') then
pos_calc_monit1_data_mask_ctl_en_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= pos_calc_monit1_data_mask_ctl_en_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "1000001" =>
if (wb_we_i = '1') then
pos_calc_monit1_data_mask_samples_beg_int <= wrdata_reg(15 downto 0);
pos_calc_monit1_data_mask_samples_beg_swb <= '1';
pos_calc_monit1_data_mask_samples_beg_swb_delay <= '1';
pos_calc_monit1_data_mask_samples_end_int <= wrdata_reg(31 downto 16);
pos_calc_monit1_data_mask_samples_end_swb <= '1';
pos_calc_monit1_data_mask_samples_end_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= pos_calc_monit1_data_mask_samples_beg_int;
rddata_reg(31 downto 16) <= pos_calc_monit1_data_mask_samples_end_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "1000010" =>
if (wb_we_i = '1') then
pos_calc_monit_tag_en_int <= wrdata_reg(0);
pos_calc_monit_tag_dly_int <= wrdata_reg(16 downto 1);
pos_calc_monit_tag_dly_swb <= '1';
pos_calc_monit_tag_dly_swb_delay <= '1';
pos_calc_monit_tag_desync_cnt_rst_int <= wrdata_reg(17);
pos_calc_monit_tag_desync_cnt_rst_int_delay <= wrdata_reg(17);
end if;
rddata_reg(0) <= pos_calc_monit_tag_en_int;
rddata_reg(16 downto 1) <= pos_calc_monit_tag_dly_int;
rddata_reg(17) <= '0';
if (wb_we_i = '0') then
pos_calc_monit_tag_desync_cnt_lwb <= '1';
pos_calc_monit_tag_desync_cnt_lwb_delay <= '1';
pos_calc_monit_tag_desync_cnt_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "1000011" =>
if (wb_we_i = '1') then
pos_calc_monit_data_mask_ctl_en_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= pos_calc_monit_data_mask_ctl_en_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "1000100" =>
if (wb_we_i = '1') then
pos_calc_monit_data_mask_samples_beg_int <= wrdata_reg(15 downto 0);
pos_calc_monit_data_mask_samples_beg_swb <= '1';
pos_calc_monit_data_mask_samples_beg_swb_delay <= '1';
pos_calc_monit_data_mask_samples_end_int <= wrdata_reg(31 downto 16);
pos_calc_monit_data_mask_samples_end_swb <= '1';
pos_calc_monit_data_mask_samples_end_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= pos_calc_monit_data_mask_samples_beg_int;
rddata_reg(31 downto 16) <= pos_calc_monit_data_mask_samples_end_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Config divisor threshold TBT
-- asynchronous std_logic_vector register : Config divisor threshold TBT (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ds_tbt_thres_val_swb_s0 <= '0';
pos_calc_ds_tbt_thres_val_swb_s1 <= '0';
pos_calc_ds_tbt_thres_val_swb_s2 <= '0';
regs_o.ds_tbt_thres_val_o <= "00000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ds_tbt_thres_val_swb_s0 <= pos_calc_ds_tbt_thres_val_swb;
pos_calc_ds_tbt_thres_val_swb_s1 <= pos_calc_ds_tbt_thres_val_swb_s0;
pos_calc_ds_tbt_thres_val_swb_s2 <= pos_calc_ds_tbt_thres_val_swb_s1;
if ((pos_calc_ds_tbt_thres_val_swb_s2 = '0') and (pos_calc_ds_tbt_thres_val_swb_s1 = '1')) then
regs_o.ds_tbt_thres_val_o <= pos_calc_ds_tbt_thres_val_int;
end if;
end if;
end process;
-- Reserved
-- Config divisor threshold FOFB
-- asynchronous std_logic_vector register : Config divisor threshold FOFB (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ds_fofb_thres_val_swb_s0 <= '0';
pos_calc_ds_fofb_thres_val_swb_s1 <= '0';
pos_calc_ds_fofb_thres_val_swb_s2 <= '0';
regs_o.ds_fofb_thres_val_o <= "00000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ds_fofb_thres_val_swb_s0 <= pos_calc_ds_fofb_thres_val_swb;
pos_calc_ds_fofb_thres_val_swb_s1 <= pos_calc_ds_fofb_thres_val_swb_s0;
pos_calc_ds_fofb_thres_val_swb_s2 <= pos_calc_ds_fofb_thres_val_swb_s1;
if ((pos_calc_ds_fofb_thres_val_swb_s2 = '0') and (pos_calc_ds_fofb_thres_val_swb_s1 = '1')) then
regs_o.ds_fofb_thres_val_o <= pos_calc_ds_fofb_thres_val_int;
end if;
end if;
end process;
-- Reserved
-- Config Divisor Threshold Monit.
-- asynchronous std_logic_vector register : Config Divisor Threshold Monit. (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ds_monit_thres_val_swb_s0 <= '0';
pos_calc_ds_monit_thres_val_swb_s1 <= '0';
pos_calc_ds_monit_thres_val_swb_s2 <= '0';
regs_o.ds_monit_thres_val_o <= "00000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ds_monit_thres_val_swb_s0 <= pos_calc_ds_monit_thres_val_swb;
pos_calc_ds_monit_thres_val_swb_s1 <= pos_calc_ds_monit_thres_val_swb_s0;
pos_calc_ds_monit_thres_val_swb_s2 <= pos_calc_ds_monit_thres_val_swb_s1;
if ((pos_calc_ds_monit_thres_val_swb_s2 = '0') and (pos_calc_ds_monit_thres_val_swb_s1 = '1')) then
regs_o.ds_monit_thres_val_o <= pos_calc_ds_monit_thres_val_int;
end if;
end if;
end process;
-- Reserved
-- BPM sensitivity (X axis) parameter register
-- asynchronous std_logic_vector register : BPM sensitivity (X axis) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_kx_val_swb_s0 <= '0';
pos_calc_kx_val_swb_s1 <= '0';
pos_calc_kx_val_swb_s2 <= '0';
regs_o.kx_val_o <= "0000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_kx_val_swb_s0 <= pos_calc_kx_val_swb;
pos_calc_kx_val_swb_s1 <= pos_calc_kx_val_swb_s0;
pos_calc_kx_val_swb_s2 <= pos_calc_kx_val_swb_s1;
if ((pos_calc_kx_val_swb_s2 = '0') and (pos_calc_kx_val_swb_s1 = '1')) then
regs_o.kx_val_o <= pos_calc_kx_val_int;
end if;
end if;
end process;
-- Reserved
-- BPM sensitivity (Y axis) parameter register
-- asynchronous std_logic_vector register : BPM sensitivity (Y axis) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ky_val_swb_s0 <= '0';
pos_calc_ky_val_swb_s1 <= '0';
pos_calc_ky_val_swb_s2 <= '0';
regs_o.ky_val_o <= "0000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ky_val_swb_s0 <= pos_calc_ky_val_swb;
pos_calc_ky_val_swb_s1 <= pos_calc_ky_val_swb_s0;
pos_calc_ky_val_swb_s2 <= pos_calc_ky_val_swb_s1;
if ((pos_calc_ky_val_swb_s2 = '0') and (pos_calc_ky_val_swb_s1 = '1')) then
regs_o.ky_val_o <= pos_calc_ky_val_int;
end if;
end if;
end process;
-- Reserved
-- BPM sensitivity (Sum) parameter register
-- asynchronous std_logic_vector register : BPM sensitivity (Sum) parameter register (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ksum_val_swb_s0 <= '0';
pos_calc_ksum_val_swb_s1 <= '0';
pos_calc_ksum_val_swb_s2 <= '0';
regs_o.ksum_val_o <= "0000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_ksum_val_swb_s0 <= pos_calc_ksum_val_swb;
pos_calc_ksum_val_swb_s1 <= pos_calc_ksum_val_swb_s0;
pos_calc_ksum_val_swb_s2 <= pos_calc_ksum_val_swb_s1;
if ((pos_calc_ksum_val_swb_s2 = '0') and (pos_calc_ksum_val_swb_s1 = '1')) then
regs_o.ksum_val_o <= pos_calc_ksum_val_int;
end if;
end if;
end process;
-- Reserved
-- TBT incorrect counter for channels 0/1 (multiplexed)
-- asynchronous std_logic_vector register : TBT incorrect counter for channels 0/1 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 <= '0';
pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 <= '0';
pos_calc_dsp_ctnr_tbt_ch01_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr_tbt_ch01_lwb_s0 <= pos_calc_dsp_ctnr_tbt_ch01_lwb;
pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 <= pos_calc_dsp_ctnr_tbt_ch01_lwb_s0;
pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 <= pos_calc_dsp_ctnr_tbt_ch01_lwb_s1;
if ((pos_calc_dsp_ctnr_tbt_ch01_lwb_s1 = '1') and (pos_calc_dsp_ctnr_tbt_ch01_lwb_s2 = '0')) then
pos_calc_dsp_ctnr_tbt_ch01_int <= regs_i.dsp_ctnr_tbt_ch01_i;
end if;
end if;
end process;
-- TBT incorrect counter for channels 2/3 (multiplexed)
-- asynchronous std_logic_vector register : TBT incorrect counter for channels 2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 <= '0';
pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 <= '0';
pos_calc_dsp_ctnr_tbt_ch23_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr_tbt_ch23_lwb_s0 <= pos_calc_dsp_ctnr_tbt_ch23_lwb;
pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 <= pos_calc_dsp_ctnr_tbt_ch23_lwb_s0;
pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 <= pos_calc_dsp_ctnr_tbt_ch23_lwb_s1;
if ((pos_calc_dsp_ctnr_tbt_ch23_lwb_s1 = '1') and (pos_calc_dsp_ctnr_tbt_ch23_lwb_s2 = '0')) then
pos_calc_dsp_ctnr_tbt_ch23_int <= regs_i.dsp_ctnr_tbt_ch23_i;
end if;
end if;
end process;
-- FOFB incorrect counter for channels 0/1 (multiplexed)
-- asynchronous std_logic_vector register : FOFB incorrect counter for channels 0/1 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 <= '0';
pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 <= '0';
pos_calc_dsp_ctnr_fofb_ch01_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr_fofb_ch01_lwb_s0 <= pos_calc_dsp_ctnr_fofb_ch01_lwb;
pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 <= pos_calc_dsp_ctnr_fofb_ch01_lwb_s0;
pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 <= pos_calc_dsp_ctnr_fofb_ch01_lwb_s1;
if ((pos_calc_dsp_ctnr_fofb_ch01_lwb_s1 = '1') and (pos_calc_dsp_ctnr_fofb_ch01_lwb_s2 = '0')) then
pos_calc_dsp_ctnr_fofb_ch01_int <= regs_i.dsp_ctnr_fofb_ch01_i;
end if;
end if;
end process;
-- FOFB incorrect counter for channels 2/3 (multiplexed)
-- asynchronous std_logic_vector register : FOFB incorrect counter for channels 2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 <= '0';
pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 <= '0';
pos_calc_dsp_ctnr_fofb_ch23_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr_fofb_ch23_lwb_s0 <= pos_calc_dsp_ctnr_fofb_ch23_lwb;
pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 <= pos_calc_dsp_ctnr_fofb_ch23_lwb_s0;
pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 <= pos_calc_dsp_ctnr_fofb_ch23_lwb_s1;
if ((pos_calc_dsp_ctnr_fofb_ch23_lwb_s1 = '1') and (pos_calc_dsp_ctnr_fofb_ch23_lwb_s2 = '0')) then
pos_calc_dsp_ctnr_fofb_ch23_int <= regs_i.dsp_ctnr_fofb_ch23_i;
end if;
end if;
end process;
-- Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed)
-- asynchronous std_logic_vector register : Monit. CIC incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr1_monit_cic_lwb_s0 <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb_s1 <= '0';
pos_calc_dsp_ctnr1_monit_cic_lwb_s2 <= '0';
pos_calc_dsp_ctnr1_monit_cic_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr1_monit_cic_lwb_s0 <= pos_calc_dsp_ctnr1_monit_cic_lwb;
pos_calc_dsp_ctnr1_monit_cic_lwb_s1 <= pos_calc_dsp_ctnr1_monit_cic_lwb_s0;
pos_calc_dsp_ctnr1_monit_cic_lwb_s2 <= pos_calc_dsp_ctnr1_monit_cic_lwb_s1;
if ((pos_calc_dsp_ctnr1_monit_cic_lwb_s1 = '1') and (pos_calc_dsp_ctnr1_monit_cic_lwb_s2 = '0')) then
pos_calc_dsp_ctnr1_monit_cic_int <= regs_i.dsp_ctnr1_monit_cic_i;
end if;
end if;
end process;
-- Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed)
-- asynchronous std_logic_vector register : Monit. CFIR incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 <= '0';
pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 <= '0';
pos_calc_dsp_ctnr1_monit_cfir_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr1_monit_cfir_lwb_s0 <= pos_calc_dsp_ctnr1_monit_cfir_lwb;
pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 <= pos_calc_dsp_ctnr1_monit_cfir_lwb_s0;
pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 <= pos_calc_dsp_ctnr1_monit_cfir_lwb_s1;
if ((pos_calc_dsp_ctnr1_monit_cfir_lwb_s1 = '1') and (pos_calc_dsp_ctnr1_monit_cfir_lwb_s2 = '0')) then
pos_calc_dsp_ctnr1_monit_cfir_int <= regs_i.dsp_ctnr1_monit_cfir_i;
end if;
end if;
end process;
-- Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed)
-- asynchronous std_logic_vector register : Monit. PFIR incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 <= '0';
pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 <= '0';
pos_calc_dsp_ctnr2_monit_pfir_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr2_monit_pfir_lwb_s0 <= pos_calc_dsp_ctnr2_monit_pfir_lwb;
pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 <= pos_calc_dsp_ctnr2_monit_pfir_lwb_s0;
pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 <= pos_calc_dsp_ctnr2_monit_pfir_lwb_s1;
if ((pos_calc_dsp_ctnr2_monit_pfir_lwb_s1 = '1') and (pos_calc_dsp_ctnr2_monit_pfir_lwb_s2 = '0')) then
pos_calc_dsp_ctnr2_monit_pfir_int <= regs_i.dsp_ctnr2_monit_pfir_i;
end if;
end if;
end process;
-- Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed)
-- asynchronous std_logic_vector register : Monit. 0.1 Hz incorrect counter for channels 0/1/2/3 (multiplexed) (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 <= '0';
pos_calc_dsp_ctnr2_monit_fir_01_int <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb;
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_s0;
pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 <= pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1;
if ((pos_calc_dsp_ctnr2_monit_fir_01_lwb_s1 = '1') and (pos_calc_dsp_ctnr2_monit_fir_01_lwb_s2 = '0')) then
pos_calc_dsp_ctnr2_monit_fir_01_int <= regs_i.dsp_ctnr2_monit_fir_01_i;
end if;
end if;
end process;
-- Clear TBT error counters
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dsp_err_clr_tbt_o <= '0';
pos_calc_dsp_err_clr_tbt_sync0 <= '0';
pos_calc_dsp_err_clr_tbt_sync1 <= '0';
pos_calc_dsp_err_clr_tbt_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_err_clr_tbt_sync0 <= pos_calc_dsp_err_clr_tbt_int;
pos_calc_dsp_err_clr_tbt_sync1 <= pos_calc_dsp_err_clr_tbt_sync0;
pos_calc_dsp_err_clr_tbt_sync2 <= pos_calc_dsp_err_clr_tbt_sync1;
regs_o.dsp_err_clr_tbt_o <= pos_calc_dsp_err_clr_tbt_sync2 and (not pos_calc_dsp_err_clr_tbt_sync1);
end if;
end process;
-- Clear FOFB error counters
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dsp_err_clr_fofb_o <= '0';
pos_calc_dsp_err_clr_fofb_sync0 <= '0';
pos_calc_dsp_err_clr_fofb_sync1 <= '0';
pos_calc_dsp_err_clr_fofb_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_err_clr_fofb_sync0 <= pos_calc_dsp_err_clr_fofb_int;
pos_calc_dsp_err_clr_fofb_sync1 <= pos_calc_dsp_err_clr_fofb_sync0;
pos_calc_dsp_err_clr_fofb_sync2 <= pos_calc_dsp_err_clr_fofb_sync1;
regs_o.dsp_err_clr_fofb_o <= pos_calc_dsp_err_clr_fofb_sync2 and (not pos_calc_dsp_err_clr_fofb_sync1);
end if;
end process;
-- Clear Monit. CIC and CFIR error counters
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dsp_err_clr_monit_part1_o <= '0';
pos_calc_dsp_err_clr_monit_part1_sync0 <= '0';
pos_calc_dsp_err_clr_monit_part1_sync1 <= '0';
pos_calc_dsp_err_clr_monit_part1_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_err_clr_monit_part1_sync0 <= pos_calc_dsp_err_clr_monit_part1_int;
pos_calc_dsp_err_clr_monit_part1_sync1 <= pos_calc_dsp_err_clr_monit_part1_sync0;
pos_calc_dsp_err_clr_monit_part1_sync2 <= pos_calc_dsp_err_clr_monit_part1_sync1;
regs_o.dsp_err_clr_monit_part1_o <= pos_calc_dsp_err_clr_monit_part1_sync2 and (not pos_calc_dsp_err_clr_monit_part1_sync1);
end if;
end process;
-- Clear Monit. PFIR and Monit. 0.1 error counters
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dsp_err_clr_monit_part2_o <= '0';
pos_calc_dsp_err_clr_monit_part2_sync0 <= '0';
pos_calc_dsp_err_clr_monit_part2_sync1 <= '0';
pos_calc_dsp_err_clr_monit_part2_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dsp_err_clr_monit_part2_sync0 <= pos_calc_dsp_err_clr_monit_part2_int;
pos_calc_dsp_err_clr_monit_part2_sync1 <= pos_calc_dsp_err_clr_monit_part2_sync0;
pos_calc_dsp_err_clr_monit_part2_sync2 <= pos_calc_dsp_err_clr_monit_part2_sync1;
regs_o.dsp_err_clr_monit_part2_o <= pos_calc_dsp_err_clr_monit_part2_sync2 and (not pos_calc_dsp_err_clr_monit_part2_sync1);
end if;
end process;
-- Valid signal for channel 0 DDS
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_valid_ch0_o <= '0';
pos_calc_dds_cfg_valid_ch0_sync0 <= '0';
pos_calc_dds_cfg_valid_ch0_sync1 <= '0';
pos_calc_dds_cfg_valid_ch0_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_valid_ch0_sync0 <= pos_calc_dds_cfg_valid_ch0_int;
pos_calc_dds_cfg_valid_ch0_sync1 <= pos_calc_dds_cfg_valid_ch0_sync0;
pos_calc_dds_cfg_valid_ch0_sync2 <= pos_calc_dds_cfg_valid_ch0_sync1;
regs_o.dds_cfg_valid_ch0_o <= pos_calc_dds_cfg_valid_ch0_sync2 and (not pos_calc_dds_cfg_valid_ch0_sync1);
end if;
end process;
-- Test data counter for all channels
-- synchronizer chain for field : Test data counter for all channels (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_test_data_o <= '0';
pos_calc_dds_cfg_test_data_sync0 <= '0';
pos_calc_dds_cfg_test_data_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_test_data_sync0 <= pos_calc_dds_cfg_test_data_int;
pos_calc_dds_cfg_test_data_sync1 <= pos_calc_dds_cfg_test_data_sync0;
regs_o.dds_cfg_test_data_o <= pos_calc_dds_cfg_test_data_sync1;
end if;
end process;
-- Reserved
-- Valid signal for channel 1 DDS
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_valid_ch1_o <= '0';
pos_calc_dds_cfg_valid_ch1_sync0 <= '0';
pos_calc_dds_cfg_valid_ch1_sync1 <= '0';
pos_calc_dds_cfg_valid_ch1_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_valid_ch1_sync0 <= pos_calc_dds_cfg_valid_ch1_int;
pos_calc_dds_cfg_valid_ch1_sync1 <= pos_calc_dds_cfg_valid_ch1_sync0;
pos_calc_dds_cfg_valid_ch1_sync2 <= pos_calc_dds_cfg_valid_ch1_sync1;
regs_o.dds_cfg_valid_ch1_o <= pos_calc_dds_cfg_valid_ch1_sync2 and (not pos_calc_dds_cfg_valid_ch1_sync1);
end if;
end process;
-- Reserved
-- Valid signal for channel 2 DDS
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_valid_ch2_o <= '0';
pos_calc_dds_cfg_valid_ch2_sync0 <= '0';
pos_calc_dds_cfg_valid_ch2_sync1 <= '0';
pos_calc_dds_cfg_valid_ch2_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_valid_ch2_sync0 <= pos_calc_dds_cfg_valid_ch2_int;
pos_calc_dds_cfg_valid_ch2_sync1 <= pos_calc_dds_cfg_valid_ch2_sync0;
pos_calc_dds_cfg_valid_ch2_sync2 <= pos_calc_dds_cfg_valid_ch2_sync1;
regs_o.dds_cfg_valid_ch2_o <= pos_calc_dds_cfg_valid_ch2_sync2 and (not pos_calc_dds_cfg_valid_ch2_sync1);
end if;
end process;
-- Reserved
-- Valid signal for channel 3 DDS
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.dds_cfg_valid_ch3_o <= '0';
pos_calc_dds_cfg_valid_ch3_sync0 <= '0';
pos_calc_dds_cfg_valid_ch3_sync1 <= '0';
pos_calc_dds_cfg_valid_ch3_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_cfg_valid_ch3_sync0 <= pos_calc_dds_cfg_valid_ch3_int;
pos_calc_dds_cfg_valid_ch3_sync1 <= pos_calc_dds_cfg_valid_ch3_sync0;
pos_calc_dds_cfg_valid_ch3_sync2 <= pos_calc_dds_cfg_valid_ch3_sync1;
regs_o.dds_cfg_valid_ch3_o <= pos_calc_dds_cfg_valid_ch3_sync2 and (not pos_calc_dds_cfg_valid_ch3_sync1);
end if;
end process;
-- Reserved
-- DDS phase increment parameter register for channel 0
-- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 0 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_pinc_ch0_val_swb_s0 <= '0';
pos_calc_dds_pinc_ch0_val_swb_s1 <= '0';
pos_calc_dds_pinc_ch0_val_swb_s2 <= '0';
regs_o.dds_pinc_ch0_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_pinc_ch0_val_swb_s0 <= pos_calc_dds_pinc_ch0_val_swb;
pos_calc_dds_pinc_ch0_val_swb_s1 <= pos_calc_dds_pinc_ch0_val_swb_s0;
pos_calc_dds_pinc_ch0_val_swb_s2 <= pos_calc_dds_pinc_ch0_val_swb_s1;
if ((pos_calc_dds_pinc_ch0_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch0_val_swb_s1 = '1')) then
regs_o.dds_pinc_ch0_val_o <= pos_calc_dds_pinc_ch0_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase increment parameter register for channel 1
-- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 1 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_pinc_ch1_val_swb_s0 <= '0';
pos_calc_dds_pinc_ch1_val_swb_s1 <= '0';
pos_calc_dds_pinc_ch1_val_swb_s2 <= '0';
regs_o.dds_pinc_ch1_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_pinc_ch1_val_swb_s0 <= pos_calc_dds_pinc_ch1_val_swb;
pos_calc_dds_pinc_ch1_val_swb_s1 <= pos_calc_dds_pinc_ch1_val_swb_s0;
pos_calc_dds_pinc_ch1_val_swb_s2 <= pos_calc_dds_pinc_ch1_val_swb_s1;
if ((pos_calc_dds_pinc_ch1_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch1_val_swb_s1 = '1')) then
regs_o.dds_pinc_ch1_val_o <= pos_calc_dds_pinc_ch1_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase increment parameter register for channel 2
-- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 2 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_pinc_ch2_val_swb_s0 <= '0';
pos_calc_dds_pinc_ch2_val_swb_s1 <= '0';
pos_calc_dds_pinc_ch2_val_swb_s2 <= '0';
regs_o.dds_pinc_ch2_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_pinc_ch2_val_swb_s0 <= pos_calc_dds_pinc_ch2_val_swb;
pos_calc_dds_pinc_ch2_val_swb_s1 <= pos_calc_dds_pinc_ch2_val_swb_s0;
pos_calc_dds_pinc_ch2_val_swb_s2 <= pos_calc_dds_pinc_ch2_val_swb_s1;
if ((pos_calc_dds_pinc_ch2_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch2_val_swb_s1 = '1')) then
regs_o.dds_pinc_ch2_val_o <= pos_calc_dds_pinc_ch2_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase increment parameter register for channel 3
-- asynchronous std_logic_vector register : DDS phase increment parameter register for channel 3 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_pinc_ch3_val_swb_s0 <= '0';
pos_calc_dds_pinc_ch3_val_swb_s1 <= '0';
pos_calc_dds_pinc_ch3_val_swb_s2 <= '0';
regs_o.dds_pinc_ch3_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_pinc_ch3_val_swb_s0 <= pos_calc_dds_pinc_ch3_val_swb;
pos_calc_dds_pinc_ch3_val_swb_s1 <= pos_calc_dds_pinc_ch3_val_swb_s0;
pos_calc_dds_pinc_ch3_val_swb_s2 <= pos_calc_dds_pinc_ch3_val_swb_s1;
if ((pos_calc_dds_pinc_ch3_val_swb_s2 = '0') and (pos_calc_dds_pinc_ch3_val_swb_s1 = '1')) then
regs_o.dds_pinc_ch3_val_o <= pos_calc_dds_pinc_ch3_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase offset parameter register for channel 0
-- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 0 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_poff_ch0_val_swb_s0 <= '0';
pos_calc_dds_poff_ch0_val_swb_s1 <= '0';
pos_calc_dds_poff_ch0_val_swb_s2 <= '0';
regs_o.dds_poff_ch0_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_poff_ch0_val_swb_s0 <= pos_calc_dds_poff_ch0_val_swb;
pos_calc_dds_poff_ch0_val_swb_s1 <= pos_calc_dds_poff_ch0_val_swb_s0;
pos_calc_dds_poff_ch0_val_swb_s2 <= pos_calc_dds_poff_ch0_val_swb_s1;
if ((pos_calc_dds_poff_ch0_val_swb_s2 = '0') and (pos_calc_dds_poff_ch0_val_swb_s1 = '1')) then
regs_o.dds_poff_ch0_val_o <= pos_calc_dds_poff_ch0_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase offset parameter register for channel 1
-- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 1 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_poff_ch1_val_swb_s0 <= '0';
pos_calc_dds_poff_ch1_val_swb_s1 <= '0';
pos_calc_dds_poff_ch1_val_swb_s2 <= '0';
regs_o.dds_poff_ch1_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_poff_ch1_val_swb_s0 <= pos_calc_dds_poff_ch1_val_swb;
pos_calc_dds_poff_ch1_val_swb_s1 <= pos_calc_dds_poff_ch1_val_swb_s0;
pos_calc_dds_poff_ch1_val_swb_s2 <= pos_calc_dds_poff_ch1_val_swb_s1;
if ((pos_calc_dds_poff_ch1_val_swb_s2 = '0') and (pos_calc_dds_poff_ch1_val_swb_s1 = '1')) then
regs_o.dds_poff_ch1_val_o <= pos_calc_dds_poff_ch1_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase offset parameter register for channel 2
-- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 2 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_poff_ch2_val_swb_s0 <= '0';
pos_calc_dds_poff_ch2_val_swb_s1 <= '0';
pos_calc_dds_poff_ch2_val_swb_s2 <= '0';
regs_o.dds_poff_ch2_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_poff_ch2_val_swb_s0 <= pos_calc_dds_poff_ch2_val_swb;
pos_calc_dds_poff_ch2_val_swb_s1 <= pos_calc_dds_poff_ch2_val_swb_s0;
pos_calc_dds_poff_ch2_val_swb_s2 <= pos_calc_dds_poff_ch2_val_swb_s1;
if ((pos_calc_dds_poff_ch2_val_swb_s2 = '0') and (pos_calc_dds_poff_ch2_val_swb_s1 = '1')) then
regs_o.dds_poff_ch2_val_o <= pos_calc_dds_poff_ch2_val_int;
end if;
end if;
end process;
-- Reserved
-- DDS phase offset parameter register for channel 3
-- asynchronous std_logic_vector register : DDS phase offset parameter register for channel 3 (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_dds_poff_ch3_val_swb_s0 <= '0';
pos_calc_dds_poff_ch3_val_swb_s1 <= '0';
pos_calc_dds_poff_ch3_val_swb_s2 <= '0';
regs_o.dds_poff_ch3_val_o <= "000000000000000000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_dds_poff_ch3_val_swb_s0 <= pos_calc_dds_poff_ch3_val_swb;
pos_calc_dds_poff_ch3_val_swb_s1 <= pos_calc_dds_poff_ch3_val_swb_s0;
pos_calc_dds_poff_ch3_val_swb_s2 <= pos_calc_dds_poff_ch3_val_swb_s1;
if ((pos_calc_dds_poff_ch3_val_swb_s2 = '0') and (pos_calc_dds_poff_ch3_val_swb_s1 = '1')) then
regs_o.dds_poff_ch3_val_o <= pos_calc_dds_poff_ch3_val_int;
end if;
end if;
end process;
-- Reserved
-- Monit. Amplitude Value for channel 0
-- Monit. Amplitude Value for channel 1
-- Monit. Amplitude Value for channel 2
-- Monit. Amplitude Value for channel 3
-- Monit. X Position Value
-- Monit. Y Position Value
-- Monit. Q Position Value
-- Monit. Sum Position Value
-- Monit. Amp/Pos Update (ignore on read)
-- pass-through field: Monit. Amp/Pos Update (ignore on read) in register: Monit. Amp/Pos update trigger
regs_o.dsp_monit_updt_o <= wrdata_reg(31 downto 0);
-- extra code for reg/fifo/mem: AMP FIFO Monitoring
pos_calc_ampfifo_monit_in_int(31 downto 0) <= regs_i.ampfifo_monit_amp_ch0_i;
pos_calc_ampfifo_monit_in_int(63 downto 32) <= regs_i.ampfifo_monit_amp_ch1_i;
pos_calc_ampfifo_monit_in_int(95 downto 64) <= regs_i.ampfifo_monit_amp_ch2_i;
pos_calc_ampfifo_monit_in_int(127 downto 96) <= regs_i.ampfifo_monit_amp_ch3_i;
pos_calc_ampfifo_monit_rst_n <= rst_n_i;
pos_calc_ampfifo_monit_INST : wbgen2_fifo_sync
generic map (
g_size => 16,
g_width => 128,
g_usedw_size => 4
)
port map (
wr_req_i => regs_i.ampfifo_monit_wr_req_i,
wr_full_o => regs_o.ampfifo_monit_wr_full_o,
wr_empty_o => regs_o.ampfifo_monit_wr_empty_o,
wr_usedw_o => regs_o.ampfifo_monit_wr_usedw_o,
rd_full_o => pos_calc_ampfifo_monit_full_int,
rd_empty_o => pos_calc_ampfifo_monit_empty_int,
rd_usedw_o => pos_calc_ampfifo_monit_usedw_int,
rd_req_i => pos_calc_ampfifo_monit_rdreq_int,
rst_n_i => pos_calc_ampfifo_monit_rst_n,
clk_i => clk_sys_i,
wr_data_i => pos_calc_ampfifo_monit_in_int,
rd_data_o => pos_calc_ampfifo_monit_out_int
);
-- extra code for reg/fifo/mem: POS FIFO Monitoring
pos_calc_posfifo_monit_in_int(31 downto 0) <= regs_i.posfifo_monit_pos_x_i;
pos_calc_posfifo_monit_in_int(63 downto 32) <= regs_i.posfifo_monit_pos_y_i;
pos_calc_posfifo_monit_in_int(95 downto 64) <= regs_i.posfifo_monit_pos_q_i;
pos_calc_posfifo_monit_in_int(127 downto 96) <= regs_i.posfifo_monit_pos_sum_i;
pos_calc_posfifo_monit_rst_n <= rst_n_i;
pos_calc_posfifo_monit_INST : wbgen2_fifo_sync
generic map (
g_size => 16,
g_width => 128,
g_usedw_size => 4
)
port map (
wr_req_i => regs_i.posfifo_monit_wr_req_i,
wr_full_o => regs_o.posfifo_monit_wr_full_o,
wr_empty_o => regs_o.posfifo_monit_wr_empty_o,
wr_usedw_o => regs_o.posfifo_monit_wr_usedw_o,
rd_full_o => pos_calc_posfifo_monit_full_int,
rd_empty_o => pos_calc_posfifo_monit_empty_int,
rd_usedw_o => pos_calc_posfifo_monit_usedw_int,
rd_req_i => pos_calc_posfifo_monit_rdreq_int,
rst_n_i => pos_calc_posfifo_monit_rst_n,
clk_i => clk_sys_i,
wr_data_i => pos_calc_posfifo_monit_in_int,
rd_data_o => pos_calc_posfifo_monit_out_int
);
-- Monit. 1 Amplitude Value for channel 0
-- Monit. 1 Amplitude Value for channel 1
-- Monit. 1 Amplitude Value for channel 2
-- Monit. 1 Amplitude Value for channel 3
-- Monit. 1 X Position Value
-- Monit. 1 Y Position Value
-- Monit. 1 Q Position Value
-- Monit. 1 Sum Position Value
-- Monit. 1 Amp/Pos Update (ignore on read)
-- pass-through field: Monit. 1 Amp/Pos Update (ignore on read) in register: Monit. 1 Amp/Pos update trigger
regs_o.dsp_monit1_updt_o <= wrdata_reg(31 downto 0);
-- extra code for reg/fifo/mem: AMP FIFO Monitoring 1
pos_calc_ampfifo_monit1_in_int(31 downto 0) <= regs_i.ampfifo_monit1_amp_ch0_i;
pos_calc_ampfifo_monit1_in_int(63 downto 32) <= regs_i.ampfifo_monit1_amp_ch1_i;
pos_calc_ampfifo_monit1_in_int(95 downto 64) <= regs_i.ampfifo_monit1_amp_ch2_i;
pos_calc_ampfifo_monit1_in_int(127 downto 96) <= regs_i.ampfifo_monit1_amp_ch3_i;
pos_calc_ampfifo_monit1_rst_n <= rst_n_i;
pos_calc_ampfifo_monit1_INST : wbgen2_fifo_sync
generic map (
g_size => 16,
g_width => 128,
g_usedw_size => 4
)
port map (
wr_req_i => regs_i.ampfifo_monit1_wr_req_i,
wr_full_o => regs_o.ampfifo_monit1_wr_full_o,
wr_empty_o => regs_o.ampfifo_monit1_wr_empty_o,
wr_usedw_o => regs_o.ampfifo_monit1_wr_usedw_o,
rd_full_o => pos_calc_ampfifo_monit1_full_int,
rd_empty_o => pos_calc_ampfifo_monit1_empty_int,
rd_usedw_o => pos_calc_ampfifo_monit1_usedw_int,
rd_req_i => pos_calc_ampfifo_monit1_rdreq_int,
rst_n_i => pos_calc_ampfifo_monit1_rst_n,
clk_i => clk_sys_i,
wr_data_i => pos_calc_ampfifo_monit1_in_int,
rd_data_o => pos_calc_ampfifo_monit1_out_int
);
-- extra code for reg/fifo/mem: POS FIFO Monitoring 1
pos_calc_posfifo_monit1_in_int(31 downto 0) <= regs_i.posfifo_monit1_pos_x_i;
pos_calc_posfifo_monit1_in_int(63 downto 32) <= regs_i.posfifo_monit1_pos_y_i;
pos_calc_posfifo_monit1_in_int(95 downto 64) <= regs_i.posfifo_monit1_pos_q_i;
pos_calc_posfifo_monit1_in_int(127 downto 96) <= regs_i.posfifo_monit1_pos_sum_i;
pos_calc_posfifo_monit1_rst_n <= rst_n_i;
pos_calc_posfifo_monit1_INST : wbgen2_fifo_sync
generic map (
g_size => 16,
g_width => 128,
g_usedw_size => 4
)
port map (
wr_req_i => regs_i.posfifo_monit1_wr_req_i,
wr_full_o => regs_o.posfifo_monit1_wr_full_o,
wr_empty_o => regs_o.posfifo_monit1_wr_empty_o,
wr_usedw_o => regs_o.posfifo_monit1_wr_usedw_o,
rd_full_o => pos_calc_posfifo_monit1_full_int,
rd_empty_o => pos_calc_posfifo_monit1_empty_int,
rd_usedw_o => pos_calc_posfifo_monit1_usedw_int,
rd_req_i => pos_calc_posfifo_monit1_rdreq_int,
rst_n_i => pos_calc_posfifo_monit1_rst_n,
clk_i => clk_sys_i,
wr_data_i => pos_calc_posfifo_monit1_in_int,
rd_data_o => pos_calc_posfifo_monit1_out_int
);
-- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ampfifo_monit_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
pos_calc_ampfifo_monit_rdreq_int_d0 <= pos_calc_ampfifo_monit_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 1
-- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 2
-- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 3
-- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_posfifo_monit_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
pos_calc_posfifo_monit_rdreq_int_d0 <= pos_calc_posfifo_monit_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring' data output register 1
-- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring' data output register 2
-- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring' data output register 3
-- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring 1' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_ampfifo_monit1_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
pos_calc_ampfifo_monit1_rdreq_int_d0 <= pos_calc_ampfifo_monit1_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring 1' data output register 1
-- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring 1' data output register 2
-- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring 1' data output register 3
-- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring 1' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_posfifo_monit1_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
pos_calc_posfifo_monit1_rdreq_int_d0 <= pos_calc_posfifo_monit1_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring 1' data output register 1
-- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring 1' data output register 2
-- extra code for reg/fifo/mem: FIFO 'POS FIFO Monitoring 1' data output register 3
-- Tag Synchronization Enable
-- synchronizer chain for field : Tag Synchronization Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.sw_tag_en_o <= '0';
pos_calc_sw_tag_en_sync0 <= '0';
pos_calc_sw_tag_en_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_sw_tag_en_sync0 <= pos_calc_sw_tag_en_int;
pos_calc_sw_tag_en_sync1 <= pos_calc_sw_tag_en_sync0;
regs_o.sw_tag_en_o <= pos_calc_sw_tag_en_sync1;
end if;
end process;
-- Switching Desynchronization Counter Reset
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.sw_tag_desync_cnt_rst_o <= '0';
pos_calc_sw_tag_desync_cnt_rst_sync0 <= '0';
pos_calc_sw_tag_desync_cnt_rst_sync1 <= '0';
pos_calc_sw_tag_desync_cnt_rst_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_sw_tag_desync_cnt_rst_sync0 <= pos_calc_sw_tag_desync_cnt_rst_int;
pos_calc_sw_tag_desync_cnt_rst_sync1 <= pos_calc_sw_tag_desync_cnt_rst_sync0;
pos_calc_sw_tag_desync_cnt_rst_sync2 <= pos_calc_sw_tag_desync_cnt_rst_sync1;
regs_o.sw_tag_desync_cnt_rst_o <= pos_calc_sw_tag_desync_cnt_rst_sync2 and (not pos_calc_sw_tag_desync_cnt_rst_sync1);
end if;
end process;
-- Switching Desynchronization Counter
-- asynchronous std_logic_vector register : Switching Desynchronization Counter (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_sw_tag_desync_cnt_lwb_s0 <= '0';
pos_calc_sw_tag_desync_cnt_lwb_s1 <= '0';
pos_calc_sw_tag_desync_cnt_lwb_s2 <= '0';
pos_calc_sw_tag_desync_cnt_int <= "00000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_sw_tag_desync_cnt_lwb_s0 <= pos_calc_sw_tag_desync_cnt_lwb;
pos_calc_sw_tag_desync_cnt_lwb_s1 <= pos_calc_sw_tag_desync_cnt_lwb_s0;
pos_calc_sw_tag_desync_cnt_lwb_s2 <= pos_calc_sw_tag_desync_cnt_lwb_s1;
if ((pos_calc_sw_tag_desync_cnt_lwb_s1 = '1') and (pos_calc_sw_tag_desync_cnt_lwb_s2 = '0')) then
pos_calc_sw_tag_desync_cnt_int <= regs_i.sw_tag_desync_cnt_i;
end if;
end if;
end process;
-- Switching Data Mask Enable
-- synchronizer chain for field : Switching Data Mask Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.sw_data_mask_en_o <= '0';
pos_calc_sw_data_mask_en_sync0 <= '0';
pos_calc_sw_data_mask_en_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_sw_data_mask_en_sync0 <= pos_calc_sw_data_mask_en_int;
pos_calc_sw_data_mask_en_sync1 <= pos_calc_sw_data_mask_en_sync0;
regs_o.sw_data_mask_en_o <= pos_calc_sw_data_mask_en_sync1;
end if;
end process;
-- Switching Data Mask Samples
-- asynchronous std_logic_vector register : Switching Data Mask Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_sw_data_mask_samples_swb_s0 <= '0';
pos_calc_sw_data_mask_samples_swb_s1 <= '0';
pos_calc_sw_data_mask_samples_swb_s2 <= '0';
regs_o.sw_data_mask_samples_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_sw_data_mask_samples_swb_s0 <= pos_calc_sw_data_mask_samples_swb;
pos_calc_sw_data_mask_samples_swb_s1 <= pos_calc_sw_data_mask_samples_swb_s0;
pos_calc_sw_data_mask_samples_swb_s2 <= pos_calc_sw_data_mask_samples_swb_s1;
if ((pos_calc_sw_data_mask_samples_swb_s2 = '0') and (pos_calc_sw_data_mask_samples_swb_s1 = '1')) then
regs_o.sw_data_mask_samples_o <= pos_calc_sw_data_mask_samples_int;
end if;
end if;
end process;
-- TbT Synchronizing Trigger Enable
-- synchronizer chain for field : TbT Synchronizing Trigger Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tbt_tag_en_o <= '0';
pos_calc_tbt_tag_en_sync0 <= '0';
pos_calc_tbt_tag_en_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_tbt_tag_en_sync0 <= pos_calc_tbt_tag_en_int;
pos_calc_tbt_tag_en_sync1 <= pos_calc_tbt_tag_en_sync0;
regs_o.tbt_tag_en_o <= pos_calc_tbt_tag_en_sync1;
end if;
end process;
-- TbT Synchronizing Trigger Delay
-- asynchronous std_logic_vector register : TbT Synchronizing Trigger Delay (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_tbt_tag_dly_swb_s0 <= '0';
pos_calc_tbt_tag_dly_swb_s1 <= '0';
pos_calc_tbt_tag_dly_swb_s2 <= '0';
regs_o.tbt_tag_dly_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_tbt_tag_dly_swb_s0 <= pos_calc_tbt_tag_dly_swb;
pos_calc_tbt_tag_dly_swb_s1 <= pos_calc_tbt_tag_dly_swb_s0;
pos_calc_tbt_tag_dly_swb_s2 <= pos_calc_tbt_tag_dly_swb_s1;
if ((pos_calc_tbt_tag_dly_swb_s2 = '0') and (pos_calc_tbt_tag_dly_swb_s1 = '1')) then
regs_o.tbt_tag_dly_o <= pos_calc_tbt_tag_dly_int;
end if;
end if;
end process;
-- TbT Desynchronization Counter Reset
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tbt_tag_desync_cnt_rst_o <= '0';
pos_calc_tbt_tag_desync_cnt_rst_sync0 <= '0';
pos_calc_tbt_tag_desync_cnt_rst_sync1 <= '0';
pos_calc_tbt_tag_desync_cnt_rst_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_tbt_tag_desync_cnt_rst_sync0 <= pos_calc_tbt_tag_desync_cnt_rst_int;
pos_calc_tbt_tag_desync_cnt_rst_sync1 <= pos_calc_tbt_tag_desync_cnt_rst_sync0;
pos_calc_tbt_tag_desync_cnt_rst_sync2 <= pos_calc_tbt_tag_desync_cnt_rst_sync1;
regs_o.tbt_tag_desync_cnt_rst_o <= pos_calc_tbt_tag_desync_cnt_rst_sync2 and (not pos_calc_tbt_tag_desync_cnt_rst_sync1);
end if;
end process;
-- TbT Desynchronization Counter
-- asynchronous std_logic_vector register : TbT Desynchronization Counter (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_tbt_tag_desync_cnt_lwb_s0 <= '0';
pos_calc_tbt_tag_desync_cnt_lwb_s1 <= '0';
pos_calc_tbt_tag_desync_cnt_lwb_s2 <= '0';
pos_calc_tbt_tag_desync_cnt_int <= "00000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_tbt_tag_desync_cnt_lwb_s0 <= pos_calc_tbt_tag_desync_cnt_lwb;
pos_calc_tbt_tag_desync_cnt_lwb_s1 <= pos_calc_tbt_tag_desync_cnt_lwb_s0;
pos_calc_tbt_tag_desync_cnt_lwb_s2 <= pos_calc_tbt_tag_desync_cnt_lwb_s1;
if ((pos_calc_tbt_tag_desync_cnt_lwb_s1 = '1') and (pos_calc_tbt_tag_desync_cnt_lwb_s2 = '0')) then
pos_calc_tbt_tag_desync_cnt_int <= regs_i.tbt_tag_desync_cnt_i;
end if;
end if;
end process;
-- TbT Masking Enable
-- synchronizer chain for field : TbT Masking Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tbt_data_mask_ctl_en_o <= '0';
pos_calc_tbt_data_mask_ctl_en_sync0 <= '0';
pos_calc_tbt_data_mask_ctl_en_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_tbt_data_mask_ctl_en_sync0 <= pos_calc_tbt_data_mask_ctl_en_int;
pos_calc_tbt_data_mask_ctl_en_sync1 <= pos_calc_tbt_data_mask_ctl_en_sync0;
regs_o.tbt_data_mask_ctl_en_o <= pos_calc_tbt_data_mask_ctl_en_sync1;
end if;
end process;
-- TbT Beginning Data Masking Samples
-- asynchronous std_logic_vector register : TbT Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_tbt_data_mask_samples_beg_swb_s0 <= '0';
pos_calc_tbt_data_mask_samples_beg_swb_s1 <= '0';
pos_calc_tbt_data_mask_samples_beg_swb_s2 <= '0';
regs_o.tbt_data_mask_samples_beg_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_tbt_data_mask_samples_beg_swb_s0 <= pos_calc_tbt_data_mask_samples_beg_swb;
pos_calc_tbt_data_mask_samples_beg_swb_s1 <= pos_calc_tbt_data_mask_samples_beg_swb_s0;
pos_calc_tbt_data_mask_samples_beg_swb_s2 <= pos_calc_tbt_data_mask_samples_beg_swb_s1;
if ((pos_calc_tbt_data_mask_samples_beg_swb_s2 = '0') and (pos_calc_tbt_data_mask_samples_beg_swb_s1 = '1')) then
regs_o.tbt_data_mask_samples_beg_o <= pos_calc_tbt_data_mask_samples_beg_int;
end if;
end if;
end process;
-- TbT Beginning Data Masking Samples
-- asynchronous std_logic_vector register : TbT Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_tbt_data_mask_samples_end_swb_s0 <= '0';
pos_calc_tbt_data_mask_samples_end_swb_s1 <= '0';
pos_calc_tbt_data_mask_samples_end_swb_s2 <= '0';
regs_o.tbt_data_mask_samples_end_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_tbt_data_mask_samples_end_swb_s0 <= pos_calc_tbt_data_mask_samples_end_swb;
pos_calc_tbt_data_mask_samples_end_swb_s1 <= pos_calc_tbt_data_mask_samples_end_swb_s0;
pos_calc_tbt_data_mask_samples_end_swb_s2 <= pos_calc_tbt_data_mask_samples_end_swb_s1;
if ((pos_calc_tbt_data_mask_samples_end_swb_s2 = '0') and (pos_calc_tbt_data_mask_samples_end_swb_s1 = '1')) then
regs_o.tbt_data_mask_samples_end_o <= pos_calc_tbt_data_mask_samples_end_int;
end if;
end if;
end process;
-- MONIT1 Synchronizing Trigger Enable
-- synchronizer chain for field : MONIT1 Synchronizing Trigger Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.monit1_tag_en_o <= '0';
pos_calc_monit1_tag_en_sync0 <= '0';
pos_calc_monit1_tag_en_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit1_tag_en_sync0 <= pos_calc_monit1_tag_en_int;
pos_calc_monit1_tag_en_sync1 <= pos_calc_monit1_tag_en_sync0;
regs_o.monit1_tag_en_o <= pos_calc_monit1_tag_en_sync1;
end if;
end process;
-- MONIT1 Synchronizing Trigger Delay
-- asynchronous std_logic_vector register : MONIT1 Synchronizing Trigger Delay (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_monit1_tag_dly_swb_s0 <= '0';
pos_calc_monit1_tag_dly_swb_s1 <= '0';
pos_calc_monit1_tag_dly_swb_s2 <= '0';
regs_o.monit1_tag_dly_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit1_tag_dly_swb_s0 <= pos_calc_monit1_tag_dly_swb;
pos_calc_monit1_tag_dly_swb_s1 <= pos_calc_monit1_tag_dly_swb_s0;
pos_calc_monit1_tag_dly_swb_s2 <= pos_calc_monit1_tag_dly_swb_s1;
if ((pos_calc_monit1_tag_dly_swb_s2 = '0') and (pos_calc_monit1_tag_dly_swb_s1 = '1')) then
regs_o.monit1_tag_dly_o <= pos_calc_monit1_tag_dly_int;
end if;
end if;
end process;
-- MONIT1 Desynchronization Counter Reset
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.monit1_tag_desync_cnt_rst_o <= '0';
pos_calc_monit1_tag_desync_cnt_rst_sync0 <= '0';
pos_calc_monit1_tag_desync_cnt_rst_sync1 <= '0';
pos_calc_monit1_tag_desync_cnt_rst_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit1_tag_desync_cnt_rst_sync0 <= pos_calc_monit1_tag_desync_cnt_rst_int;
pos_calc_monit1_tag_desync_cnt_rst_sync1 <= pos_calc_monit1_tag_desync_cnt_rst_sync0;
pos_calc_monit1_tag_desync_cnt_rst_sync2 <= pos_calc_monit1_tag_desync_cnt_rst_sync1;
regs_o.monit1_tag_desync_cnt_rst_o <= pos_calc_monit1_tag_desync_cnt_rst_sync2 and (not pos_calc_monit1_tag_desync_cnt_rst_sync1);
end if;
end process;
-- MONIT1 Desynchronization Counter
-- asynchronous std_logic_vector register : MONIT1 Desynchronization Counter (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_monit1_tag_desync_cnt_lwb_s0 <= '0';
pos_calc_monit1_tag_desync_cnt_lwb_s1 <= '0';
pos_calc_monit1_tag_desync_cnt_lwb_s2 <= '0';
pos_calc_monit1_tag_desync_cnt_int <= "00000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit1_tag_desync_cnt_lwb_s0 <= pos_calc_monit1_tag_desync_cnt_lwb;
pos_calc_monit1_tag_desync_cnt_lwb_s1 <= pos_calc_monit1_tag_desync_cnt_lwb_s0;
pos_calc_monit1_tag_desync_cnt_lwb_s2 <= pos_calc_monit1_tag_desync_cnt_lwb_s1;
if ((pos_calc_monit1_tag_desync_cnt_lwb_s1 = '1') and (pos_calc_monit1_tag_desync_cnt_lwb_s2 = '0')) then
pos_calc_monit1_tag_desync_cnt_int <= regs_i.monit1_tag_desync_cnt_i;
end if;
end if;
end process;
-- MONIT1 Masking Enable
-- synchronizer chain for field : MONIT1 Masking Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.monit1_data_mask_ctl_en_o <= '0';
pos_calc_monit1_data_mask_ctl_en_sync0 <= '0';
pos_calc_monit1_data_mask_ctl_en_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit1_data_mask_ctl_en_sync0 <= pos_calc_monit1_data_mask_ctl_en_int;
pos_calc_monit1_data_mask_ctl_en_sync1 <= pos_calc_monit1_data_mask_ctl_en_sync0;
regs_o.monit1_data_mask_ctl_en_o <= pos_calc_monit1_data_mask_ctl_en_sync1;
end if;
end process;
-- MONIT1 Beginning Data Masking Samples
-- asynchronous std_logic_vector register : MONIT1 Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_monit1_data_mask_samples_beg_swb_s0 <= '0';
pos_calc_monit1_data_mask_samples_beg_swb_s1 <= '0';
pos_calc_monit1_data_mask_samples_beg_swb_s2 <= '0';
regs_o.monit1_data_mask_samples_beg_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit1_data_mask_samples_beg_swb_s0 <= pos_calc_monit1_data_mask_samples_beg_swb;
pos_calc_monit1_data_mask_samples_beg_swb_s1 <= pos_calc_monit1_data_mask_samples_beg_swb_s0;
pos_calc_monit1_data_mask_samples_beg_swb_s2 <= pos_calc_monit1_data_mask_samples_beg_swb_s1;
if ((pos_calc_monit1_data_mask_samples_beg_swb_s2 = '0') and (pos_calc_monit1_data_mask_samples_beg_swb_s1 = '1')) then
regs_o.monit1_data_mask_samples_beg_o <= pos_calc_monit1_data_mask_samples_beg_int;
end if;
end if;
end process;
-- MONIT1 Beginning Data Masking Samples
-- asynchronous std_logic_vector register : MONIT1 Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_monit1_data_mask_samples_end_swb_s0 <= '0';
pos_calc_monit1_data_mask_samples_end_swb_s1 <= '0';
pos_calc_monit1_data_mask_samples_end_swb_s2 <= '0';
regs_o.monit1_data_mask_samples_end_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit1_data_mask_samples_end_swb_s0 <= pos_calc_monit1_data_mask_samples_end_swb;
pos_calc_monit1_data_mask_samples_end_swb_s1 <= pos_calc_monit1_data_mask_samples_end_swb_s0;
pos_calc_monit1_data_mask_samples_end_swb_s2 <= pos_calc_monit1_data_mask_samples_end_swb_s1;
if ((pos_calc_monit1_data_mask_samples_end_swb_s2 = '0') and (pos_calc_monit1_data_mask_samples_end_swb_s1 = '1')) then
regs_o.monit1_data_mask_samples_end_o <= pos_calc_monit1_data_mask_samples_end_int;
end if;
end if;
end process;
-- MONIT Synchronizing Trigger Enable
-- synchronizer chain for field : MONIT Synchronizing Trigger Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.monit_tag_en_o <= '0';
pos_calc_monit_tag_en_sync0 <= '0';
pos_calc_monit_tag_en_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit_tag_en_sync0 <= pos_calc_monit_tag_en_int;
pos_calc_monit_tag_en_sync1 <= pos_calc_monit_tag_en_sync0;
regs_o.monit_tag_en_o <= pos_calc_monit_tag_en_sync1;
end if;
end process;
-- MONIT Synchronizing Trigger Delay
-- asynchronous std_logic_vector register : MONIT Synchronizing Trigger Delay (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_monit_tag_dly_swb_s0 <= '0';
pos_calc_monit_tag_dly_swb_s1 <= '0';
pos_calc_monit_tag_dly_swb_s2 <= '0';
regs_o.monit_tag_dly_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit_tag_dly_swb_s0 <= pos_calc_monit_tag_dly_swb;
pos_calc_monit_tag_dly_swb_s1 <= pos_calc_monit_tag_dly_swb_s0;
pos_calc_monit_tag_dly_swb_s2 <= pos_calc_monit_tag_dly_swb_s1;
if ((pos_calc_monit_tag_dly_swb_s2 = '0') and (pos_calc_monit_tag_dly_swb_s1 = '1')) then
regs_o.monit_tag_dly_o <= pos_calc_monit_tag_dly_int;
end if;
end if;
end process;
-- MONIT Desynchronization Counter Reset
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.monit_tag_desync_cnt_rst_o <= '0';
pos_calc_monit_tag_desync_cnt_rst_sync0 <= '0';
pos_calc_monit_tag_desync_cnt_rst_sync1 <= '0';
pos_calc_monit_tag_desync_cnt_rst_sync2 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit_tag_desync_cnt_rst_sync0 <= pos_calc_monit_tag_desync_cnt_rst_int;
pos_calc_monit_tag_desync_cnt_rst_sync1 <= pos_calc_monit_tag_desync_cnt_rst_sync0;
pos_calc_monit_tag_desync_cnt_rst_sync2 <= pos_calc_monit_tag_desync_cnt_rst_sync1;
regs_o.monit_tag_desync_cnt_rst_o <= pos_calc_monit_tag_desync_cnt_rst_sync2 and (not pos_calc_monit_tag_desync_cnt_rst_sync1);
end if;
end process;
-- MONIT Desynchronization Counter
-- asynchronous std_logic_vector register : MONIT Desynchronization Counter (type RO/WO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_monit_tag_desync_cnt_lwb_s0 <= '0';
pos_calc_monit_tag_desync_cnt_lwb_s1 <= '0';
pos_calc_monit_tag_desync_cnt_lwb_s2 <= '0';
pos_calc_monit_tag_desync_cnt_int <= "00000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit_tag_desync_cnt_lwb_s0 <= pos_calc_monit_tag_desync_cnt_lwb;
pos_calc_monit_tag_desync_cnt_lwb_s1 <= pos_calc_monit_tag_desync_cnt_lwb_s0;
pos_calc_monit_tag_desync_cnt_lwb_s2 <= pos_calc_monit_tag_desync_cnt_lwb_s1;
if ((pos_calc_monit_tag_desync_cnt_lwb_s1 = '1') and (pos_calc_monit_tag_desync_cnt_lwb_s2 = '0')) then
pos_calc_monit_tag_desync_cnt_int <= regs_i.monit_tag_desync_cnt_i;
end if;
end if;
end process;
-- MONIT Masking Enable
-- synchronizer chain for field : MONIT Masking Enable (type RW/RO, clk_sys_i <-> fs_clk2x_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.monit_data_mask_ctl_en_o <= '0';
pos_calc_monit_data_mask_ctl_en_sync0 <= '0';
pos_calc_monit_data_mask_ctl_en_sync1 <= '0';
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit_data_mask_ctl_en_sync0 <= pos_calc_monit_data_mask_ctl_en_int;
pos_calc_monit_data_mask_ctl_en_sync1 <= pos_calc_monit_data_mask_ctl_en_sync0;
regs_o.monit_data_mask_ctl_en_o <= pos_calc_monit_data_mask_ctl_en_sync1;
end if;
end process;
-- MONIT Beginning Data Masking Samples
-- asynchronous std_logic_vector register : MONIT Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_monit_data_mask_samples_beg_swb_s0 <= '0';
pos_calc_monit_data_mask_samples_beg_swb_s1 <= '0';
pos_calc_monit_data_mask_samples_beg_swb_s2 <= '0';
regs_o.monit_data_mask_samples_beg_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit_data_mask_samples_beg_swb_s0 <= pos_calc_monit_data_mask_samples_beg_swb;
pos_calc_monit_data_mask_samples_beg_swb_s1 <= pos_calc_monit_data_mask_samples_beg_swb_s0;
pos_calc_monit_data_mask_samples_beg_swb_s2 <= pos_calc_monit_data_mask_samples_beg_swb_s1;
if ((pos_calc_monit_data_mask_samples_beg_swb_s2 = '0') and (pos_calc_monit_data_mask_samples_beg_swb_s1 = '1')) then
regs_o.monit_data_mask_samples_beg_o <= pos_calc_monit_data_mask_samples_beg_int;
end if;
end if;
end process;
-- MONIT Beginning Data Masking Samples
-- asynchronous std_logic_vector register : MONIT Beginning Data Masking Samples (type RW/RO, fs_clk2x_i <-> clk_sys_i)
process (fs_clk2x_i, rst_n_i)
begin
if (rst_n_i = '0') then
pos_calc_monit_data_mask_samples_end_swb_s0 <= '0';
pos_calc_monit_data_mask_samples_end_swb_s1 <= '0';
pos_calc_monit_data_mask_samples_end_swb_s2 <= '0';
regs_o.monit_data_mask_samples_end_o <= "0000000000000000";
elsif rising_edge(fs_clk2x_i) then
pos_calc_monit_data_mask_samples_end_swb_s0 <= pos_calc_monit_data_mask_samples_end_swb;
pos_calc_monit_data_mask_samples_end_swb_s1 <= pos_calc_monit_data_mask_samples_end_swb_s0;
pos_calc_monit_data_mask_samples_end_swb_s2 <= pos_calc_monit_data_mask_samples_end_swb_s1;
if ((pos_calc_monit_data_mask_samples_end_swb_s2 = '0') and (pos_calc_monit_data_mask_samples_end_swb_s1 = '1')) then
regs_o.monit_data_mask_samples_end_o <= pos_calc_monit_data_mask_samples_end_int;
end if;
end if;
end process;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/modules/mixer/mixer.vhd
|
1
|
3912
|
-------------------------------------------------------------------------------
-- Title : BPM Mixer
-- Project :
-------------------------------------------------------------------------------
-- File : mixer.vhd
-- Author : Gustavo BM Bruno
-- Company : LNLS - CNPEM
-- Created : 2014-01-21
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Mixer at input stage for BPM
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-21 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
use work.bpm_cores_pkg.all;
entity mixer is
generic(
g_sin_file : string := "./dds_sin.nif";
g_cos_file : string := "./dds_cos.nif";
g_number_of_points : natural := 6;
g_input_width : natural := 16;
g_dds_width : natural := 16;
g_output_width : natural := 32;
g_tag_width : natural := 1; -- Input data tag width
g_mult_levels : natural := 7
);
port(
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
signal_i : in std_logic_vector(g_input_width-1 downto 0);
valid_i : in std_logic;
tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
I_out : out std_logic_vector(g_output_width-1 downto 0);
I_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
Q_out : out std_logic_vector(g_output_width-1 downto 0);
Q_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
valid_o : out std_logic);
end entity mixer;
architecture rtl of mixer is
signal sine : std_logic_vector(g_dds_width-1 downto 0);
signal cosine : std_logic_vector(g_dds_width-1 downto 0);
signal dds_valid : std_logic;
signal I_valid_out : std_logic;
signal Q_valid_out : std_logic;
begin
cmp_dds : fixed_dds
generic map (
g_number_of_points => g_number_of_points,
g_output_width => g_dds_width,
g_sin_file => g_sin_file,
g_cos_file => g_cos_file)
port map (
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_i,
sin_o => sine,
cos_o => cosine,
valid_o => dds_valid);
cmp_mult_I : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_dds_width,
g_tag_width => g_tag_width,
g_signed => true,
g_p_width => g_output_width,
g_round_convergent => 1)
port map (
a_i => signal_i,
b_i => cosine,
tag_i => tag_i,
valid_i => dds_valid,
p_o => I_out,
valid_o => I_valid_out,
tag_o => I_tag_out,
ce_i => ce_i,
clk_i => clk_i,
rst_i => rst_i);
cmp_mult_Q : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_dds_width,
g_tag_width => g_tag_width,
g_signed => true,
g_p_width => g_output_width,
g_round_convergent => 1)
port map (
a_i => signal_i,
b_i => sine,
tag_i => tag_i,
valid_i => dds_valid,
p_o => Q_out,
valid_o => Q_valid_out,
tag_o => Q_tag_out,
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i);
-- Any valid, either from I or Q is fine.
valid_o <= I_valid_out;
end rtl;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/testbench/mixer/mixer_bench.vhd
|
1
|
4523
|
-------------------------------------------------------------------------------
-- Title : Mixer testbench
-- Project :
-------------------------------------------------------------------------------
-- File : mixer_bench.vhd
-- Author : Gustavo BM Bruno
-- Company : LNLS
-- Created : 2014-01-21
-- Last update: 2015-03-13
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Tests the mixer stage of the BPM DSP chain.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-21 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity mixer_bench is
end mixer_bench;
architecture test of mixer_bench is
constant c_input_freq : real := 112.8e6;
-- constant c_mixer_freq : real := 20.0e6;
constant c_sin_file : string := "./dds_sin.nif";
constant c_cos_file : string := "./dds_cos.nif";
constant c_number_of_points : natural := 35;
constant c_input_width : natural := 16;
constant c_dds_width : natural := 16;
constant c_output_width : natural := 31;
constant clock_period : time := 1.0 sec / (2.0 * c_input_freq);
signal clock : std_logic := '0';
signal adc_data : std_logic_vector(c_input_width-1 downto 0);
signal endoffile : bit := '0';
signal reset : std_logic := '1';
signal I_sig : std_logic_vector(c_output_width-1 downto 0);
signal Q_sig : std_logic_vector(c_output_width-1 downto 0);
component mixer is
generic (
g_sin_file : string;
g_cos_file : string;
g_number_of_points : natural;
g_input_width : natural;
g_dds_width : natural;
g_output_width : natural);
port (
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
signal_i : in std_logic_vector(g_input_width-1 downto 0);
I_out : out std_logic_vector(g_output_width-1 downto 0);
Q_out : out std_logic_vector(g_output_width-1 downto 0));
end component mixer;
begin
clk_gen : process
begin
clock <= '0';
wait for clock_period;
clock <= '1';
wait for clock_period;
end process;
rst_gen : process(clock)
variable clock_count : natural := 4;
begin
if rising_edge(clock) and clock_count /= 0 then
clock_count := clock_count - 1;
if clock_count = 0 then
reset <= '0';
end if;
end if;
end process;
adc_read : process(clock)
file adc_file : text open read_mode is "mixer.samples";
variable cur_line : line;
variable datain : real;
begin
if rising_edge(clock) and reset = '0' then
if not endfile(adc_file) then
readline(adc_file, cur_line);
read(cur_line, datain);
adc_data <= std_logic_vector(to_signed(integer(datain*(2.0**(real(c_input_width)-1.0))-1.0), c_input_width));
else
endoffile <= '1';
end if;
end if;
end process adc_read;
uut : mixer
generic map (
g_sin_file => c_sin_file,
g_cos_file => c_cos_file,
g_number_of_points => c_number_of_points,
g_input_width => c_input_width,
g_dds_width => c_dds_width,
g_output_width => c_output_width)
port map (
rst_i => reset,
clk_i => clock,
ce_i => '1',
signal_i => adc_data,
I_out => I_sig,
Q_out => Q_sig);
signal_write : process(clock)
file mixer_file : text open write_mode is "mixer_out.samples";
variable cur_line : line;
variable I, Q : integer;
begin
if rising_edge(clock) then
if(endoffile = '0') then
I := to_integer(signed(I_sig));
write(cur_line, I);
write(cur_line, string'(" "));
Q := to_integer(signed(Q_sig));
write(cur_line, Q);
writeline(mixer_file, cur_line);
else
assert (false) report "Input file finished." severity failure;
end if;
end if;
end process;
end test;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_fmc516/clk_gen.vhd
|
9
|
1499
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_dsp_fmc516/sys_pll.vhd
|
11
|
6148
|
-- MMCM_BASE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (MMCM_BASE_inst) and/or the port declarations after the
-- code : "=>" declaration maybe changed to properly reference and
-- : connect this function to the design. All inputs and outputs
-- : must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_clkbout_mult_f : real := 5.000;
-- 100 MHz output clock
g_clk0_divide_f : real := 10.000;
-- 200 MHz output clock
g_clk1_divide : integer := 5
);
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end sys_pll;
architecture syn of sys_pll is
signal s_mmcm_fbin : std_logic;
signal s_mmcm_fbout : std_logic;
signal s_clk0 : std_logic;
signal s_clk1 : std_logic;
begin
-- MMCM_BASE: Base Mixed Mode Clock Manager
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
-- Clock PLL
cmp_mmcm : MMCM_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => g_clkbout_mult_f,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => g_clk0_divide_f,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => g_clk1_divide,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => g_clkin_period,
REF_JITTER1 => 0.010,
-- Not used. Just to bypass Xilinx errors
-- Just input g_clkin_period input clock period
CLKIN2_PERIOD => g_clkin_period,
REF_JITTER2 => 0.010
)
port map(
-- Output clocks
CLKFBOUT => s_mmcm_fbout,
CLKFBOUTB => open,
CLKOUT0 => s_clk0,
CLKOUT0B => open,
CLKOUT1 => s_clk1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => s_mmcm_fbin,
CLKIN1 => clk_i,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_o,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst_i
);
-- Global clock buffers for "cmp_mmcm" instance
cmp_clkf_bufg : BUFG
port map(
O => s_mmcm_fbin,
I => s_mmcm_fbout
);
cmp_clkout0_buf : BUFG
port map(
O => clk0_o,
I => s_clk0
);
cmp_clkout1_buf : BUFG
port map(
O => clk1_o,
I => s_clk1
);
end syn;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd
|
11
|
6148
|
-- MMCM_BASE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (MMCM_BASE_inst) and/or the port declarations after the
-- code : "=>" declaration maybe changed to properly reference and
-- : connect this function to the design. All inputs and outputs
-- : must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_clkbout_mult_f : real := 5.000;
-- 100 MHz output clock
g_clk0_divide_f : real := 10.000;
-- 200 MHz output clock
g_clk1_divide : integer := 5
);
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end sys_pll;
architecture syn of sys_pll is
signal s_mmcm_fbin : std_logic;
signal s_mmcm_fbout : std_logic;
signal s_clk0 : std_logic;
signal s_clk1 : std_logic;
begin
-- MMCM_BASE: Base Mixed Mode Clock Manager
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
-- Clock PLL
cmp_mmcm : MMCM_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => g_clkbout_mult_f,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => g_clk0_divide_f,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => g_clk1_divide,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => g_clkin_period,
REF_JITTER1 => 0.010,
-- Not used. Just to bypass Xilinx errors
-- Just input g_clkin_period input clock period
CLKIN2_PERIOD => g_clkin_period,
REF_JITTER2 => 0.010
)
port map(
-- Output clocks
CLKFBOUT => s_mmcm_fbout,
CLKFBOUTB => open,
CLKOUT0 => s_clk0,
CLKOUT0B => open,
CLKOUT1 => s_clk1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => s_mmcm_fbin,
CLKIN1 => clk_i,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_o,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst_i
);
-- Global clock buffers for "cmp_mmcm" instance
cmp_clkf_bufg : BUFG
port map(
O => s_mmcm_fbin,
I => s_mmcm_fbout
);
cmp_clkout0_buf : BUFG
port map(
O => clk0_o,
I => s_clk0
);
cmp_clkout1_buf : BUFG
port map(
O => clk1_o,
I => s_clk1
);
end syn;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd
|
1
|
25998
|
------------------------------------------------------------------------------
-- Title : Wishbone Orbit Interlock Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2022-06-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone wrapper for orbit interlock
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2020-06-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Orbit interlock cores
use work.orbit_intlk_pkg.all;
-- Regs
use work.orbit_intlk_wbgen2_pkg.all;
entity wb_orbit_intlk is
generic
(
-- Wishbone
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_WITH_EXTRA_WB_REG : boolean := false;
-- Position
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_WISHBONE_ADDRESS_WIDTH-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_WISHBONE_DATA_WIDTH-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_WISHBONE_DATA_WIDTH-1 downto 0);
wb_sel_i : in std_logic_vector(c_WISHBONE_DATA_WIDTH/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end wb_orbit_intlk;
architecture rtl of wb_orbit_intlk is
---------------------------------------------------------
-- Constants --
---------------------------------------------------------
constant c_PERIPH_ADDR_SIZE : natural := 4+2;
constant c_INTLK_LMT_WIDTH : natural := 32;
-----------------------------
-- Wishbone Register Interface signals
-----------------------------
-- wb_orbit_intlk reg structure
signal regs_in : t_orbit_intlk_in_registers;
signal regs_out : t_orbit_intlk_out_registers;
-----------------------------
-- Wishbone slave adapter signals/structures
-----------------------------
signal wb_slv_adp_out : t_wishbone_master_out;
signal wb_slv_adp_in : t_wishbone_master_in;
signal resized_addr : std_logic_vector(c_WISHBONE_ADDRESS_WIDTH-1 downto 0);
-----------------------------
-- Orbit Interlock signals
-----------------------------
signal intlk_en_reg : std_logic;
signal intlk_clr_reg : std_logic;
signal intlk_min_sum_en_reg : std_logic;
signal intlk_min_sum_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_en_reg : std_logic;
signal intlk_trans_clr_reg : std_logic;
signal intlk_trans_max_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_max_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_min_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_min_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_ang_en_reg : std_logic;
signal intlk_ang_clr_reg : std_logic;
signal intlk_ang_max_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_ang_max_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_ang_min_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_ang_min_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_bigger_x : std_logic;
signal intlk_trans_bigger_y : std_logic;
signal intlk_trans_bigger_ltc_x : std_logic;
signal intlk_trans_bigger_ltc_y : std_logic;
signal intlk_trans_bigger_any : std_logic;
signal intlk_trans_bigger_ltc : std_logic;
signal intlk_trans_bigger : std_logic;
signal intlk_trans_smaller_x : std_logic;
signal intlk_trans_smaller_y : std_logic;
signal intlk_trans_smaller_ltc_x : std_logic;
signal intlk_trans_smaller_ltc_y : std_logic;
signal intlk_trans_smaller_any : std_logic;
signal intlk_trans_smaller_ltc : std_logic;
signal intlk_trans_smaller : std_logic;
signal intlk_ang_bigger_x : std_logic;
signal intlk_ang_bigger_y : std_logic;
signal intlk_ang_bigger_ltc_x : std_logic;
signal intlk_ang_bigger_ltc_y : std_logic;
signal intlk_ang_bigger_any : std_logic;
signal intlk_ang_bigger_ltc : std_logic;
signal intlk_ang_bigger : std_logic;
signal intlk_ang_smaller_x : std_logic;
signal intlk_ang_smaller_y : std_logic;
signal intlk_ang_smaller_ltc_x : std_logic;
signal intlk_ang_smaller_ltc_y : std_logic;
signal intlk_ang_smaller_any : std_logic;
signal intlk_ang_smaller_ltc : std_logic;
signal intlk_ang_smaller : std_logic;
signal intlk : std_logic;
signal intlk_ltc : std_logic;
component wb_orbit_intlk_regs
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
regs_i : in t_orbit_intlk_in_registers;
regs_o : out t_orbit_intlk_out_registers
);
end component;
begin
-----------------------------
-- Slave adapter for Wishbone Register Interface
-----------------------------
cmp_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_INTERFACE_MODE,
g_slave_granularity => g_ADDRESS_GRANULARITY
)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
master_i => wb_slv_adp_in,
master_o => wb_slv_adp_out,
sl_adr_i => resized_addr,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_rty_o => open,
sl_err_o => open,
sl_stall_o => wb_stall_o
);
-- See wb_orbit_intlk_port.vhd for register bank addresses.
resized_addr(c_periph_addr_size-1 downto 0) <= wb_adr_i(c_periph_addr_size-1 downto 0);
resized_addr(c_wishbone_address_width-1 downto c_PERIPH_ADDR_SIZE) <= (others => '0');
-- Register Bank / Wishbone Interface
cmp_wb_orbit_intlk_regs : wb_orbit_intlk_regs
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_slv_adp_out.adr(3 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
wb_sel_i => wb_slv_adp_out.sel,
wb_stb_i => wb_slv_adp_out.stb,
wb_we_i => wb_slv_adp_out.we,
wb_ack_o => wb_slv_adp_in.ack,
wb_stall_o => wb_slv_adp_in.stall,
fs_clk_i => ref_clk_i,
regs_i => regs_in,
regs_o => regs_out
);
-- Registers assignment
intlk_en_reg <= regs_out.ctrl_en_o;
intlk_clr_reg <= regs_out.ctrl_clr_o;
intlk_min_sum_en_reg <= regs_out.ctrl_min_sum_en_o;
intlk_min_sum_reg <= regs_out.min_sum_o;
intlk_trans_en_reg <= regs_out.ctrl_trans_en_o;
intlk_trans_clr_reg <= regs_out.ctrl_trans_clr_o;
intlk_trans_max_x_reg <= regs_out.trans_max_x_o;
intlk_trans_max_y_reg <= regs_out.trans_max_y_o;
intlk_trans_min_x_reg <= regs_out.trans_min_x_o;
intlk_trans_min_y_reg <= regs_out.trans_min_y_o;
intlk_ang_en_reg <= regs_out.ctrl_ang_en_o;
intlk_ang_clr_reg <= regs_out.ctrl_ang_clr_o;
intlk_ang_max_x_reg <= regs_out.ang_max_x_o;
intlk_ang_max_y_reg <= regs_out.ang_max_y_o;
intlk_ang_min_x_reg <= regs_out.ang_min_x_o;
intlk_ang_min_y_reg <= regs_out.ang_min_y_o;
regs_in.sts_trans_bigger_x_i <= intlk_trans_bigger_x;
regs_in.sts_trans_bigger_y_i <= intlk_trans_bigger_y;
regs_in.sts_trans_bigger_ltc_x_i <= intlk_trans_bigger_ltc_x;
regs_in.sts_trans_bigger_ltc_y_i <= intlk_trans_bigger_ltc_y;
regs_in.sts_trans_bigger_any_i <= intlk_trans_bigger_any;
regs_in.sts_trans_bigger_ltc_i <= intlk_trans_bigger_ltc;
regs_in.sts_trans_bigger_i <= intlk_trans_bigger;
regs_in.sts_trans_smaller_x_i <= intlk_trans_smaller_x;
regs_in.sts_trans_smaller_y_i <= intlk_trans_smaller_y;
regs_in.sts_trans_smaller_ltc_x_i <= intlk_trans_smaller_ltc_x;
regs_in.sts_trans_smaller_ltc_y_i <= intlk_trans_smaller_ltc_y;
regs_in.sts_trans_smaller_any_i <= intlk_trans_smaller_any;
regs_in.sts_trans_smaller_ltc_i <= intlk_trans_smaller_ltc;
regs_in.sts_trans_smaller_i <= intlk_trans_smaller;
regs_in.sts_ang_bigger_x_i <= intlk_ang_bigger_x;
regs_in.sts_ang_bigger_y_i <= intlk_ang_bigger_y;
regs_in.sts_ang_bigger_ltc_x_i <= intlk_ang_bigger_ltc_x;
regs_in.sts_ang_bigger_ltc_y_i <= intlk_ang_bigger_ltc_y;
regs_in.sts_ang_bigger_any_i <= intlk_ang_bigger_any;
regs_in.sts_ang_bigger_ltc_i <= intlk_ang_bigger_ltc;
regs_in.sts_ang_bigger_i <= intlk_ang_bigger;
regs_in.sts_ang_smaller_x_i <= intlk_ang_smaller_x;
regs_in.sts_ang_smaller_y_i <= intlk_ang_smaller_y;
regs_in.sts_ang_smaller_ltc_x_i <= intlk_ang_smaller_ltc_x;
regs_in.sts_ang_smaller_ltc_y_i <= intlk_ang_smaller_ltc_y;
regs_in.sts_ang_smaller_any_i <= intlk_ang_smaller_any;
regs_in.sts_ang_smaller_ltc_i <= intlk_ang_smaller_ltc;
regs_in.sts_ang_smaller_i <= intlk_ang_smaller;
regs_in.sts_intlk_i <= intlk;
regs_in.sts_intlk_ltc_i <= intlk_ltc;
-- Unused wishbone signals
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
cmp_orbit_intlk : orbit_intlk
generic map
(
g_ADC_WIDTH => g_ADC_WIDTH,
g_DECIM_WIDTH => g_DECIM_WIDTH,
g_INTLK_LMT_WIDTH => c_INTLK_LMT_WIDTH
)
port map
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i => ref_rst_n_i,
ref_clk_i => ref_clk_i,
-----------------------------
-- Interlock enable and limits signals
-----------------------------
intlk_en_i => intlk_en_reg,
intlk_clr_i => intlk_clr_reg,
-- Minimum threshold interlock on/off
intlk_min_sum_en_i => intlk_min_sum_en_reg,
-- Minimum threshold to interlock
intlk_min_sum_i => intlk_min_sum_reg,
-- Translation interlock on/off
intlk_trans_en_i => intlk_trans_en_reg,
-- Translation interlock clear
intlk_trans_clr_i => intlk_trans_clr_reg,
intlk_trans_max_x_i => intlk_trans_max_x_reg,
intlk_trans_max_y_i => intlk_trans_max_y_reg,
intlk_trans_min_x_i => intlk_trans_min_x_reg,
intlk_trans_min_y_i => intlk_trans_min_y_reg,
-- Angular interlock on/off
intlk_ang_en_i => intlk_ang_en_reg,
-- Angular interlock clear
intlk_ang_clr_i => intlk_ang_clr_reg,
intlk_ang_max_x_i => intlk_ang_max_x_reg,
intlk_ang_max_y_i => intlk_ang_max_y_reg,
intlk_ang_min_x_i => intlk_ang_min_x_reg,
intlk_ang_min_y_i => intlk_ang_min_y_reg,
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i => fs_clk_ds_i,
adc_ds_ch0_swap_i => adc_ds_ch0_swap_i,
adc_ds_ch1_swap_i => adc_ds_ch1_swap_i,
adc_ds_ch2_swap_i => adc_ds_ch2_swap_i,
adc_ds_ch3_swap_i => adc_ds_ch3_swap_i,
adc_ds_tag_i => adc_ds_tag_i,
adc_ds_swap_valid_i => adc_ds_swap_valid_i,
decim_ds_pos_x_i => decim_ds_pos_x_i,
decim_ds_pos_y_i => decim_ds_pos_y_i,
decim_ds_pos_q_i => decim_ds_pos_q_i,
decim_ds_pos_sum_i => decim_ds_pos_sum_i,
decim_ds_pos_valid_i => decim_ds_pos_valid_i,
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i => fs_clk_us_i,
adc_us_ch0_swap_i => adc_us_ch0_swap_i,
adc_us_ch1_swap_i => adc_us_ch1_swap_i,
adc_us_ch2_swap_i => adc_us_ch2_swap_i,
adc_us_ch3_swap_i => adc_us_ch3_swap_i,
adc_us_tag_i => adc_us_tag_i,
adc_us_swap_valid_i => adc_us_swap_valid_i,
decim_us_pos_x_i => decim_us_pos_x_i,
decim_us_pos_y_i => decim_us_pos_y_i,
decim_us_pos_q_i => decim_us_pos_q_i,
decim_us_pos_sum_i => decim_us_pos_sum_i,
decim_us_pos_valid_i => decim_us_pos_valid_i,
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o => intlk_trans_bigger_x,
intlk_trans_bigger_y_o => intlk_trans_bigger_y,
intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x,
intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y,
intlk_trans_bigger_any_o => intlk_trans_bigger_any,
intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc,
intlk_trans_bigger_o => intlk_trans_bigger,
intlk_trans_smaller_x_o => intlk_trans_smaller_x,
intlk_trans_smaller_y_o => intlk_trans_smaller_y,
intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x,
intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y,
intlk_trans_smaller_any_o => intlk_trans_smaller_any,
intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc,
intlk_trans_smaller_o => intlk_trans_smaller,
intlk_ang_bigger_x_o => intlk_ang_bigger_x,
intlk_ang_bigger_y_o => intlk_ang_bigger_y,
intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x,
intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y,
intlk_ang_bigger_any_o => intlk_ang_bigger_any,
intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc,
intlk_ang_bigger_o => intlk_ang_bigger,
intlk_ang_smaller_x_o => intlk_ang_smaller_x,
intlk_ang_smaller_y_o => intlk_ang_smaller_y,
intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x,
intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y,
intlk_ang_smaller_any_o => intlk_ang_smaller_any,
intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc,
intlk_ang_smaller_o => intlk_ang_smaller,
intlk_ltc_o => intlk_ltc,
intlk_o => intlk
);
-- Output assignments
intlk_trans_bigger_x_o <= intlk_trans_bigger_x;
intlk_trans_bigger_y_o <= intlk_trans_bigger_y;
intlk_trans_bigger_ltc_x_o <= intlk_trans_bigger_ltc_x;
intlk_trans_bigger_ltc_y_o <= intlk_trans_bigger_ltc_y;
intlk_trans_bigger_any_o <= intlk_trans_bigger_any;
intlk_trans_bigger_ltc_o <= intlk_trans_bigger_ltc;
intlk_trans_bigger_o <= intlk_trans_bigger;
intlk_trans_smaller_x_o <= intlk_trans_smaller_x;
intlk_trans_smaller_y_o <= intlk_trans_smaller_y;
intlk_trans_smaller_ltc_x_o <= intlk_trans_smaller_ltc_x;
intlk_trans_smaller_ltc_y_o <= intlk_trans_smaller_ltc_y;
intlk_trans_smaller_any_o <= intlk_trans_smaller_any;
intlk_trans_smaller_ltc_o <= intlk_trans_smaller_ltc;
intlk_trans_smaller_o <= intlk_trans_smaller;
intlk_ang_bigger_x_o <= intlk_ang_bigger_x;
intlk_ang_bigger_y_o <= intlk_ang_bigger_y;
intlk_ang_bigger_ltc_x_o <= intlk_ang_bigger_ltc_x;
intlk_ang_bigger_ltc_y_o <= intlk_ang_bigger_ltc_y;
intlk_ang_bigger_any_o <= intlk_ang_bigger_any;
intlk_ang_bigger_ltc_o <= intlk_ang_bigger_ltc;
intlk_ang_bigger_o <= intlk_ang_bigger;
intlk_ang_smaller_x_o <= intlk_ang_smaller_x;
intlk_ang_smaller_y_o <= intlk_ang_smaller_y;
intlk_ang_smaller_ltc_x_o <= intlk_ang_smaller_ltc_x;
intlk_ang_smaller_ltc_y_o <= intlk_ang_smaller_ltc_y;
intlk_ang_smaller_any_o <= intlk_ang_smaller_any;
intlk_ang_smaller_ltc_o <= intlk_ang_smaller_ltc;
intlk_ang_smaller_o <= intlk_ang_smaller;
intlk_ltc_o <= intlk_ltc;
intlk_o <= intlk;
end rtl;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/top/afc_v3/dbe_pbpm_with_dcc/dbe_pbpm_with_dcc.vhd
|
1
|
19219
|
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC250M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- IP cores constants
use work.ipcores_pkg.all;
-- AFC definitions
use work.afc_base_pkg.all;
entity dbe_pbpm_with_dcc is
generic (
-- Number of P2P GTs
g_NUM_P2P_GTS : integer := 8;
-- Start index of the P2P GTs
g_P2P_GT_START_ID : integer := 0
);
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '0');
p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '1');
p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmc1_adc_cnv_o : out std_logic;
fmc1_adc_sck_o : out std_logic;
fmc1_adc_sck_rtrn_i : in std_logic;
fmc1_adc_sdo1_i : in std_logic;
fmc1_adc_sdo2_i : in std_logic;
fmc1_adc_sdo3_i : in std_logic;
fmc1_adc_sdo4_i : in std_logic;
fmc1_adc_busy_cmn_i : in std_logic;
fmc1_rng_r1_o : out std_logic;
fmc1_rng_r2_o : out std_logic;
fmc1_rng_r3_o : out std_logic;
fmc1_rng_r4_o : out std_logic;
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
-- fmc1_sm_scl_o : out std_logic;
-- fmc1_sm_sda_b : inout std_logic;
fmc1_a_scl_o : out std_logic;
fmc1_a_sda_b : inout std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmc2_adc_cnv_o : out std_logic;
fmc2_adc_sck_o : out std_logic;
fmc2_adc_sck_rtrn_i : in std_logic;
fmc2_adc_sdo1_i : in std_logic;
fmc2_adc_sdo2_i : in std_logic;
fmc2_adc_sdo3_i : in std_logic;
fmc2_adc_sdo4_i : in std_logic;
fmc2_adc_busy_cmn_i : in std_logic;
fmc2_rng_r1_o : out std_logic;
fmc2_rng_r2_o : out std_logic;
fmc2_rng_r3_o : out std_logic;
fmc2_rng_r4_o : out std_logic;
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
-- Connected through FPGA MUX. Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--fmc2_sm_scl_o : out std_logic;
--fmc2_sm_sda_b : inout std_logic;
fmc2_a_scl_o : out std_logic;
fmc2_a_sda_b : inout std_logic
);
end dbe_pbpm_with_dcc;
architecture rtl of dbe_pbpm_with_dcc is
begin
cmp_dbe_bpm_gen : entity work.dbe_bpm_gen
generic map (
g_fmc_adc_type => "FMCPICO_1M",
g_NUM_P2P_GTS => g_NUM_P2P_GTS,
g_P2P_GT_START_ID => g_P2P_GT_START_ID,
g_WITH_P2P_FOFB_DCC => true
)
port map (
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,
afc_fp2_clk1_p_i => afc_fp2_clk1_p_i,
afc_fp2_clk1_n_i => afc_fp2_clk1_n_i,
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i => sys_rst_button_n_i,
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o => trig_dir_o,
trig_b => trig_b,
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i => diag_spi_cs_i,
diag_spi_si_i => diag_spi_si_i,
diag_spi_so_o => diag_spi_so_o,
diag_spi_clk_i => diag_spi_clk_i,
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o,
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b => afc_si57x_scl_b,
afc_si57x_sda_b => afc_si57x_sda_b,
-- Si57x oscillator output enable
afc_si57x_oe_o => afc_si57x_oe_o,
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- PCI clock and reset signals
pcie_clk_p_i => pcie_clk_p_i,
pcie_clk_n_i => pcie_clk_n_i,
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o => leds_o,
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b => board_i2c_scl_b,
board_i2c_sda_b => board_i2c_sda_b,
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o => spi_sclk_o,
-- spi_cs_n_o => spi_cs_n_o,
-- spi_mosi_o => spi_mosi_o,
-- spi_miso_i => spi_miso_i,
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i => p2p_gt_rx_p_i,
p2p_gt_rx_n_i => p2p_gt_rx_n_i,
p2p_gt_tx_p_o => p2p_gt_tx_p_o,
p2p_gt_tx_n_o => p2p_gt_tx_n_o,
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_1_adc_cnv_o => fmc1_adc_cnv_o,
fmcpico_1_adc_sck_o => fmc1_adc_sck_o,
fmcpico_1_adc_sck_rtrn_i => fmc1_adc_sck_rtrn_i,
fmcpico_1_adc_sdo1_i => fmc1_adc_sdo1_i,
fmcpico_1_adc_sdo2_i => fmc1_adc_sdo2_i,
fmcpico_1_adc_sdo3_i => fmc1_adc_sdo3_i,
fmcpico_1_adc_sdo4_i => fmc1_adc_sdo4_i,
fmcpico_1_adc_busy_cmn_i => fmc1_adc_busy_cmn_i,
fmcpico_1_rng_r1_o => fmc1_rng_r1_o,
fmcpico_1_rng_r2_o => fmc1_rng_r2_o,
fmcpico_1_rng_r3_o => fmc1_rng_r3_o,
fmcpico_1_rng_r4_o => fmc1_rng_r4_o,
fmcpico_1_led1_o => fmc1_led1_o,
fmcpico_1_led2_o => fmc1_led2_o,
---- Connected through FPGA MUX. Use board I2C, if needed
--fmcpico_1_sm_scl_o => fmc1_sm_scl_o,
--fmcpico_1_sm_sda_b => fmc1_sm_sda_b,
fmcpico_1_a_scl_o => fmc1_a_scl_o,
fmcpico_1_a_sda_b => fmc1_a_sda_b,
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_2_adc_cnv_o => fmc2_adc_cnv_o,
fmcpico_2_adc_sck_o => fmc2_adc_sck_o,
fmcpico_2_adc_sck_rtrn_i => fmc2_adc_sck_rtrn_i,
fmcpico_2_adc_sdo1_i => fmc2_adc_sdo1_i,
fmcpico_2_adc_sdo2_i => fmc2_adc_sdo2_i,
fmcpico_2_adc_sdo3_i => fmc2_adc_sdo3_i,
fmcpico_2_adc_sdo4_i => fmc2_adc_sdo4_i,
fmcpico_2_adc_busy_cmn_i => fmc2_adc_busy_cmn_i,
fmcpico_2_rng_r1_o => fmc2_rng_r1_o,
fmcpico_2_rng_r2_o => fmc2_rng_r2_o,
fmcpico_2_rng_r3_o => fmc2_rng_r3_o,
fmcpico_2_rng_r4_o => fmc2_rng_r4_o,
fmcpico_2_led1_o => fmc2_led1_o,
fmcpico_2_led2_o => fmc2_led2_o,
-- Connected through FPGA MUX. Use board I2C, if needed
--fmcpico_2_sm_scl_o => fmc2_sm_scl_o,
--fmcpico_2_sm_sda_b => fmc2_sm_sda_b,
fmcpico_2_a_scl_o => fmc2_a_scl_o,
fmcpico_2_a_sda_b => fmc2_a_sda_b
);
end rtl;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/syn/afc_v3/dbe_pbpm/synthesis_descriptor_pkg.vhd
|
7
|
264
|
-- This file will be overwritten prior to synthesis,
-- by hdlmake "syn_pre_cmd" specified on top Manifest.py.
--
-- However, hdlmake requires all files to be present
-- on parsing-time. So, fool the tool with this dummy
-- file so we can bypass this requirement.
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/synthesis_descriptor_pkg.vhd
|
7
|
264
|
-- This file will be overwritten prior to synthesis,
-- by hdlmake "syn_pre_cmd" specified on top Manifest.py.
--
-- However, hdlmake requires all files to be present
-- on parsing-time. So, fool the tool with this dummy
-- file so we can bypass this requirement.
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd
|
1
|
117352
|
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-01
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC130M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-01 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Custom common cores
use work.ifc_common_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- DSP definitions
use work.dsp_cores_pkg.all;
-- BPM definitions
use work.bpm_cores_pkg.all;
-- Genrams
use work.genram_pkg.all;
-- Data Acquisition core
use work.acq_core_pkg.all;
-- PCIe Core
use work.bpm_pcie_ml605_pkg.all;
-- PCIe Core Constants
use work.bpm_pcie_ml605_const_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_dsp is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
rs232_txd_o : out std_logic;
rs232_rxd_i : in std_logic;
--uart_txd_o : out std_logic;
--uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------------------
-- Position Calc signals
-----------------------------------------
-- Uncross signals
clk_swap_o : out std_logic;
clk_swap2x_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
-----------------------------------------
-- General board status
-----------------------------------------
fmc_mmcm_lock_led_o : out std_logic;
fmc_pll_status_led_o : out std_logic;
-----------------------------------------
-- PCIe pins
-----------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_ddr_dq_width-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_ddr_row_width-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_ddr_bank_width-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_ddr_ck_width-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_ddr_ck_width-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_ddr_cke_width-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_ddr_dm_width-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_ddr_odt_width-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_pcie_lanes - 1 downto 0);
-- PCI clock and reset signals
pcie_rst_n_i : in std_logic;
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
--buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_dsp;
architecture rtl of dbe_bpm_dsp is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 11;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon
constant c_masters : natural := 8; -- RS232-Syscon, PCIe
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
--constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
--constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
constant c_dpram_ethbuf_size : natural := 16384/4; -- in 32-bit words (16KB)
constant c_acq_fifo_size : natural := 256;
constant c_acq_addr_width : natural := c_ddr_addr_width;
constant c_acq_ddr_addr_res_width : natural := 32;
constant c_acq_ddr_addr_diff : natural := c_acq_ddr_addr_res_width-c_ddr_addr_width;
constant c_acq_adc_id : natural := 0;
constant c_acq_tbt_amp_id : natural := 1;
constant c_acq_tbt_pos_id : natural := 2;
constant c_acq_fofb_amp_id : natural := 3;
constant c_acq_fofb_pos_id : natural := 4;
constant c_acq_monit_amp_id : natural := 5;
constant c_acq_monit_pos_id : natural := 6;
constant c_acq_monit_1_pos_id : natural := 7;
constant c_acq_pos_ddr3_width : natural := 32;
constant c_acq_num_channels : natural := 8; -- ADC + TBT AMP + TBT POS +
-- FOFB AMP + FOFB POS + MONIT AMP + MONIT POS + MONIT_1 POS
constant c_acq_channels : t_acq_chan_param_array(c_acq_num_channels-1 downto 0) :=
( c_acq_adc_id => (width => to_unsigned(64, c_acq_chan_max_w_log2)),
c_acq_tbt_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_tbt_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_fofb_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_fofb_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_monit_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_monit_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_monit_1_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2))
);
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
-- Number of top level clocks
constant c_num_tlvl_clks : natural := 2; -- CLK_SYS and CLK_200 MHz
constant c_clk_sys_id : natural := 0; -- CLK_SYS and CLK_200 MHz
constant c_clk_200mhz_id : natural := 1; -- CLK_SYS and CLK_200 MHz
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
--constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- FMC130m_4ch
constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- Position CAlC. layout. Regs, SWAP
constant c_pos_calc_core_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000600");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 90KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00100000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"00200000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"00304000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"00305000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"00306000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"00307000"), -- Etherbone control port
7 => f_sdb_embed_bridge(c_pos_calc_core_bridge_sdb,
x"00308000"), -- Position Calc Core control port
8 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"00310000"), -- FMC130m_4ch control port
9 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"00320000"), -- General peripherals control port
10 => f_sdb_embed_device(c_xwb_acq_core_sdb, x"00330000") -- Data Acquisition control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"00300000";
-- FMC ADC data constants
constant c_adc_data_ch0_lsb : natural := 0;
constant c_adc_data_ch0_msb : natural := c_num_adc_bits-1 + c_adc_data_ch0_lsb;
constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1;
constant c_adc_data_ch1_msb : natural := c_num_adc_bits-1 + c_adc_data_ch1_lsb;
constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1;
constant c_adc_data_ch2_msb : natural := c_num_adc_bits-1 + c_adc_data_ch2_lsb;
constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1;
constant c_adc_data_ch3_msb : natural := c_num_adc_bits-1 + c_adc_data_ch3_lsb;
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- PCIe signals
signal wb_ma_pcie_ack_in : std_logic;
signal wb_ma_pcie_dat_in : std_logic_vector(63 downto 0);
signal wb_ma_pcie_addr_out : std_logic_vector(28 downto 0);
signal wb_ma_pcie_dat_out : std_logic_vector(63 downto 0);
signal wb_ma_pcie_we_out : std_logic;
signal wb_ma_pcie_stb_out : std_logic;
signal wb_ma_pcie_sel_out : std_logic;
signal wb_ma_pcie_cyc_out : std_logic;
signal wb_ma_pcie_rst : std_logic;
signal wb_ma_pcie_rstn : std_logic;
signal wb_ma_sladp_pcie_ack_in : std_logic;
signal wb_ma_sladp_pcie_dat_in : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_addr_out : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_dat_out : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_we_out : std_logic;
signal wb_ma_sladp_pcie_stb_out : std_logic;
signal wb_ma_sladp_pcie_sel_out : std_logic_vector(3 downto 0);
signal wb_ma_sladp_pcie_cyc_out : std_logic;
-- PCIe Debug signals
signal dbg_app_addr : std_logic_vector(31 downto 0);
signal dbg_app_cmd : std_logic_vector(2 downto 0);
signal dbg_app_en : std_logic;
signal dbg_app_wdf_data : std_logic_vector(c_ddr_payload_width-1 downto 0);
signal dbg_app_wdf_end : std_logic;
signal dbg_app_wdf_wren : std_logic;
signal dbg_app_wdf_mask : std_logic_vector(c_ddr_payload_width/8-1 downto 0);
signal dbg_app_rd_data : std_logic_vector(c_ddr_payload_width-1 downto 0);
signal dbg_app_rd_data_end : std_logic;
signal dbg_app_rd_data_valid : std_logic;
signal dbg_app_rdy : std_logic;
signal dbg_app_wdf_rdy : std_logic;
signal dbg_ddr_ui_clk : std_logic;
signal dbg_ddr_ui_reset : std_logic;
signal dbg_arb_req : std_logic_vector(1 downto 0);
signal dbg_arb_gnt : std_logic_vector(1 downto 0);
-- To/From Acquisition Core
signal acq_chan_array : t_acq_chan_array(c_acq_num_channels-1 downto 0);
signal bpm_acq_dpram_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal bpm_acq_dpram_valid : std_logic;
signal bpm_acq_ext_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal bpm_acq_ext_valid : std_logic;
signal bpm_acq_ext_addr : std_logic_vector(c_acq_addr_width-1 downto 0);
signal bpm_acq_ext_sof : std_logic;
signal bpm_acq_ext_eof : std_logic;
signal bpm_acq_ext_dreq : std_logic;
signal bpm_acq_ext_stall : std_logic;
signal memc_ui_clk : std_logic;
signal memc_ui_rst : std_logic;
signal memc_ui_rstn : std_logic;
signal memc_cmd_rdy : std_logic;
signal memc_cmd_en : std_logic;
signal memc_cmd_instr : std_logic_vector(2 downto 0);
signal memc_cmd_addr_resized : std_logic_vector(c_acq_ddr_addr_res_width-1 downto 0);
signal memc_cmd_addr : std_logic_vector(c_ddr_addr_width-1 downto 0);
signal memc_wr_en : std_logic;
signal memc_wr_end : std_logic;
signal memc_wr_mask : std_logic_vector(c_ddr_payload_width/8-1 downto 0);
signal memc_wr_data : std_logic_vector(c_ddr_payload_width-1 downto 0);
signal memc_wr_rdy : std_logic;
signal memc_rd_data : std_logic_vector(c_ddr_payload_width-1 downto 0);
signal memc_rd_valid : std_logic;
signal dbg_ddr_rb_data : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal dbg_ddr_rb_addr : std_logic_vector(c_acq_addr_width-1 downto 0);
signal dbg_ddr_rb_valid : std_logic;
-- memory arbiter interface
signal memarb_acc_req : std_logic;
signal memarb_acc_gnt : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal clk_200mhz_rst : std_logic;
signal clk_200mhz_rstn : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- "c_num_tlvl_clks" clocks
signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0);
signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0);
signal rs232_rstn : std_logic;
signal fs_rstn : std_logic;
signal fs_rst2xn : std_logic;
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- ADC clock
signal fs_clk : std_logic;
signal fs_clk2x : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
signal sys_clk_gen_bufg : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC130m_4ch Signals
signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc_mmcm_lock_int : std_logic;
signal fmc_pll_status_int : std_logic;
signal fmc_led1_int : std_logic;
signal fmc_led2_int : std_logic;
signal fmc_led3_int : std_logic;
signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_data_ch0 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch1 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch3 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal fmc_debug : std_logic;
signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_rst2x_n : std_logic_vector(c_num_adc_channels-1 downto 0);
-- fmc130m_4ch Debug
signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
-- Uncross signals
signal flag1_int : std_logic;
signal flag2_int : std_logic;
-- DSP signals
signal dsp_kx : std_logic_vector(24 downto 0);
signal dsp_ky : std_logic_vector(24 downto 0);
signal dsp_ksum : std_logic_vector(24 downto 0);
signal dsp_kx_in : std_logic_vector(24 downto 0);
signal dsp_ky_in : std_logic_vector(24 downto 0);
signal dsp_ksum_in : std_logic_vector(24 downto 0);
signal dsp_del_sig_div_thres_sel : std_logic_vector(1 downto 0);
signal dsp_kx_sel : std_logic_vector(1 downto 0);
signal dsp_ky_sel : std_logic_vector(1 downto 0);
signal dsp_ksum_sel : std_logic_vector(1 downto 0);
signal dsp_del_sig_div_thres : std_logic_vector(25 downto 0);
signal dsp_del_sig_div_thres_in : std_logic_vector(25 downto 0);
signal dsp_dds_config_valid_ch0 : std_logic;
signal dsp_dds_config_valid_ch1 : std_logic;
signal dsp_dds_config_valid_ch2 : std_logic;
signal dsp_dds_config_valid_ch3 : std_logic;
signal dsp_dds_pinc_ch0 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch1 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch2 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch3 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch0 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch1 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch2 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch3 : std_logic_vector(29 downto 0);
signal dsp_adc_ch0_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_valid : std_logic;
signal dsp_mix_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_valid : std_logic;
signal dsp_poly35_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_valid : std_logic;
signal dsp_cic_fofb_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_valid : std_logic;
signal dsp_tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_valid : std_logic;
signal dsp_tbt_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_valid : std_logic;
signal dsp_fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_valid : std_logic;
signal dsp_fofb_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_valid : std_logic;
signal dsp_monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_valid : std_logic;
signal dsp_pos_x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_tbt_valid : std_logic;
signal dsp_pos_x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_fofb_valid : std_logic;
signal dsp_pos_x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_monit_valid : std_logic;
signal dsp_pos_x_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_y_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_q_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_sum_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_monit_1_valid : std_logic;
signal dsp_clk_ce_1 : std_logic;
signal dsp_clk_ce_2 : std_logic;
signal dsp_clk_ce_35 : std_logic;
signal dsp_clk_ce_70 : std_logic;
signal dsp_clk_ce_1390000 : std_logic;
signal dsp_clk_ce_1112 : std_logic;
signal dsp_clk_ce_2224 : std_logic;
signal dsp_clk_ce_11120000 : std_logic;
signal dsp_clk_ce_111200000 : std_logic;
signal dsp_clk_ce_22240000 : std_logic;
signal dsp_clk_ce_222400000 : std_logic;
signal dsp_clk_ce_5000 : std_logic;
signal dsp_clk_ce_556 : std_logic;
signal dsp_clk_ce_2780000 : std_logic;
signal dsp_clk_ce_5560000 : std_logic;
signal dbg_cur_address : std_logic_vector(31 downto 0);
signal dbg_adc_ch0_cond : std_logic_vector(15 downto 0);
signal dbg_adc_ch1_cond : std_logic_vector(15 downto 0);
signal dbg_adc_ch2_cond : std_logic_vector(15 downto 0);
signal dbg_adc_ch3_cond : std_logic_vector(15 downto 0);
-- DDS test
signal dds_data : std_logic_vector(2*c_num_adc_bits-1 downto 0); -- cosine + sine
signal dds_sine : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dds_cosine : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc0 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc1 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc3 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc0_full : std_logic_vector(25 downto 0);
signal synth_adc1_full : std_logic_vector(25 downto 0);
signal synth_adc2_full : std_logic_vector(25 downto 0);
signal synth_adc3_full : std_logic_vector(25 downto 0);
signal dds_sine_gain_ch0 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch1 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch2 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch3 : std_logic_vector(9 downto 0);
signal adc_synth_data_en : std_logic;
signal clk_rffe_swap : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
signal buttons_dummy : std_logic_vector(7 downto 0) := (others => '0');
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
---- Chipscope control signals
--signal CONTROL0 : std_logic_vector(35 downto 0);
--signal CONTROL1 : std_logic_vector(35 downto 0);
--signal CONTROL2 : std_logic_vector(35 downto 0);
--signal CONTROL3 : std_logic_vector(35 downto 0);
--signal CONTROL4 : std_logic_vector(35 downto 0);
--signal CONTROL5 : std_logic_vector(35 downto 0);
--signal CONTROL6 : std_logic_vector(35 downto 0);
--signal CONTROL7 : std_logic_vector(35 downto 0);
--signal CONTROL8 : std_logic_vector(35 downto 0);
--signal CONTROL9 : std_logic_vector(35 downto 0);
--signal CONTROL10 : std_logic_vector(35 downto 0);
--signal CONTROL11 : std_logic_vector(35 downto 0);
--signal CONTROL12 : std_logic_vector(35 downto 0);
---- Chipscope ILA 0 signals
--signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 1 signals
--signal TRIG_ILA1_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA1_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 2 signals
--signal TRIG_ILA2_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA2_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 3 signals
--signal TRIG_ILA3_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA3_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 4 signals
--signal TRIG_ILA4_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA4_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA4_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA4_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA4_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 5 signals
--signal TRIG_ILA5_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA5_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA5_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA5_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA5_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 6 signals
--signal TRIG_ILA6_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA6_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA6_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA6_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA6_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 7 signals
--signal TRIG_ILA7_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA7_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA7_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA7_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA7_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 8 signals
--signal TRIG_ILA8_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA8_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA8_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA8_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA8_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 9 signals
--signal TRIG_ILA9_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA9_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA9_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA9_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA9_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 10 signals
--signal TRIG_ILA10_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA10_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA10_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA10_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA10_4 : std_logic_vector(31 downto 0);
---- Chipscope VIO signals
--signal vio_out : std_logic_vector(255 downto 0);
--signal vio_out_dsp_config : std_logic_vector(255 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic
);
end component;
-- Xilinx PLL
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
component multiplier_16x10_DSP
port (
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(9 downto 0);
p : out std_logic_vector(25 downto 0)
);
end component;
component dds_adc_input
port (
aclk : in std_logic;
m_axis_data_tvalid : out std_logic;
m_axis_data_tdata : out std_logic_vector(31 downto 0)
);
end component;
component chipscope_icon_13_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0);
CONTROL4 : inout std_logic_vector(35 downto 0);
CONTROL5 : inout std_logic_vector(35 downto 0);
CONTROL6 : inout std_logic_vector(35 downto 0);
CONTROL7 : inout std_logic_vector(35 downto 0);
CONTROL8 : inout std_logic_vector(35 downto 0);
CONTROL9 : inout std_logic_vector(35 downto 0);
CONTROL10 : inout std_logic_vector(35 downto 0);
CONTROL11 : inout std_logic_vector(35 downto 0);
CONTROL12 : inout std_logic_vector(35 downto 0)
);
end component;
component chipscope_ila
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(31 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila_1024_5_port
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(31 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_8192_5_port
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(31 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_1024
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_4096
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_65536
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_131072
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(15 downto 0);
trig2 : in std_logic_vector(15 downto 0);
trig3 : in std_logic_vector(15 downto 0);
trig4 : in std_logic_vector(15 downto 0));
end component;
component chipscope_vio_256 is
port (
control : inout std_logic_vector(35 downto 0);
async_out : out std_logic_vector(255 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen,
sys_clk_bufg_o => sys_clk_gen_bufg
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen_bufg,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => c_num_tlvl_clks -- CLK_SYS & CLK_200
)
port map(
--free_clk_i => sys_clk_gen,
free_clk_i => sys_clk_gen_bufg,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(c_clk_sys_id) <= clk_sys;
reset_clks(c_clk_200mhz_id) <= clk_200mhz;
--clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n and
rs232_rstn;-- and wb_ma_pcie_rstn;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
clk_200mhz_rstn <= reset_rstn(c_clk_200mhz_id);
clk_200mhz_rst <= not(reset_rstn(c_clk_200mhz_id));
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
--lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
-- 4 => irq_tx_done, others => '0');
----------------------------------
-- PCIe Core --
----------------------------------
cmp_xwb_bpm_pcie_ml605 : xwb_bpm_pcie_ml605
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE,
g_sim_bypass_init_cal => "OFF"
)
port map (
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- Necessity signals
ddr_clk_p_i => clk_200mhz, --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_clk_n_i => '0', --200 MHz DDR core clock (connect through BUFG or PLL)
pcie_clk_p_i => pcie_clk_p_i, --100 MHz PCIe Clock (connect directly to input pin)
pcie_clk_n_i => pcie_clk_n_i, --100 MHz PCIe Clock
pcie_rst_n_i => pcie_rst_n_i, -- PCIe core reset
-- DDR memory controller interface --
ddr_core_rst_i => clk_sys_rst,
memc_ui_clk_o => memc_ui_clk,
memc_ui_rst_o => memc_ui_rst,
memc_cmd_rdy_o => memc_cmd_rdy,
memc_cmd_en_i => memc_cmd_en,
memc_cmd_instr_i => memc_cmd_instr,
memc_cmd_addr_i => memc_cmd_addr_resized,
memc_wr_en_i => memc_wr_en,
memc_wr_end_i => memc_wr_end,
memc_wr_mask_i => memc_wr_mask,
memc_wr_data_i => memc_wr_data,
memc_wr_rdy_o => memc_wr_rdy,
memc_rd_data_o => memc_rd_data,
memc_rd_valid_o => memc_rd_valid,
---- memory arbiter interface
memarb_acc_req_i => memarb_acc_req,
memarb_acc_gnt_o => memarb_acc_gnt,
-- Wishbone interface --
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
wb_ma_i => cbar_slave_o(0),
wb_ma_o => cbar_slave_i(0),
-- Additional exported signals for instantiation
wb_ma_pcie_rst_o => wb_ma_pcie_rst,
-- Debug signals
dbg_app_addr_o => dbg_app_addr,
dbg_app_cmd_o => dbg_app_cmd,
dbg_app_en_o => dbg_app_en,
dbg_app_wdf_data_o => dbg_app_wdf_data,
dbg_app_wdf_end_o => dbg_app_wdf_end,
dbg_app_wdf_wren_o => dbg_app_wdf_wren,
dbg_app_wdf_mask_o => dbg_app_wdf_mask,
dbg_app_rd_data_o => dbg_app_rd_data,
dbg_app_rd_data_end_o => dbg_app_rd_data_end,
dbg_app_rd_data_valid_o => dbg_app_rd_data_valid,
dbg_app_rdy_o => dbg_app_rdy,
dbg_app_wdf_rdy_o => dbg_app_wdf_rdy,
dbg_ddr_ui_clk_o => dbg_ddr_ui_clk,
dbg_ddr_ui_reset_o => dbg_ddr_ui_reset,
dbg_arb_req_o => dbg_arb_req,
dbg_arb_gnt_o => dbg_arb_gnt
);
wb_ma_pcie_rstn <= not wb_ma_pcie_rst;
----------------------------------
-- RS232 Core --
----------------------------------
cmp_xwb_rs232_syscon : xwb_rs232_syscon
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rstn_i => '1', -- No need for resetting the controller
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rs232_rstn,
-- WISHBONE master
wb_master_i => cbar_slave_o(1),
wb_master_o => cbar_slave_i(1)
);
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
--g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
--g_must_have_init_file => true,
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
---- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
--The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- The FMC130M_4CH is slave 8
cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "VIRTEX6",
g_delay_type => "VAR_LOADABLE",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(8),
wb_slv_o => cbar_master_i(8),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc_adc_pga_o,
fmc_adc_shdn_o => fmc_adc_shdn_o,
fmc_adc_dith_o => fmc_adc_dith_o,
fmc_adc_rand_o => fmc_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc_adc0_clk_i,
fmc_adc0_data_i => fmc_adc0_data_i,
fmc_adc0_of_i => fmc_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc_adc1_clk_i,
fmc_adc1_data_i => fmc_adc1_data_i,
fmc_adc1_of_i => fmc_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc_adc2_clk_i,
fmc_adc2_data_i => fmc_adc2_data_i,
fmc_adc2_of_i => fmc_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc_adc3_clk_i,
fmc_adc3_data_i => fmc_adc3_data_i,
fmc_adc3_of_i => fmc_adc3_of_i,
-- FMC General Status
fmc_prsnt_i => fmc_prsnt_i,
fmc_pg_m2c_i => fmc_pg_m2c_i,
-- Trigger
fmc_trig_dir_o => fmc_trig_dir_o,
fmc_trig_term_o => fmc_trig_term_o,
fmc_trig_val_p_b => fmc_trig_val_p_b,
fmc_trig_val_n_b => fmc_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-- EEPROM
eeprom_scl_pad_b => eeprom_scl_pad_b,
eeprom_sda_pad_b => eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => lm75_scl_pad_b,
lm75_sda_pad_b => lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc_led1_int,
fmc_led2_o => fmc_led2_int,
fmc_led3_o => fmc_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0', -- Unused
fmc_ext_ref_clk2x_i => '0', -- Unused
fmc_ext_ref_mmcm_locked_i => '0', -- Unused
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc_130m_4ch_clk,
adc_clk2x_o => fmc_130m_4ch_clk2x,
adc_rst_n_o => fmc_130m_4ch_rst_n,
adc_rst2x_n_o => fmc_130m_4ch_rst2x_n,
adc_data_o => fmc_130m_4ch_data,
adc_data_valid_o => fmc_130m_4ch_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc_mmcm_lock_int,
fmc_pll_status_o => fmc_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc130m_4ch_in_array,
wbs_source_o => wbs_fmc130m_4ch_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc130m_4ch_debug_valid_int,
fifo_debug_full_o => fmc130m_4ch_debug_full_int,
fifo_debug_empty_o => fmc130m_4ch_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int;
fmc_pll_status_led_o <= fmc_pll_status_int;
fmc_led1_o <= fmc_led1_int;
fmc_led2_o <= fmc_led2_int;
fmc_led3_o <= fmc_led3_int;
adc_data_ch0 <= fmc_130m_4ch_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
adc_data_ch1 <= fmc_130m_4ch_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
adc_data_ch2 <= fmc_130m_4ch_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
adc_data_ch3 <= fmc_130m_4ch_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fs_clk <= fmc_130m_4ch_clk(c_adc_ref_clk);
fs_rstn <= fmc_130m_4ch_rst_n(c_adc_ref_clk);
fs_clk2x <= fmc_130m_4ch_clk2x(c_adc_ref_clk);
fs_rst2xn <= fmc_130m_4ch_rst2x_n(c_adc_ref_clk);
--led_south_o <= fmc_led1_int;
--led_east_o <= fmc_led2_int;
--led_north_o <= fmc_led3_int;
----------------------------------------------------------------------
-- DSP Chain Core --
----------------------------------------------------------------------
-- Testing with internal DDS
cmp_dds_adc_input : dds_adc_input
port map (
aclk => fs_clk,
m_axis_data_tvalid => open,
m_axis_data_tdata => dds_data
);
dds_sine <= dds_data(31 downto 16);
dds_cosine <= dds_data(15 downto 0);
cmp_multiplier_16x10_DSP_ch0 : multiplier_16x10_DSP
port map (
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch0,
p => synth_adc0_full
);
synth_adc0 <= synth_adc0_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch1 : multiplier_16x10_DSP
port map(
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch1,
p => synth_adc1_full
);
synth_adc1 <= synth_adc1_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch2 : multiplier_16x10_DSP
port map(
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch2,
p => synth_adc2_full
);
synth_adc2 <= synth_adc2_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch3 : multiplier_16x10_DSP
port map (
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch3,
p => synth_adc3_full
);
synth_adc3 <= synth_adc3_full(25 downto 10);
-- MUX between sinthetic data and real ADC data
adc_ch0_data <= synth_adc0 when adc_synth_data_en = '1' else adc_data_ch0;
adc_ch1_data <= synth_adc1 when adc_synth_data_en = '1' else adc_data_ch1;
adc_ch2_data <= synth_adc2 when adc_synth_data_en = '1' else adc_data_ch2;
adc_ch3_data <= synth_adc3 when adc_synth_data_en = '1' else adc_data_ch3;
-- Position calc core is slave 7
cmp_xwb_position_calc_core : xwb_position_calc_core
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_with_switching => 0
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys, -- Wishbone clock
fs_rst_n_i => fs_rstn,
fs_rst2x_n_i => fs_rst2xn,
fs_clk_i => fs_clk, -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i => fs_clk2x, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- Raw ADC signals
-----------------------------
--adc_ch0_i => adc_ch0_data_uncross,
--adc_ch1_i => adc_ch1_data_uncross,
--adc_ch2_i => adc_ch2_data_uncross,
--adc_ch3_i => adc_ch3_data_uncross,
adc_ch0_i => adc_ch0_data,
adc_ch1_i => adc_ch1_data,
adc_ch2_i => adc_ch2_data,
adc_ch3_i => adc_ch3_data,
-------------------------------
---- DSP config parameter signals
-------------------------------
--kx_i => dsp_kx,
--ky_i => dsp_ky,
--ksum_i => dsp_ksum,
--
--del_sig_div_fofb_thres_i => dsp_del_sig_div_thres,
--del_sig_div_tbt_thres_i => dsp_del_sig_div_thres,
--del_sig_div_monit_thres_i => dsp_del_sig_div_thres,
--
--dds_config_valid_ch0_i => dsp_dds_config_valid_ch0,
--dds_config_valid_ch1_i => dsp_dds_config_valid_ch1,
--dds_config_valid_ch2_i => dsp_dds_config_valid_ch2,
--dds_config_valid_ch3_i => dsp_dds_config_valid_ch3,
--dds_pinc_ch0_i => dsp_dds_pinc_ch0,
--dds_pinc_ch1_i => dsp_dds_pinc_ch1,
--dds_pinc_ch2_i => dsp_dds_pinc_ch2,
--dds_pinc_ch3_i => dsp_dds_pinc_ch3,
--dds_poff_ch0_i => dsp_dds_poff_ch0,
--dds_poff_ch1_i => dsp_dds_poff_ch1,
--dds_poff_ch2_i => dsp_dds_poff_ch2,
--dds_poff_ch3_i => dsp_dds_poff_ch3,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o => dsp_adc_ch0_data,
adc_ch1_dbg_data_o => dsp_adc_ch1_data,
adc_ch2_dbg_data_o => dsp_adc_ch2_data,
adc_ch3_dbg_data_o => dsp_adc_ch3_data,
bpf_ch0_o => dsp_bpf_ch0,
--bpf_ch1_o => out std_logic_vector(23 downto 0);
bpf_ch2_o => dsp_bpf_ch2,
--bpf_ch3_o => out std_logic_vector(23 downto 0);
bpf_valid_o => dsp_bpf_valid,
mix_ch0_i_o => dsp_mix_ch0,
--mix_ch0_q_o => out std_logic_vector(23 downto 0);
--mix_ch1_i_o => out std_logic_vector(23 downto 0);
--mix_ch1_q_o => out std_logic_vector(23 downto 0);
mix_ch2_i_o => dsp_mix_ch2,
--mix_ch2_q_o => out std_logic_vector(23 downto 0);
--mix_ch3_i_o => out std_logic_vector(23 downto 0);
--mix_ch3_q_o => out std_logic_vector(23 downto 0);
mix_valid_o => dsp_mix_valid,
tbt_decim_ch0_i_o => dsp_poly35_ch0,
--tbt_decim_ch0_i_o => open,
--poly35_ch0_q_o => out std_logic_vector(23 downto 0);
--poly35_ch1_i_o => out std_logic_vector(23 downto 0);
--poly35_ch1_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o => dsp_poly35_ch2,
--tbt_decim_ch2_i_o => open,
--poly35_ch2_q_o => out std_logic_vector(23 downto 0);
--poly35_ch3_i_o => out std_logic_vector(23 downto 0);
--poly35_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_valid_o => dsp_poly35_valid,
--tbt_decim_q_ch01_incorrect_o => dsp_tbt_decim_q_ch01_incorrect,
--tbt_decim_q_ch23_incorrect_o => dsp_tbt_decim_q_ch23_incorrect,
tbt_amp_ch0_o => dsp_tbt_amp_ch0,
tbt_amp_ch1_o => dsp_tbt_amp_ch1,
tbt_amp_ch2_o => dsp_tbt_amp_ch2,
tbt_amp_ch3_o => dsp_tbt_amp_ch3,
tbt_amp_valid_o => dsp_tbt_amp_valid,
tbt_pha_ch0_o => dsp_tbt_pha_ch0,
tbt_pha_ch1_o => dsp_tbt_pha_ch1,
tbt_pha_ch2_o => dsp_tbt_pha_ch2,
tbt_pha_ch3_o => dsp_tbt_pha_ch3,
tbt_pha_valid_o => dsp_tbt_pha_valid,
fofb_decim_ch0_i_o => dsp_cic_fofb_ch0, --out std_logic_vector(23 downto 0);
--cic_fofb_ch0_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_q_o => out std_logic_vector(24 downto 0);
fofb_decim_ch2_i_o => dsp_cic_fofb_ch2, --out std_logic_vector(23 downto 0);
--cic_fofb_ch2_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_q_o => out std_logic_vector(24 downto 0);
fofb_decim_valid_o => dsp_cic_fofb_valid,
fofb_amp_ch0_o => dsp_fofb_amp_ch0,
fofb_amp_ch1_o => dsp_fofb_amp_ch1,
fofb_amp_ch2_o => dsp_fofb_amp_ch2,
fofb_amp_ch3_o => dsp_fofb_amp_ch3,
fofb_amp_valid_o => dsp_fofb_amp_valid,
fofb_pha_ch0_o => dsp_fofb_pha_ch0,
fofb_pha_ch1_o => dsp_fofb_pha_ch1,
fofb_pha_ch2_o => dsp_fofb_pha_ch2,
fofb_pha_ch3_o => dsp_fofb_pha_ch3,
fofb_pha_valid_o => dsp_fofb_pha_valid,
monit_amp_ch0_o => dsp_monit_amp_ch0,
monit_amp_ch1_o => dsp_monit_amp_ch1,
monit_amp_ch2_o => dsp_monit_amp_ch2,
monit_amp_ch3_o => dsp_monit_amp_ch3,
monit_amp_valid_o => dsp_monit_amp_valid,
pos_x_tbt_o => dsp_pos_x_tbt,
pos_y_tbt_o => dsp_pos_y_tbt,
pos_q_tbt_o => dsp_pos_q_tbt,
pos_sum_tbt_o => dsp_pos_sum_tbt,
pos_tbt_valid_o => dsp_pos_tbt_valid,
pos_x_fofb_o => dsp_pos_x_fofb,
pos_y_fofb_o => dsp_pos_y_fofb,
pos_q_fofb_o => dsp_pos_q_fofb,
pos_sum_fofb_o => dsp_pos_sum_fofb,
pos_fofb_valid_o => dsp_pos_fofb_valid,
pos_x_monit_o => dsp_pos_x_monit,
pos_y_monit_o => dsp_pos_y_monit,
pos_q_monit_o => dsp_pos_q_monit,
pos_sum_monit_o => dsp_pos_sum_monit,
pos_monit_valid_o => dsp_pos_monit_valid,
pos_x_monit_1_o => dsp_pos_x_monit_1,
pos_y_monit_1_o => dsp_pos_y_monit_1,
pos_q_monit_1_o => dsp_pos_q_monit_1,
pos_sum_monit_1_o => dsp_pos_sum_monit_1,
pos_monit_1_valid_o => dsp_pos_monit_1_valid,
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o => clk_rffe_swap,
flag1_o => flag1_int,
flag2_o => flag2_int,
ctrl1_o => open,
ctrl2_o => open,
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o => dsp_clk_ce_1,
clk_ce_1112_o => dsp_clk_ce_1112,
clk_ce_11120000_o => dsp_clk_ce_11120000,
clk_ce_1390000_o => dsp_clk_ce_1390000,
clk_ce_2_o => dsp_clk_ce_2,
clk_ce_2224_o => dsp_clk_ce_2224,
clk_ce_22240000_o => dsp_clk_ce_22240000,
clk_ce_2780000_o => dsp_clk_ce_2780000,
clk_ce_35_o => dsp_clk_ce_35,
clk_ce_5000_o => dsp_clk_ce_5000,
clk_ce_556_o => dsp_clk_ce_556,
clk_ce_5560000_o => dsp_clk_ce_5560000,
clk_ce_70_o => dsp_clk_ce_70,
dbg_cur_address_o => dbg_cur_address,
dbg_adc_ch0_cond_o => dbg_adc_ch0_cond,
dbg_adc_ch1_cond_o => dbg_adc_ch1_cond,
dbg_adc_ch2_cond_o => dbg_adc_ch2_cond,
dbg_adc_ch3_cond_o => dbg_adc_ch3_cond
);
flag1_o <= flag1_int;
flag2_o <= flag2_int;
-- There is no clk_swap2x_o, so we just output the same as clk_swap_o
clk_swap_o <= clk_rffe_swap;
clk_swap2x_o <= clk_rffe_swap;
-- The board peripherals components is slave 9
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
--uart_rxd_i => uart_rxd_i,
--uart_txd_o => uart_txd_o,
uart_rxd_i => '1',
uart_txd_o => open,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
--button_in_i => buttons_i,
button_in_i => buttons_dummy,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(9),
slave_o => cbar_master_i(9)
);
leds_o <= gpio_leds_int;
--------------------
-- ADC data
--------------------
acq_chan_array(c_acq_adc_id).val_low <= dsp_adc_ch3_data &
dsp_adc_ch2_data &
dsp_adc_ch1_data &
dsp_adc_ch0_data;
acq_chan_array(c_acq_adc_id).val_high <= (others => '0');
acq_chan_array(c_acq_adc_id).dvalid <= '1';
acq_chan_array(c_acq_adc_id).trig <= '0';
--------------------
-- TBT AMP data
--------------------
acq_chan_array(c_acq_tbt_amp_id).val_low <= std_logic_vector(resize(signed(dsp_tbt_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp_tbt_amp_ch0), 32));
acq_chan_array(c_acq_tbt_amp_id).val_high <= std_logic_vector(resize(signed(dsp_tbt_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp_tbt_amp_ch2), 32));
acq_chan_array(c_acq_tbt_amp_id).dvalid <= dsp_tbt_amp_valid;
acq_chan_array(c_acq_tbt_amp_id).trig <= '0';
--------------------
-- TBT POS data
--------------------
acq_chan_array(c_acq_tbt_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_tbt), 32)) &
std_logic_vector(resize(signed(dsp_pos_x_tbt), 32));
acq_chan_array(c_acq_tbt_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_tbt), 32)) &
std_logic_vector(resize(signed(dsp_pos_q_tbt), 32));
acq_chan_array(c_acq_tbt_pos_id).dvalid <= dsp_pos_tbt_valid;
acq_chan_array(c_acq_tbt_pos_id).trig <= '0';
--------------------
-- FOFB AMP data
--------------------
acq_chan_array(c_acq_fofb_amp_id).val_low <= std_logic_vector(resize(signed(dsp_fofb_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp_fofb_amp_ch0), 32));
acq_chan_array(c_acq_fofb_amp_id).val_high <= std_logic_vector(resize(signed(dsp_fofb_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp_fofb_amp_ch2), 32));
acq_chan_array(c_acq_fofb_amp_id).dvalid <= dsp_fofb_amp_valid;
acq_chan_array(c_acq_fofb_amp_id).trig <= '0';
--------------------
-- FOFB POS data
--------------------
acq_chan_array(c_acq_fofb_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_fofb), 32)) &
std_logic_vector(resize(signed(dsp_pos_x_fofb), 32));
acq_chan_array(c_acq_fofb_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_fofb), 32)) &
std_logic_vector(resize(signed(dsp_pos_q_fofb), 32));
acq_chan_array(c_acq_fofb_pos_id).dvalid <= dsp_pos_fofb_valid;
acq_chan_array(c_acq_fofb_pos_id).trig <= '0';
--------------------
-- MONIT AMP data
--------------------
acq_chan_array(c_acq_monit_amp_id).val_low <= std_logic_vector(resize(signed(dsp_monit_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp_monit_amp_ch0), 32));
acq_chan_array(c_acq_monit_amp_id).val_high <= std_logic_vector(resize(signed(dsp_monit_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp_monit_amp_ch2), 32));
acq_chan_array(c_acq_monit_amp_id).dvalid <= dsp_monit_amp_valid;
acq_chan_array(c_acq_monit_amp_id).trig <= '0';
--------------------
-- MONIT POS data
--------------------
acq_chan_array(c_acq_monit_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_monit), 32)) &
std_logic_vector(resize(signed(dsp_pos_x_monit), 32));
acq_chan_array(c_acq_monit_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_monit), 32)) &
std_logic_vector(resize(signed(dsp_pos_q_monit), 32));
acq_chan_array(c_acq_monit_pos_id).dvalid <= dsp_pos_monit_valid;
acq_chan_array(c_acq_monit_pos_id).trig <= '0';
--------------------
-- MONIT1 POS data
--------------------
acq_chan_array(c_acq_monit_1_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_monit_1), 32)) &
std_logic_vector(resize(signed(dsp_pos_x_monit_1), 32));
acq_chan_array(c_acq_monit_1_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_monit_1), 32)) &
std_logic_vector(resize(signed(dsp_pos_q_monit_1), 32));
acq_chan_array(c_acq_monit_1_pos_id).dvalid <= dsp_pos_monit_1_valid;
acq_chan_array(c_acq_monit_1_pos_id).trig <= '0';
-- The xwb_acq_core is slave 9
cmp_xwb_acq_core : xwb_acq_core
generic map
(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_acq_addr_width => c_acq_addr_width,
g_acq_num_channels => c_acq_num_channels,
g_acq_channels => c_acq_channels,
g_ddr_payload_width => c_ddr_payload_width,
g_ddr_dq_width => c_ddr_dq_width,
g_ddr_addr_width => c_ddr_addr_width,
--g_multishot_ram_size => 2048,
g_fifo_fc_size => c_acq_fifo_size -- avoid fifo overflow
--g_sim_readback => false
)
port map
(
fs_clk_i => fmc_130m_4ch_clk(c_adc_ref_clk),
fs_ce_i => '1',
fs_rst_n_i => fmc_130m_4ch_rst_n(c_adc_ref_clk),
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
-- From DDR3 Controller
ext_clk_i => memc_ui_clk,
ext_rst_n_i => memc_ui_rstn,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(10),
wb_slv_o => cbar_master_i(10),
-----------------------------
-- External Interface
-----------------------------
acq_chan_array_i => acq_chan_array,
-----------------------------
-- DRRAM Interface
-----------------------------
dpram_dout_o => bpm_acq_dpram_dout , -- to chipscope
dpram_valid_o => bpm_acq_dpram_valid, -- to chipscope
-----------------------------
-- External Interface (w/ FLow Control)
-----------------------------
ext_dout_o => bpm_acq_ext_dout, -- to chipscope
ext_valid_o => bpm_acq_ext_valid, -- to chipscope
ext_addr_o => bpm_acq_ext_addr, -- to chipscope
ext_sof_o => bpm_acq_ext_sof, -- to chipscope
ext_eof_o => bpm_acq_ext_eof, -- to chipscope
ext_dreq_o => bpm_acq_ext_dreq, -- to chipscope
ext_stall_o => bpm_acq_ext_stall, -- to chipscope
-----------------------------
-- DDR3 SDRAM Interface
-----------------------------
ui_app_addr_o => memc_cmd_addr,
ui_app_cmd_o => memc_cmd_instr,
ui_app_en_o => memc_cmd_en,
ui_app_rdy_i => memc_cmd_rdy,
ui_app_wdf_data_o => memc_wr_data,
ui_app_wdf_end_o => memc_wr_end,
ui_app_wdf_mask_o => memc_wr_mask,
ui_app_wdf_wren_o => memc_wr_en,
ui_app_wdf_rdy_i => memc_wr_rdy,
ui_app_rd_data_i => memc_rd_data, -- not used!
ui_app_rd_data_end_i => '0', -- not used!
ui_app_rd_data_valid_i => memc_rd_valid, -- not used!
-- DDR3 arbitrer for multiple accesses
ui_app_req_o => memarb_acc_req,
ui_app_gnt_i => memarb_acc_gnt,
-----------------------------
-- Debug Interface
-----------------------------
dbg_ddr_rb_data_o => dbg_ddr_rb_data,
dbg_ddr_rb_addr_o => dbg_ddr_rb_addr,
dbg_ddr_rb_valid_o => dbg_ddr_rb_valid
);
memc_ui_rstn <= not(memc_ui_rst);
memc_cmd_addr_resized <= f_gen_std_logic_vector(c_acq_ddr_addr_diff, '0') &
memc_cmd_addr;
---- Chipscope Analysis
--cmp_chipscope_icon_13 : chipscope_icon_13_port
--port map (
-- CONTROL0 => CONTROL0,
-- CONTROL1 => CONTROL1,
-- CONTROL2 => CONTROL2,
-- CONTROL3 => CONTROL3,
-- CONTROL4 => CONTROL4,
-- CONTROL5 => CONTROL5,
-- CONTROL6 => CONTROL6,
-- CONTROL7 => CONTROL7,
-- CONTROL8 => CONTROL8,
-- CONTROL9 => CONTROL9,
-- CONTROL10 => CONTROL10,
-- CONTROL11 => CONTROL11,
-- CONTROL12 => CONTROL12
--);
----cmp_chipscope_ila_0_adc : chipscope_ila
--cmp_chipscope_ila_adc : chipscope_ila_8192_5_port
--port map (
-- CONTROL => CONTROL0,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA0_0,
-- TRIG1 => TRIG_ILA0_1,
-- TRIG2 => TRIG_ILA0_2,
-- TRIG3 => TRIG_ILA0_3,
-- TRIG4 => TRIG_ILA0_4
--);
---- ADC Data
--TRIG_ILA0_0 <= dsp_adc_ch1_data & dsp_adc_ch0_data;
--TRIG_ILA0_1 <= dsp_adc_ch3_data & dsp_adc_ch2_data;
--TRIG_ILA0_2 <= dbg_adc_ch1_cond & dbg_adc_ch0_cond;
--TRIG_ILA0_3 <= dbg_adc_ch3_cond & dbg_adc_ch2_cond;
--TRIG_ILA0_4(dbg_cur_address'left downto 0)
-- <= dbg_cur_address;
---- Mix and BPF data
--cmp_chipscope_ila_1024_bpf_mix : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL1,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3,
-- TRIG4 => TRIG_ILA1_4
--);
--TRIG_ILA1_0(0) <= dsp_bpf_valid;
--TRIG_ILA1_0(1) <= '0';
--TRIG_ILA1_0(2) <= '0';
--TRIG_ILA1_0(3) <= '0';
--TRIG_ILA1_0(4) <= '0';
--TRIG_ILA1_0(5) <= '0';
--TRIG_ILA1_0(6) <= '0';
--TRIG_ILA1_1(dsp_bpf_ch0'left downto 0) <= dsp_bpf_ch0;
--TRIG_ILA1_2(dsp_bpf_ch2'left downto 0) <= dsp_bpf_ch2;
--TRIG_ILA1_3(dsp_mix_ch0'left downto 0) <= dsp_mix_ch0;
--TRIG_ILA1_4(dsp_mix_ch2'left downto 0) <= dsp_mix_ch2;
----TBT amplitudes data
--cmp_chipscope_ila_1024_tbt_amp : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL2,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA2_0,
-- TRIG1 => TRIG_ILA2_1,
-- TRIG2 => TRIG_ILA2_2,
-- TRIG3 => TRIG_ILA2_3,
-- TRIG4 => TRIG_ILA2_4
--);
--TRIG_ILA2_0(0) <= dsp_tbt_amp_valid;
--TRIG_ILA2_0(1) <= '0';
--TRIG_ILA2_0(2) <= '0';
--TRIG_ILA2_0(3) <= '0';
--TRIG_ILA2_0(4) <= '0';
--TRIG_ILA2_0(5) <= '0';
--TRIG_ILA2_0(6) <= '0';
--TRIG_ILA2_1(dsp_tbt_amp_ch0'left downto 0) <= dsp_tbt_amp_ch0;
--TRIG_ILA2_2(dsp_tbt_amp_ch1'left downto 0) <= dsp_tbt_amp_ch1;
--TRIG_ILA2_3(dsp_tbt_amp_ch2'left downto 0) <= dsp_tbt_amp_ch2;
--TRIG_ILA2_4(dsp_tbt_amp_ch3'left downto 0) <= dsp_tbt_amp_ch3;
---- TBT position data
--cmp_chipscope_ila_1024_tbt_pos : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL3,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA3_0,
-- TRIG1 => TRIG_ILA3_1,
-- TRIG2 => TRIG_ILA3_2,
-- TRIG3 => TRIG_ILA3_3,
-- TRIG4 => TRIG_ILA3_4
--);
--TRIG_ILA3_0(0) <= dsp_pos_tbt_valid;
--TRIG_ILA3_0(1) <= '0';
--TRIG_ILA3_0(2) <= '0';
--TRIG_ILA3_0(3) <= '0';
--TRIG_ILA3_0(4) <= '0';
--TRIG_ILA3_0(5) <= '0';
--TRIG_ILA3_0(6) <= '0';
--TRIG_ILA3_1(dsp_pos_x_tbt'left downto 0) <= dsp_pos_x_tbt;
--TRIG_ILA3_2(dsp_pos_y_tbt'left downto 0) <= dsp_pos_y_tbt;
--TRIG_ILA3_3(dsp_pos_q_tbt'left downto 0) <= dsp_pos_q_tbt;
--TRIG_ILA3_4(dsp_pos_sum_tbt'left downto 0) <= dsp_pos_sum_tbt;
---- FOFB amplitudes data
--cmp_chipscope_ila_1024_fofb_amp : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL4,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA4_0,
-- TRIG1 => TRIG_ILA4_1,
-- TRIG2 => TRIG_ILA4_2,
-- TRIG3 => TRIG_ILA4_3,
-- TRIG4 => TRIG_ILA4_4
--);
--TRIG_ILA4_0(0) <= dsp_fofb_amp_valid;
--TRIG_ILA4_0(1) <= '0';
--TRIG_ILA4_0(2) <= '0';
--TRIG_ILA4_0(3) <= '0';
--TRIG_ILA4_0(4) <= '0';
--TRIG_ILA4_0(5) <= '0';
--TRIG_ILA4_0(6) <= '0';
--TRIG_ILA4_1(dsp_fofb_amp_ch0'left downto 0) <= dsp_fofb_amp_ch0;
--TRIG_ILA4_2(dsp_fofb_amp_ch1'left downto 0) <= dsp_fofb_amp_ch1;
--TRIG_ILA4_3(dsp_fofb_amp_ch2'left downto 0) <= dsp_fofb_amp_ch2;
--TRIG_ILA4_4(dsp_fofb_amp_ch3'left downto 0) <= dsp_fofb_amp_ch3;
---- FOFB position data
--cmp_chipscope_ila_1024_fofb_pos : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL5,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA5_0,
-- TRIG1 => TRIG_ILA5_1,
-- TRIG2 => TRIG_ILA5_2,
-- TRIG3 => TRIG_ILA5_3,
-- TRIG4 => TRIG_ILA5_4
--);
--TRIG_ILA5_0(0) <= dsp_pos_fofb_valid;
--TRIG_ILA5_0(1) <= '0';
--TRIG_ILA5_0(2) <= '0';
--TRIG_ILA5_0(3) <= '0';
--TRIG_ILA5_0(4) <= '0';
--TRIG_ILA5_0(5) <= '0';
--TRIG_ILA5_0(6) <= '0';
--TRIG_ILA5_1(dsp_pos_x_fofb'left downto 0) <= dsp_pos_x_fofb;
--TRIG_ILA5_2(dsp_pos_y_fofb'left downto 0) <= dsp_pos_y_fofb;
--TRIG_ILA5_3(dsp_pos_q_fofb'left downto 0) <= dsp_pos_q_fofb;
--TRIG_ILA5_4(dsp_pos_sum_fofb'left downto 0) <= dsp_pos_sum_fofb;
---- Monitoring position amplitude
--cmp_chipscope_ila_1024_monit_amp : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL6,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA6_0,
-- TRIG1 => TRIG_ILA6_1,
-- TRIG2 => TRIG_ILA6_2,
-- TRIG3 => TRIG_ILA6_3,
-- TRIG4 => TRIG_ILA6_4
--);
--TRIG_ILA6_0(0) <= dsp_monit_amp_valid;
--TRIG_ILA6_0(1) <= '0';
--TRIG_ILA6_0(2) <= '0';
--TRIG_ILA6_0(3) <= '0';
--TRIG_ILA6_0(4) <= '0';
--TRIG_ILA6_0(5) <= '0';
--TRIG_ILA6_0(6) <= '0';
--TRIG_ILA6_1(dsp_monit_amp_ch0'left downto 0) <= dsp_monit_amp_ch0;
--TRIG_ILA6_2(dsp_monit_amp_ch1'left downto 0) <= dsp_monit_amp_ch1;
--TRIG_ILA6_3(dsp_monit_amp_ch2'left downto 0) <= dsp_monit_amp_ch2;
--TRIG_ILA6_4(dsp_monit_amp_ch3'left downto 0) <= dsp_monit_amp_ch3;
---- Monitoring position data
---- cmp_chipscope_ila_4096_monit_pos : chipscope_ila_4096
--cmp_chipscope_ila_1024_monit_pos : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL7,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA7_0,
-- TRIG1 => TRIG_ILA7_1,
-- TRIG2 => TRIG_ILA7_2,
-- TRIG3 => TRIG_ILA7_3,
-- TRIG4 => TRIG_ILA7_4
--);
--TRIG_ILA7_0(0) <= dsp_pos_monit_valid;
--TRIG_ILA7_0(1) <= '0';
--TRIG_ILA7_0(2) <= '0';
--TRIG_ILA7_0(3) <= '0';
--TRIG_ILA7_0(4) <= '0';
--TRIG_ILA7_0(5) <= '0';
--TRIG_ILA7_0(6) <= '0';
--TRIG_ILA7_1(dsp_pos_x_monit'left downto 0) <= dsp_pos_x_monit;
--TRIG_ILA7_2(dsp_pos_y_monit'left downto 0) <= dsp_pos_y_monit;
--TRIG_ILA7_3(dsp_pos_q_monit'left downto 0) <= dsp_pos_q_monit;
--TRIG_ILA7_4(dsp_pos_sum_monit'left downto 0) <= dsp_pos_sum_monit;
---- Monitoring 1 position data
--cmp_chipscope_ila_1024_monit_pos_1 : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL8,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA8_0,
-- TRIG1 => TRIG_ILA8_1,
-- TRIG2 => TRIG_ILA8_2,
-- TRIG3 => TRIG_ILA8_3,
-- TRIG4 => TRIG_ILA8_4
--);
--TRIG_ILA8_0(0) <= dsp_pos_monit_1_valid;
--TRIG_ILA8_0(1) <= '0';
--TRIG_ILA8_0(2) <= '0';
--TRIG_ILA8_0(3) <= '0';
--TRIG_ILA8_0(4) <= '0';
--TRIG_ILA8_0(5) <= '0';
--TRIG_ILA8_0(6) <= '0';
--TRIG_ILA8_1(dsp_pos_x_monit_1'left downto 0) <= dsp_pos_x_monit_1;
--TRIG_ILA8_2(dsp_pos_y_monit_1'left downto 0) <= dsp_pos_y_monit_1;
--TRIG_ILA8_3(dsp_pos_q_monit_1'left downto 0) <= dsp_pos_q_monit_1;
--TRIG_ILA8_4(dsp_pos_sum_monit_1'left downto 0) <= dsp_pos_sum_monit_1;
---- TBT Phase data
--cmp_chipscope_ila_1024_tbt_pha : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL9,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA9_0,
-- TRIG1 => TRIG_ILA9_1,
-- TRIG2 => TRIG_ILA9_2,
-- TRIG3 => TRIG_ILA9_3,
-- TRIG4 => TRIG_ILA9_4
--);
--TRIG_ILA9_0(0) <= dsp_tbt_pha_valid;
--TRIG_ILA9_0(1) <= '0';
--TRIG_ILA9_0(2) <= '0';
--TRIG_ILA9_0(3) <= '0';
--TRIG_ILA9_0(4) <= '0';
--TRIG_ILA9_0(5) <= '0';
--TRIG_ILA9_0(6) <= '0';
--TRIG_ILA9_1(dsp_tbt_pha_ch0'left downto 0) <= dsp_tbt_pha_ch0;
--TRIG_ILA9_2(dsp_tbt_pha_ch1'left downto 0) <= dsp_tbt_pha_ch1;
--TRIG_ILA9_3(dsp_tbt_pha_ch2'left downto 0) <= dsp_tbt_pha_ch2;
--TRIG_ILA9_4(dsp_tbt_pha_ch3'left downto 0) <= dsp_tbt_pha_ch3;
---- FOFB Phase data
--cmp_chipscope_ila_1024_fofb_pha : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL10,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA10_0,
-- TRIG1 => TRIG_ILA10_1,
-- TRIG2 => TRIG_ILA10_2,
-- TRIG3 => TRIG_ILA10_3,
-- TRIG4 => TRIG_ILA10_4
--);
--TRIG_ILA10_0(0) <= dsp_fofb_pha_valid;
--TRIG_ILA10_0(1) <= '0';
--TRIG_ILA10_0(2) <= '0';
--TRIG_ILA10_0(3) <= '0';
--TRIG_ILA10_0(4) <= '0';
--TRIG_ILA10_0(5) <= '0';
--TRIG_ILA10_0(6) <= '0';
--TRIG_ILA10_1(dsp_fofb_pha_ch0'left downto 0) <= dsp_fofb_pha_ch0;
--TRIG_ILA10_2(dsp_fofb_pha_ch1'left downto 0) <= dsp_fofb_pha_ch1;
--TRIG_ILA10_3(dsp_fofb_pha_ch2'left downto 0) <= dsp_fofb_pha_ch2;
--TRIG_ILA10_4(dsp_fofb_pha_ch3'left downto 0) <= dsp_fofb_pha_ch3;
---- Controllable gain for test data
--cmp_chipscope_vio_256 : chipscope_vio_256
--port map (
-- CONTROL => CONTROL11,
-- ASYNC_OUT => vio_out
--);
--dds_sine_gain_ch0 <= vio_out(10-1 downto 0);
--dds_sine_gain_ch1 <= vio_out(20-1 downto 10);
--dds_sine_gain_ch2 <= vio_out(30-1 downto 20);
--dds_sine_gain_ch3 <= vio_out(40-1 downto 30);
--adc_synth_data_en <= vio_out(40);
---- Controllable DDS frequency and phase
--cmp_chipscope_vio_256_dsp_config : chipscope_vio_256
--port map (
-- CONTROL => CONTROL12,
-- ASYNC_OUT => vio_out_dsp_config
--);
end ;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_sr_250M/dds_cos_lut.vhd
|
1
|
2363
|
-------------------------------------------------------------------------------
-- Title : Vivado DDS cos lut for SIRIUS 250M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_cos_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2016-04-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary cosine lut for SIRIUS machine with 250M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity dds_cos_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_cos_lut;
architecture str of dds_cos_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_cos_lut_sirius_50_191_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 191,
g_init_file => "cos_lut_sirius_50_191.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/clk_gen.vhd
|
1
|
1594
|
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
sys_clk_o <= s_sys_clk;
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/orbit_intlk_cdc.vhd
|
1
|
15655
|
------------------------------------------------------------------------------
-- Title : BPM orbit interlock CDC FIFOs
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2022-06-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Module for orbit interlock CDC FIFOs
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2020-06-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- General cores
use work.gencores_pkg.all;
-- Orbit interlock cores
use work.orbit_intlk_pkg.all;
entity orbit_intlk_cdc is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Synched Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_o : out std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_o : out std_logic := '0';
decim_ds_pos_x_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_o : out std_logic;
-----------------------------
-- Synched Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_o : out std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_o : out std_logic := '0';
decim_us_pos_x_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_o : out std_logic
);
end orbit_intlk_cdc;
architecture rtl of orbit_intlk_cdc is
-- constants
constant c_ADC_WIDTH : natural := g_ADC_WIDTH;
constant c_DECIM_WIDTH : natural := g_DECIM_WIDTH;
constant c_INTLK_LMT_WIDTH : natural := g_INTLK_LMT_WIDTH;
constant c_CDC_REF_SIZE : natural := 4;
-- types
type t_bit_array is array (natural range <>) of std_logic;
type t_bit_array2d is array (natural range <>, natural range <>) of std_logic;
subtype t_adc_data is std_logic_vector(c_adc_width-1 downto 0);
type t_adc_data_array is array (natural range <>) of t_adc_data;
subtype t_adc_tag is std_logic_vector(0 downto 0);
type t_adc_tag_array is array (natural range <>) of t_adc_tag;
subtype t_decim_data is std_logic_vector(c_decim_width-1 downto 0);
type t_decim_data_array is array (natural range <>) of t_decim_data;
subtype t_intlk_lmt_data is std_logic_vector(c_intlk_lmt_width-1 downto 0);
type t_intlk_lmt_data_array is array (natural range <>) of t_intlk_lmt_data;
type t_adc_data_array2d is array (natural range <>, natural range <>) of t_adc_data;
type t_decim_data_array2d is array (natural range <>, natural range <>) of t_decim_data;
--signals
-- input mangling
signal adc_array : t_adc_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_tag_array : t_adc_tag_array(c_NUM_BPMS-1 downto 0);
signal adc_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal decim_pos_array : t_decim_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal adc_synch_array : t_adc_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_synch_valid_array : t_bit_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_synch_tag_array : t_adc_tag_array(c_NUM_BPMS-1 downto 0);
signal adc_synch_tag_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal decim_pos_synch_array : t_decim_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_synch_valid_array : t_bit_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_synch_rd : std_logic;
signal decim_pos_synch_rd : std_logic;
signal adc_synch_rd_and : std_logic_vector(c_NUM_BPMS downto 0);
signal decim_pos_synch_rd_and : std_logic_vector(c_NUM_BPMS downto 0);
signal fs_clk_array : std_logic_vector(c_NUM_BPMS-1 downto 0);
signal adc_synch_tag_empty : t_bit_array(c_NUM_BPMS-1 downto 0);
signal adc_synch_empty : t_bit_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_synch_empty : t_bit_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
begin
---------------------------------
-- Signal mangling
--------------------------------
fs_clk_array(c_BPM_DS_IDX) <= fs_clk_ds_i;
-- Downstream
adc_array(c_BPM_DS_IDX, 0) <= adc_ds_ch0_swap_i;
adc_array(c_BPM_DS_IDX, 1) <= adc_ds_ch1_swap_i;
adc_array(c_BPM_DS_IDX, 2) <= adc_ds_ch2_swap_i;
adc_array(c_BPM_DS_IDX, 3) <= adc_ds_ch3_swap_i;
adc_tag_array(c_BPM_DS_IDX) <= adc_ds_tag_i;
adc_valid_array(c_BPM_DS_IDX) <= adc_ds_swap_valid_i;
decim_pos_array(c_BPM_DS_IDX, 0) <= decim_ds_pos_x_i;
decim_pos_array(c_BPM_DS_IDX, 1) <= decim_ds_pos_y_i;
decim_pos_array(c_BPM_DS_IDX, 2) <= decim_ds_pos_q_i;
decim_pos_array(c_BPM_DS_IDX, 3) <= decim_ds_pos_sum_i;
decim_pos_valid_array(c_BPM_DS_IDX) <= decim_ds_pos_valid_i;
-- Upwnstream
fs_clk_array(c_BPM_US_IDX) <= fs_clk_us_i;
adc_array(c_BPM_US_IDX, 0) <= adc_us_ch0_swap_i;
adc_array(c_BPM_US_IDX, 1) <= adc_us_ch1_swap_i;
adc_array(c_BPM_US_IDX, 2) <= adc_us_ch2_swap_i;
adc_array(c_BPM_US_IDX, 3) <= adc_us_ch3_swap_i;
adc_tag_array(c_BPM_US_IDX) <= adc_us_tag_i;
adc_valid_array(c_BPM_US_IDX) <= adc_us_swap_valid_i;
decim_pos_array(c_BPM_US_IDX, 0) <= decim_us_pos_x_i;
decim_pos_array(c_BPM_US_IDX, 1) <= decim_us_pos_y_i;
decim_pos_array(c_BPM_US_IDX, 2) <= decim_us_pos_q_i;
decim_pos_array(c_BPM_US_IDX, 3) <= decim_us_pos_sum_i;
decim_pos_valid_array(c_BPM_US_IDX) <= decim_us_pos_valid_i;
---------------------------------
-- Decim CDC FIFOs
--------------------------------
gen_cdc_fifos_bpms : for i in 0 to c_NUM_BPMS-1 generate
cmp_orbit_intlk_adc_tag_cdc_fifo : orbit_intlk_cdc_fifo
generic map
(
g_data_width => 1,
g_size => c_CDC_REF_SIZE
)
port map
(
clk_wr_i => fs_clk_array(i),
data_i => adc_tag_array(i),
valid_i => adc_valid_array(i),
clk_rd_i => ref_clk_i,
rd_i => adc_synch_rd,
data_o => adc_synch_tag_array(i),
valid_o => adc_synch_tag_valid_array(i),
empty_o => adc_synch_tag_empty(i)
);
gen_cdc_fifos_chan : for j in 0 to c_NUM_CHANNELS-1 generate
cmp_orbit_intlk_adc_cdc_fifo : orbit_intlk_cdc_fifo
generic map
(
g_data_width => c_ADC_WIDTH,
g_size => c_CDC_REF_SIZE
)
port map
(
clk_wr_i => fs_clk_array(i),
data_i => adc_array(i, j),
valid_i => adc_valid_array(i),
clk_rd_i => ref_clk_i,
rd_i => adc_synch_rd,
data_o => adc_synch_array(i, j),
valid_o => adc_synch_valid_array(i, j),
empty_o => adc_synch_empty(i, j)
);
cmp_orbit_intlk_decim_cdc_fifo : orbit_intlk_cdc_fifo
generic map
(
g_data_width => c_DECIM_WIDTH,
g_size => c_CDC_REF_SIZE
)
port map
(
clk_wr_i => fs_clk_array(i),
data_i => decim_pos_array(i, j),
valid_i => decim_pos_valid_array(i),
clk_rd_i => ref_clk_i,
rd_i => decim_pos_synch_rd,
data_o => decim_pos_synch_array(i, j),
valid_o => decim_pos_synch_valid_array(i, j),
empty_o => decim_pos_synch_empty(i, j)
);
end generate;
end generate;
-- generate read signals based on empty FIFO flags
adc_synch_rd_and(0) <= '1';
-- ANDing all trans_bigger
gen_adc_synch_rd_and : for i in 0 to c_NUM_BPMS-1 generate
adc_synch_rd_and(i+1) <= adc_synch_rd_and(i) and not adc_synch_empty(i, 0);
end generate;
adc_synch_rd <= adc_synch_rd_and(c_NUM_BPMS);
decim_pos_synch_rd_and(0) <= '1';
-- ANDing all trans_bigger
gen_decim_pos_synch_rd_and : for i in 0 to c_NUM_BPMS-1 generate
decim_pos_synch_rd_and(i+1) <= decim_pos_synch_rd_and(i) and not decim_pos_synch_empty(i, 0);
end generate;
decim_pos_synch_rd <= decim_pos_synch_rd_and(c_NUM_BPMS);
---------------------------------
-- Signal unmangling
--------------------------------
-- Downstream
adc_ds_ch0_swap_o <= adc_synch_array(c_BPM_DS_IDX, 0);
adc_ds_ch1_swap_o <= adc_synch_array(c_BPM_DS_IDX, 1);
adc_ds_ch2_swap_o <= adc_synch_array(c_BPM_DS_IDX, 2);
adc_ds_ch3_swap_o <= adc_synch_array(c_BPM_DS_IDX, 3);
adc_ds_tag_o <= adc_synch_tag_array(c_BPM_DS_IDX);
adc_ds_swap_valid_o <= adc_synch_valid_array(c_BPM_DS_IDX, 0);
decim_ds_pos_x_o <= decim_pos_synch_array(c_BPM_DS_IDX, 0);
decim_ds_pos_y_o <= decim_pos_synch_array(c_BPM_DS_IDX, 1);
decim_ds_pos_q_o <= decim_pos_synch_array(c_BPM_DS_IDX, 2);
decim_ds_pos_sum_o <= decim_pos_synch_array(c_BPM_DS_IDX, 3);
decim_ds_pos_valid_o <= decim_pos_synch_valid_array(c_BPM_DS_IDX, 0);
-- Upstream
adc_us_ch0_swap_o <= adc_synch_array(c_BPM_US_IDX, 0);
adc_us_ch1_swap_o <= adc_synch_array(c_BPM_US_IDX, 1);
adc_us_ch2_swap_o <= adc_synch_array(c_BPM_US_IDX, 2);
adc_us_ch3_swap_o <= adc_synch_array(c_BPM_US_IDX, 3);
adc_us_tag_o <= adc_synch_tag_array(c_BPM_US_IDX);
adc_us_swap_valid_o <= adc_synch_valid_array(c_BPM_US_IDX, 0);
decim_us_pos_x_o <= decim_pos_synch_array(c_BPM_US_IDX, 0);
decim_us_pos_y_o <= decim_pos_synch_array(c_BPM_US_IDX, 1);
decim_us_pos_q_o <= decim_pos_synch_array(c_BPM_US_IDX, 2);
decim_us_pos_sum_o <= decim_pos_synch_array(c_BPM_US_IDX, 3);
decim_us_pos_valid_o <= decim_pos_synch_valid_array(c_BPM_US_IDX, 0);
end rtl;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_sr_250M/machine_pkg.vhd
|
1
|
4436
|
-------------------------------------------------------------------------------
-- Title : Machine parameters for Sirius with 250MSps ADC
-- Project :
-------------------------------------------------------------------------------
-- File : machine_pkg.vhd<sirius_250M>
-- Author : <aylons@dig-jobs>
-- Company :
-- Created : 2016-04-04
-- Last update: 2016-04-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Machine parameters for Sirius with 250MSps ADC
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package machine_pkg is
constant c_pos_calc_with_downconv : boolean := true;
constant c_pos_calc_adc_freq : real := 221.644e6;
constant c_pos_calc_input_width : natural := 16;
constant c_pos_calc_mixed_width : natural := 16;
constant c_pos_calc_adc_ratio : natural := 1;
constant c_pos_calc_dds_width : natural := 16;
constant c_pos_calc_dds_points : natural := 191;
constant c_pos_calc_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
constant c_pos_calc_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";
constant c_pos_calc_tbt_cic_delay : natural := 1;
constant c_pos_calc_tbt_cic_stages : natural := 1;
constant c_pos_calc_tbt_ratio : natural := 382;
constant c_pos_calc_tbt_decim_width : natural := 32;
constant c_pos_calc_fofb_cic_delay : natural := 1;
constant c_pos_calc_fofb_cic_stages : natural := 1;
constant c_pos_calc_fofb_ratio : natural := 8786;
constant c_pos_calc_fofb_decim_width : natural := 32;
constant c_pos_calc_monit1_cic_delay : natural := 1;
constant c_pos_calc_monit1_cic_stages : natural := 1;
constant c_pos_calc_monit1_ratio : natural := 25; --ratio between fofb and monit 1
constant c_pos_calc_monit1_cic_ratio : natural := 8;
constant c_pos_calc_monit2_cic_delay : natural := 1;
constant c_pos_calc_monit2_cic_stages : natural := 1;
constant c_pos_calc_monit2_ratio : natural := 40; -- ratio between monit 1 and 2
constant c_pos_calc_monit2_cic_ratio : natural := 8;
constant c_pos_calc_monit_decim_width : natural := 32;
constant c_pos_calc_tbt_cordic_stages : positive := 12;
constant c_pos_calc_tbt_cordic_iter_per_clk : positive := 3;
constant c_pos_calc_tbt_cordic_ratio : positive := 8;
constant c_pos_calc_fofb_cordic_stages : positive := 15;
constant c_pos_calc_fofb_cordic_iter_per_clk : positive := 3;
constant c_pos_calc_fofb_cordic_ratio : positive := 8;
constant c_pos_calc_k_width : natural := 25;
constant c_pos_calc_offset_width : natural := 32;
constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width;
constant c_pos_calc_k_sum : natural := 85e5;
constant c_pos_calc_k_x : natural := 85e5;
constant c_pos_calc_k_y : natural := 85e5;
end machine_pkg;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/top/pcie/top_afcv3.vhd
|
2
|
8547
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
use work.ipcores_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE"
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(C_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(C_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(C_DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(C_DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(C_DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(C_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_rxn : in std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_txp : out std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_txn : out std_logic_vector(c_pcielanes-1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
pci_sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
pci_sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic
);
end entity top;
architecture arch of top is
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_rst_i : std_logic;
signal ddr_axi_aclk_o : std_logic;
signal sys_rst_n_c : std_logic;
signal pll_clkin : std_logic;
signal pll_clkfbout : std_logic;
signal pll_clkout0 : std_logic;
signal pll_locked : std_logic;
signal wbone_clk : std_logic;
signal wbone_addr : std_logic_vector(31 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
signal wbone_rst : std_logic;
begin
bpm_pcie_i: entity work.bpm_pcie
generic map(
SIMULATION => SIMULATION
)
port map(
--DDR3 memory pins
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- PCIe transceivers
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- Necessity signals
ddr_sys_clk => ddr_sys_clk_i,
ddr_sys_rst => ddr_sys_rst_i,
pci_sys_clk_p => pci_sys_clk_p,
pci_sys_clk_n => pci_sys_clk_n,
pci_sys_rst_n => sys_rst_n_c,
-- DDR memory controller AXI4 interface --
-- Slave interface clock
ddr_axi_aclk_o => ddr_axi_aclk_o,
ddr_axi_aresetn_o => open,
-- Slave Interface Write Address Ports
ddr_axi_awid => (others => '0'),
ddr_axi_awaddr => (others => '0'),
ddr_axi_awlen => (others => '0'),
ddr_axi_awsize => (others => '0'),
ddr_axi_awburst => (others => '0'),
ddr_axi_awlock => '0',
ddr_axi_awcache => (others => '0'),
ddr_axi_awprot => (others => '0'),
ddr_axi_awqos => (others => '0'),
ddr_axi_awvalid => '0',
ddr_axi_awready => open,
-- Slave Interface Write Data Ports
ddr_axi_wdata => (others => '0'),
ddr_axi_wstrb => (others => '0'),
ddr_axi_wlast => '0',
ddr_axi_wvalid => '0',
ddr_axi_wready => open,
-- Slave Interface Write Response Ports
ddr_axi_bid => open,
ddr_axi_bresp => open,
ddr_axi_bvalid => open,
ddr_axi_bready => '1',
-- Slave Interface Read Address Ports
ddr_axi_arid => (others => '0'),
ddr_axi_araddr => (others => '0'),
ddr_axi_arlen => (others => '0'),
ddr_axi_arsize => (others => '0'),
ddr_axi_arburst => (others => '0'),
ddr_axi_arlock => '0',
ddr_axi_arcache => (others => '0'),
ddr_axi_arprot => (others => '0'),
ddr_axi_arqos => (others => '0'),
ddr_axi_arvalid => '0',
ddr_axi_arready => open,
-- Slave Interface Read Data Ports
ddr_axi_rid => open,
ddr_axi_rdata => open,
ddr_axi_rresp => open,
ddr_axi_rlast => open,
ddr_axi_rvalid => open,
ddr_axi_rready => '1',
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I => wbone_clk,
RST_I => wbone_rst,
ACK_I => wbone_ack,
DAT_I => wbone_mdin,
ADDR_O => wbone_addr(28 downto 0),
DAT_O => wbone_mdout,
WE_O => wbone_we,
STB_O => wbone_stb,
SEL_O => wbone_sel(0),
CYC_O => wbone_cyc,
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o => wbone_rst
);
Wishbone_mem_large: if (SIMULATION = "TRUE") generate
wb_mem_sim :
entity work.wb_mem
generic map(
AWIDTH => 16,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
Wishbone_mem_sample: if (SIMULATION = "FALSE") generate
wb_mem_syn :
entity work.wb_mem
generic map(
AWIDTH => 7,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
--temporary clock assignment
wbone_clk <= pll_clkin;
sys_reset_n_ibuf : IBUF
port map (
O => sys_rst_n_c,
I => sys_rst_n
);
ddr_inclk_buf : IBUFGDS
generic map(
IBUF_LOW_PWR => false
)
port map
(o => pll_clkin,
i => ddr_sys_clk_p,
ib => ddr_sys_clk_n
);
plle2_adv_inst : PLLE2_ADV
generic map
(bandwidth => "high",
compensation => "zhold",
divclk_divide => 5,
clkfbout_mult => 64,
clkfbout_phase => 0.000,
clkout0_divide => 8,
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkin1_period => 8.000,
ref_jitter1 => 0.010)
port map
-- output clocks
(clkfbout => pll_clkfbout,
clkout0 => pll_clkout0,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
-- input clock control
clkfbin => pll_clkfbout,
clkin1 => pll_clkin,
clkin2 => '0',
-- tied to always select the primary input clock
clkinsel => '1',
-- ports for dynamic reconfiguration
daddr => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => pll_locked,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => ddr_sys_clk_i,
I => pll_clkout0
);
ddr_sys_rst_i <= not(pll_locked);
end architecture;
|
lgpl-3.0
|
lnls-dig/bpm-gw
|
hdl/modules/wb_bpm_swap/xwb_bpm_swap.vhd
|
1
|
4838
|
------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone interface with BPM Swap core.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-11 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- BPM Cores
use work.bpm_cores_pkg.all;
-- Register Bank
use work.bpm_swap_wbgen2_pkg.all;
entity xwb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
sync_trig_i : in std_logic
);
end xwb_bpm_swap;
architecture rtl of xwb_bpm_swap is
begin
cmp_wb_bpm_swap : wb_bpm_swap
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_delay_vec_width => g_delay_vec_width,
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width,
g_ch_width => g_ch_width
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
fs_rst_n_i => fs_rst_n_i,
fs_clk_i => fs_clk_i,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
cha_i => cha_i,
chb_i => chb_i,
chc_i => chc_i,
chd_i => chd_i,
ch_valid_i => ch_valid_i,
cha_o => cha_o,
chb_o => chb_o,
chc_o => chc_o,
chd_o => chd_o,
ch_tag_o => ch_tag_o,
ch_valid_o => ch_valid_o,
rffe_swclk_o => rffe_swclk_o,
sync_trig_i => sync_trig_i
);
end rtl;
|
lgpl-3.0
|
freecores/pcounter
|
pdchain.vhdl
|
1
|
1099
|
--
-- * pipelined synchronous pulse counter *
-- pdchain -- multi-bit counter top-level entity
--
-- fast counter for slow-carry architectures
-- non-monotonic counting, value calculable by HDL/CPU
--
-- idea&code by Marek Peca <[email protected]> 08/2012
-- Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/
-- thanks to Michael Vacek <[email protected]> for testing
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdchain is
generic (
n: natural := 32
);
port (
clock: in std_logic;
en: in std_logic;
q: out std_logic_vector (n-1 downto 0)
);
end pdchain;
architecture behavioral of pdchain is
component pdivtwo
port (
clock: in std_logic;
en: in std_logic;
q, p: out std_logic
);
end component;
--
signal b: std_logic_vector (q'range);
begin
q0: pdivtwo
port map (
clock => clock, en => en, p => b(0), q => q(0)
);
ch: for k in 1 to b'high generate
qk: pdivtwo
port map (
clock => clock, en => b(k-1), p => b(k), q => q(k)
);
end generate;
end behavioral;
|
lgpl-3.0
|
gtaylormb/opl3_fpga
|
fpga/bd/opl3_cpu/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd
|
15
|
22231
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
lgpl-3.0
|
gtaylormb/opl3_fpga
|
fpga/bd/opl3_cpu/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd
|
32
|
49938
|
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
signal srst_d1 : std_logic := '0';
signal srst_d2 : std_logic := '0';
signal srst_d3 : std_logic := '0';
signal srst_d4 : std_logic := '0';
signal srst_d5 : std_logic := '0';
signal srst_d6 : std_logic := '0';
signal srst_d7 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
s_rst_d1 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d1,
C => scndry_aclk,
D => '1',
R => scndry_reset2
);
s_rst_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d2,
C => scndry_aclk,
D => srst_d1,
R => scndry_reset2
);
s_rst_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d3,
C => scndry_aclk,
D => srst_d2,
R => scndry_reset2
);
s_rst_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d4,
C => scndry_aclk,
D => srst_d3,
R => scndry_reset2
);
s_rst_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d5,
C => scndry_aclk,
D => srst_d4,
R => scndry_reset2
);
s_rst_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d6,
C => scndry_aclk,
D => srst_d5,
R => scndry_reset2
);
s_rst_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d7,
C => scndry_aclk,
D => srst_d6,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
|
lgpl-3.0
|
gtaylormb/opl3_fpga
|
fpga/bd/opl3_cpu/ip/opl3_cpu_rst_opl3_fpga_0_12M_0/synth/opl3_cpu_rst_opl3_fpga_0_12M_0.vhd
|
1
|
6650
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY opl3_cpu_rst_opl3_fpga_0_12M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END opl3_cpu_rst_opl3_fpga_0_12M_0;
ARCHITECTURE opl3_cpu_rst_opl3_fpga_0_12M_0_arch OF opl3_cpu_rst_opl3_fpga_0_12M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF opl3_cpu_rst_opl3_fpga_0_12M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF opl3_cpu_rst_opl3_fpga_0_12M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF opl3_cpu_rst_opl3_fpga_0_12M_0_arch : ARCHITECTURE IS "opl3_cpu_rst_opl3_fpga_0_12M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF opl3_cpu_rst_opl3_fpga_0_12M_0_arch: ARCHITECTURE IS "opl3_cpu_rst_opl3_fpga_0_12M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END opl3_cpu_rst_opl3_fpga_0_12M_0_arch;
|
lgpl-3.0
|
id101010/vhdl-irdecoder
|
hex2seg.vhd
|
1
|
2025
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hex2seg is
Port ( clk : in STD_LOGIC; -- Clock of the display (30-100Hz?)
en : in STD_LOGIC;
hex : in STD_LOGIC_VECTOR (3 downto 0); -- HEX number you want to display 0-F
seg : out STD_LOGIC_VECTOR (6 downto 0)); -- 7-Segment output, bit0=segment a, .. ,bit 6=segment g. Output is modulated with clock!
end hex2seg;
architecture Behavioral of hex2seg is
signal segments : STD_LOGIC_VECTOR(6 downto 0); -- '1' for every segment that should be switched on (not modulated)
signal clockvec : STD_LOGIC_VECTOR(6 downto 0); -- just "clk" on every bit of the vector
begin
clockvec <= (others => clk); -- "Copy" clock to every bit of the vector
-- Switch on the hex char, and decide which segments should be on
with hex select
segments <= "0111111" when "0000", --Ziffer 0
"0000110" when "0001", --Ziffer 1
"1011011" when "0010", --Ziffer 2
"1001111" when "0011", --Ziffer 3
"1100110" when "0100", --Ziffer 4
"1101101" when "0101", --Ziffer 5
"1111101" when "0110", --Ziffer 6
"0000111" when "0111", --Ziffer 7
"1111111" when "1000", --Ziffer 8
"1101111" when "1001", --Ziffer 9
"1110111" when "1010", --Ziffer A
"1111100" when "1011", --Ziffer B
"0111001" when "1100", --Ziffer C
"1011110" when "1101", --Ziffer D
"1111001" when "1110", --Ziffer E
"1110001" when "1111", --Ziffer F
"0000000" when others;
-- Assign seg (modulated).
-- All segments which must be on, will have the inverse polarity of the clock. The others go with the clock. We can use xor for that.
seg <= clockvec xor segments when en = '1' else clockvec;
end Behavioral;
|
lgpl-3.0
|
id101010/vhdl-irdecoder
|
hex2seg_tb.vhd
|
1
|
2270
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY hex2seg_tb IS
END hex2seg_tb;
ARCHITECTURE behavior OF hex2seg_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hex2seg
PORT(
clk : IN std_logic;
en : in std_logic;
hex : IN std_logic_vector(3 downto 0);
seg : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal en: std_logic := '0';
signal hex : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal seg : std_logic_vector(6 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hex2seg PORT MAP (
clk => clk,
en => en,
hex => hex,
seg => seg
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
--Test if nothing happens if enabled is on '0'
en <= '0';
hex <= "0001";
wait for clk_period*10;
-- Test decoding of hex numbers 0-F
en <= '1';
hex <= "0000";
wait for clk_period*10;
hex <= "0001";
wait for clk_period*10;
hex <= "0010";
wait for clk_period*10;
hex <= "0011";
wait for clk_period*10;
hex <= "0100";
wait for clk_period*10;
hex <= "0101";
wait for clk_period*10;
hex <= "0110";
wait for clk_period*10;
hex <= "0111";
wait for clk_period*10;
hex <= "1000";
wait for clk_period*10;
hex <= "1001";
wait for clk_period*10;
hex <= "1010";
wait for clk_period*10;
hex <= "1011";
wait for clk_period*10;
hex <= "1100";
wait for clk_period*10;
hex <= "1101";
wait for clk_period*10;
hex <= "1110";
wait for clk_period*10;
hex <= "1111";
wait;
end process;
END;
|
lgpl-3.0
|
AfterRace/SoC_Project
|
vivado/project/project.srcs/sources_1/ipshared/user.org/zed_audio_v1_0/8de2dafc/hdl/ADAU1761_interface.vhd
|
5
|
867
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: ADAU1761_interface - Behavioral
-- Description: Was originally to do a lot more, but just creates a clock at 1/2
-- the projects 48MHz to send to the codec.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ADAU1761_interface is
Port ( clk_48 : in STD_LOGIC;
codec_master_clk : out STD_LOGIC);
end ADAU1761_interface;
architecture Behavioral of ADAU1761_interface is
signal master_clk : std_logic := '0';
begin
codec_master_clk <= master_clk;
process(clk_48)
begin
if rising_edge(clk_48) then
master_clk <= not master_clk;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
AfterRace/SoC_Project
|
vivado/project/project.srcs/sources_1/bd/week1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/sequence.vhd
|
30
|
22215
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence;
architecture imp of sequence is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
lgpl-3.0
|
AfterRace/SoC_Project
|
vivado/project/project.srcs/sources_1/ipshared/tsotnep/volume_pregain_v1_0/75ddc6aa/src/AmplifierFP.vhd
|
2
|
2738
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:41 04/17/2015
-- Design Name:
-- Module Name: AmplifierFP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AmplifierFP is
generic ( INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer);
Port ( CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed ((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --amplifying coefficient
OUT_AMP : out signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end AmplifierFP;
architecture Behavioral of AmplifierFP is
COMPONENT MultiplierFP
generic ( INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
IN_SIG : IN signed((INTBIT_WIDTH - 1) downto 0);
IN_COEF : IN signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
OUT_MULT : OUT signed((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
READY : OUT std_logic
);
END COMPONENT;
signal mult_out : signed ((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0) := (others => '0');
signal AMP_OUT_in, AMP_OUT_out : signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal mult_ready : std_logic := '0';
begin
Amp_multiplier: MultiplierFP
generic map(
INTBIT_WIDTH => INTBIT_WIDTH,
FRACBIT_WIDTH => FRACBIT_WIDTH
)PORT MAP(
CLK => CLK,
RESET => RESET,
IN_SIG => IN_SIG,
IN_COEF => IN_COEF,
OUT_MULT => mult_out,
READY => mult_ready
);
-- for fixed point
-- AMP_OUT_in <= mult_out(2*BIT_WIDTH - BIT_WIDTH - 1 downto 0);
-- for integers
AMP_OUT_in <= mult_out((2*FRACBIT_WIDTH + INTBIT_WIDTH) - 1 downto (2*FRACBIT_WIDTH ));
seq_proc : process (CLK)
begin
if(CLK'event and CLK = '1')then
-- update the ready signal when new values gets written to the buffer
if (mult_ready = '1') then
AMP_OUT_out <= AMP_OUT_in;
end if;
end if;
end process;
OUT_RDY <= mult_ready;
OUT_AMP <= AMP_OUT_out;
end Behavioral;
|
lgpl-3.0
|
AfterRace/SoC_Project
|
vivado/project/project.srcs/sources_1/ipshared/tsotnep/filter_iir_v1_0/263d46e2/hdl/FILTER_IIR_v1_0.vhd
|
2
|
4872
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FILTER_IIR_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
SAMPLE_TRIG : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end FILTER_IIR_v1_0;
architecture arch_imp of FILTER_IIR_v1_0 is
-- component declaration
component FILTER_IIR_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
SAMPLE_TRIG : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component FILTER_IIR_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
FILTER_IIR_v1_0_S00_AXI_inst : FILTER_IIR_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
SAMPLE_TRIG => SAMPLE_TRIG,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
lgpl-3.0
|
AfterRace/SoC_Project
|
vivado/project/project.srcs/sources_1/bd/week1/ip/week1_FILTER_IIR_0_0/synth/week1_FILTER_IIR_0_0.vhd
|
1
|
9117
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: tsotnep:userLibrary:FILTER_IIR:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_FILTER_IIR_0_0 IS
PORT (
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
FILTER_DONE : OUT STD_LOGIC;
SAMPLE_TRIG : IN STD_LOGIC;
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_FILTER_IIR_0_0;
ARCHITECTURE week1_FILTER_IIR_0_0_arch OF week1_FILTER_IIR_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_FILTER_IIR_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT FILTER_IIR_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
FILTER_DONE : OUT STD_LOGIC;
SAMPLE_TRIG : IN STD_LOGIC;
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s00_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT FILTER_IIR_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_FILTER_IIR_0_0_arch: ARCHITECTURE IS "FILTER_IIR_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_FILTER_IIR_0_0_arch : ARCHITECTURE IS "week1_FILTER_IIR_0_0,FILTER_IIR_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : FILTER_IIR_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 7
)
PORT MAP (
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
SAMPLE_TRIG => SAMPLE_TRIG,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_FILTER_IIR_0_0_arch;
|
lgpl-3.0
|
egk696/VHDL_FSM_Visualizer
|
VHDL FSM Visualizer/Demo Files/moore_4s.vhd
|
1
|
1452
|
-- A Moore machine's outputs are dependent only on the current state.
-- The output is written only when the state changes. (State
-- transitions are synchronous.)
library ieee;
use ieee.std_logic_1164.all;
entity moore_4s is
port(
clk : in std_logic;
data_in : in std_logic;
reset : in std_logic;
data_out : out std_logic_vector(1 downto 0)
);
end entity;
architecture rtl of moore_4s is
-- Build an enumerated type for the state machine
type state_type is (s0, s1, s2, s3);
-- Register to hold the current state
signal state : state_type;
begin
-- Logic to advance to the next state
process (clk, reset)
begin
if reset = '1' then
state <= s0;
elsif (rising_edge(clk)) then
case state is
when s0=>
if data_in = '1' then
state <= s1;
else
state <= s3;
end if;
when s1=>
if data_in = '1' then
state <= s2;
else
state <= s1;
end if;
when s2=>
if data_in = '1' then
state <= s3;
else
state <= s2;
end if;
when s3 =>
if data_in = '1' then
state <= s0;
else
state <= s3;
end if;
end case;
end if;
end process;
-- Output depends solely on the current state
process (state)
begin
case state is
when s0 =>
data_out <= "00";
when s1 =>
data_out <= "01";
when s2 =>
data_out <= "10";
when s3 =>
data_out <= "11";
end case;
end process;
end rtl;
|
lgpl-3.0
|
LaNoC-UFC/NoCThor
|
NoC/Thor_package.vhd
|
1
|
3974
|
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;
package NoCPackage is
---------------------------------------------------------
-- INDEPENDENT CONSTANTS
---------------------------------------------------------
constant NPORT: integer := 5;
constant EAST : integer := 0;
constant WEST : integer := 1;
constant NORTH : integer := 2;
constant SOUTH : integer := 3;
constant LOCAL : integer := 4;
---------------------------------------------------------
-- CONSTANTS RELATED TO THE NETWORK BANDWIDTH
---------------------------------------------------------
constant TAM_FLIT : integer range 1 to 64 := 16;
constant METADEFLIT : integer range 1 to 32 := (TAM_FLIT/2);
constant QUARTOFLIT : integer range 1 to 16 := (TAM_FLIT/4);
---------------------------------------------------------
-- CONSTANTS RELATED TO THE DEPTH OF THE QUEUE
---------------------------------------------------------
constant TAM_BUFFER: integer := 16;
constant TAM_POINTER : integer range 1 to 32 := 5;
---------------------------------------------------------
-- CONSTANTS RELATED TO THE NUMBER OF ROUTERS
---------------------------------------------------------
constant NUM_X : integer := 2;
constant NUM_Y : integer := 2;
constant NROT: integer := NUM_X*NUM_Y;
constant MIN_X : integer := 0;
constant MIN_Y : integer := 0;
constant MAX_X : integer := NUM_X-1;
constant MAX_Y : integer := NUM_Y-1;
---------------------------------------------------------
-- NEW HARDWARE VARIABLES
---------------------------------------------------------
type RouterControl is (invalidRegion, validRegion, faultPort, portError);
---------------------------------------------------------
-- SUBTYPES, TYPES AND FUNCTIONS
---------------------------------------------------------
subtype reg3 is std_logic_vector(2 downto 0);
subtype regNrot is std_logic_vector((NROT-1) downto 0);
subtype regNport is std_logic_vector((NPORT-1) downto 0);
subtype regflit is std_logic_vector((TAM_FLIT-1) downto 0);
subtype regmetadeflit is std_logic_vector((METADEFLIT-1) downto 0);
subtype regquartoflit is std_logic_vector((QUARTOFLIT-1) downto 0);
type arrayNport_reg3 is array((NPORT-1) downto 0) of reg3;
type arrayNport_regflit is array((NPORT-1) downto 0) of regflit;
type arrayNrot_regflit is array((NROT-1) downto 0) of regflit;
type arrayNrot_regNport is array((NROT-1) downto 0) of regNport;
type matrixNrot_Nport_regflit is array((NROT-1) downto 0) of arrayNport_regflit;
---------------------------------------------------------
-- TB FUNCTIONS
---------------------------------------------------------
function ADDRESS_FROM_INDEX(index : integer) return regflit;
function X_COORDINATE(address: regflit) return natural;
function Y_COORDINATE(address: regflit) return natural;
function OR_REDUCTION(arrayN : std_logic_vector ) return boolean;
end NoCPackage;
package body NoCPackage is
function ADDRESS_FROM_INDEX(index: integer) return regflit is
variable addrX, addrY: regmetadeflit;
variable addr: regflit;
begin
addrX := std_logic_vector(to_unsigned(index/NUM_X, METADEFLIT));
addrY := std_logic_vector(to_unsigned(index mod NUM_Y, METADEFLIT));
addr := addrX & addrY;
return addr;
end ADDRESS_FROM_INDEX;
function X_COORDINATE(address: regflit) return natural is
begin
return TO_INTEGER(unsigned(address(TAM_FLIT-1 downto METADEFLIT)));
end X_COORDINATE;
function Y_COORDINATE(address: regflit) return natural is
begin
return TO_INTEGER(unsigned(address(METADEFLIT-1 downto 0)));
end Y_COORDINATE;
--
-- Do a OR operation between all elements in an array
--
function OR_REDUCTION( arrayN: in std_logic_vector ) return boolean is
begin
return unsigned(arrayN) /= 0;
end OR_REDUCTION;
end NoCPackage;
|
lgpl-3.0
|
LaNoC-UFC/NoCThor
|
NoC/RouterCC.vhd
|
1
|
1998
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.NoCPackage.all;
use work.TablePackage.all;
entity RouterCC is
generic(
address: regflit;
ramInit: memory);
port(
clock: in std_logic;
reset: in std_logic;
clock_rx: in regNport;
rx: in regNport;
data_in: in arrayNport_regflit;
credit_o: out regNport;
clock_tx: out regNport;
tx: out regNport;
data_out: out arrayNport_regflit;
credit_i: in regNport);
end RouterCC;
architecture RouterCC of RouterCC is
signal h, ack_h, data_av, sender, data_ack: regNport := (others=>'0');
signal data: arrayNport_regflit := (others=>(others=>'0'));
signal mux_in, mux_out: arrayNport_reg3 := (others=>(others=>'0'));
signal free: regNport := (others=>'0');
begin
buff : for i in EAST to LOCAL generate
B : entity work.Thor_buffer
port map(
clock => clock,
reset => reset,
data_in => data_in(i),
rx => rx(i),
h => h(i),
ack_h => ack_h(i),
data_av => data_av(i),
data => data(i),
sender => sender(i),
clock_rx => clock_rx(i),
data_ack => data_ack(i),
credit_o => credit_o(i));
clock_tx(i) <= clock;
end generate buff;
SwitchControl : Entity work.SwitchControl
generic map(
address => address,
ramInit => ramInit)
port map(
clock => clock,
reset => reset,
h => h,
ack_h => ack_h,
data => data,
sender => sender,
free => free,
mux_in => mux_in,
mux_out => mux_out);
CrossBar : Entity work.Thor_crossbar
port map(
data_av => data_av,
data_in => data,
data_ack => data_ack,
sender => sender,
free => free,
tab_in => mux_in,
tab_out => mux_out,
tx => tx,
data_out => data_out,
credit_i => credit_i);
end RouterCC;
|
lgpl-3.0
|
rmilfont/Phoenix
|
NoC/FPPM_AA00.vhd
|
1
|
2876
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.PhoenixPackage.regNport;
use work.HammingPack16.all;
entity FPPM is
port
(
clock : in std_logic;
reset_in : in std_logic; -- reset geral da NoC
rx : in regHamm_Nport; -- rx (sinal que indica que estou recebendo transmissao)
statusHamming : in array_statusHamming; -- status (sem erro, erro corrigido, erro detectado) das 4 portas (EAST,WEST,NORTH,SOUTH)
write_FaultTable : out regHamm_Nport; -- sinal para indicar escrita na tabela de falhas
row_FaultTablePorts_out : out row_FaultTable_Ports -- linha a ser escrita na tabela de falhas
);
end FPPM;
architecture FPPM of FPPM is
-- CUIDADO! Os contadores tem apenas COUNTERS_SIZE bits!
constant N: integer range 1 to 31 := 8;
constant M: integer range 1 to 31 := 4;
constant P: integer range 1 to 31 := 30;
constant COUNTER_UPDATE_TABLE: integer := 1; -- numero de flits recebidos necessarios para atualizar a tabela
begin
FPPM_generate: for i in 0 to (HAMM_NPORT-1) generate
begin
process(clock, reset_in)
variable counter_write: integer range 0 to COUNTER_UPDATE_TABLE;
variable reset: std_logic := '0';
variable counter_N, counter_M, counter_P: std_logic_vector((COUNTERS_SIZE-1) downto 0);
variable link_status: std_logic_vector(1 downto 0) := "00";
begin
if (reset_in='1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
if (clock'event and clock='1' and rx(i)='1') then
--counter_write := counter_write + 1;
case statusHamming(i) is
when NE =>
counter_N := counter_N + 1;
if (counter_N = N) then
link_status := "00";
reset := '1';
end if;
when EC =>
counter_M := counter_M + 1;
if (counter_M = M) then
link_status := "01";
reset := '1';
end if;
when ED =>
counter_P := counter_P + 1;
if (counter_P = P) then
link_status := "10";
reset := '1';
end if;
when others => null;
end case;
if (reset = '1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
end if;
if (counter_write = COUNTER_UPDATE_TABLE) then
--if (false) then
write_FaultTable(i) <= '1';
row_FaultTablePorts_out(i) <= link_status & counter_N & counter_M & counter_P;
counter_write := 0;
else
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
elsif (rx(i)='0') then
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
end process;
end generate;
end FPPM;
|
lgpl-3.0
|
rmilfont/Phoenix
|
NoC/Decoder.vhd
|
1
|
3317
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.Numeric_std.all;
use work.HammingPack16.all;
use work.PhoenixPackage.all;
entity HAM_DEC is
port
(
data_in : in regflit; -- data input
parity_in : in reghamm; -- parity input
data_out : out regflit; -- data output (corrected data)
parity_out : out reghamm; -- parity output (corrected parity)
credit_out : out std_logic_vector(2 downto 0) -- status output (hamming results status)
);
end HAM_DEC;
architecture HAM_DEC of HAM_DEC is
begin
process(data_in, parity_in)
--overall mod-2 of all bits
variable P0 : Std_logic;
--syndrome
variable Synd : Std_logic_vector(5 downto 1);
begin
--calculate overall parity of all bits---------
P0 := xor_reduce(data_in & parity_in);
----------------------------------------------
--generate each syndrome bit C1 to C4---------------------------
Synd(1) := xor_reduce((data_in and MaskP1) & parity_in(1));
Synd(2) := xor_reduce((data_in and MaskP2) & parity_in(2));
Synd(3) := xor_reduce((data_in and MaskP4) & parity_in(3));
Synd(4) := xor_reduce((data_in and MaskP8) & parity_in(4));
Synd(5) := xor_reduce((data_in and MaskP16) & parity_in(5));
----------------------------------------------------------------
if (Synd = "0000") and (P0 = '0') then --no errors
credit_out <= NE;
data_out <= data_in;
parity_out <= parity_in;
null; --accept default o/p's assigned above
elsif P0 = '1' then --single error (or odd no of errors!)
credit_out <= EC;
data_out <= data_in;
parity_out <= parity_in;
--correct single error
case to_integer(unsigned(Synd)) is
when 0 => parity_out(0) <= not parity_in(0);
when 1 => parity_out(1) <= not parity_in(1);
when 2 => parity_out(2) <= not parity_in(2);
when 3 => data_out(0) <= not data_in(0);
when 4 => parity_out(3) <= not parity_in(3);
when 5 => data_out(1) <= not data_in(1);
when 6 => data_out(2) <= not data_in(2);
when 7 => data_out(3) <= not data_in(3);
when 8 => parity_out(4) <= not parity_in(4);
when 9 => data_out(4) <= not data_in(4);
when 10 => data_out(5) <= not data_in(5);
when 11 => data_out(6) <= not data_in(6);
when 12 => data_out(7) <= not data_in(7);
when 13 => data_out(8) <= not data_in(8);
when 14 => data_out(9) <= not data_in(9);
when 15 => data_out(10) <= not data_in(10);
when 16 => parity_out(5) <= not parity_in(5);
when 17 => data_out(11) <= not data_in(11);
when 18 => data_out(12) <= not data_in(12);
when 19 => data_out(13) <= not data_in(13);
when 20 => data_out(14) <= not data_in(14);
when 21 => data_out(15) <= not data_in(15);
when others => data_out <= "0000000000000000"; parity_out <= "000000";
end case;
elsif (P0 = '0') and (Synd /= "00000") then --double error
credit_out <= ED;
data_out <= "0000000000000000";
parity_out <= "000000";
end if;
end process;
end HAM_DEC;
|
lgpl-3.0
|
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/example_design/rtl/example_top.vhd
|
1
|
42962
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end example_top;
architecture arc of example_top is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p2_DATA_MODE : std_logic_vector(3 downto 0);
C_p2_END_ADDRESS : std_logic_vector(31 downto 0);
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"20";
constant C3_MEM_TRAS : integer := 42500;
constant C3_MEM_TRCD : integer := 12500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 127500;
constant C3_MEM_TRP : integer := 12500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR2";
constant C3_MEM_DENSITY : string := "1Gb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 5;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
error <= c3_error;
calib_done <= c3_calib_done;
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_clk0,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_clk0,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_clk0,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p2_cmd_clk => c3_clk0,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_rd_clk => c3_clk0,
p2_rd_en => c3_p2_rd_en,
p2_rd_data => c3_p2_rd_data,
p2_rd_full => c3_p2_rd_full,
p2_rd_empty => c3_p2_rd_empty,
p2_rd_count => c3_p2_rd_count,
p2_rd_overflow => c3_p2_rd_overflow,
p2_rd_error => c3_p2_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
memc3_tb_top_inst : memc3_tb_top
generic map
(
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C3_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
C_p2_DATA_MODE => C3_p2_DATA_MODE,
C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS
)
port map
(
error => c3_error,
calib_done => c3_calib_done,
clk0 => c3_clk0,
rst0 => c3_rst0,
cmp_error => c3_cmp_error,
cmp_data_valid => c3_cmp_data_valid,
vio_modify_enable => c3_vio_modify_enable,
error_status => c3_error_status,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
cmp_data => c3_cmp_data,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p2_mcb_cmd_en_o => c3_p2_cmd_en,
p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
p2_mcb_cmd_full_i => c3_p2_cmd_full,
p2_mcb_rd_en_o => c3_p2_rd_en,
p2_mcb_rd_data_i => c3_p2_rd_data,
p2_mcb_rd_empty_i => c3_p2_rd_empty,
p2_mcb_rd_fifo_counts => c3_p2_rd_count
);
end arc;
|
lgpl-3.0
|
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/user_design/sim/cmd_prbs_gen.vhd
|
20
|
8359
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:37 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel use LFSR to generate random address, isntructions
-- or burst_length.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END cmd_prbs_gen;
ARCHITECTURE trans OF cmd_prbs_gen IS
SIGNAL ZEROS : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL prbs : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
function logb2 (val : integer) return integer is
variable vec_con : integer;
variable rtn : integer := 1;
begin
vec_con := val;
for index in 0 to 31 loop
if(vec_con = 1) then
rtn := rtn + 1;
return(rtn);
end if;
vec_con := vec_con/2;
rtn := rtn + 1;
end loop;
end function logb2;
BEGIN
ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
lfsr_q(63) <= lfsr_q(62) ;
lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(64) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
prbs <= lfsr_q(32 DOWNTO 1);
END PROCESS;
END GENERATE;
xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= prbs_seed_i ;
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
lfsr_q(2) <= lfsr_q(1) ;
lfsr_q(1) <= lfsr_q(32) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
IF (FAMILY = "SPARTAN6") THEN
FOR i IN (logb2(DWIDTH) + 1) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
ELSE
FOR i IN (logb2(DWIDTH) - 4) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(20) <= lfsr_q(19) ;
lfsr_q(19) <= lfsr_q(18) ;
lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(20) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
BEGIN
prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
END PROCESS;
END GENERATE;
prbs_o <= prbs;
END trans;
|
lgpl-3.0
|
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/example_design/rtl/traffic_gen/write_data_path.vhd
|
20
|
9135
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
lgpl-3.0
|
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/user_design/sim/write_data_path.vhd
|
20
|
9135
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
lgpl-3.0
|
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd
|
20
|
37533
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_traffic_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level module of memory traffic generator which can
-- generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
-- hard memory controller core.
-- Reference:
-- Revision History: 2009 Brought out internal signals cmp_data and cmp_error as outputs.
-- 2010/01/09 Removed the rd_mdata_afull_set term in signal rdpath_data_valid_i .
-- 2010/05/03 Removed local generated version of mcb_rd_empty and mcb_wr_full in TG.
-- 2010/05/20 If MEM_BURST_LEN value is passed with value of zero, it is treated as
-- "OTF" Burst Mode and TG will only generate BL 8 traffic.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_traffic_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
SIMULATION : STRING := "FALSE";
MEM_BURST_LEN : INTEGER := 8;
PORT_MODE : STRING := "BI_MODE";
DATA_PATTERN : STRING := "DGEN_ADDR";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
CMP_DATA_PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
NUM_DQ_PINS : INTEGER := 16;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : INTEGER := 3;
DWIDTH : INTEGER := 32;
EYE_TEST : STRING := "FALSE";
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
run_traffic_i : IN STD_LOGIC;
manual_clear_error : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0) := (others => '0');
bram_cmd_i : IN STD_LOGIC_VECTOR(38 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
mcb_cmd_en_o : OUT STD_LOGIC;
mcb_cmd_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
mcb_cmd_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
mcb_cmd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full_i : IN STD_LOGIC;
mcb_wr_en_o : OUT STD_LOGIC;
mcb_wr_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
mcb_wr_data_end_o : OUT STD_LOGIC;
mcb_wr_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
mcb_wr_full_i : IN STD_LOGIC;
mcb_wr_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
mcb_rd_en_o : OUT STD_LOGIC;
mcb_rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
mcb_rd_empty_i : IN STD_LOGIC;
mcb_rd_fifo_counts : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
counts_rst : IN STD_LOGIC;
wr_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
rd_data_counts : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
error : OUT STD_LOGIC;
cmp_data_valid : OUT STD_LOGIC;
error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
cmp_error : out std_logic;
cmp_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
mem_rd_data : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
cumlative_dq_lane_error :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
);
END mcb_traffic_gen;
ARCHITECTURE trans OF mcb_traffic_gen IS
COMPONENT mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_gen IS
GENERIC (
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_PRBS";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END COMPONENT;
component afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
component read_data_path IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
ADDR_WIDTH : INTEGER := 32;
CMP_DATA_PIPE_STAGES : INTEGER := 3;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
DQ_ERROR_WIDTH : INTEGER := 1;
SEL_VICTIM_LINE : integer := 3;
MEM_COL_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in std_logic_vector(9 downto 0);
manual_clear_error : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
-- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_rdy_o : OUT STD_LOGIC;
data_valid_i : IN STD_LOGIC;
data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
last_word_rd_o : OUT STD_LOGIC;
data_error_o : OUT STD_LOGIC;
cmp_data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
rd_mdata_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
cmp_data_valid : OUT STD_LOGIC;
cmp_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmp_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
cumlative_dq_lane_error_r :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
);
END component;
component write_data_path IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
ADDR_WIDTH : INTEGER := 32;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_ALL";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
MEM_COL_WIDTH : INTEGER := 10;
EYE_TEST : string := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
last_word_wr_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_mask_o : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
data_wr_end_o : out std_logic
);
END component;
component tg_status IS
GENERIC (
TCQ : TIME := 100 ps;
DWIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
manual_clear_error : IN STD_LOGIC;
data_error_i : IN STD_LOGIC;
cmp_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
rd_data_i : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
cmp_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmp_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full_i : IN STD_LOGIC;
mcb_wr_full_i : IN STD_LOGIC;
mcb_rd_empty_i : IN STD_LOGIC;
error_status : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
error : OUT STD_LOGIC
);
END component;
attribute KEEP : STRING;
attribute MAX_FANOUT : STRING;
function MEM_BLENGTH return integer is
begin
if (MEM_BURST_LEN = 4) then
return 4;
elsif (MEM_BURST_LEN = 8) then
return 8;
else
return 8;
end if;
end function MEM_BLENGTH;
constant MEM_BLEN : INTEGER := MEM_BLENGTH;
SIGNAL mcb_wr_en : STD_LOGIC;
SIGNAL cmd2flow_valid : STD_LOGIC;
SIGNAL cmd2flow_cmd : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL cmd2flow_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmd2flow_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL last_word_rd : STD_LOGIC;
SIGNAL last_word_wr : STD_LOGIC;
SIGNAL flow2cmd_rdy : STD_LOGIC;
SIGNAL wr_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wr_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rd_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL run_traffic_reg : STD_LOGIC;
SIGNAL wr_validB : STD_LOGIC;
SIGNAL wr_valid : STD_LOGIC;
SIGNAL wr_validC : STD_LOGIC;
SIGNAL bram_addr_i : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bram_instr_i : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bram_bl_i : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL upper_end_matched : STD_LOGIC;
SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL lower_end_matched : STD_LOGIC;
SIGNAL addr_o : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- SIGNAL m_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL dcount_rst : STD_LOGIC;
SIGNAL rd_addr_error : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rd_rdy : STD_LOGIC;
SIGNAL cmp_error_int : STD_LOGIC;
SIGNAL cmd_full : STD_LOGIC;
SIGNAL cmp_data_int : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mem_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL cmp_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmp_bl : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rst_ra : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL rst_rb : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL mcb_wr_full_r1 : STD_LOGIC;
SIGNAL mcb_wr_full_r2 : STD_LOGIC;
SIGNAL mcb_rd_empty_r : STD_LOGIC;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL rd_buff_avail : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL data_mode_r_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_mode_r_b : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_mode_r_c : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL tmp_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL error_access_range : STD_LOGIC ;
SIGNAL mcb_rd_empty : STD_LOGIC;
SIGNAL mcb_wr_full : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wr_rdy : STD_LOGIC;
SIGNAL rd_valid : STD_LOGIC;
SIGNAL cmd_rd_en : STD_LOGIC;
-- X-HDL generated signals
SIGNAL xhdl14 : STD_LOGIC_VECTOR(37 DOWNTO 0);
SIGNAL xhdl15 : STD_LOGIC_VECTOR(32 DOWNTO 0);
SIGNAL xhdl17 : STD_LOGIC;
SIGNAL xhdl19 : STD_LOGIC;
SIGNAL ZEROS : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bram_rdy_o_xhdl0 : STD_LOGIC;
SIGNAL mcb_cmd_en_o_xhdl5 : STD_LOGIC;
SIGNAL mcb_cmd_instr_o_xhdl6 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL mcb_cmd_addr_o_xhdl3 : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL mcb_cmd_bl_o_xhdl4 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mcb_wr_data_o_xhdl9 : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mcb_wr_data_end_o_xhdl8 : STD_LOGIC;
SIGNAL mcb_wr_mask_o_xhdl10 : STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
SIGNAL mcb_rd_en : STD_LOGIC;
SIGNAL wr_data_counts_xhdl12 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL rd_data_counts_xhdl11 : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL error_xhdl1 : STD_LOGIC;
SIGNAL error_status_xhdl2 : STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
SIGNAL cmd_fifo_wr : STD_LOGIC;
SIGNAL xfer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fifo_error : STD_LOGIC;
SIGNAL cmd_fifo_rd : STD_LOGIC;
SIGNAL cmd_fifo_empty : STD_LOGIC;
SIGNAL xfer_cmd_bl : STD_LOGIC;
SIGNAL cmd_fifo_full : STD_LOGIC;
SIGNAL rd_mdata_afull_set : STD_LOGIC;
SIGNAL rd_mdata_fifo_afull : STD_LOGIC;
SIGNAL rdpath_data_valid_i : STD_LOGIC;
SIGNAL rdpath_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL rd_mdata_fifo_empty : STD_LOGIC;
SIGNAL rd_v6_mdata : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
SIGNAL mdata_wren : STD_LOGIC;
attribute KEEP of rst_ra : signal is "TRUE";
attribute KEEP of rst_rb : signal is "TRUE";
attribute KEEP of mcb_wr_full_r1 : signal is "TRUE";
attribute KEEP of mcb_wr_full_r2 : signal is "TRUE";
attribute MAX_FANOUT of rst_ra : signal is "20";
attribute MAX_FANOUT of rst_rb : signal is "20";
BEGIN
mem_rd_data <= mem_rd_data_i;
ZEROS <= (others => '0');
cmp_data <= cmp_data_int;
cmp_error <= cmp_error_int;
-- Drive referenced outputs
bram_rdy_o <= bram_rdy_o_xhdl0;
mcb_cmd_en_o <= mcb_cmd_en_o_xhdl5;
mcb_cmd_instr_o <= mcb_cmd_instr_o_xhdl6;
mcb_cmd_addr_o <= mcb_cmd_addr_o_xhdl3;
mcb_cmd_bl_o <= mcb_cmd_bl_o_xhdl4;
mcb_wr_data_o <= mcb_wr_data_o_xhdl9;
mcb_wr_data_end_o <= mcb_wr_data_end_o_xhdl8;
mcb_wr_mask_o <= mcb_wr_mask_o_xhdl10;
mcb_rd_en_o <= mcb_rd_en;
wr_data_counts <= wr_data_counts_xhdl12;
rd_data_counts <= std_logic_vector(rd_data_counts_xhdl11);
error <= error_xhdl1;
error_status <= error_status_xhdl2;
tmp_address <= std_logic_vector(to_unsigned((to_integer(unsigned(mcb_cmd_addr_o_xhdl3)) + to_integer(unsigned(mcb_cmd_bl_o_xhdl4)) * (DWIDTH / 8)),32));
-- tmp_address <= ("00" & mcb_cmd_addr_o_xhdl3 + ("000000000000000000000000" & mcb_cmd_bl_o_xhdl4 * to_stdlogicvector(DWIDTH, 6) / "001000"));
--synthesis translate_off
PROCESS
BEGIN
IF ((MEM_BURST_LEN /= 4) AND (MEM_BURST_LEN /= 8)) THEN
report "Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!";
report "If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic.";
END IF;
WAIT;
END PROCESS;
PROCESS (mcb_cmd_en_o_xhdl5, mcb_cmd_addr_o_xhdl3, mcb_cmd_bl_o_xhdl4, end_addr_i,tmp_address)
BEGIN
IF (mcb_cmd_en_o_xhdl5 = '1' AND (tmp_address > end_addr_i)) THEN
report "Error ! Data access beyond address range"; -- severity ERROR;
error_access_range <= '1';
-- $stop();
END IF;
END PROCESS;
--synthesis translate_on
mcb_rd_empty <= mcb_rd_empty_i;
mcb_wr_full <= mcb_wr_full_i;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
data_mode_r_a <= data_mode_i;
data_mode_r_b <= data_mode_i;
data_mode_r_c <= data_mode_i;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_ra(0)) = '1') THEN
mcb_wr_full_r1 <= '0';
ELSIF (mcb_wr_fifo_counts >= "0111111") THEN
mcb_wr_full_r1 <= '1';
mcb_wr_full_r2 <= '1';
ELSE
mcb_wr_full_r1 <= '0';
mcb_wr_full_r2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_ra(0)) = '1') THEN
mcb_rd_empty_r <= '1';
ELSIF (mcb_rd_fifo_counts <= "0000001") THEN
mcb_rd_empty_r <= '1';
ELSE
mcb_rd_empty_r <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
rst_ra <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
rst_rb <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_reg <= run_traffic_i;
END IF;
END PROCESS;
bram_addr_i <= (bram_cmd_i(29 DOWNTO 0) & "00");
bram_instr_i <= bram_cmd_i(32 DOWNTO 30);
bram_bl_i(5 DOWNTO 0) <= bram_cmd_i(38 DOWNTO 33);
dcount_rst <= counts_rst OR rst_ra(0);
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') then
IF (dcount_rst = '1') THEN
wr_data_counts_xhdl12 <= (OTHERS => '0');
ELSIF (mcb_wr_en = '1') THEN
wr_data_counts_xhdl12 <= wr_data_counts_xhdl12 + std_logic_vector(to_unsigned(DWIDTH/8,48));
END IF;
end if;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') then
IF (dcount_rst = '1') THEN
rd_data_counts_xhdl11 <= (others => '0');
ELSIF (mcb_rd_en = '1') THEN
rd_data_counts_xhdl11 <= rd_data_counts_xhdl11 + std_logic_vector(to_unsigned(DWIDTH/8,48));
END IF;
end if;
END PROCESS;
xhdl13 : IF (SIMULATION = "TRUE") GENERATE
cmd_fifo_wr <= flow2cmd_rdy AND cmd2flow_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mcb_cmd_en_o_xhdl5 = '1') THEN
if (xfer_addr /= (ZEROS(31 downto ADDR_WIDTH) & mcb_cmd_addr_o_xhdl3)) then
fifo_error <= '1';
ELSE
fifo_error <= '0';
END IF;
END IF;
END IF;
END PROCESS;
cmd_fifo_rd <= mcb_cmd_en_o_xhdl5 AND NOT(mcb_cmd_full_i) AND NOT(cmd_fifo_empty);
xhdl14 <= (cmd2flow_bl & cmd2flow_addr);
xfer_cmd_bl <= xhdl15(32);
xfer_addr <= xhdl15(31 downto 0);
cmd_fifo : afifo
GENERIC MAP (
TCQ => TCQ,
DSIZE => 38,
FIFO_DEPTH => 16,
ASIZE => 4,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_ra(0),
wr_en => cmd_fifo_wr,
wr_data => xhdl14,
rd_en => cmd_fifo_rd,
rd_clk => clk_i,
rd_data => xhdl15,
full => cmd_fifo_full,
almost_full => open,
empty => cmd_fifo_empty
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i;
END IF;
END PROCESS;
u_c_gen : cmd_gen
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
PORT_MODE => PORT_MODE,
MEM_BURST_LEN => MEM_BLEN,
NUM_DQ_PINS => NUM_DQ_PINS,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => ADDR_WIDTH,
DWIDTH => DWIDTH,
MEM_COL_WIDTH => MEM_COL_WIDTH,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
PRBS_SADDR_MASK_POS => PRBS_SADDR_MASK_POS,
PRBS_EADDR => PRBS_EADDR,
PRBS_SADDR => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra,
rd_buff_avail_i => rd_buff_avail,
reading_rd_data_i => mcb_rd_en,
force_wrcmd_gen_i => force_wrcmd_gen,
run_traffic_i => run_traffic_reg,
start_addr_i => start_addr_i,
end_addr_i => end_addr_r,
cmd_seed_i => cmd_seed_i,
data_seed_i => data_seed_i,
load_seed_i => load_seed_i,
addr_mode_i => addr_mode_i,
data_mode_i => data_mode_r_a,
instr_mode_i => instr_mode_i,
bl_mode_i => bl_mode_i,
mode_load_i => mode_load_i,
fixed_bl_i => fixed_bl_i,
fixed_addr_i => fixed_addr_i,
fixed_instr_i => fixed_instr_i,
bram_addr_i => bram_addr_i,
bram_instr_i => bram_instr_i,
bram_bl_i => bram_bl_i,
bram_valid_i => bram_valid_i,
bram_rdy_o => bram_rdy_o_xhdl0,
rdy_i => flow2cmd_rdy,
instr_o => cmd2flow_cmd,
addr_o => cmd2flow_addr,
bl_o => cmd2flow_bl,
-- m_addr_o => m_addr,
cmd_o_vld => cmd2flow_valid
);
mcb_cmd_addr_o_xhdl3 <= addr_o(ADDR_WIDTH - 1 DOWNTO 0);
cmd_full <= mcb_cmd_full_i;
mcb_control : mcb_flow_control
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra,
cmd_rdy_o => flow2cmd_rdy,
cmd_valid_i => cmd2flow_valid,
cmd_i => cmd2flow_cmd,
addr_i => cmd2flow_addr,
bl_i => cmd2flow_bl,
mcb_cmd_full => cmd_full,
cmd_o => mcb_cmd_instr_o_xhdl6,
addr_o => addr_o,
bl_o => mcb_cmd_bl_o_xhdl4,
cmd_en_o => mcb_cmd_en_o_xhdl5,
last_word_wr_i => last_word_wr,
wdp_rdy_i => wr_rdy,
wdp_valid_o => wr_valid,
wdp_validB_o => wr_validB,
wdp_validC_o => wr_validC,
wr_addr_o => wr_addr,
wr_bl_o => wr_bl,
last_word_rd_i => last_word_rd,
rdp_rdy_i => rd_rdy,
rdp_valid_o => rd_valid,
rd_addr_o => rd_addr,
rd_bl_o => rd_bl
);
mdata_wren <= not mcb_rd_empty;
rd_mdata_fifo : afifo
GENERIC MAP (
TCQ => TCQ,
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_rb(0),
wr_en => mdata_wren,
wr_data => mcb_rd_data_i,
rd_en => mcb_rd_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
almost_full => open,
empty => rd_mdata_fifo_empty
);
cmd_rd_en <= NOT(mcb_cmd_full_i) AND mcb_cmd_en_o_xhdl5;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_rb(0) = '1') THEN
rd_mdata_afull_set <= '0';
ELSIF (rd_mdata_fifo_afull = '1') THEN
rd_mdata_afull_set <= '1';
END IF;
END IF;
END PROCESS;
PROCESS(rd_mdata_fifo_empty,rd_mdata_afull_set,mcb_rd_empty)
BEGIN
IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
rdpath_data_valid_i <= not(rd_mdata_fifo_empty);
ELSE
rdpath_data_valid_i <= not(mcb_rd_empty);
END IF;
END PROCESS;
PROCESS(rd_v6_mdata,mcb_rd_data_i)
BEGIN
IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
rdpath_rd_data_i <= rd_v6_mdata;
ELSE
rdpath_rd_data_i <= mcb_rd_data_i;
END IF;
END PROCESS;
RD_PATH : IF (PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE") GENERATE
xhdl17 <= NOT(mcb_rd_empty);
read_data_path_inst : read_data_path
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
MEM_BURST_LEN => MEM_BLEN,
cmp_data_pipe_stages => CMP_DATA_PIPE_STAGES,
addr_width => ADDR_WIDTH,
sel_victim_line => SEL_VICTIM_LINE,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
num_dq_pins => NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
mem_col_width => MEM_COL_WIDTH
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_rb,
manual_clear_error => manual_clear_error,
cmd_rdy_o => rd_rdy,
cmd_valid_i => rd_valid,
prbs_fseed_i => data_seed_i,
cmd_sent => mcb_cmd_instr_o_xhdl6,
bl_sent => mcb_cmd_bl_o_xhdl4,
cmd_en_i => cmd_rd_en,
data_mode_i => data_mode_r_b,
last_word_rd_o => last_word_rd,
-- m_addr_i => m_addr,
fixed_data_i => fixed_data_i,
addr_i => rd_addr,
bl_i => rd_bl,
data_rdy_o => mcb_rd_en,
data_valid_i => rdpath_data_valid_i,
data_i => rdpath_rd_data_i,
data_error_o => cmp_error_int,
cmp_data_o => cmp_data_int,
rd_mdata_o => mem_rd_data_i,
cmp_data_valid => cmp_data_valid,
cmp_addr_o => cmp_addr,
cmp_bl_o => cmp_bl,
force_wrcmd_gen_o => force_wrcmd_gen,
rd_buff_avail_o => rd_buff_avail,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
cumlative_dq_lane_error_r => cumlative_dq_lane_error
);
END GENERATE;
write_only_path_inst: IF ( NOT(PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE")) GENERATE
cmp_error_int <= '0';
END GENERATE;
xhdl18 : IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") GENERATE
xhdl19 <= NOT(mcb_wr_full);
write_data_path_inst : write_data_path
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
MEM_BURST_LEN => MEM_BLEN,
addr_width => ADDR_WIDTH,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
mem_col_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_rb,
cmd_rdy_o => wr_rdy,
cmd_valid_i => wr_valid,
cmd_validb_i => wr_validB,
cmd_validc_i => wr_validC,
prbs_fseed_i => data_seed_i,
data_mode_i => data_mode_r_c,
last_word_wr_o => last_word_wr,
-- m_addr_i => m_addr,
fixed_data_i => fixed_data_i,
addr_i => wr_addr,
bl_i => wr_bl,
data_rdy_i => xhdl19,
data_valid_o => mcb_wr_en,
data_o => mcb_wr_data_o_xhdl9,
data_mask_o => mcb_wr_mask_o_xhdl10,
data_wr_end_o => mcb_wr_data_end_o_xhdl8
-- tpt_hdata =>
);
END GENERATE;
mcb_wr_en_o <= mcb_wr_en;
tg_status_inst : tg_status
GENERIC MAP (
dwidth => DWIDTH
)
PORT MAP (
clk_i => clk_i,
rst_i => rst_ra(2),
manual_clear_error => manual_clear_error,
data_error_i => cmp_error_int,
cmp_data_i => cmp_data_int,
rd_data_i => mem_rd_data_i,
cmp_addr_i => cmp_addr,
cmp_bl_i => cmp_bl,
mcb_cmd_full_i => mcb_cmd_full_i,
mcb_wr_full_i => mcb_wr_full,
mcb_rd_empty_i => mcb_rd_empty,
error_status => error_status_xhdl2,
error => error_xhdl1
);
END trans;
|
lgpl-3.0
|
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/imports/SD_card_test/ROM_form.vhd
|
4
|
156716
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Template for a KCPSM6 program memory. This template is primarily for use during code
development including generic parameters for the convenient selection of device family,
program memory size and the ability to include the JTAG Loader hardware for rapid
software development.
Kris Chaplin and Ken Chapman (Xilinx Ltd)
17th September 2010 - First Release
4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance.
3rd March 2011 - Minor adjustments to comments only.
16th August 2011 - Additions and adjustments for support of 7-Series in ISE v13.2.
Simplification of JTAG Loader definition.
23rd November 2012 - 4K program for Spartan-6.
14th March 2013 - Unused address inputs on Virtex-6 and 7-Series BRAMs connected
High to reflect descriptions in UG363 and UG473.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INIT_40 => X"{INIT_40}",
INIT_41 => X"{INIT_41}",
INIT_42 => X"{INIT_42}",
INIT_43 => X"{INIT_43}",
INIT_44 => X"{INIT_44}",
INIT_45 => X"{INIT_45}",
INIT_46 => X"{INIT_46}",
INIT_47 => X"{INIT_47}",
INIT_48 => X"{INIT_48}",
INIT_49 => X"{INIT_49}",
INIT_4A => X"{INIT_4A}",
INIT_4B => X"{INIT_4B}",
INIT_4C => X"{INIT_4C}",
INIT_4D => X"{INIT_4D}",
INIT_4E => X"{INIT_4E}",
INIT_4F => X"{INIT_4F}",
INIT_50 => X"{INIT_50}",
INIT_51 => X"{INIT_51}",
INIT_52 => X"{INIT_52}",
INIT_53 => X"{INIT_53}",
INIT_54 => X"{INIT_54}",
INIT_55 => X"{INIT_55}",
INIT_56 => X"{INIT_56}",
INIT_57 => X"{INIT_57}",
INIT_58 => X"{INIT_58}",
INIT_59 => X"{INIT_59}",
INIT_5A => X"{INIT_5A}",
INIT_5B => X"{INIT_5B}",
INIT_5C => X"{INIT_5C}",
INIT_5D => X"{INIT_5D}",
INIT_5E => X"{INIT_5E}",
INIT_5F => X"{INIT_5F}",
INIT_60 => X"{INIT_60}",
INIT_61 => X"{INIT_61}",
INIT_62 => X"{INIT_62}",
INIT_63 => X"{INIT_63}",
INIT_64 => X"{INIT_64}",
INIT_65 => X"{INIT_65}",
INIT_66 => X"{INIT_66}",
INIT_67 => X"{INIT_67}",
INIT_68 => X"{INIT_68}",
INIT_69 => X"{INIT_69}",
INIT_6A => X"{INIT_6A}",
INIT_6B => X"{INIT_6B}",
INIT_6C => X"{INIT_6C}",
INIT_6D => X"{INIT_6D}",
INIT_6E => X"{INIT_6E}",
INIT_6F => X"{INIT_6F}",
INIT_70 => X"{INIT_70}",
INIT_71 => X"{INIT_71}",
INIT_72 => X"{INIT_72}",
INIT_73 => X"{INIT_73}",
INIT_74 => X"{INIT_74}",
INIT_75 => X"{INIT_75}",
INIT_76 => X"{INIT_76}",
INIT_77 => X"{INIT_77}",
INIT_78 => X"{INIT_78}",
INIT_79 => X"{INIT_79}",
INIT_7A => X"{INIT_7A}",
INIT_7B => X"{INIT_7B}",
INIT_7C => X"{INIT_7C}",
INIT_7D => X"{INIT_7D}",
INIT_7E => X"{INIT_7E}",
INIT_7F => X"{INIT_7F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}",
INITP_08 => X"{INITP_08}",
INITP_09 => X"{INITP_09}",
INITP_0A => X"{INITP_0A}",
INITP_0B => X"{INITP_0B}",
INITP_0C => X"{INITP_0C}",
INITP_0D => X"{INITP_0D}",
INITP_0E => X"{INITP_0E}",
INITP_0F => X"{INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_40}",
INIT_01 => X"{[8:0]_INIT_41}",
INIT_02 => X"{[8:0]_INIT_42}",
INIT_03 => X"{[8:0]_INIT_43}",
INIT_04 => X"{[8:0]_INIT_44}",
INIT_05 => X"{[8:0]_INIT_45}",
INIT_06 => X"{[8:0]_INIT_46}",
INIT_07 => X"{[8:0]_INIT_47}",
INIT_08 => X"{[8:0]_INIT_48}",
INIT_09 => X"{[8:0]_INIT_49}",
INIT_0A => X"{[8:0]_INIT_4A}",
INIT_0B => X"{[8:0]_INIT_4B}",
INIT_0C => X"{[8:0]_INIT_4C}",
INIT_0D => X"{[8:0]_INIT_4D}",
INIT_0E => X"{[8:0]_INIT_4E}",
INIT_0F => X"{[8:0]_INIT_4F}",
INIT_10 => X"{[8:0]_INIT_50}",
INIT_11 => X"{[8:0]_INIT_51}",
INIT_12 => X"{[8:0]_INIT_52}",
INIT_13 => X"{[8:0]_INIT_53}",
INIT_14 => X"{[8:0]_INIT_54}",
INIT_15 => X"{[8:0]_INIT_55}",
INIT_16 => X"{[8:0]_INIT_56}",
INIT_17 => X"{[8:0]_INIT_57}",
INIT_18 => X"{[8:0]_INIT_58}",
INIT_19 => X"{[8:0]_INIT_59}",
INIT_1A => X"{[8:0]_INIT_5A}",
INIT_1B => X"{[8:0]_INIT_5B}",
INIT_1C => X"{[8:0]_INIT_5C}",
INIT_1D => X"{[8:0]_INIT_5D}",
INIT_1E => X"{[8:0]_INIT_5E}",
INIT_1F => X"{[8:0]_INIT_5F}",
INIT_20 => X"{[8:0]_INIT_60}",
INIT_21 => X"{[8:0]_INIT_61}",
INIT_22 => X"{[8:0]_INIT_62}",
INIT_23 => X"{[8:0]_INIT_63}",
INIT_24 => X"{[8:0]_INIT_64}",
INIT_25 => X"{[8:0]_INIT_65}",
INIT_26 => X"{[8:0]_INIT_66}",
INIT_27 => X"{[8:0]_INIT_67}",
INIT_28 => X"{[8:0]_INIT_68}",
INIT_29 => X"{[8:0]_INIT_69}",
INIT_2A => X"{[8:0]_INIT_6A}",
INIT_2B => X"{[8:0]_INIT_6B}",
INIT_2C => X"{[8:0]_INIT_6C}",
INIT_2D => X"{[8:0]_INIT_6D}",
INIT_2E => X"{[8:0]_INIT_6E}",
INIT_2F => X"{[8:0]_INIT_6F}",
INIT_30 => X"{[8:0]_INIT_70}",
INIT_31 => X"{[8:0]_INIT_71}",
INIT_32 => X"{[8:0]_INIT_72}",
INIT_33 => X"{[8:0]_INIT_73}",
INIT_34 => X"{[8:0]_INIT_74}",
INIT_35 => X"{[8:0]_INIT_75}",
INIT_36 => X"{[8:0]_INIT_76}",
INIT_37 => X"{[8:0]_INIT_77}",
INIT_38 => X"{[8:0]_INIT_78}",
INIT_39 => X"{[8:0]_INIT_79}",
INIT_3A => X"{[8:0]_INIT_7A}",
INIT_3B => X"{[8:0]_INIT_7B}",
INIT_3C => X"{[8:0]_INIT_7C}",
INIT_3D => X"{[8:0]_INIT_7D}",
INIT_3E => X"{[8:0]_INIT_7E}",
INIT_3F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_08}",
INITP_01 => X"{[8:0]_INITP_09}",
INITP_02 => X"{[8:0]_INITP_0A}",
INITP_03 => X"{[8:0]_INITP_0B}",
INITP_04 => X"{[8:0]_INITP_0C}",
INITP_05 => X"{[8:0]_INITP_0D}",
INITP_06 => X"{[8:0]_INITP_0E}",
INITP_07 => X"{[8:0]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_40}",
INIT_01 => X"{[17:9]_INIT_41}",
INIT_02 => X"{[17:9]_INIT_42}",
INIT_03 => X"{[17:9]_INIT_43}",
INIT_04 => X"{[17:9]_INIT_44}",
INIT_05 => X"{[17:9]_INIT_45}",
INIT_06 => X"{[17:9]_INIT_46}",
INIT_07 => X"{[17:9]_INIT_47}",
INIT_08 => X"{[17:9]_INIT_48}",
INIT_09 => X"{[17:9]_INIT_49}",
INIT_0A => X"{[17:9]_INIT_4A}",
INIT_0B => X"{[17:9]_INIT_4B}",
INIT_0C => X"{[17:9]_INIT_4C}",
INIT_0D => X"{[17:9]_INIT_4D}",
INIT_0E => X"{[17:9]_INIT_4E}",
INIT_0F => X"{[17:9]_INIT_4F}",
INIT_10 => X"{[17:9]_INIT_50}",
INIT_11 => X"{[17:9]_INIT_51}",
INIT_12 => X"{[17:9]_INIT_52}",
INIT_13 => X"{[17:9]_INIT_53}",
INIT_14 => X"{[17:9]_INIT_54}",
INIT_15 => X"{[17:9]_INIT_55}",
INIT_16 => X"{[17:9]_INIT_56}",
INIT_17 => X"{[17:9]_INIT_57}",
INIT_18 => X"{[17:9]_INIT_58}",
INIT_19 => X"{[17:9]_INIT_59}",
INIT_1A => X"{[17:9]_INIT_5A}",
INIT_1B => X"{[17:9]_INIT_5B}",
INIT_1C => X"{[17:9]_INIT_5C}",
INIT_1D => X"{[17:9]_INIT_5D}",
INIT_1E => X"{[17:9]_INIT_5E}",
INIT_1F => X"{[17:9]_INIT_5F}",
INIT_20 => X"{[17:9]_INIT_60}",
INIT_21 => X"{[17:9]_INIT_61}",
INIT_22 => X"{[17:9]_INIT_62}",
INIT_23 => X"{[17:9]_INIT_63}",
INIT_24 => X"{[17:9]_INIT_64}",
INIT_25 => X"{[17:9]_INIT_65}",
INIT_26 => X"{[17:9]_INIT_66}",
INIT_27 => X"{[17:9]_INIT_67}",
INIT_28 => X"{[17:9]_INIT_68}",
INIT_29 => X"{[17:9]_INIT_69}",
INIT_2A => X"{[17:9]_INIT_6A}",
INIT_2B => X"{[17:9]_INIT_6B}",
INIT_2C => X"{[17:9]_INIT_6C}",
INIT_2D => X"{[17:9]_INIT_6D}",
INIT_2E => X"{[17:9]_INIT_6E}",
INIT_2F => X"{[17:9]_INIT_6F}",
INIT_30 => X"{[17:9]_INIT_70}",
INIT_31 => X"{[17:9]_INIT_71}",
INIT_32 => X"{[17:9]_INIT_72}",
INIT_33 => X"{[17:9]_INIT_73}",
INIT_34 => X"{[17:9]_INIT_74}",
INIT_35 => X"{[17:9]_INIT_75}",
INIT_36 => X"{[17:9]_INIT_76}",
INIT_37 => X"{[17:9]_INIT_77}",
INIT_38 => X"{[17:9]_INIT_78}",
INIT_39 => X"{[17:9]_INIT_79}",
INIT_3A => X"{[17:9]_INIT_7A}",
INIT_3B => X"{[17:9]_INIT_7B}",
INIT_3C => X"{[17:9]_INIT_7C}",
INIT_3D => X"{[17:9]_INIT_7D}",
INIT_3E => X"{[17:9]_INIT_7E}",
INIT_3F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_08}",
INITP_01 => X"{[17:9]_INITP_09}",
INITP_02 => X"{[17:9]_INITP_0A}",
INITP_03 => X"{[17:9]_INITP_0B}",
INITP_04 => X"{[17:9]_INITP_0C}",
INITP_05 => X"{[17:9]_INITP_0D}",
INITP_06 => X"{[17:9]_INITP_0E}",
INITP_07 => X"{[17:9]_INITP_0F}")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate
begin
BSCAN_BLOCK_inst : BSCAN_SPARTAN6
generic map ( JTAG_CHAIN => C_JTAG_CHAIN)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_SPARTAN6_gen;
--
BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate
begin
BSCAN_BLOCK_inst: BSCAN_VIRTEX6
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_VIRTEX6_gen;
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
lgpl-3.0
|
chiggs/oc_mkjpeg
|
design/mdct/MDCT_PKG.vhd
|
9
|
2517
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : MDCT_PKG
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : MDCT_PKG.VHD
-- Created : Sat Mar 5 2006
--
--------------------------------------------------------------------------------
--
-- Description : Package for MDCT core
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package MDCT_PKG is
constant IP_W : INTEGER := 8;
constant OP_W : INTEGER := 12;
constant N : INTEGER := 8;
constant COE_W : INTEGER := 12;
constant ROMDATA_W : INTEGER := COE_W+2;
constant ROMADDR_W : INTEGER := 6;
constant RAMDATA_W : INTEGER := 10;
constant RAMADRR_W : INTEGER := 6;
constant COL_MAX : INTEGER := N-1;
constant ROW_MAX : INTEGER := N-1;
constant LEVEL_SHIFT : INTEGER := 128;
constant DA_W : INTEGER := ROMDATA_W+IP_W;
constant DA2_W : INTEGER := DA_W+2;
-- 2's complement numbers
constant AP : INTEGER := 1448;
constant BP : INTEGER := 1892;
constant CP : INTEGER := 784;
constant DP : INTEGER := 2009;
constant EP : INTEGER := 1703;
constant FP : INTEGER := 1138;
constant GP : INTEGER := 400;
constant AM : INTEGER := -1448;
constant BM : INTEGER := -1892;
constant CM : INTEGER := -784;
constant DM : INTEGER := -2009;
constant EM : INTEGER := -1703;
constant FM : INTEGER := -1138;
constant GM : INTEGER := -400;
type T_ROM1DATAO is array(0 to 8) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM1ADDRO is array(0 to 8) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
type T_ROM2DATAO is array(0 to 10) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM2ADDRO is array(0 to 10) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
end MDCT_PKG;
|
lgpl-3.0
|
chiggs/oc_mkjpeg
|
design/top/JpegEnc.vhd
|
2
|
18585
|
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof
);
-------------------------------------------------------------------
-- BUF_FIFO
-------------------------------------------------------------------
U_BUF_FIFO : entity work.BUF_FIFO
port map
(
CLK => CLK,
RST => RST,
-- HOST PROG
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof,
-- HOST DATA
iram_wren => iram_wren,
iram_wdata => iram_wdata,
fifo_almost_full => iram_fifo_afull,
-- FDCT
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- output IF
outif_almost_full => outif_almost_full,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
huf_ready => huf_ready,
huf_sm_settings => huf_sm_settings,
-- ByteStuffdr
bs_start => bs_start,
bs_ready => bs_ready,
bs_sm_settings => bs_sm_settings,
-- JFIF GEN
jfif_start => jfif_start,
jfif_ready => jfif_ready,
jfif_eoi => jfif_eoi,
-- OUT MUX
out_mux_ctrl => out_mux_ctrl
);
-------------------------------------------------------------------
-- FDCT
-------------------------------------------------------------------
U_FDCT : entity work.FDCT
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => fdct_start,
ready_pb => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- BUF_FIFO
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
-- ZIG ZAG
zz_buf_sel => zz_buf_sel,
zz_rd_addr => zz_rd_addr,
zz_data => zz_data,
zz_rden => zz_rden,
-- HOST
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof
);
-------------------------------------------------------------------
-- ZigZag top level
-------------------------------------------------------------------
U_ZZ_TOP : entity work.ZZ_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
U_RLE_TOP : entity work.RLE_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => rle_start,
ready_pb => rle_ready,
rle_sm_settings => rle_sm_settings,
-- HUFFMAN
huf_buf_sel => huf_buf_sel,
huf_rden => huf_rden,
huf_runlength => huf_runlength,
huf_size => huf_size,
huf_amplitude => huf_amplitude,
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
);
-------------------------------------------------------------------
-- Huffman Encoder
-------------------------------------------------------------------
U_Huffman : entity work.Huffman
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => huf_start,
ready_pb => huf_ready,
huf_sm_settings => huf_sm_settings,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
-- RLE
rle_buf_sel => huf_buf_sel,
rd_en => huf_rden,
runlength => huf_runlength,
VLI_size => huf_size,
VLI => huf_amplitude,
d_val => huf_dval,
rle_fifo_empty => huf_fifo_empty,
-- Byte Stuffer
bs_buf_sel => bs_buf_sel,
bs_fifo_empty => bs_fifo_empty,
bs_rd_req => bs_rd_req,
bs_packed_byte => bs_packed_byte
);
-------------------------------------------------------------------
-- Byte Stuffer
-------------------------------------------------------------------
U_ByteStuffer : entity work.ByteStuffer
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => bs_start,
ready_pb => bs_ready,
-- HOST IF
sof => sof,
num_enc_bytes => num_enc_bytes,
outram_base_addr => outram_base_addr,
-- Huffman
huf_buf_sel => bs_buf_sel,
huf_fifo_empty => bs_fifo_empty,
huf_rd_req => bs_rd_req,
huf_packed_byte => bs_packed_byte,
-- OUT RAM
ram_byte => bs_ram_byte,
ram_wren => bs_ram_wren,
ram_wraddr => bs_ram_wraddr
);
-------------------------------------------------------------------
-- JFIF Generator
-------------------------------------------------------------------
U_JFIFGen : entity work.JFIFGen
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start => jfif_start,
ready => jfif_ready,
eoi => jfif_eoi,
-- ByteStuffer
num_enc_bytes => num_enc_bytes,
-- HOST IF
qwren => qwren,
qwaddr => qaddr,
qwdata => qdata,
image_size_reg => image_size_reg,
image_size_reg_wr => img_size_wr,
-- OUT RAM
ram_byte => jfif_ram_byte,
ram_wren => jfif_ram_wren,
ram_wraddr => jfif_ram_wraddr
);
image_size_reg <= img_size_x & img_size_y;
-------------------------------------------------------------------
-- OutMux
-------------------------------------------------------------------
U_OutMux : entity work.OutMux
port map
(
CLK => CLK,
RST => RST,
-- CTRL
out_mux_ctrl => out_mux_ctrl,
-- ByteStuffer
bs_ram_byte => bs_ram_byte,
bs_ram_wren => bs_ram_wren,
bs_ram_wraddr => bs_ram_wraddr,
-- ByteStuffer
jfif_ram_byte => jfif_ram_byte,
jfif_ram_wren => jfif_ram_wren,
jfif_ram_wraddr => jfif_ram_wraddr,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr
);
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
lgpl-3.0
|
chiggs/oc_mkjpeg
|
design/quantizer/ROMR.vhd
|
2
|
5447
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
|
lgpl-3.0
|
chiggs/oc_mkjpeg
|
tb/vhdl/ClkGen.vhd
|
2
|
2500
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ClkGen is
port (
CLK : out std_logic;
RST : out std_logic
);
end entity ClkGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture ClkGen_rtl of ClkGen is
constant CLOCK_PERIOD : time := 10 ns;
signal clk_s : std_logic := '0';
signal rst_s : std_logic := '0';
begin
-- Clock generator (50% duty cycle)
clk_gen: process
begin
clk_s <= '0';
wait for CLOCK_PERIOD/2;
clk_s <= '1';
wait for CLOCK_PERIOD/2;
end process clk_gen;
CLK <= clk_s;
reset_gen: process
begin
wait until rising_edge(clk_s);
rst_s <= '0';
wait until rising_edge(clk_s);
rst_s <= '1';
wait until rising_edge(clk_s);
rst_s <= '0';
wait;
end process reset_gen;
RST <= rst_s;
end architecture ClkGen_rtl;
|
lgpl-3.0
|
chiggs/oc_mkjpeg
|
design/quantizer/s_divider.vhd
|
2
|
6676
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : Signed Pipelined Divider core --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : S_DIVIDER.VHD --
-- Created : Sat Aug 26 2006 --
-- Modified : Thu Mar 12 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Signed Pipelined Divider --
-- --
-- dividend allowable range of -2**SIZE_C to 2**SIZE_C-1 [SIGNED number] --
-- divisor allowable range of 1 to (2**SIZE_C)/2-1 [UNSIGNED number] --
-- pipeline latency is 2*SIZE_C+2 (time from latching input to result ready) --
-- when pipeline is full new result is generated every clock cycle --
-- Non-Restoring division algorithm --
-- Use SIZE_C constant in divider entity to adjust bit width --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity s_divider is
generic
(
SIZE_C : INTEGER := 32
) ; -- SIZE_C: Number of bits
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
d : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
q : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
r : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
round : out STD_LOGIC
) ;
end s_divider ;
architecture str of s_divider is
type S_ARRAY is array(0 to SIZE_C+3) of unsigned(SIZE_C-1 downto 0);
type S2_ARRAY is array(0 to SIZE_C+1) of unsigned(2*SIZE_C-1 downto 0);
signal d_s : S_ARRAY;
signal q_s : S_ARRAY;
signal r_s : S2_ARRAY;
signal diff : S_ARRAY;
signal qu_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal ru_s : unsigned(SIZE_C-1 downto 0);
signal qu_s2 : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal ru_s2 : unsigned(SIZE_C-1 downto 0);
signal d_reg : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal pipeline_reg : STD_LOGIC_VECTOR(SIZE_C+3-1 downto 0);
signal r_reg : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
begin
pipeline : process(clk,rst)
begin
if rst = '1' then
for k in 0 to SIZE_C loop
r_s(k) <= (others => '0');
q_s(k) <= (others => '0');
d_s(k) <= (others => '0');
end loop;
pipeline_reg <= (others => '0');
elsif clk = '1' and clk'event then
-- negative number
if a(SIZE_C-1) = '1' then
-- negate negative number to create positive
r_s(0) <= unsigned(resize(unsigned(not(SIGNED(a)) + TO_SIGNED(1,SIZE_C)),2*SIZE_C));
-- left shift
pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '1';
else
r_s(0) <= resize(unsigned(a),2*SIZE_C);
-- left shift
pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '0';
end if;
d_s(0) <= unsigned(d);
q_s(0) <= (others => '0');
-- pipeline
for k in 0 to SIZE_C loop
-- test remainder if positive/negative
if r_s(k)(2*SIZE_C-1) = '0' then
-- shift r_tmp one bit left and subtract d_tmp from upper part of r_tmp
r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) - d_s(k);
else
r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) + d_s(k);
end if;
-- shift r_tmp one bit left (lower part)
r_s(k+1)(SIZE_C-1 downto 0) <= r_s(k)(SIZE_C-2 downto 0) & '0';
if diff(k)(SIZE_C-1) = '0' then
q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '1';
else
q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '0';
end if;
d_s(k+1) <= d_s(k);
end loop;
end if;
end process;
G_DIFF: for x in 0 to SIZE_C generate
diff(x) <= r_s(x)(2*SIZE_C-2 downto SIZE_C-1) - d_s(x) when r_s(x)(2*SIZE_C-1) = '0'
else r_s(x)(2*SIZE_C-2 downto SIZE_C-1) + d_s(x);
end generate G_DIFF;
qu_s <= STD_LOGIC_VECTOR( q_s(SIZE_C) );
ru_s <= r_s(SIZE_C)(2*SIZE_C-1 downto SIZE_C);
process(clk,rst)
begin
if rst = '1' then
q <= (others => '0');
r_reg <= (others => '0');
round <= '0';
elsif clk = '1' and clk'event then
if ru_s(SIZE_C-1) = '0' then
ru_s2 <= (ru_s);
else
ru_s2 <= (unsigned(ru_s) + d_s(SIZE_C));
end if;
qu_s2 <= qu_s;
-- negative number
if pipeline_reg(SIZE_C+1) = '1' then
-- negate positive number to create negative
q <= STD_LOGIC_VECTOR(not(SIGNED(qu_s2)) + TO_SIGNED(1,SIZE_C));
r_reg <= STD_LOGIC_VECTOR(not(SIGNED(ru_s2)) + TO_SIGNED(1,SIZE_C));
else
q <= STD_LOGIC_VECTOR(qu_s2);
r_reg <= STD_LOGIC_VECTOR(ru_s2);
end if;
-- if 2*remainder >= divisor then add 1 to round to nearest integer
if (ru_s2(SIZE_C-2 downto 0) & '0') >= d_s(SIZE_C+1) then
round <= '1';
else
round <= '0';
end if;
end if;
end process;
-- remainder
r <= r_reg;
end str;
|
lgpl-3.0
|
sandrosalvato94/System-Design-Project
|
src/polito/sdp2017/Tests/IPManager_HardwareGroup.vhd
|
2
|
5201
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.CONSTANTS.all;
entity IP_MANAGER is
port(
clk : in std_logic;
rst : in std_logic;
data_in : out std_logic_vector (DATA_WIDTH-1 downto 0);
data_out : in std_logic_vector (DATA_WIDTH-1 downto 0);
add : out std_logic_vector(ADD_WIDTH-1 downto 0);
W_enable : out std_logic;
R_enable : out std_logic;
generic_en : out std_logic;
interrupt : out std_logic;
row_0 : in std_logic_vector (DATA_WIDTH-1 downto 0);
data_in_IPs : in data_array;
data_out_IPs : out data_array;
add_IPs : in add_array;
W_enable_IPs : in std_logic_vector(0 to NUM_IPS-1);
R_enable_IPs : in std_logic_vector(0 to NUM_IPS-1);
generic_en_IPs : in std_logic_vector(0 to NUM_IPS-1);
enable_IPs : out std_logic_vector(0 to NUM_IPS-1);
ack_IPs : out std_logic_vector(0 to NUM_IPS-1);
interrupt_IPs : in std_logic_vector(0 to NUM_IPS-1)
);
end IP_MANAGER;
architecture BEHAVIOURAL of IP_MANAGER is
begin
-- PROC_1 manages the behavior of the IPMANAGER.
PROC_1: process (clk, rst)
begin -- process Clk
if Rst = '1' then -- asynchronous reset (active high)
data_in <= (others => '0');
data_out_IPs <= (others => ((others => '0')));
add <= (others => '0');
W_enable <= '0';
R_enable <= '0';
generic_en <= '0';
enable_IPs <= (others => '0');
ack_IPs <= (others => '0');
interrupt <= '0';
elsif Clk'event and Clk = '1' then -- rising clock edge
-- NOT configuration mode:
if (conv_integer(row_0(IPADD_POS downto 0)) /= 0 ) then
-- Assuring that only one IPs is enable in case the cpu decides to change the IP core without properly ending the transaction
enable_IPs <= (others => '0');
data_in <= (others => '0');
data_out_IPs <= (others => ((others => '0')));
add <= (others => '0');
W_enable <= '0';
R_enable <= '0';
generic_en <= '0';
ack_IPs <= (others => '0');
-- Releasing interrupt:
if (row_0(INT_POS) = '1' AND row_0(BE_POS) = '1' )then
interrupt <= '0';
ack_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= '1';
end if;
-- Begin ( or continue ) transaction:
if row_0(BE_POS) = '1' then
enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= '1';
data_in <= data_in_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
data_out_IPs(conv_integer(row_0(IPADD_POS downto 0))-1) <= data_out ;
add <= add_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
W_enable <= W_enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
R_enable <= R_enable_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
generic_en <= generic_en_IPs(conv_integer(row_0(IPADD_POS downto 0))-1);
-- Interrupt mode:
-- If some IPs raise the interrupt and there is no current transaction
elsif (row_0(BE_POS) = '0' and conv_integer(interrupt_IPs) /= 0 ) then
for I in (NUM_IPS-1) downto 0 loop -- scan from the lower priority IP to the higher (this avoid to insert a break statement, that is not synthesizable)
if (interrupt_IPs(I) = '1') then -- check if it rises the interrupt signal and the transaction with the Master is ended
--Write in row_0 the address of the ip with the highest priority
add <= (others => '0');
data_in <= row_0(DATA_WIDTH-1 downto 12) & conv_std_logic_vector(I+1, IPADD_POS+1);
W_enable <= '1';
R_enable <= '0';
generic_en <= '1';
-- Signal the cpu that one interrupt request must be served
interrupt <= '1';
end if;
end loop;
end if;
---- TODO : Future feature
---- Manager configuration mode:
-- else
end if;
end if;
end process PROC_1;
end architecture;
|
lgpl-3.0
|
lunod/lt24_ctrl
|
rtl/cpt_pix.vhd
|
1
|
2854
|
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity cpt_pix is
port(clk : in std_logic;
resetn : in std_logic;
clr_cptpix: in std_logic;
inc_cptpix: in std_logic;
end_cptpix: out std_logic;
x : out std_logic_vector(7 downto 0); -- [0:239]
y : out std_logic_vector(8 downto 0)); -- [0:319]
end entity cpt_pix;
---------------------------------------------------------------------------
architecture rtl of cpt_pix is
constant X_PIXELS: natural := 240;
constant Y_PIXELS: natural := 320;
signal cpt_x: unsigned(x'range);
signal cpt_y: unsigned(y'range);
begin
update_cpt: process(clk, resetn)
begin
if resetn = '0' then
cpt_x <= (others => '0');
cpt_y <= (others => '0');
end_cptpix <= '0';
elsif rising_edge(clk) then
if clr_cptpix = '1' then
cpt_x <= (others => '0');
cpt_y <= (others => '0');
end_cptpix <= '0';
elsif inc_cptpix = '1' then
-- DFFs on output signals to minimise critical path
if (cpt_y = Y_PIXELS - 1) and (cpt_x = X_PIXELS - 2) then
end_cptpix <= '1';
else
end_cptpix <= '0';
end if;
if cpt_x = X_PIXELS - 1 then
cpt_x <= (others => '0');
if cpt_y = Y_PIXELS - 1 then
cpt_y <= (others => '0');
else
cpt_y <= cpt_y + 1;
end if; -- cpt_y = Y_PIXELS - 1
else
cpt_x <= cpt_x + 1;
end if; -- cpt_x = X_PIXELS - 1
end if; -- if clr_cptpix = '1'
end if; -- if resetn = '0'
end process update_cpt;
x <= std_logic_vector(cpt_x);
y <= std_logic_vector(cpt_y);
end architecture rtl;
---------------------------------------------------------------------------
|
lgpl-3.0
|
LaNoC-UFC/Phoenix
|
NoC/FPPM_AA00.vhd
|
2
|
3418
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.HammingPack16.all;
use work.NoCPackage.regNport;
entity FPPM is
port
(
clock : in std_logic;
reset_in : in std_logic; -- reset geral da NoC
rx : in regHamm_Nport; -- rx (sinal que indica que estou recebendo transmissao)
statusHamming : in array_statusHamming; -- status (sem erro, erro corrigido, erro detectado) das 4 portas (EAST,WEST,NORTH,SOUTH)
write_FaultTable : out regHamm_Nport; -- sinal para indicar escrita na tabela de falhas
row_FaultTablePorts_out : out row_FaultTable_Ports -- linha a ser escrita na tabela de falhas
);
end FPPM;
architecture FPPM of FPPM is
-- CUIDADO! Os contadores tem apenas COUNTERS_SIZE bits!
constant N: integer range 1 to 31 := 8;
constant M: integer range 1 to 31 := 4;
constant P: integer range 1 to 31 := 30;
constant COUNTER_UPDATE_TABLE: integer := 1; -- numero de flits recebidos necessarios para atualizar a tabela
begin
FPPM_generate: for i in 0 to (HAMM_NPORT-1) generate
begin
process(clock, reset_in)
variable counter_write: integer range 0 to COUNTER_UPDATE_TABLE;
variable reset: std_logic := '0';
variable counter_N, counter_M, counter_P: unsigned((COUNTERS_SIZE-1) downto 0);
variable link_status: unsigned(1 downto 0) := "00";
begin
if (reset_in='1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
if (clock'event and clock='1' and rx(i)='1') then
--counter_write := counter_write + 1;
case statusHamming(i) is
when NE =>
counter_N := counter_N + 1;
if (counter_N = N) then
link_status := "00";
reset := '1';
end if;
when EC =>
counter_M := counter_M + 1;
if (counter_M = M) then
link_status := "01";
reset := '1';
end if;
when ED =>
counter_P := counter_P + 1;
if (counter_P = P) then
link_status := "10";
reset := '1';
end if;
when others => null;
end case;
if (reset = '1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
end if;
if (counter_write = COUNTER_UPDATE_TABLE) then
--if (false) then
write_FaultTable(i) <= '1';
row_FaultTablePorts_out(i) <= std_logic_vector(link_status & counter_N & counter_M & counter_P);
counter_write := 0;
else
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
elsif (rx(i)='0') then
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
end process;
end generate;
end FPPM;
|
lgpl-3.0
|
LaNoC-UFC/Phoenix
|
NoC/FaultInjector.vhd
|
2
|
6337
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.math_real.ALL;
use STD.textio.all;
use work.HammingPack16.all;
use work.NoCPackage.all;
entity FaultInjector is
generic(
address: regflit;
SEED_VAL_1: positive := 1;
SEED_VAL_2: positive := 1
);
port(
clock: in std_logic;
reset: in std_logic;
tx: in regNport;
data_in: in arrayNport_regphit;
data_out: out arrayNport_regphit;
credit: in regNport
);
end FaultInjector;
architecture FaultInjector of FaultInjector is
constant SA0: integer := 0; -- stuck-at 0
constant SA1: integer := 1; -- stuck-at 1
constant BF: integer := 2; -- bitflit error
constant OK: integer := 3; -- OK (sem falha)
type fault_bits is array (0 to 2) of regphit; -- 3 possiveis falhas (SA0, SA1, BT)
type arrayFaultNports is array (0 to NPORT-1) of fault_bits;
signal FaultNPorts: arrayFaultNports := (others=>(others=>(others=>'0')));
begin
-- aqui eh escolhido os bits dos dados de saida
-- baseados nos bits selecionados que ocorrerao a injecao de falha
-- tipos de falha: stuck-at 0, stuck-at 1, bitflip
data_fault: for i in 0 to NPORT-1 generate
begin
bit_fault: for j in 0 to TAM_PHIT-1 generate
begin
data_out(i)(j) <= '0' when (FaultNPorts(i)(SA0)(j)='1') else -- stuck-at 0
'1' when (FaultNPorts(i)(SA1)(j)='1') else -- stuck-at 1
not data_in(i)(j) when (FaultNPorts(i)(BF)(j)='1') -- bitflip
else data_in(i)(j); -- normal
end generate bit_fault;
end generate data_fault;
process
file file_pointer: text;
variable fstatus: file_open_status;
variable line_num : line;
variable tmp_word: string (1 to 50);
variable tmp_line: line;
variable line_counter: integer := 0;
variable char_pointer: integer;
variable char_pointer_tmp: integer;
variable time_now: integer := 0;
variable fault_rate: real;
variable fault_port: integer;
type real_array is array (0 to NPORT-1) of real;
variable fault_rate_Nports: real_array := (others=>0.0);
variable seed1: positive := SEED_VAL_1;
variable seed2: positive := SEED_VAL_2;
variable rand: real;
begin
file_open(fstatus, file_pointer,"fault_"&to_hstring(address)&".txt",READ_MODE);
if(fstatus = OPEN_OK) then
while not endfile(file_pointer) loop
-- limpa a string tmp_word
for i in 1 to tmp_word'length loop
tmp_word(i) := NUL;
end loop;
readline(file_pointer,line_num);
line_counter := line_counter + 1;
char_pointer := line_num'low;
-- copia a string da linha lida ate encontrar espaco (ira copiar o tempo do inicio da falha)
while (line_num(char_pointer) /= ' ' and char_pointer <= line_num'high) loop
tmp_word(char_pointer) := line_num(char_pointer);
char_pointer := char_pointer + 1;
end loop;
-- converte string lida (taxa de falhas) para real
write(tmp_line,tmp_word);
read(tmp_line,fault_rate);
-- limpa a string tmp_word
for i in 1 to tmp_word'length loop
tmp_word(i) := NUL;
end loop;
char_pointer := char_pointer + 1;
char_pointer_tmp := 1;
-- copia a string da linha lida ate encontrar espaco ou fim (ira copiar a porta de saida)
while (line_num(char_pointer) /= ' ' and line_num(char_pointer) /= NUL and char_pointer < line_num'high) loop
tmp_word(char_pointer_tmp) := line_num(char_pointer);
char_pointer := char_pointer + 1;
char_pointer_tmp := char_pointer_tmp + 1;
end loop;
-- copiar o ultimo character
tmp_word(char_pointer_tmp) := line_num(char_pointer);
if (tmp_word(1 to 4) = "EAST") then
fault_port := EAST;
elsif (tmp_word(1 to 4) = "WEST") then
fault_port := WEST;
elsif (tmp_word(1 to 5) = "NORTH") then
fault_port := NORTH;
elsif (tmp_word(1 to 5) = "SOUTH") then
fault_port := SOUTH;
elsif (tmp_word(1 to 5) = "LOCAL") then
fault_port := LOCAL;
else
assert false report "Erro de leitura da porta de saida: linha "&integer'image(line_counter)&" do arquivo fault_00"&to_hstring(address)&".txt" severity error;
wait;
end if;
-- limpa a string fault_type_string
for i in 1 to tmp_word'length loop
tmp_word(i) := NUL;
end loop;
fault_rate_Nports(fault_port) := fault_rate;
Deallocate(tmp_line);
end loop; -- fim da leitura do arquivo
wait until reset='0';
wait until clock='1';
wait for 1 ns;
while true loop
for i in 0 to NPORT-1 loop
if (tx(i)='1' and credit(i)='1') then
uniform(seed1, seed2, rand);
if (fault_rate_Nports(i) >= rand) then
FaultNPorts(i)(BF)(0) <= '1';
FaultNPorts(i)(BF)(1) <= '1';
else
FaultNPorts(i)(BF)(0) <= '0';
FaultNPorts(i)(BF)(1) <= '0';
end if;
else
FaultNPorts(i)(BF)(0) <= '0';
FaultNPorts(i)(BF)(1) <= '0';
end if;
end loop;
wait for CLOCK_PERIOD;
end loop;
else
report "input fault file fault_" & to_hstring(address) & ".txt could not be open";
end if;
wait;
end process;
end FaultInjector;
|
lgpl-3.0
|
LaNoC-UFC/Phoenix
|
topNoC.vhd
|
2
|
2098
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use STD.textio.all;
use work.NoCPackage.all;
entity topNoC is
end;
architecture topNoC of topNoC is
signal clock : regNrot:=(others=>'0');
signal reset : std_logic;
signal clock_rx: regNrot:=(others=>'0');
signal rx, credit_o: regNrot;
signal clock_tx, tx, credit_i, testLink_i, testLink_o: regNrot;
signal data_in, data_out : arrayNrot_regflit;
signal currentTime: unsigned(4*TAM_FLIT-1 downto 0) := (others=>'0');
begin
reset <= '1', '0' after CLOCK_PERIOD/2;
clock <= not clock after CLOCK_PERIOD/2;
clock_rx <= not clock_rx after CLOCK_PERIOD/2;
credit_i <= tx;
testLink_i <= (others=>'0');
NOC: Entity work.NOC
port map(
clock => clock,
reset => reset,
clock_rxLocal => clock_rx,
rxLocal => rx,
data_inLocal_flit => data_in,
credit_oLocal => credit_o,
clock_txLocal => clock_tx,
txLocal => tx,
data_outLocal_flit => data_out,
credit_iLocal => credit_i
);
process (reset, clock(0))
begin
if (reset = '1') then
currentTime <= (others=>'0');
elsif (rising_edge(clock(0))) then
currentTime <= currentTime + 1;
end if;
end process;
InputModules: for i in 0 to (NROT-1) generate
IM : Entity work.inputModule
generic map(address => ADDRESS_FROM_INDEX(i))
port map(
done => rx(i),
data => data_in(i),
enable => credit_o(i),
currentTime => currentTime
);
end generate InputModules;
OutputModules: for i in 0 to (NROT-1) generate
OM : Entity work.outputModule
generic map(address => ADDRESS_FROM_INDEX(i))
port map(
clock => clock(i),
tx => tx(i),
data => data_out(i),
currentTime => currentTime
);
end generate OutputModules;
end topNoC;
|
lgpl-3.0
|
NuclearKev/iir-hardware
|
resize.vhd
|
1
|
1581
|
--------------------------------------------------------------------------------
-- Copyright (C) 2017 Kevin Bloom <kdb5pct.edu>
--
-- This program is free software: you can redistribute it and/or modify it under
-- the terms of the Lesser GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option) any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the Lesser GNU General Public License for more
-- details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description:
--
-- This IP was created as a part of the IIR Hardware proect. It will resize a
-- 12 bit input to a 32 bit output.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity resize_IP is
Port ( i_value : in STD_LOGIC_VECTOR (11 downto 0);
o_value : out STD_LOGIC_VECTOR (31 downto 0));
end resize_IP;
architecture Behavioral of resize_IP is
begin
p_resize : process (i_value)
begin
o_value <= std_logic_vector(resize(signed(i_value), 32));
end process;
end Behavioral;
|
lgpl-3.0
|
NuclearKev/iir-hardware
|
fir.vhd
|
1
|
2980
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fir is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
-- ready : in std_logic;
done : out std_logic;
-- coefficient
i_coeff_0 : in std_logic_vector(14 downto 0);
i_coeff_1 : in std_logic_vector(14 downto 0);
i_coeff_2 : in std_logic_vector(14 downto 0);
i_coeff_3 : in std_logic_vector(14 downto 0);
-- data input
i_data : in std_logic_vector(11 downto 0);
-- filtered data
o_data : out std_logic_vector(11 downto 0));
end fir;
architecture Behavioral of fir is
type t_data_pipe is array (0 to 3) of signed(11 downto 0);
type t_coeff is array (0 to 3) of signed(14 downto 0);
type t_mult is array (0 to 3) of signed(26 downto 0);
type t_add_st0 is array (0 to 1) of signed(26+1 downto 0);
signal r_coeff : t_coeff ;
signal p_data : t_data_pipe;
signal r_mult : t_mult;
signal r_add_st0 : t_add_st0;
signal r_add_st1 : signed(26+2 downto 0);
begin
p_input : process (i_rstb,i_clk)
begin
if(i_rstb='1') then
p_data <= (others=>(others=>'0'));
r_coeff <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
p_data <= signed(i_data)&p_data(0 to p_data'length-2);
r_coeff(0) <= signed(i_coeff_0);
r_coeff(1) <= signed(i_coeff_1);
r_coeff(2) <= signed(i_coeff_2);
r_coeff(3) <= signed(i_coeff_3);
end if;
end process p_input;
p_mult : process (i_rstb,i_clk,p_data,r_coeff)
begin
if(i_rstb='1') then
r_mult <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 3 loop
r_mult(k) <= p_data(k) * r_coeff(k);
end loop;
end if;
end process p_mult;
p_add_st0 : process (i_rstb,i_clk,r_mult)
begin
if(i_rstb='1') then
r_add_st0 <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 1 loop
r_add_st0(k) <= resize(r_mult(2*k),28) + resize(r_mult(2*k+1),28);
end loop;
end if;
end process p_add_st0;
p_add_st1 : process (i_rstb,i_clk,r_add_st0)
begin
if(i_rstb='1') then
r_add_st1 <= (others=>'0');
elsif(i_clk='1') then
r_add_st1 <= resize(r_add_st0(0),29) + resize(r_add_st0(1),29);
end if;
end process p_add_st1;
p_output : process (i_rstb,i_clk,r_add_st1)
begin
done <= '0';
if(i_rstb='1') then
o_data <= (others=>'0');
done <= '0';
elsif(i_clk='1') then
done <= '1';
o_data <= std_logic_vector(r_add_st1(28 downto 17));
end if;
end process p_output;
-- p_done : process (i_rstb, i_clk)
-- begin
-- if(i_rstb='0') then
-- done <= '0';
-- elsif(rising_edge(i_clk)) then
-- done <= '1';
-- end if;
-- end process p_done;
end Behavioral;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5/syn/vhdl/nfa_get_initials.vhd
|
3
|
12351
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_initials is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_initials is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_initials_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_initials_buckets_read_reg_59 <= nfa_initials_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_initials_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_initials_buckets_read_reg_59;
ap_return_1 <= nfa_initials_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_address assign process. --
nfa_initials_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_initials_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_initials_buckets_address <= ap_const_lv32_0;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_initials_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_initials_buckets_dataout <= ap_const_lv32_0;
nfa_initials_buckets_req_din <= ap_const_logic_0;
-- nfa_initials_buckets_req_write assign process. --
nfa_initials_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_initials_buckets_req_write <= ap_const_logic_1;
else
nfa_initials_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_initials_buckets_rsp_read assign process. --
nfa_initials_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_initials_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_initials_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_initials_buckets_rsp_read <= ap_const_logic_1;
else
nfa_initials_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_initials_buckets_size <= ap_const_lv32_1;
end behav;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/indices_if_ap_fifo.vhd
|
3
|
2805
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity indices_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of indices_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5_plb/impl/pcores/nfa_accept_samples_generic_hw_top_v1_01_a/simhdl/vhdl/sample_buffer_if_plb_master_if.vhd
|
4
|
36941
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of sample_buffer_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of sample_buffer_if_plb_master_if is
component sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component sample_buffer_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_sample_buffer_if_fifo: component sample_buffer_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_kintex7/impl/vhdl/nfa_accept_samples_generic_hw_add_17ns_17s_17_4.vhd
|
3
|
9502
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 downto 0);
b: in std_logic_vector(16 downto 0);
s: out std_logic_vector(16 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
port (
faa : IN STD_LOGIC_VECTOR (5-1 downto 0);
fab : IN STD_LOGIC_VECTOR (5-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (5-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(16 downto 0);
signal b_reg : std_logic_vector(16 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(4 downto 0);
signal b0_cb : std_logic_vector(4 downto 0);
signal a1_cb : std_logic_vector(9 downto 5);
signal b1_cb : std_logic_vector(9 downto 5);
signal a2_cb : std_logic_vector(14 downto 10);
signal b2_cb : std_logic_vector(14 downto 10);
signal a3_cb : std_logic_vector(16 downto 15);
signal b3_cb : std_logic_vector(16 downto 15);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(16 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(16 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(4 downto 0);
b0_cb <= b_reg(4 downto 0);
a1_cb <= a_reg(9 downto 5);
b1_cb <= b_reg(9 downto 5);
a2_cb <= a_reg(14 downto 10);
b2_cb <= b_reg(14 downto 10);
a3_cb <= a_reg(16 downto 15);
b3_cb <= b_reg(16 downto 15);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(4 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(9 downto 5),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(14 downto 10),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(16 downto 15),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(4 downto 0);
s1_ca_rego1 (0) <= fas(9 downto 5);
s2_ca_rego2 (0) <= fas(14 downto 10);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(4 downto 0) <= s0_ca_rego0(2);
s_tmp(9 downto 5) <= s1_ca_rego1(1);
s_tmp(14 downto 10) <= s2_ca_rego2(0);
s_tmp(16 downto 15) <= fas(16 downto 15);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
generic(N : natural :=5);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
lgpl-3.0
|
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