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jairov4/accel-oil
|
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/nfa_finals_buckets_if_ap_fifo.vhd
|
2
|
2841
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC := '1';
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC := '1';
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_kintex7/sim/vhdl/nfa_get_finals.vhd
|
4
|
14969
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_finals is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal nfa_finals_buckets_read_reg_63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_136 : BOOLEAN;
signal ap_sig_bdd_67 : BOOLEAN;
signal ap_sig_bdd_135 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_read_reg_63 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_reg_ppiten_pp0_it2 , ap_reg_ppiten_pp0_it3 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if (not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_finals_buckets_read_reg_63;
ap_return_1 <= nfa_finals_buckets_datain;
-- ap_sig_bdd_135 assign process. --
ap_sig_bdd_135_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_135 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n)
begin
ap_sig_bdd_136 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))));
end process;
-- ap_sig_bdd_67 assign process. --
ap_sig_bdd_67_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n)
begin
ap_sig_bdd_67 <= ((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_address assign process. --
nfa_finals_buckets_address_assign_proc : process(ap_sig_bdd_136, ap_sig_bdd_67, ap_sig_bdd_135)
begin
if (ap_sig_bdd_135) then
if (ap_sig_bdd_67) then
nfa_finals_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_136) then
nfa_finals_buckets_address <= ap_const_lv32_0;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_dataout <= ap_const_lv32_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_1 = ap_ce) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
end behav;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_spartan3/impl/vhdl/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9.vhd
|
2
|
3326
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
signal tmp_product : std_logic_vector(14 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(14 - 1 downto 0);
signal a_reg : std_logic_vector(8 - 1 downto 0);
signal b_reg : std_logic_vector(6 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(14 - 1 downto 0);
signal buff1 : std_logic_vector(14 - 1 downto 0);
signal buff2 : std_logic_vector(14 - 1 downto 0);
signal buff3 : std_logic_vector(14 - 1 downto 0);
signal buff4 : std_logic_vector(14 - 1 downto 0);
signal buff5 : std_logic_vector(14 - 1 downto 0);
signal buff6 : std_logic_vector(14 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff6;
tmp_product <= std_logic_vector(resize(unsigned(a_reg) * unsigned(b_reg), 14));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg <= a_i;
b_reg <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 is
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_MulnS_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5_plb/impl/vhdl/nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2.vhd
|
1
|
2575
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(24 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 is
signal tmp_product : std_logic_vector(24 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(8 - 1 downto 0);
signal p_tmp : std_logic_vector(24 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
tmp_product <= std_logic_vector(resize(unsigned(a_i) * unsigned(b_i), 24));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
p_tmp <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2 is
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0_U : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_kintex7/sim/vhdl/AESL_autobus_indices_stride.vhd
|
1
|
28947
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_indices_stride is
generic (
constant TV_IN : STRING (1 to 75) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_stride.dat";
constant TV_OUT : STRING (1 to 80) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_indices_stride.dat";
constant DATA_WIDTH : INTEGER := 8;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 10;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_indices_stride;
architecture behav of AESL_autobus_indices_stride is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
|
lgpl-3.0
|
jairov4/accel-oil
|
impl/impl_test_single/simulation/behavioral/system_dlmb_wrapper.vhd
|
2
|
3721
|
-------------------------------------------------------------------------------
-- system_dlmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity system_dlmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end system_dlmb_wrapper;
architecture STRUCTURE of system_dlmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
dlmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_kintex7/impl/vhdl/nfa_accept_samples_generic_hw_add_14ns_14ns_14_4.vhd
|
3
|
9512
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(13 downto 0);
b: in std_logic_vector(13 downto 0);
s: out std_logic_vector(13 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(13 downto 0);
signal b_reg : std_logic_vector(13 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(13 downto 12);
signal b3_cb : std_logic_vector(13 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(13 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(13 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(13 downto 12);
b3_cb <= b_reg(13 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(13 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(13 downto 12) <= fas(13 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5_U : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_5
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5_plb/syn/vhdl/nfa_get_finals_1.vhd
|
1
|
13308
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals_1 is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (63 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
finals_buckets_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
finals_buckets_ce0 : OUT STD_LOGIC;
finals_buckets_we0 : OUT STD_LOGIC;
finals_buckets_d0 : OUT STD_LOGIC_VECTOR (63 downto 0);
tmp_28 : IN STD_LOGIC_VECTOR (4 downto 0) );
end;
architecture behav of nfa_get_finals_1 is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal tmp_28_read_reg_67 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2 : STD_LOGIC_VECTOR (4 downto 0);
signal nfa_finals_buckets_read_reg_72 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_28_cast_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1 <= tmp_28_read_reg_67;
ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2 <= ap_reg_ppstg_tmp_28_read_reg_67_pp0_it1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_read_reg_72 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_28_read_reg_67 <= tmp_28;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it2 , nfa_finals_buckets_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
finals_buckets_address0 <= tmp_28_cast_fu_63_p1(4 - 1 downto 0);
-- finals_buckets_ce0 assign process. --
finals_buckets_ce0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
finals_buckets_ce0 <= ap_const_logic_1;
else
finals_buckets_ce0 <= ap_const_logic_0;
end if;
end process;
finals_buckets_d0 <= nfa_finals_buckets_read_reg_72;
-- finals_buckets_we0 assign process. --
finals_buckets_we0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if ((((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
finals_buckets_we0 <= ap_const_logic_1;
else
finals_buckets_we0 <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_address <= ap_const_lv32_0;
nfa_finals_buckets_dataout <= ap_const_lv64_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it2, nfa_finals_buckets_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
tmp_28_cast_fu_63_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_tmp_28_read_reg_67_pp0_it2),64));
end behav;
|
lgpl-3.0
|
jairov4/accel-oil
|
impl/impl_test_pcie/hdl/system_lmb_bram_wrapper.vhd
|
1
|
2902
|
-------------------------------------------------------------------------------
-- system_lmb_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_elaborate_v1_00_a;
use lmb_bram_elaborate_v1_00_a.all;
entity system_lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of system_lmb_bram_wrapper : entity is "lmb_bram_elaborate_v1_00_a";
attribute keep_hierarchy of system_lmb_bram_wrapper : entity is "yes";
end system_lmb_bram_wrapper;
architecture STRUCTURE of system_lmb_bram_wrapper is
component lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
lmb_bram : lmb_bram_elaborate
generic map (
C_MEMSIZE => 16#1000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "virtex5"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
|
lgpl-3.0
|
jairov4/accel-oil
|
impl/impl_test_single/simulation/behavioral/system_proc_sys_reset_0_wrapper.vhd
|
2
|
4081
|
-------------------------------------------------------------------------------
-- system_proc_sys_reset_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library proc_sys_reset_v3_00_a;
use proc_sys_reset_v3_00_a.all;
entity system_proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
end system_proc_sys_reset_0_wrapper;
architecture STRUCTURE of system_proc_sys_reset_0_wrapper is
component proc_sys_reset is
generic (
C_EXT_RST_WIDTH : integer;
C_AUX_RST_WIDTH : integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic;
C_NUM_BUS_RST : integer;
C_NUM_PERP_RST : integer;
C_NUM_INTERCONNECT_ARESETN : integer;
C_NUM_PERP_ARESETN : integer
);
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to C_NUM_BUS_RST-1);
Peripheral_Reset : out std_logic_vector(0 to C_NUM_PERP_RST-1);
Interconnect_aresetn : out std_logic_vector(0 to C_NUM_INTERCONNECT_ARESETN-1);
Peripheral_aresetn : out std_logic_vector(0 to C_NUM_PERP_ARESETN-1)
);
end component;
begin
proc_sys_reset_0 : proc_sys_reset
generic map (
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '1',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
port map (
Slowest_sync_clk => Slowest_sync_clk,
Ext_Reset_In => Ext_Reset_In,
Aux_Reset_In => Aux_Reset_In,
MB_Debug_Sys_Rst => MB_Debug_Sys_Rst,
Core_Reset_Req_0 => Core_Reset_Req_0,
Chip_Reset_Req_0 => Chip_Reset_Req_0,
System_Reset_Req_0 => System_Reset_Req_0,
Core_Reset_Req_1 => Core_Reset_Req_1,
Chip_Reset_Req_1 => Chip_Reset_Req_1,
System_Reset_Req_1 => System_Reset_Req_1,
Dcm_locked => Dcm_locked,
RstcPPCresetcore_0 => RstcPPCresetcore_0,
RstcPPCresetchip_0 => RstcPPCresetchip_0,
RstcPPCresetsys_0 => RstcPPCresetsys_0,
RstcPPCresetcore_1 => RstcPPCresetcore_1,
RstcPPCresetchip_1 => RstcPPCresetchip_1,
RstcPPCresetsys_1 => RstcPPCresetsys_1,
MB_Reset => MB_Reset,
Bus_Struct_Reset => Bus_Struct_Reset,
Peripheral_Reset => Peripheral_Reset,
Interconnect_aresetn => Interconnect_aresetn,
Peripheral_aresetn => Peripheral_aresetn
);
end architecture STRUCTURE;
|
lgpl-3.0
|
jairov4/accel-oil
|
impl/impl_test_single/hdl/system_proc_sys_reset_0_wrapper.vhd
|
2
|
4214
|
-------------------------------------------------------------------------------
-- system_proc_sys_reset_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library proc_sys_reset_v3_00_a;
use proc_sys_reset_v3_00_a.all;
entity system_proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_proc_sys_reset_0_wrapper : entity is "proc_sys_reset_v3_00_a";
end system_proc_sys_reset_0_wrapper;
architecture STRUCTURE of system_proc_sys_reset_0_wrapper is
component proc_sys_reset is
generic (
C_EXT_RST_WIDTH : integer;
C_AUX_RST_WIDTH : integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic;
C_NUM_BUS_RST : integer;
C_NUM_PERP_RST : integer;
C_NUM_INTERCONNECT_ARESETN : integer;
C_NUM_PERP_ARESETN : integer
);
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to C_NUM_BUS_RST-1);
Peripheral_Reset : out std_logic_vector(0 to C_NUM_PERP_RST-1);
Interconnect_aresetn : out std_logic_vector(0 to C_NUM_INTERCONNECT_ARESETN-1);
Peripheral_aresetn : out std_logic_vector(0 to C_NUM_PERP_ARESETN-1)
);
end component;
begin
proc_sys_reset_0 : proc_sys_reset
generic map (
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '1',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
port map (
Slowest_sync_clk => Slowest_sync_clk,
Ext_Reset_In => Ext_Reset_In,
Aux_Reset_In => Aux_Reset_In,
MB_Debug_Sys_Rst => MB_Debug_Sys_Rst,
Core_Reset_Req_0 => Core_Reset_Req_0,
Chip_Reset_Req_0 => Chip_Reset_Req_0,
System_Reset_Req_0 => System_Reset_Req_0,
Core_Reset_Req_1 => Core_Reset_Req_1,
Chip_Reset_Req_1 => Chip_Reset_Req_1,
System_Reset_Req_1 => System_Reset_Req_1,
Dcm_locked => Dcm_locked,
RstcPPCresetcore_0 => RstcPPCresetcore_0,
RstcPPCresetchip_0 => RstcPPCresetchip_0,
RstcPPCresetsys_0 => RstcPPCresetsys_0,
RstcPPCresetcore_1 => RstcPPCresetcore_1,
RstcPPCresetchip_1 => RstcPPCresetchip_1,
RstcPPCresetsys_1 => RstcPPCresetsys_1,
MB_Reset => MB_Reset,
Bus_Struct_Reset => Bus_Struct_Reset,
Peripheral_Reset => Peripheral_Reset,
Interconnect_aresetn => Interconnect_aresetn,
Peripheral_aresetn => Peripheral_aresetn
);
end architecture STRUCTURE;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5/syn/vhdl/nfa_get_finals.vhd
|
3
|
12263
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_finals is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_finals_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_finals_buckets_read_reg_59 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_finals_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_finals_buckets_read_reg_59;
ap_return_1 <= nfa_finals_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_address assign process. --
nfa_finals_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_finals_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_finals_buckets_address <= ap_const_lv32_0;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_dataout <= ap_const_lv32_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
end behav;
|
lgpl-3.0
|
jairov4/accel-oil
|
impl/impl_test_pcie/hdl/system_mb_plb_wrapper.vhd
|
1
|
14676
|
-------------------------------------------------------------------------------
-- system_mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 11);
MPLB_Rst : out std_logic_vector(0 to 5);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 191);
M_UABus : in std_logic_vector(0 to 191);
M_BE : in std_logic_vector(0 to 47);
M_RNW : in std_logic_vector(0 to 5);
M_abort : in std_logic_vector(0 to 5);
M_busLock : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 95);
M_lockErr : in std_logic_vector(0 to 5);
M_MSize : in std_logic_vector(0 to 11);
M_priority : in std_logic_vector(0 to 11);
M_rdBurst : in std_logic_vector(0 to 5);
M_request : in std_logic_vector(0 to 5);
M_size : in std_logic_vector(0 to 23);
M_type : in std_logic_vector(0 to 17);
M_wrBurst : in std_logic_vector(0 to 5);
M_wrDBus : in std_logic_vector(0 to 383);
Sl_addrAck : in std_logic_vector(0 to 11);
Sl_MRdErr : in std_logic_vector(0 to 71);
Sl_MWrErr : in std_logic_vector(0 to 71);
Sl_MBusy : in std_logic_vector(0 to 71);
Sl_rdBTerm : in std_logic_vector(0 to 11);
Sl_rdComp : in std_logic_vector(0 to 11);
Sl_rdDAck : in std_logic_vector(0 to 11);
Sl_rdDBus : in std_logic_vector(0 to 767);
Sl_rdWdAddr : in std_logic_vector(0 to 47);
Sl_rearbitrate : in std_logic_vector(0 to 11);
Sl_SSize : in std_logic_vector(0 to 23);
Sl_wait : in std_logic_vector(0 to 11);
Sl_wrBTerm : in std_logic_vector(0 to 11);
Sl_wrComp : in std_logic_vector(0 to 11);
Sl_wrDAck : in std_logic_vector(0 to 11);
Sl_MIRQ : in std_logic_vector(0 to 71);
PLB_MIRQ : out std_logic_vector(0 to 5);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 5);
PLB_MTimeout : out std_logic_vector(0 to 5);
PLB_MBusy : out std_logic_vector(0 to 5);
PLB_MRdErr : out std_logic_vector(0 to 5);
PLB_MWrErr : out std_logic_vector(0 to 5);
PLB_MRdBTerm : out std_logic_vector(0 to 5);
PLB_MRdDAck : out std_logic_vector(0 to 5);
PLB_MRdDBus : out std_logic_vector(0 to 383);
PLB_MRdWdAddr : out std_logic_vector(0 to 23);
PLB_MRearbitrate : out std_logic_vector(0 to 5);
PLB_MWrBTerm : out std_logic_vector(0 to 5);
PLB_MWrDAck : out std_logic_vector(0 to 5);
PLB_MSSize : out std_logic_vector(0 to 11);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 11);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 11);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 5);
PLB_SMWrErr : out std_logic_vector(0 to 5);
PLB_SMBusy : out std_logic_vector(0 to 5);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_mb_plb_wrapper : entity is "plb_v46_v1_05_a";
end system_mb_plb_wrapper;
architecture STRUCTURE of system_mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 6,
C_PLBV46_NUM_SLAVES => 12,
C_PLBV46_MID_WIDTH => 3,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_forward_buckets_if_ap_fifo_af.vhd
|
2
|
6299
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo_af_ram is
type mem_array is array (mem_size-1 downto 0) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array;
attribute ram_style : string;
attribute ram_style of mem : signal is mem_style;
begin
p_memory_read: process (clk)
begin
if (clk = '1' and clk'event) then
if (we = '1') then
mem(CONV_INTEGER(w_addr)) <= din;
end if;
dout <= mem(CONV_INTEGER(r_addr));
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if_ap_fifo_af is
generic (
MEM_STYLE : string := "block";
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo_af is
component nfa_forward_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end component;
signal mInPtr, mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal mInPtr_next, mOutPtr_next : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_raddr, ram_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_din, ram_dout : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff_valid : STD_LOGIC;
signal ram_we : STD_LOGIC;
signal wordUsed : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal internal_empty_n, internal_full_n: STD_LOGIC;
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
ram_din <= if_din;
process (wordUsed, conflict_buff_valid, conflict_buff, ram_dout)
begin
if ( wordUsed = 1 and conflict_buff_valid = '1' ) then
if_dout <= conflict_buff;
else
if_dout <= ram_dout;
end if;
end process;
process (mOutPtr)
begin
if ( mOutPtr < DEPTH -1 ) then
mOutPtr_next <= mOutPtr + 1;
else
mOutPtr_next <= (others => '0');
end if;
end process;
process (mInPtr)
begin
if ( mInPtr < DEPTH -1 ) then
mInPtr_next <= mInPtr + 1;
else
mInPtr_next <= (others => '0');
end if;
end process;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
wordUsed <= (others => '0');
internal_empty_n <= '0';
internal_full_n <= '1';
conflict_buff <= (others => '0');
conflict_buff_valid <= '0';
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr_next;
end if;
if (if_write = '1') then
mInPtr <= mInPtr_next;
end if;
if (if_read = '1' and internal_empty_n = '1' and if_write = '0') then
wordUsed <= wordUsed -1;
if (wordUsed = 1) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif (if_read = '0' or internal_empty_n = '0') and
(if_write = '1') then
wordUsed <= wordUsed +1;
internal_empty_n <= '1';
if (wordUsed + ALMOST_FULL_MARGIN = DEPTH -1) then
internal_full_n <= '0';
end if;
end if;
conflict_buff <= if_din;
conflict_buff_valid <= if_write and internal_full_n;
end if;
end if;
end process;
ram_waddr <= mInPtr;
ram_raddr <= mOutPtr_next when if_read = '1' and internal_empty_n = '1' else mOutPtr;
-- if a read occur on the following clock edge, prepare next read data in advance
ram_we <= if_write; -- caller should check almost_full signal
U_nfa_forward_buckets_if_ap_fifo_af_ram : nfa_forward_buckets_if_ap_fifo_af_ram
generic map (
mem_style => MEM_STYLE,
dwidth => DATA_WIDTH,
awidth => ADDR_WIDTH,
mem_size => DEPTH)
port map (
clk => clk,
din => ram_din,
w_addr => ram_waddr,
we => ram_we,
r_addr => ram_raddr,
dout => ram_dout);
end rtl;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/simhdl/vhdl/nfa_initials_buckets_if_ap_fifo_af.vhd
|
2
|
6306
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nfa_initials_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end entity;
architecture rtl of nfa_initials_buckets_if_ap_fifo_af_ram is
type mem_array is array (mem_size-1 downto 0) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array;
attribute ram_style : string;
attribute ram_style of mem : signal is mem_style;
begin
p_memory_read: process (clk)
begin
if (clk = '1' and clk'event) then
if (we = '1') then
mem(CONV_INTEGER(w_addr)) <= din;
end if;
dout <= mem(CONV_INTEGER(r_addr));
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_initials_buckets_if_ap_fifo_af is
generic (
MEM_STYLE : string := "block";
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_initials_buckets_if_ap_fifo_af is
component nfa_initials_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end component;
signal mInPtr, mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal mInPtr_next, mOutPtr_next : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_raddr, ram_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_din, ram_dout : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff_valid : STD_LOGIC;
signal ram_we : STD_LOGIC;
signal wordUsed : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal internal_empty_n, internal_full_n: STD_LOGIC;
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
ram_din <= if_din;
process (wordUsed, conflict_buff_valid, conflict_buff, ram_dout)
begin
if ( wordUsed = 1 and conflict_buff_valid = '1' ) then
if_dout <= conflict_buff;
else
if_dout <= ram_dout;
end if;
end process;
process (mOutPtr)
begin
if ( mOutPtr < DEPTH -1 ) then
mOutPtr_next <= mOutPtr + 1;
else
mOutPtr_next <= (others => '0');
end if;
end process;
process (mInPtr)
begin
if ( mInPtr < DEPTH -1 ) then
mInPtr_next <= mInPtr + 1;
else
mInPtr_next <= (others => '0');
end if;
end process;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
wordUsed <= (others => '0');
internal_empty_n <= '0';
internal_full_n <= '1';
conflict_buff <= (others => '0');
conflict_buff_valid <= '0';
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr_next;
end if;
if (if_write = '1') then
mInPtr <= mInPtr_next;
end if;
if (if_read = '1' and internal_empty_n = '1' and if_write = '0') then
wordUsed <= wordUsed -1;
if (wordUsed = 1) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif (if_read = '0' or internal_empty_n = '0') and
(if_write = '1') then
wordUsed <= wordUsed +1;
internal_empty_n <= '1';
if (wordUsed + ALMOST_FULL_MARGIN = DEPTH -1) then
internal_full_n <= '0';
end if;
end if;
conflict_buff <= if_din;
conflict_buff_valid <= if_write and internal_full_n;
end if;
end if;
end process;
ram_waddr <= mInPtr;
ram_raddr <= mOutPtr_next when if_read = '1' and internal_empty_n = '1' else mOutPtr;
-- if a read occur on the following clock edge, prepare next read data in advance
ram_we <= if_write; -- caller should check almost_full signal
U_nfa_initials_buckets_if_ap_fifo_af_ram : nfa_initials_buckets_if_ap_fifo_af_ram
generic map (
mem_style => MEM_STYLE,
dwidth => DATA_WIDTH,
awidth => ADDR_WIDTH,
mem_size => DEPTH)
port map (
clk => clk,
din => ram_din,
w_addr => ram_waddr,
we => ram_we,
r_addr => ram_raddr,
dout => ram_dout);
end rtl;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_virtex5/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/vhdl/nfa_initials_buckets_if_ap_fifo.vhd
|
3
|
2831
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_initials_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
DEPTH : integer := 1);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_initials_buckets_if_ap_fifo is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype := (others => (others => '0'));
signal mInPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal mFlag_nEF_hint : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
begin
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
internal_empty_n <= '0' when mInPtr = mOutPtr and mFlag_nEF_hint = '0' else '1';
internal_full_n <= '0' when mInptr = mOutPtr and mFlag_nEF_hint = '1' else '1';
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
mFlag_nEF_hint <= '0'; -- empty hint
elsif clk'event and clk = '1' then
if if_read_ce = '1' and if_read = '1' and internal_empty_n = '1' then
if (mOutPtr = DEPTH -1) then
mOutPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mOutPtr <= mOutPtr + 1;
end if;
end if;
if if_write_ce = '1' and if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
if (mInPtr = DEPTH -1) then
mInPtr <= (others => '0');
mFlag_nEF_hint <= not mFlag_nEF_hint;
else
mInPtr <= mInPtr + 1;
end if;
end if;
end if;
end process;
end architecture;
|
lgpl-3.0
|
blytkerchan/BrainF
|
BrainF_tb.vhdl
|
1
|
6889
|
-- BrainF* interpreter - testbench
-- Version: 20141001
-- Author: Ronald Landheer-Cieslak
-- Copyright (c) 2014 Vlinder Software
-- License: LGPL-3.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.txt_util.all;
entity BrainF_tb is
end entity;
architecture behavior of BrainF_tb is
constant WARMUP_COUNTDOWN : integer := 4;
constant INITIAL_COUNTDOWN : integer := 10;
--constant PROGRAM : string := "++++++++";
--constant PROGRAM : string := "[.]";
--constant PROGRAM : string := "-+[-+][[-+]]";
--constant PROGRAM : string := "++[-][[-+]]";
--constant PROGRAM : string := ">+++++++++[<++++++++>-]<.>+++++++[<++++>-]<+.+++++++..+++.0>++++++++[<++++>-] <.>+++++++++++[<++++++++>-]<-.--------.+++.------.--------.0>++++++++[<++++>- ]<+.0++++++++++.";
constant PROGRAM : string := ">+++++++++[<++++++++>-]<.>+++++++[<++++>-]<+.+++++++..+++.[-]>++++++++[<++++>-] <.>+++++++++++[<++++++++>-]<-.--------.+++.------.--------.[-]>++++++++[<++++>- ]<+.[-]++++++++++.";
constant PROGRAM_TIMEOUT : Time := 138 ns;
component BrainF is
generic(
MAX_INSTRUCTION_COUNT : positive := 65536
; MEMORY_SIZE : positive := 65536
);
port(
resetN : in std_logic
; clock : in std_logic
; load_instructions : in std_logic
; instruction_octet : in std_logic_vector(7 downto 0)
; ack_instruction : out std_logic
; program_full : out std_logic
; read_memory : in std_logic
; memory_byte : out std_logic_vector(7 downto 0)
; memory_byte_ready : out std_logic
; memory_byte_read_ack : in std_logic
; done : out std_logic
);
end component;
type State is (warmup, initial, start_loading_program, loading_program, running_program, success);
function to_std_logic_vector(c : character) return std_logic_vector is
variable cc : integer;
begin
cc := character'pos(c);
return std_logic_vector(to_unsigned(cc, 8));
end to_std_logic_vector;
signal clock : std_logic := '0';
signal load_instructions : std_logic := '0';
signal instruction_octet : std_logic_vector(7 downto 0) := (others => '0');
signal ack_instruction : std_logic := '0';
signal program_full : std_logic := '0';
signal read_memory : std_logic := '0';
signal memory_byte : std_logic_vector(7 downto 0) := (others => '0');
signal memory_byte_ready : std_logic := '0';
signal memory_byte_read_ack : std_logic := '0';
signal done : std_logic := '0';
signal tb_state : State := warmup;
signal should_be_done : std_logic := '0';
signal end_of_simulation : std_logic := '0';
begin
interpreter : BrainF
port map(
resetN => '1'
, clock => clock
, load_instructions => load_instructions
, instruction_octet => instruction_octet
, ack_instruction => ack_instruction
, program_full => program_full
, read_memory => read_memory
, memory_byte => memory_byte
, memory_byte_ready => memory_byte_ready
, memory_byte_read_ack => memory_byte_read_ack
, done => done
);
-- generate the clock
clock <= not clock after 1 ps;
-- generate the time-out signal
should_be_done <= '1' after PROGRAM_TIMEOUT;
p_tb : process(clock)
variable countdown : integer := WARMUP_COUNTDOWN;
variable program_load_counter : integer := 0;
begin
if rising_edge(clock) then
case tb_state is
when warmup =>
assert done = '0' report "Cannot be done while warming up (pipe filling with halt instructions)" severity failure;
assert program_full = '0' report "Program cannot be initially full" severity failure;
assert ack_instruction = '0' report "Cannot acknowledge an instruction I haven't given yet" severity failure;
assert memory_byte_ready = '0' report "Cannot have memory ready when I haven't asked for anything yet" severity failure;
if countdown = 1 then
tb_state <= initial;
countdown := INITIAL_COUNTDOWN;
else
countdown := countdown - 1;
end if;
when initial =>
assert done = '1' report "Once warmed up, it should know it has no program and say it's done" severity failure;
assert program_full = '0' report "Program cannot be initially full" severity failure;
assert ack_instruction = '0' report "Cannot acknowledge an instruction I haven't given yet" severity failure;
assert memory_byte_ready = '0' report "Cannot have memory ready when I haven't asked for anything yet" severity failure;
if countdown = 1 then
tb_state <= start_loading_program;
else
countdown := countdown - 1;
end if;
when start_loading_program =>
assert program_full = '0' report "Program cannot be initially full" severity failure;
assert ack_instruction = '0' report "Cannot acknowledge an instruction I haven't given yet" severity failure;
assert memory_byte_ready = '0' report "Cannot have memory ready when I haven't asked for anything yet" severity failure;
instruction_octet <= to_std_logic_vector(program(1));
load_instructions <= '1';
tb_state <= loading_program;
program_load_counter := 2;
when loading_program =>
if program_load_counter <= program'length then
if ack_instruction = '1' then
instruction_octet <= to_std_logic_vector(program(program_load_counter));
program_load_counter := program_load_counter + 1;
end if;
else
load_instructions <= '0';
tb_state <= running_program;
end if;
when running_program =>
if should_be_done = '1' then
assert done = '1' report "Timeout!" severity failure;
end if;
if done = '1' then
tb_state <= success;
end if;
when success =>
end_of_simulation <= '1';
when others => null;
end case;
end if;
end process;
end behavior;
|
lgpl-3.0
|
blytkerchan/BrainF
|
SPISlave.vhdl
|
1
|
9365
|
-- Generic SPI Slave
-- sets the output data bit on the rising edge of the clock, reads the
-- data input bit on the falling edge.
-- To use, read the data_O output on the rising edge of
-- (data_ready_O and new_data_byte_O), set data_I to something you want to send and
-- wait for a rising edge on data_ack_O before putting another one in.
-- Data sent by the slave will be aligned to 8-bit boundaries, so if you don't
-- have any data ready to send (data_ready_I is set) when a byte starts to be sent,
-- the slave will pull its output low for the duration of the byte. You have between
-- the rising edge of the SPI clock for the last bit of a byte and the next rising
-- edge to provide new data.
-- the spi_clock_I, spi_slave_select_NI and spi_mosi_I signals should be debounced
-- before being fed to this component -- you know better how much noise to expect
-- than I do.
-- Version: 20141019
-- Author: Ronald Landheer-Cieslak
-- Copyright (c) 2014 Vlinder Software
-- License: LGPL-3.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPISlave is
port(
clock : in std_logic
; resetN : in std_logic
-- bus to the outside
; spi_clock_I : in std_logic
; spi_slave_select_NI : in std_logic
; spi_mosi_I : in std_logic
; spi_miso_O : out std_logic
-- internal bus:
-- signal to this component that data_I contains something
; data_ready_I : in std_logic
-- data to send
; data_I : in std_logic_vector(7 downto 0)
-- acknowledge we've copied the byte, so you can provide another one
; data_ack_O : out std_logic
-- indicate data_O contains valid data from the master
; data_ready_O : out std_logic
-- signal that we've changed the byte (can be used to push into a FIFO or set an SR flip-flop or something)
; new_data_byte_O : out std_logic
-- byte from the master
; data_O : out std_logic_vector(7 downto 0)
);
end entity;
architecture behavior of SPISlave is
type BitCounter is range 0 to 7;
-- driven by a SR flip-flop
signal internal_data_ready_O : std_logic := '0';
signal internal_data_ready_NO : std_logic := '1';
-- driven by p_decoder
signal set_internal_data_ready_O : std_logic := '0';
signal clear_internal_data_ready_O : std_logic := '1';
signal prev_spi_clock_I : std_logic := 'X';
signal prev_spi_slave_select_NI : std_logic := 'X';
signal internal_spi_miso_O : std_logic := 'Z';
signal input_bit_count : BitCounter := 0;
signal output_bit_count : BitCounter := 7;
signal current_input_byte : std_logic_vector(7 downto 0) := (others => 'X');
signal outputting_data : std_logic := '0';
signal current_output_byte : std_logic_vector(7 downto 0) := (others => '0');
signal current_output_byte_valid : std_logic := '0';
signal prev_data_ready_I : std_logic := 'X';
signal data_ack_on_first_seen : std_logic := '0';
signal data_ack_on_byte_change : std_logic := '0';
signal read_select : std_logic := '0';
begin
-- flip-flop for the data-ready output signal
internal_data_ready_O <= not internal_data_ready_NO or set_internal_data_ready_O;
internal_data_ready_NO <= not internal_data_ready_O or clear_internal_data_ready_O;
data_ready_O <= internal_data_ready_O;
-- let the client code know we produced a new byte
new_data_byte_O <= set_internal_data_ready_O;
-- wire-through for the MISO output
spi_miso_O <= internal_spi_miso_O;
-- acknowledge consuming a byte
data_ack_O <= data_ack_on_byte_change or data_ack_on_first_seen;
p_decoder : process(clock, resetN)
begin
if resetN = '0' then
prev_spi_clock_I <= 'X';
prev_spi_slave_select_NI <= 'X';
clear_internal_data_ready_O <= '1';
data_O <= (others => 'X');
internal_spi_miso_O <= 'Z';
set_internal_data_ready_O <= '0';
current_input_byte <= (others => 'X');
input_bit_count <= 0;
output_bit_count <= 7;
outputting_data <= '0';
current_output_byte <= (others => '0');
current_output_byte_valid <= '0';
prev_data_ready_I <= 'X';
data_ack_on_first_seen <= '0';
data_ack_on_byte_change <= '0';
read_select <= '0';
else
if rising_edge(clock) then
-- detect a falling edge of the spi_slave_select_NI input
if prev_spi_slave_select_NI = '1' and spi_slave_select_NI = '0' then
clear_internal_data_ready_O <= '1';
-- counters should already be OK at this point: either because we're coming out of a complete reset or because we have previously been deselected
-- on a rising edge (when we're deselected) reset the counters so we can't get desynchronized if we get deselected in the middle of a byte
elsif prev_spi_slave_select_NI = '0' and spi_slave_select_NI = '1' then
output_bit_count <= 7;
input_bit_count <= 0;
read_select <= '0';
else
clear_internal_data_ready_O <= '0';
end if;
prev_spi_slave_select_NI <= spi_slave_select_NI;
-- detect new output data
if prev_data_ready_I = '0'and data_ready_I = '1' then
current_output_byte <= data_I;
current_output_byte_valid <= '1';
data_ack_on_first_seen <= '1';
else
data_ack_on_first_seen <= '0';
end if;
prev_data_ready_I <= data_ready_I;
-- detect edges of the input clock
if spi_slave_select_NI = '0' then -- we are selected
if prev_spi_clock_I = '0' and spi_clock_I = '1' then -- rising edge of the clock - write a bit if we have any
-- start outputting data if we are at the start of a byte boundary, or if we were already outputting a byte
if current_output_byte_valid = '1' and (outputting_data = '1' or output_bit_count = 7) then
internal_spi_miso_O <= current_output_byte(7);
outputting_data <= '1';
else
internal_spi_miso_O <= '0';
outputting_data <= '0';
end if;
-- if we just decided to output the last bit of the byte, load the next byte if we have one, or invalidate the current byte if we don't.
-- if we do load a new byte, we should acknowledge it.
-- if we're not at the last bit, just shift a bit out of the register
if (output_bit_count = 0) then
-- we should, of course, only take the byte if we've output the current one. Otherwise, we should leave it there until we do.
if outputting_data = '1' then
current_output_byte <= data_I;
current_output_byte_valid <= data_ready_I;
data_ack_on_byte_change <= '1';
else
data_ack_on_byte_change <= '0';
end if;
output_bit_count <= 7;
else
-- shift out a bit
data_ack_on_byte_change <= '0';
output_bit_count <= output_bit_count - 1;
current_output_byte <= current_output_byte(6 downto 0) & '0';
end if;
set_internal_data_ready_O <= '0';
read_select <= '1';
elsif read_select = '1' and prev_spi_clock_I = '1' and spi_clock_I = '0' then -- falling edge of the clock - read a bit
if input_bit_count = 7 then
set_internal_data_ready_O <= '1';
data_O <= current_input_byte(6 downto 0) & spi_mosi_I;
input_bit_count <= 0;
else
set_internal_data_ready_O <= '0';
input_bit_count <= input_bit_count + 1;
end if;
current_input_byte <= current_input_byte(6 downto 0) & spi_mosi_I;
else
set_internal_data_ready_O <= '0';
end if;
else
internal_spi_miso_O <= 'Z';
set_internal_data_ready_O <= '0';
end if;
prev_spi_clock_I <= spi_clock_I;
end if;
end if;
end process;
end architecture;
|
lgpl-3.0
|
FinnK/lems2hdl
|
work/N3_pointCellCondBased/ISIM_output/reverseRaten1.vhdl
|
1
|
10652
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity reverseRaten1 is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_per_time_rate : in sfixed (18 downto -2);
param_voltage_midpoint : in sfixed (2 downto -22);
param_voltage_scale : in sfixed (2 downto -22);
param_voltage_inv_scale_inv : in sfixed (22 downto -2);
exposure_per_time_r : out sfixed (18 downto -2);
derivedvariable_per_time_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end reverseRaten1;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of reverseRaten1 is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal pre_exp_r_exponential_result1 : sfixed(18 downto -13);
signal pre_exp_r_exponential_result1_next : sfixed(18 downto -13);
signal exp_r_exponential_result1 : sfixed(18 downto -13);
Component ParamExp is
generic(
BIT_TOP : integer := 20;
BIT_BOTTOM : integer := -20);
port(
clk : In Std_logic;
init_model : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end Component;
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_per_time_r : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
signal DerivedVariable_per_time_r_next : sfixed (18 downto -2) := to_sfixed(0.0 ,18,-2);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
pre_exp_r_exponential_result1_next <= resize( ( ( requirement_voltage_v - param_voltage_midpoint ) * param_voltage_inv_scale_inv ) ,18,-13);
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then
pre_exp_r_exponential_result1 <= to_sfixed(0,18,-13);
else
if subprocess_all_ready_shot = '1' then
pre_exp_r_exponential_result1 <= pre_exp_r_exponential_result1_next;
end if;
end if;
end if;
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
ParamExp_r_exponential_result1 : ParamExp
generic map(
BIT_TOP => 18,
BIT_BOTTOM => -13
)
port map ( clk => clk,
init_model => init_model,
Start => step_once_go,
Done => subprocess_der_int_ready,
X => pre_exp_r_exponential_result1 ,
Output => exp_r_exponential_result1
);
derived_variable_process_comb :process ( sysparam_time_timestep, param_voltage_midpoint, param_voltage_scale, requirement_voltage_v , param_per_time_rate,param_voltage_inv_scale_inv,exp_r_exponential_result1 )
begin
derivedvariable_per_time_r_next <= resize(( param_per_time_rate * exp_r_exponential_result1 ),18,-2);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_per_time_r <= derivedvariable_per_time_r_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep)
begin
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_per_time_r <= derivedvariable_per_time_r_in;derivedvariable_per_time_r_out <= derivedvariable_per_time_r;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
|
lgpl-3.0
|
FinnK/lems2hdl
|
work/N1_iafRefCell/ISIM_output/neuron_model.vhdl
|
1
|
22290
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity neuron_model is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
current_regime_in_stdlv : in STD_LOGIC_VECTOR(1 downto 0);
current_regime_out_stdlv : out STD_LOGIC_VECTOR(1 downto 0);
eventport_out_spike : out STD_LOGIC;
param_time_refract : in sfixed (6 downto -18);
param_conductance_leakConductance : in sfixed (-22 downto -53);
param_voltage_leakReversal : in sfixed (2 downto -22);
param_voltage_thresh : in sfixed (2 downto -22);
param_voltage_reset : in sfixed (2 downto -22);
param_capacitance_C : in sfixed (-33 downto -47);
param_capacitance_inv_C_inv : in sfixed (47 downto 33);
exposure_voltage_v : out sfixed (2 downto -22);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_time_lastSpikeTime_out : out sfixed (6 downto -18);
statevariable_time_lastSpikeTime_in : in sfixed (6 downto -18);
param_time_SynapseModel_tauDecay : in sfixed (6 downto -18);
param_conductance_SynapseModel_gbase : in sfixed (-22 downto -53);
param_voltage_SynapseModel_erev : in sfixed (2 downto -22);
param_time_inv_SynapseModel_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_SynapseModel_i : out sfixed (-28 downto -53);
exposure_conductance_SynapseModel_g : out sfixed (-22 downto -53);
statevariable_conductance_SynapseModel_g_out : out sfixed (-22 downto -53);
statevariable_conductance_SynapseModel_g_in : in sfixed (-22 downto -53);
derivedvariable_current_SynapseModel_i_out : out sfixed (-28 downto -53);
derivedvariable_current_SynapseModel_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end neuron_model;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of neuron_model is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal SynapseModel_step_once_complete_fired : STD_LOGIC := '1';
signal step_once_complete_fired : STD_LOGIC := '1';
signal Component_done : STD_LOGIC := '0';
constant cNSpikeSources : integer := 512; -- The number of spike sources.
constant cNOutputs : integer := 512; -- The number of Synapses in the neuron model.
constant cNSelectBits : integer := 9; -- Log2(NOutputs), rounded up.
signal SpikeOut : Std_logic_vector((cNOutputs-1) downto 0);
signal statevariable_voltage_integrating_v_temp_1 : sfixed (2 downto -22);
signal statevariable_voltage_integrating_v_temp_1_next : sfixed (2 downto -22);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_iSyn : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iSyn_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_voltage_v_next : sfixed (2 downto -22);
signal statevariable_time_lastSpikeTime_next : sfixed (6 downto -18);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_out_spike_internal : std_logic := '0';
---------------------------------------------------------------------
type regime_type is (refractory,integrating);
signal current_regime_in_int: regime_type;
signal next_regime: regime_type;
function CONV_STDLV_TO_REGIME (DATA :std_logic_vector) return regime_type is
begin
return regime_type'val(to_integer(unsigned(DATA)));
end CONV_STDLV_TO_REGIME;
function CONV_REGIME_TO_STDLV (regime :regime_type) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(regime_type'pos(regime),2));
end CONV_REGIME_TO_STDLV;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component SynapseModel
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal SynapseModel_Component_done : STD_LOGIC ; signal Exposure_current_SynapseModel_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_SynapseModel_g_internal : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
SynapseModel_uut : SynapseModel
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => SynapseModel_Component_done,
eventport_in_in => EventPort_in_spike_aggregate(0),
param_time_tauDecay => param_time_SynapseModel_tauDecay,
param_conductance_gbase => param_conductance_SynapseModel_gbase,
param_voltage_erev => param_voltage_SynapseModel_erev,
param_time_inv_tauDecay_inv => param_time_inv_SynapseModel_tauDecay_inv,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_SynapseModel_i_internal,
Exposure_conductance_g => Exposure_conductance_SynapseModel_g_internal,
statevariable_conductance_g_out => statevariable_conductance_SynapseModel_g_out,
statevariable_conductance_g_in => statevariable_conductance_SynapseModel_g_in,
derivedvariable_current_i_out => derivedvariable_current_SynapseModel_i_out,
derivedvariable_current_i_in => derivedvariable_current_SynapseModel_i_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_SynapseModel_i <= Exposure_current_SynapseModel_i_internal;
Exposure_conductance_SynapseModel_g <= Exposure_conductance_SynapseModel_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_current_SynapseModel_i_internal, param_conductance_leakConductance, param_voltage_leakReversal, statevariable_voltage_v_in , derivedvariable_current_iSyn_next )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_current_SynapseModel_i_internal, param_conductance_leakConductance, param_voltage_leakReversal, statevariable_voltage_v_in , derivedvariable_current_iSyn_next )
begin
derivedvariable_current_iSyn_next <= resize(( exposure_current_SynapseModel_i_internal ),-28,-53);
derivedvariable_current_iMemb_next <= resize(( param_conductance_leakConductance * ( param_voltage_leakReversal - statevariable_voltage_v_in ) + derivedvariable_current_iSyn_next ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_iSyn <= derivedvariable_current_iSyn_next;
derivedvariable_current_iMemb <= derivedvariable_current_iMemb_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDRegime EDState Machine Process
---------------------------------------------------------------------
regime_state_process_comb :process (sysparam_time_simtime,current_regime_in_int,init_model,statevariable_voltage_v_in, statevariable_time_lastSpikeTime_in , param_time_refract, sysparam_time_simtime, param_voltage_thresh, statevariable_voltage_v_in )
begin
next_regime <= current_regime_in_int;
if init_model = '1' then
next_regime <= integrating;
else
if ( current_regime_in_int = refractory ) and To_slv ( resize (sysparam_time_simtime- ( statevariable_time_lastSpikeTime_in + param_time_refract ) ,2,-18))(20) = '0' then
next_regime <= integrating;
end if;
if ( current_regime_in_int = integrating ) and To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
next_regime <= refractory;
end if;
end if;
end process;
current_regime_out_stdlv <= CONV_REGIME_TO_STDLV(next_regime);
current_regime_in_int <= CONV_STDLV_TO_REGIME(current_regime_in_stdlv);
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv ,statevariable_voltage_v_in)
begin
statevariable_voltage_integrating_v_temp_1_next <= resize(statevariable_voltage_v_in + ( derivedvariable_current_iMemb * param_capacitance_inv_C_inv ) * sysparam_time_timestep,2,-22);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_voltage_integrating_v_temp_1 <= statevariable_voltage_integrating_v_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,param_voltage_reset,current_regime_in_int,next_regime,statevariable_voltage_integrating_v_temp_1,derivedvariable_current_iMemb,param_capacitance_C,param_capacitance_inv_C_inv)
variable statevariable_voltage_v_temp_1 : sfixed (2 downto -22);
variable statevariable_voltage_v_temp_2 : sfixed (2 downto -22);
begin
if ( current_regime_in_int = refractory ) then
statevariable_voltage_v_temp_1 := resize(statevariable_voltage_v_in ,2,-22);
end if;
if ( current_regime_in_int = integrating ) then
statevariable_voltage_v_temp_1 := statevariable_voltage_integrating_v_temp_1;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = refractory ) then
statevariable_voltage_v_temp_2 := resize( param_voltage_reset ,2,-22);
else
statevariable_voltage_v_temp_2 := statevariable_voltage_v_temp_1;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = integrating ) then
end if;
statevariable_voltage_v_next <= statevariable_voltage_v_temp_2;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_1 :process (sysparam_time_timestep,init_model,current_regime_in_int,next_regime)
variable statevariable_time_lastSpikeTime_temp_1 : sfixed (6 downto -18);
begin
if ( current_regime_in_int = refractory ) then
statevariable_time_lastSpikeTime_temp_1 := resize(statevariable_time_lastSpikeTime_in ,6,-18);
end if;
if ( current_regime_in_int = integrating ) then
statevariable_time_lastSpikeTime_temp_1 := resize(statevariable_time_lastSpikeTime_in ,6,-18);
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = refractory ) then
statevariable_time_lastSpikeTime_temp_1 := resize(sysparam_time_simtime,6,-18);
else
statevariable_time_lastSpikeTime_temp_1 := statevariable_time_lastSpikeTime_in;
end if;
if (not ( current_regime_in_int = next_regime )) and ( next_regime = integrating ) then
end if;
statevariable_time_lastSpikeTime_next <= statevariable_time_lastSpikeTime_temp_1;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
eventport_driver0 :process ( clk,sysparam_time_timestep,init_model, param_voltage_thresh, statevariable_voltage_v_in )
variable eventport_out_spike_temp_1 : std_logic;
variable eventport_out_spike_temp_2 : std_logic;
begin
if rising_edge(clk) and subprocess_all_ready_shot = '1' then
if ( current_regime_in_int = integrating) and To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' then
eventport_out_spike_temp_1 := '1';
else
eventport_out_spike_temp_1 := '0';
end if;eventport_out_spike_internal <= eventport_out_spike_temp_1;
end if;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_voltage_v <= statevariable_voltage_v_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_voltage_v_out <= statevariable_voltage_v_next;statevariable_time_lastSpikeTime_out <= statevariable_time_lastSpikeTime_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(SynapseModel_component_done,CLK)
begin
if (SynapseModel_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
---------------------------------------------------------------------
-- Control the done signal
---------------------------------------------------------------------
step_once_complete_synch:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then step_once_complete <= '0';
step_once_complete_fired <= '1';
else if component_done = '1' and step_once_complete_fired = '0' then
step_once_complete <= '1';
step_once_complete_fired <= '1';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= eventport_out_spike_internal ;
---------------------------------------------------------------------
elsif component_done = '0' then
step_once_complete <= '0';
step_once_complete_fired <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
else
step_once_complete <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
end if;
end if;
end if;
end process step_once_complete_synch;
---------------------------------------------------------------------
end RTL;
|
lgpl-3.0
|
FinnK/lems2hdl
|
work/N3_pointCellCondBased/ISIM_output/synapsemodel.vhdl
|
1
|
11618
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity synapsemodel is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end synapsemodel;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of synapsemodel is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal statevariable_conductance_noregime_g_temp_1 : sfixed (-22 downto -53);
signal statevariable_conductance_noregime_g_temp_1_next : sfixed (-22 downto -53);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_i : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_i_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_conductance_g_next : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_in_in_internal : std_logic := '0';
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, statevariable_conductance_g_in , requirement_voltage_v , param_voltage_erev )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep, statevariable_conductance_g_in , requirement_voltage_v , param_voltage_erev )
begin
derivedvariable_current_i_next <= resize(( statevariable_conductance_g_in * ( param_voltage_erev - requirement_voltage_v ) ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_i <= derivedvariable_current_i_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, param_time_tauDecay, statevariable_conductance_g_in ,param_time_inv_tauDecay_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, param_time_tauDecay, statevariable_conductance_g_in ,param_time_inv_tauDecay_inv ,statevariable_conductance_g_in)
begin
statevariable_conductance_noregime_g_temp_1_next <= resize(statevariable_conductance_g_in + ( - statevariable_conductance_g_in * param_time_inv_tauDecay_inv ) * sysparam_time_timestep,-22,-53);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_conductance_noregime_g_temp_1 <= statevariable_conductance_noregime_g_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,eventport_in_in,statevariable_conductance_g_in,param_conductance_gbase,statevariable_conductance_noregime_g_temp_1,param_time_tauDecay,statevariable_conductance_g_in,param_time_inv_tauDecay_inv)
variable statevariable_conductance_g_temp_1 : sfixed (-22 downto -53);
variable statevariable_conductance_g_temp_2 : sfixed (-22 downto -53);
begin
statevariable_conductance_g_temp_1 := statevariable_conductance_noregime_g_temp_1; if eventport_in_in = '1' then
statevariable_conductance_g_temp_2 := resize( statevariable_conductance_g_in + param_conductance_gbase ,-22,-53);
else
statevariable_conductance_g_temp_2 := statevariable_conductance_g_temp_1;
end if;
statevariable_conductance_g_next <= statevariable_conductance_g_temp_2;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_conductance_g <= statevariable_conductance_g_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_conductance_g_out <= statevariable_conductance_g_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_current_i <= derivedvariable_current_i_in;derivedvariable_current_i_out <= derivedvariable_current_i;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
|
lgpl-3.0
|
ShepardSiegel/ocpi
|
libsrc/hdl/vhd/ocpi_wci_body.vhd
|
1
|
3439
|
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.all; use ocpi.types.all;
package body wci is
-- convert byte enables to byte offsets
function decode_access(input : in_t) return access_t is begin
case input.MCmd is
when ocp.MCmd_WRITE => if input.MAddrSpace(0) = '1' then return write_e; else return Error_e; end if;
when ocp.MCmd_READ => if input.MAddrSpace(0) = '1' then return Read_e; else return Control_e; end if;
when others => return None_e;
end case;
end decode_access;
--function "=" (l,r: Property_Io_t) return boolean is begin
-- return Property_io_t'pos(l) = Property_io_t'pos(r);
--end "=";
-- return property access specific to this offset and size and address width
-- the basic decode is redundant across properties, but should be optimized anyawy
--function decode_property (input : in_t; low, high : unsigned) return property_access_t is
-- variable io : property_io_t := config_access(input);
-- variable moffset : unsigned (low'left downto 0)
-- := unsigned(input.MAddr(low'left downto 2) & be2offset(input));
--begin
-- if io /= None_e and moffset >= low and moffset <= high then
-- return property_access_t'(io, moffset - low);
-- end if;
-- return property_access_t'(None_e, property_offset_t'(others => '0'));
--end decode_property;
function get_value(input : in_t; boffset : unsigned; width : natural) return std_logic_vector is
variable bitoffset : natural := to_integer(boffset & "000");
variable bitwidth : natural := width;
begin
if bitwidth > 32 then bitwidth := 32; end if;
return input.MData(bitoffset + bitwidth - 1 downto bitoffset);
end get_value;
function to_control_op(bits : std_logic_vector(2 downto 0)) return control_op_t is
begin
--this fine in VHDL, but not in XST
--return control_op_t'val(to_integer(unsigned(bits)));
case to_integer(unsigned(bits)) is
when control_op_t'pos(initialize_e) => return initialize_e;
when control_op_t'pos(start_e) => return start_e;
when control_op_t'pos(stop_e) => return stop_e;
when control_op_t'pos(release_e) => return release_e;
when control_op_t'pos(before_query_e) => return before_query_e;
when control_op_t'pos(after_config_e) => return after_config_e;
when control_op_t'pos(test_e) => return test_e;
when others => return no_op_e;
end case;
--return start_e; --to_unsigned(2,3); --unsigned(bits);
-- case unsigned(bits) is
-- when initialize_e => return initialize_e;
-- when start_e => return start_e;
-- when stop_e => return stop_e;
-- when release_e => return release_e;
-- when before_query_e => return before_query_e;
-- when after_config_e => return after_config_e;
-- when test_e => return test_e;
-- when others => return no_op_e;
-- end case;
end to_control_op;
-- How wide should the data path be from the decoder to the property
function data_out_top (property : property_t) return natural is
begin
if property.data_width >= 32 or property.nitems > 1 then
return 31;
else
return property.data_width - 1;
end if;
end data_out_top;
function resize(bits : std_logic_vector; n : natural) return std_logic_vector is begin
return std_logic_vector(resize(unsigned(bits),n));
end resize;
end wci;
|
lgpl-3.0
|
ShepardSiegel/ocpi
|
libsrc/hdl/vhd/bias_vhdl_impl.vhd
|
1
|
28038
|
-- THIS FILE WAS GENERATED ON Tue Oct 30 13:46:44 2012 EDT
-- BASED ON THE FILE: bias_vhdl.xml
-- YOU PROBABLY SHOULD NOT EDIT IT
-- This file contains the implementation declarations for worker bias_vhdl
-- Interface definition signal names defined with pattern rule: "%s_"
-- OCP-based Control Interface, based on the WCI profile,
-- used for clk/reset, control and configuration
-- /\
-- /--\
-- +--------------------OCP----||----OCP---------------------------+
-- | \--/ |
-- | \/ |
-- | Entity: <worker> |
-- | |
-- O +------------------------------------------------------+ O
-- C | Entity: <worker>_worker | C
-- P | | P
-- | | This "inner layer" is the code you write, based | |
-- Data Input |\ | on definitions the in <worker>_worker_defs package, | |\ Data Output
-- Port based ==| \ | and the <worker>_worker entity, both in this file, | =| \ Port based
-- on the WSI ==| / | both in the "work" library. | =| / on the WSI
-- OCP Profile |/ | Package and entity declaration is this | |/ OCP Profile
-- O | <worker>_impl.vhd file. Architeture is in your | |
-- O | <worker>.vhd file | O
-- C | | C
-- P +------------------------------------------------------+ P
-- | |
-- | This outer layer is the "worker shell" code which |
-- | is automatically generated. The "worker shell" is |
-- | defined as the <worker> entity using definitions in |
-- | the <worker>_defs package. The worker shell is also |
-- | defined as a VHDL component in the <worker>_defs package, |
-- | as declared in the <worker>_defs.vhd file. |
-- | The worker shell "architecture" is also in this file, |
-- | as well as some subsidiary modules. |
-- +---------------------------------------------------------------+
-- This package defines types needed for the inner worker entity's generics or ports
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
package bias_vhdl_worker_defs is
-- The following record is for the writable properties of worker "bias_vhdl"
type worker_props_write_t is record
biasValue : ULong_t;
biasValue_written : Bool_t;
end record worker_props_write_t;
-- The following two records are for the inner/worker interfaces for port "ctl"
type worker_ctl_in_t is record
clk : std_logic; -- clock for this worker
reset : Bool_t; -- reset for this worker, at least 16 clocks long
control_op : wci.control_op_t; -- control op in progress, or no_op_e
state : wci.state_t; -- wci state: see state_t
is_operating : Bool_t; -- shorthand for state = operating_e
abort_control_op : Bool_t; -- demand that slow control op finish now
is_big_endian : Bool_t; -- for endian-switchable workers
end record worker_ctl_in_t;
type worker_ctl_out_t is record
done : Bool_t; -- is the pending prop access/config op done?
attention : Bool_t; -- worker wants attention
end record worker_ctl_out_t;
-- The following two records are for the inner/worker interfaces for port "in"
type worker_in_in_t is record
reset : Bool_t; -- this port is being reset from the outside peer
ready : Bool_t; -- this port is ready for data to be taken
-- one or more of: som, eom, valid are true
data : std_logic_vector(31 downto 0);
byte_enable : std_logic_vector(3 downto 0);
som, eom, valid : Bool_t; -- valid means data and byte_enable are present
end record worker_in_in_t;
type worker_in_out_t is record
take : Bool_t; -- take data now from this port
-- can be asserted when ready is true
end record worker_in_out_t;
-- The following two records are for the inner/worker interfaces for port "out"
type worker_out_in_t is record
reset : Bool_t; -- this port is being reset from the outside peer
ready : Bool_t; -- this port is ready for data to be given
end record worker_out_in_t;
type worker_out_out_t is record
give : Bool_t; -- give data now to this port
-- can be asserted when ready is true
data : std_logic_vector(31 downto 0);
byte_enable : std_logic_vector(3 downto 0);
som, eom, valid : Bool_t; -- one or more must be true when 'give' is asserted
end record worker_out_out_t;
end package bias_vhdl_worker_defs;
-- This is the entity to be implemented, depending on the above record types.
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_worker_defs.all;
entity bias_vhdl_worker is
port(
-- Signals for control and configuration. See record types above.
ctl_in : in worker_ctl_in_t;
ctl_out : out worker_ctl_out_t;
-- Input values and strobes for this worker's writable properties
props_write : in worker_props_write_t;
-- Signals for WSI input port named "in". See record types above.
in_in : in worker_in_in_t;
in_out : out worker_in_out_t;
-- Signals for WSI output port named "out". See record types above.
out_in : in worker_out_in_t;
out_out : out worker_out_out_t);
end entity bias_vhdl_worker;
-- The rest of the file below here is the implementation of the worker shell
-- which surrounds the entity to be implemented, above.
-- Worker-specific definitions that are needed outside entities below
package body bias_vhdl_defs is
constant worker : ocpi.wci.worker_t := (5, "00000100");
constant properties : ocpi.wci.properties_t := (
0 => (32, 0, 3, 0, 1, true, true, false, false)
);
end bias_vhdl_defs;
-- This is the entity declaration that the worker developer will implement
-- The achitecture for this entity will be in the implementation file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
library work;
use work.all;
use work.bias_vhdl_defs.all;
entity bias_vhdl is
port (
-- The WCI interface named "ctl", with "bias_vhdl" acting as OCP slave:
-- WIP attributes for this WCI interface are:
-- Clock: this interface has its own clock, named "ctl_Clk"
-- SizeOfConfigSpace: 4 (0x4)
-- WritableConfigProperties: true
-- ReadableConfigProperties: true
-- Sub32BitConfigProperties: false
-- ControlOperations (in addition to the required "start"):
-- ResetWhileSuspended: true
ctl_Clk : in std_logic;
ctl_MAddr : in std_logic_vector(4 downto 0);
ctl_MAddrSpace : in std_logic_vector(0 downto 0);
ctl_MCmd : in std_logic_vector(2 downto 0);
ctl_MData : in std_logic_vector(31 downto 0);
ctl_MFlag : in std_logic_vector(1 downto 0);
ctl_MReset_n : in std_logic;
ctl_SData : out std_logic_vector(31 downto 0);
ctl_SFlag : out std_logic_vector(1 downto 0);
ctl_SResp : out std_logic_vector(1 downto 0);
ctl_SThreadBusy : out std_logic_vector(0 downto 0);
-- The WSI consumer interface named "in", with "bias_vhdl" acting as OCP slave:
-- WIP attributes for this WSI interface are:
-- Clock: uses the clock from interface named "ctl"
-- Protocol: "stream32"
-- DataValueWidth: 8
-- DataValueGranularity: 1
-- DiverseDataSizes: false
-- MaxMessageValues: 16380
-- NumberOfOpcodes: 256
-- Producer: false
-- VariableMessageLength: true
-- ZeroLengthMessages: true
-- Continuous: false
-- DataWidth: 32
-- ByteWidth: 8
-- ImpreciseBurst: true
-- Preciseburst: true
-- Abortable: false
-- EarlyRequest: false
-- No Clk signal here. The "in" interface uses "ctl_Clk" as clock
in_MBurstLength : in std_logic_vector(11 downto 0);
in_MByteEn : in std_logic_vector(3 downto 0);
in_MCmd : in std_logic_vector(2 downto 0);
in_MData : in std_logic_vector(31 downto 0);
in_MBurstPrecise : in std_logic;
in_MReqInfo : in std_logic_vector(7 downto 0);
in_MReqLast : in std_logic;
in_MReset_n : in std_logic;
in_SReset_n : out std_logic;
in_SThreadBusy : out std_logic_vector(0 downto 0);
-- The WSI producer interface named "out", with "bias_vhdl" acting as OCP master:
-- WIP attributes for this WSI interface are:
-- Clock: uses the clock from interface named "ctl"
-- Protocol: "stream32"
-- DataValueWidth: 8
-- DataValueGranularity: 1
-- DiverseDataSizes: false
-- MaxMessageValues: 16380
-- NumberOfOpcodes: 256
-- Producer: true
-- VariableMessageLength: true
-- ZeroLengthMessages: true
-- Continuous: false
-- DataWidth: 32
-- ByteWidth: 8
-- ImpreciseBurst: true
-- Preciseburst: true
-- Abortable: false
-- EarlyRequest: false
-- No Clk signal here. The "out" interface uses "ctl_Clk" as clock
out_SReset_n : in std_logic;
out_SThreadBusy : in std_logic_vector(0 downto 0);
out_MBurstLength : out std_logic_vector(11 downto 0);
out_MByteEn : out std_logic_vector(3 downto 0);
out_MCmd : out std_logic_vector(2 downto 0);
out_MData : out std_logic_vector(31 downto 0);
out_MBurstPrecise : out std_logic;
out_MReqInfo : out std_logic_vector(7 downto 0);
out_MReqLast : out std_logic;
out_MReset_n : out std_logic
);
-- Aliases for WCI interface "ctl"
alias ctl_Terminate : std_logic is ctl_MFlag(0);
alias ctl_Endian : std_logic is ctl_MFlag(1);
alias ctl_Config : std_logic is ctl_MAddrSpace(0);
alias ctl_Attention : std_logic is ctl_SFlag(0);
-- Constants for bias_vhdl's property addresses
subtype Property_t is std_logic_vector(4 downto 0);
constant biasValue : Property_t := b"00000"; -- 0x00
-- Aliases for interface "in"
subtype in_OpCode_t is std_logic_vector(7 downto 0);
alias in_Opcode: in_OpCode_t is in_MReqInfo(7 downto 0);
-- Opcode/operation value declarations for protocol "stream32" on interface "in"
constant in_data_Op : in_Opcode_t := b"00000000"; -- 0x00
-- Aliases for interface "out"
subtype out_OpCode_t is std_logic_vector(7 downto 0);
alias out_Opcode: out_OpCode_t is out_MReqInfo(7 downto 0);
-- Opcode/operation value declarations for protocol "stream32" on interface "out"
constant out_data_Op : out_Opcode_t := b"00000000"; -- 0x00
signal wci_reset : bool_t;
-- these signals provide the values of writable properties
signal biasValue_value : ULong_t;
signal biasValue_written : Bool_t;
signal wci_attention, wci_is_operating: Bool_t;
signal wci_is_big_endian, wci_abort_control_op, wci_done : Bool_t;
signal wci_control_op : wci.control_op_t;
signal wci_state : wci.state_t;
signal in_take : Bool_t;
signal in_ready : Bool_t;
signal in_reset : Bool_t; -- this port is being reset from the outside
signal in_data : std_logic_vector(31 downto 0);
signal in_byte_enable: std_logic_vector(3 downto 0);
signal in_som : Bool_t; -- valid eom
signal in_eom : Bool_t; -- valid som
signal in_valid : Bool_t; -- valid data
signal out_give : Bool_t;
signal out_ready : Bool_t;
signal out_reset : Bool_t; -- this port is being reset from the outside
signal out_data : std_logic_vector(31 downto 0);
signal out_byte_enable: std_logic_vector(3 downto 0);
signal out_som : Bool_t; -- valid eom
signal out_eom : Bool_t; -- valid som
signal out_valid : Bool_t; -- valid data
end entity bias_vhdl;
-- Here we define and implement the WCI interface module for this worker,
-- which can be used by the worker implementer to avoid all the OCP/WCI issues
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ocpi;
use ocpi.all; use ocpi.types.all;
library work;
use work.all; use work.bias_vhdl_defs.all;
entity bias_vhdl_wci is
port(
inputs : in ctl_in_t; -- signal bundle from wci interface
done : in bool_t := btrue; -- worker uses this to delay completion
attention : in bool_t := bfalse; -- worker indicates an attention condition
outputs : out wci.out_t; -- signal bundle to wci interface
reset : out bool_t; -- wci reset for worker
control_op : out wci.control_op_t; -- control op in progress, or no_op_e
state : out wci.state_t; -- wci state: see state_t
is_operating : out bool_t; -- shorthand for state==operating_e
is_big_endian : out bool_t; -- for endian-switchable workers
abort_control_op : out bool_t; -- forcible abort a control-op when
-- worker uses 'done' to delay it
-- Outputs for this worker's writable properties
biasValue_value : out ULong_t;
biasValue_written : out Bool_t
);
end entity;
architecture rtl of bias_vhdl_wci is
signal my_reset : bool_t; -- internal usage of output
-- signals for property reads and writes
signal offsets : wci.offset_a_t(0 to 0); -- offsets within each property
signal indices : wci.offset_a_t(0 to 0); -- array index for array properties
signal hi32 : bool_t; -- high word of 64 bit value
signal nbytes_1 : types.byte_offset_t; -- # bytes minus one being read/written
-- signals between the decoder and the writable property registers
signal write_enables : bool_array_t(0 to 0);
signal data : wci.data_a_t (0 to 0); -- data being written, right justified
-- signals between the decoder and the readback mux
signal read_enables : bool_array_t(0 to 0);
signal readback_data : wci.data_a_t(bias_vhdl_defs.properties'range);
-- internal signals between property registers and the readback mux
-- for those that are writable, readable, and not volatile
signal my_biasValue_value : ULong_t;
-- temp signal to workaround isim/fuse crash bug
signal wciAddr : std_logic_vector(31 downto 0);
begin
wciAddr(inputs.MAddr'range) <= inputs.MAddr;
wciAddr(31 downto inputs.MAddr'length) <= (others => '0');
outputs.SFlag(0) <= '1' when its(attention) else '0';
outputs.SFlag(1) <= '1'; -- worker is present
outputs.SThreadBusy(0) <= '0' when its(done) else '1';
my_reset <= to_bool(inputs.MReset_n = '0');
reset <= my_reset;
x : component wci.decoder
generic map(worker => bias_vhdl_defs.worker,
properties => bias_vhdl_defs.properties)
port map( ocp_in.Clk => inputs.Clk,
ocp_in.Maddr => wciAddr,
ocp_in.MAddrSpace(0) => inputs.MAddrSpace(0),
ocp_in.MByteEn => "0000",
ocp_in.MCmd => inputs.MCmd,
ocp_in.MData => inputs.MData,
ocp_in.MFlag => inputs.MFlag,
ocp_in.MReset_n => inputs.MReset_n,
done => done,
resp => outputs.SResp,
write_enables => write_enables,
read_enables => read_enables,
offsets => offsets,
indices => indices,
hi32 => hi32,
nbytes_1 => nbytes_1,
data_outputs => data,
control_op => control_op,
state => state,
is_operating => is_operating,
abort_control_op => abort_control_op,
is_big_endian => is_big_endian);
readback : component wci.readback
generic map(bias_vhdl_defs.properties)
port map( read_enables => read_enables,
data_inputs => readback_data,
data_output => outputs.SData);
biasValue : component ocpi.props.ULong_property
generic map(worker => bias_vhdl_defs.worker,
property => bias_vhdl_defs.properties(0))
port map( clk => inputs.Clk,
reset => my_reset,
write_enable => write_enables(0),
data => data(0)(31 downto 0),
value => my_biasValue_value,
written => biasValue_written);
biasValue_value <= my_biasValue_value;
biasValue_readback : component ocpi.props.read_ULong_property
generic map(worker => bias_vhdl_defs.worker,
property => bias_vhdl_defs.properties(0))
port map( value => my_biasValue_value,
data_out => readback_data(0));
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL;
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_defs.all;
entity bias_vhdl_in_wsi is
port (-- Exterior OCP signals
ocp_in : in in_in_t;
ocp_out : out in_out_t;
-- Signals connected from the worker's WCI to this interface;
wci_clk : in std_logic;
wci_reset : in Bool_t;
-- Interior signals used by worker logic
reset : out Bool_t; -- this port is being reset from outside/peer
ready : out Bool_t; -- data can be taken
take : in Bool_t;
data : out std_logic_vector(31 downto 0);
byte_enable : out std_logic_vector(3 downto 0);
som, eom, valid : out Bool_t);
end entity;
architecture rtl of bias_vhdl_in_wsi is
signal fifo_full_n, fifo_empty_n : std_logic;
signal my_take, my_reset_n, my_enq : std_logic;
component FIFO2
generic (width : natural := 1; \guarded\ : natural := 1);
port( CLK : in std_logic;
RST : in std_logic;
D_IN : in std_logic_vector(width - 1 downto 0);
ENQ : in std_logic;
DEQ : in std_logic;
CLR : in std_logic;
FULL_N : out std_logic;
EMPTY_N : out std_logic;
D_OUT : out std_logic_vector(width - 1 downto 0));
end component FIFO2;
begin
my_take <= '1' when its(take) else '0';
my_enq <= '1' when ocp_in.MCmd = ocpi.ocp.MCmd_WRITE else '0';
my_reset_n <= '0' when wci_reset or (ocp_in.MReset_n = '0') else '1';
ready <= btrue when fifo_empty_n = '1' else bfalse;
fifo : FIFO2
generic map(width => 32)
port map( clk => wci_clk,
rst => my_reset_n,
d_in => ocp_in.MData,
enq => my_enq,
full_n => fifo_full_n,
d_out => data,
deq => my_take,
empty_n => fifo_empty_n,
clr => '0');
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL;
library ocpi; use ocpi.types.all;
library work; use work.bias_vhdl_defs.all;
entity bias_vhdl_out_wsi is
port (-- Exterior OCP signals
ocp_in : in out_in_t;
ocp_out : out out_out_t;
-- Signals connected from the worker's WCI to this interface;
wci_clk : in std_logic;
wci_reset : in Bool_t;
-- Interior signals used by worker logic
reset : out Bool_t; -- this port is being reset from outside/peer
ready : out Bool_t; -- data can be given
give : in Bool_t;
data : in std_logic_vector(31 downto 0);
byte_enable : in std_logic_vector(3 downto 0);
som, eom, valid : in Bool_t);
end entity;
architecture rtl of bias_vhdl_out_wsi is
signal my_reset : Bool_t;
begin
my_reset <= wci_reset or (ocp_in.SReset_n = '0');
reset <= my_reset;
reg: process(wci_clk) is begin
if rising_edge(wci_clk) then
if its(my_reset) then
ready <= bfalse;
else
ready <= not to_bool(ocp_in.SThreadBusy(0));
end if;
end if;
end process;
ocp_out.MCmd <= ocpi.ocp.MCmd_WRITE when its(give) else ocpi.ocp.MCmd_IDLE;
ocp_out.MData <= data;
ocp_out.MReqLast <= '1' when its(eom) else '0';
ocp_out.MBurstLength <=
std_logic_vector(to_unsigned(1,ocp_out.MBurstLength'length)) when its(eom)
else std_logic_vector(to_unsigned(2, ocp_out.MBurstLength'length));
ocp_out.MByteEn <= byte_enable;
end architecture rtl;
library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all;
library ocpi; use ocpi.types.all; -- remove this to avoid all ocpi name collisions
architecture rtl of bias_vhdl is
signal unused : std_logic_vector(3 downto 0);
begin
-- This instantiates the WCI/Control module/entity generated in the *_impl.vhd file
-- With no user logic at all, this implements writable properties.
wci : entity bias_vhdl_wci
port map(-- These first signals are just for use by the wci module, not the worker
inputs.Clk => ctl_Clk,
inputs.MAddr => ctl_MAddr,
inputs.MAddrSpace => ctl_MAddrSpace,
inputs.MCmd => ctl_MCmd,
inputs.MData => ctl_MData,
inputs.MFlag => ctl_MFlag,
inputs.MReset_n => ctl_MReset_n,
outputs.SData => ctl_SData, outputs.SResp => ctl_SResp,
outputs.SFlag => ctl_SFlag, outputs.SThreadBusy => ctl_SThreadBusy,
-- These are outputs used by the worker logic
reset => wci_reset, -- OCP guarantees 16 clocks of reset
control_op => wci_control_op,
state => wci_state,
is_operating => wci_is_operating,
is_big_endian => wci_is_big_endian,
done => wci_done,
attention => wci_attention,
abort_control_op => wci_abort_control_op, -- use this to know when we are running
-- These are outputs to the worker for writable property values.
biasValue_value => biasValue_value,
biasValue_written => biasValue_written
);
--
-- The WSI interface helper component instance for port "in"
in_port : entity bias_vhdl_in_wsi
port map(-- These signals connect this component to the external OCP interface
ocp_in.MBurstLength => in_MBurstLength,
ocp_in.MBurstPrecise => in_MBurstPrecise,
ocp_in.MByteEn => in_MByteEn,
ocp_in.MCmd => in_MCmd,
ocp_in.MData => in_MData,
ocp_in.MReqInfo => in_MReqInfo,
ocp_in.MReqLast => in_MReqLast,
ocp_in.MReset_n => in_MReset_n,
ocp_out.SReset_n => in_SReset_n,
ocp_out.SThreadBusy => in_SThreadBusy,
-- These signals are just connected to the WCI
wci_clk => ctl_Clk,
wci_reset => wci_reset,
-- This signal is the only input from worker code
take => in_take,
-- Output signals from this component into the worker
reset => in_reset, -- this port is being reset from the outside
ready => in_ready,
data => in_data,
byte_enable => in_byte_enable,
som => in_som, -- valid eom
eom => in_eom, -- valid som
valid => in_valid); -- valid data
--
-- The WSI interface helper component instance for port "out"
out_port : entity bias_vhdl_out_wsi
port map(-- These signals connect this component to the external OCP interface
ocp_in.SReset_n => out_SReset_n,
ocp_in.SThreadBusy => out_SThreadBusy,
ocp_out.MBurstLength => out_MBurstLength,
ocp_out.MBurstPrecise => out_MBurstPrecise,
ocp_out.MByteEn => out_MByteEn,
ocp_out.MCmd => out_MCmd,
ocp_out.MData => out_MData,
ocp_out.MReqInfo => out_MReqInfo,
ocp_out.MReqLast => out_MReqLast,
ocp_out.MReset_n => out_MReset_n,
-- These signals are just connected to the WCI
wci_clk => ctl_Clk,
wci_reset => wci_reset,
-- This signal is the control input from worker code
give => out_give,
-- Output signals from this component into the worker
reset => out_reset, -- this port is being reset from the outside
ready => out_ready,
data => out_data,
byte_enable => out_byte_enable,
som => out_som, -- valid eom
eom => out_eom, -- valid som
valid => out_valid); -- valid data
bias_vhdl : entity bias_vhdl_worker
port map(
ctl_in.clk => ctl_Clk, ctl_in.reset => wci_reset,
ctl_in.control_op => wci_control_op,
ctl_in.state => wci_state,
ctl_in.is_operating => wci_is_operating,
ctl_in.abort_control_op => wci_abort_control_op,
ctl_in.is_big_endian => wci_is_big_endian,
ctl_out.done => wci_done, ctl_out.attention => wci_attention,
in_in.reset => in_reset,
in_in.ready => in_ready,
in_in.data => in_data,
in_in.byte_enable => in_byte_enable,
in_in.som => in_som,
in_in.eom => in_eom,
in_in.valid => in_valid,
in_out.take => in_take,
out_in.reset => out_reset,
out_in.ready => out_ready,
out_out.give => out_give, out_out.data => out_data,
out_out.byte_enable => out_byte_enable,
out_out.som => out_som,
out_out.eom => out_eom,
out_out.valid => out_valid,
props_write.biasValue => biasValue_value,
props_write.biasValue_written => biasValue_written);
end rtl;
|
lgpl-3.0
|
The7thPres/CFTP
|
CFTP_Sat/CFTP_Sat.srcs/sources_1/ip/Signed_Mult/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
3
|
30077
|
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`protect end_protected
|
lgpl-3.0
|
The7thPres/CFTP
|
CFTP_Sat/CFTP_Sat.ip_user_files/ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
|
3
|
103154
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224)
`protect data_block
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`protect end_protected
|
lgpl-3.0
|
The7thPres/CFTP
|
CFTP_Sat/CFTP_Sat.srcs/sources_1/ip/Unsigned_Mult/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
3
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163693
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
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|
lgpl-3.0
|
id101010/vhdl-yasg
|
rotary_tb.vhd
|
1
|
1736
|
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 13:41:21 06/19/2016
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rotary_tb IS
END rotary_tb;
ARCHITECTURE behavior OF rotary_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rotary_dec
PORT(
clk : IN std_logic;
A : IN std_logic;
B : IN std_logic;
btn : IN std_logic;
btn_deb : OUT std_logic;
enc_right : OUT std_logic;
enc_ce : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal A : std_logic := '0';
signal B : std_logic := '0';
signal btn : std_logic := '0';
--Outputs
signal btn_deb : std_logic;
signal enc_right : std_logic;
signal enc_ce : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rotary_dec PORT MAP (
clk => clk,
A => A,
B => B,
btn => btn,
btn_deb => btn_deb,
enc_right => enc_right,
enc_ce => enc_ce
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;
|
lgpl-3.0
|
freecores/grain
|
src/VHDL/test_synth/hw2_grain.vhd
|
1
|
767
|
--
-- synthesis test 2:
-- * without clock enable
-- * slow
--
--
-- Altera EP2C-8, Quartus 8.0: (same as hw1_grain)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw2_grain is
port (
CLK_I : in std_logic;
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw2_grain is
begin
top: entity work.grain
generic map (
DEBUG => false,
FAST => false
)
port map (
CLK_I => CLK_I,
CLKEN_I => '1',
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
|
lgpl-3.0
|
jmarcelof/Phoenix
|
NoC/FPPM_AA00.vhd
|
2
|
3418
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.HammingPack16.all;
use work.NoCPackage.regNport;
entity FPPM is
port
(
clock : in std_logic;
reset_in : in std_logic; -- reset geral da NoC
rx : in regHamm_Nport; -- rx (sinal que indica que estou recebendo transmissao)
statusHamming : in array_statusHamming; -- status (sem erro, erro corrigido, erro detectado) das 4 portas (EAST,WEST,NORTH,SOUTH)
write_FaultTable : out regHamm_Nport; -- sinal para indicar escrita na tabela de falhas
row_FaultTablePorts_out : out row_FaultTable_Ports -- linha a ser escrita na tabela de falhas
);
end FPPM;
architecture FPPM of FPPM is
-- CUIDADO! Os contadores tem apenas COUNTERS_SIZE bits!
constant N: integer range 1 to 31 := 8;
constant M: integer range 1 to 31 := 4;
constant P: integer range 1 to 31 := 30;
constant COUNTER_UPDATE_TABLE: integer := 1; -- numero de flits recebidos necessarios para atualizar a tabela
begin
FPPM_generate: for i in 0 to (HAMM_NPORT-1) generate
begin
process(clock, reset_in)
variable counter_write: integer range 0 to COUNTER_UPDATE_TABLE;
variable reset: std_logic := '0';
variable counter_N, counter_M, counter_P: unsigned((COUNTERS_SIZE-1) downto 0);
variable link_status: unsigned(1 downto 0) := "00";
begin
if (reset_in='1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
if (clock'event and clock='1' and rx(i)='1') then
--counter_write := counter_write + 1;
case statusHamming(i) is
when NE =>
counter_N := counter_N + 1;
if (counter_N = N) then
link_status := "00";
reset := '1';
end if;
when EC =>
counter_M := counter_M + 1;
if (counter_M = M) then
link_status := "01";
reset := '1';
end if;
when ED =>
counter_P := counter_P + 1;
if (counter_P = P) then
link_status := "10";
reset := '1';
end if;
when others => null;
end case;
if (reset = '1') then
reset := '0';
counter_N := (others=>'0');
counter_M := (others=>'0');
counter_P := (others=>'0');
end if;
if (counter_write = COUNTER_UPDATE_TABLE) then
--if (false) then
write_FaultTable(i) <= '1';
row_FaultTablePorts_out(i) <= std_logic_vector(link_status & counter_N & counter_M & counter_P);
counter_write := 0;
else
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
elsif (rx(i)='0') then
write_FaultTable(i) <= '0';
row_FaultTablePorts_out(i) <= (others=>'0');
end if;
end process;
end generate;
end FPPM;
|
lgpl-3.0
|
Hyperion302/omega-cpu
|
Hardware/Open16750/slib_mv_filter.vhdl
|
1
|
2587
|
--
-- Majority voting filter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end slib_mv_filter;
architecture rtl of slib_mv_filter is
-- Signals
signal iCounter : unsigned(WIDTH downto 0); -- Sample counter
signal iQ : std_logic; -- Internal Q
begin
-- Main process
MV_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0');
iQ <= '0';
elsif (CLK'event and CLK='1') then
if (iCounter >= THRESHOLD) then -- Compare with threshold
iQ <= '1';
else
if (SAMPLE = '1' and D = '1') then -- Take sample
iCounter <= iCounter + 1;
end if;
end if;
if (CLEAR = '1') then -- Reset logic
iCounter <= (others => '0');
iQ <= '0';
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
lgpl-3.0
|
freecores/ternary_adder
|
vhdl/tb_ternary_adder.vhd
|
1
|
3180
|
---------------------------------------------------------------------------------------------
-- Author: Martin Kumm
-- Contact: [email protected]
-- License: LGPL
-- Date: 04.04.2013
--
-- Description:
-- Testbench for testing a single ternary adder component
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all; -- for uniform, trunc functions
entity tb_ternary_adder is
generic(
input_word_size : integer := 15;
subtract_y : boolean := false;
subtract_z : boolean := true;
use_output_ff : boolean := false
);
end tb_ternary_adder;
architecture tb_ternary_adder_arch of tb_ternary_adder is
signal clk, rst : std_logic := '0';
signal x,y,z : std_logic_vector(input_word_size-1 downto 0) := (others => '0');
signal sum : std_logic_vector(input_word_size+1 downto 0) := (others => '0');
signal sum_ref,sum_dut: integer := 0;
begin
dut: entity work.ternary_adder
generic map (
input_word_size => input_word_size,
subtract_y => subtract_y,
subtract_z => subtract_z,
use_output_ff => use_output_ff
)
port map (
clk_i => clk,
rst_i => rst,
x_i => x,
y_i => y,
z_i => z,
sum_o => sum
);
clk <= not clk after 5 ns; -- 100 MHz
rst <= '1', '0' after 5 ns;
process
variable seed1,seed2: positive;
variable rand : real;
variable x_int,y_int,z_int : integer;
begin
uniform(seed1, seed2, rand);
x_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
uniform(seed1, seed2, rand);
y_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
uniform(seed1, seed2, rand);
z_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
x <= std_logic_vector(to_signed(x_int, x'length)); -- rescale, quantize and convert
y <= std_logic_vector(to_signed(y_int, y'length)); -- rescale, quantize and convert
z <= std_logic_vector(to_signed(z_int, z'length)); -- rescale, quantize and convert
wait until clk'event and clk='1';
end process;
process(clk,rst,x,y,z)
variable y_sgn,z_sgn,sum_ref_unsync : integer;
begin
if subtract_y = true then
y_sgn := -1*to_integer(signed(y));
else
y_sgn := to_integer(signed(y));
end if;
if subtract_z = true then
z_sgn := -1*to_integer(signed(z));
else
z_sgn := to_integer(signed(z));
end if;
sum_ref_unsync := to_integer(signed(x)) + y_sgn + z_sgn;
if use_output_ff = false then
sum_ref <= sum_ref_unsync;
else
if clk'event and clk='1' then
sum_ref <= sum_ref_unsync;
end if;
end if;
end process;
process(clk,rst,sum_ref)
begin
end process;
sum_dut <= to_integer(signed(sum));
process
begin
wait for 50 ns;
loop
wait until clk'event and clk='0';
assert (sum_dut = sum_ref) report "Test failure" severity failure;
wait until clk'event and clk='1';
end loop;
end process;
end architecture;
|
lgpl-3.0
|
Hyperion302/omega-cpu
|
TestBenches/PortController.vhdl
|
1
|
3556
|
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use work.Constants.all;
use IEEE.Numeric_std.all;
entity PortController is
port (
CLK : in std_logic;
XMit : in Word;
Recv : out Word;
instruction : in Word;
CPUReady : in std_logic;
CPUSending: in std_logic;
PortReady: out std_logic;
PortSending: out std_logic;
Done: out std_logic;
SerialIn: in std_logic;
SerialOut: out std_logic);
end PortController;
architecture Behavioral of PortController is
signal Done_s : std_logic := '0';
signal PortSending_s : std_logic := '0';
signal nextWord : Word := (others => '0');
--signal readControl : integer := 0;
begin -- PortController
SerialOut <= '0';
PortSending <= PortSending_s;
Recv <= nextWord when PortSending_s = '1' else (others => '0');
Done <= Done_s;
process
variable input_line : line;
variable input_char : character;
variable input_read : boolean := false;
begin -- process
PortReady <= '0';
PortSending_s <= '0';
wait until rising_edge(CPUReady) and GetOpcode(instruction) = OpcodePort and (GetOperator(instruction) = LoadByteSigned or GetOperator(instruction) = LoadHalfWordSigned or GetOperator(instruction) = LoadByteUnsigned or GetOperator(instruction) = LoadHalfWordUnsigned or GetOperator(instruction) = LoadWord) and getRegisterReferenceB(instruction) = "00001"; -- rising clock edge
--wait until readControl = 1;
if not input_read then
readline(input,input_line);
end if;
if input_line'length > 0 then
read(input_line,input_char);
nextWord <= "000000000000000000000000" & std_logic_vector(to_unsigned(character'pos(input_char),8));
input_read := true;
else
nextWord <= "00000000000000000000000000001010";
input_read := false;
end if;
PortReady <= '1';
PortSending_s <= '1';
wait until CPUReady = '0';
end process;
process (CPUSending)
variable c : integer;
variable out_line : line;
variable currentOperator : Operator;
begin -- process
if rising_edge(CPUSending) then -- rising clock edge
currentOperator := GetOperator(instruction);
case currentOperator is
when StoreByte|StoreHalfWord|StoreWord =>
if CPUSending = '1' and GetRegisterReferenceB(instruction) = "00001" then
c := to_integer(unsigned(XMit(7 downto 0)));
if c /= 10 then
--write(out_line, to_bitvector(XMit));
write(out_line, character'val(c));
else
writeline(output, out_line);
end if;
Done_s <= '1';
else
Done_s <= '0';
end if;
when others =>
Done_s <= '0';
end case;
else
Done_s <= '0';
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
Hyperion302/omega-cpu
|
Hardware/Open16750/slib_clock_div.vhdl
|
1
|
2042
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
lgpl-3.0
|
Hyperion302/omega-cpu
|
Hardware/Omega/ipcore_dir/UARTClockManager/simulation/UARTClockManager_tb.vhd
|
1
|
6499
|
-- file: UARTClockManager_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity UARTClockManager_tb is
end UARTClockManager_tb;
architecture test of UARTClockManager_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.250 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component UARTClockManager_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : UARTClockManager_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET);
-- Freq Check
end test;
|
lgpl-3.0
|
Hyperion302/omega-cpu
|
Hardware/Open16750/slib_edge_detect.vhdl
|
1
|
1702
|
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
lgpl-3.0
|
Hyperion302/omega-cpu
|
Hardware/Open16750/slib_input_sync.vhdl
|
1
|
1562
|
--
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
|
lgpl-3.0
|
lerwys/GitTest
|
hdl/modules/position_calc/generated/virtex6/nonleaf_results.vhd
|
1
|
484765
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF/zero_filling1"
entity zero_filling1_entity_d0ac9899b1 is
port (
in1: in std_logic_vector(15 downto 0);
out1: out std_logic_vector(23 downto 0)
);
end zero_filling1_entity_d0ac9899b1;
architecture structural of zero_filling1_entity_d0ac9899b1 is
signal concat_y_net: std_logic_vector(23 downto 0);
signal constant_op_net: std_logic_vector(7 downto 0);
signal register1_q_net_x0: std_logic_vector(15 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(7 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(15 downto 0);
begin
register1_q_net_x0 <= in1;
out1 <= reinterpret2_output_port_net_x0;
concat: entity work.concat_cd3162dc0d
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => reinterpret_output_port_net,
in1 => reinterpret1_output_port_net,
y => concat_y_net
);
constant_x0: entity work.constant_91ef1678ca
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
reinterpret: entity work.reinterpret_7025463ea8
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register1_q_net_x0,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_f21e7f2ddf
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => constant_op_net,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => concat_y_net,
output_port => reinterpret2_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF"
entity bpf_entity_d31c4af409 is
port (
din_ch0: in std_logic_vector(15 downto 0);
din_ch1: in std_logic_vector(15 downto 0);
din_ch2: in std_logic_vector(15 downto 0);
din_ch3: in std_logic_vector(15 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end bpf_entity_d31c4af409;
architecture structural of bpf_entity_d31c4af409 is
signal register1_q_net_x1: std_logic_vector(15 downto 0);
signal register2_q_net_x1: std_logic_vector(15 downto 0);
signal register3_q_net_x1: std_logic_vector(15 downto 0);
signal register_q_net_x1: std_logic_vector(15 downto 0);
signal reinterpret2_output_port_net_x4: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x5: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x6: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x7: std_logic_vector(23 downto 0);
begin
register_q_net_x1 <= din_ch0;
register1_q_net_x1 <= din_ch1;
register2_q_net_x1 <= din_ch2;
register3_q_net_x1 <= din_ch3;
dout_ch0 <= reinterpret2_output_port_net_x7;
dout_ch1 <= reinterpret2_output_port_net_x4;
dout_ch2 <= reinterpret2_output_port_net_x5;
dout_ch3 <= reinterpret2_output_port_net_x6;
zero_filling1_d0ac9899b1: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register1_q_net_x1,
out1 => reinterpret2_output_port_net_x4
);
zero_filling2_d7e27e9bae: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register2_q_net_x1,
out1 => reinterpret2_output_port_net_x5
);
zero_filling3_1ae3b6c91e: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register3_q_net_x1,
out1 => reinterpret2_output_port_net_x6
);
zero_filling4_6d7b2d0c57: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register_q_net_x1,
out1 => reinterpret2_output_port_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub/TDM_dds_ch01_cosine"
entity tdm_dds_ch01_cosine_entity_4b8bfc9243 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
rst: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_dds_ch01_cosine_entity_4b8bfc9243;
architecture structural of tdm_dds_ch01_cosine_entity_4b8bfc9243 is
signal black_box_cos_o_net_x0: std_logic_vector(23 downto 0);
signal ce_1_sg_x0: std_logic;
signal ce_2_sg_x0: std_logic;
signal ce_logic_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal clk_2_sg_x0: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant11_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register4_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x0 <= ce_1;
ce_2_sg_x0 <= ce_2;
ce_logic_1_sg_x0 <= ce_logic_1;
clk_1_sg_x0 <= clk_1;
clk_2_sg_x0 <= clk_2;
black_box_cos_o_net_x0 <= din_ch0;
constant11_op_net_x0 <= rst;
dout <= register_q_net_x0;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x0,
clk => clk_1_sg_x0,
d => register2_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => register2_q_net,
d1 => register3_q_net,
sel(0) => register4_q_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op(0) => mux_sel1_op_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch0_q_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch1_q_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register4_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub"
entity dds_sub_entity_a4b6b880f6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_01_cosine: out std_logic_vector(23 downto 0);
dds_01_sine: out std_logic_vector(23 downto 0);
dds_23_cosine: out std_logic_vector(23 downto 0);
dds_23_sine: out std_logic_vector(23 downto 0)
);
end dds_sub_entity_a4b6b880f6;
architecture structural of dds_sub_entity_a4b6b880f6 is
signal black_box_cos_o_net_x1: std_logic_vector(23 downto 0);
signal black_box_sin_o_net_x1: std_logic_vector(23 downto 0);
signal ce_1_sg_x4: std_logic;
signal ce_2_sg_x4: std_logic;
signal ce_logic_1_sg_x4: std_logic;
signal clk_1_sg_x4: std_logic;
signal clk_2_sg_x4: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant16_op_net_x0: std_logic;
signal constant17_op_net_x0: std_logic;
signal constant3_op_net: std_logic;
signal constant7_op_net_x0: std_logic;
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
begin
ce_1_sg_x4 <= ce_1;
ce_2_sg_x4 <= ce_2;
ce_logic_1_sg_x4 <= ce_logic_1;
clk_1_sg_x4 <= clk_1;
clk_2_sg_x4 <= clk_2;
dds_01_cosine <= register_q_net_x4;
dds_01_sine <= register_q_net_x5;
dds_23_cosine <= register_q_net_x6;
dds_23_sine <= register_q_net_x7;
black_box: entity work.fixed_dds
generic map (
g_cos_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_cos.ram",
g_dither => false,
g_number_of_points => 148,
g_output_width => 24,
g_sin_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_sin.ram"
)
port map (
ce_i => ce_2_sg_x4,
clk_i => clk_2_sg_x4,
rst_n_i => constant3_op_net,
cos_o => black_box_cos_o_net_x1,
sin_o => black_box_sin_o_net_x1
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant16: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant16_op_net_x0
);
constant17: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant17_op_net_x0
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net
);
constant7: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant7_op_net_x0
);
tdm_dds_ch01_cosine_4b8bfc9243: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant11_op_net_x0,
dout => register_q_net_x4
);
tdm_dds_ch01_sine_1129eb9762: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant7_op_net_x0,
dout => register_q_net_x5
);
tdm_dds_ch23_cosine_398d5cee32: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant16_op_net_x0,
dout => register_q_net_x6
);
tdm_dds_ch23_sine_782ff6a42a: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant17_op_net_x0,
dout => register_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch/TDDM_fofb_amp0"
entity tddm_fofb_amp0_entity_fd74c6ad6e is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp0_entity_fd74c6ad6e;
architecture structural of tddm_fofb_amp0_entity_fd74c6ad6e is
signal assert2_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x0: std_logic;
signal ce_1120_sg_x0: std_logic;
signal ce_2240_sg_x0: std_logic;
signal clk_1120_sg_x0: std_logic;
signal clk_2240_sg_x0: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x0 <= ce_1120;
ce_2240_sg_x0 <= ce_2240;
assert3_dout_net_x0 <= ch_in;
clk_1120_sg_x0 <= clk_1120;
clk_2240_sg_x0 <= clk_2240;
assert2_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant1_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch"
entity tddm_fofb_amp_4ch_entity_2cc521a83f is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp_4ch_entity_2cc521a83f;
architecture structural of tddm_fofb_amp_4ch_entity_2cc521a83f is
signal assert2_dout_net_x2: std_logic_vector(23 downto 0);
signal assert2_dout_net_x3: std_logic_vector(23 downto 0);
signal assert3_dout_net_x2: std_logic;
signal assert3_dout_net_x3: std_logic;
signal ce_1120_sg_x2: std_logic;
signal ce_2240_sg_x2: std_logic;
signal clk_1120_sg_x2: std_logic;
signal clk_2240_sg_x2: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
assert2_dout_net_x2 <= amp_in0;
assert2_dout_net_x3 <= amp_in1;
ce_1120_sg_x2 <= ce_1120;
ce_2240_sg_x2 <= ce_2240;
assert3_dout_net_x2 <= ch_in0;
assert3_dout_net_x3 <= ch_in1;
clk_1120_sg_x2 <= clk_1120;
clk_2240_sg_x2 <= clk_2240;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_fofb_amp0_fd74c6ad6e: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x2,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x2,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_amp1_61cbc8ec65: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x3,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_b60a69fd9b is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_b60a69fd9b;
architecture structural of tddm_tbt_cordic1_entity_b60a69fd9b is
signal assert1_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x4: std_logic;
signal ce_1120_sg_x4: std_logic;
signal ce_2240_sg_x4: std_logic;
signal clk_1120_sg_x4: std_logic;
signal clk_2240_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x4 <= ce_1120;
ce_2240_sg_x4 <= ce_2240;
assert3_dout_net_x4 <= ch_in;
clk_1120_sg_x4 <= clk_1120;
clk_2240_sg_x4 <= clk_2240;
assert1_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant1_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0"
entity tddm_tbt_cordic0_entity_38de3613fe is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_cordic_ch_in: in std_logic;
fofb_cordic_din: in std_logic_vector(23 downto 0);
fofb_cordic_pin: in std_logic_vector(23 downto 0);
fofb_cordic_data0_out: out std_logic_vector(23 downto 0);
fofb_cordic_data1_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase0_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic0_entity_38de3613fe;
architecture structural of tddm_tbt_cordic0_entity_38de3613fe is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x4: std_logic_vector(23 downto 0);
signal assert3_dout_net_x5: std_logic;
signal ce_1120_sg_x5: std_logic;
signal ce_2240_sg_x5: std_logic;
signal clk_1120_sg_x5: std_logic;
signal clk_2240_sg_x5: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x5 <= ce_1120;
ce_2240_sg_x5 <= ce_2240;
clk_1120_sg_x5 <= clk_1120;
clk_2240_sg_x5 <= clk_2240;
assert3_dout_net_x5 <= fofb_cordic_ch_in;
assert2_dout_net_x4 <= fofb_cordic_din;
assert1_dout_net_x1 <= fofb_cordic_pin;
fofb_cordic_data0_out <= down_sample2_q_net_x2;
fofb_cordic_data1_out <= down_sample1_q_net_x2;
fofb_cordic_phase0_out <= down_sample2_q_net_x3;
fofb_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_fofb_cordic0_int_516d0c2a22: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert2_dout_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_cordic1_b60a69fd9b: entity work.tddm_tbt_cordic1_entity_b60a69fd9b
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert1_dout_net_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC"
entity fofb_cordic_entity_fad57e49ce is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_tbt_cordic0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_fad57e49ce;
architecture structural of fofb_cordic_entity_fad57e49ce is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x5: std_logic_vector(23 downto 0);
signal assert3_dout_net_x6: std_logic;
signal ce_1120_sg_x6: std_logic;
signal ce_1_sg_x5: std_logic;
signal ce_2240_sg_x6: std_logic;
signal clk_1120_sg_x6: std_logic;
signal clk_1_sg_x5: std_logic;
signal clk_2240_sg_x6: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x5 <= ce_1;
ce_1120_sg_x6 <= ce_1120;
ce_2240_sg_x6 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x5 <= clk_1;
clk_1120_sg_x6 <= clk_1120;
clk_2240_sg_x6 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x5;
ch_out <= assert3_dout_net_x6;
tddm_tbt_cordic0 <= down_sample1_q_net_x4;
tddm_tbt_cordic0_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic0_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic0_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x5
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x6
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_1700ad0af26476326977e0830172a2c4
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic0_38de3613fe: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x6,
ce_2240 => ce_2240_sg_x6,
clk_1120 => clk_1120_sg_x6,
clk_2240 => clk_2240_sg_x6,
fofb_cordic_ch_in => assert3_dout_net_x6,
fofb_cordic_din => assert2_dout_net_x5,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/Reg"
entity reg_entity_cf7aa296b2 is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end reg_entity_cf7aa296b2;
architecture structural of reg_entity_cf7aa296b2 is
signal ce_1120_sg_x7: std_logic;
signal clk_1120_sg_x7: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
begin
ce_1120_sg_x7 <= ce_1120;
clk_1120_sg_x7 <= clk_1120;
register_q_net_x2 <= din;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 23,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
d => convert_dout_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x2,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/TDDM_fofb_cic0"
entity tddm_fofb_cic0_entity_6b909292ff is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_ch_in: in std_logic;
fofb_i_in: in std_logic_vector(23 downto 0);
fofb_q_in: in std_logic_vector(23 downto 0);
cic_fofb_ch0_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch0_q_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_fofb_cic0_entity_6b909292ff;
architecture structural of tddm_fofb_cic0_entity_6b909292ff is
signal ce_1120_sg_x11: std_logic;
signal ce_2240_sg_x9: std_logic;
signal clk_1120_sg_x11: std_logic;
signal clk_2240_sg_x9: std_logic;
signal delay_q_net_x3: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x11 <= ce_1120;
ce_2240_sg_x9 <= ce_2240;
clk_1120_sg_x11 <= clk_1120;
clk_2240_sg_x9 <= clk_2240;
delay_q_net_x3 <= fofb_ch_in;
register_q_net_x4 <= fofb_i_in;
register_q_net_x3 <= fofb_q_in;
cic_fofb_ch0_i_out <= down_sample2_q_net_x2;
cic_fofb_ch0_q_out <= down_sample2_q_net_x3;
cic_fofb_ch1_i_out <= down_sample1_q_net_x2;
cic_fofb_ch1_q_out <= down_sample1_q_net_x3;
tddm_fofb_cic0_i_06b84397ec: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_cic0_q_a6a1d7c301: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg"
entity reg_entity_71dd029fba is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0)
);
end reg_entity_71dd029fba;
architecture structural of reg_entity_71dd029fba is
signal ce_1120_sg_x12: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x12: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x12 <= ce_1120;
clk_1120_sg_x12 <= clk_1120;
cic_fofb_q_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_q_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x3;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
d => convert_dout_net,
en(0) => cic_fofb_q_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x3
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_q_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg1"
entity reg1_entity_b079f30e3c is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end reg1_entity_b079f30e3c;
architecture structural of reg1_entity_b079f30e3c is
signal ce_1120_sg_x13: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x13: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register1_q_net_x2: std_logic;
signal register_q_net_x4: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x13 <= ce_1120;
clk_1120_sg_x13 <= clk_1120;
cic_fofb_i_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_i_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x4;
valid_out <= register1_q_net_x2;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x2
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d => convert_dout_net,
en(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x4
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_i_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb"
entity cic_fofb_entity_2ed6a6e00c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb_q_x0: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end cic_fofb_entity_2ed6a6e00c;
architecture structural of cic_fofb_entity_2ed6a6e00c is
signal ce_1120_sg_x14: std_logic;
signal ce_1_sg_x6: std_logic;
signal ce_logic_1_sg_x5: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tuser_chan_out_net: std_logic;
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x0: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x14: std_logic;
signal clk_1_sg_x6: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay_q_net_x4: std_logic;
signal register1_q_net_x3: std_logic;
signal register3_q_net_x0: std_logic;
signal register4_q_net_x0: std_logic_vector(23 downto 0);
signal register5_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(24 downto 0);
signal register_q_net_x6: std_logic_vector(24 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x6 <= ce_1;
ce_1120_sg_x14 <= ce_1120;
ce_logic_1_sg_x5 <= ce_logic_1;
register3_q_net_x0 <= ch_in;
clk_1_sg_x6 <= clk_1;
clk_1120_sg_x14 <= clk_1120;
register4_q_net_x0 <= i_in;
register5_q_net_x0 <= q_in;
ch_out <= delay_q_net_x4;
cic_fofb_q_x0 <= cic_fofb_q_event_tlast_missing_net_x0;
i_out <= register_q_net_x6;
q_out <= register_q_net_x5;
valid_out <= register1_q_net_x3;
cic_fofb_i: entity work.xlcic_compiler_691a78f3d9f6f4d23a2519dbc0c21266
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register4_q_net_x0,
s_axis_data_tlast => relational2_op_net,
m_axis_data_tdata_data => cic_fofb_i_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => cic_fofb_i_m_axis_data_tvalid_net_x0
);
cic_fofb_q: entity work.xlcic_compiler_691a78f3d9f6f4d23a2519dbc0c21266
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register5_q_net_x0,
s_axis_data_tlast => relational2_op_net,
event_tlast_missing => cic_fofb_q_event_tlast_missing_net_x0,
m_axis_data_tdata_data => cic_fofb_q_m_axis_data_tdata_data_net_x0,
m_axis_data_tvalid => cic_fofb_q_m_axis_data_tvalid_net_x0
);
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1120_sg_x14,
clk => clk_1120_sg_x14,
d(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q(0) => delay_q_net_x4
);
reg1_b079f30e3c: entity work.reg1_entity_b079f30e3c
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_i_m_axis_data_tdata_data_net_x0,
en => cic_fofb_i_m_axis_data_tvalid_net_x0,
dout => register_q_net_x6,
valid_out => register1_q_net_x3
);
reg_71dd029fba: entity work.reg_entity_71dd029fba
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_q_m_axis_data_tdata_data_net_x0,
en => cic_fofb_q_m_axis_data_tvalid_net_x0,
dout => register_q_net_x5
);
relational2: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x0,
b => constant1_op_net,
ce => ce_1_sg_x6,
clk => clk_1_sg_x6,
clr => '0',
op(0) => relational2_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp"
entity fofb_amp_entity_078cdb1842 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_078cdb1842;
architecture structural of fofb_amp_entity_078cdb1842 is
signal ce_1120_sg_x15: std_logic;
signal ce_1_sg_x7: std_logic;
signal ce_2240_sg_x10: std_logic;
signal ce_logic_1_sg_x6: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x15: std_logic;
signal clk_1_sg_x7: std_logic;
signal clk_2240_sg_x10: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x7 <= ce_1;
ce_1120_sg_x15 <= ce_1120;
ce_2240_sg_x10 <= ce_2240;
ce_logic_1_sg_x6 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x7 <= clk_1;
clk_1120_sg_x15 <= clk_1120;
clk_2240_sg_x10 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic0 <= down_sample1_q_net_x4;
tddm_fofb_cic0_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic0_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic0_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_2ed6a6e00c: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x7,
ce_1120 => ce_1120_sg_x15,
ce_logic_1 => ce_logic_1_sg_x6,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x7,
clk_1120 => clk_1120_sg_x15,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_6375e37e24: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_cf7aa296b2: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic0_6b909292ff: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x15,
ce_2240 => ce_2240_sg_x10,
clk_1120 => clk_1120_sg_x15,
clk_2240 => clk_2240_sg_x10,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0"
entity fofb_amp0_entity_95b23bfc2c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp0_entity_95b23bfc2c;
architecture structural of fofb_amp0_entity_95b23bfc2c is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x16: std_logic;
signal ce_1_sg_x8: std_logic;
signal ce_2240_sg_x11: std_logic;
signal ce_logic_1_sg_x7: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x16: std_logic;
signal clk_1_sg_x8: std_logic;
signal clk_2240_sg_x11: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x8 <= ce_1;
ce_1120_sg_x16 <= ce_1120;
ce_2240_sg_x11 <= ce_2240;
ce_logic_1_sg_x7 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x8 <= clk_1;
clk_1120_sg_x16 <= clk_1120;
clk_2240_sg_x11 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_078cdb1842: entity work.fofb_amp_entity_078cdb1842
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ce_logic_1 => ce_logic_1_sg_x7,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic0 => down_sample1_q_net_x10,
tddm_fofb_cic0_x0 => down_sample2_q_net_x10,
tddm_fofb_cic0_x1 => down_sample1_q_net_x11,
tddm_fofb_cic0_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_fad57e49ce: entity work.fofb_cordic_entity_fad57e49ce
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
tddm_tbt_cordic0 => down_sample1_q_net_x8,
tddm_tbt_cordic0_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic0_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic0_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_CORDIC"
entity fofb_cordic_entity_e4c0810ec7 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_fofb_cordic1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_e4c0810ec7;
architecture structural of fofb_cordic_entity_e4c0810ec7 is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x20: std_logic;
signal ce_1_sg_x9: std_logic;
signal ce_2240_sg_x15: std_logic;
signal clk_1120_sg_x20: std_logic;
signal clk_1_sg_x9: std_logic;
signal clk_2240_sg_x15: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x9 <= ce_1;
ce_1120_sg_x20 <= ce_1120;
ce_2240_sg_x15 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x9 <= clk_1;
clk_1120_sg_x20 <= clk_1120;
clk_2240_sg_x15 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
tddm_fofb_cordic1 <= down_sample1_q_net_x4;
tddm_fofb_cordic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cordic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cordic1_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x6
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x7
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_1700ad0af26476326977e0830172a2c4
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_fofb_cordic1_77b64089dc: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x20,
ce_2240 => ce_2240_sg_x15,
clk_1120 => clk_1120_sg_x20,
clk_2240 => clk_2240_sg_x15,
fofb_cordic_ch_in => assert3_dout_net_x7,
fofb_cordic_din => assert2_dout_net_x6,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_amp"
entity fofb_amp_entity_f70fcc8ed9 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_f70fcc8ed9;
architecture structural of fofb_amp_entity_f70fcc8ed9 is
signal ce_1120_sg_x29: std_logic;
signal ce_1_sg_x11: std_logic;
signal ce_2240_sg_x19: std_logic;
signal ce_logic_1_sg_x9: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x29: std_logic;
signal clk_1_sg_x11: std_logic;
signal clk_2240_sg_x19: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x11 <= ce_1;
ce_1120_sg_x29 <= ce_1120;
ce_2240_sg_x19 <= ce_2240;
ce_logic_1_sg_x9 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x11 <= clk_1;
clk_1120_sg_x29 <= clk_1120;
clk_2240_sg_x19 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic1 <= down_sample1_q_net_x4;
tddm_fofb_cic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic1_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_579902476d: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x11,
ce_1120 => ce_1120_sg_x29,
ce_logic_1 => ce_logic_1_sg_x9,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x11,
clk_1120 => clk_1120_sg_x29,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_a06a1c33b5: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_b669a3b118: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic1_4a640315a5: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x29,
ce_2240 => ce_2240_sg_x19,
clk_1120 => clk_1120_sg_x29,
clk_2240 => clk_2240_sg_x19,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1"
entity fofb_amp1_entity_a049562dde is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp1_entity_a049562dde;
architecture structural of fofb_amp1_entity_a049562dde is
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x30: std_logic;
signal ce_1_sg_x12: std_logic;
signal ce_2240_sg_x20: std_logic;
signal ce_logic_1_sg_x10: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x30: std_logic;
signal clk_1_sg_x12: std_logic;
signal clk_2240_sg_x20: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x12 <= ce_1;
ce_1120_sg_x30 <= ce_1120;
ce_2240_sg_x20 <= ce_2240;
ce_logic_1_sg_x10 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x12 <= clk_1;
clk_1120_sg_x30 <= clk_1120;
clk_2240_sg_x20 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x7;
ch_out <= assert3_dout_net_x8;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_f70fcc8ed9: entity work.fofb_amp_entity_f70fcc8ed9
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ce_logic_1 => ce_logic_1_sg_x10,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic1 => down_sample1_q_net_x10,
tddm_fofb_cic1_x0 => down_sample2_q_net_x10,
tddm_fofb_cic1_x1 => down_sample1_q_net_x11,
tddm_fofb_cic1_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_e4c0810ec7: entity work.fofb_cordic_entity_e4c0810ec7
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
tddm_fofb_cordic1 => down_sample1_q_net_x8,
tddm_fofb_cordic1_x0 => down_sample2_q_net_x8,
tddm_fofb_cordic1_x1 => down_sample1_q_net_x9,
tddm_fofb_cordic1_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp"
entity fofb_amp_entity_8b25d4b0b6 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
fofb_amp0: out std_logic_vector(23 downto 0);
fofb_amp0_x0: out std_logic_vector(23 downto 0);
fofb_amp0_x1: out std_logic_vector(23 downto 0);
fofb_amp0_x2: out std_logic_vector(23 downto 0);
fofb_amp0_x3: out std_logic_vector(23 downto 0);
fofb_amp0_x4: out std_logic_vector(23 downto 0);
fofb_amp0_x5: out std_logic_vector(23 downto 0);
fofb_amp0_x6: out std_logic_vector(23 downto 0);
fofb_amp0_x7: out std_logic;
fofb_amp1: out std_logic_vector(23 downto 0);
fofb_amp1_x0: out std_logic_vector(23 downto 0);
fofb_amp1_x1: out std_logic_vector(23 downto 0);
fofb_amp1_x2: out std_logic_vector(23 downto 0);
fofb_amp1_x3: out std_logic_vector(23 downto 0);
fofb_amp1_x4: out std_logic_vector(23 downto 0);
fofb_amp1_x5: out std_logic_vector(23 downto 0);
fofb_amp1_x6: out std_logic_vector(23 downto 0);
fofb_amp1_x7: out std_logic
);
end fofb_amp_entity_8b25d4b0b6;
architecture structural of fofb_amp_entity_8b25d4b0b6 is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x31: std_logic;
signal ce_1_sg_x13: std_logic;
signal ce_2240_sg_x21: std_logic;
signal ce_logic_1_sg_x11: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x4: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x5: std_logic;
signal clk_1120_sg_x31: std_logic;
signal clk_1_sg_x13: std_logic;
signal clk_2240_sg_x21: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal register3_q_net_x4: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x4: std_logic_vector(23 downto 0);
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x4: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x13 <= ce_1;
ce_1120_sg_x31 <= ce_1120;
ce_2240_sg_x21 <= ce_2240;
ce_logic_1_sg_x11 <= ce_logic_1;
register3_q_net_x4 <= ch_in0;
register3_q_net_x5 <= ch_in1;
clk_1_sg_x13 <= clk_1;
clk_1120_sg_x31 <= clk_1120;
clk_2240_sg_x21 <= clk_2240;
register4_q_net_x4 <= i_in0;
register4_q_net_x5 <= i_in1;
register5_q_net_x4 <= q_in0;
register5_q_net_x5 <= q_in1;
amp_out0 <= down_sample2_q_net_x16;
amp_out1 <= down_sample1_q_net_x16;
amp_out2 <= down_sample2_q_net_x17;
amp_out3 <= down_sample1_q_net_x17;
fofb_amp0 <= down_sample1_q_net_x18;
fofb_amp0_x0 <= down_sample2_q_net_x18;
fofb_amp0_x1 <= down_sample1_q_net_x19;
fofb_amp0_x2 <= down_sample2_q_net_x19;
fofb_amp0_x3 <= down_sample1_q_net_x20;
fofb_amp0_x4 <= down_sample2_q_net_x20;
fofb_amp0_x5 <= down_sample1_q_net_x21;
fofb_amp0_x6 <= down_sample2_q_net_x21;
fofb_amp0_x7 <= cic_fofb_q_event_tlast_missing_net_x4;
fofb_amp1 <= down_sample1_q_net_x22;
fofb_amp1_x0 <= down_sample2_q_net_x22;
fofb_amp1_x1 <= down_sample1_q_net_x23;
fofb_amp1_x2 <= down_sample2_q_net_x23;
fofb_amp1_x3 <= down_sample1_q_net_x24;
fofb_amp1_x4 <= down_sample2_q_net_x24;
fofb_amp1_x5 <= down_sample1_q_net_x25;
fofb_amp1_x6 <= down_sample2_q_net_x25;
fofb_amp1_x7 <= cic_fofb_q_event_tlast_missing_net_x5;
fofb_amp0_95b23bfc2c: entity work.fofb_amp0_entity_95b23bfc2c
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x4,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x4,
q_in => register5_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
fofb_amp => down_sample1_q_net_x20,
fofb_amp_x0 => down_sample2_q_net_x20,
fofb_amp_x1 => down_sample1_q_net_x21,
fofb_amp_x2 => down_sample2_q_net_x21,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x4,
fofb_cordic => down_sample1_q_net_x18,
fofb_cordic_x0 => down_sample2_q_net_x18,
fofb_cordic_x1 => down_sample1_q_net_x19,
fofb_cordic_x2 => down_sample2_q_net_x19
);
fofb_amp1_a049562dde: entity work.fofb_amp1_entity_a049562dde
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x5,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x5,
q_in => register5_q_net_x5,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
fofb_amp => down_sample1_q_net_x24,
fofb_amp_x0 => down_sample2_q_net_x24,
fofb_amp_x1 => down_sample1_q_net_x25,
fofb_amp_x2 => down_sample2_q_net_x25,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x5,
fofb_cordic => down_sample1_q_net_x22,
fofb_cordic_x0 => down_sample2_q_net_x22,
fofb_cordic_x1 => down_sample1_q_net_x23,
fofb_cordic_x2 => down_sample2_q_net_x23
);
tddm_fofb_amp_4ch_2cc521a83f: entity work.tddm_fofb_amp_4ch_entity_2cc521a83f
port map (
amp_in0 => assert2_dout_net_x6,
amp_in1 => assert2_dout_net_x7,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ch_in0 => assert3_dout_net_x7,
ch_in1 => assert3_dout_net_x8,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
amp_out0 => down_sample2_q_net_x16,
amp_out1 => down_sample1_q_net_x16,
amp_out2 => down_sample2_q_net_x17,
amp_out3 => down_sample1_q_net_x17
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3/Cast_truncate1"
entity cast_truncate1_entity_56731b7870 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_56731b7870;
architecture structural of cast_truncate1_entity_56731b7870 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3"
entity k_fofb_mult3_entity_697accc8e2 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_fofb_mult3_entity_697accc8e2;
architecture structural of k_fofb_mult3_entity_697accc8e2 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2240_sg_x22: std_logic;
signal ce_2_sg_x5: std_logic;
signal clk_2240_sg_x22: std_logic;
signal clk_2_sg_x5: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x5 <= ce_2;
ce_2240_sg_x22 <= ce_2240;
clk_2_sg_x5 <= clk_2;
clk_2240_sg_x22 <= clk_2240;
assert5_dout_net_x0 <= in1;
kx_i_net_x0 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_56731b7870: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x22,
clk => clk_2240_sg_x22,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x0,
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
clr => '0',
core_ce => ce_2_sg_x5,
core_clk => clk_2_sg_x5,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_1_mult"
entity k_monit_1_mult_entity_016885a3ac is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_1_mult_entity_016885a3ac;
architecture structural of k_monit_1_mult_entity_016885a3ac is
signal ce_224000000_sg_x0: std_logic;
signal ce_2_sg_x8: std_logic;
signal clk_224000000_sg_x0: std_logic;
signal clk_2_sg_x8: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool_dout_net_x0: std_logic;
begin
ce_2_sg_x8 <= ce_2;
ce_224000000_sg_x0 <= ce_224000000;
clk_2_sg_x8 <= clk_2;
clk_224000000_sg_x0 <= clk_224000000;
reinterpret3_output_port_net_x0 <= in1;
kx_i_net_x2 <= in2;
ufix_to_bool_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_fe5c8d5ea5: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x0,
clk => clk_224000000_sg_x0,
d(0) => ufix_to_bool_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret3_output_port_net_x0,
b => kx_i_net_x2,
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
clr => '0',
core_ce => ce_2_sg_x8,
core_clk => clk_2_sg_x8,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_mult3"
entity k_monit_mult3_entity_8a778fb5f4 is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_mult3_entity_8a778fb5f4;
architecture structural of k_monit_mult3_entity_8a778fb5f4 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_22400000_sg_x0: std_logic;
signal ce_2_sg_x11: std_logic;
signal clk_22400000_sg_x0: std_logic;
signal clk_2_sg_x11: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x4: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x11 <= ce_2;
ce_22400000_sg_x0 <= ce_22400000;
clk_2_sg_x11 <= clk_2;
clk_22400000_sg_x0 <= clk_22400000;
assert11_dout_net_x0 <= in1;
kx_i_net_x4 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_47fd83104e: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x0,
clk => clk_22400000_sg_x0,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => kx_i_net_x4,
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
clr => '0',
core_ce => ce_2_sg_x11,
core_clk => clk_2_sg_x11,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_tbt_mult"
entity k_tbt_mult_entity_b8fafff255 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_tbt_mult_entity_b8fafff255;
architecture structural of k_tbt_mult_entity_b8fafff255 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2_sg_x14: std_logic;
signal ce_70_sg_x0: std_logic;
signal clk_2_sg_x14: std_logic;
signal clk_70_sg_x0: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x6: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x14 <= ce_2;
ce_70_sg_x0 <= ce_70;
clk_2_sg_x14 <= clk_2;
clk_70_sg_x0 <= clk_70;
assert5_dout_net_x0 <= in1;
kx_i_net_x6 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4592ea30ee: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x0,
clk => clk_70_sg_x0,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x6,
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
clr => '0',
core_ce => ce_2_sg_x14,
core_clk => clk_2_sg_x14,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4/Cast_truncate1"
entity cast_truncate1_entity_18a9b21a64 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_18a9b21a64;
architecture structural of cast_truncate1_entity_18a9b21a64 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4"
entity ksum_fofb_mult4_entity_ac3ed97096 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_fofb_mult4_entity_ac3ed97096;
architecture structural of ksum_fofb_mult4_entity_ac3ed97096 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2240_sg_x25: std_logic;
signal ce_2_sg_x17: std_logic;
signal clk_2240_sg_x25: std_logic;
signal clk_2_sg_x17: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x17 <= ce_2;
ce_2240_sg_x25 <= ce_2240;
clk_2_sg_x17 <= clk_2;
clk_2240_sg_x25 <= clk_2240;
assert11_dout_net_x0 <= in1;
ksum_i_net_x0 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_18a9b21a64: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x25,
clk => clk_2240_sg_x25,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x0,
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
clr => '0',
core_ce => ce_2_sg_x17,
core_clk => clk_2_sg_x17,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_1_mult1"
entity ksum_monit_1_mult1_entity_c66dc07078 is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_1_mult1_entity_c66dc07078;
architecture structural of ksum_monit_1_mult1_entity_c66dc07078 is
signal ce_224000000_sg_x3: std_logic;
signal ce_2_sg_x18: std_logic;
signal clk_224000000_sg_x3: std_logic;
signal clk_2_sg_x18: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x1: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret4_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool3_dout_net_x0: std_logic;
begin
ce_2_sg_x18 <= ce_2;
ce_224000000_sg_x3 <= ce_224000000;
clk_2_sg_x18 <= clk_2;
clk_224000000_sg_x3 <= clk_224000000;
reinterpret4_output_port_net_x0 <= in1;
ksum_i_net_x1 <= in2;
ufix_to_bool3_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_92cc22397d: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x3,
clk => clk_224000000_sg_x3,
d(0) => ufix_to_bool3_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret4_output_port_net_x0,
b => ksum_i_net_x1,
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
clr => '0',
core_ce => ce_2_sg_x18,
core_clk => clk_2_sg_x18,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_mult2"
entity ksum_monit_mult2_entity_31877b6d2b is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_mult2_entity_31877b6d2b;
architecture structural of ksum_monit_mult2_entity_31877b6d2b is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_22400000_sg_x3: std_logic;
signal ce_2_sg_x19: std_logic;
signal clk_22400000_sg_x3: std_logic;
signal clk_2_sg_x19: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x19 <= ce_2;
ce_22400000_sg_x3 <= ce_22400000;
clk_2_sg_x19 <= clk_2;
clk_22400000_sg_x3 <= clk_22400000;
assert5_dout_net_x0 <= in1;
ksum_i_net_x2 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4c5b033963: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x3,
clk => clk_22400000_sg_x3,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => ksum_i_net_x2,
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
clr => '0',
core_ce => ce_2_sg_x19,
core_clk => clk_2_sg_x19,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_tbt_mult3"
entity ksum_tbt_mult3_entity_e0be30d675 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_tbt_mult3_entity_e0be30d675;
architecture structural of ksum_tbt_mult3_entity_e0be30d675 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2_sg_x20: std_logic;
signal ce_70_sg_x3: std_logic;
signal clk_2_sg_x20: std_logic;
signal clk_70_sg_x3: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x3: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x20 <= ce_2;
ce_70_sg_x3 <= ce_70;
clk_2_sg_x20 <= clk_2;
clk_70_sg_x3 <= clk_70;
assert11_dout_net_x0 <= in1;
ksum_i_net_x3 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_91bc0d396f: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x3,
clk => clk_70_sg_x3,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x3,
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
clr => '0',
core_ce => ce_2_sg_x20,
core_clk => clk_2_sg_x20,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En"
entity datareg_en_entity_5c82ef2965 is
port (
ce_2: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0);
valid: out std_logic
);
end datareg_en_entity_5c82ef2965;
architecture structural of datareg_en_entity_5c82ef2965 is
signal ce_2_sg_x21: std_logic;
signal clk_2_sg_x21: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant12_op_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2_sg_x21 <= ce_2;
clk_2_sg_x21 <= clk_2;
constant12_op_net_x0 <= din;
constant11_op_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d(0) => constant11_op_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d => constant12_op_net_x0,
en(0) => constant11_op_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En1"
entity datareg_en1_entity_8d533fde9e is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end datareg_en1_entity_8d533fde9e;
architecture structural of datareg_en1_entity_8d533fde9e is
signal ce_1_sg_x14: std_logic;
signal clk_1_sg_x14: std_logic;
signal constant11_op_net_x1: std_logic;
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_1_sg_x14 <= ce_1;
clk_1_sg_x14 <= clk_1;
register_q_net_x1 <= din;
constant11_op_net_x1 <= en;
dout <= register_q_net_x2;
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d => register_q_net_x1,
en(0) => constant11_op_net_x1,
rst => "0",
q => register_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0"
entity cmixer_0_entity_f630e8d7ec is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine: in std_logic_vector(23 downto 0);
dds_msine: in std_logic_vector(23 downto 0);
dds_valid: in std_logic;
din_i: in std_logic_vector(23 downto 0);
din_q: in std_logic_vector(23 downto 0);
en: in std_logic;
ch_out: out std_logic;
i_out: out std_logic_vector(23 downto 0);
q_out: out std_logic_vector(23 downto 0)
);
end cmixer_0_entity_f630e8d7ec;
architecture structural of cmixer_0_entity_f630e8d7ec is
signal a_i: std_logic_vector(23 downto 0);
signal a_r: std_logic_vector(23 downto 0);
signal b_i: std_logic_vector(23 downto 0);
signal b_r: std_logic_vector(23 downto 0);
signal ce_1_sg_x15: std_logic;
signal ce_2_sg_x22: std_logic;
signal clk_1_sg_x15: std_logic;
signal clk_2_sg_x22: std_logic;
signal complexmult_m_axis_dout_tdata_imag_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tuser_net: std_logic;
signal complexmult_m_axis_dout_tvalid_net: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x0: std_logic;
signal convert1_dout_net: std_logic_vector(23 downto 0);
signal convert2_dout_net: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
signal register_q_net_x8: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x15 <= ce_1;
ce_2_sg_x22 <= ce_2;
register1_q_net_x1 <= ch_in;
clk_1_sg_x15 <= clk_1;
clk_2_sg_x22 <= clk_2;
register_q_net_x6 <= dds_cosine;
register_q_net_x7 <= dds_msine;
constant15_op_net_x0 <= dds_valid;
register_q_net_x8 <= din_i;
constant12_op_net_x1 <= din_q;
constant11_op_net_x2 <= en;
ch_out <= register3_q_net_x5;
i_out <= register4_q_net_x5;
q_out <= register5_q_net_x5;
complexmult: entity work.xlcomplex_multiplier_9420c9297365b1438cc1e8469b8205e1
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
s_axis_a_tdata_imag => a_i,
s_axis_a_tdata_real => a_r,
s_axis_a_tvalid => constant15_op_net_x0,
s_axis_b_tdata_imag => b_i,
s_axis_b_tdata_real => b_r,
s_axis_b_tuser(0) => register_q_net,
s_axis_b_tvalid => register1_q_net_x0,
m_axis_dout_tdata_imag => complexmult_m_axis_dout_tdata_imag_net,
m_axis_dout_tdata_real => complexmult_m_axis_dout_tdata_real_net,
m_axis_dout_tuser(0) => complexmult_m_axis_dout_tuser_net,
m_axis_dout_tvalid => complexmult_m_axis_dout_tvalid_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret1_output_port_net,
en => "1",
dout => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert2_dout_net
);
datareg_en1_8d533fde9e: entity work.datareg_en1_entity_8d533fde9e
port map (
ce_1 => ce_1_sg_x15,
clk_1 => clk_1_sg_x15,
din => register_q_net_x8,
en => constant11_op_net_x2,
dout => register_q_net_x2
);
datareg_en_5c82ef2965: entity work.datareg_en_entity_5c82ef2965
port map (
ce_2 => ce_2_sg_x22,
clk_2 => clk_2_sg_x22,
din => constant12_op_net_x1,
en => constant11_op_net_x2,
dout => register_q_net_x0,
valid => register1_q_net_x0
);
delay: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x0,
q => b_i
);
delay1: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x2,
q => b_r
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x6,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_r
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x7,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_i
);
register3: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => complexmult_m_axis_dout_tuser_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register3_q_net_x5
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert1_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net_x5
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert2_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net_x5
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => register1_q_net_x1,
en(0) => constant11_op_net_x2,
rst => "0",
q(0) => register_q_net
);
reinterpret: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_imag_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_real_net,
output_port => reinterpret1_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer/TDDM_Mixer0_i"
entity tddm_mixer0_i_entity_f95b8f24ad is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_mixer0_i_entity_f95b8f24ad;
architecture structural of tddm_mixer0_i_entity_f95b8f24ad is
signal ce_1_sg_x18: std_logic;
signal ce_2_sg_x25: std_logic;
signal clk_1_sg_x18: std_logic;
signal clk_2_sg_x25: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register3_q_net_x6: std_logic;
signal register4_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x18 <= ce_1;
ce_2_sg_x25 <= ce_2;
register3_q_net_x6 <= ch_in;
clk_1_sg_x18 <= clk_1;
clk_2_sg_x25 <= clk_2;
register4_q_net_x6 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register3_q_net_x6,
b(0) => constant_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x6,
b => constant1_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer"
entity tddm_mixer_entity_8537ade7b6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
mix0_ch_in: in std_logic;
mix0_i_in: in std_logic_vector(23 downto 0);
mix0_q_in: in std_logic_vector(23 downto 0);
mix1_ch_in: in std_logic;
mix1_i_in: in std_logic_vector(23 downto 0);
mix1_q_in: in std_logic_vector(23 downto 0);
mix_ch0_i_out: out std_logic_vector(23 downto 0);
mix_ch0_q_out: out std_logic_vector(23 downto 0);
mix_ch1_i_out: out std_logic_vector(23 downto 0);
mix_ch1_q_out: out std_logic_vector(23 downto 0);
mix_ch2_i_out: out std_logic_vector(23 downto 0);
mix_ch2_q_out: out std_logic_vector(23 downto 0);
mix_ch3_i_out: out std_logic_vector(23 downto 0);
mix_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_mixer_entity_8537ade7b6;
architecture structural of tddm_mixer_entity_8537ade7b6 is
signal ce_1_sg_x22: std_logic;
signal ce_2_sg_x29: std_logic;
signal clk_1_sg_x22: std_logic;
signal clk_2_sg_x29: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x7: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x7: std_logic_vector(23 downto 0);
signal register3_q_net_x10: std_logic;
signal register3_q_net_x9: std_logic;
signal register4_q_net_x8: std_logic_vector(23 downto 0);
signal register4_q_net_x9: std_logic_vector(23 downto 0);
signal register5_q_net_x8: std_logic_vector(23 downto 0);
signal register5_q_net_x9: std_logic_vector(23 downto 0);
begin
ce_1_sg_x22 <= ce_1;
ce_2_sg_x29 <= ce_2;
clk_1_sg_x22 <= clk_1;
clk_2_sg_x29 <= clk_2;
register3_q_net_x9 <= mix0_ch_in;
register4_q_net_x8 <= mix0_i_in;
register5_q_net_x8 <= mix0_q_in;
register3_q_net_x10 <= mix1_ch_in;
register4_q_net_x9 <= mix1_i_in;
register5_q_net_x9 <= mix1_q_in;
mix_ch0_i_out <= down_sample2_q_net_x4;
mix_ch0_q_out <= down_sample2_q_net_x5;
mix_ch1_i_out <= down_sample1_q_net_x4;
mix_ch1_q_out <= down_sample1_q_net_x5;
mix_ch2_i_out <= down_sample2_q_net_x6;
mix_ch2_q_out <= down_sample2_q_net_x7;
mix_ch3_i_out <= down_sample1_q_net_x6;
mix_ch3_q_out <= down_sample1_q_net_x7;
tddm_mixer0_i_f95b8f24ad: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x8,
dout_ch0 => down_sample2_q_net_x4,
dout_ch1 => down_sample1_q_net_x4
);
tddm_mixer0_q_2c5e18f496: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x8,
dout_ch0 => down_sample2_q_net_x5,
dout_ch1 => down_sample1_q_net_x5
);
tddm_mixer1_i_1afc4ccdba: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x9,
dout_ch0 => down_sample2_q_net_x6,
dout_ch1 => down_sample1_q_net_x6
);
tddm_mixer1_q_ee4acbed30: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x9,
dout_ch0 => down_sample2_q_net_x7,
dout_ch1 => down_sample1_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer"
entity mixer_entity_a1cd828545 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine_0: in std_logic_vector(23 downto 0);
dds_cosine_1: in std_logic_vector(23 downto 0);
dds_msine_0: in std_logic_vector(23 downto 0);
dds_msine_1: in std_logic_vector(23 downto 0);
dds_valid_0: in std_logic;
dds_valid_1: in std_logic;
din0: in std_logic_vector(23 downto 0);
din1: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
i_out0: out std_logic_vector(23 downto 0);
i_out1: out std_logic_vector(23 downto 0);
q_out0: out std_logic_vector(23 downto 0);
q_out1: out std_logic_vector(23 downto 0);
tddm_mixer: out std_logic_vector(23 downto 0);
tddm_mixer_x0: out std_logic_vector(23 downto 0);
tddm_mixer_x1: out std_logic_vector(23 downto 0);
tddm_mixer_x2: out std_logic_vector(23 downto 0);
tddm_mixer_x3: out std_logic_vector(23 downto 0);
tddm_mixer_x4: out std_logic_vector(23 downto 0);
tddm_mixer_x5: out std_logic_vector(23 downto 0);
tddm_mixer_x6: out std_logic_vector(23 downto 0)
);
end mixer_entity_a1cd828545;
architecture structural of mixer_entity_a1cd828545 is
signal ce_1_sg_x23: std_logic;
signal ce_2_sg_x30: std_logic;
signal clk_1_sg_x23: std_logic;
signal clk_2_sg_x30: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x1: std_logic;
signal constant1_op_net_x2: std_logic;
signal constant2_op_net_x1: std_logic_vector(23 downto 0);
signal constant3_op_net_x1: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register3_q_net_x11: std_logic;
signal register3_q_net_x12: std_logic;
signal register4_q_net_x10: std_logic_vector(23 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x10: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x16: std_logic_vector(23 downto 0);
signal register_q_net_x17: std_logic_vector(23 downto 0);
begin
ce_1_sg_x23 <= ce_1;
ce_2_sg_x30 <= ce_2;
register1_q_net_x3 <= ch_in0;
register1_q_net_x4 <= ch_in1;
clk_1_sg_x23 <= clk_1;
clk_2_sg_x30 <= clk_2;
register_q_net_x12 <= dds_cosine_0;
register_q_net_x14 <= dds_cosine_1;
register_q_net_x13 <= dds_msine_0;
register_q_net_x15 <= dds_msine_1;
constant15_op_net_x1 <= dds_valid_0;
constant3_op_net_x1 <= dds_valid_1;
register_q_net_x16 <= din0;
register_q_net_x17 <= din1;
ch_out0 <= register3_q_net_x11;
ch_out1 <= register3_q_net_x12;
i_out0 <= register4_q_net_x10;
i_out1 <= register4_q_net_x11;
q_out0 <= register5_q_net_x10;
q_out1 <= register5_q_net_x11;
tddm_mixer <= down_sample1_q_net_x8;
tddm_mixer_x0 <= down_sample2_q_net_x8;
tddm_mixer_x1 <= down_sample1_q_net_x9;
tddm_mixer_x2 <= down_sample2_q_net_x9;
tddm_mixer_x3 <= down_sample1_q_net_x10;
tddm_mixer_x4 <= down_sample2_q_net_x10;
tddm_mixer_x5 <= down_sample1_q_net_x11;
tddm_mixer_x6 <= down_sample2_q_net_x11;
cmixer_0_f630e8d7ec: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x3,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x12,
dds_msine => register_q_net_x13,
dds_valid => constant15_op_net_x1,
din_i => register_q_net_x16,
din_q => constant12_op_net_x1,
en => constant11_op_net_x2,
ch_out => register3_q_net_x11,
i_out => register4_q_net_x10,
q_out => register5_q_net_x10
);
cmixer_1_61bfc18f90: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x4,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x14,
dds_msine => register_q_net_x15,
dds_valid => constant3_op_net_x1,
din_i => register_q_net_x17,
din_q => constant2_op_net_x1,
en => constant1_op_net_x2,
ch_out => register3_q_net_x12,
i_out => register4_q_net_x11,
q_out => register5_q_net_x11
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x2
);
constant11: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x2
);
constant12: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant12_op_net_x1
);
constant2: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net_x1
);
tddm_mixer_8537ade7b6: entity work.tddm_mixer_entity_8537ade7b6
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
mix0_ch_in => register3_q_net_x11,
mix0_i_in => register4_q_net_x10,
mix0_q_in => register5_q_net_x10,
mix1_ch_in => register3_q_net_x12,
mix1_i_in => register4_q_net_x11,
mix1_q_in => register5_q_net_x11,
mix_ch0_i_out => down_sample2_q_net_x8,
mix_ch0_q_out => down_sample2_q_net_x9,
mix_ch1_i_out => down_sample1_q_net_x8,
mix_ch1_q_out => down_sample1_q_net_x9,
mix_ch2_i_out => down_sample2_q_net_x10,
mix_ch2_q_out => down_sample2_q_net_x11,
mix_ch3_i_out => down_sample1_q_net_x10,
mix_ch3_q_out => down_sample1_q_net_x11
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2/format1"
entity format1_entity_4e0a69646b is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_4e0a69646b;
architecture structural of format1_entity_4e0a69646b is
signal ce_5600000_sg_x0: std_logic;
signal clk_5600000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_5600000_sg_x0 <= ce_5600000;
clk_5600000_sg_x0 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_5600000_sg_x0,
clk => clk_5600000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2"
entity cast2_entity_4b7421c7c9 is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast2_entity_4b7421c7c9;
architecture structural of cast2_entity_4b7421c7c9 is
signal ce_5600000_sg_x1: std_logic;
signal clk_5600000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_5600000_sg_x1 <= ce_5600000;
clk_5600000_sg_x1 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x1 <= data_in;
monit_pfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_4e0a69646b: entity work.format1_entity_4e0a69646b
port map (
ce_5600000 => ce_5600000_sg_x1,
clk_5600000 => clk_5600000_sg_x1,
din => monit_pfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x1,
clk => clk_5600000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4/format1"
entity format1_entity_3cf61b0d44 is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_3cf61b0d44;
architecture structural of format1_entity_3cf61b0d44 is
signal ce_2800000_sg_x0: std_logic;
signal clk_2800000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_2800000_sg_x0 <= ce_2800000;
clk_2800000_sg_x0 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_2800000_sg_x0,
clk => clk_2800000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4"
entity cast4_entity_4ed908d7fc is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast4_entity_4ed908d7fc;
architecture structural of cast4_entity_4ed908d7fc is
signal ce_2800000_sg_x1: std_logic;
signal clk_2800000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2800000_sg_x1 <= ce_2800000;
clk_2800000_sg_x1 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x1 <= data_in;
monit_cfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_3cf61b0d44: entity work.format1_entity_3cf61b0d44
port map (
ce_2800000 => ce_2800000_sg_x1,
clk_2800000 => clk_2800000_sg_x1,
din => monit_cfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2800000_sg_x1,
clk => clk_2800000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_cfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Reg1"
entity reg1_entity_8661a44192 is
port (
ce_1400000: in std_logic;
clk_1400000: in std_logic;
din: in std_logic_vector(60 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end reg1_entity_8661a44192;
architecture structural of reg1_entity_8661a44192 is
signal ce_1400000_sg_x0: std_logic;
signal clk_1400000_sg_x0: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(60 downto 0);
begin
ce_1400000_sg_x0 <= ce_1400000;
clk_1400000_sg_x0 <= clk_1400000;
monit_cic_m_axis_data_tdata_data_net_x0 <= din;
monit_cic_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 59,
din_width => 61,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
d => convert_dout_net,
en(0) => monit_cic_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_c88e29aa6b
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cic_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c/TDDM_monit_amp_c_int"
entity tddm_monit_amp_c_int_entity_554a834349 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_22400000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_int_entity_554a834349;
architecture structural of tddm_monit_amp_c_int_entity_554a834349 is
signal ce_22400000_sg_x4: std_logic;
signal ce_5600000_sg_x2: std_logic;
signal clk_22400000_sg_x4: std_logic;
signal clk_5600000_sg_x2: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal delay2_q_net_x0: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_22400000_sg_x4 <= ce_22400000;
ce_5600000_sg_x2 <= ce_5600000;
delay2_q_net_x0 <= ch_in;
clk_22400000_sg_x4 <= clk_22400000;
clk_5600000_sg_x2 <= clk_5600000;
register_q_net_x1 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register2_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register3_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant1_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant3_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant4_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c"
entity tddm_monit_amp_c_entity_5b2613eff7 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_ch_in: in std_logic_vector(1 downto 0);
monit_din: in std_logic_vector(23 downto 0);
monit_ch0_out: out std_logic_vector(23 downto 0);
monit_ch1_out: out std_logic_vector(23 downto 0);
monit_ch2_out: out std_logic_vector(23 downto 0);
monit_ch3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_entity_5b2613eff7;
architecture structural of tddm_monit_amp_c_entity_5b2613eff7 is
signal ce_22400000_sg_x5: std_logic;
signal ce_5600000_sg_x3: std_logic;
signal clk_22400000_sg_x5: std_logic;
signal clk_5600000_sg_x3: std_logic;
signal delay2_q_net_x1: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x5 <= ce_22400000;
ce_5600000_sg_x3 <= ce_5600000;
clk_22400000_sg_x5 <= clk_22400000;
clk_5600000_sg_x3 <= clk_5600000;
delay2_q_net_x1 <= monit_ch_in;
register_q_net_x2 <= monit_din;
monit_ch0_out <= down_sample2_q_net_x1;
monit_ch1_out <= down_sample1_q_net_x1;
monit_ch2_out <= down_sample3_q_net_x1;
monit_ch3_out <= down_sample4_q_net_x1;
tddm_monit_amp_c_int_554a834349: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x5,
ce_5600000 => ce_5600000_sg_x3,
ch_in => delay2_q_net_x1,
clk_22400000 => clk_22400000_sg_x5,
clk_5600000 => clk_5600000_sg_x3,
din => register_q_net_x2,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c"
entity monit_amp_c_entity_c83793ea71 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out_x1: out std_logic_vector(1 downto 0);
monit_cfir_x0: out std_logic;
monit_cic_x0: out std_logic;
monit_pfir_x0: out std_logic;
tddm_monit_amp_c: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x0: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x1: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x2: out std_logic_vector(23 downto 0)
);
end monit_amp_c_entity_c83793ea71;
architecture structural of monit_amp_c_entity_c83793ea71 is
signal ce_1400000_sg_x1: std_logic;
signal ce_1_sg_x24: std_logic;
signal ce_22400000_sg_x6: std_logic;
signal ce_2800000_sg_x2: std_logic;
signal ce_5600000_sg_x4: std_logic;
signal ce_560_sg_x0: std_logic;
signal ce_logic_1400000_sg_x0: std_logic;
signal ce_logic_2800000_sg_x0: std_logic;
signal ce_logic_560_sg_x0: std_logic;
signal ch_out_x0: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x1: std_logic;
signal clk_1_sg_x24: std_logic;
signal clk_22400000_sg_x6: std_logic;
signal clk_2800000_sg_x2: std_logic;
signal clk_5600000_sg_x4: std_logic;
signal clk_560_sg_x0: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay1_q_net: std_logic_vector(23 downto 0);
signal delay2_q_net_x2: std_logic_vector(1 downto 0);
signal delay3_q_net: std_logic_vector(23 downto 0);
signal delay_q_net: std_logic_vector(1 downto 0);
signal dout_x0: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x2: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal monit_cic_event_tlast_unexpected_net_x0: std_logic;
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tuser_chan_out_net: std_logic_vector(1 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register3_q_net: std_logic_vector(1 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x24 <= ce_1;
ce_1400000_sg_x1 <= ce_1400000;
ce_22400000_sg_x6 <= ce_22400000;
ce_2800000_sg_x2 <= ce_2800000;
ce_560_sg_x0 <= ce_560;
ce_5600000_sg_x4 <= ce_5600000;
ce_logic_1400000_sg_x0 <= ce_logic_1400000;
ce_logic_2800000_sg_x0 <= ce_logic_2800000;
ce_logic_560_sg_x0 <= ce_logic_560;
ch_out_x0 <= ch_in;
clk_1_sg_x24 <= clk_1;
clk_1400000_sg_x1 <= clk_1400000;
clk_22400000_sg_x6 <= clk_22400000;
clk_2800000_sg_x2 <= clk_2800000;
clk_560_sg_x0 <= clk_560;
clk_5600000_sg_x4 <= clk_5600000;
dout_x0 <= din;
amp_out <= register_q_net_x3;
ch_out_x1 <= delay2_q_net_x2;
monit_cfir_x0 <= monit_cfir_event_s_data_chanid_incorrect_net_x0;
monit_cic_x0 <= monit_cic_event_tlast_unexpected_net_x0;
monit_pfir_x0 <= monit_pfir_event_s_data_chanid_incorrect_net_x0;
tddm_monit_amp_c <= down_sample1_q_net_x2;
tddm_monit_amp_c_x0 <= down_sample2_q_net_x2;
tddm_monit_amp_c_x1 <= down_sample3_q_net_x2;
tddm_monit_amp_c_x2 <= down_sample4_q_net_x2;
cast2_4b7421c7c9: entity work.cast2_entity_4b7421c7c9
port map (
ce_5600000 => ce_5600000_sg_x4,
clk_5600000 => clk_5600000_sg_x4,
data_in => monit_pfir_m_axis_data_tdata_net_x1,
en => monit_pfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x3
);
cast4_4ed908d7fc: entity work.cast4_entity_4ed908d7fc
port map (
ce_2800000 => ce_2800000_sg_x2,
clk_2800000 => clk_2800000_sg_x2,
data_in => monit_cfir_m_axis_data_tdata_net_x1,
en => monit_cfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0
);
constant1: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => monit_cic_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
d => dout_x0,
en => '1',
rst => '1',
q => delay1_q_net
);
delay2: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_5600000_sg_x4,
clk => clk_5600000_sg_x4,
d => monit_pfir_m_axis_data_tuser_chanid_net,
en => '1',
rst => '1',
q => delay2_q_net_x2
);
delay3: entity work.xldelay
generic map (
latency => 2,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => register_q_net_x1,
en => '1',
rst => '1',
q => delay3_q_net
);
monit_cfir: entity work.xlfir_compiler_9c8746ef58b9fecaf8fa2bea81370554
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_2800000 => ce_2800000_sg_x2,
ce_logic_1400000 => ce_logic_1400000_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_2800000 => clk_2800000_sg_x2,
clk_logic_1400000 => clk_1400000_sg_x1,
s_axis_data_tdata => delay3_q_net,
s_axis_data_tuser_chanid => delay_q_net,
src_ce => ce_1400000_sg_x1,
src_clk => clk_1400000_sg_x1,
event_s_data_chanid_incorrect => monit_cfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_cfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_cfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_cfir_m_axis_data_tvalid_net_x0
);
monit_cic: entity work.xlcic_compiler_1c97a249b004729f66738a648c4f9593
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_560 => ce_560_sg_x0,
ce_logic_560 => ce_logic_560_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_560 => clk_560_sg_x0,
clk_logic_560 => clk_560_sg_x0,
s_axis_data_tdata_data => delay1_q_net,
s_axis_data_tlast => relational2_op_net,
event_tlast_unexpected => monit_cic_event_tlast_unexpected_net_x0,
m_axis_data_tdata_data => monit_cic_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out => monit_cic_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => monit_cic_m_axis_data_tvalid_net_x0
);
monit_pfir: entity work.xlfir_compiler_ef89cacae87a636bad21e5ee1476453a
port map (
ce => ce_1_sg_x24,
ce_2800000 => ce_2800000_sg_x2,
ce_5600000 => ce_5600000_sg_x4,
ce_logic_2800000 => ce_logic_2800000_sg_x0,
clk => clk_1_sg_x24,
clk_2800000 => clk_2800000_sg_x2,
clk_5600000 => clk_5600000_sg_x4,
clk_logic_2800000 => clk_2800000_sg_x2,
s_axis_data_tdata => register_q_net_x0,
s_axis_data_tuser_chanid => register3_q_net,
src_ce => ce_2800000_sg_x2,
src_clk => clk_2800000_sg_x2,
event_s_data_chanid_incorrect => monit_pfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pfir_m_axis_data_tvalid_net_x0
);
reg1_8661a44192: entity work.reg1_entity_8661a44192
port map (
ce_1400000 => ce_1400000_sg_x1,
clk_1400000 => clk_1400000_sg_x1,
din => monit_cic_m_axis_data_tdata_data_net_x0,
en => monit_cic_m_axis_data_tvalid_net_x0,
dout => register_q_net_x1
);
register3: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_2800000_sg_x2,
clk => clk_2800000_sg_x2,
d => monit_cfir_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register3_q_net
);
relational2: entity work.relational_83ca2c6a3c
port map (
a => ch_out_x0,
b => constant1_op_net,
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
clr => '0',
op(0) => relational2_op_net
);
tddm_monit_amp_c_5b2613eff7: entity work.tddm_monit_amp_c_entity_5b2613eff7
port map (
ce_22400000 => ce_22400000_sg_x6,
ce_5600000 => ce_5600000_sg_x4,
clk_22400000 => clk_22400000_sg_x6,
clk_5600000 => clk_5600000_sg_x4,
monit_ch_in => delay2_q_net_x2,
monit_din => register_q_net_x3,
monit_ch0_out => down_sample2_q_net_x2,
monit_ch1_out => down_sample1_q_net_x2,
monit_ch2_out => down_sample3_q_net_x2,
monit_ch3_out => down_sample4_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/TDDM_monit_amp_out"
entity tddm_monit_amp_out_entity_521eb373cc is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_amp_ch_in: in std_logic_vector(1 downto 0);
monit_amp_din: in std_logic_vector(23 downto 0);
monit_amp_data0_out: out std_logic_vector(23 downto 0);
monit_amp_data1_out: out std_logic_vector(23 downto 0);
monit_amp_data2_out: out std_logic_vector(23 downto 0);
monit_amp_data3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_out_entity_521eb373cc;
architecture structural of tddm_monit_amp_out_entity_521eb373cc is
signal ce_22400000_sg_x8: std_logic;
signal ce_5600000_sg_x6: std_logic;
signal clk_22400000_sg_x8: std_logic;
signal clk_5600000_sg_x6: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x8 <= ce_22400000;
ce_5600000_sg_x6 <= ce_5600000;
clk_22400000_sg_x8 <= clk_22400000;
clk_5600000_sg_x6 <= clk_5600000;
delay2_q_net_x4 <= monit_amp_ch_in;
register_q_net_x5 <= monit_amp_din;
monit_amp_data0_out <= down_sample2_q_net_x1;
monit_amp_data1_out <= down_sample1_q_net_x1;
monit_amp_data2_out <= down_sample3_q_net_x1;
monit_amp_data3_out <= down_sample4_q_net_x1;
tddm_monit_amp_out_int_b60196c7a6: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x8,
ce_5600000 => ce_5600000_sg_x6,
ch_in => delay2_q_net_x4,
clk_22400000 => clk_22400000_sg_x8,
clk_5600000 => clk_5600000_sg_x6,
din => register_q_net_x5,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp"
entity monit_amp_entity_44da74e268 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
monit_amp_c: out std_logic_vector(23 downto 0);
monit_amp_c_x0: out std_logic_vector(23 downto 0);
monit_amp_c_x1: out std_logic_vector(23 downto 0);
monit_amp_c_x2: out std_logic_vector(23 downto 0);
monit_amp_c_x3: out std_logic;
monit_amp_c_x4: out std_logic;
monit_amp_c_x5: out std_logic
);
end monit_amp_entity_44da74e268;
architecture structural of monit_amp_entity_44da74e268 is
signal ce_1400000_sg_x2: std_logic;
signal ce_1_sg_x25: std_logic;
signal ce_22400000_sg_x9: std_logic;
signal ce_2800000_sg_x3: std_logic;
signal ce_5600000_sg_x7: std_logic;
signal ce_560_sg_x1: std_logic;
signal ce_logic_1400000_sg_x1: std_logic;
signal ce_logic_2800000_sg_x1: std_logic;
signal ce_logic_560_sg_x1: std_logic;
signal ch_out_x1: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x2: std_logic;
signal clk_1_sg_x25: std_logic;
signal clk_22400000_sg_x9: std_logic;
signal clk_2800000_sg_x3: std_logic;
signal clk_5600000_sg_x7: std_logic;
signal clk_560_sg_x1: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal dout_x1: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x4: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal monit_cic_event_tlast_unexpected_net_x1: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x25 <= ce_1;
ce_1400000_sg_x2 <= ce_1400000;
ce_22400000_sg_x9 <= ce_22400000;
ce_2800000_sg_x3 <= ce_2800000;
ce_560_sg_x1 <= ce_560;
ce_5600000_sg_x7 <= ce_5600000;
ce_logic_1400000_sg_x1 <= ce_logic_1400000;
ce_logic_2800000_sg_x1 <= ce_logic_2800000;
ce_logic_560_sg_x1 <= ce_logic_560;
ch_out_x1 <= ch_in;
clk_1_sg_x25 <= clk_1;
clk_1400000_sg_x2 <= clk_1400000;
clk_22400000_sg_x9 <= clk_22400000;
clk_2800000_sg_x3 <= clk_2800000;
clk_560_sg_x1 <= clk_560;
clk_5600000_sg_x7 <= clk_5600000;
dout_x1 <= din;
amp_out0 <= down_sample2_q_net_x4;
amp_out1 <= down_sample1_q_net_x4;
amp_out2 <= down_sample3_q_net_x4;
amp_out3 <= down_sample4_q_net_x4;
monit_amp_c <= down_sample1_q_net_x3;
monit_amp_c_x0 <= down_sample2_q_net_x3;
monit_amp_c_x1 <= down_sample3_q_net_x3;
monit_amp_c_x2 <= down_sample4_q_net_x3;
monit_amp_c_x3 <= monit_cfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_x4 <= monit_cic_event_tlast_unexpected_net_x1;
monit_amp_c_x5 <= monit_pfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_c83793ea71: entity work.monit_amp_c_entity_c83793ea71
port map (
ce_1 => ce_1_sg_x25,
ce_1400000 => ce_1400000_sg_x2,
ce_22400000 => ce_22400000_sg_x9,
ce_2800000 => ce_2800000_sg_x3,
ce_560 => ce_560_sg_x1,
ce_5600000 => ce_5600000_sg_x7,
ce_logic_1400000 => ce_logic_1400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x1,
ce_logic_560 => ce_logic_560_sg_x1,
ch_in => ch_out_x1,
clk_1 => clk_1_sg_x25,
clk_1400000 => clk_1400000_sg_x2,
clk_22400000 => clk_22400000_sg_x9,
clk_2800000 => clk_2800000_sg_x3,
clk_560 => clk_560_sg_x1,
clk_5600000 => clk_5600000_sg_x7,
din => dout_x1,
amp_out => register_q_net_x5,
ch_out_x1 => delay2_q_net_x4,
monit_cfir_x0 => monit_cfir_event_s_data_chanid_incorrect_net_x1,
monit_cic_x0 => monit_cic_event_tlast_unexpected_net_x1,
monit_pfir_x0 => monit_pfir_event_s_data_chanid_incorrect_net_x1,
tddm_monit_amp_c => down_sample1_q_net_x3,
tddm_monit_amp_c_x0 => down_sample2_q_net_x3,
tddm_monit_amp_c_x1 => down_sample3_q_net_x3,
tddm_monit_amp_c_x2 => down_sample4_q_net_x3
);
tddm_monit_amp_out_521eb373cc: entity work.tddm_monit_amp_out_entity_521eb373cc
port map (
ce_22400000 => ce_22400000_sg_x9,
ce_5600000 => ce_5600000_sg_x7,
clk_22400000 => clk_22400000_sg_x9,
clk_5600000 => clk_5600000_sg_x7,
monit_amp_ch_in => delay2_q_net_x4,
monit_amp_din => register_q_net_x5,
monit_amp_data0_out => down_sample2_q_net_x4,
monit_amp_data1_out => down_sample1_q_net_x4,
monit_amp_data2_out => down_sample3_q_net_x4,
monit_amp_data3_out => down_sample4_q_net_x4
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_5b94be40c5 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_5b94be40c5;
architecture structural of tddm_tbt_cordic_entity_5b94be40c5 is
signal ce_35_sg_x0: std_logic;
signal ce_70_sg_x4: std_logic;
signal clk_35_sg_x0: std_logic;
signal clk_70_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_amp_out_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x0: std_logic;
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x0 <= ce_35;
ce_70_sg_x4 <= ce_70;
p_ch_out_x0 <= ch_in;
clk_35_sg_x0 <= clk_35;
clk_70_sg_x4 <= clk_70;
p_amp_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant1_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_d3f44a687c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_d3f44a687c;
architecture structural of tddm_tbt_cordic1_entity_d3f44a687c is
signal ce_35_sg_x1: std_logic;
signal ce_70_sg_x5: std_logic;
signal clk_35_sg_x1: std_logic;
signal clk_70_sg_x5: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x1: std_logic;
signal p_phase_out_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x1 <= ce_35;
ce_70_sg_x5 <= ce_70;
p_ch_out_x1 <= ch_in;
clk_35_sg_x1 <= clk_35;
clk_70_sg_x5 <= clk_70;
p_phase_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant1_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_18d3979a26 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_data0_out: out std_logic_vector(23 downto 0);
tbt_cordic_data1_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_18d3979a26;
architecture structural of tddm_tbt_cordic_entity_18d3979a26 is
signal ce_35_sg_x2: std_logic;
signal ce_70_sg_x6: std_logic;
signal clk_35_sg_x2: std_logic;
signal clk_70_sg_x6: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x2 <= ce_35;
ce_70_sg_x6 <= ce_70;
clk_35_sg_x2 <= clk_35;
clk_70_sg_x6 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_data0_out <= down_sample2_q_net_x2;
tbt_cordic_data1_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d3f44a687c: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_5b94be40c5: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC"
entity tbt_cordic_entity_232cb2e43e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_232cb2e43e;
architecture structural of tbt_cordic_entity_232cb2e43e is
signal ce_1_sg_x26: std_logic;
signal ce_35_sg_x3: std_logic;
signal ce_70_sg_x7: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x26: std_logic;
signal clk_35_sg_x3: std_logic;
signal clk_70_sg_x7: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x26 <= ce_1;
ce_35_sg_x3 <= ce_35;
ce_70_sg_x7 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x26 <= clk_1;
clk_35_sg_x3 <= clk_35;
clk_70_sg_x7 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_1700ad0af26476326977e0830172a2c4
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_18d3979a26: entity work.tddm_tbt_cordic_entity_18d3979a26
port map (
ce_35 => ce_35_sg_x3,
ce_70 => ce_70_sg_x7,
clk_35 => clk_35_sg_x3,
clk_70 => clk_70_sg_x7,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_data0_out => down_sample2_q_net_x4,
tbt_cordic_data1_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT/TDDM_tbt_poly_i"
entity tddm_tbt_poly_i_entity_469601736c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_poly_i_entity_469601736c;
architecture structural of tddm_tbt_poly_i_entity_469601736c is
signal ce_35_sg_x4: std_logic;
signal ce_70_sg_x8: std_logic;
signal clk_35_sg_x4: std_logic;
signal clk_70_sg_x8: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net_x1: std_logic;
signal register_q_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x4 <= ce_35;
ce_70_sg_x8 <= ce_70;
register2_q_net_x1 <= ch_in;
clk_35_sg_x4 <= clk_35;
clk_70_sg_x8 <= clk_70;
reinterpret_output_port_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register2_q_net_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register2_q_net_x1,
b => constant1_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_9ac9f65b0b is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch0_i_out: out std_logic_vector(23 downto 0);
poly35_ch0_q_out: out std_logic_vector(23 downto 0);
poly35_ch1_i_out: out std_logic_vector(23 downto 0);
poly35_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_9ac9f65b0b;
architecture structural of tddm_tbt_entity_9ac9f65b0b is
signal ce_35_sg_x6: std_logic;
signal ce_70_sg_x10: std_logic;
signal clk_35_sg_x6: std_logic;
signal clk_70_sg_x10: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x6 <= ce_35;
ce_70_sg_x10 <= ce_70;
clk_35_sg_x6 <= clk_35;
clk_70_sg_x10 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch0_i_out <= down_sample2_q_net_x2;
poly35_ch0_q_out <= down_sample2_q_net_x3;
poly35_ch1_i_out <= down_sample1_q_net_x2;
poly35_ch1_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_469601736c: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_8011b4e29e: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/Trunc"
entity trunc_entity_e5eda8a5ac is
port (
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end trunc_entity_e5eda8a5ac;
architecture structural of trunc_entity_e5eda8a5ac is
signal register1_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal slice_y_net: std_logic_vector(23 downto 0);
begin
register1_q_net_x2 <= din;
dout <= reinterpret_output_port_net_x3;
reinterpret: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x3
);
slice: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 24,
x_width => 25,
y_width => 24
)
port map (
x => register1_q_net_x2,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim"
entity tbt_poly_decim_entity_4477ec06c2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_4477ec06c2;
architecture structural of tbt_poly_decim_entity_4477ec06c2 is
signal ce_1_sg_x27: std_logic;
signal ce_35_sg_x7: std_logic;
signal ce_70_sg_x11: std_logic;
signal ce_logic_1_sg_x12: std_logic;
signal clk_1_sg_x27: std_logic;
signal clk_35_sg_x7: std_logic;
signal clk_70_sg_x11: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x12: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x27 <= ce_1;
ce_35_sg_x7 <= ce_35;
ce_70_sg_x11 <= ce_70;
ce_logic_1_sg_x12 <= ce_logic_1;
register3_q_net_x12 <= ch_in;
clk_1_sg_x27 <= clk_1;
clk_35_sg_x7 <= clk_35;
clk_70_sg_x11 <= clk_70;
register4_q_net_x11 <= i_in;
register5_q_net_x11 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_516bd78992d05073446d2f0e193ec7f1
port map (
ce => ce_1_sg_x27,
ce_35 => ce_35_sg_x7,
ce_logic_1 => ce_logic_1_sg_x12,
clk => clk_1_sg_x27,
clk_35 => clk_35_sg_x7,
clk_logic_1 => clk_1_sg_x27,
s_axis_data_tdata_path0 => register4_q_net_x11,
s_axis_data_tdata_path1 => register5_q_net_x11,
s_axis_data_tuser_chanid(0) => register3_q_net_x12,
src_ce => ce_1_sg_x27,
src_clk => clk_1_sg_x27,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_9ac9f65b0b: entity work.tddm_tbt_entity_9ac9f65b0b
port map (
ce_35 => ce_35_sg_x7,
ce_70 => ce_70_sg_x11,
clk_35 => clk_35_sg_x7,
clk_70 => clk_70_sg_x11,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch0_i_out => down_sample2_q_net_x4,
poly35_ch0_q_out => down_sample2_q_net_x5,
poly35_ch1_i_out => down_sample1_q_net_x4,
poly35_ch1_q_out => down_sample1_q_net_x5
);
trunc1_841a61ebcc: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_e5eda8a5ac: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0"
entity tbt_amp0_entity_88b1c45f0e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp0_entity_88b1c45f0e;
architecture structural of tbt_amp0_entity_88b1c45f0e is
signal ce_1_sg_x28: std_logic;
signal ce_35_sg_x8: std_logic;
signal ce_70_sg_x12: std_logic;
signal ce_logic_1_sg_x13: std_logic;
signal clk_1_sg_x28: std_logic;
signal clk_35_sg_x8: std_logic;
signal clk_70_sg_x12: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x28 <= ce_1;
ce_35_sg_x8 <= ce_35;
ce_70_sg_x12 <= ce_70;
ce_logic_1_sg_x13 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x28 <= clk_1;
clk_35_sg_x8 <= clk_35;
clk_70_sg_x12 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_232cb2e43e: entity work.tbt_cordic_entity_232cb2e43e
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_4477ec06c2: entity work.tbt_poly_decim_entity_4477ec06c2
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ce_logic_1 => ce_logic_1_sg_x13,
ch_in => register3_q_net_x13,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register4_q_net_x12,
q_in => register5_q_net_x12,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_9e99bd206d is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_ch2_out: out std_logic_vector(23 downto 0);
tbt_cordic_ch3_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_9e99bd206d;
architecture structural of tddm_tbt_cordic_entity_9e99bd206d is
signal ce_35_sg_x11: std_logic;
signal ce_70_sg_x15: std_logic;
signal clk_35_sg_x11: std_logic;
signal clk_70_sg_x15: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x11 <= ce_35;
ce_70_sg_x15 <= ce_70;
clk_35_sg_x11 <= clk_35;
clk_70_sg_x15 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_ch2_out <= down_sample2_q_net_x2;
tbt_cordic_ch3_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d22fbdac88: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_f04a48283a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC"
entity tbt_cordic_entity_9dc3371de2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_9dc3371de2;
architecture structural of tbt_cordic_entity_9dc3371de2 is
signal ce_1_sg_x29: std_logic;
signal ce_35_sg_x12: std_logic;
signal ce_70_sg_x16: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x29: std_logic;
signal clk_35_sg_x12: std_logic;
signal clk_70_sg_x16: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x29 <= ce_1;
ce_35_sg_x12 <= ce_35;
ce_70_sg_x16 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x29 <= clk_1;
clk_35_sg_x12 <= clk_35;
clk_70_sg_x16 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_1700ad0af26476326977e0830172a2c4
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_9e99bd206d: entity work.tddm_tbt_cordic_entity_9e99bd206d
port map (
ce_35 => ce_35_sg_x12,
ce_70 => ce_70_sg_x16,
clk_35 => clk_35_sg_x12,
clk_70 => clk_70_sg_x16,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_ch2_out => down_sample2_q_net_x4,
tbt_cordic_ch3_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_1f4b61e651 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch2_i_out: out std_logic_vector(23 downto 0);
poly35_ch2_q_out: out std_logic_vector(23 downto 0);
poly35_ch3_i_out: out std_logic_vector(23 downto 0);
poly35_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_1f4b61e651;
architecture structural of tddm_tbt_entity_1f4b61e651 is
signal ce_35_sg_x15: std_logic;
signal ce_70_sg_x19: std_logic;
signal clk_35_sg_x15: std_logic;
signal clk_70_sg_x19: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x15 <= ce_35;
ce_70_sg_x19 <= ce_70;
clk_35_sg_x15 <= clk_35;
clk_70_sg_x19 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch2_i_out <= down_sample2_q_net_x2;
poly35_ch2_q_out <= down_sample2_q_net_x3;
poly35_ch3_i_out <= down_sample1_q_net_x2;
poly35_ch3_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_b74b709553: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_4f85d7362a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim"
entity tbt_poly_decim_entity_bb6f6b5b6a is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_bb6f6b5b6a;
architecture structural of tbt_poly_decim_entity_bb6f6b5b6a is
signal ce_1_sg_x30: std_logic;
signal ce_35_sg_x16: std_logic;
signal ce_70_sg_x20: std_logic;
signal ce_logic_1_sg_x14: std_logic;
signal clk_1_sg_x30: std_logic;
signal clk_35_sg_x16: std_logic;
signal clk_70_sg_x20: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x30 <= ce_1;
ce_35_sg_x16 <= ce_35;
ce_70_sg_x20 <= ce_70;
ce_logic_1_sg_x14 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x30 <= clk_1;
clk_35_sg_x16 <= clk_35;
clk_70_sg_x20 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_dadbc7b58cb62c04fef420f4c58ee0d3
port map (
ce => ce_1_sg_x30,
ce_35 => ce_35_sg_x16,
ce_logic_1 => ce_logic_1_sg_x14,
clk => clk_1_sg_x30,
clk_35 => clk_35_sg_x16,
clk_logic_1 => clk_1_sg_x30,
s_axis_data_tdata_path0 => register4_q_net_x12,
s_axis_data_tdata_path1 => register5_q_net_x12,
s_axis_data_tuser_chanid(0) => register3_q_net_x13,
src_ce => ce_1_sg_x30,
src_clk => clk_1_sg_x30,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_1f4b61e651: entity work.tddm_tbt_entity_1f4b61e651
port map (
ce_35 => ce_35_sg_x16,
ce_70 => ce_70_sg_x20,
clk_35 => clk_35_sg_x16,
clk_70 => clk_70_sg_x20,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch2_i_out => down_sample2_q_net_x4,
poly35_ch2_q_out => down_sample2_q_net_x5,
poly35_ch3_i_out => down_sample1_q_net_x4,
poly35_ch3_q_out => down_sample1_q_net_x5
);
trunc1_c3e3bdeec5: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_6a2a4db298: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1"
entity tbt_amp1_entity_6e98f85f9f is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp1_entity_6e98f85f9f;
architecture structural of tbt_amp1_entity_6e98f85f9f is
signal ce_1_sg_x31: std_logic;
signal ce_35_sg_x17: std_logic;
signal ce_70_sg_x21: std_logic;
signal ce_logic_1_sg_x15: std_logic;
signal clk_1_sg_x31: std_logic;
signal clk_35_sg_x17: std_logic;
signal clk_70_sg_x21: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x14: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x13: std_logic_vector(23 downto 0);
signal register5_q_net_x13: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x31 <= ce_1;
ce_35_sg_x17 <= ce_35;
ce_70_sg_x21 <= ce_70;
ce_logic_1_sg_x15 <= ce_logic_1;
register3_q_net_x14 <= ch_in;
clk_1_sg_x31 <= clk_1;
clk_35_sg_x17 <= clk_35;
clk_70_sg_x21 <= clk_70;
register4_q_net_x13 <= i_in;
register5_q_net_x13 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_9dc3371de2: entity work.tbt_cordic_entity_9dc3371de2
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_bb6f6b5b6a: entity work.tbt_poly_decim_entity_bb6f6b5b6a
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ce_logic_1 => ce_logic_1_sg_x15,
ch_in => register3_q_net_x14,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register4_q_net_x13,
q_in => register5_q_net_x13,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TDDM_tbt_amp_4ch"
entity tddm_tbt_amp_4ch_entity_9f3ac0073e is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_35: in std_logic;
ce_70: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_tbt_amp_4ch_entity_9f3ac0073e;
architecture structural of tddm_tbt_amp_4ch_entity_9f3ac0073e is
signal ce_35_sg_x20: std_logic;
signal ce_70_sg_x24: std_logic;
signal clk_35_sg_x20: std_logic;
signal clk_70_sg_x24: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
begin
p_amp_out_x6 <= amp_in0;
p_amp_out_x7 <= amp_in1;
ce_35_sg_x20 <= ce_35;
ce_70_sg_x24 <= ce_70;
p_ch_out_x7 <= ch_in0;
p_ch_out_x8 <= ch_in1;
clk_35_sg_x20 <= clk_35;
clk_70_sg_x24 <= clk_70;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_tbt_amp0_8f2b25894a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x7,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x6,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_amp1_0c4a2e4770: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x8,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x7,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp"
entity tbt_amp_entity_cbd277bb0c is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
tbt_amp0: out std_logic_vector(23 downto 0);
tbt_amp0_x0: out std_logic_vector(23 downto 0);
tbt_amp0_x1: out std_logic_vector(23 downto 0);
tbt_amp0_x2: out std_logic_vector(23 downto 0);
tbt_amp0_x3: out std_logic;
tbt_amp0_x4: out std_logic_vector(23 downto 0);
tbt_amp0_x5: out std_logic_vector(23 downto 0);
tbt_amp0_x6: out std_logic_vector(23 downto 0);
tbt_amp0_x7: out std_logic_vector(23 downto 0);
tbt_amp1: out std_logic_vector(23 downto 0);
tbt_amp1_x0: out std_logic_vector(23 downto 0);
tbt_amp1_x1: out std_logic_vector(23 downto 0);
tbt_amp1_x2: out std_logic_vector(23 downto 0);
tbt_amp1_x3: out std_logic;
tbt_amp1_x4: out std_logic_vector(23 downto 0);
tbt_amp1_x5: out std_logic_vector(23 downto 0);
tbt_amp1_x6: out std_logic_vector(23 downto 0);
tbt_amp1_x7: out std_logic_vector(23 downto 0)
);
end tbt_amp_entity_cbd277bb0c;
architecture structural of tbt_amp_entity_cbd277bb0c is
signal ce_1_sg_x32: std_logic;
signal ce_35_sg_x21: std_logic;
signal ce_70_sg_x25: std_logic;
signal ce_logic_1_sg_x16: std_logic;
signal clk_1_sg_x32: std_logic;
signal clk_35_sg_x21: std_logic;
signal clk_70_sg_x25: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x3: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x4: std_logic;
begin
ce_1_sg_x32 <= ce_1;
ce_35_sg_x21 <= ce_35;
ce_70_sg_x25 <= ce_70;
ce_logic_1_sg_x16 <= ce_logic_1;
register3_q_net_x15 <= ch_in0;
register3_q_net_x16 <= ch_in1;
clk_1_sg_x32 <= clk_1;
clk_35_sg_x21 <= clk_35;
clk_70_sg_x25 <= clk_70;
register4_q_net_x14 <= i_in0;
register4_q_net_x15 <= i_in1;
register5_q_net_x14 <= q_in0;
register5_q_net_x15 <= q_in1;
amp_out0 <= down_sample2_q_net_x24;
amp_out1 <= down_sample1_q_net_x24;
amp_out2 <= down_sample2_q_net_x25;
amp_out3 <= down_sample1_q_net_x25;
tbt_amp0 <= down_sample1_q_net_x16;
tbt_amp0_x0 <= down_sample2_q_net_x16;
tbt_amp0_x1 <= down_sample1_q_net_x17;
tbt_amp0_x2 <= down_sample2_q_net_x17;
tbt_amp0_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x3;
tbt_amp0_x4 <= down_sample1_q_net_x18;
tbt_amp0_x5 <= down_sample2_q_net_x18;
tbt_amp0_x6 <= down_sample1_q_net_x19;
tbt_amp0_x7 <= down_sample2_q_net_x19;
tbt_amp1 <= down_sample1_q_net_x20;
tbt_amp1_x0 <= down_sample2_q_net_x20;
tbt_amp1_x1 <= down_sample1_q_net_x21;
tbt_amp1_x2 <= down_sample2_q_net_x21;
tbt_amp1_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x4;
tbt_amp1_x4 <= down_sample1_q_net_x22;
tbt_amp1_x5 <= down_sample2_q_net_x22;
tbt_amp1_x6 <= down_sample1_q_net_x23;
tbt_amp1_x7 <= down_sample2_q_net_x23;
tbt_amp0_88b1c45f0e: entity work.tbt_amp0_entity_88b1c45f0e
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x15,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x14,
q_in => register5_q_net_x14,
amp_out => p_amp_out_x6,
ch_out => p_ch_out_x7,
tbt_cordic => down_sample1_q_net_x16,
tbt_cordic_x0 => down_sample2_q_net_x16,
tbt_cordic_x1 => down_sample1_q_net_x17,
tbt_cordic_x2 => down_sample2_q_net_x17,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x3,
tbt_poly_decim_x0 => down_sample1_q_net_x18,
tbt_poly_decim_x1 => down_sample2_q_net_x18,
tbt_poly_decim_x2 => down_sample1_q_net_x19,
tbt_poly_decim_x3 => down_sample2_q_net_x19
);
tbt_amp1_6e98f85f9f: entity work.tbt_amp1_entity_6e98f85f9f
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x16,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x15,
q_in => register5_q_net_x15,
amp_out => p_amp_out_x7,
ch_out => p_ch_out_x8,
tbt_cordic => down_sample1_q_net_x20,
tbt_cordic_x0 => down_sample2_q_net_x20,
tbt_cordic_x1 => down_sample1_q_net_x21,
tbt_cordic_x2 => down_sample2_q_net_x21,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x4,
tbt_poly_decim_x0 => down_sample1_q_net_x22,
tbt_poly_decim_x1 => down_sample2_q_net_x22,
tbt_poly_decim_x2 => down_sample1_q_net_x23,
tbt_poly_decim_x3 => down_sample2_q_net_x23
);
tddm_tbt_amp_4ch_9f3ac0073e: entity work.tddm_tbt_amp_4ch_entity_9f3ac0073e
port map (
amp_in0 => p_amp_out_x6,
amp_in1 => p_amp_out_x7,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ch_in0 => p_ch_out_x7,
ch_in1 => p_ch_out_x8,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
amp_out0 => down_sample2_q_net_x24,
amp_out1 => down_sample1_q_net_x24,
amp_out2 => down_sample2_q_net_x25,
amp_out3 => down_sample1_q_net_x25
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix/TDM_mix_ch0_1"
entity tdm_mix_ch0_1_entity_b9bb73dd5f is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_mix_ch0_1_entity_b9bb73dd5f;
architecture structural of tdm_mix_ch0_1_entity_b9bb73dd5f is
signal ce_1_sg_x33: std_logic;
signal ce_2_sg_x31: std_logic;
signal ce_logic_1_sg_x17: std_logic;
signal clk_1_sg_x33: std_logic;
signal clk_2_sg_x31: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register_q_net_x17: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x8: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x9: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x33 <= ce_1;
ce_2_sg_x31 <= ce_2;
ce_logic_1_sg_x17 <= ce_logic_1;
clk_1_sg_x33 <= clk_1;
clk_2_sg_x31 <= clk_2;
reinterpret2_output_port_net_x9 <= din_ch0;
reinterpret2_output_port_net_x8 <= din_ch1;
constant10_op_net_x0 <= rst;
ch_out <= register1_q_net_x4;
dout <= register_q_net_x17;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x17,
clk => clk_1_sg_x33,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
sel(0) => mux_sel1_op_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op(0) => mux_sel1_op_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register1_q_net_x4
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x17
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x9,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x8,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix"
entity tdm_mix_entity_54ce67e6e8 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
dout0: out std_logic_vector(23 downto 0);
dout1: out std_logic_vector(23 downto 0)
);
end tdm_mix_entity_54ce67e6e8;
architecture structural of tdm_mix_entity_54ce67e6e8 is
signal ce_1_sg_x35: std_logic;
signal ce_2_sg_x33: std_logic;
signal ce_logic_1_sg_x19: std_logic;
signal clk_1_sg_x35: std_logic;
signal clk_2_sg_x33: std_logic;
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register_q_net_x19: std_logic_vector(23 downto 0);
signal register_q_net_x20: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x11: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x12: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x13: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x14: std_logic_vector(23 downto 0);
begin
ce_1_sg_x35 <= ce_1;
ce_2_sg_x33 <= ce_2;
ce_logic_1_sg_x19 <= ce_logic_1;
clk_1_sg_x35 <= clk_1;
clk_2_sg_x33 <= clk_2;
reinterpret2_output_port_net_x14 <= din_ch0;
reinterpret2_output_port_net_x11 <= din_ch1;
reinterpret2_output_port_net_x12 <= din_ch2;
reinterpret2_output_port_net_x13 <= din_ch3;
ch_out0 <= register1_q_net_x6;
ch_out1 <= register1_q_net_x7;
dout0 <= register_q_net_x19;
dout1 <= register_q_net_x20;
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
tdm_mix_ch0_1_b9bb73dd5f: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x14,
din_ch1 => reinterpret2_output_port_net_x11,
rst => constant10_op_net_x0,
ch_out => register1_q_net_x6,
dout => register_q_net_x19
);
tdm_mix_ch0_2_e9327141fc: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x12,
din_ch1 => reinterpret2_output_port_net_x13,
rst => constant11_op_net_x0,
ch_out => register1_q_net_x7,
dout => register_q_net_x20
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit"
entity tdm_monit_entity_6e38292ecb is
port (
ce_1: in std_logic;
ce_2240: in std_logic;
ce_560: in std_logic;
ce_logic_560: in std_logic;
clk_1: in std_logic;
clk_2240: in std_logic;
clk_560: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end tdm_monit_entity_6e38292ecb;
architecture structural of tdm_monit_entity_6e38292ecb is
signal ce_1_sg_x36: std_logic;
signal ce_2240_sg_x26: std_logic;
signal ce_560_sg_x2: std_logic;
signal ce_logic_560_sg_x2: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal clk_1_sg_x36: std_logic;
signal clk_2240_sg_x26: std_logic;
signal clk_560_sg_x2: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal mux_sel_op_net: std_logic_vector(1 downto 0);
signal mux_y_net: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x36 <= ce_1;
ce_2240_sg_x26 <= ce_2240;
ce_560_sg_x2 <= ce_560;
ce_logic_560_sg_x2 <= ce_logic_560;
clk_1_sg_x36 <= clk_1;
clk_2240_sg_x26 <= clk_2240;
clk_560_sg_x2 <= clk_560;
down_sample2_q_net_x18 <= din_ch0;
down_sample1_q_net_x18 <= din_ch1;
down_sample2_q_net_x19 <= din_ch2;
down_sample1_q_net_x19 <= din_ch3;
constant10_op_net_x0 <= rst;
ch_out <= ch_out_x2;
dout <= dout_x2;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_560_sg_x2,
clk => clk_560_sg_x2,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => ch_out_x2
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => mux_y_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => dout_x2
);
mux: entity work.mux_f062741975
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net,
y => mux_y_net
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_3166d4cc5b09c744",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x36,
clk => clk_1_sg_x36,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op => mux_sel_op_net
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample"
entity downsample_entity_f33f90217c is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(1 downto 0);
dout: out std_logic_vector(1 downto 0)
);
end downsample_entity_f33f90217c;
architecture structural of downsample_entity_f33f90217c is
signal ce_1_sg_x37: std_logic;
signal ce_2500_sg_x0: std_logic;
signal ce_5600000_sg_x8: std_logic;
signal clk_1_sg_x37: std_logic;
signal clk_2500_sg_x0: std_logic;
signal clk_5600000_sg_x8: std_logic;
signal down_sample5_q_net: std_logic_vector(1 downto 0);
signal down_sample_q_net_x0: std_logic_vector(1 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
begin
ce_1_sg_x37 <= ce_1;
ce_2500_sg_x0 <= ce_2500;
ce_5600000_sg_x8 <= ce_5600000;
clk_1_sg_x37 <= clk_1;
clk_2500_sg_x0 <= clk_2500;
clk_5600000_sg_x8 <= clk_5600000;
mux_sel_op_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x8,
dest_clk => clk_5600000_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x0,
src_clk => clk_2500_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net_x0,
dest_ce => ce_2500_sg_x0,
dest_clk => clk_2500_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x37,
src_clk => clk_1_sg_x37,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample1"
entity downsample1_entity_312d531c6b is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample1_entity_312d531c6b;
architecture structural of downsample1_entity_312d531c6b is
signal ce_1_sg_x38: std_logic;
signal ce_2500_sg_x1: std_logic;
signal ce_5600000_sg_x9: std_logic;
signal clk_1_sg_x38: std_logic;
signal clk_2500_sg_x1: std_logic;
signal clk_5600000_sg_x9: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
begin
ce_1_sg_x38 <= ce_1;
ce_2500_sg_x1 <= ce_2500;
ce_5600000_sg_x9 <= ce_5600000;
clk_1_sg_x38 <= clk_1;
clk_2500_sg_x1 <= clk_2500;
clk_5600000_sg_x9 <= clk_5600000;
mux_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x9,
dest_clk => clk_5600000_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x1,
src_clk => clk_2500_sg_x1,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => mux_y_net_x0,
dest_ce => ce_2500_sg_x1,
dest_clk => clk_2500_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x38,
src_clk => clk_1_sg_x38,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1"
entity tdm_monit_1_entity_746ecf54b0 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
ce_logic_5600000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din_ch0: in std_logic_vector(25 downto 0);
din_ch1: in std_logic_vector(25 downto 0);
din_ch2: in std_logic_vector(25 downto 0);
din_ch3: in std_logic_vector(25 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end tdm_monit_1_entity_746ecf54b0;
architecture structural of tdm_monit_1_entity_746ecf54b0 is
signal ce_1_sg_x39: std_logic;
signal ce_22400000_sg_x10: std_logic;
signal ce_2500_sg_x2: std_logic;
signal ce_5600000_sg_x10: std_logic;
signal ce_logic_5600000_sg_x0: std_logic;
signal clk_1_sg_x39: std_logic;
signal clk_22400000_sg_x10: std_logic;
signal clk_2500_sg_x2: std_logic;
signal clk_5600000_sg_x10: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant11_op_net_x0: std_logic;
signal down_sample_q_net_x2: std_logic_vector(1 downto 0);
signal down_sample_q_net_x3: std_logic_vector(25 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x39 <= ce_1;
ce_22400000_sg_x10 <= ce_22400000;
ce_2500_sg_x2 <= ce_2500;
ce_5600000_sg_x10 <= ce_5600000;
ce_logic_5600000_sg_x0 <= ce_logic_5600000;
clk_1_sg_x39 <= clk_1;
clk_22400000_sg_x10 <= clk_22400000;
clk_2500_sg_x2 <= clk_2500;
clk_5600000_sg_x10 <= clk_5600000;
concat_y_net_x0 <= din_ch0;
concat1_y_net_x0 <= din_ch1;
concat2_y_net_x0 <= din_ch2;
concat3_y_net_x0 <= din_ch3;
constant11_op_net_x0 <= rst;
ch_out <= down_sample_q_net_x2;
dout <= down_sample_q_net_x3;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 26,
q_width => 1
)
port map (
ce => ce_logic_5600000_sg_x0,
clk => clk_5600000_sg_x10,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
downsample1_312d531c6b: entity work.downsample1_entity_312d531c6b
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_y_net_x0,
dout => down_sample_q_net_x3
);
downsample_f33f90217c: entity work.downsample_entity_f33f90217c
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_sel_op_net_x0,
dout => down_sample_q_net_x2
);
mux: entity work.mux_187c900130
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net_x0,
y => mux_y_net_x0
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_3166d4cc5b09c744",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x39,
clk => clk_1_sg_x39,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op => mux_sel_op_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat1_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat2_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat3_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/convert_filt"
entity convert_filt_entity_fda412c1bf is
port (
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end convert_filt_entity_fda412c1bf;
architecture structural of convert_filt_entity_fda412c1bf is
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x0: std_logic_vector(24 downto 0);
begin
down_sample_q_net_x4 <= din;
dout <= reinterpret5_output_port_net_x0;
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample_q_net_x4,
dout => extractor1_dout_net
);
reinterpret5: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret5_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En"
entity datareg_en_entity_79473f9ed1 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en_entity_79473f9ed1;
architecture structural of datareg_en_entity_79473f9ed1 is
signal ce_1_sg_x40: std_logic;
signal clk_1_sg_x40: std_logic;
signal divider_dout_valid_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x40 <= ce_1;
clk_1_sg_x40 <= clk_1;
reinterpret1_output_port_net_x0 <= din;
divider_dout_valid_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d(0) => divider_dout_valid_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d => reinterpret1_output_port_net_x0,
en(0) => divider_dout_valid_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En3"
entity datareg_en3_entity_6643090018 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en3_entity_6643090018;
architecture structural of datareg_en3_entity_6643090018 is
signal ce_1_sg_x43: std_logic;
signal clk_1_sg_x43: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal delay1_q_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x43 <= ce_1;
clk_1_sg_x43 <= clk_1;
convert_dout_net_x0 <= din;
delay1_q_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d(0) => delay1_q_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d => convert_dout_net_x0,
en(0) => delay1_q_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/pulse_stretcher"
entity pulse_stretcher_entity_9893378b63 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
clr: in std_logic;
pulse_in: in std_logic;
extd_out: out std_logic
);
end pulse_stretcher_entity_9893378b63;
architecture structural of pulse_stretcher_entity_9893378b63 is
signal ce_1_sg_x44: std_logic;
signal ce_70_x0: std_logic;
signal clk_1_sg_x44: std_logic;
signal inverter_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register_q_net: std_logic;
begin
ce_1_sg_x44 <= ce_1;
clk_1_sg_x44 <= clk_1;
ce_70_x0 <= clr;
register1_q_net_x1 <= pulse_in;
extd_out <= logical3_y_net_x0;
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
clr => '0',
ip(0) => ce_70_x0,
op(0) => inverter_op_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register_q_net,
d1(0) => inverter_op_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => logical1_y_net,
y(0) => logical2_y_net
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => register_q_net,
y(0) => logical3_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
d(0) => logical2_y_net,
en => "1",
rst => "0",
q(0) => register_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb"
entity delta_sigma_fofb_entity_ee61e649ea is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_logic_2240: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_fofb_entity_ee61e649ea;
architecture structural of delta_sigma_fofb_entity_ee61e649ea is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x52: std_logic;
signal ce_2240_sg_x27: std_logic;
signal ce_2_sg_x34: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_2240_sg_x0: std_logic;
signal clk_1_sg_x52: std_logic;
signal clk_2240_sg_x27: std_logic;
signal clk_2_sg_x34: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_fofb_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x20 <= a;
down_sample1_q_net_x20 <= b;
down_sample2_q_net_x21 <= c;
ce_1_sg_x52 <= ce_1;
ce_2_sg_x34 <= ce_2;
ce_2240_sg_x27 <= ce_2240;
ce_logic_2240_sg_x0 <= ce_logic_2240;
clk_1_sg_x52 <= clk_1;
clk_2_sg_x34 <= clk_2;
clk_2240_sg_x27 <= clk_2240;
down_sample1_q_net_x21 <= d;
del_sig_div_fofb_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x21,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_2240_sg_x0,
clk => clk_2240_sg_x27,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_3225c09afc: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_5b5f4b61b7: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_6643090018: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_79473f9ed1: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x34,
src_clk => clk_2_sg_x34,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_f6401a1a3d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_38948aaba0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_816d954034: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_5d505b900f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_bee4540339: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_f82d879b1c: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_2406c4a105: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_9893378b63: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x34,
clk => clk_2_sg_x34,
d => del_sig_div_fofb_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_239e4f614ba09ab1",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample1"
entity downsample1_entity_4c88924603 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample1_entity_4c88924603;
architecture structural of downsample1_entity_4c88924603 is
signal ce_1_sg_x57: std_logic;
signal ce_22400000_sg_x11: std_logic;
signal ce_5000_sg_x0: std_logic;
signal clk_1_sg_x57: std_logic;
signal clk_22400000_sg_x11: std_logic;
signal clk_5000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x57 <= ce_1;
ce_22400000_sg_x11 <= ce_22400000;
ce_5000_sg_x0 <= ce_5000;
clk_1_sg_x57 <= clk_1;
clk_22400000_sg_x11 <= clk_22400000;
clk_5000_sg_x0 <= clk_5000;
register13_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x11,
dest_clk => clk_22400000_sg_x11,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x0,
src_clk => clk_5000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net_x0,
dest_ce => ce_5000_sg_x0,
dest_clk => clk_5000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x57,
src_clk => clk_1_sg_x57,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample2"
entity downsample2_entity_891f07b1a7 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic;
dout: out std_logic
);
end downsample2_entity_891f07b1a7;
architecture structural of downsample2_entity_891f07b1a7 is
signal ce_1_sg_x58: std_logic;
signal ce_22400000_sg_x12: std_logic;
signal ce_5000_sg_x1: std_logic;
signal clk_1_sg_x58: std_logic;
signal clk_22400000_sg_x12: std_logic;
signal clk_5000_sg_x1: std_logic;
signal down_sample5_q_net: std_logic;
signal down_sample_q_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
begin
ce_1_sg_x58 <= ce_1;
ce_22400000_sg_x12 <= ce_22400000;
ce_5000_sg_x1 <= ce_5000;
clk_1_sg_x58 <= clk_1;
clk_22400000_sg_x12 <= clk_22400000;
clk_5000_sg_x1 <= clk_5000;
logical3_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => down_sample5_q_net,
dest_ce => ce_22400000_sg_x12,
dest_clk => clk_22400000_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x1,
src_clk => clk_5000_sg_x1,
src_clr => '0',
q(0) => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_5000_sg_x1,
dest_clk => clk_5000_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x58,
src_clk => clk_1_sg_x58,
src_clr => '0',
q(0) => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample3"
entity downsample3_entity_dba589aaee is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample3_entity_dba589aaee;
architecture structural of downsample3_entity_dba589aaee is
signal ce_1_sg_x59: std_logic;
signal ce_22400000_sg_x13: std_logic;
signal ce_5000_sg_x2: std_logic;
signal clk_1_sg_x59: std_logic;
signal clk_22400000_sg_x13: std_logic;
signal clk_5000_sg_x2: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x59 <= ce_1;
ce_22400000_sg_x13 <= ce_22400000;
ce_5000_sg_x2 <= ce_5000;
clk_1_sg_x59 <= clk_1;
clk_22400000_sg_x13 <= clk_22400000;
clk_5000_sg_x2 <= clk_5000;
register12_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x13,
dest_clk => clk_22400000_sg_x13,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x2,
src_clk => clk_5000_sg_x2,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net_x0,
dest_ce => ce_5000_sg_x2,
dest_clk => clk_5000_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x59,
src_clk => clk_1_sg_x59,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample7"
entity downsample7_entity_b85055cb62 is
port (
ce_10000: in std_logic;
ce_2: in std_logic;
ce_44800000: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_44800000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample7_entity_b85055cb62;
architecture structural of downsample7_entity_b85055cb62 is
signal ce_10000_sg_x0: std_logic;
signal ce_2_sg_x35: std_logic;
signal ce_44800000_sg_x0: std_logic;
signal clk_10000_sg_x0: std_logic;
signal clk_2_sg_x35: std_logic;
signal clk_44800000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
begin
ce_10000_sg_x0 <= ce_10000;
ce_2_sg_x35 <= ce_2;
ce_44800000_sg_x0 <= ce_44800000;
clk_10000_sg_x0 <= clk_10000;
clk_2_sg_x35 <= clk_2;
clk_44800000_sg_x0 <= clk_44800000;
register14_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_44800000_sg_x0,
dest_clk => clk_44800000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_10000_sg_x0,
src_clk => clk_10000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net_x0,
dest_ce => ce_10000_sg_x0,
dest_clk => clk_10000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x35,
src_clk => clk_2_sg_x35,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad"
entity upsample_copy_pad_entity_86c97eac4f is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad_entity_86c97eac4f;
architecture structural of upsample_copy_pad_entity_86c97eac4f is
signal ce_1_sg_x73: std_logic;
signal ce_22400000_sg_x19: std_logic;
signal ce_4480_sg_x0: std_logic;
signal clk_1_sg_x73: std_logic;
signal clk_22400000_sg_x19: std_logic;
signal clk_4480_sg_x0: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x73 <= ce_1;
ce_22400000_sg_x19 <= ce_22400000;
ce_4480_sg_x0 <= ce_4480;
clk_1_sg_x73 <= clk_1;
clk_22400000_sg_x19 <= clk_22400000;
clk_4480_sg_x0 <= clk_4480;
register10_q_net_x0 <= din;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x73,
dest_clk => clk_1_sg_x73,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x0,
src_clk => clk_4480_sg_x0,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net_x0,
dest_ce => ce_4480_sg_x0,
dest_clk => clk_4480_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x19,
src_clk => clk_22400000_sg_x19,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad1"
entity upsample_copy_pad1_entity_edde199d79 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din_x0: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad1_entity_edde199d79;
architecture structural of upsample_copy_pad1_entity_edde199d79 is
signal ce_1_sg_x74: std_logic;
signal ce_22400000_sg_x20: std_logic;
signal ce_4480_sg_x1: std_logic;
signal clk_1_sg_x74: std_logic;
signal clk_22400000_sg_x20: std_logic;
signal clk_4480_sg_x1: std_logic;
signal din_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x74 <= ce_1;
ce_22400000_sg_x20 <= ce_22400000;
ce_4480_sg_x1 <= ce_4480;
clk_1_sg_x74 <= clk_1;
clk_22400000_sg_x20 <= clk_22400000;
clk_4480_sg_x1 <= clk_4480;
din_x1 <= din_x0;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x74,
dest_clk => clk_1_sg_x74,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x1,
src_clk => clk_4480_sg_x1,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din_x1,
dest_ce => ce_4480_sg_x1,
dest_clk => clk_4480_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x20,
src_clk => clk_22400000_sg_x20,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_zero_pad"
entity upsample_zero_pad_entity_e334b63be9 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic;
dout: out std_logic
);
end upsample_zero_pad_entity_e334b63be9;
architecture structural of upsample_zero_pad_entity_e334b63be9 is
signal assert13_dout_net_x0: std_logic;
signal ce_1_sg_x77: std_logic;
signal ce_22400000_sg_x23: std_logic;
signal ce_4480_sg_x4: std_logic;
signal clk_1_sg_x77: std_logic;
signal clk_22400000_sg_x23: std_logic;
signal clk_4480_sg_x4: std_logic;
signal up_sample1_q_net_x1: std_logic;
signal up_sample5_q_net: std_logic;
begin
ce_1_sg_x77 <= ce_1;
ce_22400000_sg_x23 <= ce_22400000;
ce_4480_sg_x4 <= ce_4480;
clk_1_sg_x77 <= clk_1;
clk_22400000_sg_x23 <= clk_22400000;
clk_4480_sg_x4 <= clk_4480;
assert13_dout_net_x0 <= din;
dout <= up_sample1_q_net_x1;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => up_sample5_q_net,
dest_ce => ce_1_sg_x77,
dest_clk => clk_1_sg_x77,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x4,
src_clk => clk_4480_sg_x4,
src_clr => '0',
q(0) => up_sample1_q_net_x1
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert13_dout_net_x0,
dest_ce => ce_4480_sg_x4,
dest_clk => clk_4480_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x23,
src_clk => clk_22400000_sg_x23,
src_clr => '0',
q(0) => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit"
entity delta_sigma_monit_entity_a8f8b81626 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_2: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_logic_22400000: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_monit_entity_a8f8b81626;
architecture structural of delta_sigma_monit_entity_a8f8b81626 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert13_dout_net_x3: std_logic;
signal assert2_dout_net_x0: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert9_dout_net_x1: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_10000_sg_x1: std_logic;
signal ce_1_sg_x81: std_logic;
signal ce_22400000_sg_x27: std_logic;
signal ce_2_sg_x36: std_logic;
signal ce_44800000_sg_x1: std_logic;
signal ce_4480_sg_x8: std_logic;
signal ce_5000_sg_x8: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_22400000_sg_x0: std_logic;
signal clk_10000_sg_x1: std_logic;
signal clk_1_sg_x81: std_logic;
signal clk_22400000_sg_x27: std_logic;
signal clk_2_sg_x36: std_logic;
signal clk_44800000_sg_x1: std_logic;
signal clk_4480_sg_x8: std_logic;
signal clk_5000_sg_x8: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_monit_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din_x1: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch_x0: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal down_sample_q_net_x1: std_logic;
signal down_sample_q_net_x2: std_logic_vector(24 downto 0);
signal down_sample_q_net_x3: std_logic;
signal down_sample_q_net_x4: std_logic_vector(24 downto 0);
signal down_sample_q_net_x5: std_logic;
signal down_sample_q_net_x6: std_logic_vector(25 downto 0);
signal down_sample_q_net_x7: std_logic_vector(24 downto 0);
signal down_sample_q_net_x8: std_logic;
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal register11_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x2: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x3: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x4: std_logic;
signal up_sample1_q_net_x5: std_logic;
signal up_sample1_q_net_x6: std_logic;
signal up_sample1_q_net_x7: std_logic;
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x5 <= a;
down_sample1_q_net_x5 <= b;
down_sample3_q_net_x5 <= c;
ce_1_sg_x81 <= ce_1;
ce_10000_sg_x1 <= ce_10000;
ce_2_sg_x36 <= ce_2;
ce_22400000_sg_x27 <= ce_22400000;
ce_4480_sg_x8 <= ce_4480;
ce_44800000_sg_x1 <= ce_44800000;
ce_5000_sg_x8 <= ce_5000;
ce_logic_22400000_sg_x0 <= ce_logic_22400000;
clk_1_sg_x81 <= clk_1;
clk_10000_sg_x1 <= clk_10000;
clk_2_sg_x36 <= clk_2;
clk_22400000_sg_x27 <= clk_22400000;
clk_4480_sg_x8 <= clk_4480;
clk_44800000_sg_x1 <= clk_44800000;
clk_5000_sg_x8 <= clk_5000;
down_sample4_q_net_x5 <= d;
del_sig_div_monit_thres_i_net_x0 <= ds_thres;
q <= assert4_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert10_dout_net_x1;
sum_x0 <= assert5_dout_net_x1;
x <= assert11_dout_net_x1;
x_valid <= assert12_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x1,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x2,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x3,
dout(0) => assert12_dout_net_x1
);
assert13: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert13_dout_net_x3
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert2_dout_net_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x7,
dout => assert4_dout_net_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x0,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x4,
dout => dout_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x5,
dout(0) => valid_ds_down_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x8,
dout(0) => assert9_dout_net_x1
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample3_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_22400000_sg_x0,
clk => clk_22400000_sg_x27,
d(0) => assert13_dout_net_x3,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_0658df0e73: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_b216d22f41: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_352b935ccb: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_8be792d5b9: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d(0) => logical3_y_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
downsample1_4c88924603: entity work.downsample1_entity_4c88924603
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register13_q_net_x0,
dout => down_sample_q_net_x0
);
downsample2_891f07b1a7: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x4,
dout => down_sample_q_net_x1
);
downsample3_dba589aaee: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register12_q_net_x0,
dout => down_sample_q_net_x2
);
downsample4_c9912c17cb: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x3,
dout => down_sample_q_net_x3
);
downsample5_5d411d5dea: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => dout_stretch_x0,
dout => down_sample_q_net_x4
);
downsample6_d7e68015e5: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x1,
dout => down_sample_q_net_x5
);
downsample7_b85055cb62: entity work.downsample7_entity_b85055cb62
port map (
ce_10000 => ce_10000_sg_x1,
ce_2 => ce_2_sg_x36,
ce_44800000 => ce_44800000_sg_x1,
clk_10000 => clk_10000_sg_x1,
clk_2 => clk_2_sg_x36,
clk_44800000 => clk_44800000_sg_x1,
din => register14_q_net_x0,
dout => down_sample_q_net_x6
);
downsample8_69d7284f0d: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register11_q_net_x0,
dout => down_sample_q_net_x7
);
downsample9_f5ac9b8db2: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x2,
dout => down_sample_q_net_x8
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_427f70e3c7: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x2
);
pulse_stretcher2_9a61283281: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x3
);
pulse_stretcher3_864c3e16a6: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x4
);
pulse_stretcher4_8dfd1c8928: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert6_dout_net_x0,
pulse_in => up_sample1_q_net_x6,
extd_out => logical3_y_net_x0
);
pulse_stretcher5_ac376595d0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x0,
pulse_in => up_sample1_q_net_x5,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_694b81e6b2: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert2_dout_net_x0,
pulse_in => up_sample1_q_net_x4,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_bb8174efbd: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x1,
pulse_in => up_sample1_q_net_x7,
extd_out => logical3_y_net_x7
);
pulse_stretcher_6bf297451d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x1
);
q_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net_x0
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net_x0
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net_x0
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net_x0
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x36,
clk => clk_2_sg_x36,
d => del_sig_div_monit_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net_x0
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net_x0
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data_x0
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din_x1
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch_x0
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x3,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x2,
output_port => divisor_data
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x1,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x0,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data_x0,
b => down_sample_q_net_x6,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_239e4f614ba09ab1",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
upsample_copy_pad1_edde199d79: entity work.upsample_copy_pad1_entity_edde199d79
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din_x0 => din_x1,
dout => up_sample1_q_net_x1
);
upsample_copy_pad2_46599e345b: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => divisor_data_x0,
dout => up_sample1_q_net_x2
);
upsample_copy_pad3_3571daa38f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register7_q_net_x0,
dout => up_sample1_q_net_x3
);
upsample_copy_pad_86c97eac4f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register10_q_net_x0,
dout => up_sample1_q_net_x0
);
upsample_zero_pad1_2044d1ec3f: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x5
);
upsample_zero_pad2_7f2f8f8620: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x6
);
upsample_zero_pad3_f0b4acbf28: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x7
);
upsample_zero_pad_e334b63be9: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x4
);
x_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_tbt"
entity delta_sigma_tbt_entity_bbfa8a8a69 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_70: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_tbt_entity_bbfa8a8a69;
architecture structural of delta_sigma_tbt_entity_bbfa8a8a69 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x94: std_logic;
signal ce_2_sg_x37: std_logic;
signal ce_70_sg_x26: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_70_sg_x0: std_logic;
signal clk_1_sg_x94: std_logic;
signal clk_2_sg_x37: std_logic;
signal clk_70_sg_x26: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_tbt_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x26 <= a;
down_sample1_q_net_x26 <= b;
down_sample2_q_net_x27 <= c;
ce_1_sg_x94 <= ce_1;
ce_2_sg_x37 <= ce_2;
ce_70_sg_x26 <= ce_70;
ce_logic_70_sg_x0 <= ce_logic_70;
clk_1_sg_x94 <= clk_1;
clk_2_sg_x37 <= clk_2;
clk_70_sg_x26 <= clk_70;
down_sample1_q_net_x27 <= d;
del_sig_div_tbt_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x26,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x27,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_70_sg_x0,
clk => clk_70_sg_x26,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_e5d0399944: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_02a2053e69: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_78179f99cc: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_ed948c360a: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x37,
src_clk => clk_2_sg_x37,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_eef5ee33be: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_6f5c3f41cf: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_e720dfd76f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_0a5eb3f903: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_b95a604b09: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_e7fb2961d9: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_6e7eb70147: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_f661707a58: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x37,
clk => clk_2_sg_x37,
d => del_sig_div_tbt_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_239e4f614ba09ab1",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1/format1"
entity format1_entity_a98b06306e is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end format1_entity_a98b06306e;
architecture structural of format1_entity_a98b06306e is
signal ce_56000000_sg_x0: std_logic;
signal clk_56000000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net: std_logic_vector(25 downto 0);
begin
ce_56000000_sg_x0 <= ce_56000000;
clk_56000000_sg_x0 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 24,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 24,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_56000000_sg_x0,
clk => clk_56000000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pos_1_c_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1"
entity cast1_entity_3d447d0833 is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
data_in: in std_logic_vector(25 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(24 downto 0);
vld_out: out std_logic
);
end cast1_entity_3d447d0833;
architecture structural of cast1_entity_3d447d0833 is
signal ce_56000000_sg_x1: std_logic;
signal clk_56000000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_56000000_sg_x1 <= ce_56000000;
clk_56000000_sg_x1 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x1 <= data_in;
monit_pos_1_c_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
vld_out <= register1_q_net_x0;
format1_a98b06306e: entity work.format1_entity_a98b06306e
port map (
ce_56000000 => ce_56000000_sg_x1,
clk_56000000 => clk_56000000_sg_x1,
din => monit_pos_1_c_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out/TDDM_monit_pos_1_out_int"
entity tddm_monit_pos_1_out_int_entity_3405798202 is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_224000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout_ch0: out std_logic_vector(25 downto 0);
dout_ch1: out std_logic_vector(25 downto 0);
dout_ch2: out std_logic_vector(25 downto 0);
dout_ch3: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_int_entity_3405798202;
architecture structural of tddm_monit_pos_1_out_int_entity_3405798202 is
signal ce_224000000_sg_x4: std_logic;
signal ce_56000000_sg_x2: std_logic;
signal clk_224000000_sg_x4: std_logic;
signal clk_56000000_sg_x2: std_logic;
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(25 downto 0);
signal register2_q_net: std_logic_vector(25 downto 0);
signal register3_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x1: std_logic_vector(1 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_224000000_sg_x4 <= ce_224000000;
ce_56000000_sg_x2 <= ce_56000000;
register_q_net_x1 <= ch_in;
clk_224000000_sg_x4 <= clk_224000000;
clk_56000000_sg_x2 <= clk_56000000;
concat_y_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register1_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register_q_net_x0,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register2_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register3_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net_x0
);
relational: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant1_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant3_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant4_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out"
entity tddm_monit_pos_1_out_entity_1d58a51dbf is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
clk_224000000: in std_logic;
clk_56000000: in std_logic;
monit_pos_1_ch_in: in std_logic_vector(1 downto 0);
monit_pos_1_din: in std_logic_vector(25 downto 0);
monit_pos_1_q_out: out std_logic_vector(25 downto 0);
monit_pos_1_sum_out: out std_logic_vector(25 downto 0);
monit_pos_1_x_out: out std_logic_vector(25 downto 0);
monit_pos_1_y_out: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_entity_1d58a51dbf;
architecture structural of tddm_monit_pos_1_out_entity_1d58a51dbf is
signal ce_224000000_sg_x5: std_logic;
signal ce_56000000_sg_x3: std_logic;
signal clk_224000000_sg_x5: std_logic;
signal clk_56000000_sg_x3: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
begin
ce_224000000_sg_x5 <= ce_224000000;
ce_56000000_sg_x3 <= ce_56000000;
clk_224000000_sg_x5 <= clk_224000000;
clk_56000000_sg_x3 <= clk_56000000;
register_q_net_x2 <= monit_pos_1_ch_in;
concat_y_net_x1 <= monit_pos_1_din;
monit_pos_1_q_out <= down_sample3_q_net_x1;
monit_pos_1_sum_out <= down_sample4_q_net_x1;
monit_pos_1_x_out <= down_sample2_q_net_x1;
monit_pos_1_y_out <= down_sample1_q_net_x1;
tddm_monit_pos_1_out_int_3405798202: entity work.tddm_monit_pos_1_out_int_entity_3405798202
port map (
ce_224000000 => ce_224000000_sg_x5,
ce_56000000 => ce_56000000_sg_x3,
ch_in => register_q_net_x2,
clk_224000000 => clk_224000000_sg_x5,
clk_56000000 => clk_56000000_sg_x3,
din => concat_y_net_x1,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1"
entity monit_pos_1_entity_522c8cf08d is
port (
ce_1: in std_logic;
ce_224000000: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_logic_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_224000000: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(24 downto 0);
monit_1_pos_q: out std_logic_vector(24 downto 0);
monit_1_pos_x: out std_logic_vector(24 downto 0);
monit_1_pos_y: out std_logic_vector(24 downto 0);
monit_1_sum: out std_logic_vector(24 downto 0);
monit_1_vld_q: out std_logic;
monit_1_vld_sum: out std_logic;
monit_1_vld_x: out std_logic;
monit_1_vld_y: out std_logic;
monit_pos_1_c_x0: out std_logic
);
end monit_pos_1_entity_522c8cf08d;
architecture structural of monit_pos_1_entity_522c8cf08d is
signal ce_1_sg_x95: std_logic;
signal ce_224000000_sg_x6: std_logic;
signal ce_56000000_sg_x4: std_logic;
signal ce_5600000_sg_x11: std_logic;
signal ce_logic_5600000_sg_x1: std_logic;
signal clk_1_sg_x95: std_logic;
signal clk_224000000_sg_x6: std_logic;
signal clk_56000000_sg_x4: std_logic;
signal clk_5600000_sg_x11: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal extractor1_vld_out_net: std_logic;
signal extractor2_dout_net: std_logic_vector(24 downto 0);
signal extractor2_vld_out_net: std_logic;
signal extractor3_dout_net: std_logic_vector(24 downto 0);
signal extractor3_vld_out_net: std_logic;
signal extractor4_dout_net: std_logic_vector(24 downto 0);
signal extractor4_vld_out_net: std_logic;
signal monit_pos_1_c_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
begin
ce_1_sg_x95 <= ce_1;
ce_224000000_sg_x6 <= ce_224000000;
ce_5600000_sg_x11 <= ce_5600000;
ce_56000000_sg_x4 <= ce_56000000;
ce_logic_5600000_sg_x1 <= ce_logic_5600000;
down_sample_q_net_x3 <= ch_in;
clk_1_sg_x95 <= clk_1;
clk_224000000_sg_x6 <= clk_224000000;
clk_5600000_sg_x11 <= clk_5600000;
clk_56000000_sg_x4 <= clk_56000000;
reinterpret5_output_port_net_x1 <= din;
monit_1_pos_q <= reinterpret2_output_port_net_x1;
monit_1_pos_x <= reinterpret3_output_port_net_x1;
monit_1_pos_y <= reinterpret1_output_port_net_x1;
monit_1_sum <= reinterpret4_output_port_net_x1;
monit_1_vld_q <= ufix_to_bool2_dout_net_x1;
monit_1_vld_sum <= ufix_to_bool3_dout_net_x1;
monit_1_vld_x <= ufix_to_bool_dout_net_x1;
monit_1_vld_y <= ufix_to_bool1_dout_net_x1;
monit_pos_1_c_x0 <= monit_pos_1_c_event_s_data_chanid_incorrect_net_x0;
cast1_3d447d0833: entity work.cast1_entity_3d447d0833
port map (
ce_56000000 => ce_56000000_sg_x4,
clk_56000000 => clk_56000000_sg_x4,
data_in => monit_pos_1_c_m_axis_data_tdata_net_x1,
en => monit_pos_1_c_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0,
vld_out => register1_q_net_x0
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => register1_q_net_x0,
in1 => reinterpret5_output_port_net,
y => concat_y_net_x1
);
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample3_q_net_x1,
dout => extractor1_dout_net,
vld_out(0) => extractor1_vld_out_net
);
extractor2: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample1_q_net_x1,
dout => extractor2_dout_net,
vld_out(0) => extractor2_vld_out_net
);
extractor3: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample4_q_net_x1,
dout => extractor3_dout_net,
vld_out(0) => extractor3_vld_out_net
);
extractor4: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample2_q_net_x1,
dout => extractor4_dout_net,
vld_out(0) => extractor4_vld_out_net
);
monit_pos_1_c: entity work.xlfir_compiler_c8ab56fde252f177c3a1ef23ff29e49a
port map (
ce => ce_1_sg_x95,
ce_5600000 => ce_5600000_sg_x11,
ce_56000000 => ce_56000000_sg_x4,
ce_logic_5600000 => ce_logic_5600000_sg_x1,
clk => clk_1_sg_x95,
clk_5600000 => clk_5600000_sg_x11,
clk_56000000 => clk_56000000_sg_x4,
clk_logic_5600000 => clk_5600000_sg_x11,
s_axis_data_tdata => reinterpret5_output_port_net_x1,
s_axis_data_tuser_chanid => down_sample_q_net_x3,
src_ce => ce_5600000_sg_x11,
src_clk => clk_5600000_sg_x11,
event_s_data_chanid_incorrect => monit_pos_1_c_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pos_1_c_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pos_1_c_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pos_1_c_m_axis_data_tvalid_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_56000000_sg_x4,
clk => clk_56000000_sg_x4,
d => monit_pos_1_c_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register_q_net_x2
);
reinterpret1: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor2_dout_net,
output_port => reinterpret1_output_port_net_x1
);
reinterpret2: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret2_output_port_net_x1
);
reinterpret3: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor4_dout_net,
output_port => reinterpret3_output_port_net_x1
);
reinterpret4: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor3_dout_net,
output_port => reinterpret4_output_port_net_x1
);
reinterpret5: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x0,
output_port => reinterpret5_output_port_net
);
tddm_monit_pos_1_out_1d58a51dbf: entity work.tddm_monit_pos_1_out_entity_1d58a51dbf
port map (
ce_224000000 => ce_224000000_sg_x6,
ce_56000000 => ce_56000000_sg_x4,
clk_224000000 => clk_224000000_sg_x6,
clk_56000000 => clk_56000000_sg_x4,
monit_pos_1_ch_in => register_q_net_x2,
monit_pos_1_din => concat_y_net_x1,
monit_pos_1_q_out => down_sample3_q_net_x1,
monit_pos_1_sum_out => down_sample4_q_net_x1,
monit_pos_1_x_out => down_sample2_q_net_x1,
monit_pos_1_y_out => down_sample1_q_net_x1
);
ufix_to_bool: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor4_vld_out_net,
en => "1",
dout(0) => ufix_to_bool_dout_net_x1
);
ufix_to_bool1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor2_vld_out_net,
en => "1",
dout(0) => ufix_to_bool1_dout_net_x1
);
ufix_to_bool2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor1_vld_out_net,
en => "1",
dout(0) => ufix_to_bool2_dout_net_x1
);
ufix_to_bool3: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor3_vld_out_net,
en => "1",
dout(0) => ufix_to_bool3_dout_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066"
entity ddc_bpm_476_066 is
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_1120: in std_logic;
ce_1400000: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_22400000: in std_logic;
ce_224000000: in std_logic;
ce_2500: in std_logic;
ce_2800000: in std_logic;
ce_35: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2240: in std_logic;
ce_logic_22400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ce_logic_5600000: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_1120: in std_logic;
clk_1400000: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
clk_22400000: in std_logic;
clk_224000000: in std_logic;
clk_2500: in std_logic;
clk_2800000: in std_logic;
clk_35: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
clk_70: in std_logic;
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end ddc_bpm_476_066;
architecture structural of ddc_bpm_476_066 is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "ddc_bpm_476_066,sysgen_core,{clock_period=4.44116092,clocking=Clock_Enables,compilation=HDL_Netlist,sample_periods=1.00000000000 2.00000000000 35.00000000000 70.00000000000 560.00000000000 1120.00000000000 2240.00000000000 2500.00000000000 4480.00000000000 5000.00000000000 10000.00000000000 1400000.00000000000 2800000.00000000000 5600000.00000000000 22400000.00000000000 44800000.00000000000 56000000.00000000000 224000000.00000000000,testbench=0,total_blocks=3351,xilinx_adder_subtracter_block=30,xilinx_arithmetic_relational_operator_block=66,xilinx_assert_block=55,xilinx_bit_slice_extractor_block=20,xilinx_bitbasher_block=5,xilinx_bitwise_expression_evaluator_block=3,xilinx_black_box_block=1,xilinx_bus_concatenator_block=9,xilinx_bus_multiplexer_block=8,xilinx_cic_compiler_3_0_block=5,xilinx_clock_enable_probe_block=11,xilinx_complex_multiplier_5_0__block=2,xilinx_constant_block_block=83,xilinx_cordic_5_0_block=4,xilinx_counter_block=8,xilinx_delay_block=59,xilinx_divider_generator_4_0_block=9,xilinx_down_sampler_block=118,xilinx_fir_compiler_6_3_block=5,xilinx_gateway_in_block=22,xilinx_gateway_out_block=233,xilinx_inverter_block=24,xilinx_logical_block_block=72,xilinx_multiplier_block=16,xilinx_register_block=264,xilinx_sample_time_block_block=88,xilinx_system_generator_block=1,xilinx_type_converter_block=23,xilinx_type_reinterpreter_block=94,xilinx_up_sampler_block=68,xilinx_wavescope_block=2,}";
signal adc_ch0_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch0_i_net: std_logic_vector(15 downto 0);
signal adc_ch1_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch1_i_net: std_logic_vector(15 downto 0);
signal adc_ch2_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch2_i_net: std_logic_vector(15 downto 0);
signal adc_ch3_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch3_i_net: std_logic_vector(15 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert10_dout_net_x2: std_logic;
signal assert10_dout_net_x3: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert11_dout_net_x2: std_logic_vector(24 downto 0);
signal assert11_dout_net_x3: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert12_dout_net_x2: std_logic;
signal assert12_dout_net_x3: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x2: std_logic_vector(24 downto 0);
signal assert5_dout_net_x3: std_logic_vector(24 downto 0);
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert8_dout_net_x2: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert9_dout_net_x2: std_logic;
signal assert9_dout_net_x3: std_logic;
signal bpf_ch0_o_net: std_logic_vector(23 downto 0);
signal bpf_ch1_o_net: std_logic_vector(23 downto 0);
signal bpf_ch2_o_net: std_logic_vector(23 downto 0);
signal bpf_ch3_o_net: std_logic_vector(23 downto 0);
signal ce_10000_sg_x2: std_logic;
signal ce_1120_sg_x32: std_logic;
signal ce_1400000_sg_x3: std_logic;
signal ce_1_sg_x96: std_logic;
signal ce_224000000_sg_x7: std_logic;
signal ce_22400000_sg_x28: std_logic;
signal ce_2240_sg_x28: std_logic;
signal ce_2500_sg_x3: std_logic;
signal ce_2800000_sg_x4: std_logic;
signal ce_2_sg_x38: std_logic;
signal ce_35_sg_x22: std_logic;
signal ce_44800000_sg_x2: std_logic;
signal ce_4480_sg_x9: std_logic;
signal ce_5000_sg_x9: std_logic;
signal ce_56000000_sg_x5: std_logic;
signal ce_5600000_sg_x12: std_logic;
signal ce_560_sg_x3: std_logic;
signal ce_70_sg_x27: std_logic;
signal ce_logic_1400000_sg_x2: std_logic;
signal ce_logic_1_sg_x20: std_logic;
signal ce_logic_22400000_sg_x1: std_logic;
signal ce_logic_2240_sg_x1: std_logic;
signal ce_logic_2800000_sg_x2: std_logic;
signal ce_logic_5600000_sg_x2: std_logic;
signal ce_logic_560_sg_x3: std_logic;
signal ce_logic_70_sg_x1: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal cic_fofb_q_01_missing_o_net: std_logic;
signal cic_fofb_q_23_missing_o_net: std_logic;
signal clk_10000_sg_x2: std_logic;
signal clk_1120_sg_x32: std_logic;
signal clk_1400000_sg_x3: std_logic;
signal clk_1_sg_x96: std_logic;
signal clk_224000000_sg_x7: std_logic;
signal clk_22400000_sg_x28: std_logic;
signal clk_2240_sg_x28: std_logic;
signal clk_2500_sg_x3: std_logic;
signal clk_2800000_sg_x4: std_logic;
signal clk_2_sg_x38: std_logic;
signal clk_35_sg_x22: std_logic;
signal clk_44800000_sg_x2: std_logic;
signal clk_4480_sg_x9: std_logic;
signal clk_5000_sg_x9: std_logic;
signal clk_56000000_sg_x5: std_logic;
signal clk_5600000_sg_x12: std_logic;
signal clk_560_sg_x3: std_logic;
signal clk_70_sg_x27: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant15_op_net_x1: std_logic;
signal constant3_op_net_x1: std_logic;
signal dds_config_valid_ch0_i_net: std_logic;
signal dds_config_valid_ch1_i_net: std_logic;
signal dds_config_valid_ch2_i_net: std_logic;
signal dds_config_valid_ch3_i_net: std_logic;
signal dds_pinc_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch3_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch3_i_net: std_logic_vector(29 downto 0);
signal del_sig_div_fofb_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_monit_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_tbt_thres_i_net: std_logic_vector(25 downto 0);
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_down_x2: std_logic_vector(24 downto 0);
signal dout_down_x3: std_logic_vector(24 downto 0);
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal fofb_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ksum_i_net: std_logic_vector(24 downto 0);
signal kx_i_net: std_logic_vector(24 downto 0);
signal ky_i_net: std_logic_vector(24 downto 0);
signal mix_ch0_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch0_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_q_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal monit_cfir_incorrect_o_net: std_logic;
signal monit_cic_unexpected_o_net: std_logic;
signal monit_pfir_incorrect_o_net: std_logic;
signal monit_pos_1_incorrect_o_net: std_logic;
signal q_fofb_o_net: std_logic_vector(25 downto 0);
signal q_fofb_valid_o_net: std_logic;
signal q_monit_1_o_net: std_logic_vector(25 downto 0);
signal q_monit_1_valid_o_net: std_logic;
signal q_monit_o_net: std_logic_vector(25 downto 0);
signal q_monit_valid_o_net: std_logic;
signal q_tbt_o_net: std_logic_vector(25 downto 0);
signal q_tbt_valid_o_net: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x31: std_logic_vector(23 downto 0);
signal register_q_net_x32: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal sum_fofb_o_net: std_logic_vector(25 downto 0);
signal sum_fofb_valid_o_net: std_logic;
signal sum_monit_1_o_net: std_logic_vector(25 downto 0);
signal sum_monit_1_valid_o_net: std_logic;
signal sum_monit_o_net: std_logic_vector(25 downto 0);
signal sum_monit_valid_o_net: std_logic;
signal sum_tbt_o_net: std_logic_vector(25 downto 0);
signal sum_tbt_valid_o_net: std_logic;
signal tbt_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch01_incorrect_o_net: std_logic;
signal tbt_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch23_incorrect_o_net: std_logic;
signal tbt_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
signal valid_ds_down_x1: std_logic;
signal valid_ds_down_x2: std_logic;
signal valid_ds_down_x3: std_logic;
signal x_fofb_o_net: std_logic_vector(25 downto 0);
signal x_fofb_valid_o_net: std_logic;
signal x_monit_1_o_net: std_logic_vector(25 downto 0);
signal x_monit_1_valid_o_net: std_logic;
signal x_monit_o_net: std_logic_vector(25 downto 0);
signal x_monit_valid_o_net: std_logic;
signal x_tbt_o_net: std_logic_vector(25 downto 0);
signal x_tbt_valid_o_net: std_logic;
signal y_fofb_o_net: std_logic_vector(25 downto 0);
signal y_fofb_valid_o_net: std_logic;
signal y_monit_1_o_net: std_logic_vector(25 downto 0);
signal y_monit_1_valid_o_net: std_logic;
signal y_monit_o_net: std_logic_vector(25 downto 0);
signal y_monit_valid_o_net: std_logic;
signal y_tbt_o_net: std_logic_vector(25 downto 0);
signal y_tbt_valid_o_net: std_logic;
begin
adc_ch0_i_net <= adc_ch0_i;
adc_ch1_i_net <= adc_ch1_i;
adc_ch2_i_net <= adc_ch2_i;
adc_ch3_i_net <= adc_ch3_i;
ce_1_sg_x96 <= ce_1;
ce_10000_sg_x2 <= ce_10000;
ce_1120_sg_x32 <= ce_1120;
ce_1400000_sg_x3 <= ce_1400000;
ce_2_sg_x38 <= ce_2;
ce_2240_sg_x28 <= ce_2240;
ce_22400000_sg_x28 <= ce_22400000;
ce_224000000_sg_x7 <= ce_224000000;
ce_2500_sg_x3 <= ce_2500;
ce_2800000_sg_x4 <= ce_2800000;
ce_35_sg_x22 <= ce_35;
ce_4480_sg_x9 <= ce_4480;
ce_44800000_sg_x2 <= ce_44800000;
ce_5000_sg_x9 <= ce_5000;
ce_560_sg_x3 <= ce_560;
ce_5600000_sg_x12 <= ce_5600000;
ce_56000000_sg_x5 <= ce_56000000;
ce_70_sg_x27 <= ce_70;
ce_logic_1_sg_x20 <= ce_logic_1;
ce_logic_1400000_sg_x2 <= ce_logic_1400000;
ce_logic_2240_sg_x1 <= ce_logic_2240;
ce_logic_22400000_sg_x1 <= ce_logic_22400000;
ce_logic_2800000_sg_x2 <= ce_logic_2800000;
ce_logic_560_sg_x3 <= ce_logic_560;
ce_logic_5600000_sg_x2 <= ce_logic_5600000;
ce_logic_70_sg_x1 <= ce_logic_70;
clk_1_sg_x96 <= clk_1;
clk_10000_sg_x2 <= clk_10000;
clk_1120_sg_x32 <= clk_1120;
clk_1400000_sg_x3 <= clk_1400000;
clk_2_sg_x38 <= clk_2;
clk_2240_sg_x28 <= clk_2240;
clk_22400000_sg_x28 <= clk_22400000;
clk_224000000_sg_x7 <= clk_224000000;
clk_2500_sg_x3 <= clk_2500;
clk_2800000_sg_x4 <= clk_2800000;
clk_35_sg_x22 <= clk_35;
clk_4480_sg_x9 <= clk_4480;
clk_44800000_sg_x2 <= clk_44800000;
clk_5000_sg_x9 <= clk_5000;
clk_560_sg_x3 <= clk_560;
clk_5600000_sg_x12 <= clk_5600000;
clk_56000000_sg_x5 <= clk_56000000;
clk_70_sg_x27 <= clk_70;
dds_config_valid_ch0_i_net <= dds_config_valid_ch0_i;
dds_config_valid_ch1_i_net <= dds_config_valid_ch1_i;
dds_config_valid_ch2_i_net <= dds_config_valid_ch2_i;
dds_config_valid_ch3_i_net <= dds_config_valid_ch3_i;
dds_pinc_ch0_i_net <= dds_pinc_ch0_i;
dds_pinc_ch1_i_net <= dds_pinc_ch1_i;
dds_pinc_ch2_i_net <= dds_pinc_ch2_i;
dds_pinc_ch3_i_net <= dds_pinc_ch3_i;
dds_poff_ch0_i_net <= dds_poff_ch0_i;
dds_poff_ch1_i_net <= dds_poff_ch1_i;
dds_poff_ch2_i_net <= dds_poff_ch2_i;
dds_poff_ch3_i_net <= dds_poff_ch3_i;
del_sig_div_fofb_thres_i_net <= del_sig_div_fofb_thres_i;
del_sig_div_monit_thres_i_net <= del_sig_div_monit_thres_i;
del_sig_div_tbt_thres_i_net <= del_sig_div_tbt_thres_i;
ksum_i_net <= ksum_i;
kx_i_net <= kx_i;
ky_i_net <= ky_i;
adc_ch0_dbg_data_o <= adc_ch0_dbg_data_o_net;
adc_ch1_dbg_data_o <= adc_ch1_dbg_data_o_net;
adc_ch2_dbg_data_o <= adc_ch2_dbg_data_o_net;
adc_ch3_dbg_data_o <= adc_ch3_dbg_data_o_net;
bpf_ch0_o <= bpf_ch0_o_net;
bpf_ch1_o <= bpf_ch1_o_net;
bpf_ch2_o <= bpf_ch2_o_net;
bpf_ch3_o <= bpf_ch3_o_net;
cic_fofb_q_01_missing_o <= cic_fofb_q_01_missing_o_net;
cic_fofb_q_23_missing_o <= cic_fofb_q_23_missing_o_net;
fofb_amp_ch0_o <= fofb_amp_ch0_o_net;
fofb_amp_ch1_o <= fofb_amp_ch1_o_net;
fofb_amp_ch2_o <= fofb_amp_ch2_o_net;
fofb_amp_ch3_o <= fofb_amp_ch3_o_net;
fofb_decim_ch0_i_o <= fofb_decim_ch0_i_o_net;
fofb_decim_ch0_q_o <= fofb_decim_ch0_q_o_net;
fofb_decim_ch1_i_o <= fofb_decim_ch1_i_o_net;
fofb_decim_ch1_q_o <= fofb_decim_ch1_q_o_net;
fofb_decim_ch2_i_o <= fofb_decim_ch2_i_o_net;
fofb_decim_ch2_q_o <= fofb_decim_ch2_q_o_net;
fofb_decim_ch3_i_o <= fofb_decim_ch3_i_o_net;
fofb_decim_ch3_q_o <= fofb_decim_ch3_q_o_net;
fofb_pha_ch0_o <= fofb_pha_ch0_o_net;
fofb_pha_ch1_o <= fofb_pha_ch1_o_net;
fofb_pha_ch2_o <= fofb_pha_ch2_o_net;
fofb_pha_ch3_o <= fofb_pha_ch3_o_net;
mix_ch0_i_o <= mix_ch0_i_o_net;
mix_ch0_q_o <= mix_ch0_q_o_net;
mix_ch1_i_o <= mix_ch1_i_o_net;
mix_ch1_q_o <= mix_ch1_q_o_net;
mix_ch2_i_o <= mix_ch2_i_o_net;
mix_ch2_q_o <= mix_ch2_q_o_net;
mix_ch3_i_o <= mix_ch3_i_o_net;
mix_ch3_q_o <= mix_ch3_q_o_net;
monit_amp_ch0_o <= monit_amp_ch0_o_net;
monit_amp_ch1_o <= monit_amp_ch1_o_net;
monit_amp_ch2_o <= monit_amp_ch2_o_net;
monit_amp_ch3_o <= monit_amp_ch3_o_net;
monit_cfir_incorrect_o <= monit_cfir_incorrect_o_net;
monit_cic_unexpected_o <= monit_cic_unexpected_o_net;
monit_pfir_incorrect_o <= monit_pfir_incorrect_o_net;
monit_pos_1_incorrect_o <= monit_pos_1_incorrect_o_net;
q_fofb_o <= q_fofb_o_net;
q_fofb_valid_o <= q_fofb_valid_o_net;
q_monit_1_o <= q_monit_1_o_net;
q_monit_1_valid_o <= q_monit_1_valid_o_net;
q_monit_o <= q_monit_o_net;
q_monit_valid_o <= q_monit_valid_o_net;
q_tbt_o <= q_tbt_o_net;
q_tbt_valid_o <= q_tbt_valid_o_net;
sum_fofb_o <= sum_fofb_o_net;
sum_fofb_valid_o <= sum_fofb_valid_o_net;
sum_monit_1_o <= sum_monit_1_o_net;
sum_monit_1_valid_o <= sum_monit_1_valid_o_net;
sum_monit_o <= sum_monit_o_net;
sum_monit_valid_o <= sum_monit_valid_o_net;
sum_tbt_o <= sum_tbt_o_net;
sum_tbt_valid_o <= sum_tbt_valid_o_net;
tbt_amp_ch0_o <= tbt_amp_ch0_o_net;
tbt_amp_ch1_o <= tbt_amp_ch1_o_net;
tbt_amp_ch2_o <= tbt_amp_ch2_o_net;
tbt_amp_ch3_o <= tbt_amp_ch3_o_net;
tbt_decim_ch01_incorrect_o <= tbt_decim_ch01_incorrect_o_net;
tbt_decim_ch0_i_o <= tbt_decim_ch0_i_o_net;
tbt_decim_ch0_q_o <= tbt_decim_ch0_q_o_net;
tbt_decim_ch1_i_o <= tbt_decim_ch1_i_o_net;
tbt_decim_ch1_q_o <= tbt_decim_ch1_q_o_net;
tbt_decim_ch23_incorrect_o <= tbt_decim_ch23_incorrect_o_net;
tbt_decim_ch2_i_o <= tbt_decim_ch2_i_o_net;
tbt_decim_ch2_q_o <= tbt_decim_ch2_q_o_net;
tbt_decim_ch3_i_o <= tbt_decim_ch3_i_o_net;
tbt_decim_ch3_q_o <= tbt_decim_ch3_q_o_net;
tbt_pha_ch0_o <= tbt_pha_ch0_o_net;
tbt_pha_ch1_o <= tbt_pha_ch1_o_net;
tbt_pha_ch2_o <= tbt_pha_ch2_o_net;
tbt_pha_ch3_o <= tbt_pha_ch3_o_net;
x_fofb_o <= x_fofb_o_net;
x_fofb_valid_o <= x_fofb_valid_o_net;
x_monit_1_o <= x_monit_1_o_net;
x_monit_1_valid_o <= x_monit_1_valid_o_net;
x_monit_o <= x_monit_o_net;
x_monit_valid_o <= x_monit_valid_o_net;
x_tbt_o <= x_tbt_o_net;
x_tbt_valid_o <= x_tbt_valid_o_net;
y_fofb_o <= y_fofb_o_net;
y_fofb_valid_o <= y_fofb_valid_o_net;
y_monit_1_o <= y_monit_1_o_net;
y_monit_1_valid_o <= y_monit_1_valid_o_net;
y_monit_o <= y_monit_o_net;
y_monit_valid_o <= y_monit_valid_o_net;
y_tbt_o <= y_tbt_o_net;
y_tbt_valid_o <= y_tbt_valid_o_net;
bpf_d31c4af409: entity work.bpf_entity_d31c4af409
port map (
din_ch0 => adc_ch0_dbg_data_o_net,
din_ch1 => adc_ch1_dbg_data_o_net,
din_ch2 => adc_ch2_dbg_data_o_net,
din_ch3 => adc_ch3_dbg_data_o_net,
dout_ch0 => bpf_ch0_o_net,
dout_ch1 => bpf_ch1_o_net,
dout_ch2 => bpf_ch2_o_net,
dout_ch3 => bpf_ch3_o_net
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert12_dout_net_x2,
in1 => reinterpret1_output_port_net,
y => concat_y_net_x0
);
concat1: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => valid_ds_down_x2,
in1 => reinterpret2_output_port_net,
y => concat1_y_net_x0
);
concat2: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert9_dout_net_x2,
in1 => reinterpret3_output_port_net,
y => concat2_y_net_x0
);
concat3: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert10_dout_net_x2,
in1 => reinterpret4_output_port_net,
y => concat3_y_net_x0
);
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant15: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant15_op_net_x1
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net_x1
);
convert_filt_fda412c1bf: entity work.convert_filt_entity_fda412c1bf
port map (
din => down_sample_q_net_x4,
dout => reinterpret5_output_port_net_x1
);
dds_sub_a4b6b880f6: entity work.dds_sub_entity_a4b6b880f6
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_01_cosine => register_q_net_x12,
dds_01_sine => register_q_net_x13,
dds_23_cosine => register_q_net_x14,
dds_23_sine => register_q_net_x15
);
delta_sigma_fofb_ee61e649ea: entity work.delta_sigma_fofb_entity_ee61e649ea
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
c => down_sample2_q_net_x21,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_logic_2240 => ce_logic_2240_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
d => down_sample1_q_net_x21,
ds_thres => del_sig_div_fofb_thres_i_net,
q => assert8_dout_net_x1,
q_valid => assert9_dout_net_x1,
sum_valid => assert12_dout_net_x1,
sum_x0 => assert11_dout_net_x1,
x => assert5_dout_net_x1,
x_valid => assert10_dout_net_x1,
y => dout_down_x1,
y_valid => valid_ds_down_x1
);
delta_sigma_monit_a8f8b81626: entity work.delta_sigma_monit_entity_a8f8b81626
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
c => down_sample3_q_net_x5,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
d => down_sample4_q_net_x5,
ds_thres => del_sig_div_monit_thres_i_net,
q => assert4_dout_net_x1,
q_valid => assert9_dout_net_x2,
sum_valid => assert10_dout_net_x2,
sum_x0 => assert5_dout_net_x2,
x => assert11_dout_net_x2,
x_valid => assert12_dout_net_x2,
y => dout_down_x2,
y_valid => valid_ds_down_x2
);
delta_sigma_tbt_bbfa8a8a69: entity work.delta_sigma_tbt_entity_bbfa8a8a69
port map (
a => down_sample2_q_net_x34,
b => down_sample1_q_net_x34,
c => down_sample2_q_net_x35,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
d => down_sample1_q_net_x35,
ds_thres => del_sig_div_tbt_thres_i_net,
q => assert8_dout_net_x2,
q_valid => assert9_dout_net_x3,
sum_valid => assert12_dout_net_x3,
sum_x0 => assert11_dout_net_x3,
x => assert5_dout_net_x3,
x_valid => assert10_dout_net_x3,
y => dout_down_x3,
y_valid => valid_ds_down_x3
);
fofb_amp_8b25d4b0b6: entity work.fofb_amp_entity_8b25d4b0b6
port map (
ce_1 => ce_1_sg_x96,
ce_1120 => ce_1120_sg_x32,
ce_2240 => ce_2240_sg_x28,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_1120 => clk_1120_sg_x32,
clk_2240 => clk_2240_sg_x28,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x20,
amp_out1 => down_sample1_q_net_x20,
amp_out2 => down_sample2_q_net_x21,
amp_out3 => down_sample1_q_net_x21,
fofb_amp0 => fofb_amp_ch1_o_net,
fofb_amp0_x0 => fofb_amp_ch0_o_net,
fofb_amp0_x1 => fofb_pha_ch1_o_net,
fofb_amp0_x2 => fofb_pha_ch0_o_net,
fofb_amp0_x3 => fofb_decim_ch1_i_o_net,
fofb_amp0_x4 => fofb_decim_ch0_i_o_net,
fofb_amp0_x5 => fofb_decim_ch1_q_o_net,
fofb_amp0_x6 => fofb_decim_ch0_q_o_net,
fofb_amp0_x7 => cic_fofb_q_01_missing_o_net,
fofb_amp1 => fofb_amp_ch3_o_net,
fofb_amp1_x0 => fofb_amp_ch2_o_net,
fofb_amp1_x1 => fofb_pha_ch3_o_net,
fofb_amp1_x2 => fofb_pha_ch2_o_net,
fofb_amp1_x3 => fofb_decim_ch3_i_o_net,
fofb_amp1_x4 => fofb_decim_ch2_i_o_net,
fofb_amp1_x5 => fofb_decim_ch3_q_o_net,
fofb_amp1_x6 => fofb_decim_ch2_q_o_net,
fofb_amp1_x7 => cic_fofb_q_23_missing_o_net
);
k_fofb_mult3_697accc8e2: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert5_dout_net_x1,
in2 => kx_i_net,
vld_in => assert10_dout_net_x1,
out1 => x_fofb_o_net,
vld_out => x_fofb_valid_o_net
);
k_fofb_mult4_102b49a84e: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => dout_down_x1,
in2 => ky_i_net,
vld_in => valid_ds_down_x1,
out1 => y_fofb_o_net,
vld_out => y_fofb_valid_o_net
);
k_fofb_mult5_ed47def699: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert8_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x1,
out1 => q_fofb_o_net,
vld_out => q_fofb_valid_o_net
);
k_monit_1_mult2_30ad492eba: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret1_output_port_net_x1,
in2 => ky_i_net,
vld_in => ufix_to_bool1_dout_net_x1,
out1 => y_monit_1_o_net,
vld_out => y_monit_1_valid_o_net
);
k_monit_1_mult6_71da64dfef: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret2_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool2_dout_net_x1,
out1 => q_monit_1_o_net,
vld_out => q_monit_1_valid_o_net
);
k_monit_1_mult_016885a3ac: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret3_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool_dout_net_x1,
out1 => x_monit_1_o_net,
vld_out => x_monit_1_valid_o_net
);
k_monit_mult3_8a778fb5f4: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert11_dout_net_x2,
in2 => kx_i_net,
vld_in => assert12_dout_net_x2,
out1 => x_monit_o_net,
vld_out => x_monit_valid_o_net
);
k_monit_mult4_1b07b5102a: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => dout_down_x2,
in2 => ky_i_net,
vld_in => valid_ds_down_x2,
out1 => y_monit_o_net,
vld_out => y_monit_valid_o_net
);
k_monit_mult5_a064f6aaae: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert4_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x2,
out1 => q_monit_o_net,
vld_out => q_monit_valid_o_net
);
k_tbt_mult1_cebfa469e3: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => dout_down_x3,
in2 => ky_i_net,
vld_in => valid_ds_down_x3,
out1 => y_tbt_o_net,
vld_out => y_tbt_valid_o_net
);
k_tbt_mult2_2b721a52a5: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert8_dout_net_x2,
in2 => kx_i_net,
vld_in => assert9_dout_net_x3,
out1 => q_tbt_o_net,
vld_out => q_tbt_valid_o_net
);
k_tbt_mult_b8fafff255: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert5_dout_net_x3,
in2 => kx_i_net,
vld_in => assert10_dout_net_x3,
out1 => x_tbt_o_net,
vld_out => x_tbt_valid_o_net
);
ksum_fofb_mult4_ac3ed97096: entity work.ksum_fofb_mult4_entity_ac3ed97096
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert11_dout_net_x1,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x1,
out1 => sum_fofb_o_net,
vld_out => sum_fofb_valid_o_net
);
ksum_monit_1_mult1_c66dc07078: entity work.ksum_monit_1_mult1_entity_c66dc07078
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret4_output_port_net_x1,
in2 => ksum_i_net,
vld_in => ufix_to_bool3_dout_net_x1,
out1 => sum_monit_1_o_net,
vld_out => sum_monit_1_valid_o_net
);
ksum_monit_mult2_31877b6d2b: entity work.ksum_monit_mult2_entity_31877b6d2b
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert5_dout_net_x2,
in2 => ksum_i_net,
vld_in => assert10_dout_net_x2,
out1 => sum_monit_o_net,
vld_out => sum_monit_valid_o_net
);
ksum_tbt_mult3_e0be30d675: entity work.ksum_tbt_mult3_entity_e0be30d675
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert11_dout_net_x3,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x3,
out1 => sum_tbt_o_net,
vld_out => sum_tbt_valid_o_net
);
mixer_a1cd828545: entity work.mixer_entity_a1cd828545
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ch_in0 => register1_q_net_x6,
ch_in1 => register1_q_net_x7,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_cosine_0 => register_q_net_x12,
dds_cosine_1 => register_q_net_x14,
dds_msine_0 => register_q_net_x13,
dds_msine_1 => register_q_net_x15,
dds_valid_0 => constant15_op_net_x1,
dds_valid_1 => constant3_op_net_x1,
din0 => register_q_net_x31,
din1 => register_q_net_x32,
ch_out0 => register3_q_net_x15,
ch_out1 => register3_q_net_x16,
i_out0 => register4_q_net_x14,
i_out1 => register4_q_net_x15,
q_out0 => register5_q_net_x14,
q_out1 => register5_q_net_x15,
tddm_mixer => mix_ch1_i_o_net,
tddm_mixer_x0 => mix_ch0_i_o_net,
tddm_mixer_x1 => mix_ch1_q_o_net,
tddm_mixer_x2 => mix_ch0_q_o_net,
tddm_mixer_x3 => mix_ch3_i_o_net,
tddm_mixer_x4 => mix_ch2_i_o_net,
tddm_mixer_x5 => mix_ch3_q_o_net,
tddm_mixer_x6 => mix_ch2_q_o_net
);
monit_amp_44da74e268: entity work.monit_amp_entity_44da74e268
port map (
ce_1 => ce_1_sg_x96,
ce_1400000 => ce_1400000_sg_x3,
ce_22400000 => ce_22400000_sg_x28,
ce_2800000 => ce_2800000_sg_x4,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ch_in => ch_out_x2,
clk_1 => clk_1_sg_x96,
clk_1400000 => clk_1400000_sg_x3,
clk_22400000 => clk_22400000_sg_x28,
clk_2800000 => clk_2800000_sg_x4,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din => dout_x2,
amp_out0 => down_sample2_q_net_x5,
amp_out1 => down_sample1_q_net_x5,
amp_out2 => down_sample3_q_net_x5,
amp_out3 => down_sample4_q_net_x5,
monit_amp_c => monit_amp_ch1_o_net,
monit_amp_c_x0 => monit_amp_ch0_o_net,
monit_amp_c_x1 => monit_amp_ch2_o_net,
monit_amp_c_x2 => monit_amp_ch3_o_net,
monit_amp_c_x3 => monit_cfir_incorrect_o_net,
monit_amp_c_x4 => monit_cic_unexpected_o_net,
monit_amp_c_x5 => monit_pfir_incorrect_o_net
);
monit_pos_1_522c8cf08d: entity work.monit_pos_1_entity_522c8cf08d
port map (
ce_1 => ce_1_sg_x96,
ce_224000000 => ce_224000000_sg_x7,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ch_in => down_sample_q_net_x3,
clk_1 => clk_1_sg_x96,
clk_224000000 => clk_224000000_sg_x7,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
din => reinterpret5_output_port_net_x1,
monit_1_pos_q => reinterpret2_output_port_net_x1,
monit_1_pos_x => reinterpret3_output_port_net_x1,
monit_1_pos_y => reinterpret1_output_port_net_x1,
monit_1_sum => reinterpret4_output_port_net_x1,
monit_1_vld_q => ufix_to_bool2_dout_net_x1,
monit_1_vld_sum => ufix_to_bool3_dout_net_x1,
monit_1_vld_x => ufix_to_bool_dout_net_x1,
monit_1_vld_y => ufix_to_bool1_dout_net_x1,
monit_pos_1_c_x0 => monit_pos_1_incorrect_o_net
);
register1: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch1_i_net,
en => "1",
rst => "0",
q => adc_ch1_dbg_data_o_net
);
register2: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch2_i_net,
en => "1",
rst => "0",
q => adc_ch2_dbg_data_o_net
);
register3: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch3_i_net,
en => "1",
rst => "0",
q => adc_ch3_dbg_data_o_net
);
register_x0: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch0_i_net,
en => "1",
rst => "0",
q => adc_ch0_dbg_data_o_net
);
reinterpret1: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert11_dout_net_x2,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => dout_down_x2,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert4_dout_net_x1,
output_port => reinterpret3_output_port_net
);
reinterpret4: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert5_dout_net_x2,
output_port => reinterpret4_output_port_net
);
tbt_amp_cbd277bb0c: entity work.tbt_amp_entity_cbd277bb0c
port map (
ce_1 => ce_1_sg_x96,
ce_35 => ce_35_sg_x22,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_35 => clk_35_sg_x22,
clk_70 => clk_70_sg_x27,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x34,
amp_out1 => down_sample1_q_net_x34,
amp_out2 => down_sample2_q_net_x35,
amp_out3 => down_sample1_q_net_x35,
tbt_amp0 => tbt_amp_ch1_o_net,
tbt_amp0_x0 => tbt_amp_ch0_o_net,
tbt_amp0_x1 => tbt_pha_ch1_o_net,
tbt_amp0_x2 => tbt_pha_ch0_o_net,
tbt_amp0_x3 => tbt_decim_ch01_incorrect_o_net,
tbt_amp0_x4 => tbt_decim_ch1_i_o_net,
tbt_amp0_x5 => tbt_decim_ch0_i_o_net,
tbt_amp0_x6 => tbt_decim_ch1_q_o_net,
tbt_amp0_x7 => tbt_decim_ch0_q_o_net,
tbt_amp1 => tbt_amp_ch3_o_net,
tbt_amp1_x0 => tbt_amp_ch2_o_net,
tbt_amp1_x1 => tbt_pha_ch3_o_net,
tbt_amp1_x2 => tbt_pha_ch2_o_net,
tbt_amp1_x3 => tbt_decim_ch23_incorrect_o_net,
tbt_amp1_x4 => tbt_decim_ch3_i_o_net,
tbt_amp1_x5 => tbt_decim_ch2_i_o_net,
tbt_amp1_x6 => tbt_decim_ch3_q_o_net,
tbt_amp1_x7 => tbt_decim_ch2_q_o_net
);
tdm_mix_54ce67e6e8: entity work.tdm_mix_entity_54ce67e6e8
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
din_ch0 => bpf_ch0_o_net,
din_ch1 => bpf_ch1_o_net,
din_ch2 => bpf_ch2_o_net,
din_ch3 => bpf_ch3_o_net,
ch_out0 => register1_q_net_x6,
ch_out1 => register1_q_net_x7,
dout0 => register_q_net_x31,
dout1 => register_q_net_x32
);
tdm_monit_1_746ecf54b0: entity work.tdm_monit_1_entity_746ecf54b0
port map (
ce_1 => ce_1_sg_x96,
ce_22400000 => ce_22400000_sg_x28,
ce_2500 => ce_2500_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
clk_1 => clk_1_sg_x96,
clk_22400000 => clk_22400000_sg_x28,
clk_2500 => clk_2500_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din_ch0 => concat_y_net_x0,
din_ch1 => concat1_y_net_x0,
din_ch2 => concat2_y_net_x0,
din_ch3 => concat3_y_net_x0,
rst => constant11_op_net_x0,
ch_out => down_sample_q_net_x3,
dout => down_sample_q_net_x4
);
tdm_monit_6e38292ecb: entity work.tdm_monit_entity_6e38292ecb
port map (
ce_1 => ce_1_sg_x96,
ce_2240 => ce_2240_sg_x28,
ce_560 => ce_560_sg_x3,
ce_logic_560 => ce_logic_560_sg_x3,
clk_1 => clk_1_sg_x96,
clk_2240 => clk_2240_sg_x28,
clk_560 => clk_560_sg_x3,
din_ch0 => down_sample2_q_net_x20,
din_ch1 => down_sample1_q_net_x20,
din_ch2 => down_sample2_q_net_x21,
din_ch3 => down_sample1_q_net_x21,
rst => constant10_op_net_x0,
ch_out => ch_out_x2,
dout => dout_x2
);
end structural;
|
lgpl-3.0
|
lerwys/GitTest
|
hdl/modules/position_calc/generated/virtex6/cntr_11_0_3166d4cc5b09c744.vhd
|
1
|
4453
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cntr_11_0_3166d4cc5b09c744.vhd when simulating
-- the core, cntr_11_0_3166d4cc5b09c744. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cntr_11_0_3166d4cc5b09c744 IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END cntr_11_0_3166d4cc5b09c744;
ARCHITECTURE cntr_11_0_3166d4cc5b09c744_a OF cntr_11_0_3166d4cc5b09c744 IS
-- synthesis translate_off
COMPONENT wrapped_cntr_11_0_3166d4cc5b09c744
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cntr_11_0_3166d4cc5b09c744 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 1,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 1,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 2,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cntr_11_0_3166d4cc5b09c744
PORT MAP (
clk => clk,
ce => ce,
sinit => sinit,
q => q
);
-- synthesis translate_on
END cntr_11_0_3166d4cc5b09c744_a;
|
lgpl-3.0
|
lerwys/GitTest
|
models/blackboxes/fixed_dds.vhd
|
2
|
4899
|
-------------------------------------------------------------------------------
-- Title : Fixed sin-cos DDS
-- Project :
-------------------------------------------------------------------------------
-- File : fixed_dds.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Fixed frequency phase and quadrature DDS for use in tuned DDCs.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity fixed_dds is
generic (
g_number_of_points : natural := 148;
g_output_width : natural := 24;
g_dither : boolean := false;
g_sin_file : string := "./dds_sin.ram";
g_cos_file : string := "./dds_cos.ram"
);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_n_i : in std_logic;
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0)
);
end entity fixed_dds;
-------------------------------------------------------------------------------
architecture str of fixed_dds is
constant c_bus_size : natural := f_log2_size(g_number_of_points);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0);
component generic_simple_dpram is
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(c_bus_size-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(c_bus_size-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component generic_simple_dpram;
component lut_sweep is
generic (
g_bus_size : natural;
g_first_address : natural;
g_last_address : natural;
g_sweep_mode : string);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(c_bus_size-1 downto 0));
end component lut_sweep;
begin -- architecture str
cmp_sin_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_sin_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => sin_o
);
cmp_cos_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_cos_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => cos_o
);
cmp_sweep : lut_sweep
generic map (
g_bus_size => c_bus_size,
g_first_address => 0,
g_last_address => g_number_of_points-1,
g_sweep_mode => "sawtooth")
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
ce_i => ce_i,
address_o => cur_address);
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
lerwys/GitTest
|
hdl/modules/position_calc/generated/virtex6/cmpy_v5_0_fc1d91881e8e8ae6.vhd
|
1
|
5807
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cmpy_v5_0_fc1d91881e8e8ae6.vhd when simulating
-- the core, cmpy_v5_0_fc1d91881e8e8ae6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cmpy_v5_0_fc1d91881e8e8ae6 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END cmpy_v5_0_fc1d91881e8e8ae6;
ARCHITECTURE cmpy_v5_0_fc1d91881e8e8ae6_a OF cmpy_v5_0_fc1d91881e8e8ae6 IS
-- synthesis translate_off
COMPONENT wrapped_cmpy_v5_0_fc1d91881e8e8ae6
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cmpy_v5_0_fc1d91881e8e8ae6 USE ENTITY XilinxCoreLib.cmpy_v5_0(behavioral)
GENERIC MAP (
c_a_width => 24,
c_b_width => 24,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_s_axis_a_tlast => 0,
c_has_s_axis_a_tuser => 0,
c_has_s_axis_b_tlast => 0,
c_has_s_axis_b_tuser => 1,
c_has_s_axis_ctrl_tlast => 0,
c_has_s_axis_ctrl_tuser => 0,
c_latency => 6,
c_m_axis_dout_tdata_width => 48,
c_m_axis_dout_tuser_width => 1,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_width => 24,
c_s_axis_a_tdata_width => 48,
c_s_axis_a_tuser_width => 1,
c_s_axis_b_tdata_width => 48,
c_s_axis_b_tuser_width => 1,
c_s_axis_ctrl_tdata_width => 8,
c_s_axis_ctrl_tuser_width => 1,
c_throttle_scheme => 3,
c_tlast_resolution => 0,
c_verbosity => 0,
c_xdevice => "xc6vlx240t",
c_xdevicefamily => "virtex6",
has_negate => 0,
round => 0,
single_output => 0,
use_dsp_cascades => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cmpy_v5_0_fc1d91881e8e8ae6
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tuser => s_axis_b_tuser,
s_axis_b_tdata => s_axis_b_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tuser => m_axis_dout_tuser,
m_axis_dout_tdata => m_axis_dout_tdata
);
-- synthesis translate_on
END cmpy_v5_0_fc1d91881e8e8ae6_a;
|
lgpl-3.0
|
lerwys/GitTest
|
hdl/modules/position_calc/generated/artix7/nonleaf_results.vhd
|
1
|
484765
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF/zero_filling1"
entity zero_filling1_entity_d0ac9899b1 is
port (
in1: in std_logic_vector(15 downto 0);
out1: out std_logic_vector(23 downto 0)
);
end zero_filling1_entity_d0ac9899b1;
architecture structural of zero_filling1_entity_d0ac9899b1 is
signal concat_y_net: std_logic_vector(23 downto 0);
signal constant_op_net: std_logic_vector(7 downto 0);
signal register1_q_net_x0: std_logic_vector(15 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(7 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(15 downto 0);
begin
register1_q_net_x0 <= in1;
out1 <= reinterpret2_output_port_net_x0;
concat: entity work.concat_cd3162dc0d
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => reinterpret_output_port_net,
in1 => reinterpret1_output_port_net,
y => concat_y_net
);
constant_x0: entity work.constant_91ef1678ca
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
reinterpret: entity work.reinterpret_7025463ea8
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register1_q_net_x0,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_f21e7f2ddf
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => constant_op_net,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => concat_y_net,
output_port => reinterpret2_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF"
entity bpf_entity_d31c4af409 is
port (
din_ch0: in std_logic_vector(15 downto 0);
din_ch1: in std_logic_vector(15 downto 0);
din_ch2: in std_logic_vector(15 downto 0);
din_ch3: in std_logic_vector(15 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end bpf_entity_d31c4af409;
architecture structural of bpf_entity_d31c4af409 is
signal register1_q_net_x1: std_logic_vector(15 downto 0);
signal register2_q_net_x1: std_logic_vector(15 downto 0);
signal register3_q_net_x1: std_logic_vector(15 downto 0);
signal register_q_net_x1: std_logic_vector(15 downto 0);
signal reinterpret2_output_port_net_x4: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x5: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x6: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x7: std_logic_vector(23 downto 0);
begin
register_q_net_x1 <= din_ch0;
register1_q_net_x1 <= din_ch1;
register2_q_net_x1 <= din_ch2;
register3_q_net_x1 <= din_ch3;
dout_ch0 <= reinterpret2_output_port_net_x7;
dout_ch1 <= reinterpret2_output_port_net_x4;
dout_ch2 <= reinterpret2_output_port_net_x5;
dout_ch3 <= reinterpret2_output_port_net_x6;
zero_filling1_d0ac9899b1: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register1_q_net_x1,
out1 => reinterpret2_output_port_net_x4
);
zero_filling2_d7e27e9bae: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register2_q_net_x1,
out1 => reinterpret2_output_port_net_x5
);
zero_filling3_1ae3b6c91e: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register3_q_net_x1,
out1 => reinterpret2_output_port_net_x6
);
zero_filling4_6d7b2d0c57: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register_q_net_x1,
out1 => reinterpret2_output_port_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub/TDM_dds_ch01_cosine"
entity tdm_dds_ch01_cosine_entity_4b8bfc9243 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
rst: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_dds_ch01_cosine_entity_4b8bfc9243;
architecture structural of tdm_dds_ch01_cosine_entity_4b8bfc9243 is
signal black_box_cos_o_net_x0: std_logic_vector(23 downto 0);
signal ce_1_sg_x0: std_logic;
signal ce_2_sg_x0: std_logic;
signal ce_logic_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal clk_2_sg_x0: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant11_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register4_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x0 <= ce_1;
ce_2_sg_x0 <= ce_2;
ce_logic_1_sg_x0 <= ce_logic_1;
clk_1_sg_x0 <= clk_1;
clk_2_sg_x0 <= clk_2;
black_box_cos_o_net_x0 <= din_ch0;
constant11_op_net_x0 <= rst;
dout <= register_q_net_x0;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x0,
clk => clk_1_sg_x0,
d => register2_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => register2_q_net,
d1 => register3_q_net,
sel(0) => register4_q_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op(0) => mux_sel1_op_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch0_q_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch1_q_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register4_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub"
entity dds_sub_entity_a4b6b880f6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_01_cosine: out std_logic_vector(23 downto 0);
dds_01_sine: out std_logic_vector(23 downto 0);
dds_23_cosine: out std_logic_vector(23 downto 0);
dds_23_sine: out std_logic_vector(23 downto 0)
);
end dds_sub_entity_a4b6b880f6;
architecture structural of dds_sub_entity_a4b6b880f6 is
signal black_box_cos_o_net_x1: std_logic_vector(23 downto 0);
signal black_box_sin_o_net_x1: std_logic_vector(23 downto 0);
signal ce_1_sg_x4: std_logic;
signal ce_2_sg_x4: std_logic;
signal ce_logic_1_sg_x4: std_logic;
signal clk_1_sg_x4: std_logic;
signal clk_2_sg_x4: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant16_op_net_x0: std_logic;
signal constant17_op_net_x0: std_logic;
signal constant3_op_net: std_logic;
signal constant7_op_net_x0: std_logic;
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
begin
ce_1_sg_x4 <= ce_1;
ce_2_sg_x4 <= ce_2;
ce_logic_1_sg_x4 <= ce_logic_1;
clk_1_sg_x4 <= clk_1;
clk_2_sg_x4 <= clk_2;
dds_01_cosine <= register_q_net_x4;
dds_01_sine <= register_q_net_x5;
dds_23_cosine <= register_q_net_x6;
dds_23_sine <= register_q_net_x7;
black_box: entity work.fixed_dds
generic map (
g_cos_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_cos.ram",
g_dither => false,
g_number_of_points => 148,
g_output_width => 24,
g_sin_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_sin.ram"
)
port map (
ce_i => ce_2_sg_x4,
clk_i => clk_2_sg_x4,
rst_n_i => constant3_op_net,
cos_o => black_box_cos_o_net_x1,
sin_o => black_box_sin_o_net_x1
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant16: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant16_op_net_x0
);
constant17: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant17_op_net_x0
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net
);
constant7: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant7_op_net_x0
);
tdm_dds_ch01_cosine_4b8bfc9243: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant11_op_net_x0,
dout => register_q_net_x4
);
tdm_dds_ch01_sine_1129eb9762: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant7_op_net_x0,
dout => register_q_net_x5
);
tdm_dds_ch23_cosine_398d5cee32: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant16_op_net_x0,
dout => register_q_net_x6
);
tdm_dds_ch23_sine_782ff6a42a: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant17_op_net_x0,
dout => register_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch/TDDM_fofb_amp0"
entity tddm_fofb_amp0_entity_fd74c6ad6e is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp0_entity_fd74c6ad6e;
architecture structural of tddm_fofb_amp0_entity_fd74c6ad6e is
signal assert2_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x0: std_logic;
signal ce_1120_sg_x0: std_logic;
signal ce_2240_sg_x0: std_logic;
signal clk_1120_sg_x0: std_logic;
signal clk_2240_sg_x0: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x0 <= ce_1120;
ce_2240_sg_x0 <= ce_2240;
assert3_dout_net_x0 <= ch_in;
clk_1120_sg_x0 <= clk_1120;
clk_2240_sg_x0 <= clk_2240;
assert2_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant1_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch"
entity tddm_fofb_amp_4ch_entity_2cc521a83f is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp_4ch_entity_2cc521a83f;
architecture structural of tddm_fofb_amp_4ch_entity_2cc521a83f is
signal assert2_dout_net_x2: std_logic_vector(23 downto 0);
signal assert2_dout_net_x3: std_logic_vector(23 downto 0);
signal assert3_dout_net_x2: std_logic;
signal assert3_dout_net_x3: std_logic;
signal ce_1120_sg_x2: std_logic;
signal ce_2240_sg_x2: std_logic;
signal clk_1120_sg_x2: std_logic;
signal clk_2240_sg_x2: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
assert2_dout_net_x2 <= amp_in0;
assert2_dout_net_x3 <= amp_in1;
ce_1120_sg_x2 <= ce_1120;
ce_2240_sg_x2 <= ce_2240;
assert3_dout_net_x2 <= ch_in0;
assert3_dout_net_x3 <= ch_in1;
clk_1120_sg_x2 <= clk_1120;
clk_2240_sg_x2 <= clk_2240;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_fofb_amp0_fd74c6ad6e: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x2,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x2,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_amp1_61cbc8ec65: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x3,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_b60a69fd9b is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_b60a69fd9b;
architecture structural of tddm_tbt_cordic1_entity_b60a69fd9b is
signal assert1_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x4: std_logic;
signal ce_1120_sg_x4: std_logic;
signal ce_2240_sg_x4: std_logic;
signal clk_1120_sg_x4: std_logic;
signal clk_2240_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x4 <= ce_1120;
ce_2240_sg_x4 <= ce_2240;
assert3_dout_net_x4 <= ch_in;
clk_1120_sg_x4 <= clk_1120;
clk_2240_sg_x4 <= clk_2240;
assert1_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant1_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0"
entity tddm_tbt_cordic0_entity_38de3613fe is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_cordic_ch_in: in std_logic;
fofb_cordic_din: in std_logic_vector(23 downto 0);
fofb_cordic_pin: in std_logic_vector(23 downto 0);
fofb_cordic_data0_out: out std_logic_vector(23 downto 0);
fofb_cordic_data1_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase0_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic0_entity_38de3613fe;
architecture structural of tddm_tbt_cordic0_entity_38de3613fe is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x4: std_logic_vector(23 downto 0);
signal assert3_dout_net_x5: std_logic;
signal ce_1120_sg_x5: std_logic;
signal ce_2240_sg_x5: std_logic;
signal clk_1120_sg_x5: std_logic;
signal clk_2240_sg_x5: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x5 <= ce_1120;
ce_2240_sg_x5 <= ce_2240;
clk_1120_sg_x5 <= clk_1120;
clk_2240_sg_x5 <= clk_2240;
assert3_dout_net_x5 <= fofb_cordic_ch_in;
assert2_dout_net_x4 <= fofb_cordic_din;
assert1_dout_net_x1 <= fofb_cordic_pin;
fofb_cordic_data0_out <= down_sample2_q_net_x2;
fofb_cordic_data1_out <= down_sample1_q_net_x2;
fofb_cordic_phase0_out <= down_sample2_q_net_x3;
fofb_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_fofb_cordic0_int_516d0c2a22: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert2_dout_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_cordic1_b60a69fd9b: entity work.tddm_tbt_cordic1_entity_b60a69fd9b
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert1_dout_net_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC"
entity fofb_cordic_entity_fad57e49ce is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_tbt_cordic0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_fad57e49ce;
architecture structural of fofb_cordic_entity_fad57e49ce is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x5: std_logic_vector(23 downto 0);
signal assert3_dout_net_x6: std_logic;
signal ce_1120_sg_x6: std_logic;
signal ce_1_sg_x5: std_logic;
signal ce_2240_sg_x6: std_logic;
signal clk_1120_sg_x6: std_logic;
signal clk_1_sg_x5: std_logic;
signal clk_2240_sg_x6: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x5 <= ce_1;
ce_1120_sg_x6 <= ce_1120;
ce_2240_sg_x6 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x5 <= clk_1;
clk_1120_sg_x6 <= clk_1120;
clk_2240_sg_x6 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x5;
ch_out <= assert3_dout_net_x6;
tddm_tbt_cordic0 <= down_sample1_q_net_x4;
tddm_tbt_cordic0_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic0_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic0_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x5
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x6
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic0_38de3613fe: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x6,
ce_2240 => ce_2240_sg_x6,
clk_1120 => clk_1120_sg_x6,
clk_2240 => clk_2240_sg_x6,
fofb_cordic_ch_in => assert3_dout_net_x6,
fofb_cordic_din => assert2_dout_net_x5,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/Reg"
entity reg_entity_cf7aa296b2 is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end reg_entity_cf7aa296b2;
architecture structural of reg_entity_cf7aa296b2 is
signal ce_1120_sg_x7: std_logic;
signal clk_1120_sg_x7: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
begin
ce_1120_sg_x7 <= ce_1120;
clk_1120_sg_x7 <= clk_1120;
register_q_net_x2 <= din;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 23,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
d => convert_dout_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x2,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/TDDM_fofb_cic0"
entity tddm_fofb_cic0_entity_6b909292ff is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_ch_in: in std_logic;
fofb_i_in: in std_logic_vector(23 downto 0);
fofb_q_in: in std_logic_vector(23 downto 0);
cic_fofb_ch0_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch0_q_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_fofb_cic0_entity_6b909292ff;
architecture structural of tddm_fofb_cic0_entity_6b909292ff is
signal ce_1120_sg_x11: std_logic;
signal ce_2240_sg_x9: std_logic;
signal clk_1120_sg_x11: std_logic;
signal clk_2240_sg_x9: std_logic;
signal delay_q_net_x3: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x11 <= ce_1120;
ce_2240_sg_x9 <= ce_2240;
clk_1120_sg_x11 <= clk_1120;
clk_2240_sg_x9 <= clk_2240;
delay_q_net_x3 <= fofb_ch_in;
register_q_net_x4 <= fofb_i_in;
register_q_net_x3 <= fofb_q_in;
cic_fofb_ch0_i_out <= down_sample2_q_net_x2;
cic_fofb_ch0_q_out <= down_sample2_q_net_x3;
cic_fofb_ch1_i_out <= down_sample1_q_net_x2;
cic_fofb_ch1_q_out <= down_sample1_q_net_x3;
tddm_fofb_cic0_i_06b84397ec: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_cic0_q_a6a1d7c301: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg"
entity reg_entity_71dd029fba is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0)
);
end reg_entity_71dd029fba;
architecture structural of reg_entity_71dd029fba is
signal ce_1120_sg_x12: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x12: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x12 <= ce_1120;
clk_1120_sg_x12 <= clk_1120;
cic_fofb_q_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_q_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x3;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
d => convert_dout_net,
en(0) => cic_fofb_q_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x3
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_q_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg1"
entity reg1_entity_b079f30e3c is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end reg1_entity_b079f30e3c;
architecture structural of reg1_entity_b079f30e3c is
signal ce_1120_sg_x13: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x13: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register1_q_net_x2: std_logic;
signal register_q_net_x4: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x13 <= ce_1120;
clk_1120_sg_x13 <= clk_1120;
cic_fofb_i_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_i_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x4;
valid_out <= register1_q_net_x2;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x2
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d => convert_dout_net,
en(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x4
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_i_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb"
entity cic_fofb_entity_2ed6a6e00c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb_q_x0: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end cic_fofb_entity_2ed6a6e00c;
architecture structural of cic_fofb_entity_2ed6a6e00c is
signal ce_1120_sg_x14: std_logic;
signal ce_1_sg_x6: std_logic;
signal ce_logic_1_sg_x5: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tuser_chan_out_net: std_logic;
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x0: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x14: std_logic;
signal clk_1_sg_x6: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay_q_net_x4: std_logic;
signal register1_q_net_x3: std_logic;
signal register3_q_net_x0: std_logic;
signal register4_q_net_x0: std_logic_vector(23 downto 0);
signal register5_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(24 downto 0);
signal register_q_net_x6: std_logic_vector(24 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x6 <= ce_1;
ce_1120_sg_x14 <= ce_1120;
ce_logic_1_sg_x5 <= ce_logic_1;
register3_q_net_x0 <= ch_in;
clk_1_sg_x6 <= clk_1;
clk_1120_sg_x14 <= clk_1120;
register4_q_net_x0 <= i_in;
register5_q_net_x0 <= q_in;
ch_out <= delay_q_net_x4;
cic_fofb_q_x0 <= cic_fofb_q_event_tlast_missing_net_x0;
i_out <= register_q_net_x6;
q_out <= register_q_net_x5;
valid_out <= register1_q_net_x3;
cic_fofb_i: entity work.xlcic_compiler_2d3b496704eca3daaae85383d488a908
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register4_q_net_x0,
s_axis_data_tlast => relational2_op_net,
m_axis_data_tdata_data => cic_fofb_i_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => cic_fofb_i_m_axis_data_tvalid_net_x0
);
cic_fofb_q: entity work.xlcic_compiler_2d3b496704eca3daaae85383d488a908
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register5_q_net_x0,
s_axis_data_tlast => relational2_op_net,
event_tlast_missing => cic_fofb_q_event_tlast_missing_net_x0,
m_axis_data_tdata_data => cic_fofb_q_m_axis_data_tdata_data_net_x0,
m_axis_data_tvalid => cic_fofb_q_m_axis_data_tvalid_net_x0
);
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1120_sg_x14,
clk => clk_1120_sg_x14,
d(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q(0) => delay_q_net_x4
);
reg1_b079f30e3c: entity work.reg1_entity_b079f30e3c
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_i_m_axis_data_tdata_data_net_x0,
en => cic_fofb_i_m_axis_data_tvalid_net_x0,
dout => register_q_net_x6,
valid_out => register1_q_net_x3
);
reg_71dd029fba: entity work.reg_entity_71dd029fba
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_q_m_axis_data_tdata_data_net_x0,
en => cic_fofb_q_m_axis_data_tvalid_net_x0,
dout => register_q_net_x5
);
relational2: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x0,
b => constant1_op_net,
ce => ce_1_sg_x6,
clk => clk_1_sg_x6,
clr => '0',
op(0) => relational2_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp"
entity fofb_amp_entity_078cdb1842 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_078cdb1842;
architecture structural of fofb_amp_entity_078cdb1842 is
signal ce_1120_sg_x15: std_logic;
signal ce_1_sg_x7: std_logic;
signal ce_2240_sg_x10: std_logic;
signal ce_logic_1_sg_x6: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x15: std_logic;
signal clk_1_sg_x7: std_logic;
signal clk_2240_sg_x10: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x7 <= ce_1;
ce_1120_sg_x15 <= ce_1120;
ce_2240_sg_x10 <= ce_2240;
ce_logic_1_sg_x6 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x7 <= clk_1;
clk_1120_sg_x15 <= clk_1120;
clk_2240_sg_x10 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic0 <= down_sample1_q_net_x4;
tddm_fofb_cic0_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic0_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic0_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_2ed6a6e00c: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x7,
ce_1120 => ce_1120_sg_x15,
ce_logic_1 => ce_logic_1_sg_x6,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x7,
clk_1120 => clk_1120_sg_x15,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_6375e37e24: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_cf7aa296b2: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic0_6b909292ff: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x15,
ce_2240 => ce_2240_sg_x10,
clk_1120 => clk_1120_sg_x15,
clk_2240 => clk_2240_sg_x10,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0"
entity fofb_amp0_entity_95b23bfc2c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp0_entity_95b23bfc2c;
architecture structural of fofb_amp0_entity_95b23bfc2c is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x16: std_logic;
signal ce_1_sg_x8: std_logic;
signal ce_2240_sg_x11: std_logic;
signal ce_logic_1_sg_x7: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x16: std_logic;
signal clk_1_sg_x8: std_logic;
signal clk_2240_sg_x11: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x8 <= ce_1;
ce_1120_sg_x16 <= ce_1120;
ce_2240_sg_x11 <= ce_2240;
ce_logic_1_sg_x7 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x8 <= clk_1;
clk_1120_sg_x16 <= clk_1120;
clk_2240_sg_x11 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_078cdb1842: entity work.fofb_amp_entity_078cdb1842
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ce_logic_1 => ce_logic_1_sg_x7,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic0 => down_sample1_q_net_x10,
tddm_fofb_cic0_x0 => down_sample2_q_net_x10,
tddm_fofb_cic0_x1 => down_sample1_q_net_x11,
tddm_fofb_cic0_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_fad57e49ce: entity work.fofb_cordic_entity_fad57e49ce
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
tddm_tbt_cordic0 => down_sample1_q_net_x8,
tddm_tbt_cordic0_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic0_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic0_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_CORDIC"
entity fofb_cordic_entity_e4c0810ec7 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_fofb_cordic1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_e4c0810ec7;
architecture structural of fofb_cordic_entity_e4c0810ec7 is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x20: std_logic;
signal ce_1_sg_x9: std_logic;
signal ce_2240_sg_x15: std_logic;
signal clk_1120_sg_x20: std_logic;
signal clk_1_sg_x9: std_logic;
signal clk_2240_sg_x15: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x9 <= ce_1;
ce_1120_sg_x20 <= ce_1120;
ce_2240_sg_x15 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x9 <= clk_1;
clk_1120_sg_x20 <= clk_1120;
clk_2240_sg_x15 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
tddm_fofb_cordic1 <= down_sample1_q_net_x4;
tddm_fofb_cordic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cordic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cordic1_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x6
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x7
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_fofb_cordic1_77b64089dc: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x20,
ce_2240 => ce_2240_sg_x15,
clk_1120 => clk_1120_sg_x20,
clk_2240 => clk_2240_sg_x15,
fofb_cordic_ch_in => assert3_dout_net_x7,
fofb_cordic_din => assert2_dout_net_x6,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_amp"
entity fofb_amp_entity_f70fcc8ed9 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_f70fcc8ed9;
architecture structural of fofb_amp_entity_f70fcc8ed9 is
signal ce_1120_sg_x29: std_logic;
signal ce_1_sg_x11: std_logic;
signal ce_2240_sg_x19: std_logic;
signal ce_logic_1_sg_x9: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x29: std_logic;
signal clk_1_sg_x11: std_logic;
signal clk_2240_sg_x19: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x11 <= ce_1;
ce_1120_sg_x29 <= ce_1120;
ce_2240_sg_x19 <= ce_2240;
ce_logic_1_sg_x9 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x11 <= clk_1;
clk_1120_sg_x29 <= clk_1120;
clk_2240_sg_x19 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic1 <= down_sample1_q_net_x4;
tddm_fofb_cic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic1_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_579902476d: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x11,
ce_1120 => ce_1120_sg_x29,
ce_logic_1 => ce_logic_1_sg_x9,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x11,
clk_1120 => clk_1120_sg_x29,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_a06a1c33b5: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_b669a3b118: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic1_4a640315a5: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x29,
ce_2240 => ce_2240_sg_x19,
clk_1120 => clk_1120_sg_x29,
clk_2240 => clk_2240_sg_x19,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1"
entity fofb_amp1_entity_a049562dde is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp1_entity_a049562dde;
architecture structural of fofb_amp1_entity_a049562dde is
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x30: std_logic;
signal ce_1_sg_x12: std_logic;
signal ce_2240_sg_x20: std_logic;
signal ce_logic_1_sg_x10: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x30: std_logic;
signal clk_1_sg_x12: std_logic;
signal clk_2240_sg_x20: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x12 <= ce_1;
ce_1120_sg_x30 <= ce_1120;
ce_2240_sg_x20 <= ce_2240;
ce_logic_1_sg_x10 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x12 <= clk_1;
clk_1120_sg_x30 <= clk_1120;
clk_2240_sg_x20 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x7;
ch_out <= assert3_dout_net_x8;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_f70fcc8ed9: entity work.fofb_amp_entity_f70fcc8ed9
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ce_logic_1 => ce_logic_1_sg_x10,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic1 => down_sample1_q_net_x10,
tddm_fofb_cic1_x0 => down_sample2_q_net_x10,
tddm_fofb_cic1_x1 => down_sample1_q_net_x11,
tddm_fofb_cic1_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_e4c0810ec7: entity work.fofb_cordic_entity_e4c0810ec7
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
tddm_fofb_cordic1 => down_sample1_q_net_x8,
tddm_fofb_cordic1_x0 => down_sample2_q_net_x8,
tddm_fofb_cordic1_x1 => down_sample1_q_net_x9,
tddm_fofb_cordic1_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp"
entity fofb_amp_entity_8b25d4b0b6 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
fofb_amp0: out std_logic_vector(23 downto 0);
fofb_amp0_x0: out std_logic_vector(23 downto 0);
fofb_amp0_x1: out std_logic_vector(23 downto 0);
fofb_amp0_x2: out std_logic_vector(23 downto 0);
fofb_amp0_x3: out std_logic_vector(23 downto 0);
fofb_amp0_x4: out std_logic_vector(23 downto 0);
fofb_amp0_x5: out std_logic_vector(23 downto 0);
fofb_amp0_x6: out std_logic_vector(23 downto 0);
fofb_amp0_x7: out std_logic;
fofb_amp1: out std_logic_vector(23 downto 0);
fofb_amp1_x0: out std_logic_vector(23 downto 0);
fofb_amp1_x1: out std_logic_vector(23 downto 0);
fofb_amp1_x2: out std_logic_vector(23 downto 0);
fofb_amp1_x3: out std_logic_vector(23 downto 0);
fofb_amp1_x4: out std_logic_vector(23 downto 0);
fofb_amp1_x5: out std_logic_vector(23 downto 0);
fofb_amp1_x6: out std_logic_vector(23 downto 0);
fofb_amp1_x7: out std_logic
);
end fofb_amp_entity_8b25d4b0b6;
architecture structural of fofb_amp_entity_8b25d4b0b6 is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x31: std_logic;
signal ce_1_sg_x13: std_logic;
signal ce_2240_sg_x21: std_logic;
signal ce_logic_1_sg_x11: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x4: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x5: std_logic;
signal clk_1120_sg_x31: std_logic;
signal clk_1_sg_x13: std_logic;
signal clk_2240_sg_x21: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal register3_q_net_x4: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x4: std_logic_vector(23 downto 0);
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x4: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x13 <= ce_1;
ce_1120_sg_x31 <= ce_1120;
ce_2240_sg_x21 <= ce_2240;
ce_logic_1_sg_x11 <= ce_logic_1;
register3_q_net_x4 <= ch_in0;
register3_q_net_x5 <= ch_in1;
clk_1_sg_x13 <= clk_1;
clk_1120_sg_x31 <= clk_1120;
clk_2240_sg_x21 <= clk_2240;
register4_q_net_x4 <= i_in0;
register4_q_net_x5 <= i_in1;
register5_q_net_x4 <= q_in0;
register5_q_net_x5 <= q_in1;
amp_out0 <= down_sample2_q_net_x16;
amp_out1 <= down_sample1_q_net_x16;
amp_out2 <= down_sample2_q_net_x17;
amp_out3 <= down_sample1_q_net_x17;
fofb_amp0 <= down_sample1_q_net_x18;
fofb_amp0_x0 <= down_sample2_q_net_x18;
fofb_amp0_x1 <= down_sample1_q_net_x19;
fofb_amp0_x2 <= down_sample2_q_net_x19;
fofb_amp0_x3 <= down_sample1_q_net_x20;
fofb_amp0_x4 <= down_sample2_q_net_x20;
fofb_amp0_x5 <= down_sample1_q_net_x21;
fofb_amp0_x6 <= down_sample2_q_net_x21;
fofb_amp0_x7 <= cic_fofb_q_event_tlast_missing_net_x4;
fofb_amp1 <= down_sample1_q_net_x22;
fofb_amp1_x0 <= down_sample2_q_net_x22;
fofb_amp1_x1 <= down_sample1_q_net_x23;
fofb_amp1_x2 <= down_sample2_q_net_x23;
fofb_amp1_x3 <= down_sample1_q_net_x24;
fofb_amp1_x4 <= down_sample2_q_net_x24;
fofb_amp1_x5 <= down_sample1_q_net_x25;
fofb_amp1_x6 <= down_sample2_q_net_x25;
fofb_amp1_x7 <= cic_fofb_q_event_tlast_missing_net_x5;
fofb_amp0_95b23bfc2c: entity work.fofb_amp0_entity_95b23bfc2c
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x4,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x4,
q_in => register5_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
fofb_amp => down_sample1_q_net_x20,
fofb_amp_x0 => down_sample2_q_net_x20,
fofb_amp_x1 => down_sample1_q_net_x21,
fofb_amp_x2 => down_sample2_q_net_x21,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x4,
fofb_cordic => down_sample1_q_net_x18,
fofb_cordic_x0 => down_sample2_q_net_x18,
fofb_cordic_x1 => down_sample1_q_net_x19,
fofb_cordic_x2 => down_sample2_q_net_x19
);
fofb_amp1_a049562dde: entity work.fofb_amp1_entity_a049562dde
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x5,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x5,
q_in => register5_q_net_x5,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
fofb_amp => down_sample1_q_net_x24,
fofb_amp_x0 => down_sample2_q_net_x24,
fofb_amp_x1 => down_sample1_q_net_x25,
fofb_amp_x2 => down_sample2_q_net_x25,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x5,
fofb_cordic => down_sample1_q_net_x22,
fofb_cordic_x0 => down_sample2_q_net_x22,
fofb_cordic_x1 => down_sample1_q_net_x23,
fofb_cordic_x2 => down_sample2_q_net_x23
);
tddm_fofb_amp_4ch_2cc521a83f: entity work.tddm_fofb_amp_4ch_entity_2cc521a83f
port map (
amp_in0 => assert2_dout_net_x6,
amp_in1 => assert2_dout_net_x7,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ch_in0 => assert3_dout_net_x7,
ch_in1 => assert3_dout_net_x8,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
amp_out0 => down_sample2_q_net_x16,
amp_out1 => down_sample1_q_net_x16,
amp_out2 => down_sample2_q_net_x17,
amp_out3 => down_sample1_q_net_x17
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3/Cast_truncate1"
entity cast_truncate1_entity_56731b7870 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_56731b7870;
architecture structural of cast_truncate1_entity_56731b7870 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3"
entity k_fofb_mult3_entity_697accc8e2 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_fofb_mult3_entity_697accc8e2;
architecture structural of k_fofb_mult3_entity_697accc8e2 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2240_sg_x22: std_logic;
signal ce_2_sg_x5: std_logic;
signal clk_2240_sg_x22: std_logic;
signal clk_2_sg_x5: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x5 <= ce_2;
ce_2240_sg_x22 <= ce_2240;
clk_2_sg_x5 <= clk_2;
clk_2240_sg_x22 <= clk_2240;
assert5_dout_net_x0 <= in1;
kx_i_net_x0 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_56731b7870: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x22,
clk => clk_2240_sg_x22,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x0,
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
clr => '0',
core_ce => ce_2_sg_x5,
core_clk => clk_2_sg_x5,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_1_mult"
entity k_monit_1_mult_entity_016885a3ac is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_1_mult_entity_016885a3ac;
architecture structural of k_monit_1_mult_entity_016885a3ac is
signal ce_224000000_sg_x0: std_logic;
signal ce_2_sg_x8: std_logic;
signal clk_224000000_sg_x0: std_logic;
signal clk_2_sg_x8: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool_dout_net_x0: std_logic;
begin
ce_2_sg_x8 <= ce_2;
ce_224000000_sg_x0 <= ce_224000000;
clk_2_sg_x8 <= clk_2;
clk_224000000_sg_x0 <= clk_224000000;
reinterpret3_output_port_net_x0 <= in1;
kx_i_net_x2 <= in2;
ufix_to_bool_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_fe5c8d5ea5: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x0,
clk => clk_224000000_sg_x0,
d(0) => ufix_to_bool_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret3_output_port_net_x0,
b => kx_i_net_x2,
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
clr => '0',
core_ce => ce_2_sg_x8,
core_clk => clk_2_sg_x8,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_mult3"
entity k_monit_mult3_entity_8a778fb5f4 is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_mult3_entity_8a778fb5f4;
architecture structural of k_monit_mult3_entity_8a778fb5f4 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_22400000_sg_x0: std_logic;
signal ce_2_sg_x11: std_logic;
signal clk_22400000_sg_x0: std_logic;
signal clk_2_sg_x11: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x4: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x11 <= ce_2;
ce_22400000_sg_x0 <= ce_22400000;
clk_2_sg_x11 <= clk_2;
clk_22400000_sg_x0 <= clk_22400000;
assert11_dout_net_x0 <= in1;
kx_i_net_x4 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_47fd83104e: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x0,
clk => clk_22400000_sg_x0,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => kx_i_net_x4,
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
clr => '0',
core_ce => ce_2_sg_x11,
core_clk => clk_2_sg_x11,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_tbt_mult"
entity k_tbt_mult_entity_b8fafff255 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_tbt_mult_entity_b8fafff255;
architecture structural of k_tbt_mult_entity_b8fafff255 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2_sg_x14: std_logic;
signal ce_70_sg_x0: std_logic;
signal clk_2_sg_x14: std_logic;
signal clk_70_sg_x0: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x6: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x14 <= ce_2;
ce_70_sg_x0 <= ce_70;
clk_2_sg_x14 <= clk_2;
clk_70_sg_x0 <= clk_70;
assert5_dout_net_x0 <= in1;
kx_i_net_x6 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4592ea30ee: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x0,
clk => clk_70_sg_x0,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x6,
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
clr => '0',
core_ce => ce_2_sg_x14,
core_clk => clk_2_sg_x14,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4/Cast_truncate1"
entity cast_truncate1_entity_18a9b21a64 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_18a9b21a64;
architecture structural of cast_truncate1_entity_18a9b21a64 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4"
entity ksum_fofb_mult4_entity_ac3ed97096 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_fofb_mult4_entity_ac3ed97096;
architecture structural of ksum_fofb_mult4_entity_ac3ed97096 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2240_sg_x25: std_logic;
signal ce_2_sg_x17: std_logic;
signal clk_2240_sg_x25: std_logic;
signal clk_2_sg_x17: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x17 <= ce_2;
ce_2240_sg_x25 <= ce_2240;
clk_2_sg_x17 <= clk_2;
clk_2240_sg_x25 <= clk_2240;
assert11_dout_net_x0 <= in1;
ksum_i_net_x0 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_18a9b21a64: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x25,
clk => clk_2240_sg_x25,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x0,
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
clr => '0',
core_ce => ce_2_sg_x17,
core_clk => clk_2_sg_x17,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_1_mult1"
entity ksum_monit_1_mult1_entity_c66dc07078 is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_1_mult1_entity_c66dc07078;
architecture structural of ksum_monit_1_mult1_entity_c66dc07078 is
signal ce_224000000_sg_x3: std_logic;
signal ce_2_sg_x18: std_logic;
signal clk_224000000_sg_x3: std_logic;
signal clk_2_sg_x18: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x1: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret4_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool3_dout_net_x0: std_logic;
begin
ce_2_sg_x18 <= ce_2;
ce_224000000_sg_x3 <= ce_224000000;
clk_2_sg_x18 <= clk_2;
clk_224000000_sg_x3 <= clk_224000000;
reinterpret4_output_port_net_x0 <= in1;
ksum_i_net_x1 <= in2;
ufix_to_bool3_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_92cc22397d: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x3,
clk => clk_224000000_sg_x3,
d(0) => ufix_to_bool3_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret4_output_port_net_x0,
b => ksum_i_net_x1,
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
clr => '0',
core_ce => ce_2_sg_x18,
core_clk => clk_2_sg_x18,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_mult2"
entity ksum_monit_mult2_entity_31877b6d2b is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_mult2_entity_31877b6d2b;
architecture structural of ksum_monit_mult2_entity_31877b6d2b is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_22400000_sg_x3: std_logic;
signal ce_2_sg_x19: std_logic;
signal clk_22400000_sg_x3: std_logic;
signal clk_2_sg_x19: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x19 <= ce_2;
ce_22400000_sg_x3 <= ce_22400000;
clk_2_sg_x19 <= clk_2;
clk_22400000_sg_x3 <= clk_22400000;
assert5_dout_net_x0 <= in1;
ksum_i_net_x2 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4c5b033963: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x3,
clk => clk_22400000_sg_x3,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => ksum_i_net_x2,
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
clr => '0',
core_ce => ce_2_sg_x19,
core_clk => clk_2_sg_x19,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_tbt_mult3"
entity ksum_tbt_mult3_entity_e0be30d675 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_tbt_mult3_entity_e0be30d675;
architecture structural of ksum_tbt_mult3_entity_e0be30d675 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2_sg_x20: std_logic;
signal ce_70_sg_x3: std_logic;
signal clk_2_sg_x20: std_logic;
signal clk_70_sg_x3: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x3: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x20 <= ce_2;
ce_70_sg_x3 <= ce_70;
clk_2_sg_x20 <= clk_2;
clk_70_sg_x3 <= clk_70;
assert11_dout_net_x0 <= in1;
ksum_i_net_x3 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_91bc0d396f: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x3,
clk => clk_70_sg_x3,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x3,
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
clr => '0',
core_ce => ce_2_sg_x20,
core_clk => clk_2_sg_x20,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En"
entity datareg_en_entity_5c82ef2965 is
port (
ce_2: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0);
valid: out std_logic
);
end datareg_en_entity_5c82ef2965;
architecture structural of datareg_en_entity_5c82ef2965 is
signal ce_2_sg_x21: std_logic;
signal clk_2_sg_x21: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant12_op_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2_sg_x21 <= ce_2;
clk_2_sg_x21 <= clk_2;
constant12_op_net_x0 <= din;
constant11_op_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d(0) => constant11_op_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d => constant12_op_net_x0,
en(0) => constant11_op_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En1"
entity datareg_en1_entity_8d533fde9e is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end datareg_en1_entity_8d533fde9e;
architecture structural of datareg_en1_entity_8d533fde9e is
signal ce_1_sg_x14: std_logic;
signal clk_1_sg_x14: std_logic;
signal constant11_op_net_x1: std_logic;
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_1_sg_x14 <= ce_1;
clk_1_sg_x14 <= clk_1;
register_q_net_x1 <= din;
constant11_op_net_x1 <= en;
dout <= register_q_net_x2;
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d => register_q_net_x1,
en(0) => constant11_op_net_x1,
rst => "0",
q => register_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0"
entity cmixer_0_entity_f630e8d7ec is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine: in std_logic_vector(23 downto 0);
dds_msine: in std_logic_vector(23 downto 0);
dds_valid: in std_logic;
din_i: in std_logic_vector(23 downto 0);
din_q: in std_logic_vector(23 downto 0);
en: in std_logic;
ch_out: out std_logic;
i_out: out std_logic_vector(23 downto 0);
q_out: out std_logic_vector(23 downto 0)
);
end cmixer_0_entity_f630e8d7ec;
architecture structural of cmixer_0_entity_f630e8d7ec is
signal a_i: std_logic_vector(23 downto 0);
signal a_r: std_logic_vector(23 downto 0);
signal b_i: std_logic_vector(23 downto 0);
signal b_r: std_logic_vector(23 downto 0);
signal ce_1_sg_x15: std_logic;
signal ce_2_sg_x22: std_logic;
signal clk_1_sg_x15: std_logic;
signal clk_2_sg_x22: std_logic;
signal complexmult_m_axis_dout_tdata_imag_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tuser_net: std_logic;
signal complexmult_m_axis_dout_tvalid_net: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x0: std_logic;
signal convert1_dout_net: std_logic_vector(23 downto 0);
signal convert2_dout_net: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
signal register_q_net_x8: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x15 <= ce_1;
ce_2_sg_x22 <= ce_2;
register1_q_net_x1 <= ch_in;
clk_1_sg_x15 <= clk_1;
clk_2_sg_x22 <= clk_2;
register_q_net_x6 <= dds_cosine;
register_q_net_x7 <= dds_msine;
constant15_op_net_x0 <= dds_valid;
register_q_net_x8 <= din_i;
constant12_op_net_x1 <= din_q;
constant11_op_net_x2 <= en;
ch_out <= register3_q_net_x5;
i_out <= register4_q_net_x5;
q_out <= register5_q_net_x5;
complexmult: entity work.xlcomplex_multiplier_456da30af0f77a480cf80f52b29b4396
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
s_axis_a_tdata_imag => a_i,
s_axis_a_tdata_real => a_r,
s_axis_a_tvalid => constant15_op_net_x0,
s_axis_b_tdata_imag => b_i,
s_axis_b_tdata_real => b_r,
s_axis_b_tuser(0) => register_q_net,
s_axis_b_tvalid => register1_q_net_x0,
m_axis_dout_tdata_imag => complexmult_m_axis_dout_tdata_imag_net,
m_axis_dout_tdata_real => complexmult_m_axis_dout_tdata_real_net,
m_axis_dout_tuser(0) => complexmult_m_axis_dout_tuser_net,
m_axis_dout_tvalid => complexmult_m_axis_dout_tvalid_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret1_output_port_net,
en => "1",
dout => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert2_dout_net
);
datareg_en1_8d533fde9e: entity work.datareg_en1_entity_8d533fde9e
port map (
ce_1 => ce_1_sg_x15,
clk_1 => clk_1_sg_x15,
din => register_q_net_x8,
en => constant11_op_net_x2,
dout => register_q_net_x2
);
datareg_en_5c82ef2965: entity work.datareg_en_entity_5c82ef2965
port map (
ce_2 => ce_2_sg_x22,
clk_2 => clk_2_sg_x22,
din => constant12_op_net_x1,
en => constant11_op_net_x2,
dout => register_q_net_x0,
valid => register1_q_net_x0
);
delay: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x0,
q => b_i
);
delay1: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x2,
q => b_r
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x6,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_r
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x7,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_i
);
register3: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => complexmult_m_axis_dout_tuser_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register3_q_net_x5
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert1_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net_x5
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert2_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net_x5
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => register1_q_net_x1,
en(0) => constant11_op_net_x2,
rst => "0",
q(0) => register_q_net
);
reinterpret: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_imag_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_real_net,
output_port => reinterpret1_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer/TDDM_Mixer0_i"
entity tddm_mixer0_i_entity_f95b8f24ad is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_mixer0_i_entity_f95b8f24ad;
architecture structural of tddm_mixer0_i_entity_f95b8f24ad is
signal ce_1_sg_x18: std_logic;
signal ce_2_sg_x25: std_logic;
signal clk_1_sg_x18: std_logic;
signal clk_2_sg_x25: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register3_q_net_x6: std_logic;
signal register4_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x18 <= ce_1;
ce_2_sg_x25 <= ce_2;
register3_q_net_x6 <= ch_in;
clk_1_sg_x18 <= clk_1;
clk_2_sg_x25 <= clk_2;
register4_q_net_x6 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register3_q_net_x6,
b(0) => constant_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x6,
b => constant1_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer"
entity tddm_mixer_entity_8537ade7b6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
mix0_ch_in: in std_logic;
mix0_i_in: in std_logic_vector(23 downto 0);
mix0_q_in: in std_logic_vector(23 downto 0);
mix1_ch_in: in std_logic;
mix1_i_in: in std_logic_vector(23 downto 0);
mix1_q_in: in std_logic_vector(23 downto 0);
mix_ch0_i_out: out std_logic_vector(23 downto 0);
mix_ch0_q_out: out std_logic_vector(23 downto 0);
mix_ch1_i_out: out std_logic_vector(23 downto 0);
mix_ch1_q_out: out std_logic_vector(23 downto 0);
mix_ch2_i_out: out std_logic_vector(23 downto 0);
mix_ch2_q_out: out std_logic_vector(23 downto 0);
mix_ch3_i_out: out std_logic_vector(23 downto 0);
mix_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_mixer_entity_8537ade7b6;
architecture structural of tddm_mixer_entity_8537ade7b6 is
signal ce_1_sg_x22: std_logic;
signal ce_2_sg_x29: std_logic;
signal clk_1_sg_x22: std_logic;
signal clk_2_sg_x29: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x7: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x7: std_logic_vector(23 downto 0);
signal register3_q_net_x10: std_logic;
signal register3_q_net_x9: std_logic;
signal register4_q_net_x8: std_logic_vector(23 downto 0);
signal register4_q_net_x9: std_logic_vector(23 downto 0);
signal register5_q_net_x8: std_logic_vector(23 downto 0);
signal register5_q_net_x9: std_logic_vector(23 downto 0);
begin
ce_1_sg_x22 <= ce_1;
ce_2_sg_x29 <= ce_2;
clk_1_sg_x22 <= clk_1;
clk_2_sg_x29 <= clk_2;
register3_q_net_x9 <= mix0_ch_in;
register4_q_net_x8 <= mix0_i_in;
register5_q_net_x8 <= mix0_q_in;
register3_q_net_x10 <= mix1_ch_in;
register4_q_net_x9 <= mix1_i_in;
register5_q_net_x9 <= mix1_q_in;
mix_ch0_i_out <= down_sample2_q_net_x4;
mix_ch0_q_out <= down_sample2_q_net_x5;
mix_ch1_i_out <= down_sample1_q_net_x4;
mix_ch1_q_out <= down_sample1_q_net_x5;
mix_ch2_i_out <= down_sample2_q_net_x6;
mix_ch2_q_out <= down_sample2_q_net_x7;
mix_ch3_i_out <= down_sample1_q_net_x6;
mix_ch3_q_out <= down_sample1_q_net_x7;
tddm_mixer0_i_f95b8f24ad: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x8,
dout_ch0 => down_sample2_q_net_x4,
dout_ch1 => down_sample1_q_net_x4
);
tddm_mixer0_q_2c5e18f496: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x8,
dout_ch0 => down_sample2_q_net_x5,
dout_ch1 => down_sample1_q_net_x5
);
tddm_mixer1_i_1afc4ccdba: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x9,
dout_ch0 => down_sample2_q_net_x6,
dout_ch1 => down_sample1_q_net_x6
);
tddm_mixer1_q_ee4acbed30: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x9,
dout_ch0 => down_sample2_q_net_x7,
dout_ch1 => down_sample1_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer"
entity mixer_entity_a1cd828545 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine_0: in std_logic_vector(23 downto 0);
dds_cosine_1: in std_logic_vector(23 downto 0);
dds_msine_0: in std_logic_vector(23 downto 0);
dds_msine_1: in std_logic_vector(23 downto 0);
dds_valid_0: in std_logic;
dds_valid_1: in std_logic;
din0: in std_logic_vector(23 downto 0);
din1: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
i_out0: out std_logic_vector(23 downto 0);
i_out1: out std_logic_vector(23 downto 0);
q_out0: out std_logic_vector(23 downto 0);
q_out1: out std_logic_vector(23 downto 0);
tddm_mixer: out std_logic_vector(23 downto 0);
tddm_mixer_x0: out std_logic_vector(23 downto 0);
tddm_mixer_x1: out std_logic_vector(23 downto 0);
tddm_mixer_x2: out std_logic_vector(23 downto 0);
tddm_mixer_x3: out std_logic_vector(23 downto 0);
tddm_mixer_x4: out std_logic_vector(23 downto 0);
tddm_mixer_x5: out std_logic_vector(23 downto 0);
tddm_mixer_x6: out std_logic_vector(23 downto 0)
);
end mixer_entity_a1cd828545;
architecture structural of mixer_entity_a1cd828545 is
signal ce_1_sg_x23: std_logic;
signal ce_2_sg_x30: std_logic;
signal clk_1_sg_x23: std_logic;
signal clk_2_sg_x30: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x1: std_logic;
signal constant1_op_net_x2: std_logic;
signal constant2_op_net_x1: std_logic_vector(23 downto 0);
signal constant3_op_net_x1: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register3_q_net_x11: std_logic;
signal register3_q_net_x12: std_logic;
signal register4_q_net_x10: std_logic_vector(23 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x10: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x16: std_logic_vector(23 downto 0);
signal register_q_net_x17: std_logic_vector(23 downto 0);
begin
ce_1_sg_x23 <= ce_1;
ce_2_sg_x30 <= ce_2;
register1_q_net_x3 <= ch_in0;
register1_q_net_x4 <= ch_in1;
clk_1_sg_x23 <= clk_1;
clk_2_sg_x30 <= clk_2;
register_q_net_x12 <= dds_cosine_0;
register_q_net_x14 <= dds_cosine_1;
register_q_net_x13 <= dds_msine_0;
register_q_net_x15 <= dds_msine_1;
constant15_op_net_x1 <= dds_valid_0;
constant3_op_net_x1 <= dds_valid_1;
register_q_net_x16 <= din0;
register_q_net_x17 <= din1;
ch_out0 <= register3_q_net_x11;
ch_out1 <= register3_q_net_x12;
i_out0 <= register4_q_net_x10;
i_out1 <= register4_q_net_x11;
q_out0 <= register5_q_net_x10;
q_out1 <= register5_q_net_x11;
tddm_mixer <= down_sample1_q_net_x8;
tddm_mixer_x0 <= down_sample2_q_net_x8;
tddm_mixer_x1 <= down_sample1_q_net_x9;
tddm_mixer_x2 <= down_sample2_q_net_x9;
tddm_mixer_x3 <= down_sample1_q_net_x10;
tddm_mixer_x4 <= down_sample2_q_net_x10;
tddm_mixer_x5 <= down_sample1_q_net_x11;
tddm_mixer_x6 <= down_sample2_q_net_x11;
cmixer_0_f630e8d7ec: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x3,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x12,
dds_msine => register_q_net_x13,
dds_valid => constant15_op_net_x1,
din_i => register_q_net_x16,
din_q => constant12_op_net_x1,
en => constant11_op_net_x2,
ch_out => register3_q_net_x11,
i_out => register4_q_net_x10,
q_out => register5_q_net_x10
);
cmixer_1_61bfc18f90: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x4,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x14,
dds_msine => register_q_net_x15,
dds_valid => constant3_op_net_x1,
din_i => register_q_net_x17,
din_q => constant2_op_net_x1,
en => constant1_op_net_x2,
ch_out => register3_q_net_x12,
i_out => register4_q_net_x11,
q_out => register5_q_net_x11
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x2
);
constant11: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x2
);
constant12: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant12_op_net_x1
);
constant2: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net_x1
);
tddm_mixer_8537ade7b6: entity work.tddm_mixer_entity_8537ade7b6
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
mix0_ch_in => register3_q_net_x11,
mix0_i_in => register4_q_net_x10,
mix0_q_in => register5_q_net_x10,
mix1_ch_in => register3_q_net_x12,
mix1_i_in => register4_q_net_x11,
mix1_q_in => register5_q_net_x11,
mix_ch0_i_out => down_sample2_q_net_x8,
mix_ch0_q_out => down_sample2_q_net_x9,
mix_ch1_i_out => down_sample1_q_net_x8,
mix_ch1_q_out => down_sample1_q_net_x9,
mix_ch2_i_out => down_sample2_q_net_x10,
mix_ch2_q_out => down_sample2_q_net_x11,
mix_ch3_i_out => down_sample1_q_net_x10,
mix_ch3_q_out => down_sample1_q_net_x11
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2/format1"
entity format1_entity_4e0a69646b is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_4e0a69646b;
architecture structural of format1_entity_4e0a69646b is
signal ce_5600000_sg_x0: std_logic;
signal clk_5600000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_5600000_sg_x0 <= ce_5600000;
clk_5600000_sg_x0 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_5600000_sg_x0,
clk => clk_5600000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2"
entity cast2_entity_4b7421c7c9 is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast2_entity_4b7421c7c9;
architecture structural of cast2_entity_4b7421c7c9 is
signal ce_5600000_sg_x1: std_logic;
signal clk_5600000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_5600000_sg_x1 <= ce_5600000;
clk_5600000_sg_x1 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x1 <= data_in;
monit_pfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_4e0a69646b: entity work.format1_entity_4e0a69646b
port map (
ce_5600000 => ce_5600000_sg_x1,
clk_5600000 => clk_5600000_sg_x1,
din => monit_pfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x1,
clk => clk_5600000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4/format1"
entity format1_entity_3cf61b0d44 is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_3cf61b0d44;
architecture structural of format1_entity_3cf61b0d44 is
signal ce_2800000_sg_x0: std_logic;
signal clk_2800000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_2800000_sg_x0 <= ce_2800000;
clk_2800000_sg_x0 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_2800000_sg_x0,
clk => clk_2800000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4"
entity cast4_entity_4ed908d7fc is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast4_entity_4ed908d7fc;
architecture structural of cast4_entity_4ed908d7fc is
signal ce_2800000_sg_x1: std_logic;
signal clk_2800000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2800000_sg_x1 <= ce_2800000;
clk_2800000_sg_x1 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x1 <= data_in;
monit_cfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_3cf61b0d44: entity work.format1_entity_3cf61b0d44
port map (
ce_2800000 => ce_2800000_sg_x1,
clk_2800000 => clk_2800000_sg_x1,
din => monit_cfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2800000_sg_x1,
clk => clk_2800000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_cfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Reg1"
entity reg1_entity_8661a44192 is
port (
ce_1400000: in std_logic;
clk_1400000: in std_logic;
din: in std_logic_vector(60 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end reg1_entity_8661a44192;
architecture structural of reg1_entity_8661a44192 is
signal ce_1400000_sg_x0: std_logic;
signal clk_1400000_sg_x0: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(60 downto 0);
begin
ce_1400000_sg_x0 <= ce_1400000;
clk_1400000_sg_x0 <= clk_1400000;
monit_cic_m_axis_data_tdata_data_net_x0 <= din;
monit_cic_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 59,
din_width => 61,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
d => convert_dout_net,
en(0) => monit_cic_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_c88e29aa6b
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cic_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c/TDDM_monit_amp_c_int"
entity tddm_monit_amp_c_int_entity_554a834349 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_22400000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_int_entity_554a834349;
architecture structural of tddm_monit_amp_c_int_entity_554a834349 is
signal ce_22400000_sg_x4: std_logic;
signal ce_5600000_sg_x2: std_logic;
signal clk_22400000_sg_x4: std_logic;
signal clk_5600000_sg_x2: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal delay2_q_net_x0: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_22400000_sg_x4 <= ce_22400000;
ce_5600000_sg_x2 <= ce_5600000;
delay2_q_net_x0 <= ch_in;
clk_22400000_sg_x4 <= clk_22400000;
clk_5600000_sg_x2 <= clk_5600000;
register_q_net_x1 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register2_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register3_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant1_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant3_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant4_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c"
entity tddm_monit_amp_c_entity_5b2613eff7 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_ch_in: in std_logic_vector(1 downto 0);
monit_din: in std_logic_vector(23 downto 0);
monit_ch0_out: out std_logic_vector(23 downto 0);
monit_ch1_out: out std_logic_vector(23 downto 0);
monit_ch2_out: out std_logic_vector(23 downto 0);
monit_ch3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_entity_5b2613eff7;
architecture structural of tddm_monit_amp_c_entity_5b2613eff7 is
signal ce_22400000_sg_x5: std_logic;
signal ce_5600000_sg_x3: std_logic;
signal clk_22400000_sg_x5: std_logic;
signal clk_5600000_sg_x3: std_logic;
signal delay2_q_net_x1: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x5 <= ce_22400000;
ce_5600000_sg_x3 <= ce_5600000;
clk_22400000_sg_x5 <= clk_22400000;
clk_5600000_sg_x3 <= clk_5600000;
delay2_q_net_x1 <= monit_ch_in;
register_q_net_x2 <= monit_din;
monit_ch0_out <= down_sample2_q_net_x1;
monit_ch1_out <= down_sample1_q_net_x1;
monit_ch2_out <= down_sample3_q_net_x1;
monit_ch3_out <= down_sample4_q_net_x1;
tddm_monit_amp_c_int_554a834349: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x5,
ce_5600000 => ce_5600000_sg_x3,
ch_in => delay2_q_net_x1,
clk_22400000 => clk_22400000_sg_x5,
clk_5600000 => clk_5600000_sg_x3,
din => register_q_net_x2,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c"
entity monit_amp_c_entity_c83793ea71 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out_x1: out std_logic_vector(1 downto 0);
monit_cfir_x0: out std_logic;
monit_cic_x0: out std_logic;
monit_pfir_x0: out std_logic;
tddm_monit_amp_c: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x0: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x1: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x2: out std_logic_vector(23 downto 0)
);
end monit_amp_c_entity_c83793ea71;
architecture structural of monit_amp_c_entity_c83793ea71 is
signal ce_1400000_sg_x1: std_logic;
signal ce_1_sg_x24: std_logic;
signal ce_22400000_sg_x6: std_logic;
signal ce_2800000_sg_x2: std_logic;
signal ce_5600000_sg_x4: std_logic;
signal ce_560_sg_x0: std_logic;
signal ce_logic_1400000_sg_x0: std_logic;
signal ce_logic_2800000_sg_x0: std_logic;
signal ce_logic_560_sg_x0: std_logic;
signal ch_out_x0: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x1: std_logic;
signal clk_1_sg_x24: std_logic;
signal clk_22400000_sg_x6: std_logic;
signal clk_2800000_sg_x2: std_logic;
signal clk_5600000_sg_x4: std_logic;
signal clk_560_sg_x0: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay1_q_net: std_logic_vector(23 downto 0);
signal delay2_q_net_x2: std_logic_vector(1 downto 0);
signal delay3_q_net: std_logic_vector(23 downto 0);
signal delay_q_net: std_logic_vector(1 downto 0);
signal dout_x0: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x2: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal monit_cic_event_tlast_unexpected_net_x0: std_logic;
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tuser_chan_out_net: std_logic_vector(1 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register3_q_net: std_logic_vector(1 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x24 <= ce_1;
ce_1400000_sg_x1 <= ce_1400000;
ce_22400000_sg_x6 <= ce_22400000;
ce_2800000_sg_x2 <= ce_2800000;
ce_560_sg_x0 <= ce_560;
ce_5600000_sg_x4 <= ce_5600000;
ce_logic_1400000_sg_x0 <= ce_logic_1400000;
ce_logic_2800000_sg_x0 <= ce_logic_2800000;
ce_logic_560_sg_x0 <= ce_logic_560;
ch_out_x0 <= ch_in;
clk_1_sg_x24 <= clk_1;
clk_1400000_sg_x1 <= clk_1400000;
clk_22400000_sg_x6 <= clk_22400000;
clk_2800000_sg_x2 <= clk_2800000;
clk_560_sg_x0 <= clk_560;
clk_5600000_sg_x4 <= clk_5600000;
dout_x0 <= din;
amp_out <= register_q_net_x3;
ch_out_x1 <= delay2_q_net_x2;
monit_cfir_x0 <= monit_cfir_event_s_data_chanid_incorrect_net_x0;
monit_cic_x0 <= monit_cic_event_tlast_unexpected_net_x0;
monit_pfir_x0 <= monit_pfir_event_s_data_chanid_incorrect_net_x0;
tddm_monit_amp_c <= down_sample1_q_net_x2;
tddm_monit_amp_c_x0 <= down_sample2_q_net_x2;
tddm_monit_amp_c_x1 <= down_sample3_q_net_x2;
tddm_monit_amp_c_x2 <= down_sample4_q_net_x2;
cast2_4b7421c7c9: entity work.cast2_entity_4b7421c7c9
port map (
ce_5600000 => ce_5600000_sg_x4,
clk_5600000 => clk_5600000_sg_x4,
data_in => monit_pfir_m_axis_data_tdata_net_x1,
en => monit_pfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x3
);
cast4_4ed908d7fc: entity work.cast4_entity_4ed908d7fc
port map (
ce_2800000 => ce_2800000_sg_x2,
clk_2800000 => clk_2800000_sg_x2,
data_in => monit_cfir_m_axis_data_tdata_net_x1,
en => monit_cfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0
);
constant1: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => monit_cic_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
d => dout_x0,
en => '1',
rst => '1',
q => delay1_q_net
);
delay2: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_5600000_sg_x4,
clk => clk_5600000_sg_x4,
d => monit_pfir_m_axis_data_tuser_chanid_net,
en => '1',
rst => '1',
q => delay2_q_net_x2
);
delay3: entity work.xldelay
generic map (
latency => 2,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => register_q_net_x1,
en => '1',
rst => '1',
q => delay3_q_net
);
monit_cfir: entity work.xlfir_compiler_2acadf5a08d72e0ee15ce4e1ac741dc6
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_2800000 => ce_2800000_sg_x2,
ce_logic_1400000 => ce_logic_1400000_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_2800000 => clk_2800000_sg_x2,
clk_logic_1400000 => clk_1400000_sg_x1,
s_axis_data_tdata => delay3_q_net,
s_axis_data_tuser_chanid => delay_q_net,
src_ce => ce_1400000_sg_x1,
src_clk => clk_1400000_sg_x1,
event_s_data_chanid_incorrect => monit_cfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_cfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_cfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_cfir_m_axis_data_tvalid_net_x0
);
monit_cic: entity work.xlcic_compiler_6efc67831a277bdb0701519c5a976f20
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_560 => ce_560_sg_x0,
ce_logic_560 => ce_logic_560_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_560 => clk_560_sg_x0,
clk_logic_560 => clk_560_sg_x0,
s_axis_data_tdata_data => delay1_q_net,
s_axis_data_tlast => relational2_op_net,
event_tlast_unexpected => monit_cic_event_tlast_unexpected_net_x0,
m_axis_data_tdata_data => monit_cic_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out => monit_cic_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => monit_cic_m_axis_data_tvalid_net_x0
);
monit_pfir: entity work.xlfir_compiler_1da691037bdf8c1b85b3b4502d6e9610
port map (
ce => ce_1_sg_x24,
ce_2800000 => ce_2800000_sg_x2,
ce_5600000 => ce_5600000_sg_x4,
ce_logic_2800000 => ce_logic_2800000_sg_x0,
clk => clk_1_sg_x24,
clk_2800000 => clk_2800000_sg_x2,
clk_5600000 => clk_5600000_sg_x4,
clk_logic_2800000 => clk_2800000_sg_x2,
s_axis_data_tdata => register_q_net_x0,
s_axis_data_tuser_chanid => register3_q_net,
src_ce => ce_2800000_sg_x2,
src_clk => clk_2800000_sg_x2,
event_s_data_chanid_incorrect => monit_pfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pfir_m_axis_data_tvalid_net_x0
);
reg1_8661a44192: entity work.reg1_entity_8661a44192
port map (
ce_1400000 => ce_1400000_sg_x1,
clk_1400000 => clk_1400000_sg_x1,
din => monit_cic_m_axis_data_tdata_data_net_x0,
en => monit_cic_m_axis_data_tvalid_net_x0,
dout => register_q_net_x1
);
register3: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_2800000_sg_x2,
clk => clk_2800000_sg_x2,
d => monit_cfir_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register3_q_net
);
relational2: entity work.relational_83ca2c6a3c
port map (
a => ch_out_x0,
b => constant1_op_net,
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
clr => '0',
op(0) => relational2_op_net
);
tddm_monit_amp_c_5b2613eff7: entity work.tddm_monit_amp_c_entity_5b2613eff7
port map (
ce_22400000 => ce_22400000_sg_x6,
ce_5600000 => ce_5600000_sg_x4,
clk_22400000 => clk_22400000_sg_x6,
clk_5600000 => clk_5600000_sg_x4,
monit_ch_in => delay2_q_net_x2,
monit_din => register_q_net_x3,
monit_ch0_out => down_sample2_q_net_x2,
monit_ch1_out => down_sample1_q_net_x2,
monit_ch2_out => down_sample3_q_net_x2,
monit_ch3_out => down_sample4_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/TDDM_monit_amp_out"
entity tddm_monit_amp_out_entity_521eb373cc is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_amp_ch_in: in std_logic_vector(1 downto 0);
monit_amp_din: in std_logic_vector(23 downto 0);
monit_amp_data0_out: out std_logic_vector(23 downto 0);
monit_amp_data1_out: out std_logic_vector(23 downto 0);
monit_amp_data2_out: out std_logic_vector(23 downto 0);
monit_amp_data3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_out_entity_521eb373cc;
architecture structural of tddm_monit_amp_out_entity_521eb373cc is
signal ce_22400000_sg_x8: std_logic;
signal ce_5600000_sg_x6: std_logic;
signal clk_22400000_sg_x8: std_logic;
signal clk_5600000_sg_x6: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x8 <= ce_22400000;
ce_5600000_sg_x6 <= ce_5600000;
clk_22400000_sg_x8 <= clk_22400000;
clk_5600000_sg_x6 <= clk_5600000;
delay2_q_net_x4 <= monit_amp_ch_in;
register_q_net_x5 <= monit_amp_din;
monit_amp_data0_out <= down_sample2_q_net_x1;
monit_amp_data1_out <= down_sample1_q_net_x1;
monit_amp_data2_out <= down_sample3_q_net_x1;
monit_amp_data3_out <= down_sample4_q_net_x1;
tddm_monit_amp_out_int_b60196c7a6: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x8,
ce_5600000 => ce_5600000_sg_x6,
ch_in => delay2_q_net_x4,
clk_22400000 => clk_22400000_sg_x8,
clk_5600000 => clk_5600000_sg_x6,
din => register_q_net_x5,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp"
entity monit_amp_entity_44da74e268 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
monit_amp_c: out std_logic_vector(23 downto 0);
monit_amp_c_x0: out std_logic_vector(23 downto 0);
monit_amp_c_x1: out std_logic_vector(23 downto 0);
monit_amp_c_x2: out std_logic_vector(23 downto 0);
monit_amp_c_x3: out std_logic;
monit_amp_c_x4: out std_logic;
monit_amp_c_x5: out std_logic
);
end monit_amp_entity_44da74e268;
architecture structural of monit_amp_entity_44da74e268 is
signal ce_1400000_sg_x2: std_logic;
signal ce_1_sg_x25: std_logic;
signal ce_22400000_sg_x9: std_logic;
signal ce_2800000_sg_x3: std_logic;
signal ce_5600000_sg_x7: std_logic;
signal ce_560_sg_x1: std_logic;
signal ce_logic_1400000_sg_x1: std_logic;
signal ce_logic_2800000_sg_x1: std_logic;
signal ce_logic_560_sg_x1: std_logic;
signal ch_out_x1: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x2: std_logic;
signal clk_1_sg_x25: std_logic;
signal clk_22400000_sg_x9: std_logic;
signal clk_2800000_sg_x3: std_logic;
signal clk_5600000_sg_x7: std_logic;
signal clk_560_sg_x1: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal dout_x1: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x4: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal monit_cic_event_tlast_unexpected_net_x1: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x25 <= ce_1;
ce_1400000_sg_x2 <= ce_1400000;
ce_22400000_sg_x9 <= ce_22400000;
ce_2800000_sg_x3 <= ce_2800000;
ce_560_sg_x1 <= ce_560;
ce_5600000_sg_x7 <= ce_5600000;
ce_logic_1400000_sg_x1 <= ce_logic_1400000;
ce_logic_2800000_sg_x1 <= ce_logic_2800000;
ce_logic_560_sg_x1 <= ce_logic_560;
ch_out_x1 <= ch_in;
clk_1_sg_x25 <= clk_1;
clk_1400000_sg_x2 <= clk_1400000;
clk_22400000_sg_x9 <= clk_22400000;
clk_2800000_sg_x3 <= clk_2800000;
clk_560_sg_x1 <= clk_560;
clk_5600000_sg_x7 <= clk_5600000;
dout_x1 <= din;
amp_out0 <= down_sample2_q_net_x4;
amp_out1 <= down_sample1_q_net_x4;
amp_out2 <= down_sample3_q_net_x4;
amp_out3 <= down_sample4_q_net_x4;
monit_amp_c <= down_sample1_q_net_x3;
monit_amp_c_x0 <= down_sample2_q_net_x3;
monit_amp_c_x1 <= down_sample3_q_net_x3;
monit_amp_c_x2 <= down_sample4_q_net_x3;
monit_amp_c_x3 <= monit_cfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_x4 <= monit_cic_event_tlast_unexpected_net_x1;
monit_amp_c_x5 <= monit_pfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_c83793ea71: entity work.monit_amp_c_entity_c83793ea71
port map (
ce_1 => ce_1_sg_x25,
ce_1400000 => ce_1400000_sg_x2,
ce_22400000 => ce_22400000_sg_x9,
ce_2800000 => ce_2800000_sg_x3,
ce_560 => ce_560_sg_x1,
ce_5600000 => ce_5600000_sg_x7,
ce_logic_1400000 => ce_logic_1400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x1,
ce_logic_560 => ce_logic_560_sg_x1,
ch_in => ch_out_x1,
clk_1 => clk_1_sg_x25,
clk_1400000 => clk_1400000_sg_x2,
clk_22400000 => clk_22400000_sg_x9,
clk_2800000 => clk_2800000_sg_x3,
clk_560 => clk_560_sg_x1,
clk_5600000 => clk_5600000_sg_x7,
din => dout_x1,
amp_out => register_q_net_x5,
ch_out_x1 => delay2_q_net_x4,
monit_cfir_x0 => monit_cfir_event_s_data_chanid_incorrect_net_x1,
monit_cic_x0 => monit_cic_event_tlast_unexpected_net_x1,
monit_pfir_x0 => monit_pfir_event_s_data_chanid_incorrect_net_x1,
tddm_monit_amp_c => down_sample1_q_net_x3,
tddm_monit_amp_c_x0 => down_sample2_q_net_x3,
tddm_monit_amp_c_x1 => down_sample3_q_net_x3,
tddm_monit_amp_c_x2 => down_sample4_q_net_x3
);
tddm_monit_amp_out_521eb373cc: entity work.tddm_monit_amp_out_entity_521eb373cc
port map (
ce_22400000 => ce_22400000_sg_x9,
ce_5600000 => ce_5600000_sg_x7,
clk_22400000 => clk_22400000_sg_x9,
clk_5600000 => clk_5600000_sg_x7,
monit_amp_ch_in => delay2_q_net_x4,
monit_amp_din => register_q_net_x5,
monit_amp_data0_out => down_sample2_q_net_x4,
monit_amp_data1_out => down_sample1_q_net_x4,
monit_amp_data2_out => down_sample3_q_net_x4,
monit_amp_data3_out => down_sample4_q_net_x4
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_5b94be40c5 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_5b94be40c5;
architecture structural of tddm_tbt_cordic_entity_5b94be40c5 is
signal ce_35_sg_x0: std_logic;
signal ce_70_sg_x4: std_logic;
signal clk_35_sg_x0: std_logic;
signal clk_70_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_amp_out_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x0: std_logic;
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x0 <= ce_35;
ce_70_sg_x4 <= ce_70;
p_ch_out_x0 <= ch_in;
clk_35_sg_x0 <= clk_35;
clk_70_sg_x4 <= clk_70;
p_amp_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant1_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_d3f44a687c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_d3f44a687c;
architecture structural of tddm_tbt_cordic1_entity_d3f44a687c is
signal ce_35_sg_x1: std_logic;
signal ce_70_sg_x5: std_logic;
signal clk_35_sg_x1: std_logic;
signal clk_70_sg_x5: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x1: std_logic;
signal p_phase_out_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x1 <= ce_35;
ce_70_sg_x5 <= ce_70;
p_ch_out_x1 <= ch_in;
clk_35_sg_x1 <= clk_35;
clk_70_sg_x5 <= clk_70;
p_phase_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant1_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_18d3979a26 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_data0_out: out std_logic_vector(23 downto 0);
tbt_cordic_data1_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_18d3979a26;
architecture structural of tddm_tbt_cordic_entity_18d3979a26 is
signal ce_35_sg_x2: std_logic;
signal ce_70_sg_x6: std_logic;
signal clk_35_sg_x2: std_logic;
signal clk_70_sg_x6: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x2 <= ce_35;
ce_70_sg_x6 <= ce_70;
clk_35_sg_x2 <= clk_35;
clk_70_sg_x6 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_data0_out <= down_sample2_q_net_x2;
tbt_cordic_data1_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d3f44a687c: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_5b94be40c5: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC"
entity tbt_cordic_entity_232cb2e43e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_232cb2e43e;
architecture structural of tbt_cordic_entity_232cb2e43e is
signal ce_1_sg_x26: std_logic;
signal ce_35_sg_x3: std_logic;
signal ce_70_sg_x7: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x26: std_logic;
signal clk_35_sg_x3: std_logic;
signal clk_70_sg_x7: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x26 <= ce_1;
ce_35_sg_x3 <= ce_35;
ce_70_sg_x7 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x26 <= clk_1;
clk_35_sg_x3 <= clk_35;
clk_70_sg_x7 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_18d3979a26: entity work.tddm_tbt_cordic_entity_18d3979a26
port map (
ce_35 => ce_35_sg_x3,
ce_70 => ce_70_sg_x7,
clk_35 => clk_35_sg_x3,
clk_70 => clk_70_sg_x7,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_data0_out => down_sample2_q_net_x4,
tbt_cordic_data1_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT/TDDM_tbt_poly_i"
entity tddm_tbt_poly_i_entity_469601736c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_poly_i_entity_469601736c;
architecture structural of tddm_tbt_poly_i_entity_469601736c is
signal ce_35_sg_x4: std_logic;
signal ce_70_sg_x8: std_logic;
signal clk_35_sg_x4: std_logic;
signal clk_70_sg_x8: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net_x1: std_logic;
signal register_q_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x4 <= ce_35;
ce_70_sg_x8 <= ce_70;
register2_q_net_x1 <= ch_in;
clk_35_sg_x4 <= clk_35;
clk_70_sg_x8 <= clk_70;
reinterpret_output_port_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register2_q_net_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register2_q_net_x1,
b => constant1_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_9ac9f65b0b is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch0_i_out: out std_logic_vector(23 downto 0);
poly35_ch0_q_out: out std_logic_vector(23 downto 0);
poly35_ch1_i_out: out std_logic_vector(23 downto 0);
poly35_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_9ac9f65b0b;
architecture structural of tddm_tbt_entity_9ac9f65b0b is
signal ce_35_sg_x6: std_logic;
signal ce_70_sg_x10: std_logic;
signal clk_35_sg_x6: std_logic;
signal clk_70_sg_x10: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x6 <= ce_35;
ce_70_sg_x10 <= ce_70;
clk_35_sg_x6 <= clk_35;
clk_70_sg_x10 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch0_i_out <= down_sample2_q_net_x2;
poly35_ch0_q_out <= down_sample2_q_net_x3;
poly35_ch1_i_out <= down_sample1_q_net_x2;
poly35_ch1_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_469601736c: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_8011b4e29e: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/Trunc"
entity trunc_entity_e5eda8a5ac is
port (
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end trunc_entity_e5eda8a5ac;
architecture structural of trunc_entity_e5eda8a5ac is
signal register1_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal slice_y_net: std_logic_vector(23 downto 0);
begin
register1_q_net_x2 <= din;
dout <= reinterpret_output_port_net_x3;
reinterpret: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x3
);
slice: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 24,
x_width => 25,
y_width => 24
)
port map (
x => register1_q_net_x2,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim"
entity tbt_poly_decim_entity_4477ec06c2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_4477ec06c2;
architecture structural of tbt_poly_decim_entity_4477ec06c2 is
signal ce_1_sg_x27: std_logic;
signal ce_35_sg_x7: std_logic;
signal ce_70_sg_x11: std_logic;
signal ce_logic_1_sg_x12: std_logic;
signal clk_1_sg_x27: std_logic;
signal clk_35_sg_x7: std_logic;
signal clk_70_sg_x11: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x12: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x27 <= ce_1;
ce_35_sg_x7 <= ce_35;
ce_70_sg_x11 <= ce_70;
ce_logic_1_sg_x12 <= ce_logic_1;
register3_q_net_x12 <= ch_in;
clk_1_sg_x27 <= clk_1;
clk_35_sg_x7 <= clk_35;
clk_70_sg_x11 <= clk_70;
register4_q_net_x11 <= i_in;
register5_q_net_x11 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_6508759a07908936c4d12ef4ec464ceb
port map (
ce => ce_1_sg_x27,
ce_35 => ce_35_sg_x7,
ce_logic_1 => ce_logic_1_sg_x12,
clk => clk_1_sg_x27,
clk_35 => clk_35_sg_x7,
clk_logic_1 => clk_1_sg_x27,
s_axis_data_tdata_path0 => register4_q_net_x11,
s_axis_data_tdata_path1 => register5_q_net_x11,
s_axis_data_tuser_chanid(0) => register3_q_net_x12,
src_ce => ce_1_sg_x27,
src_clk => clk_1_sg_x27,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_9ac9f65b0b: entity work.tddm_tbt_entity_9ac9f65b0b
port map (
ce_35 => ce_35_sg_x7,
ce_70 => ce_70_sg_x11,
clk_35 => clk_35_sg_x7,
clk_70 => clk_70_sg_x11,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch0_i_out => down_sample2_q_net_x4,
poly35_ch0_q_out => down_sample2_q_net_x5,
poly35_ch1_i_out => down_sample1_q_net_x4,
poly35_ch1_q_out => down_sample1_q_net_x5
);
trunc1_841a61ebcc: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_e5eda8a5ac: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0"
entity tbt_amp0_entity_88b1c45f0e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp0_entity_88b1c45f0e;
architecture structural of tbt_amp0_entity_88b1c45f0e is
signal ce_1_sg_x28: std_logic;
signal ce_35_sg_x8: std_logic;
signal ce_70_sg_x12: std_logic;
signal ce_logic_1_sg_x13: std_logic;
signal clk_1_sg_x28: std_logic;
signal clk_35_sg_x8: std_logic;
signal clk_70_sg_x12: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x28 <= ce_1;
ce_35_sg_x8 <= ce_35;
ce_70_sg_x12 <= ce_70;
ce_logic_1_sg_x13 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x28 <= clk_1;
clk_35_sg_x8 <= clk_35;
clk_70_sg_x12 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_232cb2e43e: entity work.tbt_cordic_entity_232cb2e43e
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_4477ec06c2: entity work.tbt_poly_decim_entity_4477ec06c2
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ce_logic_1 => ce_logic_1_sg_x13,
ch_in => register3_q_net_x13,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register4_q_net_x12,
q_in => register5_q_net_x12,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_9e99bd206d is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_ch2_out: out std_logic_vector(23 downto 0);
tbt_cordic_ch3_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_9e99bd206d;
architecture structural of tddm_tbt_cordic_entity_9e99bd206d is
signal ce_35_sg_x11: std_logic;
signal ce_70_sg_x15: std_logic;
signal clk_35_sg_x11: std_logic;
signal clk_70_sg_x15: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x11 <= ce_35;
ce_70_sg_x15 <= ce_70;
clk_35_sg_x11 <= clk_35;
clk_70_sg_x15 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_ch2_out <= down_sample2_q_net_x2;
tbt_cordic_ch3_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d22fbdac88: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_f04a48283a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC"
entity tbt_cordic_entity_9dc3371de2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_9dc3371de2;
architecture structural of tbt_cordic_entity_9dc3371de2 is
signal ce_1_sg_x29: std_logic;
signal ce_35_sg_x12: std_logic;
signal ce_70_sg_x16: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x29: std_logic;
signal clk_35_sg_x12: std_logic;
signal clk_70_sg_x16: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x29 <= ce_1;
ce_35_sg_x12 <= ce_35;
ce_70_sg_x16 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x29 <= clk_1;
clk_35_sg_x12 <= clk_35;
clk_70_sg_x16 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_9e99bd206d: entity work.tddm_tbt_cordic_entity_9e99bd206d
port map (
ce_35 => ce_35_sg_x12,
ce_70 => ce_70_sg_x16,
clk_35 => clk_35_sg_x12,
clk_70 => clk_70_sg_x16,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_ch2_out => down_sample2_q_net_x4,
tbt_cordic_ch3_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_1f4b61e651 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch2_i_out: out std_logic_vector(23 downto 0);
poly35_ch2_q_out: out std_logic_vector(23 downto 0);
poly35_ch3_i_out: out std_logic_vector(23 downto 0);
poly35_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_1f4b61e651;
architecture structural of tddm_tbt_entity_1f4b61e651 is
signal ce_35_sg_x15: std_logic;
signal ce_70_sg_x19: std_logic;
signal clk_35_sg_x15: std_logic;
signal clk_70_sg_x19: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x15 <= ce_35;
ce_70_sg_x19 <= ce_70;
clk_35_sg_x15 <= clk_35;
clk_70_sg_x19 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch2_i_out <= down_sample2_q_net_x2;
poly35_ch2_q_out <= down_sample2_q_net_x3;
poly35_ch3_i_out <= down_sample1_q_net_x2;
poly35_ch3_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_b74b709553: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_4f85d7362a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim"
entity tbt_poly_decim_entity_bb6f6b5b6a is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_bb6f6b5b6a;
architecture structural of tbt_poly_decim_entity_bb6f6b5b6a is
signal ce_1_sg_x30: std_logic;
signal ce_35_sg_x16: std_logic;
signal ce_70_sg_x20: std_logic;
signal ce_logic_1_sg_x14: std_logic;
signal clk_1_sg_x30: std_logic;
signal clk_35_sg_x16: std_logic;
signal clk_70_sg_x20: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x30 <= ce_1;
ce_35_sg_x16 <= ce_35;
ce_70_sg_x20 <= ce_70;
ce_logic_1_sg_x14 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x30 <= clk_1;
clk_35_sg_x16 <= clk_35;
clk_70_sg_x20 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_6508759a07908936c4d12ef4ec464ceb
port map (
ce => ce_1_sg_x30,
ce_35 => ce_35_sg_x16,
ce_logic_1 => ce_logic_1_sg_x14,
clk => clk_1_sg_x30,
clk_35 => clk_35_sg_x16,
clk_logic_1 => clk_1_sg_x30,
s_axis_data_tdata_path0 => register4_q_net_x12,
s_axis_data_tdata_path1 => register5_q_net_x12,
s_axis_data_tuser_chanid(0) => register3_q_net_x13,
src_ce => ce_1_sg_x30,
src_clk => clk_1_sg_x30,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_1f4b61e651: entity work.tddm_tbt_entity_1f4b61e651
port map (
ce_35 => ce_35_sg_x16,
ce_70 => ce_70_sg_x20,
clk_35 => clk_35_sg_x16,
clk_70 => clk_70_sg_x20,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch2_i_out => down_sample2_q_net_x4,
poly35_ch2_q_out => down_sample2_q_net_x5,
poly35_ch3_i_out => down_sample1_q_net_x4,
poly35_ch3_q_out => down_sample1_q_net_x5
);
trunc1_c3e3bdeec5: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_6a2a4db298: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1"
entity tbt_amp1_entity_6e98f85f9f is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp1_entity_6e98f85f9f;
architecture structural of tbt_amp1_entity_6e98f85f9f is
signal ce_1_sg_x31: std_logic;
signal ce_35_sg_x17: std_logic;
signal ce_70_sg_x21: std_logic;
signal ce_logic_1_sg_x15: std_logic;
signal clk_1_sg_x31: std_logic;
signal clk_35_sg_x17: std_logic;
signal clk_70_sg_x21: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x14: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x13: std_logic_vector(23 downto 0);
signal register5_q_net_x13: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x31 <= ce_1;
ce_35_sg_x17 <= ce_35;
ce_70_sg_x21 <= ce_70;
ce_logic_1_sg_x15 <= ce_logic_1;
register3_q_net_x14 <= ch_in;
clk_1_sg_x31 <= clk_1;
clk_35_sg_x17 <= clk_35;
clk_70_sg_x21 <= clk_70;
register4_q_net_x13 <= i_in;
register5_q_net_x13 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_9dc3371de2: entity work.tbt_cordic_entity_9dc3371de2
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_bb6f6b5b6a: entity work.tbt_poly_decim_entity_bb6f6b5b6a
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ce_logic_1 => ce_logic_1_sg_x15,
ch_in => register3_q_net_x14,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register4_q_net_x13,
q_in => register5_q_net_x13,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TDDM_tbt_amp_4ch"
entity tddm_tbt_amp_4ch_entity_9f3ac0073e is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_35: in std_logic;
ce_70: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_tbt_amp_4ch_entity_9f3ac0073e;
architecture structural of tddm_tbt_amp_4ch_entity_9f3ac0073e is
signal ce_35_sg_x20: std_logic;
signal ce_70_sg_x24: std_logic;
signal clk_35_sg_x20: std_logic;
signal clk_70_sg_x24: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
begin
p_amp_out_x6 <= amp_in0;
p_amp_out_x7 <= amp_in1;
ce_35_sg_x20 <= ce_35;
ce_70_sg_x24 <= ce_70;
p_ch_out_x7 <= ch_in0;
p_ch_out_x8 <= ch_in1;
clk_35_sg_x20 <= clk_35;
clk_70_sg_x24 <= clk_70;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_tbt_amp0_8f2b25894a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x7,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x6,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_amp1_0c4a2e4770: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x8,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x7,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp"
entity tbt_amp_entity_cbd277bb0c is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
tbt_amp0: out std_logic_vector(23 downto 0);
tbt_amp0_x0: out std_logic_vector(23 downto 0);
tbt_amp0_x1: out std_logic_vector(23 downto 0);
tbt_amp0_x2: out std_logic_vector(23 downto 0);
tbt_amp0_x3: out std_logic;
tbt_amp0_x4: out std_logic_vector(23 downto 0);
tbt_amp0_x5: out std_logic_vector(23 downto 0);
tbt_amp0_x6: out std_logic_vector(23 downto 0);
tbt_amp0_x7: out std_logic_vector(23 downto 0);
tbt_amp1: out std_logic_vector(23 downto 0);
tbt_amp1_x0: out std_logic_vector(23 downto 0);
tbt_amp1_x1: out std_logic_vector(23 downto 0);
tbt_amp1_x2: out std_logic_vector(23 downto 0);
tbt_amp1_x3: out std_logic;
tbt_amp1_x4: out std_logic_vector(23 downto 0);
tbt_amp1_x5: out std_logic_vector(23 downto 0);
tbt_amp1_x6: out std_logic_vector(23 downto 0);
tbt_amp1_x7: out std_logic_vector(23 downto 0)
);
end tbt_amp_entity_cbd277bb0c;
architecture structural of tbt_amp_entity_cbd277bb0c is
signal ce_1_sg_x32: std_logic;
signal ce_35_sg_x21: std_logic;
signal ce_70_sg_x25: std_logic;
signal ce_logic_1_sg_x16: std_logic;
signal clk_1_sg_x32: std_logic;
signal clk_35_sg_x21: std_logic;
signal clk_70_sg_x25: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x3: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x4: std_logic;
begin
ce_1_sg_x32 <= ce_1;
ce_35_sg_x21 <= ce_35;
ce_70_sg_x25 <= ce_70;
ce_logic_1_sg_x16 <= ce_logic_1;
register3_q_net_x15 <= ch_in0;
register3_q_net_x16 <= ch_in1;
clk_1_sg_x32 <= clk_1;
clk_35_sg_x21 <= clk_35;
clk_70_sg_x25 <= clk_70;
register4_q_net_x14 <= i_in0;
register4_q_net_x15 <= i_in1;
register5_q_net_x14 <= q_in0;
register5_q_net_x15 <= q_in1;
amp_out0 <= down_sample2_q_net_x24;
amp_out1 <= down_sample1_q_net_x24;
amp_out2 <= down_sample2_q_net_x25;
amp_out3 <= down_sample1_q_net_x25;
tbt_amp0 <= down_sample1_q_net_x16;
tbt_amp0_x0 <= down_sample2_q_net_x16;
tbt_amp0_x1 <= down_sample1_q_net_x17;
tbt_amp0_x2 <= down_sample2_q_net_x17;
tbt_amp0_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x3;
tbt_amp0_x4 <= down_sample1_q_net_x18;
tbt_amp0_x5 <= down_sample2_q_net_x18;
tbt_amp0_x6 <= down_sample1_q_net_x19;
tbt_amp0_x7 <= down_sample2_q_net_x19;
tbt_amp1 <= down_sample1_q_net_x20;
tbt_amp1_x0 <= down_sample2_q_net_x20;
tbt_amp1_x1 <= down_sample1_q_net_x21;
tbt_amp1_x2 <= down_sample2_q_net_x21;
tbt_amp1_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x4;
tbt_amp1_x4 <= down_sample1_q_net_x22;
tbt_amp1_x5 <= down_sample2_q_net_x22;
tbt_amp1_x6 <= down_sample1_q_net_x23;
tbt_amp1_x7 <= down_sample2_q_net_x23;
tbt_amp0_88b1c45f0e: entity work.tbt_amp0_entity_88b1c45f0e
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x15,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x14,
q_in => register5_q_net_x14,
amp_out => p_amp_out_x6,
ch_out => p_ch_out_x7,
tbt_cordic => down_sample1_q_net_x16,
tbt_cordic_x0 => down_sample2_q_net_x16,
tbt_cordic_x1 => down_sample1_q_net_x17,
tbt_cordic_x2 => down_sample2_q_net_x17,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x3,
tbt_poly_decim_x0 => down_sample1_q_net_x18,
tbt_poly_decim_x1 => down_sample2_q_net_x18,
tbt_poly_decim_x2 => down_sample1_q_net_x19,
tbt_poly_decim_x3 => down_sample2_q_net_x19
);
tbt_amp1_6e98f85f9f: entity work.tbt_amp1_entity_6e98f85f9f
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x16,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x15,
q_in => register5_q_net_x15,
amp_out => p_amp_out_x7,
ch_out => p_ch_out_x8,
tbt_cordic => down_sample1_q_net_x20,
tbt_cordic_x0 => down_sample2_q_net_x20,
tbt_cordic_x1 => down_sample1_q_net_x21,
tbt_cordic_x2 => down_sample2_q_net_x21,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x4,
tbt_poly_decim_x0 => down_sample1_q_net_x22,
tbt_poly_decim_x1 => down_sample2_q_net_x22,
tbt_poly_decim_x2 => down_sample1_q_net_x23,
tbt_poly_decim_x3 => down_sample2_q_net_x23
);
tddm_tbt_amp_4ch_9f3ac0073e: entity work.tddm_tbt_amp_4ch_entity_9f3ac0073e
port map (
amp_in0 => p_amp_out_x6,
amp_in1 => p_amp_out_x7,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ch_in0 => p_ch_out_x7,
ch_in1 => p_ch_out_x8,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
amp_out0 => down_sample2_q_net_x24,
amp_out1 => down_sample1_q_net_x24,
amp_out2 => down_sample2_q_net_x25,
amp_out3 => down_sample1_q_net_x25
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix/TDM_mix_ch0_1"
entity tdm_mix_ch0_1_entity_b9bb73dd5f is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_mix_ch0_1_entity_b9bb73dd5f;
architecture structural of tdm_mix_ch0_1_entity_b9bb73dd5f is
signal ce_1_sg_x33: std_logic;
signal ce_2_sg_x31: std_logic;
signal ce_logic_1_sg_x17: std_logic;
signal clk_1_sg_x33: std_logic;
signal clk_2_sg_x31: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register_q_net_x17: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x8: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x9: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x33 <= ce_1;
ce_2_sg_x31 <= ce_2;
ce_logic_1_sg_x17 <= ce_logic_1;
clk_1_sg_x33 <= clk_1;
clk_2_sg_x31 <= clk_2;
reinterpret2_output_port_net_x9 <= din_ch0;
reinterpret2_output_port_net_x8 <= din_ch1;
constant10_op_net_x0 <= rst;
ch_out <= register1_q_net_x4;
dout <= register_q_net_x17;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x17,
clk => clk_1_sg_x33,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
sel(0) => mux_sel1_op_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op(0) => mux_sel1_op_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register1_q_net_x4
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x17
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x9,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x8,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix"
entity tdm_mix_entity_54ce67e6e8 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
dout0: out std_logic_vector(23 downto 0);
dout1: out std_logic_vector(23 downto 0)
);
end tdm_mix_entity_54ce67e6e8;
architecture structural of tdm_mix_entity_54ce67e6e8 is
signal ce_1_sg_x35: std_logic;
signal ce_2_sg_x33: std_logic;
signal ce_logic_1_sg_x19: std_logic;
signal clk_1_sg_x35: std_logic;
signal clk_2_sg_x33: std_logic;
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register_q_net_x19: std_logic_vector(23 downto 0);
signal register_q_net_x20: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x11: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x12: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x13: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x14: std_logic_vector(23 downto 0);
begin
ce_1_sg_x35 <= ce_1;
ce_2_sg_x33 <= ce_2;
ce_logic_1_sg_x19 <= ce_logic_1;
clk_1_sg_x35 <= clk_1;
clk_2_sg_x33 <= clk_2;
reinterpret2_output_port_net_x14 <= din_ch0;
reinterpret2_output_port_net_x11 <= din_ch1;
reinterpret2_output_port_net_x12 <= din_ch2;
reinterpret2_output_port_net_x13 <= din_ch3;
ch_out0 <= register1_q_net_x6;
ch_out1 <= register1_q_net_x7;
dout0 <= register_q_net_x19;
dout1 <= register_q_net_x20;
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
tdm_mix_ch0_1_b9bb73dd5f: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x14,
din_ch1 => reinterpret2_output_port_net_x11,
rst => constant10_op_net_x0,
ch_out => register1_q_net_x6,
dout => register_q_net_x19
);
tdm_mix_ch0_2_e9327141fc: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x12,
din_ch1 => reinterpret2_output_port_net_x13,
rst => constant11_op_net_x0,
ch_out => register1_q_net_x7,
dout => register_q_net_x20
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit"
entity tdm_monit_entity_6e38292ecb is
port (
ce_1: in std_logic;
ce_2240: in std_logic;
ce_560: in std_logic;
ce_logic_560: in std_logic;
clk_1: in std_logic;
clk_2240: in std_logic;
clk_560: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end tdm_monit_entity_6e38292ecb;
architecture structural of tdm_monit_entity_6e38292ecb is
signal ce_1_sg_x36: std_logic;
signal ce_2240_sg_x26: std_logic;
signal ce_560_sg_x2: std_logic;
signal ce_logic_560_sg_x2: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal clk_1_sg_x36: std_logic;
signal clk_2240_sg_x26: std_logic;
signal clk_560_sg_x2: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal mux_sel_op_net: std_logic_vector(1 downto 0);
signal mux_y_net: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x36 <= ce_1;
ce_2240_sg_x26 <= ce_2240;
ce_560_sg_x2 <= ce_560;
ce_logic_560_sg_x2 <= ce_logic_560;
clk_1_sg_x36 <= clk_1;
clk_2240_sg_x26 <= clk_2240;
clk_560_sg_x2 <= clk_560;
down_sample2_q_net_x18 <= din_ch0;
down_sample1_q_net_x18 <= din_ch1;
down_sample2_q_net_x19 <= din_ch2;
down_sample1_q_net_x19 <= din_ch3;
constant10_op_net_x0 <= rst;
ch_out <= ch_out_x2;
dout <= dout_x2;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_560_sg_x2,
clk => clk_560_sg_x2,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => ch_out_x2
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => mux_y_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => dout_x2
);
mux: entity work.mux_f062741975
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net,
y => mux_y_net
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_eb46eda57512a5a4",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x36,
clk => clk_1_sg_x36,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op => mux_sel_op_net
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample"
entity downsample_entity_f33f90217c is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(1 downto 0);
dout: out std_logic_vector(1 downto 0)
);
end downsample_entity_f33f90217c;
architecture structural of downsample_entity_f33f90217c is
signal ce_1_sg_x37: std_logic;
signal ce_2500_sg_x0: std_logic;
signal ce_5600000_sg_x8: std_logic;
signal clk_1_sg_x37: std_logic;
signal clk_2500_sg_x0: std_logic;
signal clk_5600000_sg_x8: std_logic;
signal down_sample5_q_net: std_logic_vector(1 downto 0);
signal down_sample_q_net_x0: std_logic_vector(1 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
begin
ce_1_sg_x37 <= ce_1;
ce_2500_sg_x0 <= ce_2500;
ce_5600000_sg_x8 <= ce_5600000;
clk_1_sg_x37 <= clk_1;
clk_2500_sg_x0 <= clk_2500;
clk_5600000_sg_x8 <= clk_5600000;
mux_sel_op_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x8,
dest_clk => clk_5600000_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x0,
src_clk => clk_2500_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net_x0,
dest_ce => ce_2500_sg_x0,
dest_clk => clk_2500_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x37,
src_clk => clk_1_sg_x37,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample1"
entity downsample1_entity_312d531c6b is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample1_entity_312d531c6b;
architecture structural of downsample1_entity_312d531c6b is
signal ce_1_sg_x38: std_logic;
signal ce_2500_sg_x1: std_logic;
signal ce_5600000_sg_x9: std_logic;
signal clk_1_sg_x38: std_logic;
signal clk_2500_sg_x1: std_logic;
signal clk_5600000_sg_x9: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
begin
ce_1_sg_x38 <= ce_1;
ce_2500_sg_x1 <= ce_2500;
ce_5600000_sg_x9 <= ce_5600000;
clk_1_sg_x38 <= clk_1;
clk_2500_sg_x1 <= clk_2500;
clk_5600000_sg_x9 <= clk_5600000;
mux_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x9,
dest_clk => clk_5600000_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x1,
src_clk => clk_2500_sg_x1,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => mux_y_net_x0,
dest_ce => ce_2500_sg_x1,
dest_clk => clk_2500_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x38,
src_clk => clk_1_sg_x38,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1"
entity tdm_monit_1_entity_746ecf54b0 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
ce_logic_5600000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din_ch0: in std_logic_vector(25 downto 0);
din_ch1: in std_logic_vector(25 downto 0);
din_ch2: in std_logic_vector(25 downto 0);
din_ch3: in std_logic_vector(25 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end tdm_monit_1_entity_746ecf54b0;
architecture structural of tdm_monit_1_entity_746ecf54b0 is
signal ce_1_sg_x39: std_logic;
signal ce_22400000_sg_x10: std_logic;
signal ce_2500_sg_x2: std_logic;
signal ce_5600000_sg_x10: std_logic;
signal ce_logic_5600000_sg_x0: std_logic;
signal clk_1_sg_x39: std_logic;
signal clk_22400000_sg_x10: std_logic;
signal clk_2500_sg_x2: std_logic;
signal clk_5600000_sg_x10: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant11_op_net_x0: std_logic;
signal down_sample_q_net_x2: std_logic_vector(1 downto 0);
signal down_sample_q_net_x3: std_logic_vector(25 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x39 <= ce_1;
ce_22400000_sg_x10 <= ce_22400000;
ce_2500_sg_x2 <= ce_2500;
ce_5600000_sg_x10 <= ce_5600000;
ce_logic_5600000_sg_x0 <= ce_logic_5600000;
clk_1_sg_x39 <= clk_1;
clk_22400000_sg_x10 <= clk_22400000;
clk_2500_sg_x2 <= clk_2500;
clk_5600000_sg_x10 <= clk_5600000;
concat_y_net_x0 <= din_ch0;
concat1_y_net_x0 <= din_ch1;
concat2_y_net_x0 <= din_ch2;
concat3_y_net_x0 <= din_ch3;
constant11_op_net_x0 <= rst;
ch_out <= down_sample_q_net_x2;
dout <= down_sample_q_net_x3;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 26,
q_width => 1
)
port map (
ce => ce_logic_5600000_sg_x0,
clk => clk_5600000_sg_x10,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
downsample1_312d531c6b: entity work.downsample1_entity_312d531c6b
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_y_net_x0,
dout => down_sample_q_net_x3
);
downsample_f33f90217c: entity work.downsample_entity_f33f90217c
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_sel_op_net_x0,
dout => down_sample_q_net_x2
);
mux: entity work.mux_187c900130
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net_x0,
y => mux_y_net_x0
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_eb46eda57512a5a4",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x39,
clk => clk_1_sg_x39,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op => mux_sel_op_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat1_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat2_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat3_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/convert_filt"
entity convert_filt_entity_fda412c1bf is
port (
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end convert_filt_entity_fda412c1bf;
architecture structural of convert_filt_entity_fda412c1bf is
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x0: std_logic_vector(24 downto 0);
begin
down_sample_q_net_x4 <= din;
dout <= reinterpret5_output_port_net_x0;
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample_q_net_x4,
dout => extractor1_dout_net
);
reinterpret5: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret5_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En"
entity datareg_en_entity_79473f9ed1 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en_entity_79473f9ed1;
architecture structural of datareg_en_entity_79473f9ed1 is
signal ce_1_sg_x40: std_logic;
signal clk_1_sg_x40: std_logic;
signal divider_dout_valid_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x40 <= ce_1;
clk_1_sg_x40 <= clk_1;
reinterpret1_output_port_net_x0 <= din;
divider_dout_valid_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d(0) => divider_dout_valid_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d => reinterpret1_output_port_net_x0,
en(0) => divider_dout_valid_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En3"
entity datareg_en3_entity_6643090018 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en3_entity_6643090018;
architecture structural of datareg_en3_entity_6643090018 is
signal ce_1_sg_x43: std_logic;
signal clk_1_sg_x43: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal delay1_q_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x43 <= ce_1;
clk_1_sg_x43 <= clk_1;
convert_dout_net_x0 <= din;
delay1_q_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d(0) => delay1_q_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d => convert_dout_net_x0,
en(0) => delay1_q_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/pulse_stretcher"
entity pulse_stretcher_entity_9893378b63 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
clr: in std_logic;
pulse_in: in std_logic;
extd_out: out std_logic
);
end pulse_stretcher_entity_9893378b63;
architecture structural of pulse_stretcher_entity_9893378b63 is
signal ce_1_sg_x44: std_logic;
signal ce_70_x0: std_logic;
signal clk_1_sg_x44: std_logic;
signal inverter_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register_q_net: std_logic;
begin
ce_1_sg_x44 <= ce_1;
clk_1_sg_x44 <= clk_1;
ce_70_x0 <= clr;
register1_q_net_x1 <= pulse_in;
extd_out <= logical3_y_net_x0;
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
clr => '0',
ip(0) => ce_70_x0,
op(0) => inverter_op_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register_q_net,
d1(0) => inverter_op_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => logical1_y_net,
y(0) => logical2_y_net
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => register_q_net,
y(0) => logical3_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
d(0) => logical2_y_net,
en => "1",
rst => "0",
q(0) => register_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb"
entity delta_sigma_fofb_entity_ee61e649ea is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_logic_2240: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_fofb_entity_ee61e649ea;
architecture structural of delta_sigma_fofb_entity_ee61e649ea is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x52: std_logic;
signal ce_2240_sg_x27: std_logic;
signal ce_2_sg_x34: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_2240_sg_x0: std_logic;
signal clk_1_sg_x52: std_logic;
signal clk_2240_sg_x27: std_logic;
signal clk_2_sg_x34: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_fofb_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x20 <= a;
down_sample1_q_net_x20 <= b;
down_sample2_q_net_x21 <= c;
ce_1_sg_x52 <= ce_1;
ce_2_sg_x34 <= ce_2;
ce_2240_sg_x27 <= ce_2240;
ce_logic_2240_sg_x0 <= ce_logic_2240;
clk_1_sg_x52 <= clk_1;
clk_2_sg_x34 <= clk_2;
clk_2240_sg_x27 <= clk_2240;
down_sample1_q_net_x21 <= d;
del_sig_div_fofb_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x21,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_2240_sg_x0,
clk => clk_2240_sg_x27,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_3225c09afc: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_5b5f4b61b7: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_6643090018: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_79473f9ed1: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x34,
src_clk => clk_2_sg_x34,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_f6401a1a3d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_38948aaba0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_816d954034: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_5d505b900f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_bee4540339: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_f82d879b1c: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_2406c4a105: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_9893378b63: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x34,
clk => clk_2_sg_x34,
d => del_sig_div_fofb_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample1"
entity downsample1_entity_4c88924603 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample1_entity_4c88924603;
architecture structural of downsample1_entity_4c88924603 is
signal ce_1_sg_x57: std_logic;
signal ce_22400000_sg_x11: std_logic;
signal ce_5000_sg_x0: std_logic;
signal clk_1_sg_x57: std_logic;
signal clk_22400000_sg_x11: std_logic;
signal clk_5000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x57 <= ce_1;
ce_22400000_sg_x11 <= ce_22400000;
ce_5000_sg_x0 <= ce_5000;
clk_1_sg_x57 <= clk_1;
clk_22400000_sg_x11 <= clk_22400000;
clk_5000_sg_x0 <= clk_5000;
register13_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x11,
dest_clk => clk_22400000_sg_x11,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x0,
src_clk => clk_5000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net_x0,
dest_ce => ce_5000_sg_x0,
dest_clk => clk_5000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x57,
src_clk => clk_1_sg_x57,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample2"
entity downsample2_entity_891f07b1a7 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic;
dout: out std_logic
);
end downsample2_entity_891f07b1a7;
architecture structural of downsample2_entity_891f07b1a7 is
signal ce_1_sg_x58: std_logic;
signal ce_22400000_sg_x12: std_logic;
signal ce_5000_sg_x1: std_logic;
signal clk_1_sg_x58: std_logic;
signal clk_22400000_sg_x12: std_logic;
signal clk_5000_sg_x1: std_logic;
signal down_sample5_q_net: std_logic;
signal down_sample_q_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
begin
ce_1_sg_x58 <= ce_1;
ce_22400000_sg_x12 <= ce_22400000;
ce_5000_sg_x1 <= ce_5000;
clk_1_sg_x58 <= clk_1;
clk_22400000_sg_x12 <= clk_22400000;
clk_5000_sg_x1 <= clk_5000;
logical3_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => down_sample5_q_net,
dest_ce => ce_22400000_sg_x12,
dest_clk => clk_22400000_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x1,
src_clk => clk_5000_sg_x1,
src_clr => '0',
q(0) => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_5000_sg_x1,
dest_clk => clk_5000_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x58,
src_clk => clk_1_sg_x58,
src_clr => '0',
q(0) => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample3"
entity downsample3_entity_dba589aaee is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample3_entity_dba589aaee;
architecture structural of downsample3_entity_dba589aaee is
signal ce_1_sg_x59: std_logic;
signal ce_22400000_sg_x13: std_logic;
signal ce_5000_sg_x2: std_logic;
signal clk_1_sg_x59: std_logic;
signal clk_22400000_sg_x13: std_logic;
signal clk_5000_sg_x2: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x59 <= ce_1;
ce_22400000_sg_x13 <= ce_22400000;
ce_5000_sg_x2 <= ce_5000;
clk_1_sg_x59 <= clk_1;
clk_22400000_sg_x13 <= clk_22400000;
clk_5000_sg_x2 <= clk_5000;
register12_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x13,
dest_clk => clk_22400000_sg_x13,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x2,
src_clk => clk_5000_sg_x2,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net_x0,
dest_ce => ce_5000_sg_x2,
dest_clk => clk_5000_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x59,
src_clk => clk_1_sg_x59,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample7"
entity downsample7_entity_b85055cb62 is
port (
ce_10000: in std_logic;
ce_2: in std_logic;
ce_44800000: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_44800000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample7_entity_b85055cb62;
architecture structural of downsample7_entity_b85055cb62 is
signal ce_10000_sg_x0: std_logic;
signal ce_2_sg_x35: std_logic;
signal ce_44800000_sg_x0: std_logic;
signal clk_10000_sg_x0: std_logic;
signal clk_2_sg_x35: std_logic;
signal clk_44800000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
begin
ce_10000_sg_x0 <= ce_10000;
ce_2_sg_x35 <= ce_2;
ce_44800000_sg_x0 <= ce_44800000;
clk_10000_sg_x0 <= clk_10000;
clk_2_sg_x35 <= clk_2;
clk_44800000_sg_x0 <= clk_44800000;
register14_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_44800000_sg_x0,
dest_clk => clk_44800000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_10000_sg_x0,
src_clk => clk_10000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net_x0,
dest_ce => ce_10000_sg_x0,
dest_clk => clk_10000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x35,
src_clk => clk_2_sg_x35,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad"
entity upsample_copy_pad_entity_86c97eac4f is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad_entity_86c97eac4f;
architecture structural of upsample_copy_pad_entity_86c97eac4f is
signal ce_1_sg_x73: std_logic;
signal ce_22400000_sg_x19: std_logic;
signal ce_4480_sg_x0: std_logic;
signal clk_1_sg_x73: std_logic;
signal clk_22400000_sg_x19: std_logic;
signal clk_4480_sg_x0: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x73 <= ce_1;
ce_22400000_sg_x19 <= ce_22400000;
ce_4480_sg_x0 <= ce_4480;
clk_1_sg_x73 <= clk_1;
clk_22400000_sg_x19 <= clk_22400000;
clk_4480_sg_x0 <= clk_4480;
register10_q_net_x0 <= din;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x73,
dest_clk => clk_1_sg_x73,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x0,
src_clk => clk_4480_sg_x0,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net_x0,
dest_ce => ce_4480_sg_x0,
dest_clk => clk_4480_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x19,
src_clk => clk_22400000_sg_x19,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad1"
entity upsample_copy_pad1_entity_edde199d79 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din_x0: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad1_entity_edde199d79;
architecture structural of upsample_copy_pad1_entity_edde199d79 is
signal ce_1_sg_x74: std_logic;
signal ce_22400000_sg_x20: std_logic;
signal ce_4480_sg_x1: std_logic;
signal clk_1_sg_x74: std_logic;
signal clk_22400000_sg_x20: std_logic;
signal clk_4480_sg_x1: std_logic;
signal din_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x74 <= ce_1;
ce_22400000_sg_x20 <= ce_22400000;
ce_4480_sg_x1 <= ce_4480;
clk_1_sg_x74 <= clk_1;
clk_22400000_sg_x20 <= clk_22400000;
clk_4480_sg_x1 <= clk_4480;
din_x1 <= din_x0;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x74,
dest_clk => clk_1_sg_x74,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x1,
src_clk => clk_4480_sg_x1,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din_x1,
dest_ce => ce_4480_sg_x1,
dest_clk => clk_4480_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x20,
src_clk => clk_22400000_sg_x20,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_zero_pad"
entity upsample_zero_pad_entity_e334b63be9 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic;
dout: out std_logic
);
end upsample_zero_pad_entity_e334b63be9;
architecture structural of upsample_zero_pad_entity_e334b63be9 is
signal assert13_dout_net_x0: std_logic;
signal ce_1_sg_x77: std_logic;
signal ce_22400000_sg_x23: std_logic;
signal ce_4480_sg_x4: std_logic;
signal clk_1_sg_x77: std_logic;
signal clk_22400000_sg_x23: std_logic;
signal clk_4480_sg_x4: std_logic;
signal up_sample1_q_net_x1: std_logic;
signal up_sample5_q_net: std_logic;
begin
ce_1_sg_x77 <= ce_1;
ce_22400000_sg_x23 <= ce_22400000;
ce_4480_sg_x4 <= ce_4480;
clk_1_sg_x77 <= clk_1;
clk_22400000_sg_x23 <= clk_22400000;
clk_4480_sg_x4 <= clk_4480;
assert13_dout_net_x0 <= din;
dout <= up_sample1_q_net_x1;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => up_sample5_q_net,
dest_ce => ce_1_sg_x77,
dest_clk => clk_1_sg_x77,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x4,
src_clk => clk_4480_sg_x4,
src_clr => '0',
q(0) => up_sample1_q_net_x1
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert13_dout_net_x0,
dest_ce => ce_4480_sg_x4,
dest_clk => clk_4480_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x23,
src_clk => clk_22400000_sg_x23,
src_clr => '0',
q(0) => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit"
entity delta_sigma_monit_entity_a8f8b81626 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_2: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_logic_22400000: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_monit_entity_a8f8b81626;
architecture structural of delta_sigma_monit_entity_a8f8b81626 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert13_dout_net_x3: std_logic;
signal assert2_dout_net_x0: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert9_dout_net_x1: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_10000_sg_x1: std_logic;
signal ce_1_sg_x81: std_logic;
signal ce_22400000_sg_x27: std_logic;
signal ce_2_sg_x36: std_logic;
signal ce_44800000_sg_x1: std_logic;
signal ce_4480_sg_x8: std_logic;
signal ce_5000_sg_x8: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_22400000_sg_x0: std_logic;
signal clk_10000_sg_x1: std_logic;
signal clk_1_sg_x81: std_logic;
signal clk_22400000_sg_x27: std_logic;
signal clk_2_sg_x36: std_logic;
signal clk_44800000_sg_x1: std_logic;
signal clk_4480_sg_x8: std_logic;
signal clk_5000_sg_x8: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_monit_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din_x1: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch_x0: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal down_sample_q_net_x1: std_logic;
signal down_sample_q_net_x2: std_logic_vector(24 downto 0);
signal down_sample_q_net_x3: std_logic;
signal down_sample_q_net_x4: std_logic_vector(24 downto 0);
signal down_sample_q_net_x5: std_logic;
signal down_sample_q_net_x6: std_logic_vector(25 downto 0);
signal down_sample_q_net_x7: std_logic_vector(24 downto 0);
signal down_sample_q_net_x8: std_logic;
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal register11_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x2: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x3: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x4: std_logic;
signal up_sample1_q_net_x5: std_logic;
signal up_sample1_q_net_x6: std_logic;
signal up_sample1_q_net_x7: std_logic;
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x5 <= a;
down_sample1_q_net_x5 <= b;
down_sample3_q_net_x5 <= c;
ce_1_sg_x81 <= ce_1;
ce_10000_sg_x1 <= ce_10000;
ce_2_sg_x36 <= ce_2;
ce_22400000_sg_x27 <= ce_22400000;
ce_4480_sg_x8 <= ce_4480;
ce_44800000_sg_x1 <= ce_44800000;
ce_5000_sg_x8 <= ce_5000;
ce_logic_22400000_sg_x0 <= ce_logic_22400000;
clk_1_sg_x81 <= clk_1;
clk_10000_sg_x1 <= clk_10000;
clk_2_sg_x36 <= clk_2;
clk_22400000_sg_x27 <= clk_22400000;
clk_4480_sg_x8 <= clk_4480;
clk_44800000_sg_x1 <= clk_44800000;
clk_5000_sg_x8 <= clk_5000;
down_sample4_q_net_x5 <= d;
del_sig_div_monit_thres_i_net_x0 <= ds_thres;
q <= assert4_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert10_dout_net_x1;
sum_x0 <= assert5_dout_net_x1;
x <= assert11_dout_net_x1;
x_valid <= assert12_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x1,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x2,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x3,
dout(0) => assert12_dout_net_x1
);
assert13: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert13_dout_net_x3
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert2_dout_net_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x7,
dout => assert4_dout_net_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x0,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x4,
dout => dout_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x5,
dout(0) => valid_ds_down_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x8,
dout(0) => assert9_dout_net_x1
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample3_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_22400000_sg_x0,
clk => clk_22400000_sg_x27,
d(0) => assert13_dout_net_x3,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_0658df0e73: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_b216d22f41: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_352b935ccb: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_8be792d5b9: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d(0) => logical3_y_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
downsample1_4c88924603: entity work.downsample1_entity_4c88924603
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register13_q_net_x0,
dout => down_sample_q_net_x0
);
downsample2_891f07b1a7: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x4,
dout => down_sample_q_net_x1
);
downsample3_dba589aaee: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register12_q_net_x0,
dout => down_sample_q_net_x2
);
downsample4_c9912c17cb: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x3,
dout => down_sample_q_net_x3
);
downsample5_5d411d5dea: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => dout_stretch_x0,
dout => down_sample_q_net_x4
);
downsample6_d7e68015e5: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x1,
dout => down_sample_q_net_x5
);
downsample7_b85055cb62: entity work.downsample7_entity_b85055cb62
port map (
ce_10000 => ce_10000_sg_x1,
ce_2 => ce_2_sg_x36,
ce_44800000 => ce_44800000_sg_x1,
clk_10000 => clk_10000_sg_x1,
clk_2 => clk_2_sg_x36,
clk_44800000 => clk_44800000_sg_x1,
din => register14_q_net_x0,
dout => down_sample_q_net_x6
);
downsample8_69d7284f0d: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register11_q_net_x0,
dout => down_sample_q_net_x7
);
downsample9_f5ac9b8db2: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x2,
dout => down_sample_q_net_x8
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_427f70e3c7: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x2
);
pulse_stretcher2_9a61283281: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x3
);
pulse_stretcher3_864c3e16a6: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x4
);
pulse_stretcher4_8dfd1c8928: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert6_dout_net_x0,
pulse_in => up_sample1_q_net_x6,
extd_out => logical3_y_net_x0
);
pulse_stretcher5_ac376595d0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x0,
pulse_in => up_sample1_q_net_x5,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_694b81e6b2: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert2_dout_net_x0,
pulse_in => up_sample1_q_net_x4,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_bb8174efbd: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x1,
pulse_in => up_sample1_q_net_x7,
extd_out => logical3_y_net_x7
);
pulse_stretcher_6bf297451d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x1
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net_x0
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net_x0
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net_x0
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net_x0
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x36,
clk => clk_2_sg_x36,
d => del_sig_div_monit_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net_x0
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net_x0
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data_x0
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din_x1
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch_x0
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x3,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x2,
output_port => divisor_data
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x1,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x0,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data_x0,
b => down_sample_q_net_x6,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
upsample_copy_pad1_edde199d79: entity work.upsample_copy_pad1_entity_edde199d79
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din_x0 => din_x1,
dout => up_sample1_q_net_x1
);
upsample_copy_pad2_46599e345b: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => divisor_data_x0,
dout => up_sample1_q_net_x2
);
upsample_copy_pad3_3571daa38f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register7_q_net_x0,
dout => up_sample1_q_net_x3
);
upsample_copy_pad_86c97eac4f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register10_q_net_x0,
dout => up_sample1_q_net_x0
);
upsample_zero_pad1_2044d1ec3f: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x5
);
upsample_zero_pad2_7f2f8f8620: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x6
);
upsample_zero_pad3_f0b4acbf28: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x7
);
upsample_zero_pad_e334b63be9: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x4
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_tbt"
entity delta_sigma_tbt_entity_bbfa8a8a69 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_70: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_tbt_entity_bbfa8a8a69;
architecture structural of delta_sigma_tbt_entity_bbfa8a8a69 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x94: std_logic;
signal ce_2_sg_x37: std_logic;
signal ce_70_sg_x26: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_70_sg_x0: std_logic;
signal clk_1_sg_x94: std_logic;
signal clk_2_sg_x37: std_logic;
signal clk_70_sg_x26: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_tbt_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x26 <= a;
down_sample1_q_net_x26 <= b;
down_sample2_q_net_x27 <= c;
ce_1_sg_x94 <= ce_1;
ce_2_sg_x37 <= ce_2;
ce_70_sg_x26 <= ce_70;
ce_logic_70_sg_x0 <= ce_logic_70;
clk_1_sg_x94 <= clk_1;
clk_2_sg_x37 <= clk_2;
clk_70_sg_x26 <= clk_70;
down_sample1_q_net_x27 <= d;
del_sig_div_tbt_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x26,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x27,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_70_sg_x0,
clk => clk_70_sg_x26,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_e5d0399944: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_02a2053e69: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_78179f99cc: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_ed948c360a: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x37,
src_clk => clk_2_sg_x37,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_eef5ee33be: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_6f5c3f41cf: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_e720dfd76f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_0a5eb3f903: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_b95a604b09: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_e7fb2961d9: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_6e7eb70147: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_f661707a58: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x37,
clk => clk_2_sg_x37,
d => del_sig_div_tbt_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1/format1"
entity format1_entity_a98b06306e is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end format1_entity_a98b06306e;
architecture structural of format1_entity_a98b06306e is
signal ce_56000000_sg_x0: std_logic;
signal clk_56000000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net: std_logic_vector(25 downto 0);
begin
ce_56000000_sg_x0 <= ce_56000000;
clk_56000000_sg_x0 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 24,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 24,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_56000000_sg_x0,
clk => clk_56000000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pos_1_c_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1"
entity cast1_entity_3d447d0833 is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
data_in: in std_logic_vector(25 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(24 downto 0);
vld_out: out std_logic
);
end cast1_entity_3d447d0833;
architecture structural of cast1_entity_3d447d0833 is
signal ce_56000000_sg_x1: std_logic;
signal clk_56000000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_56000000_sg_x1 <= ce_56000000;
clk_56000000_sg_x1 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x1 <= data_in;
monit_pos_1_c_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
vld_out <= register1_q_net_x0;
format1_a98b06306e: entity work.format1_entity_a98b06306e
port map (
ce_56000000 => ce_56000000_sg_x1,
clk_56000000 => clk_56000000_sg_x1,
din => monit_pos_1_c_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out/TDDM_monit_pos_1_out_int"
entity tddm_monit_pos_1_out_int_entity_3405798202 is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_224000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout_ch0: out std_logic_vector(25 downto 0);
dout_ch1: out std_logic_vector(25 downto 0);
dout_ch2: out std_logic_vector(25 downto 0);
dout_ch3: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_int_entity_3405798202;
architecture structural of tddm_monit_pos_1_out_int_entity_3405798202 is
signal ce_224000000_sg_x4: std_logic;
signal ce_56000000_sg_x2: std_logic;
signal clk_224000000_sg_x4: std_logic;
signal clk_56000000_sg_x2: std_logic;
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(25 downto 0);
signal register2_q_net: std_logic_vector(25 downto 0);
signal register3_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x1: std_logic_vector(1 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_224000000_sg_x4 <= ce_224000000;
ce_56000000_sg_x2 <= ce_56000000;
register_q_net_x1 <= ch_in;
clk_224000000_sg_x4 <= clk_224000000;
clk_56000000_sg_x2 <= clk_56000000;
concat_y_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register1_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register_q_net_x0,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register2_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register3_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net_x0
);
relational: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant1_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant3_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant4_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out"
entity tddm_monit_pos_1_out_entity_1d58a51dbf is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
clk_224000000: in std_logic;
clk_56000000: in std_logic;
monit_pos_1_ch_in: in std_logic_vector(1 downto 0);
monit_pos_1_din: in std_logic_vector(25 downto 0);
monit_pos_1_q_out: out std_logic_vector(25 downto 0);
monit_pos_1_sum_out: out std_logic_vector(25 downto 0);
monit_pos_1_x_out: out std_logic_vector(25 downto 0);
monit_pos_1_y_out: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_entity_1d58a51dbf;
architecture structural of tddm_monit_pos_1_out_entity_1d58a51dbf is
signal ce_224000000_sg_x5: std_logic;
signal ce_56000000_sg_x3: std_logic;
signal clk_224000000_sg_x5: std_logic;
signal clk_56000000_sg_x3: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
begin
ce_224000000_sg_x5 <= ce_224000000;
ce_56000000_sg_x3 <= ce_56000000;
clk_224000000_sg_x5 <= clk_224000000;
clk_56000000_sg_x3 <= clk_56000000;
register_q_net_x2 <= monit_pos_1_ch_in;
concat_y_net_x1 <= monit_pos_1_din;
monit_pos_1_q_out <= down_sample3_q_net_x1;
monit_pos_1_sum_out <= down_sample4_q_net_x1;
monit_pos_1_x_out <= down_sample2_q_net_x1;
monit_pos_1_y_out <= down_sample1_q_net_x1;
tddm_monit_pos_1_out_int_3405798202: entity work.tddm_monit_pos_1_out_int_entity_3405798202
port map (
ce_224000000 => ce_224000000_sg_x5,
ce_56000000 => ce_56000000_sg_x3,
ch_in => register_q_net_x2,
clk_224000000 => clk_224000000_sg_x5,
clk_56000000 => clk_56000000_sg_x3,
din => concat_y_net_x1,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1"
entity monit_pos_1_entity_522c8cf08d is
port (
ce_1: in std_logic;
ce_224000000: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_logic_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_224000000: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(24 downto 0);
monit_1_pos_q: out std_logic_vector(24 downto 0);
monit_1_pos_x: out std_logic_vector(24 downto 0);
monit_1_pos_y: out std_logic_vector(24 downto 0);
monit_1_sum: out std_logic_vector(24 downto 0);
monit_1_vld_q: out std_logic;
monit_1_vld_sum: out std_logic;
monit_1_vld_x: out std_logic;
monit_1_vld_y: out std_logic;
monit_pos_1_c_x0: out std_logic
);
end monit_pos_1_entity_522c8cf08d;
architecture structural of monit_pos_1_entity_522c8cf08d is
signal ce_1_sg_x95: std_logic;
signal ce_224000000_sg_x6: std_logic;
signal ce_56000000_sg_x4: std_logic;
signal ce_5600000_sg_x11: std_logic;
signal ce_logic_5600000_sg_x1: std_logic;
signal clk_1_sg_x95: std_logic;
signal clk_224000000_sg_x6: std_logic;
signal clk_56000000_sg_x4: std_logic;
signal clk_5600000_sg_x11: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal extractor1_vld_out_net: std_logic;
signal extractor2_dout_net: std_logic_vector(24 downto 0);
signal extractor2_vld_out_net: std_logic;
signal extractor3_dout_net: std_logic_vector(24 downto 0);
signal extractor3_vld_out_net: std_logic;
signal extractor4_dout_net: std_logic_vector(24 downto 0);
signal extractor4_vld_out_net: std_logic;
signal monit_pos_1_c_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
begin
ce_1_sg_x95 <= ce_1;
ce_224000000_sg_x6 <= ce_224000000;
ce_5600000_sg_x11 <= ce_5600000;
ce_56000000_sg_x4 <= ce_56000000;
ce_logic_5600000_sg_x1 <= ce_logic_5600000;
down_sample_q_net_x3 <= ch_in;
clk_1_sg_x95 <= clk_1;
clk_224000000_sg_x6 <= clk_224000000;
clk_5600000_sg_x11 <= clk_5600000;
clk_56000000_sg_x4 <= clk_56000000;
reinterpret5_output_port_net_x1 <= din;
monit_1_pos_q <= reinterpret2_output_port_net_x1;
monit_1_pos_x <= reinterpret3_output_port_net_x1;
monit_1_pos_y <= reinterpret1_output_port_net_x1;
monit_1_sum <= reinterpret4_output_port_net_x1;
monit_1_vld_q <= ufix_to_bool2_dout_net_x1;
monit_1_vld_sum <= ufix_to_bool3_dout_net_x1;
monit_1_vld_x <= ufix_to_bool_dout_net_x1;
monit_1_vld_y <= ufix_to_bool1_dout_net_x1;
monit_pos_1_c_x0 <= monit_pos_1_c_event_s_data_chanid_incorrect_net_x0;
cast1_3d447d0833: entity work.cast1_entity_3d447d0833
port map (
ce_56000000 => ce_56000000_sg_x4,
clk_56000000 => clk_56000000_sg_x4,
data_in => monit_pos_1_c_m_axis_data_tdata_net_x1,
en => monit_pos_1_c_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0,
vld_out => register1_q_net_x0
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => register1_q_net_x0,
in1 => reinterpret5_output_port_net,
y => concat_y_net_x1
);
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample3_q_net_x1,
dout => extractor1_dout_net,
vld_out(0) => extractor1_vld_out_net
);
extractor2: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample1_q_net_x1,
dout => extractor2_dout_net,
vld_out(0) => extractor2_vld_out_net
);
extractor3: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample4_q_net_x1,
dout => extractor3_dout_net,
vld_out(0) => extractor3_vld_out_net
);
extractor4: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample2_q_net_x1,
dout => extractor4_dout_net,
vld_out(0) => extractor4_vld_out_net
);
monit_pos_1_c: entity work.xlfir_compiler_eebfed0cb0075aa32aca169bb967f58b
port map (
ce => ce_1_sg_x95,
ce_5600000 => ce_5600000_sg_x11,
ce_56000000 => ce_56000000_sg_x4,
ce_logic_5600000 => ce_logic_5600000_sg_x1,
clk => clk_1_sg_x95,
clk_5600000 => clk_5600000_sg_x11,
clk_56000000 => clk_56000000_sg_x4,
clk_logic_5600000 => clk_5600000_sg_x11,
s_axis_data_tdata => reinterpret5_output_port_net_x1,
s_axis_data_tuser_chanid => down_sample_q_net_x3,
src_ce => ce_5600000_sg_x11,
src_clk => clk_5600000_sg_x11,
event_s_data_chanid_incorrect => monit_pos_1_c_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pos_1_c_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pos_1_c_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pos_1_c_m_axis_data_tvalid_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_56000000_sg_x4,
clk => clk_56000000_sg_x4,
d => monit_pos_1_c_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register_q_net_x2
);
reinterpret1: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor2_dout_net,
output_port => reinterpret1_output_port_net_x1
);
reinterpret2: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret2_output_port_net_x1
);
reinterpret3: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor4_dout_net,
output_port => reinterpret3_output_port_net_x1
);
reinterpret4: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor3_dout_net,
output_port => reinterpret4_output_port_net_x1
);
reinterpret5: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x0,
output_port => reinterpret5_output_port_net
);
tddm_monit_pos_1_out_1d58a51dbf: entity work.tddm_monit_pos_1_out_entity_1d58a51dbf
port map (
ce_224000000 => ce_224000000_sg_x6,
ce_56000000 => ce_56000000_sg_x4,
clk_224000000 => clk_224000000_sg_x6,
clk_56000000 => clk_56000000_sg_x4,
monit_pos_1_ch_in => register_q_net_x2,
monit_pos_1_din => concat_y_net_x1,
monit_pos_1_q_out => down_sample3_q_net_x1,
monit_pos_1_sum_out => down_sample4_q_net_x1,
monit_pos_1_x_out => down_sample2_q_net_x1,
monit_pos_1_y_out => down_sample1_q_net_x1
);
ufix_to_bool: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor4_vld_out_net,
en => "1",
dout(0) => ufix_to_bool_dout_net_x1
);
ufix_to_bool1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor2_vld_out_net,
en => "1",
dout(0) => ufix_to_bool1_dout_net_x1
);
ufix_to_bool2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor1_vld_out_net,
en => "1",
dout(0) => ufix_to_bool2_dout_net_x1
);
ufix_to_bool3: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor3_vld_out_net,
en => "1",
dout(0) => ufix_to_bool3_dout_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066"
entity ddc_bpm_476_066 is
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_1120: in std_logic;
ce_1400000: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_22400000: in std_logic;
ce_224000000: in std_logic;
ce_2500: in std_logic;
ce_2800000: in std_logic;
ce_35: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2240: in std_logic;
ce_logic_22400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ce_logic_5600000: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_1120: in std_logic;
clk_1400000: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
clk_22400000: in std_logic;
clk_224000000: in std_logic;
clk_2500: in std_logic;
clk_2800000: in std_logic;
clk_35: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
clk_70: in std_logic;
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end ddc_bpm_476_066;
architecture structural of ddc_bpm_476_066 is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "ddc_bpm_476_066,sysgen_core,{clock_period=4.44116092,clocking=Clock_Enables,compilation=HDL_Netlist,sample_periods=1.00000000000 2.00000000000 35.00000000000 70.00000000000 560.00000000000 1120.00000000000 2240.00000000000 2500.00000000000 4480.00000000000 5000.00000000000 10000.00000000000 1400000.00000000000 2800000.00000000000 5600000.00000000000 22400000.00000000000 44800000.00000000000 56000000.00000000000 224000000.00000000000,testbench=0,total_blocks=3351,xilinx_adder_subtracter_block=30,xilinx_arithmetic_relational_operator_block=66,xilinx_assert_block=55,xilinx_bit_slice_extractor_block=20,xilinx_bitbasher_block=5,xilinx_bitwise_expression_evaluator_block=3,xilinx_black_box_block=1,xilinx_bus_concatenator_block=9,xilinx_bus_multiplexer_block=8,xilinx_cic_compiler_3_0_block=5,xilinx_clock_enable_probe_block=11,xilinx_complex_multiplier_5_0__block=2,xilinx_constant_block_block=83,xilinx_cordic_5_0_block=4,xilinx_counter_block=8,xilinx_delay_block=59,xilinx_divider_generator_4_0_block=9,xilinx_down_sampler_block=118,xilinx_fir_compiler_6_3_block=5,xilinx_gateway_in_block=22,xilinx_gateway_out_block=233,xilinx_inverter_block=24,xilinx_logical_block_block=72,xilinx_multiplier_block=16,xilinx_register_block=264,xilinx_sample_time_block_block=88,xilinx_system_generator_block=1,xilinx_type_converter_block=23,xilinx_type_reinterpreter_block=94,xilinx_up_sampler_block=68,xilinx_wavescope_block=2,}";
signal adc_ch0_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch0_i_net: std_logic_vector(15 downto 0);
signal adc_ch1_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch1_i_net: std_logic_vector(15 downto 0);
signal adc_ch2_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch2_i_net: std_logic_vector(15 downto 0);
signal adc_ch3_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch3_i_net: std_logic_vector(15 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert10_dout_net_x2: std_logic;
signal assert10_dout_net_x3: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert11_dout_net_x2: std_logic_vector(24 downto 0);
signal assert11_dout_net_x3: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert12_dout_net_x2: std_logic;
signal assert12_dout_net_x3: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x2: std_logic_vector(24 downto 0);
signal assert5_dout_net_x3: std_logic_vector(24 downto 0);
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert8_dout_net_x2: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert9_dout_net_x2: std_logic;
signal assert9_dout_net_x3: std_logic;
signal bpf_ch0_o_net: std_logic_vector(23 downto 0);
signal bpf_ch1_o_net: std_logic_vector(23 downto 0);
signal bpf_ch2_o_net: std_logic_vector(23 downto 0);
signal bpf_ch3_o_net: std_logic_vector(23 downto 0);
signal ce_10000_sg_x2: std_logic;
signal ce_1120_sg_x32: std_logic;
signal ce_1400000_sg_x3: std_logic;
signal ce_1_sg_x96: std_logic;
signal ce_224000000_sg_x7: std_logic;
signal ce_22400000_sg_x28: std_logic;
signal ce_2240_sg_x28: std_logic;
signal ce_2500_sg_x3: std_logic;
signal ce_2800000_sg_x4: std_logic;
signal ce_2_sg_x38: std_logic;
signal ce_35_sg_x22: std_logic;
signal ce_44800000_sg_x2: std_logic;
signal ce_4480_sg_x9: std_logic;
signal ce_5000_sg_x9: std_logic;
signal ce_56000000_sg_x5: std_logic;
signal ce_5600000_sg_x12: std_logic;
signal ce_560_sg_x3: std_logic;
signal ce_70_sg_x27: std_logic;
signal ce_logic_1400000_sg_x2: std_logic;
signal ce_logic_1_sg_x20: std_logic;
signal ce_logic_22400000_sg_x1: std_logic;
signal ce_logic_2240_sg_x1: std_logic;
signal ce_logic_2800000_sg_x2: std_logic;
signal ce_logic_5600000_sg_x2: std_logic;
signal ce_logic_560_sg_x3: std_logic;
signal ce_logic_70_sg_x1: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal cic_fofb_q_01_missing_o_net: std_logic;
signal cic_fofb_q_23_missing_o_net: std_logic;
signal clk_10000_sg_x2: std_logic;
signal clk_1120_sg_x32: std_logic;
signal clk_1400000_sg_x3: std_logic;
signal clk_1_sg_x96: std_logic;
signal clk_224000000_sg_x7: std_logic;
signal clk_22400000_sg_x28: std_logic;
signal clk_2240_sg_x28: std_logic;
signal clk_2500_sg_x3: std_logic;
signal clk_2800000_sg_x4: std_logic;
signal clk_2_sg_x38: std_logic;
signal clk_35_sg_x22: std_logic;
signal clk_44800000_sg_x2: std_logic;
signal clk_4480_sg_x9: std_logic;
signal clk_5000_sg_x9: std_logic;
signal clk_56000000_sg_x5: std_logic;
signal clk_5600000_sg_x12: std_logic;
signal clk_560_sg_x3: std_logic;
signal clk_70_sg_x27: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant15_op_net_x1: std_logic;
signal constant3_op_net_x1: std_logic;
signal dds_config_valid_ch0_i_net: std_logic;
signal dds_config_valid_ch1_i_net: std_logic;
signal dds_config_valid_ch2_i_net: std_logic;
signal dds_config_valid_ch3_i_net: std_logic;
signal dds_pinc_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch3_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch3_i_net: std_logic_vector(29 downto 0);
signal del_sig_div_fofb_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_monit_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_tbt_thres_i_net: std_logic_vector(25 downto 0);
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_down_x2: std_logic_vector(24 downto 0);
signal dout_down_x3: std_logic_vector(24 downto 0);
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal fofb_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ksum_i_net: std_logic_vector(24 downto 0);
signal kx_i_net: std_logic_vector(24 downto 0);
signal ky_i_net: std_logic_vector(24 downto 0);
signal mix_ch0_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch0_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_q_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal monit_cfir_incorrect_o_net: std_logic;
signal monit_cic_unexpected_o_net: std_logic;
signal monit_pfir_incorrect_o_net: std_logic;
signal monit_pos_1_incorrect_o_net: std_logic;
signal q_fofb_o_net: std_logic_vector(25 downto 0);
signal q_fofb_valid_o_net: std_logic;
signal q_monit_1_o_net: std_logic_vector(25 downto 0);
signal q_monit_1_valid_o_net: std_logic;
signal q_monit_o_net: std_logic_vector(25 downto 0);
signal q_monit_valid_o_net: std_logic;
signal q_tbt_o_net: std_logic_vector(25 downto 0);
signal q_tbt_valid_o_net: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x31: std_logic_vector(23 downto 0);
signal register_q_net_x32: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal sum_fofb_o_net: std_logic_vector(25 downto 0);
signal sum_fofb_valid_o_net: std_logic;
signal sum_monit_1_o_net: std_logic_vector(25 downto 0);
signal sum_monit_1_valid_o_net: std_logic;
signal sum_monit_o_net: std_logic_vector(25 downto 0);
signal sum_monit_valid_o_net: std_logic;
signal sum_tbt_o_net: std_logic_vector(25 downto 0);
signal sum_tbt_valid_o_net: std_logic;
signal tbt_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch01_incorrect_o_net: std_logic;
signal tbt_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch23_incorrect_o_net: std_logic;
signal tbt_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
signal valid_ds_down_x1: std_logic;
signal valid_ds_down_x2: std_logic;
signal valid_ds_down_x3: std_logic;
signal x_fofb_o_net: std_logic_vector(25 downto 0);
signal x_fofb_valid_o_net: std_logic;
signal x_monit_1_o_net: std_logic_vector(25 downto 0);
signal x_monit_1_valid_o_net: std_logic;
signal x_monit_o_net: std_logic_vector(25 downto 0);
signal x_monit_valid_o_net: std_logic;
signal x_tbt_o_net: std_logic_vector(25 downto 0);
signal x_tbt_valid_o_net: std_logic;
signal y_fofb_o_net: std_logic_vector(25 downto 0);
signal y_fofb_valid_o_net: std_logic;
signal y_monit_1_o_net: std_logic_vector(25 downto 0);
signal y_monit_1_valid_o_net: std_logic;
signal y_monit_o_net: std_logic_vector(25 downto 0);
signal y_monit_valid_o_net: std_logic;
signal y_tbt_o_net: std_logic_vector(25 downto 0);
signal y_tbt_valid_o_net: std_logic;
begin
adc_ch0_i_net <= adc_ch0_i;
adc_ch1_i_net <= adc_ch1_i;
adc_ch2_i_net <= adc_ch2_i;
adc_ch3_i_net <= adc_ch3_i;
ce_1_sg_x96 <= ce_1;
ce_10000_sg_x2 <= ce_10000;
ce_1120_sg_x32 <= ce_1120;
ce_1400000_sg_x3 <= ce_1400000;
ce_2_sg_x38 <= ce_2;
ce_2240_sg_x28 <= ce_2240;
ce_22400000_sg_x28 <= ce_22400000;
ce_224000000_sg_x7 <= ce_224000000;
ce_2500_sg_x3 <= ce_2500;
ce_2800000_sg_x4 <= ce_2800000;
ce_35_sg_x22 <= ce_35;
ce_4480_sg_x9 <= ce_4480;
ce_44800000_sg_x2 <= ce_44800000;
ce_5000_sg_x9 <= ce_5000;
ce_560_sg_x3 <= ce_560;
ce_5600000_sg_x12 <= ce_5600000;
ce_56000000_sg_x5 <= ce_56000000;
ce_70_sg_x27 <= ce_70;
ce_logic_1_sg_x20 <= ce_logic_1;
ce_logic_1400000_sg_x2 <= ce_logic_1400000;
ce_logic_2240_sg_x1 <= ce_logic_2240;
ce_logic_22400000_sg_x1 <= ce_logic_22400000;
ce_logic_2800000_sg_x2 <= ce_logic_2800000;
ce_logic_560_sg_x3 <= ce_logic_560;
ce_logic_5600000_sg_x2 <= ce_logic_5600000;
ce_logic_70_sg_x1 <= ce_logic_70;
clk_1_sg_x96 <= clk_1;
clk_10000_sg_x2 <= clk_10000;
clk_1120_sg_x32 <= clk_1120;
clk_1400000_sg_x3 <= clk_1400000;
clk_2_sg_x38 <= clk_2;
clk_2240_sg_x28 <= clk_2240;
clk_22400000_sg_x28 <= clk_22400000;
clk_224000000_sg_x7 <= clk_224000000;
clk_2500_sg_x3 <= clk_2500;
clk_2800000_sg_x4 <= clk_2800000;
clk_35_sg_x22 <= clk_35;
clk_4480_sg_x9 <= clk_4480;
clk_44800000_sg_x2 <= clk_44800000;
clk_5000_sg_x9 <= clk_5000;
clk_560_sg_x3 <= clk_560;
clk_5600000_sg_x12 <= clk_5600000;
clk_56000000_sg_x5 <= clk_56000000;
clk_70_sg_x27 <= clk_70;
dds_config_valid_ch0_i_net <= dds_config_valid_ch0_i;
dds_config_valid_ch1_i_net <= dds_config_valid_ch1_i;
dds_config_valid_ch2_i_net <= dds_config_valid_ch2_i;
dds_config_valid_ch3_i_net <= dds_config_valid_ch3_i;
dds_pinc_ch0_i_net <= dds_pinc_ch0_i;
dds_pinc_ch1_i_net <= dds_pinc_ch1_i;
dds_pinc_ch2_i_net <= dds_pinc_ch2_i;
dds_pinc_ch3_i_net <= dds_pinc_ch3_i;
dds_poff_ch0_i_net <= dds_poff_ch0_i;
dds_poff_ch1_i_net <= dds_poff_ch1_i;
dds_poff_ch2_i_net <= dds_poff_ch2_i;
dds_poff_ch3_i_net <= dds_poff_ch3_i;
del_sig_div_fofb_thres_i_net <= del_sig_div_fofb_thres_i;
del_sig_div_monit_thres_i_net <= del_sig_div_monit_thres_i;
del_sig_div_tbt_thres_i_net <= del_sig_div_tbt_thres_i;
ksum_i_net <= ksum_i;
kx_i_net <= kx_i;
ky_i_net <= ky_i;
adc_ch0_dbg_data_o <= adc_ch0_dbg_data_o_net;
adc_ch1_dbg_data_o <= adc_ch1_dbg_data_o_net;
adc_ch2_dbg_data_o <= adc_ch2_dbg_data_o_net;
adc_ch3_dbg_data_o <= adc_ch3_dbg_data_o_net;
bpf_ch0_o <= bpf_ch0_o_net;
bpf_ch1_o <= bpf_ch1_o_net;
bpf_ch2_o <= bpf_ch2_o_net;
bpf_ch3_o <= bpf_ch3_o_net;
cic_fofb_q_01_missing_o <= cic_fofb_q_01_missing_o_net;
cic_fofb_q_23_missing_o <= cic_fofb_q_23_missing_o_net;
fofb_amp_ch0_o <= fofb_amp_ch0_o_net;
fofb_amp_ch1_o <= fofb_amp_ch1_o_net;
fofb_amp_ch2_o <= fofb_amp_ch2_o_net;
fofb_amp_ch3_o <= fofb_amp_ch3_o_net;
fofb_decim_ch0_i_o <= fofb_decim_ch0_i_o_net;
fofb_decim_ch0_q_o <= fofb_decim_ch0_q_o_net;
fofb_decim_ch1_i_o <= fofb_decim_ch1_i_o_net;
fofb_decim_ch1_q_o <= fofb_decim_ch1_q_o_net;
fofb_decim_ch2_i_o <= fofb_decim_ch2_i_o_net;
fofb_decim_ch2_q_o <= fofb_decim_ch2_q_o_net;
fofb_decim_ch3_i_o <= fofb_decim_ch3_i_o_net;
fofb_decim_ch3_q_o <= fofb_decim_ch3_q_o_net;
fofb_pha_ch0_o <= fofb_pha_ch0_o_net;
fofb_pha_ch1_o <= fofb_pha_ch1_o_net;
fofb_pha_ch2_o <= fofb_pha_ch2_o_net;
fofb_pha_ch3_o <= fofb_pha_ch3_o_net;
mix_ch0_i_o <= mix_ch0_i_o_net;
mix_ch0_q_o <= mix_ch0_q_o_net;
mix_ch1_i_o <= mix_ch1_i_o_net;
mix_ch1_q_o <= mix_ch1_q_o_net;
mix_ch2_i_o <= mix_ch2_i_o_net;
mix_ch2_q_o <= mix_ch2_q_o_net;
mix_ch3_i_o <= mix_ch3_i_o_net;
mix_ch3_q_o <= mix_ch3_q_o_net;
monit_amp_ch0_o <= monit_amp_ch0_o_net;
monit_amp_ch1_o <= monit_amp_ch1_o_net;
monit_amp_ch2_o <= monit_amp_ch2_o_net;
monit_amp_ch3_o <= monit_amp_ch3_o_net;
monit_cfir_incorrect_o <= monit_cfir_incorrect_o_net;
monit_cic_unexpected_o <= monit_cic_unexpected_o_net;
monit_pfir_incorrect_o <= monit_pfir_incorrect_o_net;
monit_pos_1_incorrect_o <= monit_pos_1_incorrect_o_net;
q_fofb_o <= q_fofb_o_net;
q_fofb_valid_o <= q_fofb_valid_o_net;
q_monit_1_o <= q_monit_1_o_net;
q_monit_1_valid_o <= q_monit_1_valid_o_net;
q_monit_o <= q_monit_o_net;
q_monit_valid_o <= q_monit_valid_o_net;
q_tbt_o <= q_tbt_o_net;
q_tbt_valid_o <= q_tbt_valid_o_net;
sum_fofb_o <= sum_fofb_o_net;
sum_fofb_valid_o <= sum_fofb_valid_o_net;
sum_monit_1_o <= sum_monit_1_o_net;
sum_monit_1_valid_o <= sum_monit_1_valid_o_net;
sum_monit_o <= sum_monit_o_net;
sum_monit_valid_o <= sum_monit_valid_o_net;
sum_tbt_o <= sum_tbt_o_net;
sum_tbt_valid_o <= sum_tbt_valid_o_net;
tbt_amp_ch0_o <= tbt_amp_ch0_o_net;
tbt_amp_ch1_o <= tbt_amp_ch1_o_net;
tbt_amp_ch2_o <= tbt_amp_ch2_o_net;
tbt_amp_ch3_o <= tbt_amp_ch3_o_net;
tbt_decim_ch01_incorrect_o <= tbt_decim_ch01_incorrect_o_net;
tbt_decim_ch0_i_o <= tbt_decim_ch0_i_o_net;
tbt_decim_ch0_q_o <= tbt_decim_ch0_q_o_net;
tbt_decim_ch1_i_o <= tbt_decim_ch1_i_o_net;
tbt_decim_ch1_q_o <= tbt_decim_ch1_q_o_net;
tbt_decim_ch23_incorrect_o <= tbt_decim_ch23_incorrect_o_net;
tbt_decim_ch2_i_o <= tbt_decim_ch2_i_o_net;
tbt_decim_ch2_q_o <= tbt_decim_ch2_q_o_net;
tbt_decim_ch3_i_o <= tbt_decim_ch3_i_o_net;
tbt_decim_ch3_q_o <= tbt_decim_ch3_q_o_net;
tbt_pha_ch0_o <= tbt_pha_ch0_o_net;
tbt_pha_ch1_o <= tbt_pha_ch1_o_net;
tbt_pha_ch2_o <= tbt_pha_ch2_o_net;
tbt_pha_ch3_o <= tbt_pha_ch3_o_net;
x_fofb_o <= x_fofb_o_net;
x_fofb_valid_o <= x_fofb_valid_o_net;
x_monit_1_o <= x_monit_1_o_net;
x_monit_1_valid_o <= x_monit_1_valid_o_net;
x_monit_o <= x_monit_o_net;
x_monit_valid_o <= x_monit_valid_o_net;
x_tbt_o <= x_tbt_o_net;
x_tbt_valid_o <= x_tbt_valid_o_net;
y_fofb_o <= y_fofb_o_net;
y_fofb_valid_o <= y_fofb_valid_o_net;
y_monit_1_o <= y_monit_1_o_net;
y_monit_1_valid_o <= y_monit_1_valid_o_net;
y_monit_o <= y_monit_o_net;
y_monit_valid_o <= y_monit_valid_o_net;
y_tbt_o <= y_tbt_o_net;
y_tbt_valid_o <= y_tbt_valid_o_net;
bpf_d31c4af409: entity work.bpf_entity_d31c4af409
port map (
din_ch0 => adc_ch0_dbg_data_o_net,
din_ch1 => adc_ch1_dbg_data_o_net,
din_ch2 => adc_ch2_dbg_data_o_net,
din_ch3 => adc_ch3_dbg_data_o_net,
dout_ch0 => bpf_ch0_o_net,
dout_ch1 => bpf_ch1_o_net,
dout_ch2 => bpf_ch2_o_net,
dout_ch3 => bpf_ch3_o_net
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert12_dout_net_x2,
in1 => reinterpret1_output_port_net,
y => concat_y_net_x0
);
concat1: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => valid_ds_down_x2,
in1 => reinterpret2_output_port_net,
y => concat1_y_net_x0
);
concat2: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert9_dout_net_x2,
in1 => reinterpret3_output_port_net,
y => concat2_y_net_x0
);
concat3: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert10_dout_net_x2,
in1 => reinterpret4_output_port_net,
y => concat3_y_net_x0
);
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant15: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant15_op_net_x1
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net_x1
);
convert_filt_fda412c1bf: entity work.convert_filt_entity_fda412c1bf
port map (
din => down_sample_q_net_x4,
dout => reinterpret5_output_port_net_x1
);
dds_sub_a4b6b880f6: entity work.dds_sub_entity_a4b6b880f6
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_01_cosine => register_q_net_x12,
dds_01_sine => register_q_net_x13,
dds_23_cosine => register_q_net_x14,
dds_23_sine => register_q_net_x15
);
delta_sigma_fofb_ee61e649ea: entity work.delta_sigma_fofb_entity_ee61e649ea
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
c => down_sample2_q_net_x21,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_logic_2240 => ce_logic_2240_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
d => down_sample1_q_net_x21,
ds_thres => del_sig_div_fofb_thres_i_net,
q => assert8_dout_net_x1,
q_valid => assert9_dout_net_x1,
sum_valid => assert12_dout_net_x1,
sum_x0 => assert11_dout_net_x1,
x => assert5_dout_net_x1,
x_valid => assert10_dout_net_x1,
y => dout_down_x1,
y_valid => valid_ds_down_x1
);
delta_sigma_monit_a8f8b81626: entity work.delta_sigma_monit_entity_a8f8b81626
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
c => down_sample3_q_net_x5,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
d => down_sample4_q_net_x5,
ds_thres => del_sig_div_monit_thres_i_net,
q => assert4_dout_net_x1,
q_valid => assert9_dout_net_x2,
sum_valid => assert10_dout_net_x2,
sum_x0 => assert5_dout_net_x2,
x => assert11_dout_net_x2,
x_valid => assert12_dout_net_x2,
y => dout_down_x2,
y_valid => valid_ds_down_x2
);
delta_sigma_tbt_bbfa8a8a69: entity work.delta_sigma_tbt_entity_bbfa8a8a69
port map (
a => down_sample2_q_net_x34,
b => down_sample1_q_net_x34,
c => down_sample2_q_net_x35,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
d => down_sample1_q_net_x35,
ds_thres => del_sig_div_tbt_thres_i_net,
q => assert8_dout_net_x2,
q_valid => assert9_dout_net_x3,
sum_valid => assert12_dout_net_x3,
sum_x0 => assert11_dout_net_x3,
x => assert5_dout_net_x3,
x_valid => assert10_dout_net_x3,
y => dout_down_x3,
y_valid => valid_ds_down_x3
);
fofb_amp_8b25d4b0b6: entity work.fofb_amp_entity_8b25d4b0b6
port map (
ce_1 => ce_1_sg_x96,
ce_1120 => ce_1120_sg_x32,
ce_2240 => ce_2240_sg_x28,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_1120 => clk_1120_sg_x32,
clk_2240 => clk_2240_sg_x28,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x20,
amp_out1 => down_sample1_q_net_x20,
amp_out2 => down_sample2_q_net_x21,
amp_out3 => down_sample1_q_net_x21,
fofb_amp0 => fofb_amp_ch1_o_net,
fofb_amp0_x0 => fofb_amp_ch0_o_net,
fofb_amp0_x1 => fofb_pha_ch1_o_net,
fofb_amp0_x2 => fofb_pha_ch0_o_net,
fofb_amp0_x3 => fofb_decim_ch1_i_o_net,
fofb_amp0_x4 => fofb_decim_ch0_i_o_net,
fofb_amp0_x5 => fofb_decim_ch1_q_o_net,
fofb_amp0_x6 => fofb_decim_ch0_q_o_net,
fofb_amp0_x7 => cic_fofb_q_01_missing_o_net,
fofb_amp1 => fofb_amp_ch3_o_net,
fofb_amp1_x0 => fofb_amp_ch2_o_net,
fofb_amp1_x1 => fofb_pha_ch3_o_net,
fofb_amp1_x2 => fofb_pha_ch2_o_net,
fofb_amp1_x3 => fofb_decim_ch3_i_o_net,
fofb_amp1_x4 => fofb_decim_ch2_i_o_net,
fofb_amp1_x5 => fofb_decim_ch3_q_o_net,
fofb_amp1_x6 => fofb_decim_ch2_q_o_net,
fofb_amp1_x7 => cic_fofb_q_23_missing_o_net
);
k_fofb_mult3_697accc8e2: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert5_dout_net_x1,
in2 => kx_i_net,
vld_in => assert10_dout_net_x1,
out1 => x_fofb_o_net,
vld_out => x_fofb_valid_o_net
);
k_fofb_mult4_102b49a84e: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => dout_down_x1,
in2 => ky_i_net,
vld_in => valid_ds_down_x1,
out1 => y_fofb_o_net,
vld_out => y_fofb_valid_o_net
);
k_fofb_mult5_ed47def699: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert8_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x1,
out1 => q_fofb_o_net,
vld_out => q_fofb_valid_o_net
);
k_monit_1_mult2_30ad492eba: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret1_output_port_net_x1,
in2 => ky_i_net,
vld_in => ufix_to_bool1_dout_net_x1,
out1 => y_monit_1_o_net,
vld_out => y_monit_1_valid_o_net
);
k_monit_1_mult6_71da64dfef: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret2_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool2_dout_net_x1,
out1 => q_monit_1_o_net,
vld_out => q_monit_1_valid_o_net
);
k_monit_1_mult_016885a3ac: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret3_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool_dout_net_x1,
out1 => x_monit_1_o_net,
vld_out => x_monit_1_valid_o_net
);
k_monit_mult3_8a778fb5f4: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert11_dout_net_x2,
in2 => kx_i_net,
vld_in => assert12_dout_net_x2,
out1 => x_monit_o_net,
vld_out => x_monit_valid_o_net
);
k_monit_mult4_1b07b5102a: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => dout_down_x2,
in2 => ky_i_net,
vld_in => valid_ds_down_x2,
out1 => y_monit_o_net,
vld_out => y_monit_valid_o_net
);
k_monit_mult5_a064f6aaae: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert4_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x2,
out1 => q_monit_o_net,
vld_out => q_monit_valid_o_net
);
k_tbt_mult1_cebfa469e3: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => dout_down_x3,
in2 => ky_i_net,
vld_in => valid_ds_down_x3,
out1 => y_tbt_o_net,
vld_out => y_tbt_valid_o_net
);
k_tbt_mult2_2b721a52a5: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert8_dout_net_x2,
in2 => kx_i_net,
vld_in => assert9_dout_net_x3,
out1 => q_tbt_o_net,
vld_out => q_tbt_valid_o_net
);
k_tbt_mult_b8fafff255: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert5_dout_net_x3,
in2 => kx_i_net,
vld_in => assert10_dout_net_x3,
out1 => x_tbt_o_net,
vld_out => x_tbt_valid_o_net
);
ksum_fofb_mult4_ac3ed97096: entity work.ksum_fofb_mult4_entity_ac3ed97096
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert11_dout_net_x1,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x1,
out1 => sum_fofb_o_net,
vld_out => sum_fofb_valid_o_net
);
ksum_monit_1_mult1_c66dc07078: entity work.ksum_monit_1_mult1_entity_c66dc07078
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret4_output_port_net_x1,
in2 => ksum_i_net,
vld_in => ufix_to_bool3_dout_net_x1,
out1 => sum_monit_1_o_net,
vld_out => sum_monit_1_valid_o_net
);
ksum_monit_mult2_31877b6d2b: entity work.ksum_monit_mult2_entity_31877b6d2b
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert5_dout_net_x2,
in2 => ksum_i_net,
vld_in => assert10_dout_net_x2,
out1 => sum_monit_o_net,
vld_out => sum_monit_valid_o_net
);
ksum_tbt_mult3_e0be30d675: entity work.ksum_tbt_mult3_entity_e0be30d675
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert11_dout_net_x3,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x3,
out1 => sum_tbt_o_net,
vld_out => sum_tbt_valid_o_net
);
mixer_a1cd828545: entity work.mixer_entity_a1cd828545
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ch_in0 => register1_q_net_x6,
ch_in1 => register1_q_net_x7,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_cosine_0 => register_q_net_x12,
dds_cosine_1 => register_q_net_x14,
dds_msine_0 => register_q_net_x13,
dds_msine_1 => register_q_net_x15,
dds_valid_0 => constant15_op_net_x1,
dds_valid_1 => constant3_op_net_x1,
din0 => register_q_net_x31,
din1 => register_q_net_x32,
ch_out0 => register3_q_net_x15,
ch_out1 => register3_q_net_x16,
i_out0 => register4_q_net_x14,
i_out1 => register4_q_net_x15,
q_out0 => register5_q_net_x14,
q_out1 => register5_q_net_x15,
tddm_mixer => mix_ch1_i_o_net,
tddm_mixer_x0 => mix_ch0_i_o_net,
tddm_mixer_x1 => mix_ch1_q_o_net,
tddm_mixer_x2 => mix_ch0_q_o_net,
tddm_mixer_x3 => mix_ch3_i_o_net,
tddm_mixer_x4 => mix_ch2_i_o_net,
tddm_mixer_x5 => mix_ch3_q_o_net,
tddm_mixer_x6 => mix_ch2_q_o_net
);
monit_amp_44da74e268: entity work.monit_amp_entity_44da74e268
port map (
ce_1 => ce_1_sg_x96,
ce_1400000 => ce_1400000_sg_x3,
ce_22400000 => ce_22400000_sg_x28,
ce_2800000 => ce_2800000_sg_x4,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ch_in => ch_out_x2,
clk_1 => clk_1_sg_x96,
clk_1400000 => clk_1400000_sg_x3,
clk_22400000 => clk_22400000_sg_x28,
clk_2800000 => clk_2800000_sg_x4,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din => dout_x2,
amp_out0 => down_sample2_q_net_x5,
amp_out1 => down_sample1_q_net_x5,
amp_out2 => down_sample3_q_net_x5,
amp_out3 => down_sample4_q_net_x5,
monit_amp_c => monit_amp_ch1_o_net,
monit_amp_c_x0 => monit_amp_ch0_o_net,
monit_amp_c_x1 => monit_amp_ch2_o_net,
monit_amp_c_x2 => monit_amp_ch3_o_net,
monit_amp_c_x3 => monit_cfir_incorrect_o_net,
monit_amp_c_x4 => monit_cic_unexpected_o_net,
monit_amp_c_x5 => monit_pfir_incorrect_o_net
);
monit_pos_1_522c8cf08d: entity work.monit_pos_1_entity_522c8cf08d
port map (
ce_1 => ce_1_sg_x96,
ce_224000000 => ce_224000000_sg_x7,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ch_in => down_sample_q_net_x3,
clk_1 => clk_1_sg_x96,
clk_224000000 => clk_224000000_sg_x7,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
din => reinterpret5_output_port_net_x1,
monit_1_pos_q => reinterpret2_output_port_net_x1,
monit_1_pos_x => reinterpret3_output_port_net_x1,
monit_1_pos_y => reinterpret1_output_port_net_x1,
monit_1_sum => reinterpret4_output_port_net_x1,
monit_1_vld_q => ufix_to_bool2_dout_net_x1,
monit_1_vld_sum => ufix_to_bool3_dout_net_x1,
monit_1_vld_x => ufix_to_bool_dout_net_x1,
monit_1_vld_y => ufix_to_bool1_dout_net_x1,
monit_pos_1_c_x0 => monit_pos_1_incorrect_o_net
);
register1: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch1_i_net,
en => "1",
rst => "0",
q => adc_ch1_dbg_data_o_net
);
register2: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch2_i_net,
en => "1",
rst => "0",
q => adc_ch2_dbg_data_o_net
);
register3: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch3_i_net,
en => "1",
rst => "0",
q => adc_ch3_dbg_data_o_net
);
register_x0: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch0_i_net,
en => "1",
rst => "0",
q => adc_ch0_dbg_data_o_net
);
reinterpret1: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert11_dout_net_x2,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => dout_down_x2,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert4_dout_net_x1,
output_port => reinterpret3_output_port_net
);
reinterpret4: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert5_dout_net_x2,
output_port => reinterpret4_output_port_net
);
tbt_amp_cbd277bb0c: entity work.tbt_amp_entity_cbd277bb0c
port map (
ce_1 => ce_1_sg_x96,
ce_35 => ce_35_sg_x22,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_35 => clk_35_sg_x22,
clk_70 => clk_70_sg_x27,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x34,
amp_out1 => down_sample1_q_net_x34,
amp_out2 => down_sample2_q_net_x35,
amp_out3 => down_sample1_q_net_x35,
tbt_amp0 => tbt_amp_ch1_o_net,
tbt_amp0_x0 => tbt_amp_ch0_o_net,
tbt_amp0_x1 => tbt_pha_ch1_o_net,
tbt_amp0_x2 => tbt_pha_ch0_o_net,
tbt_amp0_x3 => tbt_decim_ch01_incorrect_o_net,
tbt_amp0_x4 => tbt_decim_ch1_i_o_net,
tbt_amp0_x5 => tbt_decim_ch0_i_o_net,
tbt_amp0_x6 => tbt_decim_ch1_q_o_net,
tbt_amp0_x7 => tbt_decim_ch0_q_o_net,
tbt_amp1 => tbt_amp_ch3_o_net,
tbt_amp1_x0 => tbt_amp_ch2_o_net,
tbt_amp1_x1 => tbt_pha_ch3_o_net,
tbt_amp1_x2 => tbt_pha_ch2_o_net,
tbt_amp1_x3 => tbt_decim_ch23_incorrect_o_net,
tbt_amp1_x4 => tbt_decim_ch3_i_o_net,
tbt_amp1_x5 => tbt_decim_ch2_i_o_net,
tbt_amp1_x6 => tbt_decim_ch3_q_o_net,
tbt_amp1_x7 => tbt_decim_ch2_q_o_net
);
tdm_mix_54ce67e6e8: entity work.tdm_mix_entity_54ce67e6e8
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
din_ch0 => bpf_ch0_o_net,
din_ch1 => bpf_ch1_o_net,
din_ch2 => bpf_ch2_o_net,
din_ch3 => bpf_ch3_o_net,
ch_out0 => register1_q_net_x6,
ch_out1 => register1_q_net_x7,
dout0 => register_q_net_x31,
dout1 => register_q_net_x32
);
tdm_monit_1_746ecf54b0: entity work.tdm_monit_1_entity_746ecf54b0
port map (
ce_1 => ce_1_sg_x96,
ce_22400000 => ce_22400000_sg_x28,
ce_2500 => ce_2500_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
clk_1 => clk_1_sg_x96,
clk_22400000 => clk_22400000_sg_x28,
clk_2500 => clk_2500_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din_ch0 => concat_y_net_x0,
din_ch1 => concat1_y_net_x0,
din_ch2 => concat2_y_net_x0,
din_ch3 => concat3_y_net_x0,
rst => constant11_op_net_x0,
ch_out => down_sample_q_net_x3,
dout => down_sample_q_net_x4
);
tdm_monit_6e38292ecb: entity work.tdm_monit_entity_6e38292ecb
port map (
ce_1 => ce_1_sg_x96,
ce_2240 => ce_2240_sg_x28,
ce_560 => ce_560_sg_x3,
ce_logic_560 => ce_logic_560_sg_x3,
clk_1 => clk_1_sg_x96,
clk_2240 => clk_2240_sg_x28,
clk_560 => clk_560_sg_x3,
din_ch0 => down_sample2_q_net_x20,
din_ch1 => down_sample1_q_net_x20,
din_ch2 => down_sample2_q_net_x21,
din_ch3 => down_sample1_q_net_x21,
rst => constant10_op_net_x0,
ch_out => ch_out_x2,
dout => dout_x2
);
end structural;
|
lgpl-3.0
|
QuickJack/logi-hard
|
hdl/wishbone/peripherals/peripheral_template.vhd
|
2
|
3222
|
-- add you license code here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.logi_utils_pack.all ;
entity <component_name> is
generic(wb_size : positive := 16 ;
memory_size : positive := <your component size in memory>
-- add your component generic parameters starting from here
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- add your component interfaces starting from here
);
end <component_name>;
architecture RTL of <component_name>
signal read_ack : std_logic ;
signal write_ack: std_logic ;
signal component_write, component_read : std_logic ;
signal component_addr : std_logic_vector(nbit(memory_size)-1 downto 0);
signal component_write_data, component_read_data: std_logic_vector(wb_size-1 downto 0);
--declare your component signals here
begin
wbs_ack <= read_ack or write_ack;
component_write <= wbs_strobe and wbs_write and wbs_cycle ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if (component_write = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
component_read <= (wbs_strobe and (not wbs_write) and wbs_cycle) ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0' ;
wbs_readdata <= (others => '0');
elsif rising_edge(gls_clk) then
wbs_readdata <= component_read_data ;
if component_read = '1' then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
component_addr <= wbs_address(nbit(memory_size)-1 downto 0);
component_write_data <= wbs_writedata;
-- insert your component code starting from here
-- use the signal component to control your logic
-- here is an example of a 32bit counter that is controlled by the wishbone bus
-- writing at address 0 will change the value of the 16 lower bits while writing to address
-- will change the 16 upper bits
--counter_bloc : process(gls_clk, gls_reset)
--begin
-- if gls_reset = '1' then
-- component_count_low <= (others => '0');
-- component_count_high <= (others => '0');
-- elsif rising_edge(gls_clk) then
-- if write_component = '1' and component_addr = 0 then
-- component_count_high <= component_write_data ;
-- else
-- component_count_high <= component_count_high + 1 ;
-- end if ;
-- if write_component = '1' and component_addr = 1 then
-- component_count_high <= component_write_data ;
-- elsif component_count_high = X"FFFF" then
-- component_count_high <= component_count_high + 1 ;
-- end if ;
-- end if;
--end process counter_bloc;
--component_read_data <= component_count ;
end RTL ;
|
lgpl-3.0
|
QuickJack/logi-hard
|
hdl/wishbone/wishbone_intercon.vhd
|
2
|
3410
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_wishbone_pack.all ;
entity wishbone_intercon is
generic(memory_map : array_of_addr );
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone slave signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector(15 downto 0);
wbs_readdata : out std_logic_vector(15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Wishbone master signals
wbm_address : out array_of_slv16((memory_map'length-1) downto 0) ;
wbm_writedata : out array_of_slv16((memory_map'length-1) downto 0);
wbm_readdata : in array_of_slv16((memory_map'length-1) downto 0);
wbm_strobe : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_cycle : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_write : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_ack : in std_logic_vector((memory_map'length-1) downto 0)
);
end wishbone_intercon;
architecture Behavioral of wishbone_intercon is
signal cs_vector : std_logic_vector(0 to (memory_map'length-1));
signal ack_vector : std_logic_vector(0 to (memory_map'length-1));
begin
gen_cs : for i in 0 to (memory_map'length-1) generate
cs_vector(i) <= '1' when wbs_address(wbs_address'length-1 downto find_X(memory_map(i))) = memory_map(i)(wbs_address'length-1 downto find_X(memory_map(i))) else
'0' ;
ack_vector(i) <= wbm_ack(i) and cs_vector(i) ;
wbm_address(i)(wbs_address'length-1 downto find_X(memory_map(i))) <= (others => '0') ;
wbm_address(i)(find_X(memory_map(i))-1 downto 0) <= wbs_address(find_X(memory_map(i))-1 downto 0) ;
wbm_writedata(i) <= wbs_writedata ;
wbm_write(i) <= wbs_write and cs_vector(i) ;
wbm_strobe(i) <= wbs_strobe and cs_vector(i) ;
wbm_cycle(i) <= wbs_cycle and cs_vector(i) ;
wbs_readdata <= wbm_readdata(i) when cs_vector(i) = '1' else
(others => 'Z') ;
end generate ;
wbs_ack <= '1' when ack_vector /= 0 else
'0' ;
wbs_readdata <= wbs_address when cs_vector = 0 else
(others => 'Z') ;
end Behavioral;
|
lgpl-3.0
|
QuickJack/logi-hard
|
hdl/wishbone/peripherals/wishbone_watchdog.vhd
|
2
|
4536
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, <names> All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_wishbone_peripherals_pack.all ;
use work.logi_utils_pack.all ;
entity wishbone_watchdog is
generic(
wb_size : natural := 16; -- Data port size for wishbone
watchdog_timeout_ms : positive := 1000;
clock_period_ns : positive := 10
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reset_out : out std_logic
);
end wishbone_watchdog;
architecture RTL of wishbone_watchdog is
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- declare your signals here
constant DIVIDER : positive := 1_000_000/clock_period_ns;
signal enable_watchdog : std_logic ;
signal count_divider : std_logic_vector(nbit(DIVIDER)-1 downto 0);
signal count_timeout : std_logic_vector(nbit(watchdog_timeout_ms)-1 downto 0);
signal reset_watchdog, reset_watchdog_old, reset_watchdog_rising_edge : std_logic ;
signal enable, enable_count : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
enable_watchdog <= '0' ;
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
-- complete with what to do on a write
enable_watchdog <= wbs_writedata(0) ;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
-- complete with what to do on a read
wbs_readdata(0) <= enable_watchdog ;
wbs_readdata(15 downto 1) <= (others => '0');
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
--- watchdog logic
reset_watchdog <= write_ack ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
reset_watchdog_old <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
reset_watchdog_old <= reset_watchdog;
end if;
end process ;
reset_watchdog_rising_edge <= (NOT reset_watchdog_old) and reset_watchdog ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
count_divider <= std_logic_vector(to_unsigned(DIVIDER, nbit(DIVIDER))) ;
elsif gls_clk'event and gls_clk = '1' then
if count_divider /= 0 then
count_divider <= count_divider - 1 ;
else
count_divider <= std_logic_vector(to_unsigned(DIVIDER, nbit(DIVIDER))) ;
end if ;
end if;
end process ;
enable_count <= '1' when count_divider = 0 else
'0' ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
count_timeout <= std_logic_vector(to_unsigned(watchdog_timeout_ms, nbit(watchdog_timeout_ms))) ;
elsif gls_clk'event and gls_clk = '1' then
if reset_watchdog_rising_edge = '1' then
count_timeout <= std_logic_vector(to_unsigned(watchdog_timeout_ms, nbit(watchdog_timeout_ms))) ;
elsif count_timeout /= 0 and enable_count = '1' then
count_timeout <= count_timeout - 1 ;
end if ;
end if;
end process ;
reset_out <= '1' when count_timeout = 0 and enable_watchdog = '1' else
'0' ;
end RTL;
|
lgpl-3.0
|
QuickJack/logi-hard
|
hdl/control/mcp3002_interface.vhd
|
2
|
7395
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:47:08 08/26/2013
-- Design Name:
-- Module Name: mcp3002_interface - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.utils_pack.all ;
entity mcp3002_interface is
generic(CLK_DIV : positive := 1024;
SAMPLING_DIV : positive := 2048);
port(
clk, resetn : std_logic ;
sample : out std_logic_vector(9 downto 0);
dv : out std_logic ;
chan : in std_logic ;
-- spi signals
DOUT : out std_logic ;
DIN : in std_logic ;
SCLK : out std_logic ;
SSN : out std_logic
);
end mcp3002_interface;
architecture Behavioral of mcp3002_interface is
type tranfer_state is (WAIT_SAMPLE, ASSERT_CS, XFER_DATA, DEASSERT_CS);
signal current_transfer_state, next_transfer_state : tranfer_state;
signal data_out_shift_reg, data_in_shift_reg : std_logic_vector(15 downto 0) ;
signal load_shift_register : std_logic ;
signal tempo_val : std_logic_vector(15 downto 0);
signal count_tempo : std_logic_vector(15 downto 0 );
signal load_tempo, en_tempo, end_tempo : std_logic ;
signal data_clk, data_clk_old, data_clk_re, data_clk_fe : std_logic ;
signal en_bit_count, reset_bit_count : std_logic ;
signal bit_count : std_logic_vector(4 downto 0);
signal bit_count_eq_16 : std_logic ;
signal cmd_word : std_logic_vector(15 downto 0);
signal ssn_d : std_logic ;
begin
-- tempo
process(clk, resetn)
begin
if resetn = '0' then
count_tempo <= (others => '1');
elsif clk'event and clk = '1' then
if load_tempo = '1' then
count_tempo <= tempo_val ;
elsif en_tempo = '1' then
if count_tempo /= 0 then
count_tempo <= count_tempo - 1 ;
end if ;
end if ;
end if ;
end process ;
end_tempo <= '1' when count_tempo = 0 else
'0' ;
-- bit counter
process(clk, resetn)
begin
if resetn = '0' then
bit_count <= (others => '0');
elsif clk'event and clk = '1' then
if reset_bit_count = '1' then
bit_count <= (others => '0');
elsif en_bit_count = '1' then
bit_count <= bit_count + 1 ;
end if ;
end if ;
end process ;
bit_count_eq_16 <= '1' when bit_count = 16 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
current_transfer_state <= WAIT_SAMPLE;
elsif clk'event and clk = '1' then
current_transfer_state <= next_transfer_state;
end if ;
end process ;
process(bit_count, end_tempo)
begin
next_transfer_state <= current_transfer_state ;
case current_transfer_state is
when wait_sample =>
if end_tempo = '1' then
next_transfer_state <= assert_cs ;
end if ;
when assert_cs =>
if end_tempo = '1' then
next_transfer_state <= xfer_data ;
end if ;
when xfer_data =>
if bit_count = 16 then
next_transfer_state <= deassert_cs ;
end if ;
when deassert_cs =>
if end_tempo = '1' then
next_transfer_state <= wait_sample ;
end if ;
when others =>
next_transfer_state <= wait_sample ;
end case;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
data_clk <= '0' ;
elsif clk'event and clk = '1' then
if current_transfer_state = xfer_data then
if end_tempo = '1' then
data_clk <= not data_clk ;
end if ;
else
data_clk <= '0' ;
end if ;
end if ;
end process ;
-- data clock rising edge and falling edge detect
process(clk, resetn)
begin
if resetn = '0' then
data_clk_old <= '0' ;
elsif clk'event and clk = '1' then
data_clk_old <= data_clk ;
end if ;
end process ;
data_clk_re <= data_clk and (not data_clk_old);
data_clk_fe <= (not data_clk) and data_clk_old;
cmd_word <= "10" & chan & "0" & X"000" ;
--shift register for data out
process(clk, resetn)
begin
if resetn = '0' then
data_out_shift_reg <= (others => '0') ;
elsif clk'event and clk = '1' then
if load_shift_register = '1' then
data_out_shift_reg <= cmd_word ;
elsif data_clk_fe = '1' then
data_out_shift_reg(15 downto 1) <= data_out_shift_reg(14 downto 0) ;
data_out_shift_reg(0) <= '0' ;
end if ;
end if ;
end process ;
--shift register for data in
process(clk, resetn)
begin
if resetn = '0' then
data_in_shift_reg <= (others => '0') ;
elsif clk'event and clk = '1' then
if data_clk_re = '1' then
data_in_shift_reg(15 downto 1) <= data_in_shift_reg(14 downto 0) ;
data_in_shift_reg(0) <= DIN ;
end if ;
end if ;
end process ;
with current_transfer_state select
load_shift_register <= end_tempo when assert_cs,
'0' when others ;
en_tempo <= '1' ;
with current_transfer_state select
tempo_val <= std_logic_vector(to_unsigned(CLK_DIV, 16)) when wait_sample,
std_logic_vector(to_unsigned(CLK_DIV, 16)) when assert_cs,
std_logic_vector(to_unsigned(CLK_DIV, 16)) when xfer_data,
std_logic_vector(to_unsigned(SAMPLING_DIV, 16)) when deassert_cs,
(others => '0') when others ;
with current_transfer_state select
load_tempo <= end_tempo when wait_sample,
end_tempo when assert_cs,
end_tempo when xfer_data,
end_tempo when deassert_cs,
'0' when others ;
with current_transfer_state select
en_bit_count <= data_clk_fe when xfer_data,
'0' when others ;
with current_transfer_state select
reset_bit_count <= bit_count_eq_16 when xfer_data,
'1' when others ;
-- outputs
with current_transfer_state select
ssn_d <= '0' when assert_cs,
'0' when xfer_data,
'1' when others ;
sample <= data_in_shift_reg(9 downto 0);
dv <= '1' when current_transfer_state=xfer_data and bit_count_eq_16= '1' else
'0' ;
-- todo may delete following stuf, output are not combinatorial ...
process(clk, resetn)
begin
if resetn = '0' then
DOUT <= '0' ;
SCLK <= '0' ;
SSN <= '1' ;
elsif clk'event and clk = '1' then
DOUT <= data_out_shift_reg(15) ;
SCLK <= data_clk ;
SSN <= ssn_d ;
end if ;
end process ;
end Behavioral;
|
lgpl-3.0
|
QuickJack/logi-hard
|
test_bench/async_serial_tb.vhd
|
2
|
5330
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:49 03/22/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/async_serial_tb.vhd
-- Project Name: test_ugv
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: async_serial
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
library work ;
use work.logi_utils_pack.all ;
ENTITY async_serial_tb IS
END async_serial_tb;
ARCHITECTURE behavior OF async_serial_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT async_serial
generic(CLK_FREQ : positive := 100_000_000; BAUDRATE : positive := 115_200) ;
PORT(
clk : IN std_logic;
reset : IN std_logic;
rx : IN std_logic;
tx : OUT std_logic;
data_out : OUT std_logic_vector(7 downto 0);
data_in : IN std_logic_vector(7 downto 0);
data_ready : OUT std_logic;
data_send : IN std_logic;
available : out std_logic
);
END COMPONENT;
component nmea_frame_extractor is
generic(nmea_header : string := "$GPRMC");
port(
clk, reset : in std_logic ;
nmea_byte_in : in std_logic_vector(7 downto 0);
new_byte_in : in std_logic ;
nmea_byte_out : out std_logic_vector(7 downto 0);
new_byte_out : out std_logic;
frame_size : out std_logic_vector(7 downto 0);
end_of_frame : out std_logic
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal rx : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_send : std_logic := '0';
--Outputs
signal tx : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_ready : std_logic;
signal available : std_logic ;
signal new_byte_out : std_logic ;
signal nmea_byte_out : std_logic_vector(7 downto 0) ;
signal frame_size : std_logic_vector(7 downto 0) ;
signal end_of_frame : std_logic ;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant baud_period : time := 8680 ns;
constant data_serial : std_logic_vector(7 downto 0) := X"5A";
constant gps_string : STRING (1 to 27):="$GPRMC,0,0,0,1,0,0,0,0,0*56";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: async_serial
GENERIC MAP(CLK_FREQ => 100_000_000)
PORT MAP (
clk => clk,
reset => reset,
rx => rx,
tx => tx,
data_out => data_out,
data_in => data_in,
data_ready => data_ready,
data_send => data_send,
available => available
);
nmea_filter : nmea_frame_extractor
generic map(nmea_header => "$GPRMC")
port map(
clk => clk,
reset => reset,
nmea_byte_in => data_out,
new_byte_in => data_ready,
nmea_byte_out => nmea_byte_out,
new_byte_out => new_byte_out,
frame_size => frame_size,
end_of_frame => end_of_frame
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1' ;
-- rx <= '1' ;
wait for 100 ns;
reset <= '0' ;
-- wait for clk_period*10;
-- rx <= '1' ;
-- wait for baud_period*10;
-- rx <= '0' ; -- start
-- wait for baud_period;
-- loop_0 : for i in 0 to 7 loop
-- rx <= data_serial(i) ; -- start
-- wait for baud_period;
-- end loop ;
-- rx <= '1' ;
-- wait for baud_period*10;
--
-- rx <= '0' ; -- start
-- wait for baud_period;
-- loop_1 : for i in 0 to 7 loop
-- rx <= data_serial(i) ; -- start
-- wait for baud_period;
-- end loop ;
-- rx <= '0' ;
-- wait for baud_period;
-- rx <= '1' ;
-- wait for baud_period*10;
-- -- insert stimulus here
-- rx <= '0' ; -- start
-- wait for baud_period;
-- loop_2 : for i in 0 to 7 loop
-- rx <= data_serial(i) ; -- start
-- wait for baud_period;
-- end loop ;
-- rx <= '1' ;
-- wait for baud_period*10 ;
-- rx <= tx ;
for i in 1 to gps_string'length loop
data_in <= std_logic_vector(to_unsigned(character'pos(gps_string(i)), 8));
data_send <= '1' ;
wait until available = '0' ;
data_send <= '0' ;
wait until data_ready = '1' ;
end loop ;
for i in 0 to 8 loop
data_in <= X"0D";
data_send <= '1' ;
wait until available = '0' ;
data_send <= '0' ;
wait until data_ready = '1' ;
end loop ;
wait;
end process;
rx <= tx ;
END;
|
lgpl-3.0
|
HackLinux/ION
|
src/testbench/common/sim_params_pkg.vhdl
|
1
|
2354
|
--------------------------------------------------------------------------------
-- obj_code_pkg.vhdl -- Application object code in vhdl constant string format.
--------------------------------------------------------------------------------
-- Built for project 'CPU tester'.
--------------------------------------------------------------------------------
-- This file contains object code in the form of a VHDL byte table constant.
-- This constant can be used to initialize FPGA memories for synthesis or
-- simulation.
-- Note that the object code is stored as a plain byte table in byte address
-- order. This table knows nothing of data endianess and can be used to
-- initialize 32-, 16- or 8-bit-wide memory -- memory initialization functions
-- can be found in package mips_pkg.
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
package SIM_PARAMS_PKG is
-- Simulation or synthesis parameters ------------------------------------------
constant SIMULATION_LENGTH : integer := 25000;
constant LOG_TRIGGER_ADDRESS : t_word := X"bfc00000";
-- Memory initialization data --------------------------------------------------
end package SIM_PARAMS_PKG;
|
lgpl-3.0
|
HackLinux/ION
|
src/rtl/buses/ion_tcm_data.vhdl
|
1
|
5572
|
--------------------------------------------------------------------------------
-- ion_tcm_data.vhdl -- Tightly Coupled Memory for the data space.
--------------------------------------------------------------------------------
-- FIXME explain!
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_TCM_DATA is
generic(
-- Size of TCM block in 32-bit words. Set to zero to disable TCM.
SIZE : integer := 4096;
-- Initial contents of TCM. Default is zeros.
INIT_DATA : t_obj_code := zero_objcode(16)
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
EN_I : in std_logic;
MEM_MOSI_I : in t_cpumem_mosi;
MEM_MISO_O : out t_cpumem_miso
);
end;
architecture rtl of ION_TCM_DATA is
constant TCM_ADDR_SIZE : integer := log2(SIZE);
subtype t_tcm_address is std_logic_vector(TCM_ADDR_SIZE-1 downto 2);
signal tcm_addr : t_tcm_address;
signal tcm_rd_data : t_word;
signal tcm_rd_data0 : t_byte;
signal tcm_rd_data1 : t_byte;
signal tcm_rd_data2 : t_byte;
signal tcm_rd_data3 : t_byte;
signal wr_data0 : t_byte;
signal wr_data1 : t_byte;
signal wr_data2 : t_byte;
signal wr_data3 : t_byte;
signal tcm_ram0: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 0);
signal tcm_ram1: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 1);
signal tcm_ram2: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 2);
signal tcm_ram3: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 3);
begin
tcm_addr <= MEM_MOSI_I.addr(tcm_addr'high downto 2);
--------------------------------------------------------------------------------
---- Memory block inference.
-- We ned to implement the TCM as four independent blocks because it's not
-- possible to just infer a BRAM with byte enables. We just don't want to
-- instantiate vendor-specific BRAM entities.
tcm_memory_block0:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data0 <= tcm_ram0(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(0)='1' and EN_I='1' then
tcm_ram0(conv_integer(unsigned(tcm_addr))) <= wr_data0;
end if;
end if;
end process tcm_memory_block0;
tcm_memory_block1:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data1 <= tcm_ram1(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(1)='1' and EN_I='1' then
tcm_ram1(conv_integer(unsigned(tcm_addr))) <= wr_data1;
end if;
end if;
end process tcm_memory_block1;
tcm_memory_block2:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data2 <= tcm_ram2(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(2)='1' and EN_I='1' then
tcm_ram2(conv_integer(unsigned(tcm_addr))) <= wr_data2;
end if;
end if;
end process tcm_memory_block2;
tcm_memory_block3:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data3 <= tcm_ram3(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(3)='1' and EN_I='1' then
tcm_ram3(conv_integer(unsigned(tcm_addr))) <= wr_data3;
end if;
end if;
end process tcm_memory_block3;
wr_data0 <= MEM_MOSI_I.wr_data( 7 downto 0);
wr_data1 <= MEM_MOSI_I.wr_data(15 downto 8);
wr_data2 <= MEM_MOSI_I.wr_data(23 downto 16);
wr_data3 <= MEM_MOSI_I.wr_data(31 downto 24);
MEM_MISO_O.rd_data <= tcm_rd_data3 & tcm_rd_data2 & tcm_rd_data1 & tcm_rd_data0;
MEM_MISO_O.mwait <= '0';
end architecture rtl;
|
lgpl-3.0
|
HackLinux/ION
|
src/rtl/caches/ion_cache.vhdl
|
1
|
15093
|
--------------------------------------------------------------------------------
-- ion_icache.vhdl -- Instruction/Data Cache.
--------------------------------------------------------------------------------
--
--
-- NOTES:
--
-- @note1:
-- All supported CACHE instruction functions involve invalidating a line
-- or explicity zeroing a tag. So the valid flag is always written as 0
-- except when REFILL.
-- Remember our "Store Tag" implementation uses a hardwired zero TagLo.
--
-- @ note2:
-- In the first clock cycle of all write accesses, the addressed line
-- is invalidated. The CPU address is only valid in this cycle so we
-- do it right now and save a register and a mux.
--
-- @note3:
-- When a RD comes the cycle after a WR, we'll lose it unless we register
-- the fact. This happens because the rd_en signal is asserted for a single
-- clock cycle, even if the RD instruction is stalled waiting for the WR
-- to finish.
-- The same thing happens when a WR follows a RD.
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
-- NOTES:
--
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_CACHE is
generic(
-- Number of lines per way.
NUM_LINES : integer := 128;
-- Size of line in 32-bit words.
LINE_SIZE : integer := 8
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
CACHE_CTRL_MOSI_I : in t_cache_mosi;
CACHE_CTRL_MISO_O : out t_cache_miso;
CE_I : in std_logic;
CPU_MOSI_I : in t_cpumem_mosi;
CPU_MISO_O : out t_cpumem_miso;
MEM_MOSI_O : out t_wishbone_mosi;
MEM_MISO_I : in t_wishbone_miso
);
end;
architecture rtl of ION_CACHE is
constant LINE_INDEX_WIDTH : integer := log2(NUM_LINES);
constant LINE_OFFSET_WIDTH : integer := log2(LINE_SIZE);
constant LINE_ADDRESS_WIDTH : integer := LINE_INDEX_WIDTH + LINE_OFFSET_WIDTH;
constant TAG_WIDTH : integer := 32 - 2 - LINE_ADDRESS_WIDTH;
constant LINE_TABLE_SIZE : integer := LINE_SIZE * NUM_LINES;
-- Tag table signals.
subtype t_index is std_logic_vector(LINE_INDEX_WIDTH-1 downto 0);
subtype t_offset is std_logic_vector(LINE_OFFSET_WIDTH-1 downto 0);
subtype t_line_address is std_logic_vector(LINE_ADDRESS_WIDTH-1 downto 0);
subtype t_tag_address is std_logic_vector(TAG_WIDTH-1 downto 0);
-- Valid bit appended to address tag; this is what's stored in the tag table.
subtype t_tag is std_logic_vector(TAG_WIDTH+1-1 downto 0);
-- Tag table implemented as (inferred) synchronous BRAM.
type t_tag_table is array(0 to NUM_LINES-1) of t_tag;
-- Initial value meant for TB only. Helps catch errors in invalidation opcodes.
signal tag_table : t_tag_table; -- := (others => '1' & X"90000");
-- Signals used to access the tag table.
signal tag : t_tag_address;
signal tag_reg : t_tag_address;
signal cached_tag_addr : t_tag_address;
signal line_index : t_index;
signal line_address : t_line_address;
signal cached_tag : t_tag;
signal tag_table_we : std_logic;
-- Valid flag to be stored in tag table.
signal new_valid_flag : std_logic;
-- Valid flag read from tag table during a lookup.
signal cached_tag_valid : std_logic;
-- Line table implemented as (inferred) BRAM table.
type t_line_table is array(0 to LINE_TABLE_SIZE-1) of t_word;
signal line_table : t_line_table;
-- Signals used to access the line table.
signal refill_line_address : t_line_address;
signal refill_line_address_reg : t_line_address;
signal cached_word : t_word;
signal line_table_we : std_logic;
-- Misc control signals.
signal miss : std_logic;
signal lookup : std_logic;
signal lookup_reg : std_logic;
signal write_cycle : std_logic;
signal update_tag : std_logic;
signal data_wr_reg : t_word;
signal addr_reg : t_word;
signal wr_be_reg : std_logic_vector(3 downto 0);
signal read_pending : std_logic;
-- Refill state machine signals.
type t_refill_state is (
HIT,
REFILL,
WRITETHROUGH,
REFILL_LAST_WORD
);
signal ns, ps : t_refill_state;
signal refill_ctr : t_offset;
signal store_delay_ctr : integer range 0 to 2;
signal refill_done : std_logic;
begin
-- CPU interface -----------------------------------------------------------
CPU_MISO_O.rd_data <= cached_word;
CPU_MISO_O.mwait <=
'1' when ps = REFILL else
'1' when ps = REFILL_LAST_WORD else
'1' when ps = HIT and miss = '1' else -- !!
'1' when ps = HIT and read_pending = '1' else -- see @note3
'1' when ps = WRITETHROUGH else
'0';
lookup <=
'1' when CPU_MOSI_I.rd_en='1' and CE_I='1' else
'1' when read_pending='1' and ps=HIT else
'0';
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
lookup_reg <= '0';
else
lookup_reg <= lookup;
if CPU_MOSI_I.wr_be/="0000" then
data_wr_reg <= CPU_MOSI_I.wr_data;
wr_be_reg <= CPU_MOSI_I.wr_be;
end if;
if CPU_MOSI_I.rd_en='1' or CPU_MOSI_I.wr_be/="0000" then
addr_reg <= CPU_MOSI_I.addr;
end if;
end if;
end if;
end process;
-- Assert update_tag for special CACHE instructions only.
-- FIXME control interface is crude and needs to be defined & refactored
update_tag <= '1' when
CACHE_CTRL_MOSI_I.data_cache = '1' and
CACHE_CTRL_MOSI_I.function_en = '1'
else '0';
-- Tag table ---------------------------------------------------------------
-- Extract all relevand fields from incoming CPU address.
tag <= CPU_MOSI_I.addr(31 downto LINE_ADDRESS_WIDTH+2);
tag_reg <= addr_reg(31 downto LINE_ADDRESS_WIDTH+2);
line_index <= CPU_MOSI_I.addr(LINE_ADDRESS_WIDTH+1 downto LINE_OFFSET_WIDTH + 2);
line_address <= CPU_MOSI_I.addr(LINE_ADDRESS_WIDTH+1 downto 2);
-- Tag table inferred BRAM.
synchronous_tag_table:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if tag_table_we='1' then
tag_table(conv_integer(line_index)) <= new_valid_flag & tag;
end if;
cached_tag <= tag_table(conv_integer(line_index));
end if;
end process synchronous_tag_table;
-- Extract fields from the word we just read from the tag table.
cached_tag_valid <= cached_tag(cached_tag'high);
cached_tag_addr <= cached_tag(cached_tag'high-1 downto 0);
-- When in REFILL, set valid flag. Otherwise reset it.
with ps select new_valid_flag <=
'1' when REFILL,
'0' when others; -- see @note1
-- The miss signal needs only be valid in the "HIT" state.
miss <=
'1' when ((cached_tag_addr /= tag_reg) or
(cached_tag_valid = '0')) and
lookup_reg = '1'
else '0';
write_cycle <= '1' when CPU_MOSI_I.wr_be/="0000" and CE_I='1' else '0';
-- Line table --------------------------------------------------------------
-- Line table (inferred) BRAM.
synchronous_line_table:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if line_table_we='1' then
line_table(conv_integer(refill_line_address_reg)) <= MEM_MISO_I.dat;
end if;
cached_word <= line_table(conv_integer(line_address));
end if;
end process synchronous_line_table;
-- Since the target address is only present in the ION CPU bus for a single
-- cycle, we need to register it to use it along the refill operation.
refill_addr_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if lookup = '1' and ps=HIT then
refill_line_address(LINE_ADDRESS_WIDTH-1 downto LINE_OFFSET_WIDTH) <=
CPU_MOSI_I.addr(LINE_ADDRESS_WIDTH-1+2 downto LINE_OFFSET_WIDTH+2);
end if;
refill_line_address_reg <= refill_line_address;
end if;
end process refill_addr_register;
-- The low bits of the refill address come from the refill counter.
refill_line_address(LINE_OFFSET_WIDTH-1 downto 0) <= refill_ctr;
-- We write onto the line table only in the cycles in which there is valid
-- refill data in the refill WB bus.
line_table_we <=
'1' when ps = REFILL and MEM_MISO_I.ack = '1' else
'1' when ps = REFILL_LAST_WORD and store_delay_ctr = 2 else
'0';
-- Refill State Machine ----------------------------------------------------
refill_state_machine_reg:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
ps <= HIT;
else
ps <= ns;
end if;
end if;
end process refill_state_machine_reg;
refill_state_machine_transitions:
process(ps, miss, refill_done, write_cycle, MEM_MISO_I.stall,
store_delay_ctr, read_pending)
begin
case ps is
when HIT =>
if miss='1' then
ns <= REFILL;
elsif write_cycle='1' then
ns <= WRITETHROUGH;
else
ns <= ps;
end if;
when REFILL =>
if refill_done='1' then
ns <= REFILL_LAST_WORD;
else
ns <= ps;
end if;
when REFILL_LAST_WORD =>
if store_delay_ctr = 0 then
ns <= HIT;
else
ns <= ps;
end if;
when WRITETHROUGH =>
if MEM_MISO_I.stall='0' then
ns <= HIT;
else
ns <= ps;
end if;
when others =>
-- NOTE: We´re not detecting here a real derailed HW state machine,
-- only a buggy rtl.
ns <= HIT;
end case;
end process refill_state_machine_transitions;
-- When the last word in the line has been read from the WB bus, we are done
-- REFILL.
refill_done <=
'1' when refill_ctr = (LINE_SIZE-1) and MEM_MISO_I.stall = '0'
else '0';
refill_word_counter:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I = '1' then
refill_ctr <= (others => '0');
elsif ps = REFILL and MEM_MISO_I.stall = '0' then
refill_ctr <= refill_ctr + 1;
end if;
end if;
end process refill_word_counter;
store_delay_counter:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I = '1' then
store_delay_ctr <= 2;
elsif ps = REFILL_LAST_WORD then
if store_delay_ctr /= 0 then
store_delay_ctr <= store_delay_ctr - 1;
end if;
else
store_delay_ctr <= 2;
end if;
end if;
end process store_delay_counter;
tag_table_we <=
'1' when ps = REFILL and MEM_MISO_I.ack = '1' and refill_ctr="001" else
'1' when ps = HIT and CPU_MOSI_I.wr_be/="0000" else -- see @note2
'1' when update_tag = '1' else -- see @note1
'0';
-- Refill WB interface -----------------------------------------------------
MEM_MOSI_O.adr(31 downto LINE_ADDRESS_WIDTH+2) <= addr_reg(31 downto LINE_ADDRESS_WIDTH+2);
with ps select MEM_MOSI_O.adr(LINE_ADDRESS_WIDTH-1+2 downto 2) <=
refill_line_address when REFILL,
addr_reg(LINE_ADDRESS_WIDTH-1+2 downto 2) when others;
MEM_MOSI_O.adr(1 downto 0) <= (others => '0');
MEM_MOSI_O.dat <= data_wr_reg;
MEM_MOSI_O.stb <= '1' when (ps = REFILL or ps = WRITETHROUGH) else '0';
MEM_MOSI_O.cyc <= '1' when (ps = REFILL or ps = WRITETHROUGH) else '0';
MEM_MOSI_O.we <= '1' when ps = WRITETHROUGH else '0';
MEM_MOSI_O.tga <= "0000"; -- FIXME tag use unspecified yet
MEM_MOSI_O.sel <= wr_be_reg;
-- The cache control interface MOSI consists of this lone "present" signal.
CACHE_CTRL_MISO_O.present <= '1';
-- Back-to-back access support logic ---------------------------------------
-- This flag will be raised when a READ comes immediately aftr a write (in
-- the following clock cycle). Since the ION bus control signals are valid
-- for only one cycle we need to remember the request here.
-- The address is not going to change in the meantime.
read_pending_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
read_pending <= '0';
elsif ps=WRITETHROUGH and CPU_MOSI_I.rd_en='1' then
read_pending <= '1';
elsif ps/=WRITETHROUGH then
read_pending <= '0';
end if;
end if;
end process read_pending_register;
-- FIXME support RD-WR operations too.
end architecture rtl;
|
lgpl-3.0
|
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_glitch_filt.vhd
|
1
|
4193
|
--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana ([email protected])
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
-- Glitch filter consisting of a set of chained flip-flops followed by a
-- comparator. The comparator toggles to '1' when all FFs in the chain are
-- '1' and respectively to '0' when all the FFS in the chain are '0'.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana [email protected] File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity gc_glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input, synchronous to clk_i
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end entity gc_glitch_filt;
architecture behav of gc_glitch_filt is
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Glitch filtration logic
--============================================================================
glitch_filt(0) <= dat_i;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_len downto 1) <= (others => '0');
else
glitch_filt(g_len downto 1) <= glitch_filt(g_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
-- and set the data output based on the state of the glitch filter
p_output: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
dat_o <= '0';
elsif (unsigned(glitch_filt) = (glitch_filt'range => '1')) then
dat_o <= '1';
elsif (unsigned(glitch_filt) = (glitch_filt'range => '0')) then
dat_o <= '0';
end if;
end if;
end process p_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
|
lgpl-3.0
|
twlostow/dsi-shield
|
hdl/ip_cores/local/simple_uart_pkg.vhd
|
1
|
3987
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Simple Wishbone UART
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Thu Feb 14 10:36:11 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_uart_in_registers is record
sr_tx_busy_i : std_logic;
sr_rx_rdy_i : std_logic;
rdr_rx_data_i : std_logic_vector(7 downto 0);
host_tdr_rdy_i : std_logic;
host_rdr_data_i : std_logic_vector(7 downto 0);
host_rdr_rdy_i : std_logic;
host_rdr_count_i : std_logic_vector(15 downto 0);
end record;
constant c_uart_in_registers_init_value: t_uart_in_registers := (
sr_tx_busy_i => '0',
sr_rx_rdy_i => '0',
rdr_rx_data_i => (others => '0'),
host_tdr_rdy_i => '0',
host_rdr_data_i => (others => '0'),
host_rdr_rdy_i => '0',
host_rdr_count_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_uart_out_registers is record
bcr_o : std_logic_vector(31 downto 0);
bcr_wr_o : std_logic;
tdr_tx_data_o : std_logic_vector(7 downto 0);
tdr_tx_data_wr_o : std_logic;
host_tdr_data_o : std_logic_vector(7 downto 0);
host_tdr_data_wr_o : std_logic;
end record;
constant c_uart_out_registers_init_value: t_uart_out_registers := (
bcr_o => (others => '0'),
bcr_wr_o => '0',
tdr_tx_data_o => (others => '0'),
tdr_tx_data_wr_o => '0',
host_tdr_data_o => (others => '0'),
host_tdr_data_wr_o => '0'
);
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body uart_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers is
variable tmp: t_uart_in_registers;
begin
tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
return tmp;
end function;
end package body;
|
lgpl-3.0
|
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_sync_register.vhd
|
1
|
1324
|
library ieee;
use ieee.std_logic_1164.all;
entity gc_sync_register is
generic (
g_width : integer);
port (
clk_i : in std_logic;
rst_n_a_i : in std_logic;
d_i : in std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0));
end gc_sync_register;
architecture rtl of gc_sync_register is
signal gc_sync_register_in : std_logic_vector(g_width-1 downto 0);
signal sync0, sync1 : std_logic_vector(g_width-1 downto 0);
attribute shreg_extract : string;
attribute shreg_extract of gc_sync_register_in : signal is "no";
attribute shreg_extract of sync0 : signal is "no";
attribute shreg_extract of sync1 : signal is "no";
attribute keep : string;
attribute keep of gc_sync_register_in : signal is "true";
attribute keep of sync0 : signal is "true";
attribute keep of sync1 : signal is "true";
begin
process(clk_i, rst_n_a_i)
begin
if(rst_n_a_i = '0') then
sync1 <= (others => '0');
sync0 <= (others => '0');
elsif rising_edge(clk_i) then
sync0 <= gc_sync_register_in;
sync1 <= sync0;
end if;
end process;
gc_sync_register_in <= d_i;
q_o <= sync1;
end rtl;
|
lgpl-3.0
|
twlostow/dsi-shield
|
hdl/ip_cores/local/genram_pkg.vhd
|
1
|
9017
|
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2013-10-30
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
function f_zeros (size : integer) return std_logic_vector;
type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "none";
g_addr_conflict_resolution : string := "dont_care") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0):= f_gen_dummy_vec('1', (g_data_width+7)/8);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_simple_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width -1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
qb_o : out std_logic_vector(g_data_width -1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic := '0';
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
web_i : in std_logic := '0';
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_shiftreg_fifo
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
full_o : out std_logic;
almost_full_o : out std_logic;
q_valid_o : out std_logic
);
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector is
variable tmp : std_logic_vector(size-1 downto 0);
begin
for i in 0 to size-1 loop
tmp(i) := val;
end loop; -- i
return tmp;
end f_gen_dummy_vec;
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
end genram_pkg;
|
lgpl-3.0
|
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_i2c_slave.vhd
|
1
|
17824
|
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C slave core
--==============================================================================
--
-- author: Theodor Stana ([email protected])
--
-- date of creation: 2013-03-13
--
-- version: 1.0
--
-- description:
--
-- Simple I2C slave interface, providing the basic low-level functionality
-- of the I2C protocol.
--
-- The gc_i2c_slave module waits for a master to initiate a transfer via
-- a start condition. The address is sent next and if the address matches
-- the slave address set via the i2c_addr_i input, the addr_good_p_o output
-- is set. Based on the eighth bit of the first I2C transfer byte, the module
-- then starts shifting in or out each byte in the transfer, setting the
-- r/w_done_p_o output after each received/sent byte.
--
-- For master write (slave read) transfers, the received byte can be read at
-- the rx_byte_o output when the r_done_p_o pin is high. For master read (slave
-- write) transfers, the slave sends the byte at the tx_byte_i input, which
-- should be set when the w_done_p_o output is high, either after I2C address
-- reception, or a successful send of a previous byte.
--
-- dependencies:
-- OHWR general-cores library
--
-- references:
-- [1] The I2C bus specification, version 2.1, NXP Semiconductor, Jan. 2000
-- http://www.nxp.com/documents/other/39340011.pdf
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-13 Theodor Stana File created
-- 2013-11-22 Theodor Stana Changed to sampling SDA on SCL rising edge
--==============================================================================
-- TODO:
-- - Stop condition
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity gc_i2c_slave is
generic
(
-- Length of glitch filter
-- 0 - SCL and SDA lines are passed only through synchronizer
-- 1 - one clk_i glitches filtered
-- 2 - two clk_i glitches filtered
g_gf_len : natural := 0
);
port
(
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
ack_i : in std_logic;
-- Byte to send, should be loaded while done_p_o = '1'
tx_byte_i : in std_logic_vector(7 downto 0);
-- Received byte, valid after done_p_o = '1'
rx_byte_o : out std_logic_vector(7 downto 0);
-- Pulse outputs signaling various I2C actions
-- Start and stop conditions
i2c_sta_p_o : out std_logic;
i2c_sto_p_o : out std_logic;
-- Received address corresponds i2c_addr_i
addr_good_p_o : out std_logic;
-- Read and write done
r_done_p_o : out std_logic;
w_done_p_o : out std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o : out std_logic
);
end entity gc_i2c_slave;
architecture behav of gc_i2c_slave is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
(
IDLE, -- idle
ADDR, -- shift in I2C address bits
ADDR_ACK, -- ACK/NACK to I2C address
RD, -- shift in byte to read
RD_ACK, -- ACK/NACK to received byte
WR_LOAD_TXSR, -- load byte to send via I2C
WR, -- shift out byte
WR_ACK -- get ACK/NACK from master
);
--============================================================================
-- Signal declarations
--============================================================================
-- Deglitched signals and delays for SCL and SDA lines
signal scl_synced : std_logic;
signal scl_deglitched : std_logic;
signal scl_deglitched_d0 : std_logic;
signal sda_synced : std_logic;
signal sda_deglitched : std_logic;
signal sda_deglitched_d0 : std_logic;
signal scl_r_edge_p : std_logic;
signal scl_f_edge_p : std_logic;
signal sda_f_edge_p : std_logic;
signal sda_r_edge_p : std_logic;
-- FSM signals
signal state : t_state;
signal inhibit : std_logic;
-- RX and TX shift registers
signal txsr : std_logic_vector(7 downto 0);
signal rxsr : std_logic_vector(7 downto 0);
-- Bit counter on RX & TX
signal bit_cnt : unsigned(2 downto 0);
-- Start and stop condition pulse signals
signal sta_p, sto_p : std_logic;
-- Master ACKed after it has read a byte from the slave
signal mst_acked : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- I/O logic
--============================================================================
-- No clock stretching implemented, always disable SCL line
scl_o <= '0';
scl_en_o <= '0';
-- SDA line driven low; SDA_EN line controls when the tristate buffer is enabled
sda_o <= '0';
-- Assign RX byte output
rx_byte_o <= rxsr;
--============================================================================
-- Deglitching logic
--============================================================================
-- First, synchronize the SCL signal in the clk_i domain
cmp_sync_scl : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => scl_i,
synced_o => scl_synced
);
-- Generate deglitched SCL signal
cmp_scl_deglitch : gc_glitch_filt
generic map
(
g_len => g_gf_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => scl_synced,
dat_o => scl_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling-edge detection signal
p_scl_degl_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
scl_deglitched_d0 <= '0';
scl_f_edge_p <= '0';
scl_r_edge_p <= '0';
else
scl_deglitched_d0 <= scl_deglitched;
scl_f_edge_p <= (not scl_deglitched) and scl_deglitched_d0;
scl_r_edge_p <= scl_deglitched and (not scl_deglitched_d0);
end if;
end if;
end process p_scl_degl_d0;
-- Synchronize SDA signal in clk_i domain
cmp_sda_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => sda_i,
synced_o => sda_synced
);
-- Generate deglitched SDA signal
cmp_sda_deglitch : gc_glitch_filt
generic map
(
g_len => g_gf_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => sda_synced,
dat_o => sda_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling- and rising-edge detection signals
p_sda_deglitched_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
sda_deglitched_d0 <= '0';
sda_f_edge_p <= '0';
sda_r_edge_p <= '0';
else
sda_deglitched_d0 <= sda_deglitched;
sda_f_edge_p <= (not sda_deglitched) and sda_deglitched_d0;
sda_r_edge_p <= sda_deglitched and (not sda_deglitched_d0);
end if;
end if;
end process p_sda_deglitched_d0;
--============================================================================
-- Start and stop condition outputs
--============================================================================
-- First the process to set the start and stop conditions as per I2C standard
p_sta_sto : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
sta_p <= '0';
sto_p <= '0';
else
sta_p <= sda_f_edge_p and scl_deglitched;
sto_p <= sda_r_edge_p and scl_deglitched;
end if;
end if;
end process p_sta_sto;
-- Finally, set the outputs
i2c_sta_p_o <= sta_p;
i2c_sto_p_o <= sto_p;
--============================================================================
-- FSM logic
--============================================================================
p_fsm: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
inhibit <= '0';
bit_cnt <= (others => '0');
rxsr <= (others => '0');
txsr <= (others => '0');
mst_acked <= '0';
sda_en_o <= '0';
r_done_p_o <= '0';
w_done_p_o <= '0';
addr_good_p_o <= '0';
op_o <= '0';
-- start and stop conditions are followed by I2C address, so any byte
-- following would be an address byte; therefore, it is safe to deinhibit
-- the FSM
elsif (sta_p = '1') or (sto_p = '1') then
state <= IDLE;
inhibit <= '0';
-- state machine logic
else
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
when IDLE =>
-- clear outputs and bit counter
bit_cnt <= (others => '0');
sda_en_o <= '0';
mst_acked <= '0';
r_done_p_o <= '0';
w_done_p_o <= '0';
addr_good_p_o <= '0';
if (scl_f_edge_p = '1') and (inhibit = '0') then
state <= ADDR;
end if;
---------------------------------------------------------------------
-- ADDR
---------------------------------------------------------------------
when ADDR =>
-- Shifting in is done on rising edge of SCL
if (scl_r_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
end if;
--
-- Checking the bit counter is done on the falling edge of SCL
--
-- If 8 bits have been shifted in, the received address is checked
-- and the slave goes in the ADDR_ACK state.
--
-- If the address is not ours, go back to IDLE and set inhibit bits
-- so bytes sent to or received from another slave that happen to
-- coincide to the address of this slave don't get interpreted
-- as accesses to this slave.
--
if (scl_f_edge_p = '1') then
if (bit_cnt = 0) then
if (rxsr(7 downto 1) = i2c_addr_i) then
op_o <= rxsr(0);
addr_good_p_o <= '1';
state <= ADDR_ACK;
else
inhibit <= '1';
state <= IDLE;
end if;
end if;
end if;
---------------------------------------------------------------------
-- ADDR_ACK
---------------------------------------------------------------------
when ADDR_ACK =>
-- clear addr_good pulse
addr_good_p_o <= '0';
-- send ACK from input, check the ACK on falling edge and go to
-- loading of the TXSR if the OP bit is a write, or read otherwise
sda_en_o <= ack_i;
if (scl_f_edge_p = '1') then
if (ack_i = '1') then
if (rxsr(0) = '0') then
state <= RD;
else
state <= WR_LOAD_TXSR;
end if;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- RD
---------------------------------------------------------------------
-- Shift in bits sent by the master
---------------------------------------------------------------------
when RD =>
-- not controlling SDA, clear enable signal
sda_en_o <= '0';
-- shift in on rising-edge
if (scl_r_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
end if;
if (scl_f_edge_p = '1') then
-- Received 8 bits, go to RD_ACK and signal external module
if (bit_cnt = 0) then
state <= RD_ACK;
r_done_p_o <= '1';
end if;
end if;
---------------------------------------------------------------------
-- RD_ACK
---------------------------------------------------------------------
when RD_ACK =>
-- Clear done pulse
r_done_p_o <= '0';
-- we write the ACK bit, so control sda_en_o signal to send ACK/NACK
sda_en_o <= ack_i;
-- based on the ACK received by external command, we read the next
-- bit (ACK) or go back to idle state (NACK)
if (scl_f_edge_p = '1') then
if (ack_i = '1') then
state <= RD;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- WR_LOAD_TXSR
---------------------------------------------------------------------
when WR_LOAD_TXSR =>
txsr <= tx_byte_i;
state <= WR;
---------------------------------------------------------------------
-- WR
---------------------------------------------------------------------
when WR =>
-- slave writes, SDA output enable is the negated value of the bit
-- to send (since on I2C, '1' is a release of the bus)
sda_en_o <= not txsr(7);
-- increment bit counter on rising edge
if (scl_r_edge_p = '1') then
bit_cnt <= bit_cnt + 1;
end if;
-- Shift TXSR on falling edge of SCL
if (scl_f_edge_p = '1') then
txsr <= txsr(6 downto 0) & '0';
-- Eight bits sent, disable SDA and go to WR_ACK
if (bit_cnt = 0) then
state <= WR_ACK;
w_done_p_o <= '1';
end if;
end if;
---------------------------------------------------------------------
-- WR_ACK
---------------------------------------------------------------------
when WR_ACK =>
-- master controls SDA, clear sda_en_o
sda_en_o <= '0';
-- clear done pulse
w_done_p_o <= '0';
-- sample in ACK from master on rising edge
if (scl_r_edge_p = '1') then
if (sda_deglitched = '0') then
mst_acked <= '1';
else
mst_acked <= '0';
end if;
end if;
-- and check it on falling edge
if (scl_f_edge_p = '1') then
if (mst_acked = '1') then
state <= WR_LOAD_TXSR;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- Any other state: go back to IDLE
---------------------------------------------------------------------
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
|
lgpl-3.0
|
twlostow/dsi-shield
|
hdl/ip_cores/local/generic_spram.vhd
|
1
|
5219
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
entity generic_spram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 1024;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := false;
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "write_first";
g_init_file : string := ""
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- byte write enable, actiwe when g_
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
-- global write enable (masked by bwe_i if g_with_byte_enable = true)
we_i : in std_logic;
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data input
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_spram;
architecture syn of generic_spram is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
type t_string_file_type is file of string;
impure function f_bitstring_2_slv(s : string; num_bits : integer) return std_logic_vector is
begin
end function f_bitstring_2_slv;
impure function f_load_from_file(file_name : string) return t_ram_type is
file f : t_string_file_type;
variable fstatus : file_open_status;
begin
file_open(fstatus, f, file_name, read_mode);
if(fstatus /= open_ok) then
report "generic_spram: Cannot open memory initialization file: " & file_name severity failure;
end if;
end function f_load_from_file;
signal ram : t_ram_type;
signal s_we : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in : std_logic_vector(g_data_width-1 downto 0);
signal s_ram_out : std_logic_vector(g_data_width-1 downto 0);
begin
assert (g_init_file = "" or g_init_file = "none")
report "generic_spram: Memory initialization files not supported yet. Sorry :("
severity failure;
gen_with_byte_enable_writefirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "write_first") generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
begin
for i in 0 to c_num_bytes-1 loop
if s_we(i) = '1' then
s_ram_in(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
s_ram_out(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
else
s_ram_in(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
s_ram_out(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
end if;
end loop; -- i
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
ram(conv_integer(unsigned(a_i))) <= s_ram_in;
q_o <= s_ram_out;
end if;
end process;
end generate gen_with_byte_enable_writefirst;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
begin
for i in 0 to c_num_bytes-1 loop
if (s_we(i) = '1') then
s_ram_in(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
else
s_ram_in(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
ram(conv_integer(unsigned(a_i))) <= s_ram_in;
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(we_i = '1') then
ram(conv_integer(unsigned(a_i))) <= d_i;
q_o <= d_i;
else
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(we_i = '1') then
ram(conv_integer(unsigned(a_i))) <= d_i;
end if;
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end process;
end generate gen_without_byte_enable_readfirst;
end syn;
|
lgpl-3.0
|
trondd/mkjpeg
|
design/huffman/DC_CR_ROM.vhd
|
2
|
4872
|
-------------------------------------------------------------------------------
-- File Name : DC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : DC_CR_ROM
--
-- Content : DC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090329: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DC_CR_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
VLI_size : in std_logic_vector(3 downto 0);
VLC_DC_size : out std_logic_vector(3 downto 0);
VLC_DC : out unsigned(10 downto 0)
);
end entity DC_CR_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DC_CR_ROM is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- DC-ROM
-------------------------------------------------------------------
p_DC_CR_ROM : process(CLK, RST)
begin
if RST = '1' then
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
elsif CLK'event and CLK = '1' then
case VLI_size is
when X"0" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("00", VLC_DC'length);
when X"1" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("01", VLC_DC'length);
when X"2" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("10", VLC_DC'length);
when X"3" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("110", VLC_DC'length);
when X"4" =>
VLC_DC_size <= X"4";
VLC_DC <= resize("1110", VLC_DC'length);
when X"5" =>
VLC_DC_size <= X"5";
VLC_DC <= resize("11110", VLC_DC'length);
when X"6" =>
VLC_DC_size <= X"6";
VLC_DC <= resize("111110", VLC_DC'length);
when X"7" =>
VLC_DC_size <= X"7";
VLC_DC <= resize("1111110", VLC_DC'length);
when X"8" =>
VLC_DC_size <= X"8";
VLC_DC <= resize("11111110", VLC_DC'length);
when X"9" =>
VLC_DC_size <= X"9";
VLC_DC <= resize("111111110", VLC_DC'length);
when X"A" =>
VLC_DC_size <= X"A";
VLC_DC <= resize("1111111110", VLC_DC'length);
when X"B" =>
VLC_DC_size <= X"B";
VLC_DC <= resize("11111111110", VLC_DC'length);
when others =>
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
lgpl-3.0
|
trondd/mkjpeg
|
design/JFIFGen/HeaderRAM.vhd
|
2
|
1490
|
LIBRARY ieee, std;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
ENTITY HeaderRam IS
GENERIC
(
ADDRESS_WIDTH : integer := 10;
DATA_WIDTH : integer := 8
);
PORT
(
clk : IN std_logic;
d : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
waddr : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
raddr : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
we : IN std_logic;
q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
);
END HeaderRam;
ARCHITECTURE rtl OF HeaderRam IS
TYPE RamType IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
impure function InitRamFromFile(RamFileName : in string) return RamType is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for l in RamType'range loop
readline(RamFile, RamFileLine);
hread(RamFileLine, RAM(l));
end loop;
return RAM;
end function;
--SIGNAL ram_block : RamType := InitRamFromFile("../design/jfifgen/header.hex");
SIGNAL ram_block : RamType;
attribute ram_init_file : string;
attribute ram_init_file of ram_block :
signal is "./src/jpg/JFIFGen/header.mif";
BEGIN
PROCESS (clk)
BEGIN
IF (clk'event AND clk = '1') THEN
IF (we = '1') THEN
ram_block(to_integer(unsigned(waddr))) <= d;
END IF;
q <= ram_block(to_integer(unsigned(raddr)));
END IF;
END PROCESS;
END rtl;
|
lgpl-3.0
|
trondd/mkjpeg
|
tb/vhdl/ClkGen.vhd
|
2
|
2500
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ClkGen is
port (
CLK : out std_logic;
RST : out std_logic
);
end entity ClkGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture ClkGen_rtl of ClkGen is
constant CLOCK_PERIOD : time := 10 ns;
signal clk_s : std_logic := '0';
signal rst_s : std_logic := '0';
begin
-- Clock generator (50% duty cycle)
clk_gen: process
begin
clk_s <= '0';
wait for CLOCK_PERIOD/2;
clk_s <= '1';
wait for CLOCK_PERIOD/2;
end process clk_gen;
CLK <= clk_s;
reset_gen: process
begin
wait until rising_edge(clk_s);
rst_s <= '0';
wait until rising_edge(clk_s);
rst_s <= '1';
wait until rising_edge(clk_s);
rst_s <= '0';
wait;
end process reset_gen;
RST <= rst_s;
end architecture ClkGen_rtl;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_spartan3/syn/vhdl/nfa_accept_samples_generic_hw.vhd
|
1
|
85839
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc3s200avq100-5,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.449000,HLS_SYN_LAT=117874014,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (5 downto 0) := "100100";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (5 downto 0) := "100101";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (5 downto 0) := "100110";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (5 downto 0) := "100111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal stop_on_first_read_read_fu_102_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_fu_228_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_313 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_fu_238_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_reg_323 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_327 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal offset_reg_333 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_return : STD_LOGIC_VECTOR (0 downto 0);
signal r_reg_338 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_done : STD_LOGIC;
signal or_cond_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_343 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_249_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_reg_347 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_start : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_ap_idle : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_ap_ready : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_empty : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_length_r : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_reg_144 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_154 : STD_LOGIC_VECTOR (15 downto 0);
signal p_0_reg_164 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_sample_iterator_next_fu_209_ap_start_ap_start_reg : STD_LOGIC := '0';
signal c_fu_92 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_ce : STD_LOGIC;
component nfa_accept_sample IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
empty : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_nfa_accept_sample_fu_176 : component nfa_accept_sample
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_accept_sample_fu_176_ap_start,
ap_done => grp_nfa_accept_sample_fu_176_ap_done,
ap_idle => grp_nfa_accept_sample_fu_176_ap_idle,
ap_ready => grp_nfa_accept_sample_fu_176_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size,
nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size,
nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address,
nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout,
nfa_forward_buckets_size => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size,
nfa_symbols => grp_nfa_accept_sample_fu_176_nfa_symbols,
sample_req_din => grp_nfa_accept_sample_fu_176_sample_req_din,
sample_req_full_n => grp_nfa_accept_sample_fu_176_sample_req_full_n,
sample_req_write => grp_nfa_accept_sample_fu_176_sample_req_write,
sample_rsp_empty_n => grp_nfa_accept_sample_fu_176_sample_rsp_empty_n,
sample_rsp_read => grp_nfa_accept_sample_fu_176_sample_rsp_read,
sample_address => grp_nfa_accept_sample_fu_176_sample_address,
sample_datain => grp_nfa_accept_sample_fu_176_sample_datain,
sample_dataout => grp_nfa_accept_sample_fu_176_sample_dataout,
sample_size => grp_nfa_accept_sample_fu_176_sample_size,
empty => grp_nfa_accept_sample_fu_176_empty,
length_r => grp_nfa_accept_sample_fu_176_length_r,
ap_return => grp_nfa_accept_sample_fu_176_ap_return);
grp_sample_iterator_get_offset_fu_192 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_192_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_192_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_192_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_192_ap_ready,
indices_stride_req_din => grp_sample_iterator_get_offset_fu_192_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_get_offset_fu_192_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_get_offset_fu_192_indices_stride_address,
indices_stride_datain => grp_sample_iterator_get_offset_fu_192_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_get_offset_fu_192_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_get_offset_fu_192_indices_stride_size,
indices_begin_req_din => grp_sample_iterator_get_offset_fu_192_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_get_offset_fu_192_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_get_offset_fu_192_indices_begin_address,
indices_begin_datain => grp_sample_iterator_get_offset_fu_192_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_get_offset_fu_192_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_get_offset_fu_192_indices_begin_size,
ap_ce => grp_sample_iterator_get_offset_fu_192_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_192_i_index,
i_sample => grp_sample_iterator_get_offset_fu_192_i_sample,
indices_samples_req_din => grp_sample_iterator_get_offset_fu_192_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_get_offset_fu_192_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_get_offset_fu_192_indices_samples_address,
indices_samples_datain => grp_sample_iterator_get_offset_fu_192_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_get_offset_fu_192_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_get_offset_fu_192_indices_samples_size,
sample_buffer_size => grp_sample_iterator_get_offset_fu_192_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_192_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_192_ap_return);
grp_sample_iterator_next_fu_209 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_209_ap_start,
ap_done => grp_sample_iterator_next_fu_209_ap_done,
ap_idle => grp_sample_iterator_next_fu_209_ap_idle,
ap_ready => grp_sample_iterator_next_fu_209_ap_ready,
indices_samples_req_din => grp_sample_iterator_next_fu_209_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_next_fu_209_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_next_fu_209_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_next_fu_209_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_next_fu_209_indices_samples_address,
indices_samples_datain => grp_sample_iterator_next_fu_209_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_next_fu_209_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_next_fu_209_indices_samples_size,
ap_ce => grp_sample_iterator_next_fu_209_ap_ce,
indices_begin_req_din => grp_sample_iterator_next_fu_209_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_next_fu_209_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_next_fu_209_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_next_fu_209_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_next_fu_209_indices_begin_address,
indices_begin_datain => grp_sample_iterator_next_fu_209_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_next_fu_209_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_next_fu_209_indices_begin_size,
indices_stride_req_din => grp_sample_iterator_next_fu_209_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_next_fu_209_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_next_fu_209_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_next_fu_209_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_next_fu_209_indices_stride_address,
indices_stride_datain => grp_sample_iterator_next_fu_209_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_next_fu_209_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_next_fu_209_indices_stride_size,
i_index => grp_sample_iterator_next_fu_209_i_index,
i_sample => grp_sample_iterator_next_fu_209_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_209_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_209_ap_return_1);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 38,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_249_p0,
din1 => grp_fu_249_p1,
ce => grp_fu_249_ce,
dout => grp_fu_249_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg assign process. --
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((ap_ST_st22_fsm_21 = ap_CS_fsm)) then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_176_ap_ready)) then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_238_p2 = ap_const_lv1_0))) then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_192_ap_ready)) then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_209_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st32_fsm_31 = ap_NS_fsm) and ((ap_ST_st24_fsm_23 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm)))) then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_209_ap_ready)) then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_fu_92 assign process. --
c_fu_92_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st32_fsm_31 = ap_CS_fsm) and (or_cond_reg_343 = ap_const_lv1_0))) then
c_fu_92 <= c_1_reg_347;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_92 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_index_reg_144 assign process. --
i_index_reg_144_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st39_fsm_38 = ap_CS_fsm)) then
i_index_reg_144 <= grp_sample_iterator_next_fu_209_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_144 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_154 assign process. --
i_sample_reg_154_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st39_fsm_38 = ap_CS_fsm)) then
i_sample_reg_154 <= grp_sample_iterator_next_fu_209_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_154 <= begin_sample;
end if;
end if;
end process;
-- p_0_reg_164 assign process. --
p_0_reg_164_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st24_fsm_23 = ap_CS_fsm) and not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
p_0_reg_164 <= ap_const_lv32_1;
elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_323 = ap_const_lv1_0)))) then
p_0_reg_164 <= c_fu_92;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st31_fsm_30 = ap_CS_fsm)) then
c_1_reg_347 <= grp_fu_249_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
c_load_reg_327 <= c_fu_92;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st22_fsm_21 = ap_CS_fsm)) then
offset_reg_333 <= grp_sample_iterator_get_offset_fu_192_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st24_fsm_23 = ap_CS_fsm)) then
or_cond_reg_343 <= or_cond_fu_245_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st23_fsm_22 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)))) then
r_reg_338 <= grp_nfa_accept_sample_fu_176_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
tmp_i_10_reg_318 <= tmp_i_10_fu_233_p2;
tmp_i_reg_313 <= tmp_i_fu_228_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
tmp_i_11_reg_323 <= tmp_i_11_fu_238_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_102_p2 , tmp_i_11_reg_323 , grp_nfa_accept_sample_fu_176_ap_done , or_cond_fu_245_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((tmp_i_11_reg_323 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
if (not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st23_fsm_22;
end if;
when ap_ST_st24_fsm_23 =>
if ((not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
elsif (((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st25_fsm_24;
else
ap_NS_fsm <= ap_ST_st32_fsm_31;
end if;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st40_fsm_39 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_164;
grp_fu_249_ce <= ap_const_logic_1;
grp_fu_249_p0 <= c_load_reg_327;
grp_fu_249_p1 <= ap_const_lv32_1;
grp_nfa_accept_sample_fu_176_ap_start <= grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg;
grp_nfa_accept_sample_fu_176_empty <= offset_reg_333;
grp_nfa_accept_sample_fu_176_length_r <= sample_length;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain <= nfa_forward_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_symbols <= nfa_symbols;
grp_nfa_accept_sample_fu_176_sample_datain <= sample_buffer_datain;
grp_nfa_accept_sample_fu_176_sample_req_full_n <= sample_buffer_req_full_n;
grp_nfa_accept_sample_fu_176_sample_rsp_empty_n <= sample_buffer_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_192_ap_start <= grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_192_i_index <= i_index_reg_144;
grp_sample_iterator_get_offset_fu_192_i_sample <= i_sample_reg_154;
grp_sample_iterator_get_offset_fu_192_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_192_sample_length <= sample_length;
grp_sample_iterator_next_fu_209_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_209_ap_start <= grp_sample_iterator_next_fu_209_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_209_i_index <= i_index_reg_144;
grp_sample_iterator_next_fu_209_i_sample <= i_sample_reg_154;
grp_sample_iterator_next_fu_209_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_next_fu_209_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_next_fu_209_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_next_fu_209_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_next_fu_209_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_next_fu_209_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
-- indices_begin_address assign process. --
indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_address, grp_sample_iterator_next_fu_209_indices_begin_address)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_next_fu_209_indices_begin_address;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_get_offset_fu_192_indices_begin_address;
else
indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_dataout assign process. --
indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_dataout, grp_sample_iterator_next_fu_209_indices_begin_dataout)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_next_fu_209_indices_begin_dataout;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_get_offset_fu_192_indices_begin_dataout;
else
indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_req_din assign process. --
indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_req_din, grp_sample_iterator_next_fu_209_indices_begin_req_din)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_next_fu_209_indices_begin_req_din;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_din;
else
indices_begin_req_din <= 'X';
end if;
end process;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_req_write, grp_sample_iterator_next_fu_209_indices_begin_req_write)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_next_fu_209_indices_begin_req_write;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_write;
else
indices_begin_req_write <= 'X';
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read, grp_sample_iterator_next_fu_209_indices_begin_rsp_read)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_next_fu_209_indices_begin_rsp_read;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read;
else
indices_begin_rsp_read <= 'X';
end if;
end process;
-- indices_begin_size assign process. --
indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_size, grp_sample_iterator_next_fu_209_indices_begin_size)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_next_fu_209_indices_begin_size;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_get_offset_fu_192_indices_begin_size;
else
indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_address assign process. --
indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_address, grp_sample_iterator_next_fu_209_indices_samples_address)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_next_fu_209_indices_samples_address;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_get_offset_fu_192_indices_samples_address;
else
indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_dataout assign process. --
indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_dataout, grp_sample_iterator_next_fu_209_indices_samples_dataout)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_next_fu_209_indices_samples_dataout;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_get_offset_fu_192_indices_samples_dataout;
else
indices_samples_dataout <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_req_din assign process. --
indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_req_din, grp_sample_iterator_next_fu_209_indices_samples_req_din)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_next_fu_209_indices_samples_req_din;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_din;
else
indices_samples_req_din <= 'X';
end if;
end process;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_req_write, grp_sample_iterator_next_fu_209_indices_samples_req_write)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_next_fu_209_indices_samples_req_write;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_write;
else
indices_samples_req_write <= 'X';
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read, grp_sample_iterator_next_fu_209_indices_samples_rsp_read)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_next_fu_209_indices_samples_rsp_read;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read;
else
indices_samples_rsp_read <= 'X';
end if;
end process;
-- indices_samples_size assign process. --
indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_size, grp_sample_iterator_next_fu_209_indices_samples_size)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_next_fu_209_indices_samples_size;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_get_offset_fu_192_indices_samples_size;
else
indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_address assign process. --
indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_address, grp_sample_iterator_next_fu_209_indices_stride_address)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_next_fu_209_indices_stride_address;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_get_offset_fu_192_indices_stride_address;
else
indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_dataout assign process. --
indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_dataout, grp_sample_iterator_next_fu_209_indices_stride_dataout)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_next_fu_209_indices_stride_dataout;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_get_offset_fu_192_indices_stride_dataout;
else
indices_stride_dataout <= "XXXXXXXX";
end if;
end process;
-- indices_stride_req_din assign process. --
indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_req_din, grp_sample_iterator_next_fu_209_indices_stride_req_din)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_next_fu_209_indices_stride_req_din;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_din;
else
indices_stride_req_din <= 'X';
end if;
end process;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_req_write, grp_sample_iterator_next_fu_209_indices_stride_req_write)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_next_fu_209_indices_stride_req_write;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_write;
else
indices_stride_req_write <= 'X';
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read, grp_sample_iterator_next_fu_209_indices_stride_rsp_read)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_next_fu_209_indices_stride_rsp_read;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read;
else
indices_stride_rsp_read <= 'X';
end if;
end process;
-- indices_stride_size assign process. --
indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_size, grp_sample_iterator_next_fu_209_indices_stride_size)
begin
if (((ap_ST_st39_fsm_38 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm) or (ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st35_fsm_34 = ap_CS_fsm) or (ap_ST_st36_fsm_35 = ap_CS_fsm) or (ap_ST_st37_fsm_36 = ap_CS_fsm) or (ap_ST_st38_fsm_37 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_next_fu_209_indices_stride_size;
elsif (((ap_ST_st22_fsm_21 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm) or (ap_ST_st17_fsm_16 = ap_CS_fsm) or (ap_ST_st18_fsm_17 = ap_CS_fsm) or (ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st20_fsm_19 = ap_CS_fsm) or (ap_ST_st21_fsm_20 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_get_offset_fu_192_indices_stride_size;
else
indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size;
nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address;
nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout;
nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din;
nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write;
nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read;
nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size;
nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size;
or_cond_fu_245_p2 <= (r_reg_338 xor accept);
sample_buffer_address <= grp_nfa_accept_sample_fu_176_sample_address;
sample_buffer_dataout <= grp_nfa_accept_sample_fu_176_sample_dataout;
sample_buffer_req_din <= grp_nfa_accept_sample_fu_176_sample_req_din;
sample_buffer_req_write <= grp_nfa_accept_sample_fu_176_sample_req_write;
sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_176_sample_rsp_read;
sample_buffer_size <= grp_nfa_accept_sample_fu_176_sample_size;
stop_on_first_read_read_fu_102_p2 <= stop_on_first;
tmp_i_10_fu_233_p2 <= "1" when (i_index_reg_144 = end_index) else "0";
tmp_i_11_fu_238_p2 <= (tmp_i_reg_313 and tmp_i_10_reg_318);
tmp_i_fu_228_p2 <= "1" when (i_sample_reg_154 = end_sample) else "0";
end behav;
|
lgpl-3.0
|
jairov4/accel-oil
|
solution_kintex7/sim/vhdl/nfa_accept_samples_generic_hw.autotb.vhd
|
1
|
99901
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity apatb_nfa_accept_samples_generic_hw_top is
generic (
AUTOTB_CLOCK_PERIOD : TIME := 2.000000 ns;
AUTOTB_TVIN_nfa_initials_buckets : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_initials_buckets.dat";
AUTOTB_TVIN_nfa_finals_buckets : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_finals_buckets.dat";
AUTOTB_TVIN_nfa_forward_buckets : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_forward_buckets.dat";
AUTOTB_TVIN_nfa_symbols : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_nfa_symbols.dat";
AUTOTB_TVIN_sample_buffer : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_sample_buffer.dat";
AUTOTB_TVIN_sample_buffer_length : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_sample_buffer_length.dat";
AUTOTB_TVIN_sample_length : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_sample_length.dat";
AUTOTB_TVIN_indices_begin : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_begin.dat";
AUTOTB_TVIN_indices_samples : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_samples.dat";
AUTOTB_TVIN_indices_stride : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_stride.dat";
AUTOTB_TVIN_begin_index : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_begin_index.dat";
AUTOTB_TVIN_begin_sample : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_begin_sample.dat";
AUTOTB_TVIN_end_index : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_end_index.dat";
AUTOTB_TVIN_end_sample : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_end_sample.dat";
AUTOTB_TVIN_stop_on_first : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_stop_on_first.dat";
AUTOTB_TVIN_accept : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_accept.dat";
AUTOTB_TVIN_nfa_initials_buckets_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_nfa_initials_buckets.dat";
AUTOTB_TVIN_nfa_finals_buckets_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_nfa_finals_buckets.dat";
AUTOTB_TVIN_nfa_forward_buckets_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_nfa_forward_buckets.dat";
AUTOTB_TVIN_nfa_symbols_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_nfa_symbols.dat";
AUTOTB_TVIN_sample_buffer_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_sample_buffer.dat";
AUTOTB_TVIN_sample_buffer_length_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_sample_buffer_length.dat";
AUTOTB_TVIN_sample_length_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_sample_length.dat";
AUTOTB_TVIN_indices_begin_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_indices_begin.dat";
AUTOTB_TVIN_indices_samples_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_indices_samples.dat";
AUTOTB_TVIN_indices_stride_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_indices_stride.dat";
AUTOTB_TVIN_begin_index_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_begin_index.dat";
AUTOTB_TVIN_begin_sample_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_begin_sample.dat";
AUTOTB_TVIN_end_index_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_end_index.dat";
AUTOTB_TVIN_end_sample_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_end_sample.dat";
AUTOTB_TVIN_stop_on_first_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_stop_on_first.dat";
AUTOTB_TVIN_accept_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvin_accept.dat";
AUTOTB_TVOUT_ap_return : STRING := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvout_ap_return.dat";
AUTOTB_TVOUT_ap_return_out_wrapc : STRING := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_ap_return.dat";
AUTOTB_LAT_RESULT_FILE : STRING := "nfa_accept_samples_generic_hw.result.lat.rb";
AUTOTB_PER_RESULT_TRANS_FILE : STRING := "nfa_accept_samples_generic_hw.performance.result.transaction.xml";
LENGTH_nfa_initials_buckets : INTEGER := 2;
LENGTH_nfa_finals_buckets : INTEGER := 2;
LENGTH_nfa_forward_buckets : INTEGER := 10;
LENGTH_nfa_symbols : INTEGER := 1;
LENGTH_sample_buffer : INTEGER := 10;
LENGTH_sample_buffer_length : INTEGER := 1;
LENGTH_sample_length : INTEGER := 1;
LENGTH_indices_begin : INTEGER := 10;
LENGTH_indices_samples : INTEGER := 10;
LENGTH_indices_stride : INTEGER := 10;
LENGTH_begin_index : INTEGER := 1;
LENGTH_begin_sample : INTEGER := 1;
LENGTH_end_index : INTEGER := 1;
LENGTH_end_sample : INTEGER := 1;
LENGTH_stop_on_first : INTEGER := 1;
LENGTH_accept : INTEGER := 1;
LENGTH_ap_return : INTEGER := 1;
AUTOTB_TRANSACTION_NUM : INTEGER := 4
);
end apatb_nfa_accept_samples_generic_hw_top;
architecture behav of apatb_nfa_accept_samples_generic_hw_top is
signal AESL_clock : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal start : STD_LOGIC := '0';
signal ce : STD_LOGIC;
signal continue : STD_LOGIC := '0';
signal AESL_reset : STD_LOGIC := '0';
signal AESL_start : STD_LOGIC := '0';
signal AESL_ce : STD_LOGIC := '0';
signal AESL_continue : STD_LOGIC := '0';
signal AESL_ready : STD_LOGIC := '0';
signal AESL_idle : STD_LOGIC := '0';
signal AESL_done : STD_LOGIC := '0';
signal AESL_done_delay : STD_LOGIC := '0';
signal AESL_done_delay2 : STD_LOGIC := '0';
signal AESL_ready_delay : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
signal ready_wire : STD_LOGIC := '0';
signal ap_clk : STD_LOGIC;
signal ap_rst : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_ready : STD_LOGIC;
signal nfa_initials_buckets_req_din : STD_LOGIC;
signal nfa_initials_buckets_req_full_n : STD_LOGIC;
signal nfa_initials_buckets_req_write : STD_LOGIC;
signal nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal nfa_initials_buckets_rsp_read : STD_LOGIC;
signal nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_finals_buckets_req_din : STD_LOGIC;
signal nfa_finals_buckets_req_full_n : STD_LOGIC;
signal nfa_finals_buckets_req_write : STD_LOGIC;
signal nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal nfa_finals_buckets_rsp_read : STD_LOGIC;
signal nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_forward_buckets_req_din : STD_LOGIC;
signal nfa_forward_buckets_req_full_n : STD_LOGIC;
signal nfa_forward_buckets_req_write : STD_LOGIC;
signal nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal nfa_forward_buckets_rsp_read : STD_LOGIC;
signal nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal nfa_symbols : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal sample_buffer_req_din : STD_LOGIC;
signal sample_buffer_req_full_n : STD_LOGIC;
signal sample_buffer_req_write : STD_LOGIC;
signal sample_buffer_rsp_empty_n : STD_LOGIC;
signal sample_buffer_rsp_read : STD_LOGIC;
signal sample_buffer_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal sample_buffer_datain : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal sample_buffer_dataout : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal sample_buffer_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal sample_buffer_length : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal sample_length : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal indices_begin_req_din : STD_LOGIC;
signal indices_begin_req_full_n : STD_LOGIC;
signal indices_begin_req_write : STD_LOGIC;
signal indices_begin_rsp_empty_n : STD_LOGIC;
signal indices_begin_rsp_read : STD_LOGIC;
signal indices_begin_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_begin_datain : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_begin_dataout : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_begin_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_samples_req_din : STD_LOGIC;
signal indices_samples_req_full_n : STD_LOGIC;
signal indices_samples_req_write : STD_LOGIC;
signal indices_samples_rsp_empty_n : STD_LOGIC;
signal indices_samples_rsp_read : STD_LOGIC;
signal indices_samples_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_samples_datain : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal indices_samples_dataout : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal indices_samples_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_stride_req_din : STD_LOGIC;
signal indices_stride_req_full_n : STD_LOGIC;
signal indices_stride_req_write : STD_LOGIC;
signal indices_stride_rsp_empty_n : STD_LOGIC;
signal indices_stride_rsp_read : STD_LOGIC;
signal indices_stride_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal indices_stride_datain : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal indices_stride_dataout : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal indices_stride_size : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal i_size : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal begin_index : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal begin_sample : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal end_index : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal end_sample : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal stop_on_first : STD_LOGIC_VECTOR (0 DOWNTO 0);
signal accept : STD_LOGIC_VECTOR (0 DOWNTO 0);
signal ap_return : STD_LOGIC_VECTOR (31 DOWNTO 0);
shared variable AESL_ready_cnt : INTEGER := 0;
shared variable ready_cnt : INTEGER := 0;
shared variable done_cnt : INTEGER := 0;
signal ready_initial : STD_LOGIC;
signal ready_initial_n : STD_LOGIC;
signal ready_last_n : STD_LOGIC;
signal ready_delay_last_n : STD_LOGIC;
signal done_delay_last_n : STD_LOGIC;
signal interface_done : STD_LOGIC := '0';
-- Subtype for random state number, to prevent confusing it with true integers
-- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines
subtype T_RANDINT is integer range 1 to integer'high;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
shared variable AESL_mLatCnterIn : latency_record;
shared variable AESL_mLatCnterOut : latency_record;
shared variable AESL_mLatCnterIn_addr : INTEGER;
shared variable AESL_mLatCnterOut_addr : INTEGER;
shared variable AESL_clk_counter : INTEGER;
component nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
sample_length : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
i_size : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
begin_index : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
begin_sample : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
end_index : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
end_sample : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
accept : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
ap_return : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component;
signal bus_nfa_initials_buckets_req_RW : STD_LOGIC;
signal bus_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal reg_bus_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal bus_nfa_initials_buckets_req_RW_en : STD_LOGIC;
signal bus_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal reg_bus_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal bus_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal bus_nfa_initials_buckets_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_initials_buckets_din : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_initials_buckets_dout : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_initials_buckets_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_initials_buckets_ready : STD_LOGIC;
signal bus_nfa_initials_buckets_done : STD_LOGIC;
component AESL_autobus_nfa_initials_buckets is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal bus_nfa_finals_buckets_req_RW : STD_LOGIC;
signal bus_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal reg_bus_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal bus_nfa_finals_buckets_req_RW_en : STD_LOGIC;
signal bus_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal reg_bus_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal bus_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal bus_nfa_finals_buckets_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_finals_buckets_din : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_finals_buckets_dout : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_finals_buckets_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_finals_buckets_ready : STD_LOGIC;
signal bus_nfa_finals_buckets_done : STD_LOGIC;
component AESL_autobus_nfa_finals_buckets is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal bus_nfa_forward_buckets_req_RW : STD_LOGIC;
signal bus_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal reg_bus_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal bus_nfa_forward_buckets_req_RW_en : STD_LOGIC;
signal bus_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal reg_bus_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal bus_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal bus_nfa_forward_buckets_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_forward_buckets_din : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_forward_buckets_dout : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_forward_buckets_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_nfa_forward_buckets_ready : STD_LOGIC;
signal bus_nfa_forward_buckets_done : STD_LOGIC;
component AESL_autobus_nfa_forward_buckets is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal arraynfa_backward_buckets_ce0, arraynfa_backward_buckets_ce1 : STD_LOGIC;
signal arraynfa_backward_buckets_we0, arraynfa_backward_buckets_we1 : STD_LOGIC;
signal arraynfa_backward_buckets_address0, arraynfa_backward_buckets_address1 : STD_LOGIC_VECTOR(14 downto 0);
signal arraynfa_backward_buckets_din0, arraynfa_backward_buckets_din1 : STD_LOGIC_VECTOR(31 downto 0);
signal arraynfa_backward_buckets_dout0, arraynfa_backward_buckets_dout1 : STD_LOGIC_VECTOR(31 downto 0);
signal arraynfa_backward_buckets_ready : STD_LOGIC;
signal arraynfa_backward_buckets_done : STD_LOGIC;
component AESL_automem_nfa_backward_buckets is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR;
din0 : IN STD_LOGIC_VECTOR;
dout0 : OUT STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
address1 : IN STD_LOGIC_VECTOR;
din1 : IN STD_LOGIC_VECTOR;
dout1 : OUT STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
-- The signal of port nfa_symbols
shared variable AESL_REG_nfa_symbols : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal bus_sample_buffer_req_RW : STD_LOGIC;
signal bus_sample_buffer_req_full_n : STD_LOGIC;
signal reg_bus_sample_buffer_req_full_n : STD_LOGIC;
signal bus_sample_buffer_req_RW_en : STD_LOGIC;
signal bus_sample_buffer_rsp_empty_n : STD_LOGIC;
signal reg_bus_sample_buffer_rsp_empty_n : STD_LOGIC;
signal bus_sample_buffer_rsp_read : STD_LOGIC;
signal bus_sample_buffer_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_sample_buffer_din : STD_LOGIC_VECTOR(7 downto 0);
signal bus_sample_buffer_dout : STD_LOGIC_VECTOR(7 downto 0);
signal bus_sample_buffer_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_sample_buffer_ready : STD_LOGIC;
signal bus_sample_buffer_done : STD_LOGIC;
component AESL_autobus_sample_buffer is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
-- The signal of port sample_buffer_length
shared variable AESL_REG_sample_buffer_length : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port sample_length
shared variable AESL_REG_sample_length : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal bus_indices_begin_req_RW : STD_LOGIC;
signal bus_indices_begin_req_full_n : STD_LOGIC;
signal reg_bus_indices_begin_req_full_n : STD_LOGIC;
signal bus_indices_begin_req_RW_en : STD_LOGIC;
signal bus_indices_begin_rsp_empty_n : STD_LOGIC;
signal reg_bus_indices_begin_rsp_empty_n : STD_LOGIC;
signal bus_indices_begin_rsp_read : STD_LOGIC;
signal bus_indices_begin_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_begin_din : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_begin_dout : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_begin_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_begin_ready : STD_LOGIC;
signal bus_indices_begin_done : STD_LOGIC;
component AESL_autobus_indices_begin is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal bus_indices_samples_req_RW : STD_LOGIC;
signal bus_indices_samples_req_full_n : STD_LOGIC;
signal reg_bus_indices_samples_req_full_n : STD_LOGIC;
signal bus_indices_samples_req_RW_en : STD_LOGIC;
signal bus_indices_samples_rsp_empty_n : STD_LOGIC;
signal reg_bus_indices_samples_rsp_empty_n : STD_LOGIC;
signal bus_indices_samples_rsp_read : STD_LOGIC;
signal bus_indices_samples_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_samples_din : STD_LOGIC_VECTOR(15 downto 0);
signal bus_indices_samples_dout : STD_LOGIC_VECTOR(15 downto 0);
signal bus_indices_samples_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_samples_ready : STD_LOGIC;
signal bus_indices_samples_done : STD_LOGIC;
component AESL_autobus_indices_samples is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal bus_indices_stride_req_RW : STD_LOGIC;
signal bus_indices_stride_req_full_n : STD_LOGIC;
signal reg_bus_indices_stride_req_full_n : STD_LOGIC;
signal bus_indices_stride_req_RW_en : STD_LOGIC;
signal bus_indices_stride_rsp_empty_n : STD_LOGIC;
signal reg_bus_indices_stride_rsp_empty_n : STD_LOGIC;
signal bus_indices_stride_rsp_read : STD_LOGIC;
signal bus_indices_stride_address : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_stride_din : STD_LOGIC_VECTOR(7 downto 0);
signal bus_indices_stride_dout : STD_LOGIC_VECTOR(7 downto 0);
signal bus_indices_stride_size : STD_LOGIC_VECTOR(31 downto 0);
signal bus_indices_stride_ready : STD_LOGIC;
signal bus_indices_stride_done : STD_LOGIC;
component AESL_autobus_indices_stride is
port(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR;
bus_din : IN STD_LOGIC_VECTOR;
bus_dout : OUT STD_LOGIC_VECTOR;
bus_size : IN STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
-- The signal of port i_size
shared variable AESL_REG_i_size : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port begin_index
shared variable AESL_REG_begin_index : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port begin_sample
shared variable AESL_REG_begin_sample : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port end_index
shared variable AESL_REG_end_index : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port end_sample
shared variable AESL_REG_end_sample : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
-- The signal of port stop_on_first
shared variable AESL_REG_stop_on_first : STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
-- The signal of port accept
shared variable AESL_REG_accept : STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
-- purpose: initialise the random state variable based on an integer seed
function init_rand(seed : integer) return T_RANDINT is
variable result : T_RANDINT;
begin
-- If the seed is smaller than the minimum value of the random state variable, use the minimum value
if seed < T_RANDINT'low then
result := T_RANDINT'low;
-- If the seed is larger than the maximum value of the random state variable, use the maximum value
elsif seed > T_RANDINT'high then
result := T_RANDINT'high;
-- If the seed is within the range of the random state variable, just use the seed
else
result := seed;
end if;
-- Return the result
return result;
end init_rand;
-- purpose: generate a random integer between min and max limits
procedure rand_int(variable rand : inout T_RANDINT;
constant minval : in integer;
constant maxval : in integer;
variable result : out integer
) is
variable k, q : integer;
variable real_rand : real;
variable res : integer;
begin
-- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE
-- Based on an example from Numerical Recipes in C, 2nd Edition, page 279
k := rand/127773;
q := 16807*(rand-k*127773)-2836*k;
if q < 0 then
q := q + 2147483647;
end if;
rand := init_rand(q);
-- Convert this integer to a real number in the range 0 to 1
real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low);
-- Convert this real number to an integer in the range minval to maxval
-- The +1 and -0.5 are to get equal probability of minval and maxval as other values
res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval;
-- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this
if res < minval then
res := minval;
elsif res > maxval then
res := maxval;
end if;
-- assign output
result := res;
end rand_int;
begin
AESL_inst_nfa_accept_samples_generic_hw : nfa_accept_samples_generic_hw port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => ap_start,
ap_done => ap_done,
ap_idle => ap_idle,
ap_ready => ap_ready,
nfa_initials_buckets_req_din => nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => nfa_initials_buckets_address,
nfa_initials_buckets_datain => nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => nfa_initials_buckets_dataout,
nfa_initials_buckets_size => nfa_initials_buckets_size,
nfa_finals_buckets_req_din => nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => nfa_finals_buckets_address,
nfa_finals_buckets_datain => nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => nfa_finals_buckets_dataout,
nfa_finals_buckets_size => nfa_finals_buckets_size,
nfa_forward_buckets_req_din => nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => nfa_forward_buckets_address,
nfa_forward_buckets_datain => nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => nfa_forward_buckets_dataout,
nfa_forward_buckets_size => nfa_forward_buckets_size,
nfa_symbols => nfa_symbols,
sample_buffer_req_din => sample_buffer_req_din,
sample_buffer_req_full_n => sample_buffer_req_full_n,
sample_buffer_req_write => sample_buffer_req_write,
sample_buffer_rsp_empty_n => sample_buffer_rsp_empty_n,
sample_buffer_rsp_read => sample_buffer_rsp_read,
sample_buffer_address => sample_buffer_address,
sample_buffer_datain => sample_buffer_datain,
sample_buffer_dataout => sample_buffer_dataout,
sample_buffer_size => sample_buffer_size,
sample_buffer_length => sample_buffer_length,
sample_length => sample_length,
indices_begin_req_din => indices_begin_req_din,
indices_begin_req_full_n => indices_begin_req_full_n,
indices_begin_req_write => indices_begin_req_write,
indices_begin_rsp_empty_n => indices_begin_rsp_empty_n,
indices_begin_rsp_read => indices_begin_rsp_read,
indices_begin_address => indices_begin_address,
indices_begin_datain => indices_begin_datain,
indices_begin_dataout => indices_begin_dataout,
indices_begin_size => indices_begin_size,
indices_samples_req_din => indices_samples_req_din,
indices_samples_req_full_n => indices_samples_req_full_n,
indices_samples_req_write => indices_samples_req_write,
indices_samples_rsp_empty_n => indices_samples_rsp_empty_n,
indices_samples_rsp_read => indices_samples_rsp_read,
indices_samples_address => indices_samples_address,
indices_samples_datain => indices_samples_datain,
indices_samples_dataout => indices_samples_dataout,
indices_samples_size => indices_samples_size,
indices_stride_req_din => indices_stride_req_din,
indices_stride_req_full_n => indices_stride_req_full_n,
indices_stride_req_write => indices_stride_req_write,
indices_stride_rsp_empty_n => indices_stride_rsp_empty_n,
indices_stride_rsp_read => indices_stride_rsp_read,
indices_stride_address => indices_stride_address,
indices_stride_datain => indices_stride_datain,
indices_stride_dataout => indices_stride_dataout,
indices_stride_size => indices_stride_size,
i_size => i_size,
begin_index => begin_index,
begin_sample => begin_sample,
end_index => end_index,
end_sample => end_sample,
stop_on_first => stop_on_first,
accept => accept,
ap_return => ap_return
);
-- Assignment for control signal
ap_clk <= AESL_clock;
ap_rst <= AESL_reset;
AESL_reset <= rst;
ap_start <= AESL_start;
AESL_start <= start;
AESL_done <= ap_done;
AESL_idle <= ap_idle;
AESL_ready <= ap_ready;
AESL_ce <= ce;
AESL_continue <= continue;
AESL_inst_nfa_initials_buckets : AESL_autobus_nfa_initials_buckets port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_nfa_initials_buckets_req_RW,
bus_req_full_n => bus_nfa_initials_buckets_req_full_n,
bus_req_RW_en => bus_nfa_initials_buckets_req_RW_en,
bus_rsp_empty_n => bus_nfa_initials_buckets_rsp_empty_n,
bus_rsp_read => bus_nfa_initials_buckets_rsp_read,
bus_address => bus_nfa_initials_buckets_address,
bus_din => bus_nfa_initials_buckets_din,
bus_dout => bus_nfa_initials_buckets_dout,
bus_size => bus_nfa_initials_buckets_size,
ready => bus_nfa_initials_buckets_ready,
done => bus_nfa_initials_buckets_done
);
-- Assignment between dut and bus nfa_initials_buckets
-- Assign input of bus nfa_initials_buckets
bus_nfa_initials_buckets_req_RW <= nfa_initials_buckets_req_din;
bus_nfa_initials_buckets_req_RW_en <= nfa_initials_buckets_req_write and nfa_initials_buckets_req_full_n;
bus_nfa_initials_buckets_rsp_read <= nfa_initials_buckets_rsp_read and nfa_initials_buckets_rsp_empty_n;
bus_nfa_initials_buckets_address <= nfa_initials_buckets_address;
bus_nfa_initials_buckets_din <= nfa_initials_buckets_dataout;
bus_nfa_initials_buckets_size <= nfa_initials_buckets_size;
bus_nfa_initials_buckets_ready <= ready;
-- Assign input of dut
nfa_initials_buckets_datain <= bus_nfa_initials_buckets_dout;
gen_reg_bus_nfa_initials_buckets_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_initials_buckets_req_full_n <= '0';
while(true) loop
wait until bus_nfa_initials_buckets_req_full_n'event;
if(bus_nfa_initials_buckets_req_full_n = '1') then
end if;
reg_bus_nfa_initials_buckets_req_full_n <= bus_nfa_initials_buckets_req_full_n;
end loop;
end process;
nfa_initials_buckets_req_full_n <= reg_bus_nfa_initials_buckets_req_full_n;
gen_reg_bus_nfa_initials_buckets_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_initials_buckets_rsp_empty_n <= '0';
while(true) loop
wait until bus_nfa_initials_buckets_rsp_empty_n'event;
if(bus_nfa_initials_buckets_rsp_empty_n = '1') then
end if;
reg_bus_nfa_initials_buckets_rsp_empty_n <= bus_nfa_initials_buckets_rsp_empty_n;
end loop;
end process;
nfa_initials_buckets_rsp_empty_n <= reg_bus_nfa_initials_buckets_rsp_empty_n;
AESL_inst_nfa_finals_buckets : AESL_autobus_nfa_finals_buckets port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_nfa_finals_buckets_req_RW,
bus_req_full_n => bus_nfa_finals_buckets_req_full_n,
bus_req_RW_en => bus_nfa_finals_buckets_req_RW_en,
bus_rsp_empty_n => bus_nfa_finals_buckets_rsp_empty_n,
bus_rsp_read => bus_nfa_finals_buckets_rsp_read,
bus_address => bus_nfa_finals_buckets_address,
bus_din => bus_nfa_finals_buckets_din,
bus_dout => bus_nfa_finals_buckets_dout,
bus_size => bus_nfa_finals_buckets_size,
ready => bus_nfa_finals_buckets_ready,
done => bus_nfa_finals_buckets_done
);
-- Assignment between dut and bus nfa_finals_buckets
-- Assign input of bus nfa_finals_buckets
bus_nfa_finals_buckets_req_RW <= nfa_finals_buckets_req_din;
bus_nfa_finals_buckets_req_RW_en <= nfa_finals_buckets_req_write and nfa_finals_buckets_req_full_n;
bus_nfa_finals_buckets_rsp_read <= nfa_finals_buckets_rsp_read and nfa_finals_buckets_rsp_empty_n;
bus_nfa_finals_buckets_address <= nfa_finals_buckets_address;
bus_nfa_finals_buckets_din <= nfa_finals_buckets_dataout;
bus_nfa_finals_buckets_size <= nfa_finals_buckets_size;
bus_nfa_finals_buckets_ready <= ready;
-- Assign input of dut
nfa_finals_buckets_datain <= bus_nfa_finals_buckets_dout;
gen_reg_bus_nfa_finals_buckets_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_finals_buckets_req_full_n <= '0';
while(true) loop
wait until bus_nfa_finals_buckets_req_full_n'event;
if(bus_nfa_finals_buckets_req_full_n = '1') then
end if;
reg_bus_nfa_finals_buckets_req_full_n <= bus_nfa_finals_buckets_req_full_n;
end loop;
end process;
nfa_finals_buckets_req_full_n <= reg_bus_nfa_finals_buckets_req_full_n;
gen_reg_bus_nfa_finals_buckets_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_finals_buckets_rsp_empty_n <= '0';
while(true) loop
wait until bus_nfa_finals_buckets_rsp_empty_n'event;
if(bus_nfa_finals_buckets_rsp_empty_n = '1') then
end if;
reg_bus_nfa_finals_buckets_rsp_empty_n <= bus_nfa_finals_buckets_rsp_empty_n;
end loop;
end process;
nfa_finals_buckets_rsp_empty_n <= reg_bus_nfa_finals_buckets_rsp_empty_n;
AESL_inst_nfa_forward_buckets : AESL_autobus_nfa_forward_buckets port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_nfa_forward_buckets_req_RW,
bus_req_full_n => bus_nfa_forward_buckets_req_full_n,
bus_req_RW_en => bus_nfa_forward_buckets_req_RW_en,
bus_rsp_empty_n => bus_nfa_forward_buckets_rsp_empty_n,
bus_rsp_read => bus_nfa_forward_buckets_rsp_read,
bus_address => bus_nfa_forward_buckets_address,
bus_din => bus_nfa_forward_buckets_din,
bus_dout => bus_nfa_forward_buckets_dout,
bus_size => bus_nfa_forward_buckets_size,
ready => bus_nfa_forward_buckets_ready,
done => bus_nfa_forward_buckets_done
);
-- Assignment between dut and bus nfa_forward_buckets
-- Assign input of bus nfa_forward_buckets
bus_nfa_forward_buckets_req_RW <= nfa_forward_buckets_req_din;
bus_nfa_forward_buckets_req_RW_en <= nfa_forward_buckets_req_write and nfa_forward_buckets_req_full_n;
bus_nfa_forward_buckets_rsp_read <= nfa_forward_buckets_rsp_read and nfa_forward_buckets_rsp_empty_n;
bus_nfa_forward_buckets_address <= nfa_forward_buckets_address;
bus_nfa_forward_buckets_din <= nfa_forward_buckets_dataout;
bus_nfa_forward_buckets_size <= nfa_forward_buckets_size;
bus_nfa_forward_buckets_ready <= ready;
-- Assign input of dut
nfa_forward_buckets_datain <= bus_nfa_forward_buckets_dout;
gen_reg_bus_nfa_forward_buckets_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_forward_buckets_req_full_n <= '0';
while(true) loop
wait until bus_nfa_forward_buckets_req_full_n'event;
if(bus_nfa_forward_buckets_req_full_n = '1') then
end if;
reg_bus_nfa_forward_buckets_req_full_n <= bus_nfa_forward_buckets_req_full_n;
end loop;
end process;
nfa_forward_buckets_req_full_n <= reg_bus_nfa_forward_buckets_req_full_n;
gen_reg_bus_nfa_forward_buckets_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_nfa_forward_buckets_rsp_empty_n <= '0';
while(true) loop
wait until bus_nfa_forward_buckets_rsp_empty_n'event;
if(bus_nfa_forward_buckets_rsp_empty_n = '1') then
end if;
reg_bus_nfa_forward_buckets_rsp_empty_n <= bus_nfa_forward_buckets_rsp_empty_n;
end loop;
end process;
nfa_forward_buckets_rsp_empty_n <= reg_bus_nfa_forward_buckets_rsp_empty_n;
-- Assignment between dut and arraynfa_backward_buckets
arraynfa_backward_buckets_done <= '0';
gen_assign_nfa_symbols_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
nfa_symbols <= AESL_REG_nfa_symbols;
end process;
read_file_process_nfa_symbols : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_nfa_symbols, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_nfa_symbols & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_nfa_symbols severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_nfa_symbols severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_nfa_symbols := esl_str2lv_hex(token, 8 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
AESL_inst_sample_buffer : AESL_autobus_sample_buffer port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_sample_buffer_req_RW,
bus_req_full_n => bus_sample_buffer_req_full_n,
bus_req_RW_en => bus_sample_buffer_req_RW_en,
bus_rsp_empty_n => bus_sample_buffer_rsp_empty_n,
bus_rsp_read => bus_sample_buffer_rsp_read,
bus_address => bus_sample_buffer_address,
bus_din => bus_sample_buffer_din,
bus_dout => bus_sample_buffer_dout,
bus_size => bus_sample_buffer_size,
ready => bus_sample_buffer_ready,
done => bus_sample_buffer_done
);
-- Assignment between dut and bus sample_buffer
-- Assign input of bus sample_buffer
bus_sample_buffer_req_RW <= sample_buffer_req_din;
bus_sample_buffer_req_RW_en <= sample_buffer_req_write and sample_buffer_req_full_n;
bus_sample_buffer_rsp_read <= sample_buffer_rsp_read and sample_buffer_rsp_empty_n;
bus_sample_buffer_address <= sample_buffer_address;
bus_sample_buffer_din <= sample_buffer_dataout;
bus_sample_buffer_size <= sample_buffer_size;
bus_sample_buffer_ready <= ready;
-- Assign input of dut
sample_buffer_datain <= bus_sample_buffer_dout;
gen_reg_bus_sample_buffer_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_sample_buffer_req_full_n <= '0';
while(true) loop
wait until bus_sample_buffer_req_full_n'event;
if(bus_sample_buffer_req_full_n = '1') then
end if;
reg_bus_sample_buffer_req_full_n <= bus_sample_buffer_req_full_n;
end loop;
end process;
sample_buffer_req_full_n <= reg_bus_sample_buffer_req_full_n;
gen_reg_bus_sample_buffer_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_sample_buffer_rsp_empty_n <= '0';
while(true) loop
wait until bus_sample_buffer_rsp_empty_n'event;
if(bus_sample_buffer_rsp_empty_n = '1') then
end if;
reg_bus_sample_buffer_rsp_empty_n <= bus_sample_buffer_rsp_empty_n;
end loop;
end process;
sample_buffer_rsp_empty_n <= reg_bus_sample_buffer_rsp_empty_n;
gen_assign_sample_buffer_length_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
sample_buffer_length <= AESL_REG_sample_buffer_length;
end process;
read_file_process_sample_buffer_length : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_sample_buffer_length, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_sample_buffer_length & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_sample_buffer_length severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_sample_buffer_length severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_sample_buffer_length := esl_str2lv_hex(token, 32 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_sample_length_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
sample_length <= AESL_REG_sample_length;
end process;
read_file_process_sample_length : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_sample_length, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_sample_length & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_sample_length severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_sample_length severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_sample_length := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
AESL_inst_indices_begin : AESL_autobus_indices_begin port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_indices_begin_req_RW,
bus_req_full_n => bus_indices_begin_req_full_n,
bus_req_RW_en => bus_indices_begin_req_RW_en,
bus_rsp_empty_n => bus_indices_begin_rsp_empty_n,
bus_rsp_read => bus_indices_begin_rsp_read,
bus_address => bus_indices_begin_address,
bus_din => bus_indices_begin_din,
bus_dout => bus_indices_begin_dout,
bus_size => bus_indices_begin_size,
ready => bus_indices_begin_ready,
done => bus_indices_begin_done
);
-- Assignment between dut and bus indices_begin
-- Assign input of bus indices_begin
bus_indices_begin_req_RW <= indices_begin_req_din;
bus_indices_begin_req_RW_en <= indices_begin_req_write and indices_begin_req_full_n;
bus_indices_begin_rsp_read <= indices_begin_rsp_read and indices_begin_rsp_empty_n;
bus_indices_begin_address <= indices_begin_address;
bus_indices_begin_din <= indices_begin_dataout;
bus_indices_begin_size <= indices_begin_size;
bus_indices_begin_ready <= ready;
-- Assign input of dut
indices_begin_datain <= bus_indices_begin_dout;
gen_reg_bus_indices_begin_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_begin_req_full_n <= '0';
while(true) loop
wait until bus_indices_begin_req_full_n'event;
if(bus_indices_begin_req_full_n = '1') then
end if;
reg_bus_indices_begin_req_full_n <= bus_indices_begin_req_full_n;
end loop;
end process;
indices_begin_req_full_n <= reg_bus_indices_begin_req_full_n;
gen_reg_bus_indices_begin_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_begin_rsp_empty_n <= '0';
while(true) loop
wait until bus_indices_begin_rsp_empty_n'event;
if(bus_indices_begin_rsp_empty_n = '1') then
end if;
reg_bus_indices_begin_rsp_empty_n <= bus_indices_begin_rsp_empty_n;
end loop;
end process;
indices_begin_rsp_empty_n <= reg_bus_indices_begin_rsp_empty_n;
AESL_inst_indices_samples : AESL_autobus_indices_samples port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_indices_samples_req_RW,
bus_req_full_n => bus_indices_samples_req_full_n,
bus_req_RW_en => bus_indices_samples_req_RW_en,
bus_rsp_empty_n => bus_indices_samples_rsp_empty_n,
bus_rsp_read => bus_indices_samples_rsp_read,
bus_address => bus_indices_samples_address,
bus_din => bus_indices_samples_din,
bus_dout => bus_indices_samples_dout,
bus_size => bus_indices_samples_size,
ready => bus_indices_samples_ready,
done => bus_indices_samples_done
);
-- Assignment between dut and bus indices_samples
-- Assign input of bus indices_samples
bus_indices_samples_req_RW <= indices_samples_req_din;
bus_indices_samples_req_RW_en <= indices_samples_req_write and indices_samples_req_full_n;
bus_indices_samples_rsp_read <= indices_samples_rsp_read and indices_samples_rsp_empty_n;
bus_indices_samples_address <= indices_samples_address;
bus_indices_samples_din <= indices_samples_dataout;
bus_indices_samples_size <= indices_samples_size;
bus_indices_samples_ready <= ready;
-- Assign input of dut
indices_samples_datain <= bus_indices_samples_dout;
gen_reg_bus_indices_samples_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_samples_req_full_n <= '0';
while(true) loop
wait until bus_indices_samples_req_full_n'event;
if(bus_indices_samples_req_full_n = '1') then
end if;
reg_bus_indices_samples_req_full_n <= bus_indices_samples_req_full_n;
end loop;
end process;
indices_samples_req_full_n <= reg_bus_indices_samples_req_full_n;
gen_reg_bus_indices_samples_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_samples_rsp_empty_n <= '0';
while(true) loop
wait until bus_indices_samples_rsp_empty_n'event;
if(bus_indices_samples_rsp_empty_n = '1') then
end if;
reg_bus_indices_samples_rsp_empty_n <= bus_indices_samples_rsp_empty_n;
end loop;
end process;
indices_samples_rsp_empty_n <= reg_bus_indices_samples_rsp_empty_n;
AESL_inst_indices_stride : AESL_autobus_indices_stride port map (
clk => AESL_clock,
rst => AESL_reset,
bus_req_RW => bus_indices_stride_req_RW,
bus_req_full_n => bus_indices_stride_req_full_n,
bus_req_RW_en => bus_indices_stride_req_RW_en,
bus_rsp_empty_n => bus_indices_stride_rsp_empty_n,
bus_rsp_read => bus_indices_stride_rsp_read,
bus_address => bus_indices_stride_address,
bus_din => bus_indices_stride_din,
bus_dout => bus_indices_stride_dout,
bus_size => bus_indices_stride_size,
ready => bus_indices_stride_ready,
done => bus_indices_stride_done
);
-- Assignment between dut and bus indices_stride
-- Assign input of bus indices_stride
bus_indices_stride_req_RW <= indices_stride_req_din;
bus_indices_stride_req_RW_en <= indices_stride_req_write and indices_stride_req_full_n;
bus_indices_stride_rsp_read <= indices_stride_rsp_read and indices_stride_rsp_empty_n;
bus_indices_stride_address <= indices_stride_address;
bus_indices_stride_din <= indices_stride_dataout;
bus_indices_stride_size <= indices_stride_size;
bus_indices_stride_ready <= ready;
-- Assign input of dut
indices_stride_datain <= bus_indices_stride_dout;
gen_reg_bus_indices_stride_req_full_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_stride_req_full_n <= '0';
while(true) loop
wait until bus_indices_stride_req_full_n'event;
if(bus_indices_stride_req_full_n = '1') then
end if;
reg_bus_indices_stride_req_full_n <= bus_indices_stride_req_full_n;
end loop;
end process;
indices_stride_req_full_n <= reg_bus_indices_stride_req_full_n;
gen_reg_bus_indices_stride_rsp_empty_n_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_bus_indices_stride_rsp_empty_n <= '0';
while(true) loop
wait until bus_indices_stride_rsp_empty_n'event;
if(bus_indices_stride_rsp_empty_n = '1') then
end if;
reg_bus_indices_stride_rsp_empty_n <= bus_indices_stride_rsp_empty_n;
end loop;
end process;
indices_stride_rsp_empty_n <= reg_bus_indices_stride_rsp_empty_n;
gen_assign_i_size_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
i_size <= AESL_REG_i_size;
end process;
gen_assign_begin_index_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
begin_index <= AESL_REG_begin_index;
end process;
read_file_process_begin_index : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_begin_index, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_begin_index & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_begin_index severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_begin_index severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_begin_index := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_begin_sample_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
begin_sample <= AESL_REG_begin_sample;
end process;
read_file_process_begin_sample : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_begin_sample, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_begin_sample & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_begin_sample severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_begin_sample severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_begin_sample := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_end_index_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
end_index <= AESL_REG_end_index;
end process;
read_file_process_end_index : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_end_index, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_end_index & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_end_index severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_end_index severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_end_index := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_end_sample_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
end_sample <= AESL_REG_end_sample;
end process;
read_file_process_end_sample : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_end_sample, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_end_sample & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_end_sample severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_end_sample severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_end_sample := esl_str2lv_hex(token, 16 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_stop_on_first_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
stop_on_first <= AESL_REG_stop_on_first;
end process;
read_file_process_stop_on_first : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_stop_on_first, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_stop_on_first & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_stop_on_first severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_stop_on_first severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_stop_on_first := esl_str2lv_hex(token, 1 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
gen_assign_accept_proc : process
begin
wait until (AESL_clock'event and AESL_clock = '1');
wait for 0.45 ns;
accept <= AESL_REG_accept;
end process;
read_file_process_accept : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable i : INTEGER;
variable transaction_finish : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVIN_accept, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVIN_accept & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & AUTOTB_TVIN_accept severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & AUTOTB_TVIN_accept severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
esl_read_token(fp, token_line, token);
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
while(ready_wire /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.2 ns;
end loop;
if(token(1 to 16) /= "[[/transaction]]") then
AESL_REG_accept := esl_str2lv_hex(token, 1 );
esl_read_token(fp, token_line, token);
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
write_file_process_ap_return : process
file fp : TEXT;
file fp_size : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 280);
variable transaction_idx : INTEGER;
variable ap_return_count : INTEGER;
variable hls_stream_size : INTEGER;
variable i : INTEGER;
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
wait until AESL_reset = '0';
file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[runtime]]]"));
writeline(fp, token_line);
transaction_idx := 0;
while (transaction_idx /= AUTOTB_TRANSACTION_NUM) loop
write(token_line, string'("[[transaction]] ") & integer'image(transaction_idx));
writeline(fp, token_line);
wait until AESL_clock'event and AESL_clock = '1';
while(AESL_done /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
write(token_line, "0x" & esl_conv_string_hex(ap_return));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[[/runtime]]]"));
writeline(fp, token_line);
file_close(fp);
wait;
end process;
generate_AESL_ready_cnt_proc : process
begin
AESL_ready_cnt := 0;
wait until AESL_reset = '0';
while(AESL_ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
while(AESL_ready /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait until AESL_clock'event and AESL_clock = '0';
AESL_ready_cnt := AESL_ready_cnt + 1;
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
end process;
generate_ready_cnt_proc : process
begin
ready_cnt := 0;
wait until AESL_reset = '0';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
while(ready /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait until AESL_clock'event and AESL_clock = '0';
ready_cnt := ready_cnt + 1;
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait;
end process;
generate_done_cnt_proc : process
begin
done_cnt := 0;
wait until AESL_reset = '0';
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
while(AESL_done /= '1') loop
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait until AESL_clock'event and AESL_clock = '0';
done_cnt := done_cnt + 1;
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait for 0.4 ns;
assert false report "simulation done!" severity note;
assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure;
wait;
end process;
gen_clock_proc : process
begin
AESL_clock <= '0';
while(true) loop
wait for (AUTOTB_CLOCK_PERIOD/2.0);
AESL_clock <= not AESL_clock;
end loop;
wait;
end process;
gen_reset_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
rst <= '1';
wait for 100 ns;
for i in 1 to 3 loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
rst <= '0';
wait;
end process;
gen_start_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
start <= '0';
ce <= '1';
wait until AESL_reset = '0';
wait until (AESL_clock'event and AESL_clock = '1');
start <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop
wait until (AESL_clock'event and AESL_clock = '1');
if(AESL_ready = '1') then
start <= '0';
start <= '1';
end if;
end loop;
start <= '0';
wait;
end process;
gen_continue_proc : process(AESL_done)
begin
continue <= AESL_done;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until AESL_start = '1';
ready_initial <= '1';
wait until AESL_clock'event and AESL_clock = '1';
ready_initial <= '0';
wait;
end process;
gen_AESL_ready_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_ready_delay <= '0';
else
AESL_ready_delay <= AESL_ready;
end if;
end if;
end process;
ready_last_n_proc : process
begin
ready_last_n <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
ready_last_n <= '0';
wait;
end process;
gen_ready_delay_n_last_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
ready_delay_last_n <= '0';
else
ready_delay_last_n <= ready_last_n;
end if;
end if;
end process;
ready <= (ready_initial or AESL_ready_delay);
ready_wire <= ready_initial or AESL_ready_delay;
gen_done_delay_last_n_proc : process
begin
done_delay_last_n <= '1';
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
done_delay_last_n <= '0';
wait;
end process;
gen_done_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_done_delay <= '0';
AESL_done_delay2 <= '0';
else
AESL_done_delay <= AESL_done and done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end if;
end if;
end process;
gen_interface_done : process(ready, AESL_done_delay)
begin
if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then
interface_done <= ready;
elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_done_delay;
else
interface_done <= '0';
end if;
end process;
gen_clock_counter_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_clk_counter := 0;
else
AESL_clk_counter := AESL_clk_counter + 1;
end if;
end if;
end process;
gen_mLatcnterout_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_mLatCnterOut_addr := 0;
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ;
else
if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter;
AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1;
end if;
end if;
end if;
end process;
gen_mLatcnterin_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '1') then
AESL_mLatCnterIn_addr := 0;
else
if (AESL_start = '1' and AESL_mLatCnterIn_addr = 0) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
if (AESL_ready = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1 ) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
end if;
end if;
end process;
gen_performance_check_proc : process
variable transaction_counter : INTEGER;
variable i : INTEGER;
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable latthistime : INTEGER;
variable lattotal : INTEGER;
variable latmax : INTEGER;
variable latmin : INTEGER;
variable thrthistime : INTEGER;
variable thrtotal : INTEGER;
variable thrmax : INTEGER;
variable thrmin : INTEGER;
variable lataver : INTEGER;
variable thraver : INTEGER;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
variable lat_array : latency_record;
variable thr_array : latency_record;
begin
i := 0;
lattotal := 0;
latmax := 0;
latmin := 16#7fffffff#;
lataver := 0;
thrtotal := 0;
thrmax := 0;
thrmin := 16#7fffffff#;
thraver := 0;
wait until (AESL_clock'event and AESL_clock = '1');
wait until (AESL_reset = '0');
while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
wait for 0.001 ns;
if (AESL_mLatCnterIn_addr = 1 or AESL_mLatCnterIn_addr = 0 ) then
latmax := 0;
latmin := 0;
lataver := 0;
thrmax := 0;
thrmin := 0;
thraver := 0;
lat_array(0) := 0;
thr_array(0) := 0;
elsif (AESL_mLatCnterOut_addr = 1 or AESL_mLatCnterOut_addr = 0 ) then
latmax := AESL_mLatCnterOut(0) - AESL_mLatCnterIn(0);
latmin := AESL_mLatCnterOut(0) - AESL_mLatCnterIn(0);
lataver := AESL_mLatCnterOut(0) - AESL_mLatCnterIn(0);
thrmax := AESL_mLatCnterIn(1) - AESL_mLatCnterIn(0) + 1;
thrmin := AESL_mLatCnterIn(1) - AESL_mLatCnterIn(0) + 1;
thraver := AESL_mLatCnterIn(1) - AESL_mLatCnterIn(0) + 1;
lat_array(0) := lataver;
thr_array(0) := thraver;
else
-- LATENCY
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i) ;
if ( i > 0 ) then
if (latthistime - 1 < 0) then
latthistime := 0;
else
latthistime := latthistime - 1;
end if;
end if;
lattotal := lattotal + latthistime;
lat_array(i) := latthistime;
if (latthistime > latmax) then
latmax := latthistime;
end if;
if (latthistime < latmin) then
latmin := latthistime;
end if;
end loop;
-- II
for i in 0 to AESL_mLatCnterIn_addr - 2 loop
thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i);
if ( i = 0 ) then
thrthistime := thrthistime + 1;
end if;
thrtotal := thrtotal + thrthistime;
thr_array(i) := thrthistime;
if (thrthistime > thrmax) then
thrmax := thrthistime;
end if;
if (thrthistime < thrmin) then
thrmin := thrthistime;
end if;
end loop;
thr_array(AESL_mLatCnterIn_addr - 1) := 0;
lataver := lattotal / ( AESL_mLatCnterOut_addr);
thraver := thrtotal / ( AESL_mLatCnterIn_addr - 1 );
end if;
file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
file_close(fp);
file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line,string'(" latency interval"));
writeline(fp, token_line);
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
end loop;
file_close(fp);
wait;
end process;
end behav;
|
lgpl-3.0
|
jairov4/accel-oil
|
impl/impl_test_single/simulation/behavioral/nfa_accept_samples_generic_hw_top_v1_01_a/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2/_primary.vhd
|
1
|
1039
|
library verilog;
use verilog.vl_types.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2 is
generic(
ID : integer := 1;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 1;
din1_WIDTH : integer := 1;
dout_WIDTH : integer := 1
);
port(
clk : in vl_logic;
reset : in vl_logic;
ce : in vl_logic;
din0 : in vl_logic_vector;
din1 : in vl_logic_vector;
dout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of NUM_STAGE : constant is 1;
attribute mti_svvh_generic_type of din0_WIDTH : constant is 1;
attribute mti_svvh_generic_type of din1_WIDTH : constant is 1;
attribute mti_svvh_generic_type of dout_WIDTH : constant is 1;
end nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2;
|
lgpl-3.0
|
lerwys/GitTest
|
hdl/modules/wb_un_cross/cross_uncross_core/swap_cnt_top.vhd
|
1
|
7231
|
------------------------------------------------------------------------------
-- Title : Swapping Channel Pairs under Counter, Top entity
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This design uses a counter to divide clock input frequency and
-- apply it as enable signal to swap the switches of rf_ch_swap
-- block. The counting constant is a generic parameter.
-- Is possible to select the blocks independently. This option
-- allow us to compare with x without swiching mode of channels to
-- see how useful is switching mode to mitigate board drifts.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-01-24 1.0 jose.berkenbrock Created
-- 2013-01-25 1.1 jose.berkenbrock Independently mode selection
-- 2013-01-30 1.1 jose.berkenbrock Core description
-- 2013-02-14 1.2 jose.berkenbrock Set enable divider as generic
-- 2013-02-18 2.0 jose.berkenbrock New outputs swap and en_inv[2:1]
-- 2013-02-21 3.0 jose.berkenbrock New flag output, en_inv supressed
-- 2013-02-22 4.0 jose.berkenbrock New status out;flag/swap supressed
-- 2013-03-09 5.0 jose.berkenbrock swap_div_f_i added
-- 2013-07-01 5.1 lucas.russo Changed to synchronous resets
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library unisim;
--use unisim.vcomponents.all;
entity swap_cnt_top is
generic(
--g_en_swap_div : natural := 1023
g_swap_div_freq_vec_width : natural range 0 to 16 := 10
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
mode1_i : in std_logic_vector(1 downto 0);
mode2_i : in std_logic_vector(1 downto 0);
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
ext_clk_i : in std_logic;
ext_clk_en_i : in std_logic;
clk_swap_o : out std_logic;
clk_swap_en_i : in std_logic;
--blink_fmc : out std_logic;
status1_o : out std_logic;
status2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end swap_cnt_top;
architecture rtl of swap_cnt_top is
component rf_ch_swap
generic(
g_direct : std_logic_vector(7 downto 0) := "10100101";
g_inverted : std_logic_vector(7 downto 0) := "01011010");
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_swap_i : in std_logic;
mode_i : in std_logic_vector(1 downto 0);
status_o : out std_logic;
ctrl_o : out std_logic_vector(7 downto 0)
);
end component;
signal count : natural range 0 to 2**g_swap_div_freq_vec_width-1;
signal count_half : natural range 0 to 1;
signal cnst_swap_div_f : natural range 0 to 2**g_swap_div_freq_vec_width-1;
signal count2 : natural range 0 to 20000000;
signal blink : std_logic;
signal swap : std_logic;
signal swap_mux : std_logic;
signal swap_posedge : std_logic;
signal swap_old : std_logic;
signal swap_half : std_logic;
signal status1, status1_old : std_logic;
signal status2, status2_old : std_logic;
begin
cnst_swap_div_f <= (to_integer(unsigned(swap_div_f_i))+1);
------------------------------------------------------------------
---- Mode Register
----------------------------------
-- p_reg_mode : process(clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if rst_n_i = '0' then
-- s_mode <= (others => '0');
-- else
-- s_mode <= mode_i;
-- end if;
-- end if;
-- end process p_reg_mode;
----------------------------------------------------------------
-- Swapp_ch_rf Components Instantiation
----------------------------------------------------------------
swapp_inst_1: rf_ch_swap
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
--en_swap_i => swap,
en_swap_i => swap_half,
mode_i => mode1_i,
status_o => status1,
ctrl_o => ctrl1_o
);
swapp_inst_2: rf_ch_swap
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
--en_swap_i => swap,
en_swap_i => swap_half,
mode_i => mode2_i,
status_o => status2,
ctrl_o => ctrl2_o
);
----------------------------------------------------------------
p_freq_swap : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= 0;
swap <= '0';
else
if clk_swap_en_i = '0' then
count <= 0;
swap <= '0';
elsif count = cnst_swap_div_f then
count <= 0;
swap <= not swap;
else
count <= count + 1;
end if;
end if;
end if;
end process p_freq_swap;
----------------------------------------------------------------
-- Use external provided clock or the internal generated one
swap_mux <= ext_clk_i when ext_clk_en_i = '1' else swap;
p_swap_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
swap_old <= '0';
else
swap_old <= swap_mux;
end if;
end if;
end process p_swap_reg;
swap_posedge <= '1' when swap_mux = '1' and swap_old = '0' else '0';
p_freq_swap_half : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
--count_half <= 0;
swap_half <= '0';
else
if clk_swap_en_i = '0' then
swap_half <= '0';
elsif swap_posedge = '1' then
swap_half <= not swap_half;
end if;
end if;
end if;
end process p_freq_swap_half;
----------------------------------------------------------------
p_status : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
status1_old <= '0';
status2_old <= '0';
else
status1_old <= status1;
status2_old <= status2;
end if;
end if;
end process p_status;
----------------------------------------------------------------
clk_swap_o <= swap_mux;
status1_o <= status1 xor status1_old;
status2_o <= status2 xor status2_old;
end;
|
lgpl-3.0
|
fpga-logi/logi-hard
|
hdl/wishbone/logi_wishbone_pack.vhd
|
1
|
7247
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package logi_wishbone_pack is
function find_X(slv : std_logic_vector) return natural;
type wishbone16_bus is
record
address : std_logic_vector(15 downto 0);
writedata : std_logic_vector(15 downto 0);
readdata : std_logic_vector(15 downto 0);
cycle: std_logic;
write : std_logic;
strobe : std_logic;
ack : std_logic;
end record;
type array_of_addr is array(NATURAL range <>) of std_logic_vector(15 downto 0);
type array_of_slv16 is array(NATURAL range <>) of std_logic_vector(15 downto 0);
component gpmc_wishbone_wrapper is
generic(sync : boolean := false ; burst : boolean := false );
port
(
-- GPMC SIGNALS
gpmc_ad : inout std_logic_vector(15 downto 0);
gpmc_csn : in std_logic;
gpmc_oen : in std_logic;
gpmc_wen : in std_logic;
gpmc_advn : in std_logic;
gpmc_clk : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end component;
component gpmc_wishbone_wrapper_aad is
generic(
sync : boolean := true;
burst : boolean := false;
addr_width : natural := 28
);
port (
-- GPMC SIGNALS
gpmc_ad : inout std_logic_vector(15 downto 0);
gpmc_csn : in std_logic;
gpmc_oen : in std_logic;
gpmc_wen : in std_logic;
gpmc_advn : in std_logic;
gpmc_clk : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone master interface signals
wbm_address : out std_logic_vector(ADDR_WIDTH-1 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end component;
component spi_wishbone_wrapper is
generic(BIG_ENDIAN : boolean := true);
port
(
-- SPI SIGNALS
mosi, ss, sck : in std_logic;
miso : out std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic ; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end component;
component wishbone_intercon is
generic(memory_map : array_of_addr );
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone slave signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector(15 downto 0);
wbs_readdata : out std_logic_vector(15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Wishbone master signals
wbm_address : out array_of_slv16((memory_map'length-1) downto 0) ;
wbm_writedata : out array_of_slv16((memory_map'length-1) downto 0);
wbm_readdata : in array_of_slv16((memory_map'length-1) downto 0);
wbm_strobe : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_cycle : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_write : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_ack : in std_logic_vector((memory_map'length-1) downto 0)
);
end component;
end logi_wishbone_pack;
package body logi_wishbone_pack is
function find_X(slv : std_logic_vector) return natural is
begin
for i in slv'range loop
if slv(i) ='X' then
return i+1 ;
end if;
end loop;
return 0;
end function find_X;
--function sim_wishbone_write(data :integer; address : integer; wish_bus : wishbone16_bus ; clk : std_logic) return natural is
--
-- begin
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wish_bus.writedata <= std_logic_vector(to_unsigned(data, 16));
-- wish_bus.address <= std_logic_vector(to_unsigned(address, 16));
-- wait for rising_edge(clk);
-- wish_bus.cycle <= '1' ;
-- wish_bus.strobe <= '1';
-- wish_bus.write <= '1' ;
-- wait for wish_bus.ack = '1' ;
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wait for falling_edge(clk);
-- return 1;
--end function sim_wishbone_write;
--
--function sim_wishbone_write(data :integer; address : integer; wish_bus : wishbone16_bus ; clk : std_logic) return std_logic_vector(15 downto 0) is
--
-- begin
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wish_bus.writedata <= std_logic_vector(to_unsigned(0, 16));
-- wish_bus.address <= std_logic_vector(to_unsigned(address, 16));
-- wait for rising_edge(clk);
-- wish_bus.cycle <= '1' ;
-- wish_bus.strobe <= '1';
-- wish_bus.write <= '0' ;
-- wait for wish_bus.ack = '1' ;
-- wish_bus.cycle <= '0' ;
-- wish_bus.strobe <= '0';
-- wish_bus.write <= '0' ;
-- wait for falling_edge(clk);
-- return wish_bus.readdata;
--end function sim_wishbone_write;
end logi_wishbone_pack;
|
lgpl-3.0
|
fpga-logi/logi-hard
|
hdl/wishbone/peripherals/wishbone_to_xil_fifo.vhd
|
2
|
5572
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_to_xil_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
WR_FIFO_SIZE : natural := 128;
RD_FIFO_SIZE : natural := 128
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- fifo signals
fifo_rst : out std_logic;
-- write xil_fifo signals
wr_clk : out std_logic ;
dout : out std_logic_vector(15 downto 0);
wr_en : out std_logic ;
full : in std_logic ;
wr_data_count : in std_logic_vector(15 downto 0);
overflow : in std_logic;
-- read xil_fifo signals
rd_clk : out std_logic ;
din : in std_logic_vector(15 downto 0);
rd_en : out std_logic ;
empty : in std_logic ;
rd_data_count : in std_logic_vector(15 downto 0);
underflow : in std_logic
);
end wishbone_to_xil_fifo;
architecture RTL of wishbone_to_xil_fifo is
constant address_space_nbit : integer := MAX(nbit(WR_FIFO_SIZE), nbit(RD_FIFO_SIZE));
signal write_ack, read_ack : std_logic ;
signal gls_resetn : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data, fifo_status : std_logic_vector(15 downto 0) ;
signal fifo_data : std_logic_vector(15 downto 0) ;
signal data_access : std_logic ;
signal control_space_data_spacen : std_logic ;
begin
rd_clk <= gls_clk ;
wr_clk <= gls_clk ;
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
control_space_data_spacen <= wbs_address(address_space_nbit) ;
wbs_readdata <= control_latched when control_space_data_spacen = '1' else --data_access = '0' else
fifo_data ;
rd_en <= '1' when control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' and read_ack = '0' else
'0' ;
wr_en <= '1' when control_space_data_spacen = '0' and (wbs_strobe and wbs_write and wbs_cycle)= '1' and write_ack = '0' else
'0' ;
with conv_integer(wbs_address(address_space_nbit-1 downto 0)) select
control_data <= std_logic_vector(to_unsigned(RD_FIFO_SIZE, 16)) when 0,
std_logic_vector(to_unsigned(WR_FIFO_SIZE, 16)) when 1,
std_logic_vector(resize(unsigned(rd_data_count), 16)) when 2,
std_logic_vector(resize(unsigned(wr_data_count), 16)) when 3,
fifo_status when others;
fifo_status <= X"000" & empty & underflow & full & overflow ;
fifo_rst <= '1' when gls_reset = '1' else
'1' when control_space_data_spacen = '1' and (wbs_strobe and wbs_write and wbs_cycle)= '1' else
'0' ;
dout <= wbs_writedata ;
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
fifo_data <= (others => '0');
elsif rising_edge(gls_clk) then
if control_space_data_spacen = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' and read_ack = '0' then
fifo_data <= din ;
end if ;
end if;
end process;
end RTL;
|
lgpl-3.0
|
fpga-logi/logi-hard
|
hdl/control/l3gd20_interface.vhd
|
2
|
10118
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:47:08 08/26/2013
-- Design Name:
-- Module Name: mcp3002_interface - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity l3gd20_interface is
generic(CLK_DIV : positive := 100;
SAMPLING_DIV : positive := 1_000_000;
POL : std_logic := '0';
PHA : std_logic := '0');
port(
clk, resetn : std_logic ;
offset_x : in std_logic_vector(15 downto 0);
offset_y : in std_logic_vector(15 downto 0);
offset_z : in std_logic_vector(15 downto 0);
sample_x : out std_logic_vector(15 downto 0);
sample_y : out std_logic_vector(15 downto 0);
sample_z : out std_logic_vector(15 downto 0);
dv : out std_logic ;
-- spi signals
DOUT : out std_logic ;
DIN : in std_logic ;
SCLK : out std_logic ;
SSN : out std_logic
);
end l3gd20_interface;
architecture Behavioral of l3gd20_interface is
type tranfer_state is (WAIT_SAMPLE, ASSERT_CS, XFER_DATA, DEASSERT_CS);
signal current_transfer_state, next_transfer_state : tranfer_state;
signal data_out_shift_reg : std_logic_vector(15 downto 0) ;
signal data_in_shift_reg : std_logic_vector(55 downto 0);
signal load_shift_register : std_logic ;
signal tempo_val : std_logic_vector(nbit(SAMPLING_DIV)-1 downto 0);
signal count_tempo : std_logic_vector(nbit(SAMPLING_DIV)-1 downto 0 );
signal load_tempo, en_tempo, end_tempo : std_logic ;
signal data_clk, data_clk_old, data_clk_re, data_clk_fe : std_logic ;
signal en_bit_count, reset_byte_count : std_logic ;
signal bit_count, byte_count : std_logic_vector(4 downto 0);
signal bit_count_eq_8 : std_logic ;
signal cmd_word, config_word : std_logic_vector(15 downto 0);
signal init_done : std_logic ;
signal ssn_d : std_logic ;
signal shift_in_en, shift_out_en : std_logic ;
signal end_of_xfer: std_logic ;
signal latch_data : std_logic ;
signal sample_x_temp, sample_y_temp, sample_z_temp : std_logic_vector(15 downto 0);
begin
-- tempo
process(clk, resetn)
begin
if resetn = '0' then
count_tempo <= (others => '1');
elsif clk'event and clk = '1' then
if load_tempo = '1' then
count_tempo <= tempo_val ;
elsif en_tempo = '1' then
if count_tempo /= 0 then
count_tempo <= count_tempo - 1 ;
end if ;
end if ;
end if ;
end process ;
end_tempo <= '1' when count_tempo = 0 else
'0' ;
-- bit counter
process(clk, resetn)
begin
if resetn = '0' then
bit_count <= (others => '0');
byte_count <= (others => '0');
elsif clk'event and clk = '1' then
if bit_count_eq_8 = '1' then
bit_count <= (others => '0');
elsif en_bit_count = '1' then
bit_count <= bit_count + 1 ;
end if ;
if reset_byte_count = '1' then
byte_count <= (others => '0');
elsif bit_count_eq_8 = '1' then
byte_count <= byte_count + 1 ;
end if ;
end if ;
end process ;
bit_count_eq_8 <= '1' when bit_count = 8 else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
current_transfer_state <= WAIT_SAMPLE;
elsif clk'event and clk = '1' then
current_transfer_state <= next_transfer_state;
end if ;
end process ;
process(bit_count, byte_count, end_tempo, init_done, bit_count_eq_8, current_transfer_state)
begin
next_transfer_state <= current_transfer_state ;
case current_transfer_state is
when wait_sample =>
if end_tempo = '1' then
next_transfer_state <= assert_cs ;
end if ;
when assert_cs =>
if end_tempo = '1' then
next_transfer_state <= xfer_data ;
end if ;
when xfer_data =>
if end_of_xfer = '1' then
next_transfer_state <= deassert_cs ;
end if ;
when deassert_cs =>
if end_tempo = '1' then
next_transfer_state <= wait_sample ;
end if ;
when others =>
next_transfer_state <= wait_sample ;
end case;
end process ;
end_of_xfer <= '1' when byte_count = 2 and bit_count = 0 and init_done = '0' and end_tempo = '1' else -- once on reset
'1' when byte_count = 7 and bit_count = 0 and init_done = '1' and end_tempo = '1' else
'0' ;
process(clk, resetn)
begin
if resetn = '0' then
init_done <= '0' ;
elsif clk'event and clk = '1' then
if current_transfer_state = deassert_cs then
init_done <= '1' ;
end if ;
end if ;
end process ;
-- generating clk for spi communication
process(clk, resetn)
begin
if resetn = '0' then
data_clk <= '0' ;
elsif clk'event and clk = '1' then
if current_transfer_state = xfer_data and end_of_xfer = '0'then
if end_tempo = '1' then
data_clk <= not data_clk ;
end if ;
else
data_clk <= POL ;
end if ;
end if ;
end process ;
-- data clock rising edge and falling edge detect
process(clk, resetn)
begin
if resetn = '0' then
data_clk_old <= '0' ;
elsif clk'event and clk = '1' then
data_clk_old <= data_clk ;
end if ;
end process ;
data_clk_re <= data_clk and (not data_clk_old);
data_clk_fe <= (not data_clk) and data_clk_old;
-- command to send on reset ...
-- starting on register 2, and auto increment of address enabled
config_word <= X"60" & X"0F" ;--& X"00" & X"80" ;
-- L3GD20_REGISTER_OUT_X_L | 0x80 for reading the data
cmd_word <= X"E8FF" ;
shift_out_en <= data_clk_re when POL = '0' else
data_clk_fe when POL = '1' and (bit_count > 0 or byte_count > 0);
--shift register for data out
process(clk, resetn)
begin
if resetn = '0' then
data_out_shift_reg <= (others => '0') ;
elsif clk'event and clk = '1' then
if load_shift_register = '1' and init_done = '0' then
data_out_shift_reg <= config_word ;
elsif load_shift_register = '1' and init_done = '1' then
data_out_shift_reg <= cmd_word ;
elsif shift_out_en = '1' then
data_out_shift_reg(15 downto 1) <= data_out_shift_reg(14 downto 0) ;
data_out_shift_reg(0) <= '1' ;
end if ;
end if ;
end process ;
shift_in_en <= data_clk_fe when POL = '0' else
data_clk_re;--shift register for data in
process(clk, resetn)
begin
if resetn = '0' then
data_in_shift_reg <= (others => '0') ;
elsif clk'event and clk = '1' then
if shift_in_en = '1' then
data_in_shift_reg(55 downto 1) <= data_in_shift_reg(54 downto 0) ;
data_in_shift_reg(0) <= DIN ;
end if ;
end if ;
end process ;
with current_transfer_state select
load_shift_register <= end_tempo when assert_cs,
'0' when others ;
en_tempo <= '1' ;
with current_transfer_state select
tempo_val <= std_logic_vector(to_unsigned(CLK_DIV, nbit(SAMPLING_DIV))) when wait_sample,
std_logic_vector(to_unsigned(CLK_DIV, nbit(SAMPLING_DIV))) when assert_cs,
std_logic_vector(to_unsigned(CLK_DIV, nbit(SAMPLING_DIV))) when xfer_data,
std_logic_vector(to_unsigned(SAMPLING_DIV, nbit(SAMPLING_DIV))) when deassert_cs,
(others => '0') when others ;
with current_transfer_state select
load_tempo <= end_tempo when wait_sample,
end_tempo when assert_cs,
end_tempo when xfer_data,
end_tempo when deassert_cs,
'0' when others ;
with current_transfer_state select
en_bit_count <= shift_in_en when xfer_data,
'0' when others ;
with current_transfer_state select
reset_byte_count <= '1' when deassert_cs,
'1' when wait_sample,
'1' when assert_cs,
'0' when others ;
-- outputs
with current_transfer_state select
ssn_d <= '0' when assert_cs,
'0' when xfer_data,
'1' when others ;
latch_data <= '1' when current_transfer_state=xfer_data and byte_count = 7 and bit_count_eq_8 = '1' else
'0' ;
sample_x_temp(7 downto 0) <= data_in_shift_reg(47 downto 40);
sample_x_temp(15 downto 8) <= data_in_shift_reg(39 downto 32);
sample_y_temp(7 downto 0) <= data_in_shift_reg(31 downto 24);
sample_y_temp(15 downto 8) <= data_in_shift_reg(23 downto 16);
sample_z_temp(7 downto 0) <= data_in_shift_reg(15 downto 8);
sample_z_temp(15 downto 8) <= data_in_shift_reg(7 downto 0);
process(clk, resetn)
begin
if resetn = '0' then
sample_x <=(others => '0');
sample_y <= (others => '0');
sample_z <= (others => '0');
elsif clk'event and clk = '1' then
if latch_data <= '1' then
sample_x <= sample_x_temp - offset_x ;
sample_y <= sample_y_temp - offset_y ;
sample_z <= sample_z_temp - offset_z ;
end if ;
dv <= latch_data ;
end if ;
end process ;
-- todo may delete following stuf, output are not combinatorial ...
process(clk, resetn)
begin
if resetn = '0' then
DOUT <= '0' ;
SCLK <= '0' ;
SSN <= '1' ;
elsif clk'event and clk = '1' then
DOUT <= data_out_shift_reg(15) ;
SCLK <= data_clk ;
SSN <= ssn_d ;
end if ;
end process ;
end Behavioral;
|
lgpl-3.0
|
fpga-logi/logi-hard
|
hdl/interface/SDRAM_Controller.vhd
|
2
|
25292
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 14:09:12 09/15/2013
-- Module Name: SDRAM_Controller - Behavioral
-- Description: Simple SDRAM controller for a Micron 48LC16M16A2-7E
-- or Micron 48LC4M16A2-7E @ 100MHz
-- Revision:
-- Revision 0.1 - Initial version
-- Revision 0.2 - Removed second clock signal that isn't needed.
-- Revision 0.3 - Added back-to-back reads and writes.
-- Revision 0.4 - Allow refeshes to be delayed till next PRECHARGE is issued,
-- Unless they get really, really delayed. If a delay occurs multiple
-- refreshes might get pushed out, but it will have avioded about
-- 50% of the refresh overhead
-- Revision 0.5 - Add more paramaters to the design, allowing it to work for both the
-- Papilio Pro and Logi-Pi
--
-- Worst case performance (single accesses to different rows or banks) is:
-- Writes 16 cycles = 6,250,000 writes/sec = 25.0MB/s (excluding refresh overhead)
-- Reads 17 cycles = 5,882,352 reads/sec = 23.5MB/s (excluding refresh overhead)
--
-- For 1:1 mixed reads and writes into the same row it is around 88MB/s
-- For reads or wries to the same it is can be as high as 184MB/s
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.NUMERIC_STD.ALL;
entity SDRAM_Controller is
generic (
sdram_address_width : natural;
sdram_column_bits : natural;
sdram_startup_cycles: natural;
cycles_per_refresh : natural ;
very_low_speed : natural := 0
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- Interface to issue reads or write data
cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : in STD_LOGIC; -- Is this a write?
cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
data_out_ready : out STD_LOGIC; -- is new data ready?
-- SDRAM signals
SDRAM_CLK : out STD_LOGIC;
SDRAM_CKE : out STD_LOGIC;
SDRAM_CS : out STD_LOGIC;
SDRAM_RAS : out STD_LOGIC;
SDRAM_CAS : out STD_LOGIC;
SDRAM_WE : out STD_LOGIC;
SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0));
end SDRAM_Controller;
architecture Behavioral of SDRAM_Controller is
-- From page 37 of MT48LC16M16A2 datasheet
-- Name (Function) CS# RAS# CAS# WE# DQM Addr Data
-- COMMAND INHIBIT (NOP) H X X X X X X
-- NO OPERATION (NOP) L H H H X X X
-- ACTIVE L L H H X Bank/row X
-- READ L H L H L/H Bank/col X
-- WRITE L H L L L/H Bank/col Valid
-- BURST TERMINATE L H H L X X Active
-- PRECHARGE L L H L X Code X
-- AUTO REFRESH L L L H X X X
-- LOAD MODE REGISTER L L L L X Op-code X
-- Write enable X X X X L X Active
-- Write inhibit X X X X H X High-Z
-- Here are the commands mapped to constants
constant CMD_UNSELECTED : std_logic_vector(3 downto 0) := "1000";
constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011";
constant CMD_READ : std_logic_vector(3 downto 0) := "0101";
constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant CMD_TERMINATE : std_logic_vector(3 downto 0) := "0110";
constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
constant CMD_REFRESH : std_logic_vector(3 downto 0) := "0001";
constant CMD_LOAD_MODE_REG : std_logic_vector(3 downto 0) := "0000";
constant MODE_REG : std_logic_vector(12 downto 0) :=
-- Reserved, wr bust, OpMode, CAS Latency (2), Burst Type, Burst Length (2)
"000" & "0" & "00" & "010" & "0" & "001";
signal iob_command : std_logic_vector( 3 downto 0) := CMD_NOP;
signal iob_address : std_logic_vector(12 downto 0) := (others => '0');
signal iob_data : std_logic_vector(15 downto 0) := (others => '0');
signal iob_dqm : std_logic_vector( 1 downto 0) := (others => '0');
signal iob_cke : std_logic := '0';
signal iob_bank : std_logic_vector( 1 downto 0) := (others => '0');
attribute IOB: string;
attribute IOB of iob_command: signal is "true";
attribute IOB of iob_address: signal is "true";
attribute IOB of iob_dqm : signal is "true";
attribute IOB of iob_cke : signal is "true";
attribute IOB of iob_bank : signal is "true";
attribute IOB of iob_data : signal is "true";
signal iob_data_next : std_logic_vector(15 downto 0) := (others => '0');
signal captured_data : std_logic_vector(15 downto 0) := (others => '0');
signal captured_data_last : std_logic_vector(15 downto 0) := (others => '0');
signal sdram_din : std_logic_vector(15 downto 0);
attribute IOB of captured_data : signal is "true";
type fsm_state is (s_startup,
s_idle_in_6, s_idle_in_5, s_idle_in_4, s_idle_in_3, s_idle_in_2, s_idle_in_1,
s_idle,
s_open_in_2, s_open_in_1,
s_write_1, s_write_2, s_write_3,
s_read_1, s_read_2, s_read_3, s_read_4,
s_precharge
);
signal state : fsm_state := s_startup;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of state : signal is "ONE-HOT";
-- dual purpose counter, it counts up during the startup phase, then is used to trigger refreshes.
constant startup_refresh_max : unsigned(13 downto 0) := (others => '1');
signal startup_refresh_count : unsigned(13 downto 0) := startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
-- logic to decide when to refresh
signal pending_refresh : std_logic := '0';
signal forcing_refresh : std_logic := '0';
-- The incoming address is split into these three values
signal addr_row : std_logic_vector(12 downto 0) := (others => '0');
signal addr_col : std_logic_vector(12 downto 0) := (others => '0');
signal addr_bank : std_logic_vector( 1 downto 0) := (others => '0');
signal dqm_sr : std_logic_vector( 3 downto 0) := (others => '1'); -- an extra two bits in case CAS=3
-- signals to hold the requested transaction before it is completed
signal save_wr : std_logic := '0';
signal save_row : std_logic_vector(12 downto 0);
signal save_bank : std_logic_vector( 1 downto 0);
signal save_col : std_logic_vector(12 downto 0);
signal save_data_in : std_logic_vector(31 downto 0);
signal save_byte_enable : std_logic_vector( 3 downto 0);
-- control when new transactions are accepted
signal ready_for_new : std_logic := '0';
signal got_transaction : std_logic := '0';
signal can_back_to_back : std_logic := '0';
-- signal to control the Hi-Z state of the DQ bus
signal iob_dq_hiz : std_logic := '1';
-- signals for when to read the data off of the bus
signal data_ready_delay : std_logic_vector( 4 - (very_low_speed) downto 0);
-- bit indexes used when splitting the address into row/colum/bank.
constant start_of_col : natural := 0;
constant end_of_col : natural := sdram_column_bits-2;
constant start_of_bank : natural := sdram_column_bits-1;
constant end_of_bank : natural := sdram_column_bits;
constant start_of_row : natural := sdram_column_bits+1;
constant end_of_row : natural := sdram_address_width-2;
constant prefresh_cmd : natural := 10;
begin
-- Indicate the need to refresh when the counter is 2048,
-- Force a refresh when the counter is 4096 - (if a refresh is forced,
-- multiple refresshes will be forced until the counter is below 2048
pending_refresh <= startup_refresh_count(11);
forcing_refresh <= startup_refresh_count(12);
-- tell the outside world when we can accept a new transaction;
cmd_ready <= ready_for_new;
----------------------------------------------------------------------------
-- Seperate the address into row / bank / address
----------------------------------------------------------------------------
addr_row(end_of_row-start_of_row downto 0) <= cmd_address(end_of_row downto start_of_row); -- 12:0 <= 22:10
addr_bank <= cmd_address(end_of_bank downto start_of_bank); -- 1:0 <= 9:8
addr_col(sdram_column_bits-1 downto 0) <= cmd_address(end_of_col downto start_of_col) & '0'; -- 8:0 <= 7:0 & '0'
-----------------------------------------------------------
-- Forward the SDRAM clock to the SDRAM chip - 180 degress
-- out of phase with the control signals (ensuring setup and holdup
-----------------------------------------------------------
sdram_clk_forward : ODDR2
generic map(DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC")
port map (Q => sdram_clk, C0 => clk, C1 => not clk, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1');
-----------------------------------------------
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--!! Ensure that all outputs are registered. !!
--!! Check the pinout report to be sure !!
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-----------------------------------------------
sdram_cke <= iob_cke;
sdram_CS <= iob_command(3);
sdram_RAS <= iob_command(2);
sdram_CAS <= iob_command(1);
sdram_WE <= iob_command(0);
sdram_dqm <= iob_dqm;
sdram_ba <= iob_bank;
sdram_addr <= iob_address;
---------------------------------------------------------------
-- Explicitly set up the tristate I/O buffers on the DQ signals
---------------------------------------------------------------
iob_dq_g: for i in 0 to 15 generate
begin
iob_dq_iob: IOBUF
generic map (DRIVE => 12, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map ( O => sdram_din(i), IO => sdram_data(i), I => iob_data(i), T => iob_dq_hiz);
end generate;
capture_proc: process(clk)
begin
if rising_edge(clk) then
captured_data <= sdram_din;
end if;
end process;
main_proc: process(clk)
begin
if rising_edge(clk) then
captured_data_last <= captured_data;
------------------------------------------------
-- Default state is to do nothing
------------------------------------------------
iob_command <= CMD_NOP;
iob_address <= (others => '0');
iob_bank <= (others => '0');
------------------------------------------------
-- countdown for initialisation & refresh
------------------------------------------------
startup_refresh_count <= startup_refresh_count+1;
-------------------------------------------------------------------
-- It we are ready for a new tranasction and one is being presented
-- then accept it. Also remember what we are reading or writing,
-- and if it can be back-to-backed with the last transaction
-------------------------------------------------------------------
if ready_for_new = '1' and cmd_enable = '1' then
if save_bank = addr_bank and save_row = addr_row then
can_back_to_back <= '1';
else
can_back_to_back <= '0';
end if;
save_row <= addr_row;
save_bank <= addr_bank;
save_col <= addr_col;
save_wr <= cmd_wr;
save_data_in <= cmd_data_in;
save_byte_enable <= cmd_byte_enable;
got_transaction <= '1';
ready_for_new <= '0';
end if;
------------------------------------------------
-- Handle the data coming back from the
-- SDRAM for the Read transaction
------------------------------------------------
data_out_ready <= '0';
if data_ready_delay(0) = '1' then
data_out <= captured_data & captured_data_last;
data_out_ready <= '1';
end if;
----------------------------------------------------------------------------
-- update shift registers used to choose when to present data to/from memory
----------------------------------------------------------------------------
data_ready_delay <= '0' & data_ready_delay(data_ready_delay'high downto 1);
iob_dqm <= dqm_sr(1 downto 0);
dqm_sr <= "11" & dqm_sr(dqm_sr'high downto 2);
case state is
when s_startup =>
------------------------------------------------------------------------
-- This is the initial startup state, where we wait for at least 100us
-- before starting the start sequence
--
-- The initialisation is sequence is
-- * de-assert SDRAM_CKE
-- * 100us wait,
-- * assert SDRAM_CKE
-- * wait at least one cycle,
-- * PRECHARGE
-- * wait 2 cycles
-- * REFRESH,
-- * tREF wait
-- * REFRESH,
-- * tREF wait
-- * LOAD_MODE_REG
-- * 2 cycles wait
------------------------------------------------------------------------
iob_CKE <= '1';
-- All the commands during the startup are NOPS, except these
if startup_refresh_count = startup_refresh_max-31 then
-- ensure all rows are closed
iob_command <= CMD_PRECHARGE;
iob_address(prefresh_cmd) <= '1'; -- all banks
iob_bank <= (others => '0');
elsif startup_refresh_count = startup_refresh_max-23 then
-- these refreshes need to be at least tREF (66ns) apart
iob_command <= CMD_REFRESH;
elsif startup_refresh_count = startup_refresh_max-15 then
iob_command <= CMD_REFRESH;
elsif startup_refresh_count = startup_refresh_max-7 then
-- Now load the mode register
iob_command <= CMD_LOAD_MODE_REG;
iob_address <= MODE_REG;
end if;
------------------------------------------------------
-- if startup is coomplete then go into idle mode,
-- get prepared to accept a new command, and schedule
-- the first refresh cycle
------------------------------------------------------
if startup_refresh_count = 0 then
state <= s_idle;
ready_for_new <= '1';
got_transaction <= '0';
startup_refresh_count <= to_unsigned(2048 - cycles_per_refresh+1,14);
end if;
when s_idle_in_6 => state <= s_idle_in_5;
when s_idle_in_5 => state <= s_idle_in_4;
when s_idle_in_4 => state <= s_idle_in_3;
when s_idle_in_3 => state <= s_idle_in_2;
when s_idle_in_2 => state <= s_idle_in_1;
when s_idle_in_1 => state <= s_idle;
when s_idle =>
-- Priority is to issue a refresh if one is outstanding
if pending_refresh = '1' or forcing_refresh = '1' then
------------------------------------------------------------------------
-- Start the refresh cycle.
-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
------------------------------------------------------------------------
state <= s_idle_in_6;
iob_command <= CMD_REFRESH;
startup_refresh_count <= startup_refresh_count - cycles_per_refresh+1;
elsif got_transaction = '1' then
--------------------------------
-- Start the read or write cycle.
-- First task is to open the row
--------------------------------
state <= s_open_in_2;
iob_command <= CMD_ACTIVE;
iob_address <= save_row;
iob_bank <= save_bank;
end if;
--------------------------------------------
-- Opening the row ready for reads or writes
--------------------------------------------
when s_open_in_2 => state <= s_open_in_1;
when s_open_in_1 =>
-- still waiting for row to open
if save_wr = '1' then
state <= s_write_1;
iob_dq_hiz <= '0';
iob_data <= save_data_in(15 downto 0); -- get the DQ bus out of HiZ early
else
iob_dq_hiz <= '1';
state <= s_read_1;
end if;
-- we will be ready for a new transaction next cycle!
ready_for_new <= '1';
got_transaction <= '0';
----------------------------------
-- Processing the read transaction
----------------------------------
when s_read_1 =>
state <= s_read_2;
iob_command <= CMD_READ;
iob_address <= save_col;
iob_bank <= save_bank;
iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
-- Schedule reading the data values off the bus
data_ready_delay(data_ready_delay'high) <= '1';
-- Set the data masks to read all bytes
iob_dqm <= (others => '0');
dqm_sr(1 downto 0) <= (others => '0');
when s_read_2 =>
state <= s_read_3;
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
end if;
when s_read_3 =>
state <= s_read_4;
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
end if;
when s_read_4 =>
state <= s_precharge;
-- can we do back-to-back read?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '0' then
state <= s_read_1;
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
else
state <= s_open_in_2; -- we have to wait for the read data to come back before we swutch the bus into HiZ
end if;
end if;
------------------------------------------------------------------
-- Processing the write transaction
-------------------------------------------------------------------
when s_write_1 =>
state <= s_write_2;
iob_command <= CMD_WRITE;
iob_address <= save_col;
iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
iob_bank <= save_bank;
iob_dqm <= NOT save_byte_enable(1 downto 0);
dqm_sr(1 downto 0) <= NOT save_byte_enable(3 downto 2);
iob_data <= save_data_in(15 downto 0);
iob_data_next <= save_data_in(31 downto 16);
when s_write_2 =>
state <= s_write_3;
iob_data <= iob_data_next;
-- can we do a back-to-back write?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '1' then
-- back-to-back write?
state <= s_write_1;
ready_for_new <= '1';
got_transaction <= '0';
end if;
-- Although it looks right in simulation you can't go write-to-read
-- here due to bus contention, as iob_dq_hiz takes a few ns.
end if;
when s_write_3 => -- must wait tRDL, hence the extra idle state
-- back to back transaction?
if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
if save_wr = '1' then
-- back-to-back write?
state <= s_write_1;
ready_for_new <= '1';
got_transaction <= '0';
else
-- write-to-read switch?
state <= s_read_1;
iob_dq_hiz <= '1';
ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
got_transaction <= '0';
end if;
else
iob_dq_hiz <= '1';
state <= s_precharge;
end if;
-------------------------------------------------------------------
-- Closing the row off (this closes all banks)
-------------------------------------------------------------------
when s_precharge =>
state <= s_idle_in_3;
iob_command <= CMD_PRECHARGE;
iob_address(prefresh_cmd) <= '1'; -- A10 actually matters - it selects all banks or just one
-------------------------------------------------------------------
-- We should never get here, but if we do then reset the memory
-------------------------------------------------------------------
when others =>
state <= s_startup;
ready_for_new <= '0';
startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
end case;
if reset = '1' then -- Sync reset
state <= s_startup;
ready_for_new <= '0';
startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
end if;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd
|
1
|
13680
|
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
--
-- Modified by Lucas Russo <[email protected]> for multiple width support
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wb_stream_generic_pkg.all;
entity wb_stream_sink_gen is
generic (
--g_wbs_adr_width : natural := c_wbs_adr4_width;
g_wbs_interface_width : t_wbs_interface_width := LARGE1
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Streaming Interface I/O.
-- Only the used interface should be connected. The others can be left unconnected
-- 16-bit interface
snk_adr16_i : in t_wbs_adr4 := cc_dummy_wbs_adr4;
snk_dat16_i : in t_wbs_dat16 := cc_dummy_wbs_dat16;
snk_sel16_i : in t_wbs_sel16 := cc_dummy_wbs_sel16;
-- 32-bit interface
snk_adr32_i : in t_wbs_adr4 := cc_dummy_wbs_adr4;
snk_dat32_i : in t_wbs_dat32 := cc_dummy_wbs_dat32;
snk_sel32_i : in t_wbs_sel32 := cc_dummy_wbs_sel32;
-- 64-bit interface
snk_adr64_i : in t_wbs_adr4 := cc_dummy_wbs_adr4;
snk_dat64_i : in t_wbs_dat64 := cc_dummy_wbs_dat64;
snk_sel64_i : in t_wbs_sel64 := cc_dummy_wbs_sel64;
-- 128-bit interface
snk_adr128_i : in t_wbs_adr4 := cc_dummy_wbs_adr4;
snk_dat128_i : in t_wbs_dat128 := cc_dummy_wbs_dat128;
snk_sel128_i : in t_wbs_sel128 := cc_dummy_wbs_sel128;
-- Common Wishbone Streaming lines
snk_cyc_i : in std_logic := '0';
snk_stb_i : in std_logic := '0';
snk_we_i : in std_logic := '0';
snk_ack_o : out std_logic;
snk_stall_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered logic
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
adr16_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat16_o : out std_logic_vector(c_wbs_dat16_width-1 downto 0);
sel16_o : out std_logic_vector(c_wbs_sel16_width-1 downto 0);
-- 32-bit interface
adr32_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat32_o : out std_logic_vector(c_wbs_dat32_width-1 downto 0);
sel32_o : out std_logic_vector(c_wbs_sel32_width-1 downto 0);
-- 64-bit interface
adr64_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat64_o : out std_logic_vector(c_wbs_dat64_width-1 downto 0);
sel64_o : out std_logic_vector(c_wbs_sel64_width-1 downto 0);
-- 128-bit interface
adr128_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat128_o : out std_logic_vector(c_wbs_dat128_width-1 downto 0);
sel128_o : out std_logic_vector(c_wbs_sel128_width-1 downto 0);
-- Common lines
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
dreq_i : in std_logic := '0'
);
end wb_stream_sink_gen;
architecture rtl of wb_stream_sink_gen is
-- Convert enum to natural
constant c_wbs_dat_width : natural := f_conv_wbs_interface_width(g_wbs_interface_width);
constant c_wbs_sel_width : natural := c_wbs_dat_width/8;
-- Fixed 4-bit address as we do not exceptct it to address real peripheral
-- just to inform some other conditions
constant c_wbs_adr_width : natural := c_wbs_adr4_width;
-- FIFO ranges
constant c_dat_lsb : natural := 0;
constant c_dat_msb : natural := c_dat_lsb + c_wbs_dat_width - 1;
constant c_adr_lsb : natural := c_dat_msb + 1;
constant c_adr_msb : natural := c_adr_lsb + c_wbs_adr_width -1;
constant c_valid_bit : natural := c_adr_msb + 1;
constant c_sel_lsb : natural := c_valid_bit + 1;
constant c_sel_msb : natural := c_sel_lsb + c_wbs_sel_width - 1;
constant c_eof_bit : natural := c_sel_msb + 1;
constant c_sof_bit : natural := c_eof_bit + 1;
alias c_logic_lsb is c_valid_bit;
alias c_logic_msb is c_sof_bit;
constant c_logic_width : integer := c_sof_bit - c_valid_bit + 1;
constant c_fifo_width : integer := c_sof_bit - c_dat_lsb + 1;
constant c_fifo_depth : integer := 32;
constant c_logic_zeros : std_logic_vector(c_logic_msb downto c_logic_lsb)
:= std_logic_vector(to_unsigned(0, c_logic_width));
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
signal cyc_d0, rd_d0 : std_logic;
signal pre_sof, pre_dvalid : std_logic;
signal pre_eof : std_logic;
signal pre_dat : std_logic_vector(c_wbs_dat_width-1 downto 0);
signal pre_adr : std_logic_vector(c_wbs_adr_width-1 downto 0);
signal pre_sel : std_logic_vector(c_wbs_sel_width-1 downto 0);
signal post_sof, post_dvalid : std_logic;
signal post_adr : std_logic_vector(c_wbs_adr_width-1 downto 0);
signal post_dat : std_logic_vector(c_wbs_dat_width-1 downto 0);
signal post_eof : std_logic;
signal post_sel : std_logic_vector(c_wbs_sel_width-1 downto 0);
-- Internal signals
signal snk_stall_int : std_logic;
signal snk_ack_int : std_logic;
signal snk_rty_int : std_logic;
signal snk_err_int : std_logic;
begin -- rtl
p_delay_cyc_and_rd : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
rd_d0 <= '0';
else
if(full = '0') then
cyc_d0 <= snk_cyc_i;
end if;
rd_d0 <= rd;
end if;
end if;
end process;
pre_sof <= snk_cyc_i and not cyc_d0;
pre_eof <= not snk_cyc_i and cyc_d0;
pre_dvalid <= snk_stb_i and snk_we_i and snk_cyc_i and not snk_stall_int;
-----------------------------
-- Wishbone Streaming Interface selection
-----------------------------
gen_16_bit_interface_in : if g_wbs_interface_width = NARROW2 generate
fin(c_dat_msb downto c_dat_lsb) <= snk_dat16_i;
fin(c_adr_msb downto c_adr_lsb) <= snk_adr16_i;
pre_sel <= snk_sel16_i;
end generate;
gen_32_bit_interface_in : if g_wbs_interface_width = NARROW1 generate
fin(c_dat_msb downto c_dat_lsb) <= snk_dat32_i;
fin(c_adr_msb downto c_adr_lsb) <= snk_adr32_i;
pre_sel <= snk_sel32_i;
end generate;
gen_64_bit_interface_in : if g_wbs_interface_width = LARGE1 generate
fin(c_dat_msb downto c_dat_lsb) <= snk_dat64_i;
fin(c_adr_msb downto c_adr_lsb) <= snk_adr64_i;
pre_sel <= snk_sel64_i;
end generate;
gen_128_bit_interface_in : if g_wbs_interface_width = LARGE2 generate
fin(c_dat_msb downto c_dat_lsb) <= snk_dat128_i;
fin(c_adr_msb downto c_adr_lsb) <= snk_adr128_i;
pre_sel <= snk_sel128_i;
end generate;
fin(c_logic_msb downto c_logic_lsb) <= pre_sof & pre_eof & pre_sel & pre_dvalid;
snk_stall_int <= full or (snk_cyc_i and not cyc_d0);
snk_err_int <= '0';
snk_rty_int <= '0';
p_gen_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
snk_ack_int <= '0';
else
snk_ack_int <= snk_cyc_i and snk_stb_i and snk_we_i and not snk_stall_int;
end if;
end if;
end process;
we <= '1' when fin(c_logic_msb downto c_logic_lsb) /= c_logic_zeros
and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid
);
p_fout_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fout_reg <= (others => '0');
elsif(rd = '1') then
fout_reg <= fout;
end if;
end if;
end process;
-- Output fifo registers only when valid
--p_post_regs : process(fout_reg, q_valid)
--begin
-- if q_valid = '1' then
-- post_data <= fout_reg(c_data_msb downto c_data_lsb);
-- post_addr <= fout_reg(c_addr_msb downto c_addr_lsb);
-- post_sof <= fout_reg(c_sof_bit); --and rd_d0; --and q_valid;
-- post_dvalid <= fout_reg(c_valid_bit);
-- post_eof <= fout_reg(c_eof_bit);-- and rd_d0;
-- post_bytesel <= fout_reg(c_sel_msb downto c_sel_lsb);
-- else
-- post_data <= (others => '0');
-- post_addr <= (others => '0');
-- post_sof <= '0';
-- post_dvalid <= '0';
-- post_eof <= '0';
-- post_bytesel <= (others => '0');
-- end if;
--end process;
post_sof <= fout_reg(c_sof_bit) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(c_valid_bit);
post_eof <= fout_reg(c_eof_bit);
post_sel <= fout_reg(c_sel_msb downto c_sel_lsb);
post_dat <= fout_reg(c_dat_msb downto c_dat_lsb);
post_adr <= fout_reg(c_adr_msb downto c_adr_lsb);
snk_stall_o <= snk_stall_int;
snk_ack_o <= snk_ack_int;
snk_rty_o <= snk_rty_int;
snk_err_o <= snk_err_int;
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_adr = std_logic_vector(resize(c_WBS_STATUS, post_adr'length))) and
(f_unmarshall_wbs_status(post_dat).error = '1') else '0';
eof_o <= post_eof and rd_d0;
-----------------------------
-- Wishbone Streaming Interface selection
-----------------------------
gen_16_bit_interface_out : if g_wbs_interface_width = NARROW2 generate
sel16_o <= post_sel;
dat16_o <= post_dat;
adr16_o <= post_adr;
end generate;
gen_32_bit_interface_out : if g_wbs_interface_width = NARROW1 generate
sel32_o <= post_sel;
dat32_o <= post_dat;
adr32_o <= post_adr;
end generate;
gen_64_bit_interface_out : if g_wbs_interface_width = LARGE1 generate
sel64_o <= post_sel;
dat64_o <= post_dat;
adr64_o <= post_adr;
end generate;
gen_128_bit_interface_out : if g_wbs_interface_width = LARGE2 generate
sel128_o <= post_sel;
dat128_o <= post_dat;
adr128_o <= post_adr;
end generate;
end rtl;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/sim/dac3283_init_mem.vhd
|
1
|
5466
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file dac3283_init_mem.vhd when simulating
-- the core, dac3283_init_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY dac3283_init_mem IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END dac3283_init_mem;
ARCHITECTURE dac3283_init_mem_a OF dac3283_init_mem IS
-- synthesis translate_off
COMPONENT wrapped_dac3283_init_mem
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_dac3283_init_mem USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "virtex6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/sim/dac3283_init_mem.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_dac3283_init_mem
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END dac3283_init_mem_a;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd
|
1
|
20129
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : rank_common.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Wed Jun 17 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-- Block for logic common to all rank machines. Contains
-- a clock prescaler, and arbiters for refresh and periodic
-- read functions.
entity rank_common is
generic (
TCQ : integer := 100;
DRAM_TYPE : string := "DDR3";
MAINT_PRESCALER_DIV : integer := 40;
nBANK_MACHS : integer := 4;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
REFRESH_TIMER_DIV : integer := 39;
ZQ_TIMER_DIV : integer := 640000
);
port (
-- Outputs
-- Inputs
-- ceiling logb2
-- Maintenance and periodic read prescaler. Nominally 200 nS.
--clogb2(MAINT_PRESCALER_DIV + 1);
maint_prescaler_tick_r : out std_logic;
-- Refresh timebase. Nominically 7800 nS.
refresh_tick : out std_logic;
-- block: maintenance_request
maint_zq_r : out std_logic;
maint_req_r : out std_logic;
maint_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
-- Periodic reads to maintain PHY alignment.
-- Demand insertion of periodic read as soon as
-- possible. Since the is a single rank, bank compare mechanism
-- must be used, periodic reads must be forced in at the
-- expense of not accepting a normal request.
clear_periodic_rd_request : out std_logic_vector(RANKS - 1 downto 0);
-- Maintenance request pipeline.
-- Arbitrate periodic read requests.
-- Inputs
-- Encode and set periodic read rank into periodic_rd_rank_r.
-- Once the request is dropped in the queue, it might be a while before it
-- emerges. Can't clear the request based on seeing the read issued.
-- Need to clear the request as soon as its made it into the queue.
-- block: maintenance_request
periodic_rd_r : out std_logic;
periodic_rd_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
dfi_init_complete : in std_logic;
app_zq_req : in std_logic;
insert_maint_r1 : in std_logic;
refresh_request : in std_logic_vector(RANKS - 1 downto 0);
maint_wip_r : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
periodic_rd_request : in std_logic_vector(RANKS - 1 downto 0);
periodic_rd_ack_r : in std_logic
);
end entity rank_common;
architecture trans of rank_common is
component round_robin_arb
generic (
TCQ : integer := 100;
WIDTH : integer := 3
);
port (
grant_ns : out std_logic_vector(WIDTH - 1 downto 0);
grant_r : out std_logic_vector(WIDTH - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
req : in std_logic_vector(WIDTH - 1 downto 0);
disable_grant : in std_logic;
current_master : in std_logic_vector(WIDTH - 1 downto 0);
upd_last_master : in std_logic
);
end component;
function nCOPY (A : in std_logic; B : in integer) return std_logic_vector is
variable tmp : std_logic_vector(B - 1 downto 0);
begin
for i in 0 to B - 1 loop
tmp(i) := A;
end loop;
return tmp;
end function nCOPY;
function clogb2(size: integer) return integer is
variable tmp : integer := 1;
variable tmp_size : std_logic_vector (31 downto 0);
begin
tmp_size := std_logic_vector(TO_UNSIGNED((size - 1),32));
while ( to_integer(UNSIGNED(tmp_size)) > 1 ) loop
tmp_size := std_logic_vector(UNSIGNED(tmp_size) srl 1);
tmp := tmp + 1;
end loop;
return tmp;
--for i in 23 downto 0 loop
-- if( size <= 2** i) then
-- tmp := i;
-- end if;
--end loop;
--return tmp;
end function clogb2;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
constant ONE : integer := 1;
constant MAINT_PRESCALER_WIDTH : integer := clogb2(MAINT_PRESCALER_DIV + 1);
constant REFRESH_TIMER_WIDTH : integer := clogb2(REFRESH_TIMER_DIV + 1);
constant ZQ_TIMER_WIDTH : integer := clogb2(ZQ_TIMER_DIV + 1);
signal maint_prescaler_tick_r_lcl : std_logic;
signal refresh_tick_lcl : std_logic;
signal maint_zq_r_lcl : std_logic;
signal zq_request : std_logic := '0';
signal maint_req_r_lcl : std_logic;
signal maint_rank_r_lcl : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal periodic_rd_r_lcl : std_logic;
signal periodic_rd_rank_r_lcl : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal periodic_rd_rank_ns : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal periodic_rd_grant_r : std_logic_vector(RANKS - 1 downto 0);
signal periodic_rd_grant_ns : std_logic_vector(RANKS - 1 downto 0);
signal maint_grant_ns : std_logic_vector(RANKS downto 0);
signal maint_grant_r : std_logic_vector(RANKS downto 0);
signal maint_rank_ns : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal periodic_rd_busy : std_logic;
signal maint_zq_ns : std_logic;
signal upd_last_master_ns : std_logic;
signal upd_last_master_r : std_logic;
signal new_maint_rank_r : std_logic;
signal zq_timer_r : std_logic_vector(ZQ_TIMER_WIDTH - 1 downto 0);
signal zq_timer_ns : std_logic_vector(ZQ_TIMER_WIDTH - 1 downto 0);
signal refresh_timer_r : std_logic_vector(REFRESH_TIMER_WIDTH - 1 downto 0);
signal refresh_timer_ns : std_logic_vector(REFRESH_TIMER_WIDTH - 1 downto 0);
signal periodic_upd_last_master_ns : std_logic; -- local signal in verilog code within periodic request
signal periodic_upd_last_master_r : std_logic;
signal maint_request : std_logic_vector(RANKS downto 0);
signal maint_busy : std_logic;
signal maint_prescaler_r : std_logic_vector(MAINT_PRESCALER_WIDTH-1 downto 0);
signal maint_prescaler_ns : std_logic_vector(MAINT_PRESCALER_WIDTH-1 downto 0);
signal maint_prescaler_tick_ns : std_logic;
signal zq_request_r : std_logic;
signal zq_request_ns : std_logic;
signal zq_tick : std_logic := '0';
signal zq_clears_zq_request : std_logic;
signal present : std_logic_vector(7 downto 0);
signal periodic_rd_ns : std_logic;
signal int2 : std_logic;
signal int3 : std_logic_vector(RANKS - 1 downto 0);
signal tst_rdor_rd_request : std_logic;
begin
maint_prescaler_tick_ns <= BOOLEAN_TO_STD_LOGIC(maint_prescaler_r = std_logic_vector(TO_UNSIGNED(1,MAINT_PRESCALER_WIDTH)));
process (dfi_init_complete, maint_prescaler_r, maint_prescaler_tick_ns)
begin
maint_prescaler_ns <= maint_prescaler_r;
if ((not(dfi_init_complete) or maint_prescaler_tick_ns) = '1') then
maint_prescaler_ns <= std_logic_vector(TO_UNSIGNED(MAINT_PRESCALER_DIV,MAINT_PRESCALER_WIDTH));
elsif ((REDUCTION_OR(maint_prescaler_r)) = '1') then
maint_prescaler_ns <= maint_prescaler_r - std_logic_vector(TO_UNSIGNED(1,MAINT_PRESCALER_WIDTH));
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
maint_prescaler_r <= maint_prescaler_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
maint_prescaler_tick_r_lcl <= maint_prescaler_tick_ns after (TCQ)*1 ps;
end if;
end process;
maint_prescaler_tick_r <= maint_prescaler_tick_r_lcl;
process (dfi_init_complete, maint_prescaler_tick_r_lcl, refresh_tick_lcl, refresh_timer_r)
begin
refresh_timer_ns <= refresh_timer_r;
if ((not(dfi_init_complete) or refresh_tick_lcl) = '1') then
refresh_timer_ns <= std_logic_vector(TO_UNSIGNED(REFRESH_TIMER_DIV,REFRESH_TIMER_WIDTH ));
elsif ((REDUCTION_OR(refresh_timer_r) and maint_prescaler_tick_r_lcl) = '1') then
refresh_timer_ns <= refresh_timer_r - std_logic_vector(TO_UNSIGNED(1,REFRESH_TIMER_WIDTH));
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
refresh_timer_r <= refresh_timer_ns after (TCQ)*1 ps;
end if;
end process;
refresh_tick_lcl <= BOOLEAN_TO_STD_LOGIC(refresh_timer_r = std_logic_vector(TO_UNSIGNED(1,REFRESH_TIMER_WIDTH ))) and maint_prescaler_tick_r_lcl;
refresh_tick <= refresh_tick_lcl;
int0 : if (DRAM_TYPE = "DDR3") generate
int1 : if (ZQ_TIMER_DIV /= 0) generate
process (dfi_init_complete, maint_prescaler_tick_r_lcl, zq_tick, zq_timer_r)
variable zq_timer_ns_tmp : std_logic_vector(ZQ_TIMER_WIDTH - 1 downto 0);
begin
zq_timer_ns_tmp := zq_timer_r;
if ((not(dfi_init_complete) or zq_tick) = '1') then
zq_timer_ns_tmp := std_logic_vector(TO_UNSIGNED(ZQ_TIMER_DIV,ZQ_TIMER_WIDTH ));
elsif ((REDUCTION_OR(zq_timer_r) and maint_prescaler_tick_r_lcl) = '1') then
zq_timer_ns_tmp := zq_timer_r - std_logic_vector(TO_UNSIGNED(1,ZQ_TIMER_WIDTH ));
end if;
zq_timer_ns <= zq_timer_ns_tmp ;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
zq_timer_r <= zq_timer_ns after (TCQ)*1 ps;
end if;
end process;
process (maint_prescaler_tick_r_lcl, zq_timer_r)
begin
zq_tick <= (BOOLEAN_TO_STD_LOGIC(zq_timer_r = std_logic_vector(TO_UNSIGNED(1,ZQ_TIMER_WIDTH ))) and maint_prescaler_tick_r_lcl);
end process;
end generate;
zq_clears_zq_request <= insert_maint_r1 and maint_zq_r_lcl;
zq_request_ns <= not(rst) and BOOLEAN_TO_STD_LOGIC(DRAM_TYPE = "DDR3") and
((not(dfi_init_complete) and BOOLEAN_TO_STD_LOGIC(ZQ_TIMER_DIV /= 0)) or
(zq_request_r and not(zq_clears_zq_request)) or
zq_tick or
(app_zq_req and dfi_init_complete));
process (clk)
begin
if (clk'event and clk = '1') then
zq_request_r <= zq_request_ns after (TCQ)*1 ps;
end if;
end process;
process (dfi_init_complete, zq_request_r)
begin
zq_request <= dfi_init_complete and zq_request_r;
end process;
end generate;
-- Maintenance_request
maint_busy <= upd_last_master_r or new_maint_rank_r or maint_req_r_lcl or maint_wip_r;
maint_request <= (zq_request & refresh_request(RANKS - 1 downto 0));
upd_last_master_ns <= REDUCTION_OR(maint_request) and not(maint_busy);
process (clk)
begin
if (clk'event and clk = '1') then
upd_last_master_r <= upd_last_master_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
new_maint_rank_r <= upd_last_master_r after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
maint_req_r_lcl <= new_maint_rank_r after (TCQ)*1 ps;
end if;
end process;
maint_arb0 : round_robin_arb
generic map (
WIDTH => (RANKS + 1)
)
port map (
grant_ns => maint_grant_ns,
grant_r => maint_grant_r,
upd_last_master => upd_last_master_r,
current_master => maint_grant_r,
req => maint_request,
disable_grant => '0',
clk => clk,
rst => rst
);
present <= slot_0_present or slot_1_present;
maint_zq_ns <= not(rst) and maint_grant_r(RANKS) when (upd_last_master_r = '1') else
not(rst) and maint_zq_r_lcl;
process (maint_grant_r, maint_rank_r_lcl, maint_zq_ns, present, rst, upd_last_master_r)
variable maint_rank_ns_tmp : std_logic_vector(RANK_WIDTH-1 downto 0);
begin
if (rst = '1') then
maint_rank_ns_tmp := (others => '0' );
else
maint_rank_ns_tmp := maint_rank_r_lcl;
if (maint_zq_ns = '1') then
maint_rank_ns_tmp := maint_rank_r_lcl + std_logic_vector(TO_UNSIGNED(1,RANK_WIDTH ));
for i in 0 to 7 loop
if ((not(present(to_integer(UNSIGNED(maint_rank_ns_tmp))))) = '1') then
maint_rank_ns_tmp := maint_rank_ns_tmp + std_logic_vector(TO_UNSIGNED(1,RANK_WIDTH));
end if;
end loop;
elsif (upd_last_master_r = '1') then
for i in 0 to RANKS - 1 loop
if ((maint_grant_r(i)) = '1') then
maint_rank_ns_tmp := std_logic_vector(TO_UNSIGNED(i,RANK_WIDTH ));
end if;
end loop;
end if;
end if;
maint_rank_ns <= maint_rank_ns_tmp;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
maint_rank_r_lcl <= maint_rank_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
maint_zq_r_lcl <= maint_zq_ns after (TCQ)*1 ps;
end if;
end process;
maint_zq_r <= maint_zq_r_lcl;
maint_req_r <= maint_req_r_lcl;
maint_rank_r <= maint_rank_r_lcl;
-- generate : periodic_read_request
periodic_rd_busy <= periodic_upd_last_master_r or periodic_rd_r_lcl;
--upd_last_master_ns <= dfi_init_complete and (REDUCTION_OR(periodic_rd_request) and not(periodic_rd_busy));
periodic_upd_last_master_ns <= dfi_init_complete and (REDUCTION_OR(periodic_rd_request) and not(periodic_rd_busy));
process (clk)
begin
if (clk'event and clk = '1') then
periodic_upd_last_master_r <= periodic_upd_last_master_ns after (TCQ)*1 ps;
end if;
end process;
periodic_rd_ns <= dfi_init_complete and (periodic_upd_last_master_r or (periodic_rd_r_lcl and not(periodic_rd_ack_r)));
process (clk)
begin
if (clk'event and clk = '1') then
periodic_rd_r_lcl <= periodic_rd_ns after (TCQ)*1 ps;
end if;
end process;
periodic_rd_arb0 : round_robin_arb
generic map (
WIDTH => RANKS
)
port map (
grant_ns => periodic_rd_grant_ns(RANKS - 1 downto 0),
grant_r => open,
upd_last_master => periodic_upd_last_master_r,--upd_last_master_r,
current_master => periodic_rd_grant_r(RANKS - 1 downto 0),
req => periodic_rd_request(RANKS - 1 downto 0),
disable_grant => '0',
clk => clk,
rst => rst
);
int3 <= periodic_rd_grant_ns when (periodic_upd_last_master_ns = '1') else
periodic_rd_grant_r;
process (clk)
begin
if (clk'event and clk = '1') then
periodic_rd_grant_r <= int3;
end if;
end process;
process (periodic_rd_grant_r, periodic_rd_rank_r_lcl, periodic_upd_last_master_r)
begin
periodic_rd_rank_ns <= periodic_rd_rank_r_lcl;
if (periodic_upd_last_master_r = '1') then
for i in 0 to RANKS - 1 loop
if ((periodic_rd_grant_r(i)) = '1') then
periodic_rd_rank_ns <= std_logic_vector(TO_UNSIGNED(i,RANK_WIDTH ));
end if;
end loop;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
periodic_rd_rank_r_lcl <= periodic_rd_rank_ns after (TCQ)*1 ps;
end if;
end process;
clear_periodic_rd_request <= periodic_rd_grant_r and nCOPY(periodic_rd_ack_r,RANKS);
periodic_rd_r <= periodic_rd_r_lcl;
periodic_rd_rank_r <= periodic_rd_rank_r_lcl;
end architecture trans;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192.vhd
|
2
|
1215
|
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila_8192.vhd
-- /___/ /\ Timestamp : Thu Mar 28 15:52:52 BRT 2013
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila_8192 IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(7 downto 0);
TRIG1: in std_logic_vector(31 downto 0);
TRIG2: in std_logic_vector(31 downto 0);
TRIG3: in std_logic_vector(31 downto 0);
TRIG4: in std_logic_vector(31 downto 0));
END chipscope_ila_8192;
ARCHITECTURE chipscope_ila_8192_a OF chipscope_ila_8192 IS
BEGIN
END chipscope_ila_8192_a;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/top/pcie/top_ml605.vhd
|
1
|
11157
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_sys_clk_n : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic --Reset to PCIe core
);
end entity top;
architecture arch of top is
component bpm_pcie_ml605 is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE"
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
---- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic
);
end component bpm_pcie_ml605;
-- WISHBONE SLAVE interface:
-- Single-Port RAM with Asynchronous Read
--
component WB_MEM is
generic(
AWIDTH : natural range 2 to 29 := 7;
DWIDTH : natural range 8 to 128 := 64
);
port(
CLK_I : in std_logic;
ACK_O : out std_logic;
ADR_I : in std_logic_vector(AWIDTH-1 downto 0);
DAT_I : in std_logic_vector(DWIDTH-1 downto 0);
DAT_O : out std_logic_vector(DWIDTH-1 downto 0);
STB_I : in std_logic;
WE_I : in std_logic
);
end component;
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_rst_i : std_logic;
signal ddr_ui_clk : std_logic;
signal pll_clkin : std_logic;
signal pll_clkfbout : std_logic;
signal pll_clkout0 : std_logic;
signal pll_locked : std_logic;
signal wbone_clk : std_logic;
signal wbone_addr : std_logic_vector(31 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
signal wbone_rst : std_logic;
begin
bpm_pcie : bpm_pcie_ml605
generic map(
SIMULATION => SIMULATION,
-- ****
-- PCIe core parameters
-- ****
pcieLanes => pcieLanes,
PL_FAST_TRAIN => PL_FAST_TRAIN,
PIPE_SIM_MODE => PIPE_SIM_MODE
)
port map(
--DDR3 memory pins
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cs_n => ddr3_cs_n,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- PCIe transceivers
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- Necessity signals
ddr_sys_clk_p => ddr_sys_clk_i,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_rst_n => sys_rst_n,
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst => ddr_sys_rst_i,
memc_ui_clk => ddr_ui_clk,
memc_ui_rst => open,
memc_cmd_rdy => open,
memc_cmd_en => '0',
memc_cmd_instr => (others => '0'),
memc_cmd_addr => (others => '0'),
memc_wr_en => '0',
memc_wr_end => '0',
memc_wr_mask => (others => '0'),
memc_wr_data => (others => '0'),
memc_wr_rdy => open,
memc_rd_data => open,
memc_rd_valid => open,
---- memory arbiter interface
memarb_acc_req => '0',
memarb_acc_gnt => open,
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I => wbone_clk,
RST_I => wbone_rst,
ACK_I => wbone_ack,
DAT_I => wbone_mdin,
ADDR_O => wbone_addr(28 downto 0),
DAT_O => wbone_mdout,
WE_O => wbone_we,
STB_O => wbone_stb,
SEL_O => wbone_sel(0),
CYC_O => wbone_cyc,
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o => wbone_rst
);
Wishbone_mem_large: if (SIMULATION = "TRUE") generate
wb_mem_sim :
wb_mem
generic map(
AWIDTH => 16,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
Wishbone_mem_sample: if (SIMULATION = "FALSE") generate
wb_mem_syn :
wb_mem
generic map(
AWIDTH => 7,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
--temporary clock assignment
wbone_clk <= ddr_ui_clk;
ddr_inclk_bufgds : IBUFGDS
generic map(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE
)
port map(
O => ddr_sys_clk_i,
I => ddr_sys_clk_p,
IB => ddr_sys_clk_n
);
ddr_sys_rst_i <= wbone_rst;
end architecture;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/rx_dsDMA_Channel.vhd
|
1
|
25924
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: dsDMA_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.30 - DMA engine divided into 2 modules: calculation and FSM. 26.07.2007
--
-- Revision 1.20 - DMA engine shared out. 12.02.2007
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity dsDMA_Transact is
port (
-- downstream DMA Channel Buffer
MRd_dsp_Req : out std_logic;
MRd_dsp_RE : in std_logic;
MRd_dsp_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Downstream reset from MWr channel
dsDMA_Channel_Rst : in std_logic;
-- Downstream Registers from MWr Channel
DMA_ds_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : in std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : in std_logic;
dsBDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : in std_logic;
dsLeng_Lo7b_True : in std_logic;
-- from Cpl/D channel
dsDMA_dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Control Signals from MWr Channel
dsDMA_Start : in std_logic; -- out of 1st dex
dsDMA_Stop : in std_logic; -- out of 1st dex
-- Downstream Control Signals from CplD Channel
dsDMA_Start2 : in std_logic; -- out of consecutive dex
dsDMA_Stop2 : in std_logic; -- out of consecutive dex
-- Downstream DMA Acknowledge to the start command
DMA_Cmd_Ack : out std_logic;
-- Downstream Handshake Signals with CplD Channel for Busy/Done
Tag_Map_Clear : in std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
FC_pop : in std_logic;
-- Downstream tRAM port A write request
tRAM_weB : out std_logic;
tRAM_AddrB : out std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : out std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- To Interrupt module
DMA_Done : out std_logic;
DMA_TimeOut : out std_logic;
DMA_Busy : out std_logic;
-- To Tx Port
DMA_ds_Status : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : in std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- Common ports
user_clk : in std_logic
);
end entity dsDMA_Transact;
architecture Behavioral of dsDMA_Transact is
signal FC_push : std_logic;
signal FC_counter : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal dsFC_stop : std_logic;
signal dsFC_stop_128B : std_logic;
signal dsFC_stop_256B : std_logic;
signal dsFC_stop_512B : std_logic;
signal dsFC_stop_1024B : std_logic;
signal dsFC_stop_2048B : std_logic;
signal dsFC_stop_4096B : std_logic;
-- Reset
signal Local_Reset_i : std_logic;
signal Local_Reset_n_i : std_logic;
signal cfg_MRS : std_logic_vector(C_CFG_MRS_BIT_TOP-C_CFG_MRS_BIT_BOT downto 0);
-- Tag RAM port B write
signal tRAM_dinB_i : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_AddrB_i : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_weB_i : std_logic;
-- DMA calculation
component DMA_Calculate
port(
-- Downstream Registers from MWr Channel
DMA_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : in std_logic;
BDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : in std_logic;
Leng_Lo7b_True : in std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : out std_logic;
-- Only for downstream channel
DMA_PA_Snout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : out std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
--
DMA_Snout_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Engine control signals
DMA_Start : in std_logic;
DMA_Start2 : in std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : out std_logic;
ThereIs_Snout : out std_logic;
ThereIs_Body : out std_logic;
ThereIs_Tail : out std_logic;
ThereIs_Dex : out std_logic;
HA64bit : out std_logic;
Addr_Inc : out std_logic;
-- FSM indicators
State_Is_LoadParam : in std_logic;
State_Is_Snout : in std_logic;
State_Is_Body : in std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : in std_logic_vector(2 downto 0);
-- Common ports
dma_clk : in std_logic;
dma_reset : in std_logic
);
end component;
signal dsDMA_PA_Loaded : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_PA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_HA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_BDA_fsm : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsBDA_is_64b_fsm : std_logic;
signal dsDMA_PA_snout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_BAR_Number : std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
signal dsDMA_Snout_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal dsDMA_Body_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal dsDMA_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal dsNo_More_Bodies : std_logic;
signal dsThereIs_Snout : std_logic;
signal dsThereIs_Body : std_logic;
signal dsThereIs_Tail : std_logic;
signal dsThereIs_Dex : std_logic;
signal dsHA64bit : std_logic;
signal ds_AInc : std_logic;
-- DMA state machine
component DMA_FSM
port(
-- Fixed information for 1st header of TLP: MRd/MWr
TLP_Has_Payload : in std_logic;
TLP_Hdr_is_4DW : in std_logic;
DMA_Addr_Inc : in std_logic;
DMA_BAR_Number : in std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
-- FSM control signals
DMA_Start : in std_logic;
DMA_Start2 : in std_logic;
DMA_Stop : in std_logic;
DMA_Stop2 : in std_logic;
No_More_Bodies : in std_logic;
ThereIs_Snout : in std_logic;
ThereIs_Body : in std_logic;
ThereIs_Tail : in std_logic;
ThereIs_Dex : in std_logic;
-- Parameters to be written into ChBuf
DMA_PA_Loaded : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : in std_logic;
DMA_Snout_Length : in std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : in std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Busy/Done conditions
Done_Condition_1 : in std_logic;
Done_Condition_2 : in std_logic;
Done_Condition_3 : in std_logic;
Done_Condition_4 : in std_logic;
Done_Condition_5 : in std_logic;
-- Channel buffer write
us_MWr_Param_Vec : in std_logic_vector(6-1 downto 0);
ChBuf_aFull : in std_logic;
ChBuf_WrEn : out std_logic;
ChBuf_WrDin : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FSM indicators
State_Is_LoadParam : out std_logic;
State_Is_Snout : out std_logic;
State_Is_Body : out std_logic;
State_Is_Tail : out std_logic;
DMA_Cmd_Ack : out std_logic;
-- To Tx Port
ChBuf_ValidRd : in std_logic;
BDA_nAligned : out std_logic;
DMA_TimeOut : out std_logic;
DMA_Busy : out std_logic;
DMA_Done : out std_logic;
-- DMA_Done_Rise : OUT std_logic;
-- Tags
Pkt_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
Dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Common ports
dma_clk : in std_logic;
dma_reset : in std_logic
);
end component;
signal Tag_DMA_dsp : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- FSM state indicators
signal dsState_Is_LoadParam : std_logic;
signal dsState_Is_Snout : std_logic;
signal dsState_Is_Body : std_logic;
signal dsState_Is_Tail : std_logic;
signal dsChBuf_ValidRd : std_logic;
signal dsBDA_nAligned : std_logic;
signal dsDMA_TimeOut_i : std_logic;
signal dsDMA_Busy_i : std_logic;
signal dsDMA_Done_i : std_logic;
signal DMA_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
---------------------------------------------------------------
-- Done state identification uses 2^C_TAGRAM_AWIDTH bits, 2 stages logic
signal Tag_Map_Bits : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal Tag_Map_filling : std_logic_vector(C_SUB_TAG_MAP_WIDTH-1 downto 0);
signal All_CplD_have_come : std_logic;
-- Built-in single-port fifo as downstream DMA channel buffer
-- 128-bit wide, for 64-bit address
component sfifo_15x128
port (
clk : in std_logic;
rst : in std_logic;
prog_full : out std_logic;
-- wr_clk : IN std_logic;
wr_en : in std_logic;
din : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
full : out std_logic;
-- rd_clk : IN std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
prog_empty : out std_logic;
empty : out std_logic
);
end component;
-- Signal with DMA_downstream channel FIFO
signal MRd_dsp_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal MRd_dsp_dout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal MRd_dsp_re_i : std_logic;
signal MRd_dsp_we : std_logic;
signal MRd_dsp_empty_i : std_logic;
signal MRd_dsp_full : std_logic;
signal MRd_dsp_prog_Full : std_logic;
signal MRd_dsp_prog_Full_r1 : std_logic;
signal MRd_dsp_re_r1 : std_logic;
signal MRd_dsp_empty_r1 : std_logic;
-- Request for output arbitration
signal MRd_dsp_Req_i : std_logic;
begin
-- DMA done signal
DMA_Done <= dsDMA_Done_i;
DMA_TimeOut <= dsDMA_TimeOut_i;
DMA_Busy <= dsDMA_Busy_i;
-- connecting FIFO's signals
MRd_dsp_Qout <= MRd_dsp_dout;
MRd_dsp_re_i <= MRd_dsp_RE;
MRd_dsp_Req <= MRd_dsp_Req_i;
-- tag RAM write request signals
tRAM_weB <= tRAM_weB_i;
tRAM_AddrB <= tRAM_AddrB_i;
tRAM_dinB <= tRAM_dinB_i;
-- positive local reset
Local_Reset_i <= dsDMA_Channel_Rst;
Local_Reset_n_i <= not(Local_Reset_i);
-- Max Read Request Size bits
cfg_MRS <= cfg_dcommand(C_CFG_MRS_BIT_TOP downto C_CFG_MRS_BIT_BOT);
-- Kernel Engine
ds_DMA_Calculation :
DMA_Calculate
port map(
DMA_PA => DMA_ds_PA ,
DMA_HA => DMA_ds_HA ,
DMA_BDA => DMA_ds_BDA ,
DMA_Length => DMA_ds_Length ,
DMA_Control => DMA_ds_Control ,
HA_is_64b => dsHA_is_64b ,
BDA_is_64b => dsBDA_is_64b ,
Leng_Hi19b_True => dsLeng_Hi19b_True ,
Leng_Lo7b_True => dsLeng_Lo7b_True ,
DMA_PA_Loaded => dsDMA_PA_Loaded ,
DMA_PA_Var => dsDMA_PA_Var ,
DMA_HA_Var => dsDMA_HA_Var ,
DMA_BDA_fsm => dsDMA_BDA_fsm ,
BDA_is_64b_fsm => dsBDA_is_64b_fsm ,
-- Only for downstream channel
DMA_PA_Snout => dsDMA_PA_snout ,
DMA_BAR_Number => dsDMA_BAR_Number ,
-- Lengths
DMA_Snout_Length => dsDMA_Snout_Length ,
DMA_Body_Length => dsDMA_Body_Length ,
DMA_Tail_Length => dsDMA_Tail_Length ,
-- Control signals to FSM
No_More_Bodies => dsNo_More_Bodies ,
ThereIs_Snout => dsThereIs_Snout ,
ThereIs_Body => dsThereIs_Body ,
ThereIs_Tail => dsThereIs_Tail ,
ThereIs_Dex => dsThereIs_Dex ,
HA64bit => dsHA64bit ,
Addr_Inc => ds_AInc ,
DMA_Start => dsDMA_Start ,
DMA_Start2 => dsDMA_Start2 ,
State_Is_LoadParam => dsState_Is_LoadParam ,
State_Is_Snout => dsState_Is_Snout ,
State_Is_Body => dsState_Is_Body ,
-- State_Is_Tail => dsState_Is_Tail ,
Param_Max_Cfg => cfg_MRS ,
dma_clk => user_clk ,
dma_reset => Local_Reset_i
);
-- Kernel FSM
ds_DMA_StateMachine :
DMA_FSM
port map(
TLP_Has_Payload => '0' ,
TLP_Hdr_is_4DW => dsHA64bit ,
DMA_Addr_Inc => '0' , -- of any value
DMA_BAR_Number => dsDMA_BAR_Number ,
DMA_Start => dsDMA_Start ,
DMA_Start2 => dsDMA_Start2 ,
DMA_Stop => dsDMA_Stop ,
DMA_Stop2 => dsDMA_Stop2 ,
-- Control signals to FSM
No_More_Bodies => dsNo_More_Bodies ,
ThereIs_Snout => dsThereIs_Snout ,
ThereIs_Body => dsThereIs_Body ,
ThereIs_Tail => dsThereIs_Tail ,
ThereIs_Dex => dsThereIs_Dex ,
DMA_PA_Loaded => dsDMA_PA_Loaded ,
DMA_PA_Var => dsDMA_PA_Var ,
DMA_HA_Var => dsDMA_HA_Var ,
DMA_BDA_fsm => dsDMA_BDA_fsm ,
BDA_is_64b_fsm => dsBDA_is_64b_fsm ,
DMA_Snout_Length => dsDMA_Snout_Length ,
DMA_Body_Length => dsDMA_Body_Length ,
DMA_Tail_Length => dsDMA_Tail_Length ,
ChBuf_ValidRd => dsChBuf_ValidRd,
BDA_nAligned => dsBDA_nAligned ,
DMA_TimeOut => dsDMA_TimeOut_i,
DMA_Busy => dsDMA_Busy_i ,
DMA_Done => dsDMA_Done_i ,
-- DMA_Done_Rise => open ,
Pkt_Tag => Tag_DMA_dsp ,
Dex_Tag => dsDMA_dex_Tag ,
Done_Condition_1 => '1' ,
Done_Condition_2 => MRd_dsp_empty_r1 ,
Done_Condition_3 => '1' ,
Done_Condition_4 => '1' ,
Done_Condition_5 => All_CplD_have_come ,
us_MWr_Param_Vec => "000000" ,
ChBuf_aFull => MRd_dsp_prog_Full_r1 ,
ChBuf_WrEn => MRd_dsp_we ,
ChBuf_WrDin => MRd_dsp_din ,
State_Is_LoadParam => dsState_Is_LoadParam ,
State_Is_Snout => dsState_Is_Snout ,
State_Is_Body => dsState_Is_Body ,
State_Is_Tail => dsState_Is_Tail ,
DMA_Cmd_Ack => DMA_Cmd_Ack ,
dma_clk => user_clk ,
dma_reset => Local_Reset_i
);
dsChBuf_ValidRd <= MRd_dsp_RE; -- MRd_dsp_re_i and not MRd_dsp_empty_i;
-- -------------------------------------------------
--
DMA_ds_Status <= DMA_Status_i;
--
-- Synchronous output: DMA_Status
--
DS_DMA_Status_Concat :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DMA_Status_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
DMA_Status_i <= (
CINT_BIT_DMA_STAT_NALIGN => dsBDA_nAligned,
CINT_BIT_DMA_STAT_TIMEOUT => dsDMA_TimeOut_i,
CINT_BIT_DMA_STAT_BDANULL => dsDMA_BDA_eq_Null,
CINT_BIT_DMA_STAT_BUSY => dsDMA_Busy_i,
CINT_BIT_DMA_STAT_DONE => dsDMA_Done_i,
others => '0'
);
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: tRAM_weB
-- tRAM_AddrB
-- tRAM_dinB
--
FSM_dsDMA_tRAM_PortB :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_weB_i <= '0';
tRAM_AddrB_i <= (others => '1');
tRAM_dinB_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
tRAM_AddrB_i <= Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_weB_i <= dsState_Is_Snout
or dsState_Is_Body
or dsState_Is_Tail;
if dsState_Is_Snout = '1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_snout(C_TAGBAR_BIT_BOT-1 downto 2)&"00";
elsif dsState_Is_Body = '1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_Var(C_TAGBAR_BIT_BOT-1 downto 2) &"00";
elsif dsState_Is_Tail = '1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_Var(C_TAGBAR_BIT_BOT-1 downto 2) &"00";
else
tRAM_dinB_i <= (others => '0');
end if;
end if;
end process;
-- ------------------------------------------
-- Loop: Tag_Map
--
Sync_Tag_set_reset_Bits :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_Bits <= (others => '0');
elsif user_clk'event and user_clk = '1' then
for j in 0 to C_TAG_MAP_WIDTH-1 loop
if tRAM_AddrB_i = CONV_STD_LOGIC_VECTOR(j, C_TAGRAM_AWIDTH) and tRAM_weB_i = '1' then
Tag_Map_Bits(j) <= '1';
elsif Tag_Map_Clear(j) = '1' then
Tag_Map_Bits(j) <= '0';
else
Tag_Map_Bits(j) <= Tag_Map_Bits(j);
end if;
end loop;
end if;
end process;
-- ------------------------------------------
-- Determination: All_CplD_have_come
--
Sync_Reg_All_CplD_have_come :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_filling <= (others => '0');
All_CplD_have_come <= '0';
elsif user_clk'event and user_clk = '1' then
for k in 0 to C_SUB_TAG_MAP_WIDTH-1 loop
if Tag_Map_Bits((C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*(k+1)-1 downto (C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*k)
= C_ALL_ZEROS((C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*(k+1)-1 downto (C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*k)
then
Tag_Map_filling(k) <= '1';
else
Tag_Map_filling(k) <= '0';
end if;
end loop;
-- final signal : All_CplD_have_come
if Tag_Map_filling = C_ALL_ONES(C_SUB_TAG_MAP_WIDTH-1 downto 0) then
All_CplD_have_come <= '1';
else
All_CplD_have_come <= '0';
end if;
end if;
end process;
-- ------------------------------------------
-- Synchronous Output: Tag_DMA_dsp
--
FSM_dsDMA_Tag_DMA_dsp :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_DMA_dsp <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if dsState_Is_Snout = '1'
or dsState_Is_Body = '1'
or dsState_Is_Tail = '1'
then
Tag_DMA_dsp <= '0' & dsDMA_BAR_Number(CINT_FIFO_SPACE_BAR/2)
& (Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(1, C_TAGRAM_AWIDTH));
else
Tag_DMA_dsp <= '0' & dsDMA_BAR_Number(CINT_FIFO_SPACE_BAR/2)
& Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0);
end if;
end if;
end process;
-- -------------------------------------------------
-- ds MRd TLP Buffer
-- -------------------------------------------------
DMA_DSP_Buffer :
generic_sync_fifo
generic map (
g_data_width => 128,
g_size => 16,
g_show_ahead => false,
g_with_empty => true,
g_with_full => false,
g_with_almost_empty => true,
g_with_almost_full => true,
g_with_count => false,
g_almost_empty_threshold => 3,
g_almost_full_threshold => 13)
port map (
rst_n_i => Local_Reset_n_i,
clk_i => user_clk,
d_i => MRd_dsp_din,
we_i => MRd_dsp_we,
q_o => MRd_dsp_dout,
rd_i => MRd_dsp_re_i,
empty_o => MRd_dsp_empty_i,
full_o => MRd_dsp_full,
almost_empty_o => open,
almost_full_o => MRd_dsp_prog_Full,
count_o => open);
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
MRd_dsp_re_r1 <= MRd_dsp_re_i;
MRd_dsp_empty_r1 <= MRd_dsp_empty_i;
MRd_dsp_prog_Full_r1 <= MRd_dsp_prog_Full;
MRd_dsp_Req_i <= not MRd_dsp_empty_i
and not dsDMA_Stop
and not dsDMA_Stop2
and not dsFC_stop;
end if;
end process;
-- ------------------------------------------
-- Synchronous: FC_push
--
Synch_Calc_FC_push :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_push <= '0';
elsif user_clk'event and user_clk = '1' then
FC_push <= MRd_dsp_re_r1 and not MRd_dsp_empty_r1
and not MRd_dsp_dout(C_CHBUF_TAG_BIT_TOP);
end if;
end process;
-- ------------------------------------------
-- Synchronous: FC_counter
--
Synch_Calc_FC_counter :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_counter <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if FC_push = '1' and FC_pop = '0' then
FC_counter <= FC_counter + '1';
elsif FC_push = '0' and FC_pop = '1' then
FC_counter <= FC_counter - '1';
else
FC_counter <= FC_counter;
end if;
end if;
end process;
-- ------------------------------------------
-- Synchronous: dsFC_stop
--
Synch_Calc_dsFC_stop :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
dsFC_stop_128B <= '1';
dsFC_stop_256B <= '1';
dsFC_stop_512B <= '1';
dsFC_stop_1024B <= '1';
dsFC_stop_2048B <= '1';
dsFC_stop_4096B <= '1';
elsif user_clk'event and user_clk = '1' then
if FC_counter(C_TAGRAM_AWIDTH-1 downto 0) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 0) then
dsFC_stop_4096B <= '1';
else
dsFC_stop_4096B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 0) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 0) then
dsFC_stop_2048B <= '1';
else
dsFC_stop_2048B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 1) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 1) then
dsFC_stop_1024B <= '1';
else
dsFC_stop_1024B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 2) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 2) then
dsFC_stop_512B <= '1';
else
dsFC_stop_512B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 3) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 3) then
dsFC_stop_256B <= '1';
else
dsFC_stop_256B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 4) /= C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 4) then
dsFC_stop_128B <= '1';
else
dsFC_stop_128B <= '0';
end if;
end if;
end process;
-- ------------------------------------------
-- Configuration pamameters: cfg_MRS
--
Syn_Config_Param_cfg_MRS :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then -- 0x0080 Bytes
dsFC_stop <= '1';
elsif user_clk'event and user_clk = '1' then
case cfg_MRS is
when "000" => -- 0x0080 Bytes
dsFC_stop <= dsFC_stop_128B;
when "001" => -- 0x0100 Bytes
dsFC_stop <= dsFC_stop_256B;
when "010" => -- 0x0200 Bytes
dsFC_stop <= dsFC_stop_512B;
when "011" => -- 0x0400 Bytes
dsFC_stop <= dsFC_stop_1024B;
when "100" => -- 0x0800 Bytes
dsFC_stop <= dsFC_stop_2048B;
when "101" => -- 0x1000 Bytes
dsFC_stop <= dsFC_stop_4096B;
when others => -- as 0x0080 Bytes
dsFC_stop <= dsFC_stop_128B;
end case;
end if;
end process;
end architecture Behavioral;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_mach.vhd
|
1
|
16673
|
--*****************************************************************************
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : rank_mach.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Top level rank machine structural block. This block
-- instantiates a configurable number of rank controller blocks.
entity rank_mach is
generic (
BURST_MODE : string := "8";
CS_WIDTH : integer := 4;
DRAM_TYPE : string := "DDR3";
MAINT_PRESCALER_DIV : integer := 40;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
CL : integer := 5;
nFAW : integer := 30;
nREFRESH_BANK : integer := 8;
nRRD : integer := 4;
nWTR : integer := 4;
PERIODIC_RD_TIMER_DIV : integer := 20;
RANK_BM_BV_WIDTH : integer := 16;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
PHASE_DETECT : string := "OFF"; --Added to control periodic reads
REFRESH_TIMER_DIV : integer := 39;
ZQ_TIMER_DIV : integer := 640000
);
port (
-- Outputs
-- Inputs
-- Beginning of automatic inputs (from unused autoinst inputs)
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_common0 of rank_common.v
-- To rank_cntrl0 of rank_cntrl.v, ...
-- To rank_cntrl0 of rank_cntrl.v, ...
-- To rank_cntrl0 of rank_cntrl.v, ...
-- To rank_common0 of rank_common.v
-- To rank_common0 of rank_common.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v, ...
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_common0 of rank_common.v
-- To rank_common0 of rank_common.v
-- To rank_cntrl0 of rank_cntrl.v
-- End of automatics
-- Beginning of automatic outputs (from unused autoinst outputs)
-- From rank_common0 of rank_common.v
-- From rank_common0 of rank_common.v
periodic_rd_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0); -- From rank_common0 of rank_common.v
periodic_rd_r : out std_logic;
maint_req_r : out std_logic;
-- End of automatics
-- Beginning of automatic wires (for undeclared instantiated-module outputs)
-- From rank_common0 of rank_common.v
-- From rank_common0 of rank_common.v
-- End of automatics
inhbt_act_faw_r : out std_logic_vector(RANKS - 1 downto 0);
inhbt_rd_r : out std_logic_vector(RANKS - 1 downto 0);
wtr_inhbt_config_r : out std_logic_vector(RANKS - 1 downto 0);
maint_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
maint_zq_r : out std_logic;
wr_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
slot_0_present : in std_logic_vector(7 downto 0);
sending_row : in std_logic_vector(nBANK_MACHS - 1 downto 0);
sending_col : in std_logic_vector(nBANK_MACHS - 1 downto 0);
rst : in std_logic;
rd_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
rank_busy_r : in std_logic_vector((RANKS * nBANK_MACHS) - 1 downto 0);
periodic_rd_ack_r : in std_logic;
maint_wip_r : in std_logic;
insert_maint_r1 : in std_logic;
dfi_init_complete : in std_logic;
clk : in std_logic;
app_zq_req : in std_logic;
app_ref_req : in std_logic;
app_periodic_rd_req : in std_logic;
act_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0)
);
end entity rank_mach;
architecture trans of rank_mach is
component rank_cntrl is
generic (
TCQ : integer := 100;
BURST_MODE : string := "8";
ID : integer := 0;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
CL : integer := 5;
nFAW : integer := 30;
nREFRESH_BANK : integer := 8;
nRRD : integer := 4;
nWTR : integer := 4;
PERIODIC_RD_TIMER_DIV : integer := 20;
RANK_BM_BV_WIDTH : integer := 16;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
PHASE_DETECT : string := "OFF";
REFRESH_TIMER_DIV : integer := 39
);
port (
inhbt_act_faw_r : out std_logic;
inhbt_rd_r : out std_logic;
wtr_inhbt_config_r : out std_logic;
refresh_request : out std_logic;
periodic_rd_request : out std_logic;
clk : in std_logic;
rst : in std_logic;
sending_row : in std_logic_vector(nBANK_MACHS - 1 downto 0);
act_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
sending_col : in std_logic_vector(nBANK_MACHS - 1 downto 0);
wr_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
app_ref_req : in std_logic;
dfi_init_complete : in std_logic;
rank_busy_r : in std_logic_vector((RANKS * nBANK_MACHS) - 1 downto 0);
refresh_tick : in std_logic;
insert_maint_r1 : in std_logic;
maint_zq_r : in std_logic;
maint_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
app_periodic_rd_req : in std_logic;
maint_prescaler_tick_r : in std_logic;
clear_periodic_rd_request : in std_logic;
rd_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0)
);
end component;
component rank_common is
generic (
TCQ : integer := 100;
DRAM_TYPE : string := "DDR3";
MAINT_PRESCALER_DIV : integer := 40;
nBANK_MACHS : integer := 4;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
REFRESH_TIMER_DIV : integer := 39;
ZQ_TIMER_DIV : integer := 640000
);
port (
maint_prescaler_tick_r : out std_logic;
refresh_tick : out std_logic;
maint_zq_r : out std_logic;
maint_req_r : out std_logic;
maint_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
clear_periodic_rd_request : out std_logic_vector(RANKS - 1 downto 0);
periodic_rd_r : out std_logic;
periodic_rd_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
dfi_init_complete : in std_logic;
app_zq_req : in std_logic;
insert_maint_r1 : in std_logic;
refresh_request : in std_logic_vector(RANKS - 1 downto 0);
maint_wip_r : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
periodic_rd_request : in std_logic_vector(RANKS - 1 downto 0);
periodic_rd_ack_r : in std_logic
);
end component;
signal maint_prescaler_tick_r : std_logic;
signal refresh_tick : std_logic;
signal refresh_request : std_logic_vector(RANKS - 1 downto 0);
signal periodic_rd_request : std_logic_vector(RANKS - 1 downto 0);
signal clear_periodic_rd_request : std_logic_vector(RANKS - 1 downto 0);
-- Declare intermediate signals for referenced outputs
signal periodic_rd_rank_r_int6 : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal periodic_rd_r_int5 : std_logic;
signal maint_req_r_int3 : std_logic;
signal inhbt_act_faw_r_int0 : std_logic_vector(RANKS - 1 downto 0);
signal inhbt_rd_r_int1 : std_logic_vector(RANKS - 1 downto 0);
signal wtr_inhbt_config_r_int7 : std_logic_vector(RANKS - 1 downto 0);
signal maint_rank_r_int2 : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal maint_zq_r_int4 : std_logic;
begin
-- Drive referenced outputs
periodic_rd_rank_r <= periodic_rd_rank_r_int6;
periodic_rd_r <= periodic_rd_r_int5;
maint_req_r <= maint_req_r_int3;
inhbt_act_faw_r <= inhbt_act_faw_r_int0;
inhbt_rd_r <= inhbt_rd_r_int1;
wtr_inhbt_config_r <= wtr_inhbt_config_r_int7;
maint_rank_r <= maint_rank_r_int2;
maint_zq_r <= maint_zq_r_int4;
rank_cntrl_inst : for ID in 0 to RANKS - 1 generate
-- Parameters
rank_cntrl0 : rank_cntrl
generic map (
BURST_MODE => BURST_MODE,
ID => ID,
nBANK_MACHS => nBANK_MACHS,
nCK_PER_CLK => nCK_PER_CLK,
CL => CL,
nFAW => nFAW,
nREFRESH_BANK => nREFRESH_BANK,
nRRD => nRRD,
nWTR => nWTR,
PERIODIC_RD_TIMER_DIV => PERIODIC_RD_TIMER_DIV,
RANK_BM_BV_WIDTH => RANK_BM_BV_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
PHASE_DETECT => PHASE_DETECT,
REFRESH_TIMER_DIV => REFRESH_TIMER_DIV
)
port map (
clear_periodic_rd_request => clear_periodic_rd_request(ID),
inhbt_act_faw_r => inhbt_act_faw_r_int0(ID),
inhbt_rd_r => inhbt_rd_r_int1(ID),
periodic_rd_request => periodic_rd_request(ID),
refresh_request => refresh_request(ID),
wtr_inhbt_config_r => wtr_inhbt_config_r_int7(ID),
-- Inputs
clk => clk,
rst => rst,
sending_row => sending_row(nBANK_MACHS - 1 downto 0),
act_this_rank_r => act_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
sending_col => sending_col(nBANK_MACHS - 1 downto 0),
wr_this_rank_r => wr_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
app_ref_req => app_ref_req,
dfi_init_complete => dfi_init_complete,
rank_busy_r => rank_busy_r((RANKS * nBANK_MACHS) - 1 downto 0),
refresh_tick => refresh_tick,
insert_maint_r1 => insert_maint_r1,
maint_zq_r => maint_zq_r_int4,
maint_rank_r => maint_rank_r_int2(RANK_WIDTH - 1 downto 0),
app_periodic_rd_req => app_periodic_rd_req,
maint_prescaler_tick_r => maint_prescaler_tick_r,
rd_this_rank_r => rd_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0)
);
end generate;
-- Parameters
rank_common0 : rank_common
generic map (
DRAM_TYPE => DRAM_TYPE,
MAINT_PRESCALER_DIV => MAINT_PRESCALER_DIV,
nBANK_MACHS => nBANK_MACHS,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
REFRESH_TIMER_DIV => REFRESH_TIMER_DIV,
ZQ_TIMER_DIV => ZQ_TIMER_DIV
)
port map (
clear_periodic_rd_request => clear_periodic_rd_request(RANKS - 1 downto 0),
-- Outputs
maint_prescaler_tick_r => maint_prescaler_tick_r,
refresh_tick => refresh_tick,
maint_zq_r => maint_zq_r_int4,
maint_req_r => maint_req_r_int3,
maint_rank_r => maint_rank_r_int2(RANK_WIDTH - 1 downto 0),
periodic_rd_r => periodic_rd_r_int5,
periodic_rd_rank_r => periodic_rd_rank_r_int6(RANK_WIDTH - 1 downto 0),
-- Inputs
clk => clk,
rst => rst,
dfi_init_complete => dfi_init_complete,
app_zq_req => app_zq_req,
insert_maint_r1 => insert_maint_r1,
refresh_request => refresh_request(RANKS - 1 downto 0),
maint_wip_r => maint_wip_r,
slot_0_present => slot_0_present(7 downto 0),
slot_1_present => slot_1_present(7 downto 0),
periodic_rd_request => periodic_rd_request(RANKS - 1 downto 0),
periodic_rd_ack_r => periodic_rd_ack_r
);
end architecture trans;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/bpm_pcie_ml605.vhd
|
1
|
55209
|
----------------------------------------------------------------------------------
-- Company: Creotech
-- Engineer: Adrian Byszuk ([email protected])
--
-- Design Name:
-- Module Name: bpm_pcie_ml605 - Behavioral
-- Project Name:
-- Target Devices: XC7A200T on AC uTCA card from OHWR
-- Tool versions: ISE 14.4, ISE 14.6
-- Description: This is TOP module for the versatile firmware for PCIe communication.
-- It provides DMA engine with scatter-gather (linked list) functionality.
-- DDR memory is supported through BAR1. Wishbone endpoint is accessible through BAR2.
--
-- Dependencies: Xilinx PCIe core for 7 series. Xilinx DDR core for 7 series.
--
-- Revision: 2.00 - Original file completely rewritten by abyszuk.
--
-- Revision 1.00 - File Released
--
-- Additional Comments: This file can be used both as TOP module for independent operation, or
-- instantiated in another projects. To use it in your project, change INSTANTIATED generic to
-- "TRUE" and uncomment relevant interface sections in entity declaration. ATTENTION: you also
-- have to comment out dummy signal with names exactly the same as port names (it was necessary so
-- that XST won't complain about missing signal names).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bpm_pcie_ml605 is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1;
SIM_BYPASS_INIT_CAL : string := "FAST"
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
---- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic
);
end entity bpm_pcie_ml605;
architecture Behavioral of bpm_pcie_ml605 is
constant DDR_ADDR_WIDTH : integer := 28;
component pcie_core
generic (
PL_FAST_TRAIN : string := "FALSE";
UPSTREAM_FACING : string := "TRUE"
);
port (
-------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
-------------------------------------------------------------------------------------------------------------------
pci_exp_txp : out std_logic_vector(3 downto 0);
pci_exp_txn : out std_logic_vector(3 downto 0);
pci_exp_rxp : in std_logic_vector(3 downto 0);
pci_exp_rxn : in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 2. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out : out std_logic;
user_reset_out : out std_logic;
user_lnk_up : out std_logic;
-- TX
tx_buf_av : out std_logic_vector(5 downto 0);
tx_cfg_req : out std_logic;
tx_err_drop : out std_logic;
s_axis_tx_tready : out std_logic;
s_axis_tx_tdata : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);
s_axis_tx_tkeep : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
s_axis_tx_tlast : in std_logic;
s_axis_tx_tvalid : in std_logic;
s_axis_tx_tuser : in std_logic_vector(3 downto 0);
tx_cfg_gnt : in std_logic;
-- RX
m_axis_rx_tdata : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);
m_axis_rx_tkeep : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
m_axis_rx_tlast : out std_logic;
m_axis_rx_tvalid : out std_logic;
m_axis_rx_tready : in std_logic;
m_axis_rx_tuser : out std_logic_vector(21 downto 0);
rx_np_ok : in std_logic;
-- Flow Control
fc_cpld : out std_logic_vector(11 downto 0);
fc_cplh : out std_logic_vector(7 downto 0);
fc_npd : out std_logic_vector(11 downto 0);
fc_nph : out std_logic_vector(7 downto 0);
fc_pd : out std_logic_vector(11 downto 0);
fc_ph : out std_logic_vector(7 downto 0);
fc_sel : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 3. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
cfg_di : in std_logic_vector(31 downto 0);
cfg_byte_en : in std_logic_vector(3 downto 0);
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_wr_en : in std_logic;
cfg_rd_en : in std_logic;
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
cfg_dcommand2 : out std_logic_vector(15 downto 0);
cfg_pcie_link_state : out std_logic_vector(2 downto 0);
cfg_pmcsr_pme_en : out std_logic;
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
cfg_pmcsr_pme_status : out std_logic;
-- Error Reporting Interface
cfg_err_ecrc : in std_logic;
cfg_err_ur : in std_logic;
cfg_err_cpl_timeout : in std_logic;
cfg_err_cpl_unexpect : in std_logic;
cfg_err_cpl_abort : in std_logic;
cfg_err_posted : in std_logic;
cfg_err_cor : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy : out std_logic;
cfg_err_locked : in std_logic;
cfg_trn_pending : in std_logic;
cfg_dsn : std_logic_vector(63 downto 0);
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt : in std_logic;
cfg_interrupt_rdy : out std_logic;
cfg_interrupt_assert : in std_logic;
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_interrupt_msixenable : out std_logic;
cfg_interrupt_msixfm : out std_logic;
cfg_to_turnoff : out std_logic;
cfg_turnoff_ok : in std_logic;
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_pm_wake : in std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 4. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_change : in std_logic_vector(1 downto 0);
pl_directed_link_width : in std_logic_vector(1 downto 0);
pl_directed_link_speed : in std_logic;
pl_directed_link_auton : in std_logic;
pl_upstream_prefer_deemph : in std_logic;
pl_ltssm_state : out std_logic_vector(5 downto 0);
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
pl_link_partner_gen2_supported : out std_logic;
pl_initial_link_width : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 6. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
sys_clk : in std_logic;
sys_reset : in std_logic);
end component;
component ddr_v6
generic(
SIM_BYPASS_INIT_CAL : string := "OFF";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Skip memory init &
-- calibration sequence
-- # = "FAST" - Skip memory init & use
-- abbreviated calib sequence
RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port(
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
sda : inout std_logic;
scl : out std_logic;
app_addr : in std_logic_vector(DDR_ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
ui_clk_sync_rst : out std_logic;
ui_clk : out std_logic;
phy_init_done : out std_logic;
sys_clk : in std_logic;
clk_ref : in std_logic;
sys_rst : in std_logic
);
end component ddr_v6;
-- -----------------------------------------------------------------------
-- DDR SDRAM control module
-- -----------------------------------------------------------------------
component bram_DDRs_Control_loopback
generic (
C_ASYNFIFO_WIDTH : integer;
P_SIMULATION : boolean
);
port (
DDR_wr_sof : in std_logic;
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_sof : in std_logic;
DDR_rdc_eof : in std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : out std_logic;
DDR_Blinker : out std_logic;
mem_clk : in std_logic;
user_clk : in std_logic;
Sim_Zeichen : out std_logic;
user_reset : in std_logic
);
end component;
component DDR_Transact
generic (
SIMULATION : string;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
DDR_UI_DATAWIDTH : integer;
DDR_DQ_WIDTH : integer;
DEVICE_TYPE : string -- "VIRTEX6"
-- "KINTEX7"
-- "ARTIX7"
);
port (
--ext logic interface to memory core
-- memory controller interface --
memc_ui_clk : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_UI_DATAWIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_UI_DATAWIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_UI_DATAWIDTH-1 downto 0);
memc_rd_valid : out std_logic;
-- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ext logic interface
-- PCIE interface
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--/PCIE interface
-- Common interface
DDR_Ready : out std_logic;
-- DDR core UI
app_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : out std_logic_vector(2 downto 0);
app_en : out std_logic;
app_wdf_data : out std_logic_vector((DDR_UI_DATAWIDTH)-1 downto 0);
app_wdf_end : out std_logic;
app_wdf_mask : out std_logic_vector((DDR_UI_DATAWIDTH)/8-1 downto 0);
app_wdf_wren : out std_logic;
app_rd_data : in std_logic_vector((DDR_UI_DATAWIDTH)-1 downto 0);
app_rd_data_end : in std_logic;
app_rd_data_valid : in std_logic;
app_rdy : in std_logic;
app_wdf_rdy : in std_logic;
ui_clk : in std_logic;
ui_clk_sync_rst : in std_logic;
init_calib_complete : in std_logic;
--clocking & reset
user_clk : in std_logic;
user_reset : in std_logic
);
end component;
signal DDR_wr_sof : std_logic;
signal DDR_wr_eof : std_logic;
signal DDR_wr_v : std_logic;
signal DDR_wr_Shift : std_logic;
signal DDR_wr_Mask : std_logic_vector(2-1 downto 0);
signal DDR_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_full : std_logic;
signal DDR_rdc_sof : std_logic;
signal DDR_rdc_eof : std_logic;
signal DDR_rdc_v : std_logic;
signal DDR_rdc_Shift : std_logic;
signal DDR_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_rdc_full : std_logic;
signal DDR_FIFO_RdEn : std_logic;
signal DDR_FIFO_Empty : std_logic;
signal DDR_FIFO_RdQout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_Ready : std_logic;
-- -----------------------------------------------------------------------
-- Wishbone interface module
-- -----------------------------------------------------------------------
component wb_transact is
port (
-- PCIE user clk
user_clk : in std_logic;
-- Write port
wr_we : in std_logic;
wr_sof : in std_logic;
wr_eof : in std_logic;
wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full : out std_logic;
-- Read command port
rdc_sof : in std_logic;
rdc_v : in std_logic;
rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full : out std_logic;
rd_tout : in std_logic;
-- Read data port
rd_ren : in std_logic;
rd_empty : out std_logic;
rd_dout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk : in std_logic;
wb_rst : in std_logic;
addr_o : out std_logic_vector(28 downto 0);
dat_i : in std_logic_vector(63 downto 0);
dat_o : out std_logic_vector(63 downto 0);
we_o : out std_logic;
sel_o : out std_logic_vector(0 downto 0);
stb_o : out std_logic;
ack_i : in std_logic;
cyc_o : out std_logic;
--RESET from PCIe
rst : in std_logic
);
end component;
signal wbone_clk : std_logic;
signal wb_wr_we : std_logic;
signal wb_wr_wsof : std_logic;
signal wb_wr_weof : std_logic;
signal wb_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_wr_pfull : std_logic;
signal wb_wr_full : std_logic;
signal wb_rdc_sof : std_logic;
signal wb_rdc_v : std_logic;
signal wb_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdc_full : std_logic;
signal wb_timeout : std_logic;
signal wb_rdd_ren : std_logic;
signal wb_rdd_dout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdd_pempty : std_logic;
signal wb_rdd_empty : std_logic;
signal wbone_rst : std_logic;
signal wb_fifo_rst : std_logic;
signal wbone_addr : std_logic_vector(28 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
------------- COMPONENT Declaration: tlpControl ------
--
component tlpControl
port (
-- Wishbone interface
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_FIFO_full : in std_logic;
wb_FIFO_Rst : out std_logic;
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
wb_timeout : out std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR control interface
DDR_Ready : in std_logic;
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Transaction layer interface
user_lnk_up : in std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
s_axis_tx_terrfwd : out std_logic;
user_clk : in std_logic;
user_reset : in std_logic;
m_axis_rx_tvalid : in std_logic;
s_axis_tx_tready : in std_logic;
m_axis_rx_tlast : in std_logic;
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
cfg_dcommand : in std_logic_vector(15 downto 0);
pcie_link_width : in std_logic_vector(5 downto 0);
localId : in std_logic_vector(15 downto 0);
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(6 downto 0);
s_axis_tx_tvalid : out std_logic;
m_axis_rx_tready : out std_logic;
s_axis_tx_tlast : out std_logic;
s_axis_tx_tkeep : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
s_axis_tx_tdata : out std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
-- TRN Layer signals
signal tx_err_drop : std_logic;
signal tx_cfg_gnt : std_logic;
signal fc_cpld : std_logic_vector (12-1 downto 0);
signal fc_cplh : std_logic_vector (8-1 downto 0);
signal fc_npd : std_logic_vector (12-1 downto 0);
signal fc_nph : std_logic_vector (8-1 downto 0);
signal fc_pd : std_logic_vector (12-1 downto 0);
signal fc_ph : std_logic_vector (8-1 downto 0);
signal fc_sel : std_logic_vector (3-1 downto 0);
signal cfg_dcommand2 : std_logic_vector (16-1 downto 0);
signal tx_cfg_req : std_logic;
signal pl_initial_link_width : std_logic_vector (3-1 downto 0);
signal pl_lane_reversal_mode : std_logic_vector (2-1 downto 0);
signal pl_link_partner_gen2_supported : std_logic;
signal pl_received_hot_rst : std_logic;
signal pl_directed_link_auton : std_logic;
signal pl_directed_link_change : std_logic_vector (2-1 downto 0);
signal pl_directed_link_speed : std_logic;
signal pl_directed_link_width : std_logic_vector (2-1 downto 0);
signal pl_upstream_prefer_deemph : std_logic;
-- Wires used for external clocking connectivity
signal PIPE_PCLK_IN : std_logic := '0';
signal PIPE_RXUSRCLK_IN : std_logic := '0';
signal PIPE_RXOUTCLK_IN : std_logic_vector(3 downto 0) := (others => '0');
signal PIPE_DCLK_IN : std_logic := '0';
signal PIPE_USERCLK1_IN : std_logic := '0';
signal PIPE_USERCLK2_IN : std_logic := '0';
signal PIPE_OOBCLK_IN : std_logic := '0';
signal PIPE_MMCM_LOCK_IN : std_logic := '0';
signal PIPE_TXOUTCLK_OUT : std_logic;
signal PIPE_RXOUTCLK_OUT : std_logic_vector(3 downto 0);
signal PIPE_PCLK_SEL_OUT : std_logic_vector(3 downto 0);
signal PIPE_GEN3_OUT : std_logic;
----------------------------------------------------
signal user_reset_int1 : std_logic;
signal user_lnk_up_int1 : std_logic;
signal user_clk : std_logic;
signal user_reset : std_logic;
signal user_lnk_up : std_logic;
signal s_axis_tx_tdata : std_logic_vector(63 downto 0);
signal s_axis_tx_tkeep : std_logic_vector(7 downto 0);
signal s_axis_tx_tlast : std_logic;
signal s_axis_tx_tvalid : std_logic;
signal s_axis_tx_tready : std_logic;
signal s_axis_tx_tuser : std_logic_vector(3 downto 0);
signal s_axis_tx_tdsc : std_logic;
signal s_axis_tx_terrfwd : std_logic;
signal tx_buf_av : std_logic_vector(5 downto 0);
signal m_axis_rx_tdata : std_logic_vector(63 downto 0);
signal m_axis_rx_tkeep : std_logic_vector(7 downto 0);
signal m_axis_rx_tlast : std_logic;
signal m_axis_rx_tvalid : std_logic;
signal m_axis_rx_tready : std_logic;
signal m_axis_rx_terrfwd : std_logic;
signal m_axis_rx_tuser : std_logic_vector(21 downto 0);
signal rx_np_ok : std_logic;
signal rx_np_req : std_logic;
signal m_axis_rx_tbar_hit : std_logic_vector(6 downto 0);
signal trn_rfc_nph_av : std_logic_vector(7 downto 0);
signal trn_rfc_npd_av : std_logic_vector(11 downto 0);
signal trn_rfc_ph_av : std_logic_vector(7 downto 0);
signal trn_rfc_pd_av : std_logic_vector(11 downto 0);
signal trn_rfc_cplh_av : std_logic_vector(7 downto 0);
signal trn_rfc_cpld_av : std_logic_vector(11 downto 0);
signal cfg_do : std_logic_vector(31 downto 0);
signal cfg_mgmt_rd_wr_done : std_logic;
signal cfg_di : std_logic_vector(31 downto 0);
signal cfg_mgmt_byte_en : std_logic_vector(3 downto 0);
signal cfg_dwaddr : std_logic_vector(9 downto 0);
signal cfg_mgmt_wr_en : std_logic;
signal cfg_mgmt_rd_en : std_logic;
signal cfg_err_cor : std_logic;
signal cfg_err_ur : std_logic;
signal cfg_err_cpl_rdy : std_logic;
signal cfg_err_ecrc : std_logic;
signal cfg_err_cpl_timeout : std_logic;
signal cfg_err_cpl_abort : std_logic;
signal cfg_err_cpl_unexpect : std_logic;
signal cfg_err_posted : std_logic;
signal cfg_err_locked : std_logic;
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
signal cfg_interrupt : std_logic;
signal cfg_interrupt_rdy : std_logic;
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable : std_logic;
signal cfg_interrupt_msixenable : std_logic;
signal cfg_interrupt_msixfm : std_logic;
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
signal cfg_interrupt_assert : std_logic;
signal cfg_turnoff_ok : std_logic;
signal cfg_to_turnoff : std_logic;
signal cfg_pm_wake : std_logic;
signal cfg_pcie_link_state : std_logic_vector(2 downto 0);
signal cfg_trn_pending : std_logic;
signal cfg_bus_number : std_logic_vector(7 downto 0);
signal cfg_device_number : std_logic_vector(4 downto 0);
signal cfg_function_number : std_logic_vector(2 downto 0);
signal cfg_dsn : std_logic_vector(63 downto 0);
signal cfg_status : std_logic_vector(15 downto 0);
signal cfg_command : std_logic_vector(15 downto 0);
signal cfg_dstatus : std_logic_vector(15 downto 0);
signal cfg_dcommand : std_logic_vector(15 downto 0);
signal cfg_lstatus : std_logic_vector(15 downto 0);
signal cfg_lcommand : std_logic_vector(15 downto 0);
signal sys_clk_c : std_logic;
signal sys_reset_n_c : std_logic;
signal sys_reset_c : std_logic;
signal reset_n : std_logic;
signal localId : std_logic_vector(15 downto 0);
signal pcie_link_width : std_logic_vector(5 downto 0);
signal ddr_ref_clk_i : std_logic;
----- DDR core User Interface signals -----------------------
signal app_addr : std_logic_vector(DDR_ADDR_WIDTH-1 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_wdf_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
signal app_wdf_wren : std_logic;
signal app_rd_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal ddr_ui_clk : std_logic;
signal ddr_ui_reset : std_logic;
signal ddr_calib_done : std_logic;
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_reset_i : std_logic;
begin
sys_reset_c <= not sys_reset_n_c;
sys_reset_n_ibuf : IBUF
port map (
O => sys_reset_n_c,
I => sys_rst_n
);
pcieclk_ibuf : IBUFDS_GTXE1
port map (
O => sys_clk_c,
ODIV2 => open,
I => sys_clk_p,
IB => sys_clk_n,
CEB => '0'
);
cfg_err_cor <= '0';
cfg_err_ur <= '0';
cfg_err_ecrc <= '0';
cfg_err_cpl_timeout <= '0';
cfg_err_cpl_abort <= '0';
cfg_err_cpl_unexpect <= '0';
cfg_err_posted <= '1';
cfg_err_locked <= '1';
cfg_err_tlp_cpl_header <= (others => '0');
cfg_trn_pending <= '0';
cfg_pm_wake <= '0';
--
fc_sel <= (others => '0');
pl_directed_link_auton <= '0';
pl_directed_link_change <= (others => '0');
pl_directed_link_speed <= '0';
pl_directed_link_width <= (others => '0');
pl_upstream_prefer_deemph <= '0';
tx_cfg_gnt <= '1';
s_axis_tx_tuser <= s_axis_tx_tdsc & '0' & s_axis_tx_terrfwd & '0';
m_axis_rx_terrfwd <= m_axis_rx_tuser(1);
m_axis_rx_tbar_hit <= m_axis_rx_tuser(8 downto 2);
--
cfg_di <= (others => '0');
cfg_dwaddr <= (others => '1');
cfg_mgmt_byte_en <= (others => '0');
cfg_mgmt_wr_en <= '0';
cfg_mgmt_rd_en <= '0';
cfg_dsn <= X"00000001" & X"01" & X"000A35"; -- //this is taken from GUI -
cfg_turnoff_ok <= '1';
localId <= cfg_bus_number & cfg_device_number & cfg_function_number;
pcie_link_width <= cfg_lstatus(9 downto 4);
user_lnk_up_int_i : FDPE
generic map (
INIT => '0'
)
port map (
Q => user_lnk_up,
D => user_lnk_up_int1,
C => user_clk,
CE => '1',
PRE => '0'
);
user_reset_i : FDPE
generic map (
INIT => '1'
)
port map (
Q => user_reset,
D => user_reset_int1,
C => user_clk,
CE => '1',
PRE => '0'
);
-- --------------------------------------------------------------
-- --------------------------------------------------------------
pcie_core_i : pcie_core
generic map(
PL_FAST_TRAIN => PL_FAST_TRAIN
)
port map(
--------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
--------------------------------------------------------------------------------------------------------------------
--TX
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- RX
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
-------------------------------------------------------------------------------------------------------------------
-- 2. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out => user_clk ,
user_reset_out => user_reset_int1,
user_lnk_up => user_lnk_up_int1,
-- TX
tx_buf_av => tx_buf_av ,
tx_cfg_req => tx_cfg_req ,
tx_err_drop => tx_err_drop ,
s_axis_tx_tready => s_axis_tx_tready ,
s_axis_tx_tdata => s_axis_tx_tdata ,
s_axis_tx_tkeep => s_axis_tx_tkeep ,
s_axis_tx_tlast => s_axis_tx_tlast ,
s_axis_tx_tvalid => s_axis_tx_tvalid ,
s_axis_tx_tuser => s_axis_tx_tuser,
tx_cfg_gnt => tx_cfg_gnt ,
-- RX
m_axis_rx_tdata => m_axis_rx_tdata ,
m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_tvalid => m_axis_rx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready ,
m_axis_rx_tuser => m_axis_rx_tuser,
rx_np_ok => rx_np_ok ,
-- Flow Control
fc_cpld => fc_cpld ,
fc_cplh => fc_cplh ,
fc_npd => fc_npd ,
fc_nph => fc_nph ,
fc_pd => fc_pd ,
fc_ph => fc_ph ,
fc_sel => fc_sel ,
-------------------------------------------------------------------------------------------------------------------
-- 3. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
cfg_di => cfg_di,
cfg_byte_en => (others => '0'),
cfg_dwaddr => cfg_dwaddr,
cfg_wr_en => '0',
cfg_rd_en => '0',
cfg_status => cfg_status ,
cfg_command => cfg_command ,
cfg_dstatus => cfg_dstatus ,
cfg_dcommand => cfg_dcommand ,
cfg_lstatus => cfg_lstatus ,
cfg_lcommand => cfg_lcommand ,
cfg_dcommand2 => cfg_dcommand2 ,
cfg_pcie_link_state => cfg_pcie_link_state ,
cfg_pmcsr_pme_en => open ,
cfg_pmcsr_pme_status => open ,
cfg_pmcsr_powerstate => open ,
cfg_err_ecrc => cfg_err_ecrc ,
cfg_err_ur => cfg_err_ur ,
cfg_err_cpl_timeout => cfg_err_cpl_timeout ,
cfg_err_cpl_unexpect => cfg_err_cpl_unexpect ,
cfg_err_cpl_abort => cfg_err_cpl_abort ,
cfg_err_posted => cfg_err_posted ,
cfg_err_cor => cfg_err_cor ,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy => cfg_err_cpl_rdy ,
cfg_err_locked => cfg_err_locked ,
cfg_trn_pending => cfg_trn_pending ,
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt => cfg_interrupt ,
cfg_interrupt_rdy => cfg_interrupt_rdy ,
cfg_interrupt_assert => cfg_interrupt_assert ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_to_turnoff => cfg_to_turnoff ,
cfg_turnoff_ok => cfg_turnoff_ok ,
cfg_bus_number => cfg_bus_number ,
cfg_device_number => cfg_device_number ,
cfg_function_number => cfg_function_number ,
cfg_pm_wake => cfg_pm_wake ,
-------------------------------------------------------------------------------------------------------------------
-- 5. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_auton => pl_directed_link_auton ,
pl_directed_link_change => pl_directed_link_change ,
pl_directed_link_speed => pl_directed_link_speed ,
pl_directed_link_width => pl_directed_link_width ,
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
pl_ltssm_state => open ,
pl_lane_reversal_mode => pl_lane_reversal_mode ,
cfg_dsn => cfg_dsn ,
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
pl_initial_link_width => pl_initial_link_width ,
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst => pl_received_hot_rst ,
-------------------------------------------------------------------------------------------------------------------
-- 6. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
sys_clk => sys_clk_c ,
sys_reset => sys_reset_c
);
-- ---------------------------------------------------------------
-- tlp control module
-- ---------------------------------------------------------------
theTlpControl :
tlpControl
port map (
-- Wishbone FIFO interface
wb_FIFO_we => wb_wr_we , -- OUT std_logic;
wb_FIFO_wsof => wb_wr_wsof , -- OUT std_logic;
wb_FIFO_weof => wb_wr_weof , -- OUT std_logic;
wb_FIFO_din => wb_wr_din(C_DBUS_WIDTH-1 downto 0) , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_fifo_full => wb_wr_full,
wb_FIFO_re => wb_rdd_ren , -- OUT std_logic;
wb_FIFO_empty => wb_rdd_empty , -- IN std_logic;
wb_FIFO_qout => wb_rdd_dout(C_DBUS_WIDTH-1 downto 0) , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_sof => wb_rdc_sof, --out std_logic;
wb_rdc_v => wb_rdc_v, --out std_logic;
wb_rdc_din => wb_rdc_din, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full => wb_rdc_full, --in std_logic;
wb_timeout => wb_timeout,
wb_FIFO_Rst => wb_fifo_rst , -- OUT std_logic;
-------------------
-- DDR Interface
DDR_Ready => DDR_Ready , -- IN std_logic;
DDR_wr_sof => DDR_wr_sof , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof , -- OUT std_logic;
DDR_wr_v => DDR_wr_v , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- OUT std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-------------------
-- Transaction Interface
user_lnk_up => user_lnk_up ,
rx_np_ok => rx_np_ok ,
rx_np_req => rx_np_req ,
s_axis_tx_tdsc => s_axis_tx_tdsc ,
tx_buf_av => tx_buf_av ,
s_axis_tx_terrfwd => s_axis_tx_terrfwd ,
user_clk => user_clk ,
user_reset => user_reset ,
m_axis_rx_tvalid => m_axis_rx_tvalid ,
s_axis_tx_tready => s_axis_tx_tready ,
m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_terrfwd => m_axis_rx_terrfwd ,
m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tdata => m_axis_rx_tdata ,
cfg_interrupt => cfg_interrupt ,
cfg_interrupt_rdy => cfg_interrupt_rdy ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_assert => cfg_interrupt_assert ,
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit ,
s_axis_tx_tvalid => s_axis_tx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready ,
s_axis_tx_tlast => s_axis_tx_tlast ,
s_axis_tx_tkeep => s_axis_tx_tkeep ,
s_axis_tx_tdata => s_axis_tx_tdata ,
cfg_dcommand => cfg_dcommand ,
pcie_link_width => pcie_link_width ,
localId => localId
);
-- -----------------------------------------------------------------------
-- DDR SDRAM: control module USER LOGIC (2 BRAM Module:
-- -----------------------------------------------------------------------
LoopBack_BRAM_Off : if not USE_LOOPBACK_TEST generate
DDRs_ctrl_module : DDR_Transact
generic map (
SIMULATION => SIMULATION,
DATA_WIDTH => C_DBUS_WIDTH,
ADDR_WIDTH => DDR_ADDR_WIDTH,
DDR_UI_DATAWIDTH => DDR_PAYLOAD_WIDTH,
DDR_DQ_WIDTH => DDR_DQ_WIDTH/2, --!!! Fix for differences between Virtex6 and 7 family devices
DEVICE_TYPE => "VIRTEX6"
)
port map(
memc_ui_clk => memc_ui_clk, --: out std_logic;
memc_cmd_rdy => memc_cmd_rdy, --: out std_logic;
memc_cmd_en => memc_cmd_en, --: in std_logic;
memc_cmd_instr => memc_cmd_instr, --: in std_logic_vector(2 downto 0);
memc_cmd_addr => memc_cmd_addr, --: in std_logic_vector(31 downto 0);
memc_wr_en => memc_wr_en, --: in std_logic;
memc_wr_end => memc_wr_end, --: in std_logic;
memc_wr_mask => memc_wr_mask, --: in std_logic_vector(64/8-1 downto 0);
memc_wr_data => memc_wr_data, --: in std_logic_vector(64-1 downto 0);
memc_wr_rdy => memc_wr_rdy, --: out std_logic;
memc_rd_data => memc_rd_data, --: out std_logic_vector(64-1 downto 0);
memc_rd_valid => memc_rd_valid, --: out std_logic;
memarb_acc_req => memarb_acc_req, --: in std_logic;
memarb_acc_gnt => memarb_acc_gnt, --: out std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready, -- OUT std_logic;
-- DDR core User Interface signals
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
ui_clk => ddr_ui_clk,
ui_clk_sync_rst => ddr_ui_reset,
init_calib_complete => ddr_calib_done,
--clocking & reset
user_clk => user_clk , -- IN std_logic;
user_reset => user_reset -- IN std_logic
);
end generate;
LoopBack_BRAM_On : if USE_LOOPBACK_TEST generate
DDRs_ctrl_module :
bram_DDRs_Control_loopback
generic map (
C_ASYNFIFO_WIDTH => 72 ,
P_SIMULATION => false
)
port map(
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_sof => DDR_wr_sof , -- IN std_logic;
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- IN std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- IN std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready , -- OUT std_logic;
DDR_Blinker => open , -- OUT std_logic;
mem_clk => user_clk , -- IN
user_clk => user_clk , -- IN std_logic;
Sim_Zeichen => open , -- OUT std_logic;
user_reset => user_reset -- IN std_logic
);
end generate;
Wishbone_intf :
wb_transact
port map(
-- PCIE user clk
user_clk => user_clk, --in std_logic;
-- Write port
wr_we => wb_wr_we, --in std_logic;
wr_sof => wb_wr_wsof, --in std_logic;
wr_eof => wb_wr_weof, --in std_logic;
wr_din => wb_wr_din, --in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full => wb_wr_full, --out std_logic;
-- Read command port
rdc_sof => wb_rdc_sof, --in std_logic;
rdc_v => wb_rdc_v, --in std_logic;
rdc_din => wb_rdc_din, --in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full => wb_rdc_full,--out std_logic;
rd_tout => wb_timeout,
-- Read data port
rd_ren => wb_rdd_ren, --in std_logic;
rd_empty => wb_rdd_empty, --out std_logic;
rd_dout => wb_rdd_dout, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk => wbone_clk, --in std_logic;
wb_rst => wbone_rst, --in std_logic;
addr_o => wbone_addr(28 downto 0), --out std_logic_vector(31 downto 0);
dat_i => wbone_mdin, --in std_logic_vector(63 downto 0);
dat_o => wbone_mdout, --out std_logic_vector(63 downto 0);
we_o => wbone_we, --out std_logic;
sel_o => wbone_sel, --out std_logic_vector(0 downto 0);
stb_o => wbone_stb, --out std_logic;
ack_i => wbone_ack, --in std_logic;
cyc_o => wbone_cyc, --out std_logic;
--RESET from PCIe
rst => user_reset --in std_logic
);
wbone_clk <= CLK_I;
wbone_rst <= RST_I;
wbone_mdin <= DAT_I;
wbone_ack <= ACK_I;
ADDR_O <= wbone_addr;
DAT_O <= wbone_mdout;
WE_O <= wbone_we;
SEL_O <= wbone_sel(0);
STB_O <= wbone_stb;
CYC_O <= wbone_cyc;
ext_rst_o <= wb_fifo_rst;
u_ddr_core : ddr_v6
generic map (
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
RST_ACT_LOW => 0
)
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
phy_init_done => ddr_calib_done,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
scl => open,
sda => open,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
ui_clk => ddr_ui_clk,
ui_clk_sync_rst => ddr_ui_reset,
-- System Clock Ports
sys_clk => ddr_sys_clk_i,
clk_ref => ddr_ref_clk_i,
sys_rst => ddr_sys_reset_i
);
ddr_sys_clk_i <= ddr_sys_clk_p;
ddr_ref_clk_i <= ddr_sys_clk_p;
ddr_sys_reset_i <= ddr_core_rst;
memc_ui_rst <= ddr_ui_reset;
end Behavioral;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/fmc_adc_common/fmc_adc_clk.vhd
|
1
|
17659
|
------------------------------------------------------------------------------
-- Title : Wishbone FMC ADC clock Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-29-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Clock Interface with FMC ADC boards.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-29-10 1.0 lucas.russo Created
-- 2013-19-08 1.1 lucas.russo Refactored to enable use with other FMC ADC boards
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc_adc_pkg.all;
entity fmc_adc_clk is
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_delay_type : string := "VARIABLE";
g_adc_clock_period : real;
g_default_adc_clk_delay : natural := 0;
g_with_ref_clk : boolean := false;
g_mmcm_param : t_mmcm_param := default_mmcm_param;
g_with_fn_dly_select : boolean := false;
g_with_bufio : boolean := true;
g_with_bufr : boolean := true;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
sys_rst_i : in std_logic;
-----------------------------
-- External ports
-----------------------------
-- ADC clocks. One clock per ADC channel
adc_clk_i : in std_logic;
-----------------------------
-- ADC Delay signals.
-----------------------------
-- ADC fine delay control
adc_clk_fn_dly_i : in t_adc_clk_fn_dly;
adc_clk_fn_dly_o : out t_adc_clk_fn_dly;
-----------------------------
-- ADC output signals.
-----------------------------
adc_clk_chain_priv_o : out t_adc_clk_chain_priv;
adc_clk_chain_glob_o : out t_adc_clk_chain_glob
-----------------------------
-- MMCM general signals
-----------------------------
--mmcm_adc_locked_o : out std_logic
);
end fmc_adc_clk;
architecture rtl of fmc_adc_clk is
alias c_mmcm_param is g_mmcm_param;
-- Clock and reset signals
signal adc_clk_ibufgds : std_logic;
signal adc_clk_ibufgds_dly : std_logic;
-- Clock BUFMR signals
signal adc_clk_bufmr : std_logic;
-- Clock BUFIO/BUFR input signals
signal adc_clk_bufio_in : std_logic;
signal adc_clk_bufr_in : std_logic;
signal adc_clk_mmcm_in : std_logic;
-- Clock internal signals interconnect
signal adc_clk_bufio : std_logic;
signal adc_clk_bufr : std_logic;
signal adc_clk_bufg : std_logic;
signal adc_clk2x_bufg : std_logic;
-- Clock MMCM signals
signal adc_clk_fbin : std_logic;
signal adc_clk_fbout : std_logic;
signal adc_clk_mmcm_out : std_logic;
signal adc_clk2x_mmcm_out : std_logic;
signal mmcm_adc_locked_int : std_logic;
-- Clock delay signals
signal iodelay_update : std_logic;
--signal adc_clk_dly_val_int : std_logic_vector(4 downto 0);
begin
-- Check for unsupported generic configs
-- Supported options
--BUFIO yes / BUFR no (unsupported)
--BUFIO no / BUFR yes (OK)
--BUFIO yes / BUFR yes (OK)
--BUFIO no / BUFR no (OK)
assert not (g_with_bufio and not g_with_bufr) report
"If BUFIO is used, then BUFR must also be!" severity failure;
-----------------------------
-- Clock signal datapath
-----------------------------
-- Delay for Clock Buffers
-- From Virtex-6 SelectIO Datasheet:
-- Sets the type of tap delay line. DEFAULT delay guarantees zero hold times.
-- FIXED delay sets a static delay value. VAR_LOADABLE dynamically loads tap
-- values. VARIABLE delay dynamically adjusts the delay value.
--
-- HIGH_PERFORMANCE_MODE = TRUE reduces the output
-- jitter in exchange of increase power dissipation
gen_adc_clk_var_loadable_iodelay : if (g_delay_type = "VAR_LOADABLE") generate
cmp_ibufds_clk_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_clk_delay,
SIGNAL_PATTERN => "CLOCK",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
idatain => adc_clk_i,
dataout => adc_clk_ibufgds_dly,
c => sys_clk_i,
ce => '0',
--inc => adc_clk_dly_incdec_i,
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
--rst => adc_clk_dly_pulse_i,
rst => iodelay_update,
cntvaluein => adc_clk_fn_dly_i.idelay.val,
cntvalueout => adc_clk_fn_dly_o.idelay.val,
cinvctrl => '0',
t => '1'
);
end generate;
gen_adc_clk_variable_iodelay : if (g_delay_type = "VARIABLE") generate
cmp_ibufds_clk_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_clk_delay,
SIGNAL_PATTERN => "CLOCK",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
idatain => adc_clk_i,
dataout => adc_clk_ibufgds_dly,
c => sys_clk_i,
--ce => adc_clk_dly_pulse_i,
ce => iodelay_update,
inc => adc_clk_fn_dly_i.idelay.incdec,
datain => '0',
odatain => '0',
clkin => '0',
rst => '0',
cntvaluein => adc_clk_fn_dly_i.idelay.val,
cntvalueout => adc_clk_fn_dly_o.idelay.val,
cinvctrl => '0',
t => '1'
);
end generate;
gen_with_fn_dly_select : if (g_with_fn_dly_select) generate
iodelay_update <= '1' when adc_clk_fn_dly_i.idelay.pulse = '1' and
adc_clk_fn_dly_i.sel.which = '1' else '0';
end generate;
gen_without_fn_dly_select : if (not g_with_fn_dly_select) generate
iodelay_update <= adc_clk_fn_dly_i.idelay.pulse;
end generate;
-- Generate BUFMR and connect directly to BUFIO/BUFR
--
-- In Xilinx 7-Series devices, BUFIO/BUFR only drives a single clock region.
-- If BUFIO/BUFR must drive multi clock-regions (up to 3: actual, above and
-- below), we must instanciate a multi-clock buffer (BUFMR) and then drive
-- the BUFIO/BUFR as needed.
gen_bufmr : if (g_fpga_device = "7SERIES") generate
-- We either have BUFIO + BUFR or just BUFR. We only
-- have to check for BUFR, then.
gen_bufmr_7_series : if (g_with_bufr) generate
-- 1-bit output: Clock output (connect to BUFIOs/BUFRs)
-- 1-bit input: Clock input (Connect to IBUFG)
cmp_bufmr : bufmr
port map (
O => adc_clk_bufmr,
I => adc_clk_ibufgds_dly
);
adc_clk_bufio_in <= adc_clk_bufmr;
adc_clk_bufr_in <= adc_clk_bufmr;
end generate;
gen_not_bufmr_7_series : if (not g_with_bufr) generate
adc_clk_bufio_in <= adc_clk_ibufgds_dly;
adc_clk_bufr_in <= adc_clk_ibufgds_dly;
end generate;
end generate;
-- Do not generate BUFMR and connect the input clock directly to BUFIO/BUFR
gen_not_bufmr : if (g_fpga_device = "VIRTEX6") generate
adc_clk_bufio_in <= adc_clk_ibufgds_dly;
adc_clk_bufr_in <= adc_clk_ibufgds_dly;
end generate;
-- BUFIO (better switching characteristics than BUFR and BUFG).
-- It can be used just inside ILOGIC blocks resources, such as
-- an IDDR block.
gen_with_bufio : if (g_with_bufio) generate
cmp_adc_clk_bufio : bufio
port map (
O => adc_clk_bufio,
I => adc_clk_bufio_in
);
end generate;
-- BUFR (better switching characteristics than BUFG).
-- It can drive logic elements (block ram, CLB, DSP tiles,
-- etc) up to 6 clock regions.
gen_with_bufr : if (g_with_bufr) generate
cmp_adc_clk_bufr : bufr
generic map(
SIM_DEVICE => g_fpga_device,
BUFR_DIVIDE => "BYPASS"
)
port map (
CLR => '0',
CE => '1',
I => adc_clk_bufr_in,
O => adc_clk_bufr
);
end generate;
-- MMCM input clock
gen_mmcm_clk_fallback_in : if (not g_with_bufr and not g_with_bufio) generate
adc_clk_mmcm_in <= adc_clk_ibufgds_dly;
end generate;
gen_mmcm_clk_in : if (g_with_bufr) generate
adc_clk_mmcm_in <= adc_clk_bufr;
end generate;
gen_with_ref_clk : if (g_with_ref_clk) generate
-- ADC Clock PLL
cmp_mmcm_adc_clk : MMCM_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
-- Let the synthesis tools select the best appropriate
-- compensation method (as dictated in Virtex-6 clocking
-- resourses guide page 53, note 2)
--COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
--DIVCLK_DIVIDE => 4,
DIVCLK_DIVIDE => c_mmcm_param.divclk,
--CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_MULT_F => c_mmcm_param.clkbout_mult_f,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
-- adc clock
--CLKOUT0_DIVIDE_F => 3.000,
CLKOUT0_DIVIDE_F => c_mmcm_param.clk0_out_div_f,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
-- 2x adc clock.
--CLKOUT1_DIVIDE => 3,
CLKOUT1_DIVIDE => c_mmcm_param.clk1_out_div,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 130 MHZ input clock
CLKIN1_PERIOD => c_mmcm_param.clk0_in_period,
REF_JITTER1 => 0.10,
-- Not used. Just to bypass Xilinx errors
-- Just input 130 MHz input clock
CLKIN2_PERIOD => c_mmcm_param.clk0_in_period,
REF_JITTER2 => 0.10
)
port map(
-- Output clocks
CLKFBOUT => adc_clk_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_clk_mmcm_out,
CLKOUT0B => open,
CLKOUT1 => adc_clk2x_mmcm_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_clk_fbin,
CLKIN1 => adc_clk_mmcm_in,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked_int,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => sys_rst_i
);
-- Global clock buffer for MMCM feedback. Deskew MMCM configuration
cmp_adc_clk_fb_bufg : BUFG
port map(
O => adc_clk_fbin,
I => adc_clk_fbout
);
-- Global clock buffer for FPGA logic
cmp_adc_out_bufg : BUFG
port map(
O => adc_clk_bufg,
I => adc_clk_mmcm_out
);
cmp_adc2x_out_bufg : BUFG
port map(
O => adc_clk2x_bufg,
I => adc_clk2x_mmcm_out
);
end generate;
-- Only instantiate BUFG if BUFIO and BUFR not selected and not a reference clock
gen_without_ref_clk : if (not g_with_ref_clk) generate
gen_without_bufio_bufr : if (not g_with_bufio and not g_with_bufr) generate
cmp_noref_clk_bufg : BUFG
port map(
O => adc_clk_bufg,
I => adc_clk_mmcm_in
);
end generate;
end generate;
-- Clock buffer supported options
--BUFIO yes / BUFR no (unsupported)
--BUFIO no / BUFR yes (OK)
--BUFIO yes / BUFR yes (OK)
--BUFIO no / BUFR no (OK)
-- Output clocks.
-- BUFIO selected
gen_with_bufio_out : if (g_with_bufio) generate
adc_clk_chain_priv_o.adc_clk_bufio <= adc_clk_bufio;
end generate;
-- BUFR selected
gen_with_bufr_out : if (g_with_bufr) generate
adc_clk_chain_priv_o.adc_clk_bufr <= adc_clk_bufr;
-- BUFR selected but BUFIO NOT selected. Output BUFIO clock as BUFR clock
gen_withou_bufio_out : if (not g_with_bufio) generate
adc_clk_chain_priv_o.adc_clk_bufio <= adc_clk_bufr;
end generate;
end generate;
-- BUFR NOT selected and BUFIO NOT selected. Output BUFIO and BUFR as BUFG clock
gen_withou_bufr_bufio_out : if (not g_with_bufio and not g_with_bufr) generate
adc_clk_chain_priv_o.adc_clk_bufr <= adc_clk_bufg;
adc_clk_chain_priv_o.adc_clk_bufio <= adc_clk_bufg;
end generate;
-- Output Reference ADC clock if selected
gen_ref_clks : if (g_with_ref_clk) generate
adc_clk_chain_glob_o.adc_clk_bufg <= adc_clk_bufg;
adc_clk_chain_glob_o.adc_clk2x_bufg <= adc_clk2x_bufg;
end generate;
gen_true_mmcm_lock_ref_clk : if (g_with_ref_clk) generate
adc_clk_chain_glob_o.mmcm_adc_locked <= mmcm_adc_locked_int;
end generate;
gen_false_mmcm_lock_ref_clk : if (not g_with_ref_clk) generate
adc_clk_chain_glob_o.mmcm_adc_locked <= '1';
end generate;
end rtl;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd
|
1
|
102365
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
--Purpose:
-- Top-level for memory physical layer (PHY) interface
-- NOTES:
-- 1. Need to support multiple copies of CS outputs
-- 2. DFI_DRAM_CKE_DISABLE not supported
--
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_top.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_top.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_top is
generic (
TCQ : integer := 100;
nCK_PER_CLK : integer := 2; -- # of memory clocks per CLK
CLK_PERIOD : integer := 3333; -- Internal clock period (in ps)
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
-- Slot Conifg parameters
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := X"01";
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := X"00";
-- DRAM bus widths
BANK_WIDTH : integer := 2; -- # of bank bits
CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory
COL_WIDTH : integer := 10; -- column address width
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
DQ_CNT_WIDTH : integer := 6; -- = ceil(log2(DQ_WIDTH))
DQ_WIDTH : integer := 64; -- # of DQ (data)
DM_WIDTH : integer := 8; -- # of DM (data mask)
DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH))
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
ROW_WIDTH : integer := 14; -- DRAM address bus width
RANK_WIDTH : integer := 1; -- log2(CS_WIDTH)
CS_WIDTH : integer := 1; -- # of DRAM ranks
CKE_WIDTH : integer := 1; -- # of DRAM ranks
CAL_WIDTH : string := "HALF"; -- # of DRAM ranks to be calibrated
-- CAL_WIDTH = CS_WIDTH when "FULL"
-- CAL_WIDTH = CS_WIDTH/2 when "HALF"
-- calibration Address. The address given below will be used for calibration
-- read and write operations.
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000"; -- Calibration row address
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000"; -- Calibration column address
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000"; -- Calibration bank address
-- DRAM mode settings
AL : string := "0"; -- Additive Latency option
BURST_MODE : string := "8"; -- Burst length
BURST_TYPE : string := "SEQ"; -- Burst type
nAL : integer := 0; -- Additive latency (in clk cyc)
nCL : integer := 5; -- Read CAS latency (in clk cyc)
nCWL : integer := 5; -- Write CAS latency (in clk cyc)
tRFC : integer := 110000; -- Refresh-to-command delay
OUTPUT_DRV : string := "HIGH"; -- DRAM reduced output drive option
REG_CTRL : string := "ON"; -- "ON" for registered DIMM
RTT_NOM : string := "60"; -- ODT Nominal termination value
RTT_WR : string := "60"; -- ODT Write termination value
WRLVL : string := "OFF"; -- Enable write leveling
-- Phase Detector/Read Leveling options
PHASE_DETECT : string := "OFF"; -- Enable read phase detector
PD_TAP_REQ : integer := 0; -- # of IODELAY taps reserved for PD
PD_MSB_SEL : integer := 8; -- # of IODELAY taps reserved for PD
PD_DQS0_ONLY : string := "ON"; -- Enable use of DQS[0] only for
-- phase detector
PD_LHC_WIDTH : integer := 16; -- sampling averaging cntr widths
PD_CALIB_MODE : string := "PARALLEL"; -- parallel/seq PD calibration
-- IODELAY/BUFFER options
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG"; -- May be assigned unique name
-- when mult IP cores in design
-- Pin-out related parameters
nDQS_COL0 : integer := 8; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 0; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 0; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 0; -- # DQS groups in I/O column #4
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"11100F0E0D0C0B0A09080706050403020100";
-- DQS grps in col #1
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #2
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #3
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #4
USE_DM_PORT : integer := 1; -- DM instantation enable
-- Simulation /debug options
SIM_BYPASS_INIT_CAL : string := "OFF"; -- Parameter used to force skipping
-- or abbreviation of initialization
-- and calibration. Overrides
-- SIM_INIT_OPTION, SIM_CAL_OPTION,
-- and disables various other blocks
SIM_INIT_OPTION : string := "NONE"; -- Skip various initialization steps
SIM_CAL_OPTION : string := "NONE"; -- Skip various calibration steps
DEBUG_PORT : string := "OFF" -- Enable debug port
);
port (
clk_mem : in std_logic; -- Memory clock
clk : in std_logic; -- Internal (logic) clock
clk_rd_base : in std_logic; -- For inner/outer I/O cols
rst : in std_logic; -- Reset sync'ed to CLK
-- Slot present inputs
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
-- DFI Control/Address
dfi_address0 : in std_logic_vector(ROW_WIDTH-1 downto 0);
dfi_address1 : in std_logic_vector(ROW_WIDTH-1 downto 0);
dfi_bank0 : in std_logic_vector(BANK_WIDTH-1 downto 0);
dfi_bank1 : in std_logic_vector(BANK_WIDTH-1 downto 0);
dfi_cas_n0 : in std_logic;
dfi_cas_n1 : in std_logic;
dfi_cke0 : in std_logic_vector(CKE_WIDTH-1 downto 0);
dfi_cke1 : in std_logic_vector(CKE_WIDTH-1 downto 0);
dfi_cs_n0 : in std_logic_vector(CS_WIDTH*nCS_PER_RANK - 1 downto 0);
dfi_cs_n1 : in std_logic_vector(CS_WIDTH*nCS_PER_RANK - 1 downto 0);
dfi_odt0 : in std_logic_vector(CS_WIDTH*nCS_PER_RANK - 1 downto 0);
dfi_odt1 : in std_logic_vector(CS_WIDTH*nCS_PER_RANK - 1 downto 0);
dfi_ras_n0 : in std_logic;
dfi_ras_n1 : in std_logic;
dfi_reset_n : in std_logic;
dfi_we_n0 : in std_logic;
dfi_we_n1 : in std_logic;
-- DFI Write
dfi_wrdata_en : in std_logic;
dfi_wrdata : in std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
dfi_wrdata_mask : in std_logic_vector(4 * (DQ_WIDTH / 8) - 1 downto 0);
-- DFI Read
dfi_rddata_en : in std_logic;
dfi_rddata : out std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
dfi_rddata_valid : out std_logic;
-- DFI Initialization Status / CLK Disable
dfi_dram_clk_disable : in std_logic;
dfi_init_complete : out std_logic;
-- sideband signals
io_config_strobe : in std_logic;
io_config : in std_logic_vector(RANK_WIDTH downto 0);
-- DDRx Output Interface
ddr_ck_p : out std_logic_vector(CK_WIDTH - 1 downto 0);
ddr_ck_n : out std_logic_vector(CK_WIDTH - 1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH - 1 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_cs_n : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH - 1 downto 0);
ddr_odt : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_dm : out std_logic_vector(DM_WIDTH - 1 downto 0);
ddr_dqs_p : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dq : inout std_logic_vector(DQ_WIDTH - 1 downto 0);
-- Read Phase Detector Interface
pd_PSDONE : in std_logic;
pd_PSEN : out std_logic;
pd_PSINCDEC : out std_logic;
-- Debug Port
-- Write leveling logic
dbg_wr_dqs_tap_set : in std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_wr_dq_tap_set : in std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_wr_tap_set_en : in std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wl_dqs_inverted : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dbg_wr_calib_clk_delay : out std_logic_vector(2 * DQS_WIDTH - 1 downto 0);
dbg_wl_odelay_dqs_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_wl_odelay_dq_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(4 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH - 1 downto 0);
-- Read leveling logic
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_rd_bitslip_cnt : out std_logic_vector(3 * DQS_WIDTH - 1 downto 0);
dbg_rd_clkdly_cnt : out std_logic_vector(2 * DQS_WIDTH - 1 downto 0);
dbg_rd_active_dly : out std_logic_vector(4 downto 0);
dbg_rd_data : out std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
-- Delay control
dbg_idel_up_all : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_rsync : in std_logic;
dbg_idel_down_rsync : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_rsync : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_sel_all_idel_rsync : in std_logic;
dbg_cpt_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_rsync_tap_cnt : out std_logic_vector(19 downto 0);
dbg_dqs_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_dq_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
-- Phase detector
dbg_pd_off : in std_logic;
dbg_pd_maintain_off : in std_logic;
dbg_pd_maintain_0_only : in std_logic;
dbg_pd_inc_cpt : in std_logic;
dbg_pd_dec_cpt : in std_logic;
dbg_pd_inc_dqs : in std_logic;
dbg_pd_dec_dqs : in std_logic;
dbg_pd_disab_hyst : in std_logic;
dbg_pd_disab_hyst_0 : in std_logic;
dbg_pd_msb_sel : in std_logic_vector(3 downto 0);
dbg_pd_byte_sel : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_inc_rd_fps : in std_logic;
dbg_dec_rd_fps : in std_logic;
-- General debug ports - connect to internal nets as needed
dbg_phy_pd : out std_logic_vector(255 downto 0); -- Phase Detector
dbg_phy_read : out std_logic_vector(255 downto 0); -- Read datapath
dbg_phy_rdlvl : out std_logic_vector(255 downto 0); -- Read leveling calibration
dbg_phy_top : out std_logic_vector(255 downto 0) -- General PHY debug
);
end entity phy_top;
architecture arch of phy_top is
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of arch : ARCHITECTURE IS
"mig_v3_92_ddr3_V6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of arch : ARCHITECTURE IS "ddr3_V6_phy,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, LEVEL=PHY, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=2500, MEMORY_TYPE=SODIMM, MEMORY_PART=mt4jsf12864hz-1g4, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, BURST_MODE=4, BURST_TYPE=SEQ, OUTPUT_DRV=HIGH, RTT_NOM=60, REFCLK_FREQ=200, MMCM_ADV_BANDWIDTH=OPTIMIZED, CLKFBOUT_MULT_F=6, CLKOUT_DIVIDE=3, DEBUG_PORT=OFF, IODELAY_HP_MODE=ON, INTERNAL_VREF=0, DCI_INOUTS=1, CLASS_ADDR=I, INPUT_CLK_TYPE=SINGLE_ENDED}";
-- For reg dimm addign one extra cycle of latency for CWL. The new value
-- will be passed to phy_write and phy_data_io
function CALC_CWL_M return integer is
begin
if (REG_CTRL = "ON") then
return (nCWL + 1);
else
return nCWL;
end if;
end function;
-- function to AND the bits in a vectored signal
function AND_BR (inp_var: std_logic_vector)
return std_logic is
variable temp: std_logic := '1';
begin
for idx in inp_var'range loop
temp := temp and inp_var(idx);
end loop;
return temp;
end function;
-- function to OR the bits in a vectored signal
function OR_BR (inp_var: std_logic_vector)
return std_logic is
variable temp: std_logic := '0';
begin
for idx in inp_var'range loop
temp := temp or inp_var(idx);
end loop;
return temp;
end function;
-- Calculate number of slots in the system
function CALC_nSLOTS return integer is
begin
if (OR_BR(SLOT_1_CONFIG) = '1') then
return (2);
else
return (1);
end if;
end function;
-- Temp parameters used to force skipping or abbreviation of
-- initialization and calibration. In some cases logic blocks
-- may be disabled altogether.
function CALC_SIM_INIT_OPTION_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP" or
SIM_BYPASS_INIT_CAL = "FAST") then
return ("SKIP_PU_DLY");
else
return (SIM_INIT_OPTION);
end if;
end function;
function CALC_SIM_CAL_OPTION_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("SKIP_CAL");
elsif (SIM_BYPASS_INIT_CAL = "FAST") then
return ("FAST_CAL");
else
return (SIM_CAL_OPTION);
end if;
end function;
function CALC_WRLVL_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("OFF");
else
return (WRLVL);
end if;
end function;
function CALC_PHASE_DETECT_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("OFF");
else
return (PHASE_DETECT);
end if;
end function;
-- Parameter used to force skipping or abbreviation of initialization
-- and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
-- disables various other blocks depending on the option selected
-- This option should only be used during simulation. In the case of
-- the "SKIP" option, the testbench used should also not be modeling
-- propagation delays.
-- Allowable options = {"NONE", "SKIP", "FAST"}
-- "NONE" = options determined by the individual parameter settings
-- "SKIP" = skip power-up delay, skip calibration for read leveling,
-- write leveling, and phase detector. In the case of write
-- leveling and the phase detector, this means not instantiating
-- those blocks at all.
-- "FAST" = skip power-up delay, and calibrate (read leveling, write
-- leveling, and phase detector) only using one DQS group, and
-- apply the results to all other DQS groups.
constant SIM_INIT_OPTION_W : string := CALC_SIM_INIT_OPTION_W;
constant SIM_CAL_OPTION_W : string := CALC_SIM_CAL_OPTION_W;
constant WRLVL_W : string := CALC_WRLVL_W;
constant PHASE_DETECT_W : string := CALC_PHASE_DETECT_W;
-- Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
-- align DQ and DQS on writes. Round (up or down) value to nearest integer
constant SHIFT_TBY4_TAP : integer := integer((real(CLK_PERIOD) + (real(nCK_PER_CLK)*(1000000.0/(REFCLK_FREQ*64.0))*2.0) - 1.0) /
(real(nCK_PER_CLK)*(1000000.0/(REFCLK_FREQ*64.0)) * 4.0));
constant CWL_M : integer := CALC_CWL_M;
constant nSLOTS : integer := CALC_nSLOTS;
-- Temp parameter to enable disable PD based on the PD override parameter
-- Disabling phase detect below 250 MHz for the MIG 3.2 release
function CALC_PHASE_DETECT_TOP return string is
begin
if (CLK_PERIOD > 8000) then
return ("OFF");
else
return (PHASE_DETECT_W);
end if;
end function;
constant USE_PHASE_DETECT : string := CALC_PHASE_DETECT_TOP;
-- Param to determine if the configuration is an UDIMM configuration for DDR2
-- this parameter is used for advancing the chip select for frequencies above
-- 200 MHz.
function DDR2_EARLY_CS_CALC return integer is
begin
if ((CLK_PERIOD < 10000) and ( DQ_WIDTH >= 64) and (CK_WIDTH < 5) and
(DRAM_TYPE = "DDR2") and (REG_CTRL = "OFF")) then
return 1;
else
return 0;
end if;
end function;
constant DDR2_EARLY_CS : integer := DDR2_EARLY_CS_CALC;
signal calib_width : std_logic_vector(2 downto 0);
signal chip_cnt : std_logic_vector(1 downto 0);
signal chip_cnt_r : std_logic_vector(1 downto 0);
signal chip_cnt_r1 : std_logic_vector(1 downto 0);
signal clk_cpt : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal clk_rsync : std_logic_vector(3 downto 0);
signal dfi_rd_dqs : std_logic_vector(4*DQS_WIDTH - 1 downto 0);
signal dlyce_cpt : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dlyce_pd_cpt : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dlyce_rdlvl_cpt : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dlyce_rdlvl_rsync : std_logic_vector(3 downto 0);
signal dlyce_rsync : std_logic_vector(3 downto 0);
signal dlyinc_cpt : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dlyinc_pd_cpt : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dlyinc_pd_dqs : std_logic;
signal dlyinc_rdlvl_cpt : std_logic;
signal dlyinc_rdlvl_rsync : std_logic;
signal dlyinc_rsync : std_logic_vector(3 downto 0);
signal dlyrst_cpt : std_logic;
signal dlyrst_rsync : std_logic;
signal dlyval_dq : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dlyval_dqs : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dlyval_pd_dqs : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dlyval_rdlvl_dq : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dlyval_rdlvl_dqs : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dlyval_wrlvl_dq : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dlyval_wrlvl_dq_w : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dlyval_wrlvl_dqs : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dlyval_wrlvl_dqs_w : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal dm_ce : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dq_oe_n : std_logic_vector(4*DQS_WIDTH - 1 downto 0);
signal dqs_inv : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dqs_oe_n : std_logic_vector(4*DQS_WIDTH - 1 downto 0);
signal dqs_oe : std_logic;
signal dqs_rst : std_logic_vector((DQS_WIDTH*4) - 1 downto 0);
signal inv_dqs : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal mask_data_fall0 : std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
signal mask_data_fall1 : std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
signal mask_data_rise0 : std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
signal mask_data_rise1 : std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
signal pd_cal_done : std_logic;
signal pd_cal_start : std_logic;
signal pd_prech_req : std_logic;
signal phy_address0 : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal phy_address1 : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal phy_bank0 : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal phy_bank1 : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal phy_cas_n0 : std_logic;
signal phy_cas_n1 : std_logic;
signal phy_cke0 : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal phy_cke1 : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal phy_cs_n0 : std_logic_vector(CS_WIDTH*nCS_PER_RANK - 1 downto 0);
signal phy_cs_n1 : std_logic_vector(CS_WIDTH*nCS_PER_RANK - 1 downto 0);
signal phy_init_data_sel : std_logic;
signal phy_io_config : std_logic_vector(0 downto 0); --bus can be expanded later
signal phy_io_config_strobe : std_logic;
signal phy_odt0 : std_logic_vector(CS_WIDTH*nCS_PER_RANK - 1 downto 0);
signal phy_odt1 : std_logic_vector(CS_WIDTH*nCS_PER_RANK - 1 downto 0);
signal phy_ras_n0 : std_logic;
signal phy_ras_n1 : std_logic;
signal phy_rddata_en : std_logic;
signal phy_reset_n : std_logic;
signal phy_we_n0 : std_logic;
signal phy_we_n1 : std_logic;
signal phy_wrdata : std_logic_vector(4*DQ_WIDTH - 1 downto 0);
signal phy_wrdata_en : std_logic;
signal phy_wrdata_mask : std_logic_vector(4*(DQ_WIDTH / 8) - 1 downto 0);
signal prech_done : std_logic;
signal rank_cnt : std_logic_vector(1 downto 0);
signal rd_active_dly : std_logic_vector(4 downto 0);
signal rd_bitslip_cnt : std_logic_vector(2*DQS_WIDTH - 1 downto 0);
signal rd_clkdiv_inv : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rd_clkdly_cnt : std_logic_vector(2*DQS_WIDTH - 1 downto 0);
signal rd_data_fall0 : std_logic_vector(DQ_WIDTH - 1 downto 0);
signal rd_data_fall1 : std_logic_vector(DQ_WIDTH - 1 downto 0);
signal rd_data_rise0 : std_logic_vector(DQ_WIDTH - 1 downto 0);
signal rd_data_rise1 : std_logic_vector(DQ_WIDTH - 1 downto 0);
signal rd_dqs_fall0 : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rd_dqs_fall1 : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rd_dqs_rise0 : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rd_dqs_rise1 : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rdlvl_clkdiv_done : std_logic;
signal rdlvl_clkdiv_start : std_logic;
signal rdlvl_done : std_logic_vector(1 downto 0);
signal rdlvl_err : std_logic_vector(1 downto 0);
signal rdlvl_pat_resume : std_logic;
signal rdlvl_pat_resume_w : std_logic;
signal rdlvl_pat_err : std_logic;
signal rdlvl_pat_err_cnt : std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
signal rdlvl_prech_req : std_logic;
signal rdlvl_start : std_logic_vector(1 downto 0);
signal rst_rsync : std_logic_vector(3 downto 0);
signal wl_sm_start : std_logic;
signal wr_calib_dly : std_logic_vector(2*DQS_WIDTH - 1 downto 0);
signal wr_data_rise0 : std_logic_vector(DQ_WIDTH - 1 downto 0);
signal wr_data_fall0 : std_logic_vector(DQ_WIDTH - 1 downto 0);
signal wr_data_rise1 : std_logic_vector(DQ_WIDTH - 1 downto 0);
signal wr_data_fall1 : std_logic_vector(DQ_WIDTH - 1 downto 0);
signal wrcal_dly_w : std_logic_vector(2*DQS_WIDTH - 1 downto 0);
signal wrcal_err : std_logic;
signal wrlvl_active : std_logic;
signal wrlvl_done : std_logic;
signal wrlvl_err : std_logic;
signal wrlvl_start : std_logic;
signal dfi_rddata_valid_phy : std_logic;
signal dbg_wr_calib_clk_dly_cnt : std_logic;
signal rdpath_rdy : std_logic;
signal wrlvl_rank_done : std_logic;
signal out_oserdes_wc : std_logic;
-- X-HDL generated signals
signal xhdl1 : std_logic_vector(3 downto 0);
signal xhdl2 : std_logic_vector(3 downto 0);
-- Declare intermediate signals for referenced outputs
signal pll_lock_ck_fb_41 : std_logic;
signal dfi_rddata_37 : std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
signal dfi_rddata_valid_38 : std_logic;
signal dfi_init_complete_36 : std_logic;
signal ddr_ck_p_27 : std_logic_vector(CK_WIDTH - 1 downto 0);
signal ddr_ck_n_26 : std_logic_vector(CK_WIDTH - 1 downto 0);
signal ddr_addr_23 : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal ddr_ba_24 : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal ddr_ras_n_33 : std_logic;
signal ddr_cas_n_25 : std_logic;
signal ddr_we_n_35 : std_logic;
signal ddr_cs_n_29 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal ddr_cke_28 : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal ddr_odt_31 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal ddr_reset_n_34 : std_logic;
signal ddr_parity_32 : std_logic;
signal ddr_dm_30 : std_logic_vector(DM_WIDTH - 1 downto 0);
signal dbg_tap_cnt_during_wrlvl_21 : std_logic_vector(4 downto 0);
signal dbg_wl_edge_detect_valid_22 : std_logic;
signal dbg_rd_data_edge_detect_16 : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dbg_rdlvl_clk_17 : std_logic;
signal dbg_cpt_first_edge_cnt_0 : std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
signal dbg_cpt_second_edge_cnt_1 : std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
signal dbg_rd_bitslip_cnt_14 : std_logic_vector(3 * DQS_WIDTH - 1 downto 0);
signal dbg_rd_clkdly_cnt_15 : std_logic_vector(2 * DQS_WIDTH - 1 downto 0);
signal dbg_rd_active_dly_13 : std_logic_vector(4 downto 0);
signal dbg_phy_rdlvl_11 : std_logic_vector(255 downto 0);
signal dbg_phy_read_12 : std_logic_vector(255 downto 0);
signal dbg_dly_clk_3 : std_logic;
signal dbg_cpt_tap_cnt_2 : std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
signal dbg_rsync_tap_cnt_20 : std_logic_vector(19 downto 0);
signal dbg_dqs_tap_cnt_6 : std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
signal dbg_dq_tap_cnt_4 : std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
signal dbg_pd_clk_9 : std_logic;
signal dbg_phy_pd_10 : std_logic_vector(255 downto 0);
--------- component phy_init ---------
component phy_init
generic (
TCQ : integer := 100;
nCK_PER_CLK : integer := 2;
CLK_PERIOD : integer := 3333;
BANK_WIDTH : integer := 2;
COL_WIDTH : integer := 10;
nCS_PER_RANK : integer := 1;
DQ_WIDTH : integer := 64;
ROW_WIDTH : integer := 14;
CS_WIDTH : integer := 1;
CKE_WIDTH : integer := 1;
DRAM_TYPE : string := "DDR3";
REG_CTRL : string := "ON";
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
AL : string := "0";
BURST_MODE : string := "8";
BURST_TYPE : string := "SEQ";
nAL : integer := 0;
nCL : integer := 5;
nCWL : integer := 5;
tRFC : integer := 110000;
OUTPUT_DRV : string := "HIGH";
RTT_NOM : string := "60";
RTT_WR : string := "60";
WRLVL : string := "ON";
PHASE_DETECT : string := "ON";
DDR2_DQSN_ENABLE : string := "YES";
nSLOTS : integer := 1;
SIM_INIT_OPTION : string := "NONE";
SIM_CAL_OPTION : string := "NONE"
);
port (
clk : in std_logic;
rst : in std_logic;
calib_width : in std_logic_vector(2 downto 0);
rdpath_rdy : in std_logic;
wrlvl_done : in std_logic;
wrlvl_rank_done : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
wrlvl_active : out std_logic;
rdlvl_done : in std_logic_vector(1 downto 0);
rdlvl_start : out std_logic_vector(1 downto 0);
rdlvl_clkdiv_done : in std_logic;
rdlvl_clkdiv_start : out std_logic;
rdlvl_prech_req : in std_logic;
rdlvl_resume : in std_logic;
chip_cnt : out std_logic_vector(1 downto 0);
pd_cal_start : out std_logic;
pd_cal_done : in std_logic;
pd_prech_req : in std_logic;
prech_done : out std_logic;
dfi_init_complete : out std_logic;
phy_address0 : out std_logic_vector(ROW_WIDTH - 1 downto 0);
phy_address1 : out std_logic_vector(ROW_WIDTH - 1 downto 0);
phy_bank0 : out std_logic_vector(BANK_WIDTH - 1 downto 0);
phy_bank1 : out std_logic_vector(BANK_WIDTH - 1 downto 0);
phy_cas_n0 : out std_logic;
phy_cas_n1 : out std_logic;
phy_cke0 : out std_logic_vector(CKE_WIDTH - 1 downto 0);
phy_cke1 : out std_logic_vector(CKE_WIDTH - 1 downto 0);
phy_cs_n0 : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_cs_n1 : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_init_data_sel : out std_logic;
phy_odt0 : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_odt1 : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_ras_n0 : out std_logic;
phy_ras_n1 : out std_logic;
phy_reset_n : out std_logic;
phy_we_n0 : out std_logic;
phy_we_n1 : out std_logic;
phy_wrdata_en : out std_logic;
phy_wrdata : out std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
phy_rddata_en : out std_logic;
phy_ioconfig : out std_logic_vector(0 downto 0);
phy_ioconfig_en : out std_logic
);
end component;
--------- component phy_control_io ---------
component phy_control_io
generic (
TCQ : integer := 100;
BANK_WIDTH : integer := 2;
RANK_WIDTH : integer := 1;
nCS_PER_RANK : integer := 1;
CS_WIDTH : integer := 1;
CKE_WIDTH : integer := 1;
ROW_WIDTH : integer := 14;
WRLVL : string := "OFF";
nCWL : integer := 5;
DRAM_TYPE : string := "DDR3";
REG_CTRL : string := "ON";
REFCLK_FREQ : real := 300.0;
IODELAY_HP_MODE : string := "ON";
IODELAY_GRP : string := "IODELAY_MIG";
DDR2_EARLY_CS : integer := 0
);
port (
clk_mem : in std_logic;
clk : in std_logic;
rst : in std_logic;
mc_data_sel : in std_logic;
dfi_address0 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
dfi_address1 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
dfi_bank0 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_bank1 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_cas_n0 : in std_logic;
dfi_cas_n1 : in std_logic;
dfi_cke0 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
dfi_cke1 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
dfi_cs_n0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_cs_n1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_odt0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_odt1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_ras_n0 : in std_logic;
dfi_ras_n1 : in std_logic;
dfi_reset_n : in std_logic;
dfi_we_n0 : in std_logic;
dfi_we_n1 : in std_logic;
phy_address0 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
phy_address1 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
phy_bank0 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
phy_bank1 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
phy_cas_n0 : in std_logic;
phy_cas_n1 : in std_logic;
phy_cke0 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
phy_cke1 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
phy_cs_n0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_cs_n1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_odt0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_odt1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_ras_n0 : in std_logic;
phy_ras_n1 : in std_logic;
phy_reset_n : in std_logic;
phy_we_n0 : in std_logic;
phy_we_n1 : in std_logic;
ddr_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH - 1 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH - 1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_odt : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_parity : out std_logic;
ddr_reset_n : out std_logic
);
end component;
--------- component phy_clock_io ---------
component phy_clock_io
generic (
TCQ : integer := 100;
CK_WIDTH : integer := 2;
WRLVL : string := "OFF";
DRAM_TYPE : string := "DDR3";
REFCLK_FREQ : real := 300.0;
IODELAY_GRP : string := "IODELAY_MIG"
);
port (
clk_mem : in std_logic;
clk : in std_logic;
rst : in std_logic;
ddr_ck_p : out std_logic_vector(CK_WIDTH - 1 downto 0);
ddr_ck_n : out std_logic_vector(CK_WIDTH - 1 downto 0)
);
end component;
--------- component phy_data_io ---------
component phy_data_io
generic (
TCQ : integer := 100;
nCK_PER_CLK : integer := 2;
CLK_PERIOD : integer := 3000;
DRAM_WIDTH : integer := 8;
DM_WIDTH : integer := 9;
DQ_WIDTH : integer := 72;
DQS_WIDTH : integer := 9;
DRAM_TYPE : string := "DDR3";
nCWL : integer := 5;
WRLVL : string := "OFF";
REFCLK_FREQ : real := 300.0;
IBUF_LPWR_MODE : string := "OFF";
IODELAY_HP_MODE : string := "ON";
IODELAY_GRP : string := "IODELAY_MIG";
nDQS_COL0 : integer := 4;
nDQS_COL1 : integer := 4;
nDQS_COL2 : integer := 0;
nDQS_COL3 : integer := 0;
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"000000000000000000000000000003020100";
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000007060504";
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
USE_DM_PORT : integer := 1
);
port (
clk_mem : in std_logic;
clk : in std_logic;
clk_cpt : in std_logic_vector(DQS_WIDTH - 1 downto 0);
clk_rsync : in std_logic_vector(3 downto 0);
rst : in std_logic;
rst_rsync : in std_logic_vector(3 downto 0);
dlyval_dq : in std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dlyval_dqs : in std_logic_vector(5*DQS_WIDTH - 1 downto 0);
inv_dqs : in std_logic_vector(DQS_WIDTH - 1 downto 0);
wr_calib_dly : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
dqs_oe_n : in std_logic_vector(4*DQS_WIDTH - 1 downto 0);
dq_oe_n : in std_logic_vector(4*DQS_WIDTH - 1 downto 0);
dqs_rst : in std_logic_vector((DQS_WIDTH * 4) - 1 downto 0);
dm_ce : in std_logic_vector(DQS_WIDTH - 1 downto 0);
mask_data_rise0 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_fall0 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_rise1 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_fall1 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
wr_data_rise0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_rise1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_fall0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_fall1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_bitslip_cnt : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdly_cnt : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdiv_inv : in std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_data_rise0 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall0 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_rise1 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall1 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_dqs_rise0 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_fall0 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_rise1 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_fall1 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH - 1 downto 0);
ddr_dqs_p : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dq : inout std_logic_vector(DQ_WIDTH - 1 downto 0);
dbg_dqs_tap_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_dq_tap_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0)
);
end component;
--------- component phy_dly_ctrl ---------
component phy_dly_ctrl
generic (
TCQ : integer := 100;
DQ_WIDTH : integer := 64;
DQS_CNT_WIDTH : integer := 3;
DQS_WIDTH : integer := 8;
RANK_WIDTH : integer := 1;
nCWL : integer := 5;
REG_CTRL : string := "OFF";
WRLVL : string := "ON";
PHASE_DETECT : string := "ON";
DRAM_TYPE : string := "DDR3";
nDQS_COL0 : integer := 4;
nDQS_COL1 : integer := 4;
nDQS_COL2 : integer := 0;
nDQS_COL3 : integer := 0;
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"000000000000000000000000000003020100";
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000007060504";
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DEBUG_PORT : string := "OFF"
);
port (
clk : in std_logic;
rst : in std_logic;
clk_rsync : in std_logic_vector(3 downto 0);
rst_rsync : in std_logic_vector(3 downto 0);
wrlvl_done : in std_logic;
rdlvl_done : in std_logic_vector(1 downto 0);
pd_cal_done : in std_logic;
mc_data_sel : in std_logic;
mc_ioconfig : in std_logic_vector(RANK_WIDTH downto 0);
mc_ioconfig_en : in std_logic;
phy_ioconfig : in std_logic_vector(0 downto 0);
phy_ioconfig_en : in std_logic;
dqs_oe : in std_logic;
dlyval_wrlvl_dqs : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyval_wrlvl_dq : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyce_rdlvl_cpt : in std_logic_vector((DQS_WIDTH-1) downto 0);
dlyinc_rdlvl_cpt : in std_logic;
dlyce_rdlvl_rsync : in std_logic_vector(3 downto 0);
dlyinc_rdlvl_rsync : in std_logic;
dlyval_rdlvl_dq : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyval_rdlvl_dqs : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyce_pd_cpt : in std_logic_vector((DQS_WIDTH-1) downto 0);
dlyinc_pd_cpt : in std_logic_vector((DQS_WIDTH-1) downto 0);
dlyval_pd_dqs : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyval_dqs : out std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyval_dq : out std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyrst_cpt : out std_logic;
dlyce_cpt : out std_logic_vector((DQS_WIDTH-1) downto 0);
dlyinc_cpt : out std_logic_vector((DQS_WIDTH-1) downto 0);
dlyrst_rsync : out std_logic;
dlyce_rsync : out std_logic_vector(3 downto 0);
dlyinc_rsync : out std_logic_vector(3 downto 0);
dbg_pd_off : in std_logic
);
end component;
-------- component phy_write ---------
component phy_write
generic (
TCQ : integer := 100;
WRLVL : string := "ON";
DRAM_TYPE : string := "DDR3";
DQ_WIDTH : integer := 64;
DQS_WIDTH : integer := 8;
nCWL : integer := 5;
REG_CTRL : string := "OFF";
RANK_WIDTH : integer := 1;
CLKPERF_DLY_USED : string := "OFF"
);
port (
clk : in std_logic;
rst : in std_logic;
mc_data_sel : in std_logic;
wrlvl_active : in std_logic;
wrlvl_done : in std_logic;
inv_dqs : in std_logic_vector(DQS_WIDTH-1 downto 0);
wr_calib_dly : in std_logic_vector(2*DQS_WIDTH-1 downto 0);
dfi_wrdata : in std_logic_vector(4*DQ_WIDTH-1 downto 0);
dfi_wrdata_mask : in std_logic_vector((4*DQ_WIDTH/8)-1 downto 0);
dfi_wrdata_en : in std_logic;
mc_ioconfig_en : in std_logic;
mc_ioconfig : in std_logic_vector(RANK_WIDTH downto 0);
phy_wrdata_en : in std_logic;
phy_wrdata : in std_logic_vector(4*DQ_WIDTH-1 downto 0);
phy_ioconfig_en : in std_logic;
phy_ioconfig : in std_logic_vector(0 downto 0);
out_oserdes_wc : in std_logic;
dm_ce : out std_logic_vector(DQS_WIDTH-1 downto 0);
dq_oe_n : out std_logic_vector(4*DQS_WIDTH-1 downto 0);
dqs_oe_n : out std_logic_vector(4*DQS_WIDTH-1 downto 0);
dqs_rst : out std_logic_vector(4*DQS_WIDTH-1 downto 0);
dq_wc : out std_logic;
dqs_wc : out std_logic;
mask_data_rise0 : out std_logic_vector((DQ_WIDTH/8)-1 downto 0);
mask_data_fall0 : out std_logic_vector((DQ_WIDTH/8)-1 downto 0);
mask_data_rise1 : out std_logic_vector((DQ_WIDTH/8)-1 downto 0);
mask_data_fall1 : out std_logic_vector((DQ_WIDTH/8)-1 downto 0);
wl_sm_start : out std_logic;
wr_lvl_start : out std_logic;
wr_data_rise0 : out std_logic_vector(DQ_WIDTH-1 downto 0);
wr_data_fall0 : out std_logic_vector(DQ_WIDTH-1 downto 0);
wr_data_rise1 : out std_logic_vector(DQ_WIDTH-1 downto 0);
wr_data_fall1 : out std_logic_vector(DQ_WIDTH-1 downto 0)
);
end component;
--------- component phy_wrlvl ---------
component phy_wrlvl
generic (
TCQ : integer := 100;
DQS_CNT_WIDTH : integer := 3;
DQ_WIDTH : integer := 64;
SHIFT_TBY4_TAP : integer := 7;
DQS_WIDTH : integer := 8;
DRAM_WIDTH : integer := 8;
CS_WIDTH : integer := 1;
CAL_WIDTH : string := "HALF";
DQS_TAP_CNT_INDEX : integer := 42;
SIM_CAL_OPTION : string := "NONE"
);
port (
clk : in std_logic;
rst : in std_logic;
calib_width : in std_logic_vector(2 downto 0);
rank_cnt : in std_logic_vector(1 downto 0);
wr_level_start : in std_logic;
wl_sm_start : in std_logic;
rd_data_rise0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rdlvl_error : in std_logic;
rdlvl_err_byte : in std_logic_vector((DQS_CNT_WIDTH-1) downto 0);
wr_level_done : out std_logic;
wrlvl_rank_done : out std_logic;
dlyval_wr_dqs : out std_logic_vector(DQS_TAP_CNT_INDEX downto 0);
dlyval_wr_dq : out std_logic_vector(DQS_TAP_CNT_INDEX downto 0);
inv_dqs : out std_logic_vector((DQS_WIDTH-1) downto 0);
rdlvl_resume : out std_logic;
wr_calib_dly : out std_logic_vector((2*DQS_WIDTH-1) downto 0);
wrcal_err : out std_logic;
wrlvl_err : out std_logic;
dbg_wl_tap_cnt : out std_logic_vector(4 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_rd_data_edge_detect : out std_logic_vector((DQS_WIDTH-1) downto 0);
dbg_rd_data_inv_edge_detect : out std_logic_vector((DQS_WIDTH-1) downto 0);
dbg_dqs_count : out std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_wl_state : out std_logic_vector(3 downto 0)
);
end component;
--------- component phy_read ---------
component phy_read
generic (
TCQ : integer := 100;
nCK_PER_CLK : integer := 2;
CLK_PERIOD : integer := 3333;
REFCLK_FREQ : real := 300.0;
DQS_WIDTH : integer := 8;
DQ_WIDTH : integer := 64;
DRAM_WIDTH : integer := 8;
IODELAY_GRP : string := "IODELAY_MIG";
nDQS_COL0 : integer := 4;
nDQS_COL1 : integer := 4;
nDQS_COL2 : integer := 0;
nDQS_COL3 : integer := 0;
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"11100F0E0D0C0B0A09080706050403020100";
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000"
);
port (
clk_mem : in std_logic;
clk : in std_logic;
rst : in std_logic;
clk_rd_base : in std_logic;
dlyrst_cpt : in std_logic;
dlyce_cpt : in std_logic_vector(DQS_WIDTH-1 downto 0);
dlyinc_cpt : in std_logic_vector(DQS_WIDTH-1 downto 0);
dlyrst_rsync : in std_logic;
dlyce_rsync : in std_logic_vector(3 downto 0);
dlyinc_rsync : in std_logic_vector(3 downto 0);
clk_cpt : out std_logic_vector(DQS_WIDTH-1 downto 0);
clk_rsync : out std_logic_vector(3 downto 0);
rst_rsync : out std_logic_vector(3 downto 0);
rdpath_rdy : out std_logic;
mc_data_sel : in std_logic;
rd_active_dly : in std_logic_vector(4 downto 0);
rd_data_rise0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_fall0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_rise1 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_fall1 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_dqs_rise0 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_fall0 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_rise1 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_fall1 : in std_logic_vector((DQS_WIDTH-1) downto 0);
dfi_rddata_en : in std_logic;
phy_rddata_en : in std_logic;
dfi_rddata_valid : out std_logic;
dfi_rddata_valid_phy : out std_logic;
dfi_rddata : out std_logic_vector((4*DQ_WIDTH-1) downto 0);
dfi_rd_dqs : out std_logic_vector((4*DQS_WIDTH-1) downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_rsync_tap_cnt : out std_logic_vector(19 downto 0);
dbg_phy_read : out std_logic_vector(255 downto 0)
);
end component;
--------- component phy_rdlvl ---------
component phy_rdlvl
generic (
TCQ : integer := 100;
nCK_PER_CLK : integer := 2;
CLK_PERIOD : integer := 3333;
REFCLK_FREQ : integer := 300;
DQ_WIDTH : integer := 64;
DQS_CNT_WIDTH : integer := 3;
DQS_WIDTH : integer := 2;
DRAM_WIDTH : integer := 8;
DRAM_TYPE : string := "DDR3";
PD_TAP_REQ : integer := 10;
nCL : integer := 5;
SIM_CAL_OPTION : string := "FAST_WIN_DETECT";
REG_CTRL : string := "ON";
DEBUG_PORT : string := "ON"
);
port (
clk : in std_logic;
rst : in std_logic;
rdlvl_start : in std_logic_vector(1 downto 0);
rdlvl_clkdiv_start : in std_logic;
rdlvl_rd_active : in std_logic;
rdlvl_done : out std_logic_vector(1 downto 0);
rdlvl_clkdiv_done : out std_logic;
rdlvl_err : out std_logic_vector(1 downto 0);
rdlvl_prech_req : out std_logic;
prech_done : in std_logic;
rd_data_rise0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_rise1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
dlyce_cpt : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dlyinc_cpt : out std_logic;
dlyce_rsync : out std_logic_vector(3 downto 0);
dlyinc_rsync : out std_logic;
dlyval_dq : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dlyval_dqs : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
rd_bitslip_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdly_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_active_dly : out std_logic_vector(4 downto 0);
rdlvl_pat_resume : in std_logic;
rdlvl_pat_err : out std_logic;
rdlvl_pat_err_cnt : out std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
rd_clkdiv_inv : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_rd_bitslip_cnt : out std_logic_vector(3*DQS_WIDTH - 1 downto 0);
dbg_rd_clkdiv_inv : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dbg_rd_clkdly_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
dbg_rd_active_dly : out std_logic_vector(4 downto 0);
dbg_idel_up_all : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_rsync : in std_logic;
dbg_idel_down_rsync : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_rsync : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_sel_all_idel_rsync : in std_logic;
dbg_phy_rdlvl : out std_logic_vector(255 downto 0)
);
end component;
--------- component phy_pd_top ---------
component phy_pd_top
generic (
TCQ : integer := 100;
DQS_CNT_WIDTH : integer := 3;
DQS_WIDTH : integer := 8;
SIM_CAL_OPTION : string := "NONE";
PD_LHC_WIDTH : integer := 16;
PD_CALIB_MODE : string := "PARALLEL";
PD_MSB_SEL : integer := 8;
PD_DQS0_ONLY : string := "ON";
DEBUG_PORT : string := "OFF"
);
port (
clk : in std_logic;
rst : in std_logic;
pd_cal_start : in std_logic;
pd_cal_done : out std_logic;
dfi_init_complete : in std_logic;
read_valid : in std_logic;
pd_PSEN : out std_logic;
pd_PSINCDEC : out std_logic;
dlyval_rdlvl_dqs : in std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dlyce_pd_cpt : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dlyinc_pd_cpt : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dlyval_pd_dqs : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
rd_dqs_rise0 : in std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_fall0 : in std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_rise1 : in std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_fall1 : in std_logic_vector(DQS_WIDTH - 1 downto 0);
pd_prech_req : out std_logic;
prech_done : in std_logic;
dbg_pd_off : in std_logic;
dbg_pd_maintain_off : in std_logic;
dbg_pd_maintain_0_only : in std_logic;
dbg_pd_inc_cpt : in std_logic;
dbg_pd_dec_cpt : in std_logic;
dbg_pd_inc_dqs : in std_logic;
dbg_pd_dec_dqs : in std_logic;
dbg_pd_disab_hyst : in std_logic;
dbg_pd_disab_hyst_0 : in std_logic;
dbg_pd_msb_sel : in std_logic_vector(3 downto 0);
dbg_pd_byte_sel : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_inc_rd_fps : in std_logic;
dbg_dec_rd_fps : in std_logic;
dbg_phy_pd : out std_logic_vector(255 downto 0)
);
end component;
--------- component phy_ocb_mon_top ---------
component phy_ocb_mon_top
generic (
TCQ : integer := 100;
MMCM_ADV_PS_WA : string := "OFF";
DRAM_TYPE : string := "DDR3";
CLKPERF_DLY_USED : string := "OFF";
SIM_CAL_OPTION : string := "NONE"
);
port (
dbg_ocb_mon_off : in std_logic;
dbg_ocb_mon_clk : out std_logic;
dbg_ocb_mon : out std_logic_vector(255 downto 0);
ocb_mon_PSEN : out std_logic;
ocb_mon_PSINCDEC : out std_logic;
ocb_mon_calib_done : out std_logic;
ocb_mon_PSDONE : in std_logic;
ocb_mon_go : in std_logic;
clk_mem : in std_logic;
clk : in std_logic;
clk_wr : in std_logic;
rst : in std_logic
);
end component;
begin
-- Drive referenced outputs
dfi_rddata <= dfi_rddata_37;
dfi_rddata_valid <= dfi_rddata_valid_38;
dfi_init_complete <= dfi_init_complete_36;
ddr_ck_p <= ddr_ck_p_27;
ddr_ck_n <= ddr_ck_n_26;
ddr_addr <= ddr_addr_23;
ddr_ba <= ddr_ba_24;
ddr_ras_n <= ddr_ras_n_33;
ddr_cas_n <= ddr_cas_n_25;
ddr_we_n <= ddr_we_n_35;
ddr_cs_n <= ddr_cs_n_29;
ddr_cke <= ddr_cke_28;
ddr_odt <= ddr_odt_31;
ddr_reset_n <= ddr_reset_n_34;
ddr_parity <= ddr_parity_32;
ddr_dm <= ddr_dm_30;
dbg_tap_cnt_during_wrlvl <= dbg_tap_cnt_during_wrlvl_21;
dbg_wl_edge_detect_valid <= dbg_wl_edge_detect_valid_22;
dbg_rd_data_edge_detect <= dbg_rd_data_edge_detect_16;
dbg_cpt_first_edge_cnt <= dbg_cpt_first_edge_cnt_0;
dbg_cpt_second_edge_cnt <= dbg_cpt_second_edge_cnt_1;
dbg_rd_bitslip_cnt <= dbg_rd_bitslip_cnt_14;
dbg_rd_clkdly_cnt <= dbg_rd_clkdly_cnt_15;
dbg_rd_active_dly <= dbg_rd_active_dly_13;
dbg_phy_rdlvl <= dbg_phy_rdlvl_11;
dbg_phy_read <= dbg_phy_read_12;
dbg_cpt_tap_cnt <= dbg_cpt_tap_cnt_2;
dbg_rsync_tap_cnt <= dbg_rsync_tap_cnt_20;
dbg_dqs_tap_cnt <= dbg_dqs_tap_cnt_6;
dbg_dq_tap_cnt <= dbg_dq_tap_cnt_4;
dbg_phy_pd <= dbg_phy_pd_10;
--***************************************************************************
-- Debug
--***************************************************************************
-- Captured data in clk domain
-- NOTE: Prior to MIG 3.4, this data was synchronized to CLK_RSYNC domain
-- But was never connected beyond PHY_TOP (at the MEM_INTFC level, this
-- port is never used, and instead DFI_RDDATA was routed to DBG_RDDATA)
dbg_rd_data <= dfi_rddata_37;
-- Unused for now - use these as needed to bring up lower level signals
dbg_phy_top <= (others => '0');
-- Write Level and write calibration debug observation ports
dbg_wrlvl_start <= wrlvl_start;
dbg_wrlvl_done <= wrlvl_done;
dbg_wrlvl_err <= wrlvl_err;
dbg_wl_dqs_inverted <= dqs_inv;
dbg_wl_odelay_dqs_tap_cnt <= dlyval_wrlvl_dqs;
dbg_wl_odelay_dq_tap_cnt <= dlyval_wrlvl_dq;
dbg_wr_calib_clk_delay <= wr_calib_dly;
-- Read Level debug observation ports
dbg_rdlvl_start <= rdlvl_start;
dbg_rdlvl_done <= rdlvl_done;
dbg_rdlvl_err <= rdlvl_err;
--***************************************************************************
-- Write leveling dependent signals
--***************************************************************************
rdlvl_pat_resume_w <= rdlvl_pat_resume when (WRLVL_W = "ON") else '0';
dqs_inv <= inv_dqs when (WRLVL_W = "ON") else (others => '0');
wrcal_dly_w <= wr_calib_dly when (WRLVL_W = "ON") else (others => '0');
-- Rank count (chip_cnt) from phy_init for write bitslip during read leveling
-- Rank count (io_config) from MC during normal operation
process (rst, dfi_init_complete_36, chip_cnt_r1, io_config)
begin
if ((rst = '1') or (RANK_WIDTH = 0)) then
rank_cnt <= "00";
else
if (dfi_init_complete_36 = '0') then
rank_cnt <= chip_cnt_r1;
else
-- io_config[1:0] causes warning with VCS
-- io_config[RANK_WIDTH-1:0] causes error with VCS
if (RANK_WIDTH = 2) then
rank_cnt <= io_config(1 downto 0);
else
rank_cnt <= ('0' & io_config(0));
end if;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
chip_cnt_r <= chip_cnt after (TCQ)*1 ps;
chip_cnt_r1 <= chip_cnt_r after (TCQ)*1 ps;
end if;
end process;
--*****************************************************************
-- DETERMINE DQ/DQS output delay values
-- 1. If WRLVL disabled: DQS = 0 delay, DQ = 90 degrees delay
-- 2. If WRLVL enabled: DQS and DQ delays are determined during
-- write leveling
-- For multi-rank design the appropriate rank values will be sent to
-- phy_write, phy_dly_ctrl, and phy_data_io
--*****************************************************************
gen_offset_tap: for offset_i in 0 to (DQS_WIDTH-1) generate
gen_offset_tap_dbg: if (DEBUG_PORT = "ON") generate
-- Allow debug port to modify the post-write-leveling ODELAY
-- values of DQ and DQS. This can be used to measure DQ-DQS
-- (as well as tDQSS) timing margin on writes
dlyval_wrlvl_dq(5*offset_i+4 downto 5*offset_i) <=
dbg_wr_dq_tap_set(5*offset_i+4 downto 5*offset_i) when ((WRLVL_W = "ON") and ((wrlvl_done and dbg_wr_tap_set_en)= '1')) else
dlyval_wrlvl_dq_w(5*offset_i+4 downto 5*offset_i) when ((WRLVL_W = "ON") and not((wrlvl_done and dbg_wr_tap_set_en)= '1')) else
dbg_wr_dq_tap_set(5*offset_i+4 downto 5*offset_i) when (not(WRLVL_W = "ON") and (dbg_wr_tap_set_en = '1')) else
std_logic_vector(to_unsigned(SHIFT_TBY4_TAP,5));
dlyval_wrlvl_dqs(5*offset_i+4 downto 5*offset_i) <=
dbg_wr_dqs_tap_set(5*offset_i+4 downto 5*offset_i) when ((WRLVL_W = "ON") and ((wrlvl_done and dbg_wr_tap_set_en)= '1')) else
dlyval_wrlvl_dqs_w(5*offset_i+4 downto 5*offset_i) when ((WRLVL_W = "ON") and not((wrlvl_done and dbg_wr_tap_set_en)= '1')) else
dbg_wr_dqs_tap_set(5*offset_i+4 downto 5*offset_i) when (not(WRLVL_W = "ON") and (dbg_wr_tap_set_en = '1')) else
(others => '0');
end generate;
gen_offset_tap_nodbg: if (not(DEBUG_PORT = "ON")) generate
dlyval_wrlvl_dq(5*offset_i+4 downto 5*offset_i) <= dlyval_wrlvl_dq_w(5*offset_i+4 downto 5*offset_i) when (WRLVL_W = "ON") else
std_logic_vector(to_unsigned(SHIFT_TBY4_TAP,5));
dlyval_wrlvl_dqs(5*offset_i+4 downto 5*offset_i) <= dlyval_wrlvl_dqs_w(5*offset_i+4 downto 5*offset_i) when (WRLVL_W = "ON") else
(others => '0');
end generate;
end generate;
--***************************************************************************
-- Used for multi-rank case to determine the number of ranks to be calibrated
-- The number of ranks to be calibrated can be less than the CS_WIDTH (rank
-- width)
-- Assumes at least one rank per slot to be calibrated
-- If nSLOTS equals 1 slot_1_present input will be ignored
-- Assumes CS_WIDTH to be 1, 2, 3, or 4
--***************************************************************************
gen_single_slot : if (nSLOTS = 1) generate
xhdl1 <= slot_0_present(0) & slot_0_present(1) & slot_0_present(2) & slot_0_present(3);
process (clk)
begin
if (clk'event and clk = '1') then
case xhdl1 is
-- single slot quad rank calibration
when "1111" =>
if (CAL_WIDTH = "FULL") then
calib_width <= "100" after (TCQ)*1 ps;
else
calib_width <= "010" after (TCQ)*1 ps;
end if;
-- single slot dual rank calibration
when "1100" =>
if (CAL_WIDTH = "FULL") then
calib_width <= "010" after (TCQ)*1 ps;
else
calib_width <= "001" after (TCQ)*1 ps;
end if;
when others =>
calib_width <= "001" after (TCQ)*1 ps;
end case;
end if;
end process;
end generate;
gen_dual_slot : if (nSLOTS = 2) generate
xhdl2 <= slot_0_present(0) & slot_0_present(1) & slot_1_present(0) & slot_1_present(1);
process (clk)
begin
if (clk'event and clk = '1') then
case xhdl2 is
-- two slots single rank per slot CAL_WIDTH ignored since one rank
-- per slot must be calibrated
when "1010" =>
calib_width <= "010" after (TCQ)*1 ps;
-- two slots single rank in slot0
when "1000" =>
calib_width <= "001" after (TCQ)*1 ps;
-- two slots single rank in slot1
when "0010" =>
calib_width <= "001" after (TCQ)*1 ps;
-- two slots two ranks per slot calibration
when "1111" =>
if (CAL_WIDTH = "FULL") then
calib_width <= "100" after (TCQ)*1 ps;
else
calib_width <= "010" after (TCQ)*1 ps;
end if;
-- two slots: 2 ranks in slot0, 1 rank in slot1
when "1110" =>
if (CAL_WIDTH = "FULL") then
calib_width <= "011" after (TCQ)*1 ps;
else
calib_width <= "010" after (TCQ)*1 ps;
end if;
-- two slots: 2 ranks in slot0, none in slot1
when "1100" =>
if (CAL_WIDTH = "FULL") then
calib_width <= "010" after (TCQ)*1 ps;
else
calib_width <= "001" after (TCQ)*1 ps;
end if;
-- two slots: 1 rank in slot0, 2 ranks in slot1
when "1011" =>
if (CAL_WIDTH = "FULL") then
calib_width <= "011" after (TCQ)*1 ps;
else
calib_width <= "010" after (TCQ)*1 ps;
end if;
-- two slots: none in slot0, 2 ranks in slot1
when "0011" =>
if (CAL_WIDTH = "FULL") then
calib_width <= "010" after (TCQ)*1 ps;
else
calib_width <= "001" after (TCQ)*1 ps;
end if;
when others =>
calib_width <= "010" after (TCQ)*1 ps;
end case;
end if;
end process;
end generate;
--***************************************************************************
-- Initialization / Master PHY state logic (overall control during memory
-- init, timing leveling)
--***************************************************************************
u_phy_init : phy_init
generic map (
tcq => TCQ,
nck_per_clk => nCK_PER_CLK,
clk_period => CLK_PERIOD,
dram_type => DRAM_TYPE,
bank_width => BANK_WIDTH,
col_width => COL_WIDTH,
ncs_per_rank => nCS_PER_RANK,
dq_width => DQ_WIDTH,
row_width => ROW_WIDTH,
cs_width => CS_WIDTH,
cke_width => CKE_WIDTH,
calib_row_add => CALIB_ROW_ADD,
calib_col_add => CALIB_COL_ADD,
calib_ba_add => CALIB_BA_ADD,
al => AL,
burst_mode => BURST_MODE,
burst_type => BURST_TYPE,
nal => nAL,
ncl => nCL,
ncwl => nCWL,
trfc => tRFC,
output_drv => OUTPUT_DRV,
reg_ctrl => REG_CTRL,
rtt_nom => RTT_NOM,
rtt_wr => RTT_WR,
wrlvl => WRLVL_W,
phase_detect => USE_PHASE_DETECT,
nslots => nSLOTS,
sim_init_option => SIM_INIT_OPTION_W,
sim_cal_option => SIM_CAL_OPTION_W
)
port map (
clk => clk,
rst => rst,
calib_width => calib_width,
rdpath_rdy => rdpath_rdy,
wrlvl_done => wrlvl_done,
wrlvl_rank_done => wrlvl_rank_done,
wrlvl_active => wrlvl_active,
slot_0_present => slot_0_present,
slot_1_present => slot_1_present,
rdlvl_done => rdlvl_done,
rdlvl_start => rdlvl_start,
rdlvl_clkdiv_done => rdlvl_clkdiv_done,
rdlvl_clkdiv_start => rdlvl_clkdiv_start,
rdlvl_prech_req => rdlvl_prech_req,
rdlvl_resume => rdlvl_pat_resume_w,
chip_cnt => chip_cnt,
pd_cal_start => pd_cal_start,
pd_cal_done => pd_cal_done,
pd_prech_req => pd_prech_req,
prech_done => prech_done,
dfi_init_complete => dfi_init_complete_36,
phy_address0 => phy_address0,
phy_address1 => phy_address1,
phy_bank0 => phy_bank0,
phy_bank1 => phy_bank1,
phy_cas_n0 => phy_cas_n0,
phy_cas_n1 => phy_cas_n1,
phy_cke0 => phy_cke0,
phy_cke1 => phy_cke1,
phy_cs_n0 => phy_cs_n0,
phy_cs_n1 => phy_cs_n1,
phy_init_data_sel => phy_init_data_sel,
phy_odt0 => phy_odt0,
phy_odt1 => phy_odt1,
phy_ras_n0 => phy_ras_n0,
phy_ras_n1 => phy_ras_n1,
phy_reset_n => phy_reset_n,
phy_we_n0 => phy_we_n0,
phy_we_n1 => phy_we_n1,
phy_wrdata_en => phy_wrdata_en,
phy_wrdata => phy_wrdata,
phy_rddata_en => phy_rddata_en,
phy_ioconfig => phy_io_config,
phy_ioconfig_en => phy_io_config_strobe
);
--*****************************************************************
-- Control/Address MUX and IOB logic
--*****************************************************************
u_phy_control_io : phy_control_io
generic map (
tcq => TCQ,
bank_width => BANK_WIDTH,
rank_width => RANK_WIDTH,
ncs_per_rank => nCS_PER_RANK,
cs_width => CS_WIDTH,
row_width => ROW_WIDTH,
cke_width => CKE_WIDTH,
wrlvl => WRLVL_W,
ncwl => CWL_M,
dram_type => DRAM_TYPE,
reg_ctrl => REG_CTRL,
refclk_freq => REFCLK_FREQ,
iodelay_hp_mode => IODELAY_HP_MODE,
iodelay_grp => IODELAY_GRP,
ddr2_early_cs => DDR2_EARLY_CS
)
port map (
clk_mem => clk_mem,
clk => clk,
rst => rst,
mc_data_sel => phy_init_data_sel,
dfi_address0 => dfi_address0,
dfi_address1 => dfi_address1,
dfi_bank0 => dfi_bank0,
dfi_bank1 => dfi_bank1,
dfi_cas_n0 => dfi_cas_n0,
dfi_cas_n1 => dfi_cas_n1,
dfi_cke0 => dfi_cke0,
dfi_cke1 => dfi_cke1,
dfi_cs_n0 => dfi_cs_n0,
dfi_cs_n1 => dfi_cs_n1,
dfi_odt0 => dfi_odt0,
dfi_odt1 => dfi_odt1,
dfi_ras_n0 => dfi_ras_n0,
dfi_ras_n1 => dfi_ras_n1,
dfi_reset_n => dfi_reset_n,
dfi_we_n0 => dfi_we_n0,
dfi_we_n1 => dfi_we_n1,
phy_address0 => phy_address0,
phy_address1 => phy_address1,
phy_bank0 => phy_bank0,
phy_bank1 => phy_bank1,
phy_cas_n0 => phy_cas_n0,
phy_cas_n1 => phy_cas_n1,
phy_cke0 => phy_cke0,
phy_cke1 => phy_cke1,
phy_cs_n0 => phy_cs_n0,
phy_cs_n1 => phy_cs_n1,
phy_odt0 => phy_odt0,
phy_odt1 => phy_odt1,
phy_ras_n0 => phy_ras_n0,
phy_ras_n1 => phy_ras_n1,
phy_reset_n => phy_reset_n,
phy_we_n0 => phy_we_n0,
phy_we_n1 => phy_we_n1,
ddr_addr => ddr_addr_23,
ddr_ba => ddr_ba_24,
ddr_ras_n => ddr_ras_n_33,
ddr_cas_n => ddr_cas_n_25,
ddr_we_n => ddr_we_n_35,
ddr_cke => ddr_cke_28,
ddr_cs_n => ddr_cs_n_29,
ddr_odt => ddr_odt_31,
ddr_parity => ddr_parity_32,
ddr_reset_n => ddr_reset_n_34
);
--*****************************************************************
-- Memory clock forwarding and feedback
--*****************************************************************
u_phy_clock_io : phy_clock_io
generic map (
tcq => TCQ,
ck_width => CK_WIDTH,
wrlvl => WRLVL_W,
dram_type => DRAM_TYPE,
refclk_freq => REFCLK_FREQ,
iodelay_grp => IODELAY_GRP
)
port map (
clk_mem => clk_mem,
clk => clk,
rst => rst,
ddr_ck_p => ddr_ck_p_27,
ddr_ck_n => ddr_ck_n_26
);
--*****************************************************************
-- Data-related IOBs (data, strobe, mask), and regional clock buffers
-- Also includes output clock IOBs, and external feedback clock
--*****************************************************************
u_phy_data_io : phy_data_io
generic map (
tcq => TCQ,
nck_per_clk => nCK_PER_CLK,
clk_period => CLK_PERIOD,
dram_type => DRAM_TYPE,
dram_width => DRAM_WIDTH,
dm_width => DM_WIDTH,
dq_width => DQ_WIDTH,
dqs_width => DQS_WIDTH,
ncwl => CWL_M,
wrlvl => WRLVL_W,
refclk_freq => REFCLK_FREQ,
ibuf_lpwr_mode => IBUF_LPWR_MODE,
iodelay_hp_mode => IODELAY_HP_MODE,
iodelay_grp => IODELAY_GRP,
ndqs_col0 => nDQS_COL0,
ndqs_col1 => nDQS_COL1,
ndqs_col2 => nDQS_COL2,
ndqs_col3 => nDQS_COL3,
dqs_loc_col0 => DQS_LOC_COL0,
dqs_loc_col1 => DQS_LOC_COL1,
dqs_loc_col2 => DQS_LOC_COL2,
dqs_loc_col3 => DQS_LOC_COL3,
use_dm_port => USE_DM_PORT
)
port map (
clk_mem => clk_mem,
clk => clk,
clk_cpt => clk_cpt,
clk_rsync => clk_rsync,
rst => rst,
rst_rsync => rst_rsync,
-- IODELAY I/F
dlyval_dq => dlyval_dq,
dlyval_dqs => dlyval_dqs,
-- Write datapath I/F
inv_dqs => dqs_inv,
wr_calib_dly => wrcal_dly_w,
dqs_oe_n => dqs_oe_n,
dq_oe_n => dq_oe_n,
dqs_rst => dqs_rst,
dm_ce => dm_ce,
mask_data_rise0 => mask_data_rise0,
mask_data_fall0 => mask_data_fall0,
mask_data_rise1 => mask_data_rise1,
mask_data_fall1 => mask_data_fall1,
wr_data_rise0 => wr_data_rise0,
wr_data_fall0 => wr_data_fall0,
wr_data_rise1 => wr_data_rise1,
wr_data_fall1 => wr_data_fall1,
-- Read datapath I/F
rd_bitslip_cnt => rd_bitslip_cnt,
rd_clkdly_cnt => rd_clkdly_cnt,
rd_clkdiv_inv => rd_clkdiv_inv,
rd_data_rise0 => rd_data_rise0,
rd_data_fall0 => rd_data_fall0,
rd_data_rise1 => rd_data_rise1,
rd_data_fall1 => rd_data_fall1,
rd_dqs_rise0 => rd_dqs_rise0,
rd_dqs_fall0 => rd_dqs_fall0,
rd_dqs_rise1 => rd_dqs_rise1,
rd_dqs_fall1 => rd_dqs_fall1,
-- DDR3 bus signals
ddr_dm => ddr_dm_30,
ddr_dqs_p => ddr_dqs_p,
ddr_dqs_n => ddr_dqs_n,
ddr_dq => ddr_dq,
-- Debug signals
dbg_dqs_tap_cnt => dbg_dqs_tap_cnt_6,
dbg_dq_tap_cnt => dbg_dq_tap_cnt_4
);
--*****************************************************************
-- IODELAY control logic
--*****************************************************************
u_phy_dly_ctrl : phy_dly_ctrl
generic map (
tcq => TCQ,
dq_width => DQ_WIDTH,
dqs_cnt_width => DQS_CNT_WIDTH,
dqs_width => DQS_WIDTH,
rank_width => RANK_WIDTH,
ncwl => CWL_M,
reg_ctrl => REG_CTRL,
wrlvl => WRLVL_W,
phase_detect => USE_PHASE_DETECT,
dram_type => DRAM_TYPE,
ndqs_col0 => nDQS_COL0,
ndqs_col1 => nDQS_COL1,
ndqs_col2 => nDQS_COL2,
ndqs_col3 => nDQS_COL3,
dqs_loc_col0 => DQS_LOC_COL0,
dqs_loc_col1 => DQS_LOC_COL1,
dqs_loc_col2 => DQS_LOC_COL2,
dqs_loc_col3 => DQS_LOC_COL3,
debug_port => DEBUG_PORT
)
port map (
clk => clk,
rst => rst,
clk_rsync => clk_rsync,
rst_rsync => rst_rsync,
wrlvl_done => wrlvl_done,
rdlvl_done => rdlvl_done,
pd_cal_done => pd_cal_done,
mc_data_sel => phy_init_data_sel,
mc_ioconfig => io_config,
mc_ioconfig_en => io_config_strobe,
phy_ioconfig => phy_io_config,
phy_ioconfig_en => phy_io_config_strobe,
dqs_oe => dqs_oe,
dlyval_wrlvl_dqs => dlyval_wrlvl_dqs,
dlyval_wrlvl_dq => dlyval_wrlvl_dq,
dlyce_rdlvl_cpt => dlyce_rdlvl_cpt,
dlyinc_rdlvl_cpt => dlyinc_rdlvl_cpt,
dlyce_rdlvl_rsync => dlyce_rdlvl_rsync,
dlyinc_rdlvl_rsync => dlyinc_rdlvl_rsync,
dlyval_rdlvl_dq => dlyval_rdlvl_dq,
dlyval_rdlvl_dqs => dlyval_rdlvl_dqs,
dlyce_pd_cpt => dlyce_pd_cpt,
dlyinc_pd_cpt => dlyinc_pd_cpt,
dlyval_pd_dqs => dlyval_pd_dqs,
dlyval_dqs => dlyval_dqs,
dlyval_dq => dlyval_dq,
dlyrst_cpt => dlyrst_cpt,
dlyce_cpt => dlyce_cpt,
dlyinc_cpt => dlyinc_cpt,
dlyrst_rsync => dlyrst_rsync,
dlyce_rsync => dlyce_rsync,
dlyinc_rsync => dlyinc_rsync,
dbg_pd_off => dbg_pd_off
);
--*****************************************************************
-- Write path logic (datapath, tri-state enable)
--*****************************************************************
u_phy_write : phy_write
generic map (
tcq => TCQ,
wrlvl => WRLVL_W,
dq_width => DQ_WIDTH,
dqs_width => DQS_WIDTH,
dram_type => DRAM_TYPE,
rank_width => RANK_WIDTH,
ncwl => CWL_M,
REG_CTRL => REG_CTRL
)
port map (
clk => clk,
rst => rst,
mc_data_sel => phy_init_data_sel,
wrlvl_active => wrlvl_active,
wrlvl_done => wrlvl_done,
inv_dqs => dqs_inv,
wr_calib_dly => wrcal_dly_w,
dfi_wrdata => dfi_wrdata,
dfi_wrdata_mask => dfi_wrdata_mask,
dfi_wrdata_en => dfi_wrdata_en,
mc_ioconfig_en => io_config_strobe,
mc_ioconfig => io_config,
phy_wrdata => phy_wrdata,
phy_wrdata_en => phy_wrdata_en,
phy_ioconfig_en => phy_io_config_strobe,
phy_ioconfig => phy_io_config,
dm_ce => dm_ce,
dq_oe_n => dq_oe_n,
dqs_oe_n => dqs_oe_n,
dqs_rst => dqs_rst,
out_oserdes_wc => out_oserdes_wc,
dqs_wc => open,
dq_wc => open,
wl_sm_start => wl_sm_start,
wr_lvl_start => wrlvl_start,
wr_data_rise0 => wr_data_rise0,
wr_data_fall0 => wr_data_fall0,
wr_data_rise1 => wr_data_rise1,
wr_data_fall1 => wr_data_fall1,
mask_data_rise0 => mask_data_rise0,
mask_data_fall0 => mask_data_fall0,
mask_data_rise1 => mask_data_rise1,
mask_data_fall1 => mask_data_fall1
);
--***************************************************************************
-- Registered version of DQS Output Enable to determine when to switch
-- from ODELAY to IDELAY in phy_dly_ctrl module
--***************************************************************************
-- SYNTHESIS_NOTE: might need another pipeline stage to meet timing
process (clk)
begin
if (clk'event and clk = '1') then
dqs_oe <= not(AND_BR(dqs_oe_n)) after (TCQ)*1 ps;
end if;
end process;
--***************************************************************************
-- Write-leveling calibration logic
--***************************************************************************
mb_wrlvl_inst : if (WRLVL_W = "ON") generate
u_phy_wrlvl : phy_wrlvl
generic map (
tcq => TCQ,
dqs_cnt_width => DQS_CNT_WIDTH,
dq_width => DQ_WIDTH,
dqs_width => DQS_WIDTH,
dram_width => DRAM_WIDTH,
cs_width => CS_WIDTH,
cal_width => CAL_WIDTH,
dqs_tap_cnt_index => 5*DQS_WIDTH-1,
shift_tby4_tap => SHIFT_TBY4_TAP,
SIM_CAL_OPTION => SIM_CAL_OPTION_W
)
port map (
clk => clk,
rst => rst,
calib_width => calib_width,
rank_cnt => rank_cnt,
wr_level_start => wrlvl_start,
wl_sm_start => wl_sm_start,
rd_data_rise0 => dfi_rddata_37(DQ_WIDTH-1 downto 0),
wr_level_done => wrlvl_done,
wrlvl_rank_done => wrlvl_rank_done,
dlyval_wr_dqs => dlyval_wrlvl_dqs_w,
dlyval_wr_dq => dlyval_wrlvl_dq_w,
inv_dqs => inv_dqs,
rdlvl_error => rdlvl_pat_err,
rdlvl_err_byte => rdlvl_pat_err_cnt,
rdlvl_resume => rdlvl_pat_resume,
wr_calib_dly => wr_calib_dly,
wrcal_err => wrcal_err,
wrlvl_err => wrlvl_err,
dbg_wl_tap_cnt => dbg_tap_cnt_during_wrlvl_21,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid_22,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect_16,
dbg_rd_data_inv_edge_detect => open,
dbg_dqs_count => open,
dbg_wl_state => open
);
end generate;
--*****************************************************************
-- Read clock generation and data/control synchronization
--*****************************************************************
u_phy_read : phy_read
generic map (
tcq => TCQ,
nck_per_clk => nCK_PER_CLK,
clk_period => CLK_PERIOD,
refclk_freq => REFCLK_FREQ,
dqs_width => DQS_WIDTH,
dq_width => DQ_WIDTH,
dram_width => DRAM_WIDTH,
iodelay_grp => IODELAY_GRP,
ndqs_col0 => nDQS_COL0,
ndqs_col1 => nDQS_COL1,
ndqs_col2 => nDQS_COL2,
ndqs_col3 => nDQS_COL3,
dqs_loc_col0 => DQS_LOC_COL0,
dqs_loc_col1 => DQS_LOC_COL1,
dqs_loc_col2 => DQS_LOC_COL2,
dqs_loc_col3 => DQS_LOC_COL3
)
port map (
clk_mem => clk_mem,
clk => clk,
clk_rd_base => clk_rd_base,
rst => rst,
dlyrst_cpt => dlyrst_cpt,
dlyce_cpt => dlyce_cpt,
dlyinc_cpt => dlyinc_cpt,
dlyrst_rsync => dlyrst_rsync,
dlyce_rsync => dlyce_rsync,
dlyinc_rsync => dlyinc_rsync,
clk_cpt => clk_cpt,
clk_rsync => clk_rsync,
rst_rsync => rst_rsync,
rdpath_rdy => rdpath_rdy,
mc_data_sel => phy_init_data_sel,
rd_active_dly => rd_active_dly,
rd_data_rise0 => rd_data_rise0,
rd_data_fall0 => rd_data_fall0,
rd_data_rise1 => rd_data_rise1,
rd_data_fall1 => rd_data_fall1,
rd_dqs_rise0 => rd_dqs_rise0,
rd_dqs_fall0 => rd_dqs_fall0,
rd_dqs_rise1 => rd_dqs_rise1,
rd_dqs_fall1 => rd_dqs_fall1,
dfi_rddata_en => dfi_rddata_en,
phy_rddata_en => phy_rddata_en,
dfi_rddata_valid => dfi_rddata_valid_38,
dfi_rddata_valid_phy => dfi_rddata_valid_phy,
dfi_rddata => dfi_rddata_37,
dfi_rd_dqs => dfi_rd_dqs,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt_2,
dbg_rsync_tap_cnt => dbg_rsync_tap_cnt_20,
dbg_phy_read => dbg_phy_read_12
);
--***************************************************************************
-- Read-leveling calibration logic
--***************************************************************************
u_phy_rdlvl : phy_rdlvl
generic map (
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLK_PERIOD => CLK_PERIOD,
REFCLK_FREQ => integer(REFCLK_FREQ),
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_WIDTH => DRAM_WIDTH,
DRAM_TYPE => DRAM_TYPE,
nCL => nCL,
PD_TAP_REQ => PD_TAP_REQ,
SIM_CAL_OPTION => SIM_CAL_OPTION_W,
REG_CTRL => REG_CTRL,
DEBUG_PORT => DEBUG_PORT
)
port map (
clk => clk,
rst => rst,
rdlvl_start => rdlvl_start,
rdlvl_clkdiv_start => rdlvl_clkdiv_start,
rdlvl_rd_active => dfi_rddata_valid_phy,
rdlvl_done => rdlvl_done,
rdlvl_clkdiv_done => rdlvl_clkdiv_done,
rdlvl_err => rdlvl_err,
rdlvl_prech_req => rdlvl_prech_req,
prech_done => prech_done,
rd_data_rise0 => dfi_rddata_37(DQ_WIDTH - 1 downto 0),
rd_data_fall0 => dfi_rddata_37(2 * DQ_WIDTH - 1 downto DQ_WIDTH),
rd_data_rise1 => dfi_rddata_37(3 * DQ_WIDTH - 1 downto 2 * DQ_WIDTH),
rd_data_fall1 => dfi_rddata_37(4 * DQ_WIDTH - 1 downto 3 * DQ_WIDTH),
dlyce_cpt => dlyce_rdlvl_cpt,
dlyinc_cpt => dlyinc_rdlvl_cpt,
dlyce_rsync => dlyce_rdlvl_rsync,
dlyinc_rsync => dlyinc_rdlvl_rsync,
dlyval_dq => dlyval_rdlvl_dq,
dlyval_dqs => dlyval_rdlvl_dqs,
rd_bitslip_cnt => rd_bitslip_cnt,
rd_clkdly_cnt => rd_clkdly_cnt,
rd_active_dly => rd_active_dly,
rdlvl_pat_resume => rdlvl_pat_resume_w,
rdlvl_pat_err => rdlvl_pat_err,
rdlvl_pat_err_cnt => rdlvl_pat_err_cnt,
rd_clkdiv_inv => rd_clkdiv_inv,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt_0,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt_1,
dbg_rd_bitslip_cnt => dbg_rd_bitslip_cnt_14,
dbg_rd_clkdiv_inv => open, -- connect in future release
dbg_rd_clkdly_cnt => dbg_rd_clkdly_cnt_15,
dbg_rd_active_dly => dbg_rd_active_dly_13,
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_idel_up_rsync => dbg_idel_up_rsync,
dbg_idel_down_rsync => dbg_idel_down_rsync,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_sel_idel_rsync => dbg_sel_idel_rsync,
dbg_sel_all_idel_rsync => dbg_sel_all_idel_rsync,
dbg_phy_rdlvl => dbg_phy_rdlvl_11
);
--***************************************************************************
-- Phase Detector: Periodic read-path delay compensation
--***************************************************************************
gen_enable_pd : if (USE_PHASE_DETECT = "ON") generate
u_phy_pd_top : phy_pd_top
generic map (
TCQ => TCQ,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
PD_LHC_WIDTH => PD_LHC_WIDTH,
PD_CALIB_MODE => PD_CALIB_MODE,
PD_MSB_SEL => PD_MSB_SEL,
PD_DQS0_ONLY => PD_DQS0_ONLY,
SIM_CAL_OPTION => SIM_CAL_OPTION_W,
DEBUG_PORT => DEBUG_PORT
)
port map (
clk => clk,
rst => rst,
pd_cal_start => pd_cal_start,
pd_cal_done => pd_cal_done,
dfi_init_complete => phy_init_data_sel,
pd_PSEN => pd_PSEN,
pd_PSINCDEC => pd_PSINCDEC,
read_valid => dfi_rddata_valid_phy,
dlyval_rdlvl_dqs => dlyval_rdlvl_dqs,
dlyce_pd_cpt => dlyce_pd_cpt,
dlyinc_pd_cpt => dlyinc_pd_cpt,
dlyval_pd_dqs => dlyval_pd_dqs,
rd_dqs_rise0 => dfi_rd_dqs(DQS_WIDTH - 1 downto 0),
rd_dqs_fall0 => dfi_rd_dqs(2*DQS_WIDTH - 1 downto DQS_WIDTH),
rd_dqs_rise1 => dfi_rd_dqs(3*DQS_WIDTH - 1 downto 2*DQS_WIDTH),
rd_dqs_fall1 => dfi_rd_dqs(4*DQS_WIDTH - 1 downto 3*DQS_WIDTH),
pd_prech_req => pd_prech_req,
prech_done => prech_done,
dbg_pd_off => dbg_pd_off,
dbg_pd_maintain_off => dbg_pd_maintain_off,
dbg_pd_maintain_0_only => dbg_pd_maintain_0_only,
dbg_pd_inc_cpt => dbg_pd_inc_cpt,
dbg_pd_dec_cpt => dbg_pd_dec_cpt,
dbg_pd_inc_dqs => dbg_pd_inc_dqs,
dbg_pd_dec_dqs => dbg_pd_dec_dqs,
dbg_pd_disab_hyst => dbg_pd_disab_hyst,
dbg_pd_disab_hyst_0 => dbg_pd_disab_hyst_0,
dbg_pd_msb_sel => dbg_pd_msb_sel,
dbg_pd_byte_sel => dbg_pd_byte_sel,
dbg_inc_rd_fps => dbg_inc_rd_fps,
dbg_dec_rd_fps => dbg_dec_rd_fps,
dbg_phy_pd => dbg_phy_pd_10
);
end generate;
gen_disable_pd_tie_off : if (not(USE_PHASE_DETECT = "ON")) generate
-- Otherwise if phase detector is not used, tie off all PD-related
-- control signals
pd_cal_done <= '0';
pd_prech_req <= '0';
dlyce_pd_cpt <= (others => '0');
dlyinc_pd_cpt <= (others => '0');
dlyval_pd_dqs <= (others => '0');
end generate;
end architecture arch;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd
|
1
|
29322
|
-- Simple DBE simple design
-- Created by Lucas Russo <[email protected]>
-- Date: 11/10/2012
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_simple_top is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- FMC150 pins
-----------------------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_simple_top;
architecture rtl of dbe_bpm_simple_top is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 7; -- LED, Button, Dual-port memory, UART, DMA control port, FMC150
-- Number of masters
constant c_masters : natural := 4; -- LM32 master. Data + Instruction, DMA read+write master
--constant c_dpram_size : natural := 16384; -- in 32-bit words (64KB)
constant c_dpram_size : natural := 22528; -- in 32-bit words (64KB)
-- Number of source/sink Wishbone stream components
constant c_sinks : natural := 1;
constant c_sources : natural := c_sinks;
-- GPIO num pins
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 64KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(c_xwb_dma_sdb, x"20000400"), -- DMA control port
3 => f_sdb_embed_device(c_xwb_fmc150_sdb, x"20000500"), -- FMC control port
4 => f_sdb_embed_device(c_xwb_uart_sdb, x"20000600"), -- UART control port
5 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000700"), -- GPIO LED
6 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000800") -- GPIO Button
--7 => f_sdb_embed_device(c_xwb_irqmngr_sdb, x"20000900") -- IRQ_MNGR
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"20000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- Wishbone Stream source/sinks arrays
signal wbs_src_i : t_wbs_source_in_array(c_sources-1 downto 0);
signal wbs_src_o : t_wbs_source_out_array(c_sources-1 downto 0);
-- Check the use of this kind of alias
alias wbs_sink_i is wbs_src_o;
alias wbs_sink_o is wbs_src_i;
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_adc_rstn : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_adc_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_adc : std_logic;
signal rst_button_sys_n : std_logic;
signal rst_button_adc_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(1 downto 0);
signal reset_rstn : std_logic_vector(1 downto 0);
-- 200 Mhz clocck for iodelatctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal s_leds : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- IRQ manager signals
--signal gpio_slave_irqmngr_o : t_wishbone_slave_out;
--signal gpio_slave_irqmngr_i : t_wishbone_slave_in;
-- LEDS, button and irq manager signals
--signal r_leds : std_logic_vector(7 downto 0);
--signal r_reset : std_logic;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
constant s_counter_full : integer := 100000000;
-- FMC150 signals
signal clk_adc : std_logic;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
component chipscope_icon_2_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
-- Is this a safe approach to ADC reset domain?
cmp_reset : gc_reset
generic map(
g_clocks => 2 -- CLK_SYS + CLK_ADC
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Detect button positive edge of clk_adc
cmp_button_adc_ffs : gc_sync_ffs
port map (
clk_i => clk_adc,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_adc_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_adc_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_adc,
rst_n_i => '1',
pulse_i => rst_button_adc_pp,
extended_o => rst_button_adc
);
rst_button_sys_n <= not rst_button_sys;
rst_button_adc_n <= not rst_button_adc;
reset_clks(0) <= clk_sys;
reset_clks(1) <= clk_adc;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_adc_rstn <= reset_rstn(1) and rst_button_adc_n;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => false, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupts 31 downto 1 disabled for now.
-- Interrupt '0' is DMA completion.
lm32_interrupt(31 downto 1) <= (others => '0');
-- A DMA controller is master 2+3, slave 2, and interrupt 0
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => lm32_interrupt(0)
);
-- Slave 0+1 is the RAM. Load a input file containing a simple led blink program!
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
--slave2_i => cc_dummy_slave_in, -- CYC always low
--slave2_o => open
);
-- Slave 3 is the FMC150 interface
cmp_xwb_fmc150 : xwb_fmc150
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE
--g_packet_size => 32,
--g_sim => 0
)
port map(
rst_n_i => clk_sys_rstn,
clk_sys_i => clk_sys,
--clk_100Mhz_i : in std_logic;
clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(3),
wb_slv_o => cbar_master_i(3),
-----------------------------
-- Simulation Only ports!
-----------------------------
sim_adc_clk_i => '0',
sim_adc_clk2x_i => '0',
sim_adc_cha_data_i => f_zeros(14),
sim_adc_chb_data_i => f_zeros(14),
sim_adc_data_valid => '0',
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => adc_clk_ab_p_i,
adc_clk_ab_n_i => adc_clk_ab_n_i,
adc_cha_p_i => adc_cha_p_i,
adc_cha_n_i => adc_cha_n_i,
adc_chb_p_i => adc_chb_p_i,
adc_chb_n_i => adc_chb_n_i,
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o => dac_dclk_p_o,
dac_dclk_n_o => dac_dclk_n_o,
dac_data_p_o => dac_data_p_o,
dac_data_n_o => dac_data_n_o,
dac_frame_p_o => dac_frame_p_o,
dac_frame_n_o => dac_frame_n_o,
txenable_o => txenable_o,
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o => spi_sclk_o, -- Shared SPI clock line
spi_sdata_o => spi_sdata_o,-- Shared SPI data line
-- ADC specific signals
adc_n_en_o => adc_n_en_o, -- SPI chip select
adc_sdo_i => adc_sdo_i, -- SPI data out
adc_reset_o => adc_reset_o,-- SPI reset
-- CDCE specific signals
cdce_n_en_o => cdce_n_en_o, -- SPI chip select
cdce_sdo_i => cdce_sdo_i, -- SPI data out
cdce_n_reset_o => cdce_n_reset_o,
cdce_n_pd_o => cdce_n_pd_o,
cdce_ref_en_o => cdce_ref_en_o,
cdce_pll_status_i => cdce_pll_status_i,
-- DAC specific signals
dac_n_en_o => dac_n_en_o, -- SPI chip select
dac_sdo_i => dac_sdo_i, -- SPI data out
-- Monitoring specific signals
mon_n_en_o => mon_n_en_o, -- SPI chip select
mon_sdo_i => mon_sdo_i, -- SPI data out
mon_n_reset_o => mon_n_reset_o,
mon_n_int_i => mon_n_int_i,
--FMC Present status
prsnt_m2c_l_i => prsnt_m2c_l_i,
-- ADC output signals
-- ADC data is interfaced through the wishbone stream interface (wbs_src_o)
adc_dout_o => open,
clk_adc_o => clk_adc,
-- Wishbone Streaming Interface Source
wbs_source_i => wbs_src_i(0),
wbs_source_o => wbs_src_o(0)
);
-- Slave 4 is the UART
cmp_uart : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(4),
slave_o => cbar_master_i(4),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
-- Slave 5 is the example LED driver
cmp_leds : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_leds_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(5),
slave_o => cbar_master_i(5),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => s_leds,
--gpio_out_o => open,
gpio_in_i => s_leds,
gpio_oen_o => open
);
leds_o <= s_leds;
--p_test_leds : process (clk_adc)
--begin
-- if rising_edge(clk_adc) then
-- if clk_adc_rstn = '0' then
-- s_counter <= (others => '0');
-- s_leds <= x"55";
-- else
-- if (s_counter = s_counter_full-1) then
-- s_counter <= (others => '0');
-- s_leds <= s_leds(c_leds_num_pins-2 downto 0) & s_leds(c_leds_num_pins-1);
-- else
-- s_counter <= s_counter + 1;
-- end if;
-- end if;
-- end if;
--end process;
-- Slave 1 is the example LED driver
--gpio_slave_led_i <= cbar_master_o(1);
--cbar_master_i(1) <= gpio_slave_led_o;
--leds_o <= not r_leds;
-- There is a tool called 'wbgen2' which can autogenerate a Wishbone
-- interface and C header file, but this is a simple example.
--gpio : process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- It is vitally important that for each occurance of
-- (cyc and stb and not stall) there is (ack or rty or err)
-- sometime later on the bus.
--
-- This is an easy solution for a device that never stalls:
-- gpio_slave_led_o.ack <= gpio_slave_led_i.cyc and gpio_slave_led_i.stb;
-- Detect a write to the register byte
-- if gpio_slave_led_i.cyc = '1' and gpio_slave_led_i.stb = '1' and
-- gpio_slave_led_i.we = '1' and gpio_slave_led_i.sel(0) = '1' then
-- Register 0x0 = LEDs, 0x4 = CPU reset
-- if gpio_slave_led_i.adr(2) = '0' then
-- r_leds <= gpio_slave_led_i.dat(7 downto 0);
-- else
-- r_reset <= gpio_slave_led_i.dat(0);
-- end if;
-- end if;
-- Read to the register byte
-- if gpio_slave_led_i.adr(2) = '0' then
-- gpio_slave_led_o.dat(31 downto 8) <= (others => '0');
-- gpio_slave_led_o.dat(7 downto 0) <= r_leds;
-- else
-- gpio_slave_led_o.dat(31 downto 2) <= (others => '0');
-- gpio_slave_led_o.dat(0) <= r_reset;
-- end if;
--end if;
--end process;
--gpio_slave_led_o.int <= '0';
--gpio_slave_led_o.err <= '0';
--gpio_slave_led_o.rty <= '0';
--gpio_slave_led_o.stall <= '0'; -- This simple example is always ready
-- Slave 6 is the example Button driver
cmp_buttons : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_buttons_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(6),
slave_o => cbar_master_i(6),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => open,
gpio_in_i => buttons_i,
gpio_oen_o => open
);
-- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_2_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1
);
cmp_chipscope_ila_0 : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys,
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- FMC150 master output (slave input) control data
TRIG_ILA0_0 <= cbar_master_o(3).dat;
-- FMC150 master input (slave output) control data
TRIG_ILA0_1 <= cbar_master_i(3).dat;
-- FMC150 master control output (slave input) control signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA0_2(16 downto 0) <= cbar_master_o(3).cyc &
cbar_master_o(3).stb &
cbar_master_o(3).adr(9 downto 0) &
cbar_master_o(3).sel &
cbar_master_o(3).we;
--TRIG_ILA0_2(31 downto 11) <= (others => '0');
TRIG_ILA0_2(31 downto 17) <= (others => '0');
-- FMC150 master control input (slave output) control signals
TRIG_ILA0_3(4 downto 0) <= cbar_master_i(3).ack &
cbar_master_i(3).err &
cbar_master_i(3).rty &
cbar_master_i(3).stall &
cbar_master_i(3).int;
TRIG_ILA0_3(31 downto 5) <= (others => '0');
cmp_chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL1,
CLK => clk_adc,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- FMC150 source output (sink input) stream data
TRIG_ILA1_0 <= wbs_src_o(0).dat;
-- FMC150 source input (sink output) stream data
--TRIG_ILA1_1 <= wbs_src_i(0).dat;
-- FMC150 source control output (sink input) stream signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA1_1(10 downto 0) <= wbs_src_o(0).cyc &
wbs_src_o(0).stb &
wbs_src_o(0).adr(3 downto 0) &
wbs_src_o(0).sel &
wbs_src_o(0).we;
TRIG_ILA1_1(31 downto 11) <= (others => '0');
-- FMC150 master control input (slave output) stream signals
TRIG_ILA1_2(3 downto 0) <= wbs_src_i(0).ack &
wbs_src_i(0).err &
wbs_src_i(0).rty &
wbs_src_i(0).stall;
TRIG_ILA1_2(31 downto 4) <= (others => '0');
TRIG_ILA1_3(31 downto 0) <= (others => '0');
end rtl;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd
|
11
|
6148
|
-- MMCM_BASE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (MMCM_BASE_inst) and/or the port declarations after the
-- code : "=>" declaration maybe changed to properly reference and
-- : connect this function to the design. All inputs and outputs
-- : must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_clkbout_mult_f : real := 5.000;
-- 100 MHz output clock
g_clk0_divide_f : real := 10.000;
-- 200 MHz output clock
g_clk1_divide : integer := 5
);
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end sys_pll;
architecture syn of sys_pll is
signal s_mmcm_fbin : std_logic;
signal s_mmcm_fbout : std_logic;
signal s_clk0 : std_logic;
signal s_clk1 : std_logic;
begin
-- MMCM_BASE: Base Mixed Mode Clock Manager
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
-- Clock PLL
cmp_mmcm : MMCM_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => g_clkbout_mult_f,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => g_clk0_divide_f,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => g_clk1_divide,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => g_clkin_period,
REF_JITTER1 => 0.010,
-- Not used. Just to bypass Xilinx errors
-- Just input g_clkin_period input clock period
CLKIN2_PERIOD => g_clkin_period,
REF_JITTER2 => 0.010
)
port map(
-- Output clocks
CLKFBOUT => s_mmcm_fbout,
CLKFBOUTB => open,
CLKOUT0 => s_clk0,
CLKOUT0B => open,
CLKOUT1 => s_clk1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => s_mmcm_fbin,
CLKIN1 => clk_i,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_o,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst_i
);
-- Global clock buffers for "cmp_mmcm" instance
cmp_clkf_bufg : BUFG
port map(
O => s_mmcm_fbin,
I => s_mmcm_fbout
);
cmp_clkout0_buf : BUFG
port map(
O => clk0_o,
I => s_clk0
);
cmp_clkout1_buf : BUFG
port map(
O => clk1_o,
I => s_clk1
);
end syn;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
embedded-sw/dbe_lwip.vhd
|
1
|
743044
|
-- AUTOGENERATED FILE (from genramvhd.c run on -s) --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.memory_loader_pkg.all;
package dbe_lwip_bin_pkg is
constant dbe_lwip_bin_init : t_meminit_array(32767 downto 0, 31 downto 0) := (
0 => x"98000000", 1 => x"d0000000", 2 => x"d0200000",
3 => x"78010000", 4 => x"38210000", 5 => x"d0e10000",
6 => x"f800003a", 7 => x"34000000", 8 => x"00000000",
9 => x"00000000", 10 => x"00000000", 11 => x"00000000",
12 => x"00000000", 13 => x"00000000", 14 => x"00000000",
15 => x"00000000", 16 => x"00000000", 17 => x"00000000",
18 => x"00000000", 19 => x"00000000", 20 => x"00000000",
21 => x"00000000", 22 => x"00000000", 23 => x"00000000",
24 => x"00000000", 25 => x"00000000", 26 => x"00000000",
27 => x"00000000", 28 => x"00000000", 29 => x"00000000",
30 => x"00000000", 31 => x"00000000", 32 => x"00000000",
33 => x"00000000", 34 => x"00000000", 35 => x"00000000",
36 => x"00000000", 37 => x"00000000", 38 => x"00000000",
39 => x"00000000", 40 => x"00000000", 41 => x"00000000",
42 => x"00000000", 43 => x"00000000", 44 => x"00000000",
45 => x"00000000", 46 => x"00000000", 47 => x"00000000",
48 => x"5b9d0000", 49 => x"f8000020", 50 => x"34010002",
51 => x"f8000675", 52 => x"e0000030", 53 => x"34000000",
54 => x"34000000", 55 => x"34000000", 56 => x"00000000",
57 => x"00000000", 58 => x"00000000", 59 => x"00000000",
60 => x"00000000", 61 => x"00000000", 62 => x"00000000",
63 => x"00000000", 64 => x"98000000", 65 => x"781c0001",
66 => x"3b9cfffc", 67 => x"781a0000", 68 => x"3b5aba00",
69 => x"78010000", 70 => x"38213a08", 71 => x"34020000",
72 => x"78030000", 73 => x"386349f4", 74 => x"c8611800",
75 => x"f8000b85", 76 => x"34010000", 77 => x"34020000",
78 => x"34030000", 79 => x"f8000206", 80 => x"e0000000",
81 => x"379cffc4", 82 => x"5b810004", 83 => x"5b820008",
84 => x"5b83000c", 85 => x"5b840010", 86 => x"5b850014",
87 => x"5b860018", 88 => x"5b87001c", 89 => x"5b880020",
90 => x"5b890024", 91 => x"5b8a0028", 92 => x"5b9e0034",
93 => x"5b9f0038", 94 => x"2b81003c", 95 => x"5b810030",
96 => x"bb800800", 97 => x"3421003c", 98 => x"5b81002c",
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1734 => x"5d8dfff7", 1735 => x"2b9d0004", 1736 => x"2b8b0018",
1737 => x"2b8c0014", 1738 => x"2b8d0010", 1739 => x"2b8e000c",
1740 => x"2b8f0008", 1741 => x"379c0018", 1742 => x"c3a00000",
1743 => x"78010000", 1744 => x"38214234", 1745 => x"34220100",
1746 => x"58200000", 1747 => x"58200004", 1748 => x"34210008",
1749 => x"5c22fffd", 1750 => x"34010000", 1751 => x"d0210000",
1752 => x"34010001", 1753 => x"d0010000", 1754 => x"34010000",
1755 => x"c3a00000", 1756 => x"3c250003", 1757 => x"78040000",
1758 => x"38844234", 1759 => x"b4852000", 1760 => x"58820000",
1761 => x"58830004", 1762 => x"90201000", 1763 => x"34030001",
1764 => x"bc610800", 1765 => x"b8410800", 1766 => x"d0210000",
1767 => x"34010000", 1768 => x"c3a00000", 1769 => x"379cfff4",
1770 => x"5b8b000c", 1771 => x"5b8c0008", 1772 => x"5b9d0004",
1773 => x"780b0000", 1774 => x"b8202000", 1775 => x"396b4334",
1776 => x"b8401800", 1777 => x"b9600800", 1778 => x"b8801000",
1779 => x"f8000163", 1780 => x"b8206000", 1781 => x"b9600800",
1782 => x"f800034e", 1783 => x"b9800800", 1784 => x"2b9d0004",
1785 => x"2b8b000c", 1786 => x"2b8c0008", 1787 => x"379c000c",
1788 => x"c3a00000", 1789 => x"379cffdc", 1790 => x"5b9d0004",
1791 => x"5b82000c", 1792 => x"3782000c", 1793 => x"5b810008",
1794 => x"5b830010", 1795 => x"5b840014", 1796 => x"5b850018",
1797 => x"5b86001c", 1798 => x"5b870020", 1799 => x"5b880024",
1800 => x"fbffffe1", 1801 => x"2b9d0004", 1802 => x"379c0024",
1803 => x"c3a00000", 1804 => x"379cffec", 1805 => x"5b8b0014",
1806 => x"5b8c0010", 1807 => x"5b8d000c", 1808 => x"5b8e0008",
1809 => x"5b9d0004", 1810 => x"b8205800", 1811 => x"78010000",
1812 => x"382138c0", 1813 => x"282e0000", 1814 => x"b8406000",
1815 => x"558e003f", 1816 => x"01860004", 1817 => x"01840008",
1818 => x"0182000c", 1819 => x"20c6000f", 1820 => x"2084000f",
1821 => x"b4c40800", 1822 => x"b4220800", 1823 => x"08210006",
1824 => x"218c000f", 1825 => x"08450009", 1826 => x"b42c6000",
1827 => x"098300cd", 1828 => x"08870005", 1829 => x"b4a62800",
1830 => x"0063000b", 1831 => x"b4a72800", 1832 => x"0861000a",
1833 => x"b4a32800", 1834 => x"c9816000", 1835 => x"358c0030",
1836 => x"316c0000", 1837 => x"35610001", 1838 => x"44a00021",
1839 => x"08a300cd", 1840 => x"3c840001", 1841 => x"0063000b",
1842 => x"0861000a", 1843 => x"b4641800", 1844 => x"b8622000",
1845 => x"c8a12800", 1846 => x"34a50030", 1847 => x"31650001",
1848 => x"35610002", 1849 => x"44800016", 1850 => x"0864000d",
1851 => x"3c420002", 1852 => x"00840007", 1853 => x"0881000a",
1854 => x"b4821000", 1855 => x"c8611800", 1856 => x"34630030",
1857 => x"31630002", 1858 => x"35610003", 1859 => x"4440000c",
1860 => x"084300cd", 1861 => x"0063000b", 1862 => x"0861000a",
1863 => x"c8411000", 1864 => x"34420030", 1865 => x"31620003",
1866 => x"35610004", 1867 => x"44600004", 1868 => x"34630030",
1869 => x"31630004", 1870 => x"35610005", 1871 => x"2b9d0004",
1872 => x"2b8b0014", 1873 => x"2b8c0010", 1874 => x"2b8d000c",
1875 => x"2b8e0008", 1876 => x"379c0014", 1877 => x"c3a00000",
1878 => x"78030000", 1879 => x"386338c4", 1880 => x"28620000",
1881 => x"b9800800", 1882 => x"f800044a", 1883 => x"78030000",
1884 => x"386338c4", 1885 => x"28620000", 1886 => x"b8206800",
1887 => x"b9800800", 1888 => x"f8000434", 1889 => x"01a50004",
1890 => x"01a20008", 1891 => x"20a5000f", 1892 => x"2042000f",
1893 => x"b8206000", 1894 => x"01a1000c", 1895 => x"b4a21800",
1896 => x"b4611800", 1897 => x"08630006", 1898 => x"21ad000f",
1899 => x"08460005", 1900 => x"b46d6800", 1901 => x"09a300cd",
1902 => x"3c420001", 1903 => x"0063000b", 1904 => x"0864000a",
1905 => x"c9a46800", 1906 => x"08240009", 1907 => x"3c210002",
1908 => x"35ad0030", 1909 => x"b4852000", 1910 => x"b4862000",
1911 => x"b4832000", 1912 => x"088300cd", 1913 => x"316d0000",
1914 => x"0063000b", 1915 => x"b4621000", 1916 => x"0865000a",
1917 => x"0843000d", 1918 => x"c8852000", 1919 => x"00630007",
1920 => x"34840030", 1921 => x"31640001", 1922 => x"0864000a",
1923 => x"b4610800", 1924 => x"c8441000", 1925 => x"34420030",
1926 => x"31620002", 1927 => x"082200cd", 1928 => x"0042000b",
1929 => x"0843000a", 1930 => x"34420030", 1931 => x"31620004",
1932 => x"c8230800", 1933 => x"34210030", 1934 => x"31610003",
1935 => x"356b0005", 1936 => x"e3ffff87", 1937 => x"379cff94",
1938 => x"5b8b0028", 1939 => x"5b8c0024", 1940 => x"5b8d0020",
1941 => x"5b8e001c", 1942 => x"5b8f0018", 1943 => x"5b900014",
1944 => x"5b910010", 1945 => x"5b92000c", 1946 => x"5b930008",
1947 => x"5b9d0004", 1948 => x"b8205800", 1949 => x"00d10006",
1950 => x"7c61000a", 1951 => x"20d00020", 1952 => x"a2218800",
1953 => x"20c10010", 1954 => x"b8607000", 1955 => x"b8806800",
1956 => x"b8a09000", 1957 => x"b8c06000", 1958 => x"221000ff",
1959 => x"44200003", 1960 => x"3401fffe", 1961 => x"a0c16000",
1962 => x"21810002", 1963 => x"340f0000", 1964 => x"4420000f",
1965 => x"4c400005", 1966 => x"c8021000", 1967 => x"35adffff",
1968 => x"340f002d", 1969 => x"e000000a", 1970 => x"21810004",
1971 => x"44200004", 1972 => x"35adffff", 1973 => x"340f002b",
1974 => x"e0000005", 1975 => x"21810008", 1976 => x"442f0003",
1977 => x"35adffff", 1978 => x"340f0020", 1979 => x"46200004",
1980 => x"65c10010", 1981 => x"35adffff", 1982 => x"c9a16800",
1983 => x"5c400005", 1984 => x"34010030", 1985 => x"3381002c",
1986 => x"34010001", 1987 => x"e0000019", 1988 => x"3401000a",
1989 => x"45c10013", 1990 => x"65c40010", 1991 => x"78030000",
1992 => x"35c6ffff", 1993 => x"34840003", 1994 => x"34010000",
1995 => x"3785002c", 1996 => x"386338d8", 1997 => x"204800ff",
1998 => x"a1064000", 1999 => x"b4684000", 2000 => x"41080000",
2001 => x"b4a13800", 2002 => x"80441000", 2003 => x"ba084000",
2004 => x"30e80000", 2005 => x"34210001", 2006 => x"5c40fff7",
2007 => x"e0000005", 2008 => x"3793002c", 2009 => x"ba600800",
2010 => x"fbffff32", 2011 => x"c8330800", 2012 => x"b8201000",
2013 => x"4c320002", 2014 => x"ba401000", 2015 => x"21830011",
2016 => x"c9a26800", 2017 => x"5c600008", 2018 => x"e0000004",
2019 => x"31630000", 2020 => x"356b0001", 2021 => x"e0000002",
2022 => x"34030020", 2023 => x"35adffff", 2024 => x"4da0fffb",
2025 => x"45e00003", 2026 => x"316f0000", 2027 => x"356b0001",
2028 => x"46200009", 2029 => x"34030030", 2030 => x"31630000",
2031 => x"34030010", 2032 => x"356b0001", 2033 => x"5dc30004",
2034 => x"3a100058", 2035 => x"31700000", 2036 => x"356b0001",
2037 => x"21830010", 2038 => x"5c600010", 2039 => x"218c0001",
2040 => x"e5836000", 2041 => x"3404fff0", 2042 => x"c80c6000",
2043 => x"a1846000", 2044 => x"358c0030", 2045 => x"e0000003",
2046 => x"316c0000", 2047 => x"356b0001", 2048 => x"35adffff",
2049 => x"4da0fffd", 2050 => x"e0000004", 2051 => x"31630000",
2052 => x"356b0001", 2053 => x"e0000002", 2054 => x"34030030",
2055 => x"3442ffff", 2056 => x"4c41fffb", 2057 => x"e0000006",
2058 => x"b4611000", 2059 => x"40420000", 2060 => x"31620000",
2061 => x"356b0001", 2062 => x"e0000002", 2063 => x"3783002c",
2064 => x"3421ffff", 2065 => x"4c20fff9", 2066 => x"e0000004",
2067 => x"31610000", 2068 => x"356b0001", 2069 => x"e0000002",
2070 => x"34010020", 2071 => x"35adffff", 2072 => x"4da0fffb",
2073 => x"b9600800", 2074 => x"2b9d0004", 2075 => x"2b8b0028",
2076 => x"2b8c0024", 2077 => x"2b8d0020", 2078 => x"2b8e001c",
2079 => x"2b8f0018", 2080 => x"2b900014", 2081 => x"2b910010",
2082 => x"2b92000c", 2083 => x"2b930008", 2084 => x"379c006c",
2085 => x"c3a00000", 2086 => x"379cffec", 2087 => x"5b8b0014",
2088 => x"5b8c0010", 2089 => x"5b8d000c", 2090 => x"5b8e0008",
2091 => x"5b9d0004", 2092 => x"b8406000", 2093 => x"b8205800",
2094 => x"b8606800", 2095 => x"b8801000", 2096 => x"b8a07000",
2097 => x"5d800003", 2098 => x"780c0000", 2099 => x"398c38c8",
2100 => x"b9800800", 2101 => x"f8000400", 2102 => x"21c50010",
2103 => x"5ca00009", 2104 => x"e0000004", 2105 => x"31620000",
2106 => x"356b0001", 2107 => x"e0000002", 2108 => x"34020020",
2109 => x"35adffff", 2110 => x"35a30001", 2111 => x"4861fffa",
2112 => x"34020000", 2113 => x"e0000006", 2114 => x"b5821800",
2115 => x"40630000", 2116 => x"34420001", 2117 => x"31630000",
2118 => x"356b0001", 2119 => x"4822fffb", 2120 => x"34020020",
2121 => x"e0000004", 2122 => x"31620000", 2123 => x"35adffff",
2124 => x"356b0001", 2125 => x"49a1fffd", 2126 => x"b9600800",
2127 => x"2b9d0004", 2128 => x"2b8b0014", 2129 => x"2b8c0010",
2130 => x"2b8d000c", 2131 => x"2b8e0008", 2132 => x"379c0014",
2133 => x"c3a00000", 2134 => x"379cffbc", 2135 => x"5b8b0044",
2136 => x"5b8c0040", 2137 => x"5b8d003c", 2138 => x"5b8e0038",
2139 => x"5b8f0034", 2140 => x"5b900030", 2141 => x"5b91002c",
2142 => x"5b920028", 2143 => x"5b930024", 2144 => x"5b940020",
2145 => x"5b95001c", 2146 => x"5b960018", 2147 => x"5b970014",
2148 => x"5b980010", 2149 => x"5b99000c", 2150 => x"5b9b0008",
2151 => x"5b9d0004", 2152 => x"78100000", 2153 => x"b8207800",
2154 => x"b8406000", 2155 => x"b8605000", 2156 => x"34110025",
2157 => x"3415002b", 2158 => x"340d0009", 2159 => x"341bffff",
2160 => x"3414006e", 2161 => x"340e006c", 2162 => x"34130074",
2163 => x"34190068", 2164 => x"34180025", 2165 => x"34120073",
2166 => x"34170075", 2167 => x"34160078", 2168 => x"3a1038d0",
2169 => x"e00000e1", 2170 => x"5c7100c4", 2171 => x"34060000",
2172 => x"358c0001", 2173 => x"41870000", 2174 => x"44f5000e",
2175 => x"54f50006", 2176 => x"34020020", 2177 => x"44e2000d",
2178 => x"34020023", 2179 => x"5ce20011", 2180 => x"e000000c",
2181 => x"3402002d", 2182 => x"44e20004", 2183 => x"34020030",
2184 => x"5ce2000c", 2185 => x"e0000009", 2186 => x"38c60010",
2187 => x"e3fffff1", 2188 => x"38c60004", 2189 => x"e3ffffef",
2190 => x"38c60008", 2191 => x"e3ffffed", 2192 => x"38c60040",
2193 => x"e3ffffeb", 2194 => x"38c60001", 2195 => x"e3ffffe9",
2196 => x"34e3ffd0", 2197 => x"206300ff", 2198 => x"546d000b",
2199 => x"34080000", 2200 => x"e0000004", 2201 => x"0908000a",
2202 => x"358c0001", 2203 => x"b4484000", 2204 => x"41820000",
2205 => x"3442ffd0", 2206 => x"204300ff", 2207 => x"51a3fffa",
2208 => x"e000000a", 2209 => x"3403002a", 2210 => x"3408ffff",
2211 => x"5ce30007", 2212 => x"29480000", 2213 => x"358c0001",
2214 => x"354a0004", 2215 => x"4d000003", 2216 => x"c8084000",
2217 => x"38c60010", 2218 => x"41830000", 2219 => x"3402002e",
2220 => x"3405ffff", 2221 => x"5c62001b", 2222 => x"358c0001",
2223 => x"41870000", 2224 => x"34e3ffd0", 2225 => x"206300ff",
2226 => x"546d000b", 2227 => x"34050000", 2228 => x"e0000004",
2229 => x"08a5000a", 2230 => x"358c0001", 2231 => x"b4452800",
2232 => x"41820000", 2233 => x"3442ffd0", 2234 => x"204300ff",
2235 => x"51a3fffa", 2236 => x"e000000c", 2237 => x"3403002a",
2238 => x"34050000", 2239 => x"5ce30009", 2240 => x"29450000",
2241 => x"358c0001", 2242 => x"35470004", 2243 => x"48050003",
2244 => x"b8e05000", 2245 => x"e0000003", 2246 => x"b8e05000",
2247 => x"34050000", 2248 => x"41870000", 2249 => x"64e4006c",
2250 => x"64e30068", 2251 => x"b8831800", 2252 => x"5c600009",
2253 => x"3403004c", 2254 => x"44e30007", 2255 => x"3403005a",
2256 => x"44e30005", 2257 => x"3403007a", 2258 => x"44e30003",
2259 => x"3409ffff", 2260 => x"5cf30008", 2261 => x"b8e04800",
2262 => x"358c0001", 2263 => x"5cee0005", 2264 => x"41830000",
2265 => x"5c6e0003", 2266 => x"358c0001", 2267 => x"3409004c",
2268 => x"41870000", 2269 => x"44f4004f", 2270 => x"54f4000d",
2271 => x"34030063", 2272 => x"44e30015", 2273 => x"54e30005",
2274 => x"44f10050", 2275 => x"34030058", 2276 => x"5ce30056",
2277 => x"e0000060", 2278 => x"34030064", 2279 => x"44e30051",
2280 => x"34030069", 2281 => x"5ce30051", 2282 => x"e000004e",
2283 => x"44f2001e", 2284 => x"54f20006", 2285 => x"3403006f",
2286 => x"44e30046", 2287 => x"34030070", 2288 => x"5ce3004a",
2289 => x"e000001f", 2290 => x"44f70051", 2291 => x"5cf60047",
2292 => x"e0000042", 2293 => x"20c60010", 2294 => x"5cc00008",
2295 => x"e0000004", 2296 => x"30230000", 2297 => x"34210001",
2298 => x"e0000002", 2299 => x"34030020", 2300 => x"3508ffff",
2301 => x"4900fffb", 2302 => x"29440000", 2303 => x"35430004",
2304 => x"30240000", 2305 => x"34210001", 2306 => x"34040020",
2307 => x"e0000003", 2308 => x"30240000", 2309 => x"34210001",
2310 => x"3508ffff", 2311 => x"4900fffd", 2312 => x"e0000028",
2313 => x"29420000", 2314 => x"b8a02000", 2315 => x"b9001800",
2316 => x"b8c02800", 2317 => x"354b0004", 2318 => x"fbffff18",
2319 => x"e0000049", 2320 => x"29420000", 2321 => x"354b0004",
2322 => x"5c400007", 2323 => x"b8a02000", 2324 => x"ba001000",
2325 => x"b9001800", 2326 => x"b8c02800", 2327 => x"fbffff0f",
2328 => x"e000000c", 2329 => x"38c70020", 2330 => x"5d1b0003",
2331 => x"38c70021", 2332 => x"34080008", 2333 => x"34030010",
2334 => x"b9002000", 2335 => x"b8e03000", 2336 => x"fbfffe71",
2337 => x"e0000003", 2338 => x"b8606000", 2339 => x"e0000002",
2340 => x"34040019", 2341 => x"41820001", 2342 => x"35830001",
2343 => x"3445ff9f", 2344 => x"5085fffa", 2345 => x"3445ffbf",
2346 => x"5085fff8", 2347 => x"e0000046", 2348 => x"29450000",
2349 => x"c82f2000", 2350 => x"35430004", 2351 => x"58a40000",
2352 => x"b8605000", 2353 => x"e0000028", 2354 => x"30310000",
2355 => x"e000000c", 2356 => x"34030008", 2357 => x"e0000011",
2358 => x"38c60020", 2359 => x"e000000e", 2360 => x"38c60002",
2361 => x"e000000a", 2362 => x"30380000", 2363 => x"41830000",
2364 => x"34210001", 2365 => x"44600004", 2366 => x"30230000",
2367 => x"34210001", 2368 => x"e0000019", 2369 => x"358cffff",
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2373 => x"34030010", 2374 => x"452e0006", 2375 => x"6527007a",
2376 => x"6524005a", 2377 => x"b8e42000", 2378 => x"5c800002",
2379 => x"5d330004", 2380 => x"354b0004", 2381 => x"29420000",
2382 => x"e0000008", 2383 => x"354b0004", 2384 => x"29420000",
2385 => x"5d390005", 2386 => x"20c40002", 2387 => x"2042ffff",
2388 => x"44800002", 2389 => x"dc401000", 2390 => x"b9002000",
2391 => x"fbfffe3a", 2392 => x"b9605000", 2393 => x"358c0001",
2394 => x"41830000", 2395 => x"5c60ff1f", 2396 => x"30200000",
2397 => x"c82f0800", 2398 => x"2b9d0004", 2399 => x"2b8b0044",
2400 => x"2b8c0040", 2401 => x"2b8d003c", 2402 => x"2b8e0038",
2403 => x"2b8f0034", 2404 => x"2b900030", 2405 => x"2b91002c",
2406 => x"2b920028", 2407 => x"2b930024", 2408 => x"2b940020",
2409 => x"2b95001c", 2410 => x"2b960018", 2411 => x"2b970014",
2412 => x"2b980010", 2413 => x"2b99000c", 2414 => x"2b9b0008",
2415 => x"379c0044", 2416 => x"c3a00000", 2417 => x"3442ffd0",
2418 => x"51a2ffb0", 2419 => x"e3ffffe5", 2420 => x"379cfff8",
2421 => x"5b8b0008", 2422 => x"5b9d0004", 2423 => x"780b0000",
2424 => x"396b43d0", 2425 => x"29620000", 2426 => x"3401ffff",
2427 => x"28430008", 2428 => x"44600013", 2429 => x"28410004",
2430 => x"3c210002", 2431 => x"fbfff9a7", 2432 => x"29630000",
2433 => x"78020000", 2434 => x"384249e4", 2435 => x"58410000",
2436 => x"28640004", 2437 => x"28620008", 2438 => x"34030000",
2439 => x"e0000006", 2440 => x"28450000", 2441 => x"28420004",
2442 => x"34630001", 2443 => x"58250000", 2444 => x"34210004",
2445 => x"5c64fffb", 2446 => x"34010000", 2447 => x"2b9d0004",
2448 => x"2b8b0008", 2449 => x"379c0008", 2450 => x"c3a00000",
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2454 => x"5b8d0014", 2455 => x"5b8e0010", 2456 => x"5b8f000c",
2457 => x"5b900008", 2458 => x"5b9d0004", 2459 => x"780b0000",
2460 => x"396b43cc", 2461 => x"29620000", 2462 => x"3401ffff",
2463 => x"28430008", 2464 => x"44600025", 2465 => x"28410004",
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2481 => x"29c50000", 2482 => x"3d810002", 2483 => x"b9802000",
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2490 => x"29ce0004", 2491 => x"358c0001", 2492 => x"29610000",
2493 => x"28240004", 2494 => x"548cfff2", 2495 => x"78010000",
2496 => x"38213908", 2497 => x"b9a01000", 2498 => x"3403001a",
2499 => x"fbfffd3a", 2500 => x"34010000", 2501 => x"2b9d0004",
2502 => x"2b8b001c", 2503 => x"2b8c0018", 2504 => x"2b8d0014",
2505 => x"2b8e0010", 2506 => x"2b8f000c", 2507 => x"2b900008",
2508 => x"379c001c", 2509 => x"c3a00000", 2510 => x"78040000",
2511 => x"388449e8", 2512 => x"3c210002", 2513 => x"44600008",
2514 => x"28830000", 2515 => x"b4610800", 2516 => x"28210000",
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31806 => x"00000000", 31807 => x"00000000", 31808 => x"00000000",
31809 => x"00000000", 31810 => x"00000000", 31811 => x"00000000",
31812 => x"00000000", 31813 => x"00000000", 31814 => x"00000000",
31815 => x"00000000", 31816 => x"00000000", 31817 => x"00000000",
31818 => x"00000000", 31819 => x"00000000", 31820 => x"00000000",
31821 => x"00000000", 31822 => x"00000000", 31823 => x"00000000",
31824 => x"00000000", 31825 => x"00000000", 31826 => x"00000000",
31827 => x"00000000", 31828 => x"00000000", 31829 => x"00000000",
31830 => x"00000000", 31831 => x"00000000", 31832 => x"00000000",
31833 => x"00000000", 31834 => x"00000000", 31835 => x"00000000",
31836 => x"00000000", 31837 => x"00000000", 31838 => x"00000000",
31839 => x"00000000", 31840 => x"00000000", 31841 => x"00000000",
31842 => x"00000000", 31843 => x"00000000", 31844 => x"00000000",
31845 => x"00000000", 31846 => x"00000000", 31847 => x"00000000",
31848 => x"00000000", 31849 => x"00000000", 31850 => x"00000000",
31851 => x"00000000", 31852 => x"00000000", 31853 => x"00000000",
31854 => x"00000000", 31855 => x"00000000", 31856 => x"00000000",
31857 => x"00000000", 31858 => x"00000000", 31859 => x"00000000",
31860 => x"00000000", 31861 => x"00000000", 31862 => x"00000000",
31863 => x"00000000", 31864 => x"00000000", 31865 => x"00000000",
31866 => x"00000000", 31867 => x"00000000", 31868 => x"00000000",
31869 => x"00000000", 31870 => x"00000000", 31871 => x"00000000",
31872 => x"00000000", 31873 => x"00000000", 31874 => x"00000000",
31875 => x"00000000", 31876 => x"00000000", 31877 => x"00000000",
31878 => x"00000000", 31879 => x"00000000", 31880 => x"00000000",
31881 => x"00000000", 31882 => x"00000000", 31883 => x"00000000",
31884 => x"00000000", 31885 => x"00000000", 31886 => x"00000000",
31887 => x"00000000", 31888 => x"00000000", 31889 => x"00000000",
31890 => x"00000000", 31891 => x"00000000", 31892 => x"00000000",
31893 => x"00000000", 31894 => x"00000000", 31895 => x"00000000",
31896 => x"00000000", 31897 => x"00000000", 31898 => x"00000000",
31899 => x"00000000", 31900 => x"00000000", 31901 => x"00000000",
31902 => x"00000000", 31903 => x"00000000", 31904 => x"00000000",
31905 => x"00000000", 31906 => x"00000000", 31907 => x"00000000",
31908 => x"00000000", 31909 => x"00000000", 31910 => x"00000000",
31911 => x"00000000", 31912 => x"00000000", 31913 => x"00000000",
31914 => x"00000000", 31915 => x"00000000", 31916 => x"00000000",
31917 => x"00000000", 31918 => x"00000000", 31919 => x"00000000",
31920 => x"00000000", 31921 => x"00000000", 31922 => x"00000000",
31923 => x"00000000", 31924 => x"00000000", 31925 => x"00000000",
31926 => x"00000000", 31927 => x"00000000", 31928 => x"00000000",
31929 => x"00000000", 31930 => x"00000000", 31931 => x"00000000",
31932 => x"00000000", 31933 => x"00000000", 31934 => x"00000000",
31935 => x"00000000", 31936 => x"00000000", 31937 => x"00000000",
31938 => x"00000000", 31939 => x"00000000", 31940 => x"00000000",
31941 => x"00000000", 31942 => x"00000000", 31943 => x"00000000",
31944 => x"00000000", 31945 => x"00000000", 31946 => x"00000000",
31947 => x"00000000", 31948 => x"00000000", 31949 => x"00000000",
31950 => x"00000000", 31951 => x"00000000", 31952 => x"00000000",
31953 => x"00000000", 31954 => x"00000000", 31955 => x"00000000",
31956 => x"00000000", 31957 => x"00000000", 31958 => x"00000000",
31959 => x"00000000", 31960 => x"00000000", 31961 => x"00000000",
31962 => x"00000000", 31963 => x"00000000", 31964 => x"00000000",
31965 => x"00000000", 31966 => x"00000000", 31967 => x"00000000",
31968 => x"00000000", 31969 => x"00000000", 31970 => x"00000000",
31971 => x"00000000", 31972 => x"00000000", 31973 => x"00000000",
31974 => x"00000000", 31975 => x"00000000", 31976 => x"00000000",
31977 => x"00000000", 31978 => x"00000000", 31979 => x"00000000",
31980 => x"00000000", 31981 => x"00000000", 31982 => x"00000000",
31983 => x"00000000", 31984 => x"00000000", 31985 => x"00000000",
31986 => x"00000000", 31987 => x"00000000", 31988 => x"00000000",
31989 => x"00000000", 31990 => x"00000000", 31991 => x"00000000",
31992 => x"00000000", 31993 => x"00000000", 31994 => x"00000000",
31995 => x"00000000", 31996 => x"00000000", 31997 => x"00000000",
31998 => x"00000000", 31999 => x"00000000", 32000 => x"00000000",
32001 => x"00000000", 32002 => x"00000000", 32003 => x"00000000",
32004 => x"00000000", 32005 => x"00000000", 32006 => x"00000000",
32007 => x"00000000", 32008 => x"00000000", 32009 => x"00000000",
32010 => x"00000000", 32011 => x"00000000", 32012 => x"00000000",
32013 => x"00000000", 32014 => x"00000000", 32015 => x"00000000",
32016 => x"00000000", 32017 => x"00000000", 32018 => x"00000000",
32019 => x"00000000", 32020 => x"00000000", 32021 => x"00000000",
32022 => x"00000000", 32023 => x"00000000", 32024 => x"00000000",
32025 => x"00000000", 32026 => x"00000000", 32027 => x"00000000",
32028 => x"00000000", 32029 => x"00000000", 32030 => x"00000000",
32031 => x"00000000", 32032 => x"00000000", 32033 => x"00000000",
32034 => x"00000000", 32035 => x"00000000", 32036 => x"00000000",
32037 => x"00000000", 32038 => x"00000000", 32039 => x"00000000",
32040 => x"00000000", 32041 => x"00000000", 32042 => x"00000000",
32043 => x"00000000", 32044 => x"00000000", 32045 => x"00000000",
32046 => x"00000000", 32047 => x"00000000", 32048 => x"00000000",
32049 => x"00000000", 32050 => x"00000000", 32051 => x"00000000",
32052 => x"00000000", 32053 => x"00000000", 32054 => x"00000000",
32055 => x"00000000", 32056 => x"00000000", 32057 => x"00000000",
32058 => x"00000000", 32059 => x"00000000", 32060 => x"00000000",
32061 => x"00000000", 32062 => x"00000000", 32063 => x"00000000",
32064 => x"00000000", 32065 => x"00000000", 32066 => x"00000000",
32067 => x"00000000", 32068 => x"00000000", 32069 => x"00000000",
32070 => x"00000000", 32071 => x"00000000", 32072 => x"00000000",
32073 => x"00000000", 32074 => x"00000000", 32075 => x"00000000",
32076 => x"00000000", 32077 => x"00000000", 32078 => x"00000000",
32079 => x"00000000", 32080 => x"00000000", 32081 => x"00000000",
32082 => x"00000000", 32083 => x"00000000", 32084 => x"00000000",
32085 => x"00000000", 32086 => x"00000000", 32087 => x"00000000",
32088 => x"00000000", 32089 => x"00000000", 32090 => x"00000000",
32091 => x"00000000", 32092 => x"00000000", 32093 => x"00000000",
32094 => x"00000000", 32095 => x"00000000", 32096 => x"00000000",
32097 => x"00000000", 32098 => x"00000000", 32099 => x"00000000",
32100 => x"00000000", 32101 => x"00000000", 32102 => x"00000000",
32103 => x"00000000", 32104 => x"00000000", 32105 => x"00000000",
32106 => x"00000000", 32107 => x"00000000", 32108 => x"00000000",
32109 => x"00000000", 32110 => x"00000000", 32111 => x"00000000",
32112 => x"00000000", 32113 => x"00000000", 32114 => x"00000000",
32115 => x"00000000", 32116 => x"00000000", 32117 => x"00000000",
32118 => x"00000000", 32119 => x"00000000", 32120 => x"00000000",
32121 => x"00000000", 32122 => x"00000000", 32123 => x"00000000",
32124 => x"00000000", 32125 => x"00000000", 32126 => x"00000000",
32127 => x"00000000", 32128 => x"00000000", 32129 => x"00000000",
32130 => x"00000000", 32131 => x"00000000", 32132 => x"00000000",
32133 => x"00000000", 32134 => x"00000000", 32135 => x"00000000",
32136 => x"00000000", 32137 => x"00000000", 32138 => x"00000000",
32139 => x"00000000", 32140 => x"00000000", 32141 => x"00000000",
32142 => x"00000000", 32143 => x"00000000", 32144 => x"00000000",
32145 => x"00000000", 32146 => x"00000000", 32147 => x"00000000",
32148 => x"00000000", 32149 => x"00000000", 32150 => x"00000000",
32151 => x"00000000", 32152 => x"00000000", 32153 => x"00000000",
32154 => x"00000000", 32155 => x"00000000", 32156 => x"00000000",
32157 => x"00000000", 32158 => x"00000000", 32159 => x"00000000",
32160 => x"00000000", 32161 => x"00000000", 32162 => x"00000000",
32163 => x"00000000", 32164 => x"00000000", 32165 => x"00000000",
32166 => x"00000000", 32167 => x"00000000", 32168 => x"00000000",
32169 => x"00000000", 32170 => x"00000000", 32171 => x"00000000",
32172 => x"00000000", 32173 => x"00000000", 32174 => x"00000000",
32175 => x"00000000", 32176 => x"00000000", 32177 => x"00000000",
32178 => x"00000000", 32179 => x"00000000", 32180 => x"00000000",
32181 => x"00000000", 32182 => x"00000000", 32183 => x"00000000",
32184 => x"00000000", 32185 => x"00000000", 32186 => x"00000000",
32187 => x"00000000", 32188 => x"00000000", 32189 => x"00000000",
32190 => x"00000000", 32191 => x"00000000", 32192 => x"00000000",
32193 => x"00000000", 32194 => x"00000000", 32195 => x"00000000",
32196 => x"00000000", 32197 => x"00000000", 32198 => x"00000000",
32199 => x"00000000", 32200 => x"00000000", 32201 => x"00000000",
32202 => x"00000000", 32203 => x"00000000", 32204 => x"00000000",
32205 => x"00000000", 32206 => x"00000000", 32207 => x"00000000",
32208 => x"00000000", 32209 => x"00000000", 32210 => x"00000000",
32211 => x"00000000", 32212 => x"00000000", 32213 => x"00000000",
32214 => x"00000000", 32215 => x"00000000", 32216 => x"00000000",
32217 => x"00000000", 32218 => x"00000000", 32219 => x"00000000",
32220 => x"00000000", 32221 => x"00000000", 32222 => x"00000000",
32223 => x"00000000", 32224 => x"00000000", 32225 => x"00000000",
32226 => x"00000000", 32227 => x"00000000", 32228 => x"00000000",
32229 => x"00000000", 32230 => x"00000000", 32231 => x"00000000",
32232 => x"00000000", 32233 => x"00000000", 32234 => x"00000000",
32235 => x"00000000", 32236 => x"00000000", 32237 => x"00000000",
32238 => x"00000000", 32239 => x"00000000", 32240 => x"00000000",
32241 => x"00000000", 32242 => x"00000000", 32243 => x"00000000",
32244 => x"00000000", 32245 => x"00000000", 32246 => x"00000000",
32247 => x"00000000", 32248 => x"00000000", 32249 => x"00000000",
32250 => x"00000000", 32251 => x"00000000", 32252 => x"00000000",
32253 => x"00000000", 32254 => x"00000000", 32255 => x"00000000",
32256 => x"00000000", 32257 => x"00000000", 32258 => x"00000000",
32259 => x"00000000", 32260 => x"00000000", 32261 => x"00000000",
32262 => x"00000000", 32263 => x"00000000", 32264 => x"00000000",
32265 => x"00000000", 32266 => x"00000000", 32267 => x"00000000",
32268 => x"00000000", 32269 => x"00000000", 32270 => x"00000000",
32271 => x"00000000", 32272 => x"00000000", 32273 => x"00000000",
32274 => x"00000000", 32275 => x"00000000", 32276 => x"00000000",
32277 => x"00000000", 32278 => x"00000000", 32279 => x"00000000",
32280 => x"00000000", 32281 => x"00000000", 32282 => x"00000000",
32283 => x"00000000", 32284 => x"00000000", 32285 => x"00000000",
32286 => x"00000000", 32287 => x"00000000", 32288 => x"00000000",
32289 => x"00000000", 32290 => x"00000000", 32291 => x"00000000",
32292 => x"00000000", 32293 => x"00000000", 32294 => x"00000000",
32295 => x"00000000", 32296 => x"00000000", 32297 => x"00000000",
32298 => x"00000000", 32299 => x"00000000", 32300 => x"00000000",
32301 => x"00000000", 32302 => x"00000000", 32303 => x"00000000",
32304 => x"00000000", 32305 => x"00000000", 32306 => x"00000000",
32307 => x"00000000", 32308 => x"00000000", 32309 => x"00000000",
32310 => x"00000000", 32311 => x"00000000", 32312 => x"00000000",
32313 => x"00000000", 32314 => x"00000000", 32315 => x"00000000",
32316 => x"00000000", 32317 => x"00000000", 32318 => x"00000000",
32319 => x"00000000", 32320 => x"00000000", 32321 => x"00000000",
32322 => x"00000000", 32323 => x"00000000", 32324 => x"00000000",
32325 => x"00000000", 32326 => x"00000000", 32327 => x"00000000",
32328 => x"00000000", 32329 => x"00000000", 32330 => x"00000000",
32331 => x"00000000", 32332 => x"00000000", 32333 => x"00000000",
32334 => x"00000000", 32335 => x"00000000", 32336 => x"00000000",
32337 => x"00000000", 32338 => x"00000000", 32339 => x"00000000",
32340 => x"00000000", 32341 => x"00000000", 32342 => x"00000000",
32343 => x"00000000", 32344 => x"00000000", 32345 => x"00000000",
32346 => x"00000000", 32347 => x"00000000", 32348 => x"00000000",
32349 => x"00000000", 32350 => x"00000000", 32351 => x"00000000",
32352 => x"00000000", 32353 => x"00000000", 32354 => x"00000000",
32355 => x"00000000", 32356 => x"00000000", 32357 => x"00000000",
32358 => x"00000000", 32359 => x"00000000", 32360 => x"00000000",
32361 => x"00000000", 32362 => x"00000000", 32363 => x"00000000",
32364 => x"00000000", 32365 => x"00000000", 32366 => x"00000000",
32367 => x"00000000", 32368 => x"00000000", 32369 => x"00000000",
32370 => x"00000000", 32371 => x"00000000", 32372 => x"00000000",
32373 => x"00000000", 32374 => x"00000000", 32375 => x"00000000",
32376 => x"00000000", 32377 => x"00000000", 32378 => x"00000000",
32379 => x"00000000", 32380 => x"00000000", 32381 => x"00000000",
32382 => x"00000000", 32383 => x"00000000", 32384 => x"00000000",
32385 => x"00000000", 32386 => x"00000000", 32387 => x"00000000",
32388 => x"00000000", 32389 => x"00000000", 32390 => x"00000000",
32391 => x"00000000", 32392 => x"00000000", 32393 => x"00000000",
32394 => x"00000000", 32395 => x"00000000", 32396 => x"00000000",
32397 => x"00000000", 32398 => x"00000000", 32399 => x"00000000",
32400 => x"00000000", 32401 => x"00000000", 32402 => x"00000000",
32403 => x"00000000", 32404 => x"00000000", 32405 => x"00000000",
32406 => x"00000000", 32407 => x"00000000", 32408 => x"00000000",
32409 => x"00000000", 32410 => x"00000000", 32411 => x"00000000",
32412 => x"00000000", 32413 => x"00000000", 32414 => x"00000000",
32415 => x"00000000", 32416 => x"00000000", 32417 => x"00000000",
32418 => x"00000000", 32419 => x"00000000", 32420 => x"00000000",
32421 => x"00000000", 32422 => x"00000000", 32423 => x"00000000",
32424 => x"00000000", 32425 => x"00000000", 32426 => x"00000000",
32427 => x"00000000", 32428 => x"00000000", 32429 => x"00000000",
32430 => x"00000000", 32431 => x"00000000", 32432 => x"00000000",
32433 => x"00000000", 32434 => x"00000000", 32435 => x"00000000",
32436 => x"00000000", 32437 => x"00000000", 32438 => x"00000000",
32439 => x"00000000", 32440 => x"00000000", 32441 => x"00000000",
32442 => x"00000000", 32443 => x"00000000", 32444 => x"00000000",
32445 => x"00000000", 32446 => x"00000000", 32447 => x"00000000",
32448 => x"00000000", 32449 => x"00000000", 32450 => x"00000000",
32451 => x"00000000", 32452 => x"00000000", 32453 => x"00000000",
32454 => x"00000000", 32455 => x"00000000", 32456 => x"00000000",
32457 => x"00000000", 32458 => x"00000000", 32459 => x"00000000",
32460 => x"00000000", 32461 => x"00000000", 32462 => x"00000000",
32463 => x"00000000", 32464 => x"00000000", 32465 => x"00000000",
32466 => x"00000000", 32467 => x"00000000", 32468 => x"00000000",
32469 => x"00000000", 32470 => x"00000000", 32471 => x"00000000",
32472 => x"00000000", 32473 => x"00000000", 32474 => x"00000000",
32475 => x"00000000", 32476 => x"00000000", 32477 => x"00000000",
32478 => x"00000000", 32479 => x"00000000", 32480 => x"00000000",
32481 => x"00000000", 32482 => x"00000000", 32483 => x"00000000",
32484 => x"00000000", 32485 => x"00000000", 32486 => x"00000000",
32487 => x"00000000", 32488 => x"00000000", 32489 => x"00000000",
32490 => x"00000000", 32491 => x"00000000", 32492 => x"00000000",
32493 => x"00000000", 32494 => x"00000000", 32495 => x"00000000",
32496 => x"00000000", 32497 => x"00000000", 32498 => x"00000000",
32499 => x"00000000", 32500 => x"00000000", 32501 => x"00000000",
32502 => x"00000000", 32503 => x"00000000", 32504 => x"00000000",
32505 => x"00000000", 32506 => x"00000000", 32507 => x"00000000",
32508 => x"00000000", 32509 => x"00000000", 32510 => x"00000000",
32511 => x"00000000", 32512 => x"00000000", 32513 => x"00000000",
32514 => x"00000000", 32515 => x"00000000", 32516 => x"00000000",
32517 => x"00000000", 32518 => x"00000000", 32519 => x"00000000",
32520 => x"00000000", 32521 => x"00000000", 32522 => x"00000000",
32523 => x"00000000", 32524 => x"00000000", 32525 => x"00000000",
32526 => x"00000000", 32527 => x"00000000", 32528 => x"00000000",
32529 => x"00000000", 32530 => x"00000000", 32531 => x"00000000",
32532 => x"00000000", 32533 => x"00000000", 32534 => x"00000000",
32535 => x"00000000", 32536 => x"00000000", 32537 => x"00000000",
32538 => x"00000000", 32539 => x"00000000", 32540 => x"00000000",
32541 => x"00000000", 32542 => x"00000000", 32543 => x"00000000",
32544 => x"00000000", 32545 => x"00000000", 32546 => x"00000000",
32547 => x"00000000", 32548 => x"00000000", 32549 => x"00000000",
32550 => x"00000000", 32551 => x"00000000", 32552 => x"00000000",
32553 => x"00000000", 32554 => x"00000000", 32555 => x"00000000",
32556 => x"00000000", 32557 => x"00000000", 32558 => x"00000000",
32559 => x"00000000", 32560 => x"00000000", 32561 => x"00000000",
32562 => x"00000000", 32563 => x"00000000", 32564 => x"00000000",
32565 => x"00000000", 32566 => x"00000000", 32567 => x"00000000",
32568 => x"00000000", 32569 => x"00000000", 32570 => x"00000000",
32571 => x"00000000", 32572 => x"00000000", 32573 => x"00000000",
32574 => x"00000000", 32575 => x"00000000", 32576 => x"00000000",
32577 => x"00000000", 32578 => x"00000000", 32579 => x"00000000",
32580 => x"00000000", 32581 => x"00000000", 32582 => x"00000000",
32583 => x"00000000", 32584 => x"00000000", 32585 => x"00000000",
32586 => x"00000000", 32587 => x"00000000", 32588 => x"00000000",
32589 => x"00000000", 32590 => x"00000000", 32591 => x"00000000",
32592 => x"00000000", 32593 => x"00000000", 32594 => x"00000000",
32595 => x"00000000", 32596 => x"00000000", 32597 => x"00000000",
32598 => x"00000000", 32599 => x"00000000", 32600 => x"00000000",
32601 => x"00000000", 32602 => x"00000000", 32603 => x"00000000",
32604 => x"00000000", 32605 => x"00000000", 32606 => x"00000000",
32607 => x"00000000", 32608 => x"00000000", 32609 => x"00000000",
32610 => x"00000000", 32611 => x"00000000", 32612 => x"00000000",
32613 => x"00000000", 32614 => x"00000000", 32615 => x"00000000",
32616 => x"00000000", 32617 => x"00000000", 32618 => x"00000000",
32619 => x"00000000", 32620 => x"00000000", 32621 => x"00000000",
32622 => x"00000000", 32623 => x"00000000", 32624 => x"00000000",
32625 => x"00000000", 32626 => x"00000000", 32627 => x"00000000",
32628 => x"00000000", 32629 => x"00000000", 32630 => x"00000000",
32631 => x"00000000", 32632 => x"00000000", 32633 => x"00000000",
32634 => x"00000000", 32635 => x"00000000", 32636 => x"00000000",
32637 => x"00000000", 32638 => x"00000000", 32639 => x"00000000",
32640 => x"00000000", 32641 => x"00000000", 32642 => x"00000000",
32643 => x"00000000", 32644 => x"00000000", 32645 => x"00000000",
32646 => x"00000000", 32647 => x"00000000", 32648 => x"00000000",
32649 => x"00000000", 32650 => x"00000000", 32651 => x"00000000",
32652 => x"00000000", 32653 => x"00000000", 32654 => x"00000000",
32655 => x"00000000", 32656 => x"00000000", 32657 => x"00000000",
32658 => x"00000000", 32659 => x"00000000", 32660 => x"00000000",
32661 => x"00000000", 32662 => x"00000000", 32663 => x"00000000",
32664 => x"00000000", 32665 => x"00000000", 32666 => x"00000000",
32667 => x"00000000", 32668 => x"00000000", 32669 => x"00000000",
32670 => x"00000000", 32671 => x"00000000", 32672 => x"00000000",
32673 => x"00000000", 32674 => x"00000000", 32675 => x"00000000",
32676 => x"00000000", 32677 => x"00000000", 32678 => x"00000000",
32679 => x"00000000", 32680 => x"00000000", 32681 => x"00000000",
32682 => x"00000000", 32683 => x"00000000", 32684 => x"00000000",
32685 => x"00000000", 32686 => x"00000000", 32687 => x"00000000",
32688 => x"00000000", 32689 => x"00000000", 32690 => x"00000000",
32691 => x"00000000", 32692 => x"00000000", 32693 => x"00000000",
32694 => x"00000000", 32695 => x"00000000", 32696 => x"00000000",
32697 => x"00000000", 32698 => x"00000000", 32699 => x"00000000",
32700 => x"00000000", 32701 => x"00000000", 32702 => x"00000000",
32703 => x"00000000", 32704 => x"00000000", 32705 => x"00000000",
32706 => x"00000000", 32707 => x"00000000", 32708 => x"00000000",
32709 => x"00000000", 32710 => x"00000000", 32711 => x"00000000",
32712 => x"00000000", 32713 => x"00000000", 32714 => x"00000000",
32715 => x"00000000", 32716 => x"00000000", 32717 => x"00000000",
32718 => x"00000000", 32719 => x"00000000", 32720 => x"00000000",
32721 => x"00000000", 32722 => x"00000000", 32723 => x"00000000",
32724 => x"00000000", 32725 => x"00000000", 32726 => x"00000000",
32727 => x"00000000", 32728 => x"00000000", 32729 => x"00000000",
32730 => x"00000000", 32731 => x"00000000", 32732 => x"00000000",
32733 => x"00000000", 32734 => x"00000000", 32735 => x"00000000",
32736 => x"00000000", 32737 => x"00000000", 32738 => x"00000000",
32739 => x"00000000", 32740 => x"00000000", 32741 => x"00000000",
32742 => x"00000000", 32743 => x"00000000", 32744 => x"00000000",
32745 => x"00000000", 32746 => x"00000000", 32747 => x"00000000",
32748 => x"00000000", 32749 => x"00000000", 32750 => x"00000000",
32751 => x"00000000", 32752 => x"00000000", 32753 => x"00000000",
32754 => x"00000000", 32755 => x"00000000", 32756 => x"00000000",
32757 => x"00000000", 32758 => x"00000000", 32759 => x"00000000",
32760 => x"00000000", 32761 => x"00000000", 32762 => x"00000000",
32763 => x"00000000", 32764 => x"00000000", 32765 => x"00000000",
32766 => x"00000000", 32767 => x"00000000");
end dbe_lwip_bin_pkg;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_gen.vhd
|
1
|
7366
|
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 01:03:24
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ecc/ecc_gen.v
-- Component name : ecc_gen
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Generate the ecc code. Note that the synthesizer should
-- generate this as a static logic. Code in this block should
-- never run during simulation phase, or directly impact timing.
--
-- The code generated is a single correct, double detect code.
-- It is the classic Hamming code. Instead, the code is
-- optimized for minimal/balanced tree depth and size. See
-- Hsiao IBM Technial Journal 1970.
--
-- The code is returned as a single bit vector, h_rows. This was
-- the only way to "subroutinize" this with the restrictions of
-- disallowed include files and that matrices cannot be passed
-- in ports.
--
-- Factorial and the combos functions are defined. Combos
-- simply computes the number of combinations from the set
-- size and elements at a time.
--
-- The function next_combo computes the next combination in
-- lexicographical order given the "current" combination. Its
-- output is undefined if given the last combination in the
-- lexicographical order.
--
-- next_combo is insensitive to the number of elements in the
-- combinations.
--
-- An H transpose matrix is generated because that's the easiest
-- way to do it. The H transpose matrix is generated by taking
-- the one at a time combinations, then the 3 at a time, then
-- the 5 at a time. The number combinations used is equal to
-- the width of the code (CODE_WIDTH). The boundaries between
-- the 1, 3 and 5 groups are hardcoded in the for loop.
--
-- At the same time the h_rows vector is generated from the
-- H transpose matrix.
entity ecc_gen is
generic (
CODE_WIDTH : integer := 72;
ECC_WIDTH : integer := 8;
DATA_WIDTH : integer := 64
);
port (
-- Outputs
-- function next_combo
-- Given a combination, return the next combo in lexicographical
-- order. Scans from right to left. Assumes the first combination
-- is k ones all of the way to the left.
--
-- Upon entry, initialize seen0, trig1, and ones. "seen0" means
-- that a zero has been observed while scanning from right to left.
-- "trig1" means that a one have been observed _after_ seen0 is set.
-- "ones" counts the number of ones observed while scanning the input.
--
-- If trig1 is one, just copy the input bit to the output and increment
-- to the next bit. Otherwise set the the output bit to zero, if the
-- input is a one, increment ones. If the input bit is a one and seen0
-- is true, dump out the accumulated ones. Set seen0 to the complement
-- of the input bit. Note that seen0 is not used subsequent to trig1
-- getting set.
-- The stuff above leads to excessive XST execution times. For now, hardwire to 72/64 bit.
h_rows : out std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
end entity ecc_gen;
architecture trans of ecc_gen is
function factorial (ivar: integer) return integer is
variable tmp : integer;
begin
if (ivar = 1) then
return 1;
else
tmp := 1;
for i in ivar downto 2 loop
tmp := tmp * i;
end loop;
end if;
return tmp;
end function factorial;
function combos ( n, k: integer) return integer is
begin
return factorial(n)/(factorial(k)*factorial(n-k));
end function combos;
function next_combo (i: std_logic_vector) return std_logic_vector is
variable seen0: std_logic;
variable trig1: std_logic;
variable ones: std_logic_vector (ECC_WIDTH-1 downto 0);
variable tmp: std_logic_vector (ECC_WIDTH-1 downto 0);
variable tmp_index : integer;
begin
seen0 := '0';
trig1 := '0';
ones := (others => '0');
for index in ECC_WIDTH -1 downto 0 loop
tmp_index := ECC_WIDTH -1 - index;
if (trig1 = '1') then
tmp(tmp_index) := i(tmp_index);
else
tmp(tmp_index) := '0';
ones := ones + i(tmp_index);
if ((i(tmp_index) = '1') and (seen0 = '1')) then
trig1 := '1';
for dump_index in tmp_index-1 downto 0 loop
if (dump_index >= (tmp_index- conv_integer(ones)) ) then
tmp(dump_index) := '1';
end if;
end loop;
end if;
seen0 := not(i(tmp_index));
end if;
end loop;
return tmp;
end function next_combo;
constant COMBOS_3 : integer := combos(ECC_WIDTH, 3);
constant COMBOS_5 : integer := combos(ECC_WIDTH, 5);
type twoDarray is array (CODE_WIDTH -1 downto 0) of std_logic_vector (ECC_WIDTH-1 downto 0);
signal ht_matrix : twoDarray;
begin
columns: for n in CODE_WIDTH - 1 downto 0 generate
column0: if (n = 0) generate
ht_matrix(n) <= "111" & conv_std_logic_vector(0,ECC_WIDTH-3);
end generate;
column_combos3: if ((n = COMBOS_3) and ( n < DATA_WIDTH) ) generate
ht_matrix(n) <= "11111" & conv_std_logic_vector(0,ECC_WIDTH-5);
end generate;
column_combos5: if ((n = COMBOS_3 + COMBOS_5) and ( n < DATA_WIDTH) ) generate
ht_matrix(n) <= "1111111" & conv_std_logic_vector(0,ECC_WIDTH-7);
end generate;
column_datawidth: if (n = DATA_WIDTH) generate
ht_matrix(n) <= "1" & conv_std_logic_vector(0,ECC_WIDTH-1);
end generate;
column_gen: if ( (n /= 0 ) and ((n /= COMBOS_3) or (n > DATA_WIDTH)) and ((n /= COMBOS_3+COMBOS_5) or (n > DATA_WIDTH)) and (n /= DATA_WIDTH) ) generate
ht_matrix(n) <= next_combo(ht_matrix(n-1));
end generate;
out_assign: for s in ECC_WIDTH-1 downto 0 generate
h_rows(s*CODE_WIDTH+n) <= ht_matrix(n)(s);
end generate;
end generate;
--h_row0 <= "100000000100100011101101001101001000110100100010000110100100010000100000";
--h_row1 <= "010000001010010011011010101010100100101010010001000101010010001000010000";
--h_row2 <= "001000001001001010110110010110010010011001001000100011001001000100001000";
--h_row3 <= "000100000111000101110001110001110001000111000100010000111000100010000100";
--h_row4 <= "000010000000111100001111110000001111000000111100001000000111100001000010";
--h_row5 <= "000001001111111100000000001111111111000000000011111000000000011111000001";
--h_row6 <= "000000101111111100000000000000000000111111111111111000000000000000111111";
--h_row7 <= "000000011111111100000000000000000000000000000000000111111111111111111111";
--h_rows <= (h_row7 & h_row6 & h_row5 & h_row4 & h_row3 & h_row2 & h_row1 & h_row0);
end architecture trans;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd
|
1
|
16066
|
-------------------------------------------------------------------------------------
-- FILE NAME : ads62p49_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - ads62p49_ctrl
-- architecture - ads62p49_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the ADS62P49 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity ads62p49_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
adc_reset : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end ads62p49_ctrl;
architecture ads62p49_ctrl_syn of ads62p49_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component ads62p49_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(4 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000077";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0000076";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"0000076";
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal reset : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(15 downto 0);
signal init_address : std_logic_vector(4 downto 0);
signal init_data : std_logic_vector(15 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
gen_serial_clk : if (g_sim = 0) generate
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the rising edge of SCLK.
-- therefore we make sure the external clock is slightly
-- after the internal clock.
serial_clk <= clk_div(clk_div'length-1);
sclk_ext <= serial_clk;
end if;
end process;
end generate;
-- Do not divide clock. Improve simulation speed.
gen_serial_clk_sim : if (g_sim = 1) generate
serial_clk <= clk;
end generate;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
reset <= '1';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
reset <= out_reg(1);
else
reset <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 27) & '0' & busy & '0' & reset & init_done_prev;
-- read from serial if when address is within device range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(7 downto 0);
data_reg <= out_reg(7 downto 0);
-- Read instruction, only when address is within device range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(7 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 1;
--end generate;
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= sh_counter_gen;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= init_data;
-- Stop when update instruction is reveived (= last instruction)
if (init_data(15 downto 8) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length - 2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
ads62p49_init_mem_inst : ads62p49_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
adc_reset <= reset;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end ads62p49_ctrl_syn;
|
lgpl-3.0
|
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd
|
1
|
24774
|
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ui_rd_data.v
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Tue Jun 30 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
-- User interface read buffer. Re orders read data returned from the
-- memory controller back to the request order.
--
-- Consists of a large buffer for the data, a status RAM and two counters.
--
-- The large buffer is implemented with distributed RAM in 6 bit wide,
-- 1 read, 1 write mode. The status RAM is implemented with a distributed
-- RAM configured as 2 bits wide 1 read/write, 1 read mode.
--
-- As read requests are received from the application, the data_buf_addr
-- counter supplies the data_buf_addr sent into the memory controller.
-- With each read request, the counter is incremented, eventually rolling
-- over. This mechanism labels each read request with an incrementing number.
--
-- When the memory controller returns read data, it echos the original
-- data_buf_addr with the read data.
--
-- The status RAM is indexed with the same address as the data buffer
-- RAM. Each word of the data buffer RAM has an associated status bit
-- and "end" bit. Requests of size 1 return a data burst on two consecutive
-- states. Requests of size zero return with a single assertion of rd_data_en.
--
-- Upon returning data, the status and end bits are updated for each
-- corresponding location in the status RAM indexed by the data_buf_addr
-- echoed on the rd_data_addr field.
--
-- The other side of the status and data RAMs is indexed by the rd_buf_indx.
-- The rd_buf_indx constantly monitors the status bit it is currently
-- pointing to. When the status becomes set to the proper state (more on
-- this later) read data is returned to the application, and the rd_buf_indx
-- is incremented.
--
-- At rst the rd_buf_indx is initialized to zero. Data will not have been
-- returned from the memory controller yet, so there is nothing to return
-- to the application. Evenutally, read requests will be made, and the
-- memory controller will return the corresponding data. The memory
-- controller may not return this data in the request order. In which
-- case, the status bit at location zero, will not indicate
-- the data for request zero is ready. Eventually, the memory controller
-- will return data for request zero. The data is forwarded on to the
-- application, and rd_buf_indx is incremented to point to the next status
-- bits and data in the buffers. The status bit will be examined, and if
-- data is valid, this data will be returned as well. This process
-- continues until the status bit indexed by rd_buf_indx indicates data
-- is not ready. This may be because the rd_data_buf
-- is empty, or that some data was returned out of order. Since rd_buf_indx
-- always increments sequentially, data is always returned to the application
-- in request order.
--
-- Some further discussion of the status bit is in order. The rd_data_buf
-- is a circular buffer. The status bit is a single bit. Distributed RAM
-- supports only a single write port. The write port is consumed by
-- memory controller read data updates. If a simple '1' were used to
-- indicate the status, when rd_data_indx rolled over it would immediately
-- encounter a one for a request that may not be ready.
--
-- This problem is solved by causing read data returns to flip the
-- status bit, and adding hi order bit beyond the size required to
-- index the rd_data_buf. Data is considered ready when the status bit
-- and this hi order bit are equal.
--
-- The status RAM needs to be initialized to zero after reset. This is
-- accomplished by cycling through all rd_buf_indx valus and writing a
-- zero to the status bits directly following deassertion of reset. This
-- mechanism is used for similar purposes
-- for the wr_data_buf.
--
-- When ORDERING == "STRICT", read data reordering is unnecessary. For thi
-- case, most of the logic in the block is not generated.
-- User interface read data.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
LIBRARY unisim;
USE unisim.VCOMPONENTS.all;
ENTITY ui_rd_data IS
GENERIC (
TCQ : INTEGER := 100;
APP_DATA_WIDTH : INTEGER := 256;
ECC : STRING := "OFF";
ORDERING : STRING := "NORM"
);
PORT (
ram_init_done_r : OUT STD_LOGIC;
ram_init_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
app_rd_data_valid : OUT STD_LOGIC;
app_rd_data_end : OUT STD_LOGIC;
app_rd_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_ecc_multiple_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_buf_full : OUT STD_LOGIC;
rd_data_buf_addr_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
rd_data_en : IN STD_LOGIC;
rd_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_offset : IN STD_LOGIC;
rd_data_end : IN STD_LOGIC;
rd_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
ecc_multiple : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_accepted : IN STD_LOGIC
);
END ENTITY ui_rd_data;
ARCHITECTURE trans OF ui_rd_data IS
SIGNAL rd_buf_indx_r : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL ram_init_done_r_lcl : STD_LOGIC;
SIGNAL app_rd_data_valid_ns : STD_LOGIC;
SIGNAL app_rd_data_valid_copy : STD_LOGIC;
SIGNAL single_data : STD_LOGIC;
SIGNAL app_ecc_multiple_err_r : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
FUNCTION CALC_RD_BUF_WIDTH ( APP_DATA_WIDTH : integer; ECC : string) RETURN integer is
BEGIN
IF ( ECC = "OFF" ) THEN
RETURN APP_DATA_WIDTH;
ELSE
RETURN APP_DATA_WIDTH + 4;
END IF;
END FUNCTION CALC_RD_BUF_WIDTH;
FUNCTION CALC_RAM_CNT ( FULL_RAM_CNT,REMAINDER: integer) RETURN integer is
BEGIN
IF ( REMAINDER = 0 ) THEN
RETURN FULL_RAM_CNT;
ELSE
RETURN FULL_RAM_CNT + 1;
END IF;
END FUNCTION CALC_RAM_CNT;
-- Compute dimensions of read data buffer. Depending on width of
-- DQ bus and DRAM CK
-- to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in
-- single write, single read, 6 bit wide mode.
CONSTANT RD_BUF_WIDTH : INTEGER := CALC_RD_BUF_WIDTH(APP_DATA_WIDTH,ECC);
CONSTANT FULL_RAM_CNT : INTEGER := (RD_BUF_WIDTH/6);
CONSTANT REMAINDER : INTEGER := (RD_BUF_WIDTH mod 6);
CONSTANT RAM_CNT : INTEGER := CALC_RAM_CNT(FULL_RAM_CNT,REMAINDER);
CONSTANT RAM_WIDTH : INTEGER := (RAM_CNT * 6);
-- X-HDL generated signals
SIGNAL xhdl11 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL upd_rd_buf_indx : STD_LOGIC;
SIGNAL ram_init_done_ns : STD_LOGIC;
SIGNAL rd_buf_indx_ns : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL rd_data_buf_addr_ns : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rd_data_buf_addr_r_lcl : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
SIGNAL rd_buf_wr_addr : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rd_status : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL status_ram_wr_addr_ns : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL status_ram_wr_addr_r : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wr_status : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wr_status_r1 : STD_LOGIC;
SIGNAL status_ram_wr_data_ns : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL status_ram_wr_data_r : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL rd_buf_we_r1 : STD_LOGIC;
SIGNAL rd_buf_out_data : STD_LOGIC_VECTOR (RAM_WIDTH-1 DOWNTO 0);
SIGNAL rd_buf_indx_copy_r : STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
SIGNAL rd_buf_in_data : STD_LOGIC_VECTOR (RAM_WIDTH-1 DOWNTO 0);
SIGNAL rd_data_rdy : STD_LOGIC;
SIGNAL bypass : STD_LOGIC;
SIGNAL app_rd_data_end_ns : STD_LOGIC;
SIGNAL app_rd_data_ns : STD_LOGIC_VECTOR (APP_DATA_WIDTH-1 DOWNTO 0);
SIGNAL app_ecc_multiple_err_ns : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL free_rd_buf : STD_LOGIC;
SIGNAL occ_cnt_r : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL occ_minus_one : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL occ_plus_one : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL occ_cnt_ns : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rd_buf_we : STD_LOGIC;
SIGNAL app_rd_data_end_int : STD_LOGIC;
ATTRIBUTE equivalent_register_removal : string;
ATTRIBUTE equivalent_register_removal of rd_buf_indx_copy_r : signal is "no";
ATTRIBUTE equivalent_register_removal of app_rd_data_valid_copy : SIGNAL IS "no";
BEGIN
--This signal is added have the internal usage of the port
--app_rd_data_end
app_rd_data_end <= app_rd_data_end_int;
-- rd_buf_indx points to the status and data storage rams for
-- reading data out to the app.
ram_init_done_r <= ram_init_done_r_lcl;
upd_rd_buf_indx <= NOT(ram_init_done_r_lcl) OR app_rd_data_valid_ns;
-- Loop through all status write addresses once after rst. Initializes
-- the status and pointer RAMs.
ram_init_done_ns <= NOT(rst) when (rd_buf_indx_r(4 DOWNTO 0) = "11111") else NOT(rst) AND ram_init_done_r_lcl ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
ram_init_done_r_lcl <= ram_init_done_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (rd_buf_indx_r, rst, single_data, upd_rd_buf_indx)
BEGIN
rd_buf_indx_ns <= rd_buf_indx_r;
IF (rst = '1') THEN
rd_buf_indx_ns <= "000000";
ELSIF (upd_rd_buf_indx = '1') THEN
rd_buf_indx_ns <= rd_buf_indx_r + "000001" + ("00000" & single_data);
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_buf_indx_r <= rd_buf_indx_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
ram_init_addr <= rd_buf_indx_r(3 DOWNTO 0);
app_ecc_multiple_err <= app_ecc_multiple_err_r;
xhdl0 : IF (ORDERING = "STRICT") GENERATE
app_rd_data_valid_ns <= '0';
single_data <= '0';
rd_buf_full <= '0';
rd_data_buf_addr_ns <= "0000" WHEN (rst = '1') ELSE
rd_data_buf_addr_r_lcl + ("000" & rd_accepted);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_data_buf_addr_r_lcl <= rd_data_buf_addr_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
rd_data_buf_addr_r <= rd_data_buf_addr_ns;
-- app_* signals required to be registered.
xhdl1 : IF (ECC = "OFF") GENERATE
PROCESS (rd_data)
BEGIN
app_rd_data <= rd_data;
END PROCESS;
PROCESS (rd_data_en)
BEGIN
app_rd_data_valid <= rd_data_en;
END PROCESS;
PROCESS (rd_data_end)
BEGIN
app_rd_data_end_int <= rd_data_end;
END PROCESS;
END GENERATE;
xhdl2 : IF (NOT(ECC = "OFF")) GENERATE
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data <= rd_data AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_valid <= rd_data_en AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_end_int <= rd_data_end AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_ecc_multiple_err_r <= ecc_multiple AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
END GENERATE;
END GENERATE;
xhdl3 : IF (NOT(ORDERING = "STRICT")) GENERATE
rd_buf_we <= NOT(ram_init_done_r_lcl) OR rd_data_en;
rd_buf_wr_addr <= (rd_data_addr & rd_data_offset);
-- Instantiate status RAM. One bit for status and one for "end".
-- Turns out read to write back status is a timing path. Update
-- the status in the ram on the state following the read. Bypass
-- the write data into the status read path.
status_ram_wr_addr_ns <= rd_buf_wr_addr WHEN (ram_init_done_r_lcl = '1') ELSE
rd_buf_indx_r(4 DOWNTO 0);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
status_ram_wr_addr_r <= status_ram_wr_addr_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
-- Not guaranteed to write second status bit. If it is written, always
-- copy in the first status bit.
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
wr_status_r1 <= wr_status(0) AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
status_ram_wr_data_ns <= "00" WHEN ( ram_init_done_r_lcl = '0') ELSE
(rd_data_end & NOT( wr_status_r1 )) WHEN (rd_data_offset = '1') ELSE
(rd_data_end & NOT( wr_status(0) ));
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
status_ram_wr_data_r <= status_ram_wr_data_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_buf_we_r1 <= rd_buf_we AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
RAM32M0 : RAM32M
GENERIC MAP (
init_a => "0000000000000000000000000000000000000000000000000000000000000000",
init_b => "0000000000000000000000000000000000000000000000000000000000000000",
init_c => "0000000000000000000000000000000000000000000000000000000000000000",
init_d => "0000000000000000000000000000000000000000000000000000000000000000"
)
PORT MAP (
doa => rd_status,
dob => open,
doc => wr_status,
dod => open,
dia => status_ram_wr_data_r,
dib => "00",
dic => status_ram_wr_data_r,
did => status_ram_wr_data_r,
addra => rd_buf_indx_r(4 DOWNTO 0),
addrb => "00000",
addrc => status_ram_wr_addr_ns,
addrd => status_ram_wr_addr_r,
we => rd_buf_we_r1,
wclk => clk
);
-- block: status_ram
xhdl4 : IF (REMAINDER = 0) GENERATE
xhdl5 : IF (ECC = "OFF") GENERATE
rd_buf_in_data <= rd_data;
END GENERATE;
xhdl6 : IF (NOT(ECC = "OFF")) GENERATE
SIGNAL ecc_multiple_rd_data : STD_LOGIC_VECTOR ( APP_DATA_WIDTH + 3 DOWNTO 0 );
BEGIN
ecc_multiple_rd_data <= (ecc_multiple & rd_data);
rd_buf_in_data <= ecc_multiple_rd_data(RAM_WIDTH - 1 DOWNTO 0);
END GENERATE;
END GENERATE;
xhdl7 : IF (NOT(REMAINDER = 0)) GENERATE
xhdl8 : IF (ECC = "OFF") GENERATE
SIGNAL zero_rd_data : STD_LOGIC_VECTOR ( 6-REMAINDER+APP_DATA_WIDTH-1 DOWNTO 0);
BEGIN
zero_rd_data <= (std_logic_vector(to_unsigned(0,6-REMAINDER)) & rd_data);
rd_buf_in_data <= zero_rd_data (RAM_WIDTH-1 DOWNTO 0);
END GENERATE;
xhdl9 : IF (NOT(ECC = "OFF")) GENERATE
SIGNAL zero_ecc_multiple_rd_data : STD_LOGIC_VECTOR ( 6-REMAINDER+APP_DATA_WIDTH+3 DOWNTO 0);
BEGIN
zero_ecc_multiple_rd_data <= (std_logic_vector(to_unsigned(0,6-REMAINDER)) & ecc_multiple & rd_data);
rd_buf_in_data <= zero_ecc_multiple_rd_data(RAM_WIDTH - 1 DOWNTO 0);
END GENERATE;
END GENERATE;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_buf_indx_copy_r <= rd_buf_indx_ns (4 DOWNTO 0);
END IF;
END PROCESS;
rd_buffer_ram : FOR i IN 0 TO RAM_CNT - 1 GENERATE
RAM32M0 : RAM32M
GENERIC MAP (
init_a => "0000000000000000000000000000000000000000000000000000000000000000",
init_b => "0000000000000000000000000000000000000000000000000000000000000000",
init_c => "0000000000000000000000000000000000000000000000000000000000000000",
init_d => "0000000000000000000000000000000000000000000000000000000000000000"
)
PORT MAP (
doa => rd_buf_out_data(((i * 6) + 4) + 1 DOWNTO ((i * 6) + 4)),
dob => rd_buf_out_data(((i * 6) + 2) + 1 DOWNTO ((i * 6) + 2)),
doc => rd_buf_out_data(((i * 6) + 0) + 1 DOWNTO ((i * 6) + 0)),
dod => open,
dia => rd_buf_in_data(((i * 6) + 4) + 1 DOWNTO ((i * 6) + 4)),
dib => rd_buf_in_data(((i * 6) + 2) + 1 DOWNTO ((i * 6) + 2)),
dic => rd_buf_in_data(((i * 6) + 0) + 1 DOWNTO ((i * 6) + 0)),
did => "00",
addra => rd_buf_indx_copy_r(4 DOWNTO 0),
addrb => rd_buf_indx_copy_r(4 DOWNTO 0),
addrc => rd_buf_indx_copy_r(4 DOWNTO 0),
addrd => rd_buf_wr_addr,
we => rd_buf_we,
wclk => clk
);
-- block: rd_buffer_ram
END GENERATE;
rd_data_rdy <= '1' when (rd_status(0) = rd_buf_indx_r(5)) else '0';
bypass <= rd_data_en when (rd_buf_wr_addr(4 DOWNTO 0) = rd_buf_indx_r(4 DOWNTO 0)) else '0';
app_rd_data_valid_ns <= ram_init_done_r_lcl AND (bypass OR rd_data_rdy);
app_rd_data_end_ns <= rd_data_end WHEN (bypass = '1') ELSE
rd_status(1);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_valid <= app_rd_data_valid_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_end_int <= app_rd_data_end_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
single_data <= app_rd_data_valid_ns AND app_rd_data_end_ns AND NOT(rd_buf_indx_r(0));
app_rd_data_ns <= rd_data WHEN (bypass = '1') ELSE
rd_buf_out_data(APP_DATA_WIDTH - 1 DOWNTO 0);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data <= app_rd_data_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
xhdl10 : IF ( NOT(ECC = "OFF")) GENERATE
app_ecc_multiple_err_ns <= ecc_multiple WHEN (bypass = '1') ELSE
rd_buf_out_data(APP_DATA_WIDTH + 3 DOWNTO APP_DATA_WIDTH);
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_ecc_multiple_err_r <= app_ecc_multiple_err_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
-- Keep track of how many entries in the queue hold data.
END GENERATE;
--Added to fix timing. The signal app_rd_data_valid has
--a very high fanout. So making a dedicated copy for usage
--with the occ_cnt counter.
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
app_rd_data_valid_copy <= app_rd_data_valid_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
free_rd_buf <= app_rd_data_valid_copy AND app_rd_data_end_int; --changed to use registered version
--of the signals in ordered to fix timing
occ_minus_one <= occ_cnt_r - "00001";
occ_plus_one <= occ_cnt_r + "00001";
xhdl11 <= rd_accepted & free_rd_buf;
PROCESS (free_rd_buf, occ_cnt_r, rd_accepted, rst, occ_minus_one, occ_plus_one,xhdl11)
BEGIN
occ_cnt_ns <= occ_cnt_r;
IF (rst = '1') THEN
occ_cnt_ns <= "00000";
ELSE
CASE xhdl11 IS
WHEN "01" =>
occ_cnt_ns <= occ_minus_one;
WHEN "10" => -- case ({wr_data_end, new_rd_data})
occ_cnt_ns <= occ_plus_one;
WHEN OTHERS =>
occ_cnt_ns <= occ_cnt_r;
END CASE;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
occ_cnt_r <= occ_cnt_ns AFTER (TCQ)*1 ps;
END IF;
END PROCESS;
rd_buf_full <= occ_cnt_ns(4);
-- block: occupied_counter
-- Generate the data_buf_address written into the memory controller
-- for reads. Increment with each accepted read, and rollover at 0xf.
rd_data_buf_addr_r <= rd_data_buf_addr_r_lcl;
PROCESS (rd_accepted, rd_data_buf_addr_r_lcl, rst)
BEGIN
rd_data_buf_addr_ns <= rd_data_buf_addr_r_lcl;
IF (rst = '1') THEN
rd_data_buf_addr_ns <= "0000";
ELSIF (rd_accepted = '1') THEN
rd_data_buf_addr_ns <= rd_data_buf_addr_r_lcl + "0001";
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
rd_data_buf_addr_r_lcl <= rd_data_buf_addr_ns AFTER (TCQ)*1 ps; -- block: data_buf_addr
END IF;
END PROCESS;
-- block: not_strict_mode
END GENERATE;
-- ui_rd_data
END ARCHITECTURE trans;
|
lgpl-3.0
|
AnttiLukats/opl3_fpga
|
fpga/modules/clks/ip/clk_gen/clk_gen_stub.vhdl
|
2
|
1113
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
-- Date : Sun Mar 8 22:11:52 2015
-- Host : edinburgh running 64-bit Ubuntu 14.10
-- Command : write_vhdl -force -mode synth_stub
-- /media/sf_D_DRIVE/Users/Greg/git/opl3_fpga/fpga/modules/clks/ip/clk_gen/clk_gen_stub.vhdl
-- Design : clk_gen
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_gen is
Port (
clk125 : in STD_LOGIC;
clk : out STD_LOGIC;
clk_locked : out STD_LOGIC
);
end clk_gen;
architecture stub of clk_gen is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk125,clk,clk_locked";
begin
end;
|
lgpl-3.0
|
Ttl/bf_cpu
|
testbenches/cpu_tb.vhd
|
1
|
2101
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
ENTITY cpu_tb IS
END cpu_tb;
ARCHITECTURE behavior OF cpu_tb IS
signal clk, reset, tx, rx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
signal uart_tx_req, uart_tx_end, uart_rx_ready : std_logic;
signal uart_tx_data, uart_rx_data : std_logic_vector(7 downto 0);
BEGIN
-- Component Instantiation
uut: entity work.cpu
Generic map ( INSTRUCTIONS => "scripts/branch.mif"
)
Port map(clk => clk,
reset => reset,
tx => rx,
rx => tx
);
uart1 : entity work.uart
Generic map(
CLK_FREQ => 100,
SER_FREQ => 2000000,
PARITY_BIT => false
)
Port map (
clk => clk,
rst => reset,
rx => rx,
tx => tx,
tx_req => uart_tx_req,
tx_end => uart_tx_end,
tx_data => uart_tx_data,
rx_ready => uart_rx_ready,
rx_data => uart_rx_data
);
-- Print received bytes
uart_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
if to_integer(unsigned(uart_rx_data)) > 31 and to_integer(unsigned(uart_rx_data)) < 127 then
report "Received ASCII: "&character'image(character'val(to_integer(unsigned(uart_rx_data))));
else
report "Received Dec: "&integer'image(to_integer(unsigned(uart_rx_data)));
end if;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
reset <= '1';
uart_tx_req <= '0';
wait for 100 ns; -- wait until global set/reset completes
reset <= '0';
-- Send character
uart_tx_req <= '1';
uart_tx_data <= x"41"; -- A
wait for clk_period;
uart_tx_req <= '0';
wait until uart_tx_end = '1';
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
lgpl-3.0
|
CogPy/cog
|
xUnit/vhdl/somedir/Cents.vhd
|
1
|
1889
|
-------------------------------------------------------------------------------
-- Title : Cents
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity Cents is
port (
Clk : in std_logic;
Clr : in std_logic;
Cents_A : in std_logic_vector(3 downto 0);
Cents_B : in std_logic_vector(3 downto 0);
Cents_AB : out std_logic_vector(4 downto 0)
);
end entity Cents;
-------------------------------------------------------------------------------
architecture str of Cents is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal AB : unsigned(Cents_AB'range);
begin -- architecture str
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
Cents_AB <= std_logic_vector(AB);
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
p_addAandB: process (Clk) is
begin -- process p_addAandB
if Clk'event and Clk = '1' then -- rising clock edge
if Clr = '1' then
AB <= to_unsigned(0, AB'length);
else
AB <= resize(unsigned(Cents_A), AB'length) + resize(unsigned(Cents_B), AB'length);
end if;
end if;
end process p_addAandB;
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
CogPy/cog
|
xUnit/vhdl/A.vhd
|
1
|
3141
|
-------------------------------------------------------------------------------
-- Title : test1
-- Project :
-------------------------------------------------------------------------------
-- File : test1.vhd
-- Author : <kristoffer.nordstrom@HELVNB0100>
-- Company :
-- Created : 2015-04-27
-- Last update: 2015-05-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-27 1.0 kn Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity A is
port (
Clk : in std_logic;
Clr : in std_logic;
A_A : in std_logic_vector(3 downto 0);
A_B : in std_logic_vector(3 downto 0);
A_AB : out std_logic_vector(4 downto 0)
);
end entity A;
-------------------------------------------------------------------------------
architecture str of A is
signal Cents_A : std_logic_vector(3 downto 0);
signal Cents_B : std_logic_vector(3 downto 0);
signal Cents_AB : std_logic_vector(4 downto 0);
signal B_A : std_logic_vector(3 downto 0);
signal B_B : std_logic_vector(3 downto 0);
signal B_AB : std_logic_vector(4 downto 0);
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal AB : unsigned(A_AB'range);
begin -- architecture str
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
A_AB <= std_logic_vector(AB);
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
p_addAandB: process (Clk) is
begin -- process p_addAandB
if Clk'event and Clk = '1' then -- rising clock edge
if Clr = '1' then
AB <= to_unsigned(0, AB'length);
else
AB <= resize(unsigned(A_A), AB'length) + resize(unsigned(A_B), AB'length);
end if;
end if;
end process p_addAandB;
i_B_1: entity work.B
port map (
Clk => Clk,
Clr => Clr,
B_A => B_A,
B_B => B_B,
B_AB => B_AB);
i_Cents_1: entity work.Cents
port map (
Clk => Clk,
Clr => Clr,
Cents_A => Cents_A,
Cents_B => Cents_B,
Cents_AB => Cents_AB);
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
8l/luz-cpu
|
experimental/luz_uc/luz_uc_testbench/cpu/controller/controller_tb.vhd
|
2
|
6387
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
use work.utils_pak.all;
entity controller_tb is end;
architecture controller_tb_arc of controller_tb is
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal mem_read: std_logic;
signal mem_write: std_logic;
signal mem_bytesel: std_logic_vector(3 downto 0);
signal mem_addr: word;
signal mem_data_out: word;
signal mem_ack: std_logic;
signal mem_data_in: word;
signal reg_sel_a: std_logic_vector(4 downto 0);
signal reg_a_out: word;
signal reg_sel_b: std_logic_vector(4 downto 0);
signal reg_b_out: word;
signal reg_sel_c: std_logic_vector(4 downto 0);
signal reg_c_out: word;
signal reg_sel_y: std_logic_vector(4 downto 0);
signal reg_write_y: std_logic;
signal reg_y_in: word;
signal reg_sel_z: std_logic_vector(4 downto 0);
signal reg_write_z: std_logic;
signal reg_z_in: word;
signal alu_op: cpu_opcode;
signal alu_rs_in: word;
signal alu_rt_in: word;
signal alu_rd_in: word;
signal alu_imm_in: word;
signal alu_output_a: word;
signal alu_output_b: word;
signal pc_in: word;
signal pc_write: std_logic;
signal pc_out: word;
signal dummy: std_logic;
begin
clk <= not clk after 14 ns;
reset_n <= '0', '1' after 100 ns;
-- Providing the controller with data from the memory.
-- Simulating a synchronous memory read access
--
proc_mem_data_in: process(clk, reset_n)
begin
if (reset_n = '0') then
mem_data_in <= (others => '0');
elsif (rising_edge(clk)) then
if mem_read = '1' then
-- The reset address, provide first instruction
if mem_addr = x"00100000" then
--
-- sub $r5, $r6, $r9
--
-- generated by luz_asm_sim test_assembler.py
--
mem_data_in <= x"04a64800";
elsif mem_addr = x"00100004" then
--
-- mulu $r20, $r2, $r3
--
mem_data_in <= x"0A821800";
end if;
end if;
end if;
end process;
-- Simulate the way the acknowledge signal from memory behaves
--
mem_ack <= '1' when mem_read = '1' or mem_write = '1' else '0';
-- Simulate reading from register A (Rd)
--
proc_reg_a_out: process(clk, reset_n)
begin
if (reset_n = '0') then
reg_a_out <= (others => '0');
elsif (rising_edge(clk)) then
if to_integer(unsigned(reg_sel_a)) = 6 then
reg_a_out <= x"0034AABB";
else
reg_a_out <= (others => '0');
end if;
end if;
end process;
-- Simulate reading from register B (Rs)
--
proc_reg_b_out: process(clk, reset_n)
begin
if (reset_n = '0') then
reg_b_out <= (others => '0');
elsif (rising_edge(clk)) then
if to_integer(unsigned(reg_sel_b)) = 6 then
reg_b_out <= x"0034AABB";
elsif to_integer(unsigned(reg_sel_b)) = 2 then
reg_b_out <= x"00400000";
else
reg_b_out <= (others => '0');
end if;
end if;
end process;
-- Simulate reading from register C (Rt)
--
proc_reg_c_out: process(clk, reset_n)
begin
if (reset_n = '0') then
reg_c_out <= (others => '0');
elsif (rising_edge(clk)) then
if to_integer(unsigned(reg_sel_c)) = 9 then
reg_c_out <= x"00126789";
elsif to_integer(unsigned(reg_sel_c)) = 3 then
reg_c_out <= x"00AB0000";
else
reg_c_out <= (others => '0');
end if;
end if;
end process;
process
begin
wait;
end process;
dut: entity work.controller(controller_arc)
port map
(
clk => clk,
reset_n => reset_n,
mem_read => mem_read,
mem_write => mem_write,
mem_bytesel => mem_bytesel,
mem_addr => mem_addr,
mem_data_out => mem_data_out,
mem_ack => mem_ack,
mem_data_in => mem_data_in,
reg_sel_a => reg_sel_a,
reg_a_out => reg_a_out,
reg_sel_b => reg_sel_b,
reg_b_out => reg_b_out,
reg_sel_c => reg_sel_c,
reg_c_out => reg_c_out,
reg_sel_y => reg_sel_y,
reg_write_y => reg_write_y,
reg_y_in => reg_y_in,
reg_sel_z => reg_sel_z,
reg_write_z => reg_write_z,
reg_z_in => reg_z_in,
alu_op => alu_op,
alu_rs_in => alu_rs_in,
alu_rt_in => alu_rt_in,
alu_rd_in => alu_rd_in,
alu_imm_in => alu_imm_in,
alu_output_a => alu_output_a,
alu_output_b => alu_output_b,
pc_in => pc_in,
pc_write => pc_write,
pc_out => pc_out,
dummy => dummy
);
pc_map: entity work.program_counter(program_counter_arc)
generic map
(
INIT => x"00100000"
)
port map
(
clk => clk,
reset_n => reset_n,
pc_in => pc_in,
pc_out => pc_out,
pc_write => pc_write
);
alu_map: entity work.alu(alu_arc)
port map
(
clk => clk,
reset_n => reset_n,
op => alu_op,
rd_in => alu_rd_in,
rt_in => alu_rt_in,
rs_in => alu_rs_in,
imm_in => alu_imm_in,
output_a => alu_output_a,
output_b => alu_output_b
);
end;
|
unlicense
|
8l/luz-cpu
|
experimental/luz_uc/luz_uc_rtl/cpu/controller.vhd
|
2
|
12296
|
-- CPU controller.
-- Main controller code of the CPU - fetching, decoding and
-- executing instructions.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
use work.utils_pak.all;
-- The main CPU controller module.
--
entity controller is
port
(
clk: in std_logic;
reset_n: in std_logic;
-- memory interface
--
mem_read: out std_logic;
mem_write: out std_logic;
mem_bytesel: out std_logic_vector(3 downto 0);
mem_addr: out word;
mem_data_out: out word;
mem_ack: in std_logic;
mem_data_in: in word;
-- interface to the register file
--
reg_sel_a: out std_logic_vector(4 downto 0);
reg_a_out: in word;
reg_sel_b: out std_logic_vector(4 downto 0);
reg_b_out: in word;
reg_sel_c: out std_logic_vector(4 downto 0);
reg_c_out: in word;
reg_sel_y: out std_logic_vector(4 downto 0);
reg_write_y: out std_logic;
reg_y_in: out word;
reg_sel_z: out std_logic_vector(4 downto 0);
reg_write_z: out std_logic;
reg_z_in: out word;
-- interface to the ALU
--
alu_op: out cpu_opcode;
alu_rs_in: out word;
alu_rt_in: out word;
alu_rd_in: out word;
alu_imm_in: out word;
alu_output_a: in word;
alu_output_b: in word;
-- interface to the program counter
--
pc_in: out word;
pc_write: out std_logic;
pc_out: in word;
dummy: out std_logic
);
end controller;
architecture controller_arc of controller is
signal PC_ff, NPC_ff: word;
signal IR_ff: word;
signal Rs_ff, Rt_ff, Rd_ff: word;
signal Imm_unsigned_ff: word;
signal Imm_signed_ff: word;
signal ALU_out_a_ff: word;
signal ALU_out_b_ff: word;
signal LMD_ff: word;
signal OP_ff: cpu_opcode;
signal load_addr_ff: word;
signal store_addr_ff: word;
signal branch_addr_ff: word;
signal reg_rs_sel: std_logic_vector(4 downto 0);
signal reg_rt_sel: std_logic_vector(4 downto 0);
signal reg_rd_sel: std_logic_vector(4 downto 0);
-- CPU execution cycles:
--
-- out_of_reset:
--
type cycle_type is
(
halted,
out_of_reset,
fetch,
decode,
execution,
memory_access,
write_back
);
signal cycle: cycle_type;
signal instr_fetch: boolean;
signal instr_is_load: boolean;
signal instr_is_store: boolean;
signal instr_is_branch: boolean;
signal instr_writes_back: boolean;
signal instr_result_dword: boolean;
signal branch_is_taken: boolean;
begin
-- The main state machine process
--
proc_cycle: process(clk, reset_n)
begin
if (reset_n = '0') then
cycle <= out_of_reset;
elsif (rising_edge(clk)) then
case (cycle) is
when out_of_reset =>
cycle <= fetch;
-- When data is ready in mem_data_in, move to
-- the decoding cycle.
--
when fetch =>
if mem_ack = '1' then
cycle <= decode;
end if;
-- During the decoding cycle the instruction is
-- taken from IR and is decoded into its
-- constituents.
--
when decode =>
cycle <= execution;
-- During the execution cycle, the ALU does its
-- work on the arguments taken from registers.
--
when execution =>
cycle <= memory_access;
-- The memory access is for memory loads/stores.
--
when memory_access =>
if ( not (instr_is_store or instr_is_load) or
mem_ack = '1') then
cycle <= write_back;
end if;
when write_back =>
cycle <= fetch;
when halted =>
cycle <= halted;
when others =>
end case;
end if;
end process;
-- Updating the value of the program counter when in memory
-- access cycle. The value is either changed to a branch
-- address for branch instructions, or just advanced by 4 for
-- other instructions. ZZZ: what about JR?!
--
pc_write <= '1' when cycle = memory_access else '0';
pc_in <= branch_addr_ff when instr_is_branch and branch_is_taken else
std_logic_vector(unsigned(PC_ff) + 4);
-- Next PC
--
NPC_ff <= pc_out;
-- Stores the program counter for later usage
--
proc_PC_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
PC_ff <= NPC_ff;
elsif (rising_edge(clk)) then
if cycle = fetch then
PC_ff <= NPC_ff;
end if;
end if;
end process;
-- Instruction fetch
--
instr_fetch <= cycle = fetch;
-- Helper signals for identifying instruction types
--
with OP_ff select
instr_is_load <= true when OP_LB | OP_LBU | OP_LH | OP_LHU | OP_LW,
false when others;
with OP_ff select
instr_is_store <= true when OP_SB | OP_SH | OP_SW,
false when others;
with OP_ff select
instr_is_branch <= true when OP_BEQ | OP_BNE | OP_BGE |
OP_BGT | OP_BLE | OP_BLT |
OP_BGEU | OP_BGTU |
OP_BLEU | OP_BLTU,
false when others;
-- instr_writes_back: an instruction that stores a result in
-- a register
--
with OP_ff select
instr_writes_back <= true when OP_ADD | OP_ADDI | OP_SUB |
OP_SUBI | OP_MULU | OP_MUL |
OP_DIVU | OP_DIV | OP_LUI |
OP_SLL | OP_SLLI | OP_SRL |
OP_SRLI | OP_AND | OP_ANDI |
OP_OR | OP_ORI | OP_NOR |
OP_XOR | OP_LB | OP_LBU |
OP_LH | OP_LHU | OP_LW |
OP_CALL,
false when others;
-- instr_result_dword: an instruction that produces a 64-bit
-- result
--
with OP_ff select
instr_result_dword <= true when OP_MUL | OP_MULU |
OP_DIV | OP_DIVU,
false when others;
branch_is_taken <= instr_is_branch and ALU_out_a_ff(0) = '1';
-- Read from memory when:
-- * fetching an instruction
-- * executing a load instruction
--
mem_read <= '1' when instr_fetch or
(cycle = memory_access and instr_is_load)
else '0';
-- Write to memory when executing a store instruction
--
mem_write <= '1' when cycle = memory_access and instr_is_store else '0';
-- Byte select lines depend on the width of the load/store
-- access. For instructions, words are fetched.
--
mem_bytesel <= "1111" when instr_fetch else
"0001" when OP_ff = OP_SB or OP_ff = OP_LB or OP_ff = OP_LBU else
"0011" when OP_ff = OP_SH or OP_ff = OP_LH or OP_ff = OP_LHU else
"1111" when OP_ff = OP_LW or OP_ff = OP_SW else
"0000";
-- Memory address
--
mem_addr <= NPC_ff when instr_fetch else
load_addr_ff when cycle = memory_access and instr_is_load else
store_addr_ff when cycle = memory_access and instr_is_store
else (others => '0');
-- Memory data in is taken from Rs in store instructions
--
mem_data_out <= Rs_ff;
-- The instruction register holds the current instruction
-- read from the memory.
-- Since the memory outputs are synchronous, IR_ff is just an
-- alias. It will be read only on rising_edge(clk), so it
-- really represents a register.
--
IR_ff <= mem_data_in;
-- The opcode
--
proc_OP_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
OP_ff <= (others => '0');
elsif (rising_edge(clk)) then
OP_ff <= IR_ff(31 downto 26);
end if;
end process;
reg_rd_sel <= IR_ff(25 downto 21);
reg_rs_sel <= IR_ff(20 downto 16);
reg_rt_sel <= IR_ff(15 downto 11);
reg_sel_a <= reg_rd_sel;
reg_sel_b <= reg_rs_sel;
reg_sel_c <= reg_rt_sel;
-- The unsigned (zero-extended) and signed (sign-extended)
-- interpretations of the immediate value.
-- Both are delayed by a clock cycle to be ready in the same
-- cycle with the values of registers.
--
proc_Imm_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
Imm_unsigned_ff <= (others => '0');
Imm_signed_ff <= (others => '0');
elsif (rising_edge(clk)) then
Imm_unsigned_ff <= std_logic_vector(resize(unsigned(IR_ff(15 downto 0)), 32));
Imm_signed_ff <= std_logic_vector(resize(signed(IR_ff(15 downto 0)), 32));
end if;
end process;
-- Contents of registers.
--
Rd_ff <= reg_a_out;
Rs_ff <= reg_b_out;
Rt_ff <= reg_c_out;
-- ALU arguments and outputs
--
alu_op <= OP_ff;
alu_rs_in <= Rs_ff;
alu_rt_in <= Rt_ff;
alu_rd_in <= Rd_ff;
alu_imm_in <= Imm_unsigned_ff;
ALU_out_a_ff <= alu_output_a;
ALU_out_b_ff <= alu_output_b;
-- load and store addresses, computed during the execution
-- cycle.
--
proc_load_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
load_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
load_addr_ff <= std_logic_vector(signed(Rs_ff) + signed(Imm_signed_ff));
end if;
end process;
proc_store_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
store_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
store_addr_ff <= std_logic_vector(signed(Rd_ff) + signed(Imm_signed_ff));
end if;
end process;
-- Loaded memory data
--
LMD_ff <= mem_data_in;
-- branch address, computed during the execution cycle.
--
proc_branch_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
branch_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
if cycle = execution then
branch_addr_ff <= std_logic_vector(signed(PC_ff) + shift_left(signed(Imm_signed_ff), 2));
end if;
end if;
end process;
-- writing to registers
--
reg_y_in <= ALU_out_a_ff;
reg_z_in <= ALU_out_b_ff;
-- Port y is Rd
-- Port z is R(d+1) unless d is 31
--
reg_sel_y <= reg_rd_sel;
reg_sel_z <= (others => '0') when unsigned(reg_rd_sel) = 31 else
std_logic_vector(unsigned(reg_rd_sel) + 1);
reg_write_y <= '1' when (cycle = write_back and
instr_writes_back and
unsigned(reg_rd_sel) /= 0)
else '0';
reg_write_z <= '1' when (cycle = write_back and
instr_result_dword and
unsigned(reg_rd_sel) /= 31)
else '0';
end;
|
unlicense
|
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/ram_dq_PHASE_n.vhd
|
2
|
7072
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_n.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_PHASE_n IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_PHASE_n;
ARCHITECTURE SYN OF ram_dq_phase_n IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_n",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "PH_n"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_n"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_n_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
unlicense
|
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/lpm_rom0.vhd
|
2
|
6146
|
-- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "UDP.mif",
intended_device_family => "Arria GX",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "UDP.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "UDP.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
unlicense
|
TWW12/lzw
|
ip_repo/axi_compression_1.0/src/output_fifo/synth/output_fifo.vhd
|
2
|
38780
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY output_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END output_fifo;
ARCHITECTURE output_fifo_arch OF output_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF output_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF output_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF output_fifo_arch : ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF output_fifo_arch: ARCHITECTURE IS "output_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=12,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=12,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMIN" &
"IT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=2,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH" &
"_NEGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=1,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE" &
"_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=" &
"1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_R" &
"DCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERRO" &
"R_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_" &
"WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023," &
"C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_" &
"VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 12,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 12,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 2,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 1,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END output_fifo_arch;
|
unlicense
|
TWW12/lzw
|
final_project_sim/lzw/lzw.cache/ip/1ef49ae738cde1e4/bram_2048_0_stub.vhdl
|
1
|
1613
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:16 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_2048_0_stub.vhdl
-- Design : bram_2048_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
unlicense
|
Lyrositor/insa
|
3if/ac/tp-ac_1/register_n.vhdl
|
1
|
785
|
-- register_1
-- An N-bit register.
library ieee;
use ieee.std_logic_1164.all;
library work;
entity register_n is
generic(n: integer);
port(
clk, enable, reset: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0)
);
end entity;
architecture rtl of register_n is
component register_1 is
port(
enable, clk, d, reset: in std_logic;
q: out std_logic
);
end component;
begin
addloop:
for i in 0 to n-1 generate
begin
register_1_instance: register_1 port map(
clk => clk,
d => d(i),
reset => reset,
enable => enable,
q => q(i)
);
end generate;
end architecture;
|
unlicense
|
Lyrositor/insa
|
3if/ac/tp-ac_2/testbench_passage_a_niveau.vhdl
|
1
|
2019
|
library ieee;
use ieee.std_logic_1164.all;
library work;
entity testbench_passage_a_niveau is
end entity;
architecture behaviorial of testbench_passage_a_niveau is
component passage_a_niveau is
port(
clock: in std_logic;
reset: in std_logic;
capteur_droite: in std_logic;
capteur_gauche: in std_logic;
ampoule: out std_logic;
alert: out std_logic
);
end component;
signal clock, reset, capteur_droite, capteur_gauche, ampoule, alert: std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
uut: passage_a_niveau port map(
clock => clock,
reset => reset,
capteur_droite => capteur_droite,
capteur_gauche => capteur_gauche,
ampoule => ampoule,
alert => alert
);
-- a clock process
clock_process: process
begin
clock <= '1';
wait for 0.5 ns;
clock <= '0';
wait for 0.5 ns;
end process;
-- A test process
test_process: process
begin
reset <= '1';
wait for 2.3 ns;
reset <= '0';
capteur_gauche <= '0';
capteur_droite <= '0';
wait for 12.3 ns;
-- un train court vient de droite
capteur_droite <= '1';
wait for 10 ns;
capteur_droite <= '0';
wait for 5 ns;
capteur_gauche <= '1';
wait for 10 ns;
capteur_gauche <= '0';
wait for 20 ns;
-- un train long vient de droite
capteur_droite <= '1';
wait for 20 ns;
capteur_gauche <= '1';
wait for 10 ns;
capteur_droite <= '0';
wait for 20 ns;
capteur_gauche <= '0';
wait for 20 ns;
-- deux trains rentrent en collision
capteur_droite <= '1';
capteur_gauche <= '1';
wait for 10 ns;
capteur_droite <= '0';
capteur_gauche <= '0';
wait for 20 ns;
end process;
end behaviorial;
|
unlicense
|
frznchckn/polarbear
|
hw/cores/uart/hdl/vhdl/uart_bhv.vhd
|
1
|
8562
|
--------------------------------------------------------------------------------
--|
--| Filename : uart_bhv
--| Author : Russell L Friesenhahn
--| Origin Date : 20130828
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--| Behavorial architecture of UART core
--|
--------------------------------------------------------------------------------
--|
--| Modification History
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| References
--|
--|
--|
--------------------------------------------------------------------------------
architecture bhv of uart is
-----------------------------
-- Component Declarations
-----------------------------
component cntr is
generic (
CntrWidth : integer := 8
);
port (
Clk : in std_ulogic;
Rst : in std_ulogic;
En : in std_ulogic;
Clr : in std_ulogic;
CritValue : in std_ulogic_vector(CntrWidth-1 downto 0);
CntrValue : out std_ulogic_vector(CntrWidth-1 downto 0);
CntReached : out std_ulogic
);
end component;
-----------------------------
-- Constant Declarations
-----------------------------
-- constant clk16Gen : integer := SysClkRate / BaudRate / 16;
-----------------------------
-- Type Declarations
-----------------------------
type rxst is (
IDLE,
START,
RX,
PARITYCK,
STOP,
ERR
);
type txst is (
IDLE,
START,
TX,
TXPARITY,
STOP
);
-----------------------------
-- Signal Declarations
-----------------------------
signal clkCntr : unsigned(19 downto 0);
signal clkTxCntr : unsigned(23 downto 0);
-- signal clkTxGen : unsigned(23 downto 0);
signal clkTxGen : std_ulogic_vector(23 downto 0);
signal ClkTxPulse : std_ulogic;
signal startTxCntr : std_ulogic;
signal clk16Pulse : std_ulogic;
signal rxcs : rxst;
signal din_d0 : std_ulogic;
signal din_d1 : std_ulogic;
signal din_d2 : std_ulogic;
signal clk16Cnt : unsigned(3 downto 0);
-- signal dout_int : std_ulogic_vector(7 downto 0);
signal rxCnt : unsigned(3 downto 0);
signal dout_i : std_ulogic_vector(7 downto 0);
signal parity : std_ulogic;
signal txcs : txst;
signal bitTxParity : std_ulogic;
signal txCnt : unsigned(2 downto 0);
signal byteRx_d1 : std_ulogic_vector(7 downto 0);
signal byteRx_d2 : std_ulogic_vector(7 downto 0);
signal byteRxValid_d1 : std_ulogic;
signal txBusy_i : std_ulogic;
begin
ByteTx <= dout_i;
TxBusy <= txBusy_i;
clkTxGen <= BaudRateGen & X"0";
cntr_tx : cntr
generic map (
CntrWidth => 24
)
port map (
Clk => Clk,
Rst => Rst,
En => '1',
Clr => startTxCntr,
CritValue => clkTxGen,
CntrValue => open,
CntReached => ClkTxPulse
);
P_TX : process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
BitTx <= '1';
txBusy_i <= '1';
clkTxCntr <= (others => '0');
byteRxValid_d1 <= '0';
startTxCntr <= '0';
else
if ByteRxValid = '1' and txBusy_i = '0' then
byteRx_d1 <= ByteRx;
byteRxValid_d1 <= ByteRxValid;
txBusy_i <= '1';
end if;
C_TX : case txcs is
when IDLE =>
txBusy_i <= '0';
BitTx <= '1';
bitTxParity <= ParityType;
txCnt <= (others => '0');
if byteRxValid_d1 = '1' then
byteRx_d2 <= byteRx_d1;
startTxCntr <= '1';
txBusy_i <= '1';
txcs <= START;
byteRxValid_d1 <= '0';
end if;
when START =>
startTxCntr <= '0';
BitTx <= '0';
if ClkTxPulse = '1' then
txcs <= TX;
BitTx <= byteRx_d1(0);
bitTxParity <= bitTxParity xor byteRx_d1(0);
txCnt <= txCnt + 1;
end if;
when TX =>
if ClkTxPulse = '1' then
if txCnt = to_unsigned(0, txCnt'length) then
BitTx <= bitTxParity;
txcs <= TXPARITY;
else
BitTx <= byteRx_d1(to_integer(txCnt));
bitTxParity <= bitTxParity xor byteRx_d1(to_integer(txCnt));
txCnt <= txCnt + 1;
end if;
end if;
when TXPARITY =>
if ClkTxPulse = '1' then
BitTx <= '1';
txcs <= STOP;
end if;
when STOP =>
txBusy_i <= '0';
if ClkTxPulse = '1' then
BitTx <= '1';
txcs <= IDLE;
end if;
when others => null;
end case C_TX;
end if;
end if;
end process P_TX;
CLK16_PULSE_GEN : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
clkCntr <= (others => '0');
clk16Pulse <= '0';
else
-- if clkCntr = to_unsigned(clk16Gen, clkCntr'length)
if clkCntr = unsigned(BaudRateGen)
then
clkCntr <= (others => '0');
clk16Pulse <= '1';
else
clkCntr <= clkCntr + 1;
clk16Pulse <= '0';
end if;
end if;
end if;
end process CLK16_PULSE_GEN;
P_STABLE_DATA : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
din_d0 <= '0';
din_d1 <= '0';
din_d2 <= '0';
else
din_d2 <= din_d1;
din_d1 <= din_d0;
din_d0 <= BitRx;
end if;
end if;
end process P_STABLE_DATA;
P_CLK16_CNTR : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
clk16Cnt <= (others => '0');
else
if clk16Pulse = '1'
then
clk16Cnt <= clk16Cnt + 1;
end if;
if din_d1 /= din_d2
then
clk16Cnt <= (others => '0');
end if;
end if;
end if;
end process P_CLK16_CNTR;
P_RX : process (Clk)
begin
if Clk'event and Clk = '1'
then
if Rst = '1'
then
rxcs <= IDLE;
dout_i <= (others => '0');
ParErr <= '0';
StopErr <= '0';
else
CO_RX_SM : case rxcs is
when IDLE =>
ByteTxValid <= '0';
rxCnt <= (others => '0');
parity <= ParityType;
if din_d1 = '0'
and din_d2 = '1'
then
rxcs <= START;
end if;
when START =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if din_d2 = '0'
then
rxcs <= RX;
else
rxcs <= IDLE;
end if;
end if;
when RX =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
rxCnt <= rxCnt + 1;
end if;
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
dout_i <= din_d2 & dout_i(7 downto 1);
parity <= parity xor din_d2;
end if;
if rxCnt = to_unsigned(8, 4)
then
if UseParity = '1'
then
rxcs <= PARITYCK;
else
rxcs <= STOP;
end if;
end if;
when PARITYCK =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if parity /= din_d2
then
ParErr <= '1';
rxcs <= ERR;
assert false
report "ERROR: parity incorrect"
severity error;
else
rxcs <= STOP;
end if;
end if;
when STOP =>
if clk16Pulse = '1'
and clk16Cnt = to_unsigned(7, 4)
then
if din_d2 = '1'
then
ByteTxValid <= '1';
rxcs <= IDLE;
else
StopErr <= '1';
rxcs <= ERR;
end if;
end if;
when ERR =>
ParErr <= '0';
StopErr <= '0';
rxcs <= IDLE;
end case;
end if;
end if;
end process P_RX;
end architecture bhv;
|
unlicense
|
jza00425/SingleCycleARM
|
lab2/work/register/_primary.vhd
|
3
|
425
|
library verilog;
use verilog.vl_types.all;
entity \register\ is
generic(
width : integer := 32;
reset_value : integer := 0
);
port(
q : out vl_logic_vector;
d : in vl_logic_vector;
clk : in vl_logic;
enable : in vl_logic;
rst_b : in vl_logic
);
end \register\;
|
unlicense
|
mike7c2/befunge_processor
|
befunge_alu.vhd
|
1
|
4106
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity befunge_alu is
generic(
word_size : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
a : in std_logic_vector(word_size-1 downto 0);
b : in std_logic_vector(word_size-1 downto 0);
result : out std_logic_vector(word_size-1 downto 0);
op : in std_logic_vector(2 downto 0);
en : in std_logic;
working : out std_logic
);
end befunge_alu;
architecture alu_v1 of befunge_alu is
constant zero : std_logic_vector(word_size - 1 downto 0) := (others => '0');
signal en_shadow : std_logic;
signal div_rfd : std_logic;
signal div_quotient : std_logic_vector(word_size-1 downto 0);
signal div_remainder : std_logic_vector(word_size-1 downto 0);
component div_gen_v3_0 is
port (
rfd : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
dividend : in STD_LOGIC_VECTOR ( 7 downto 0 );
quotient : out STD_LOGIC_VECTOR ( 7 downto 0 );
divisor : in STD_LOGIC_VECTOR ( 7 downto 0 );
fractional : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component;
begin
divider : div_gen_v3_0
port map
(
div_rfd,
clk,
b,
div_quotient,
a,
div_remainder
);
process(reset,clk)
variable result_int : std_logic_vector((word_size * 2) -1 downto 0);
variable div_wait : integer range 0 to 12;
variable div_or_mod : std_logic;
begin
if(reset = '1') then
result <= (others => '0');
en_shadow <= '0';
working <= '0';--This flag should be used to stall the cpu for multi cycle instructions (mod and div)
div_wait := 0;
div_or_mod := '0';
else
if rising_edge(clk) then
en_shadow <= en;
if ( en = '1' and en_shadow = '0' ) then
working <= '1';
if ( op = "000" ) then -- + add
result <= std_logic_vector(Unsigned(a) + Unsigned(b));
elsif ( op = "001" ) then -- - subract
result <= std_logic_vector(Unsigned(a) - Unsigned(b));
elsif ( op = "010" ) then -- * multiply
result_int := std_logic_vector(Unsigned(a) * Unsigned(b));
result <= result_int(word_size-1 downto 0);
elsif ( op = "011" ) then -- / divide (hard!)
div_wait := 12;
div_or_mod := '0';
-- result <= std_logic_vector(Unsigned(a) / Unsigned(b));
elsif ( op = "100" ) then -- % modulue (hard!)
div_wait := 12;
div_or_mod := '1';
--result <= std_logic_vector(Unsigned(a) % Unsigned(b));
elsif ( op = "101" ) then -- ! not
if (a /= zero) then
result <= (others => '0');
else
result <= "00000001";
end if;
elsif ( op = "110" ) then -- ' greater than
result <= (others => '0');
end if;
elsif (div_wait = 1) then
if (div_or_mod = '0') then
result <= div_quotient;
else
result <= div_remainder;
end if;
div_wait := div_wait - 1;
elsif (div_wait > 0) then
div_wait := div_wait -1;
elsif (div_wait = 0) then
working <= '0';
end if;
end if;
end if;
end process;
end alu_v1;
|
unlicense
|
sahandKashani/TRDB_D5M
|
DE1-SoC/hw/hdl/cmos_sensor_input/hdl/cmos_sensor_input_avalon_st_source.vhd
|
5
|
3540
|
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- Avalon-ST Source
ready : in std_logic;
valid : out std_logic;
data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- fifo
fifo_read : out std_logic;
fifo_empty : in std_logic;
fifo_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
fifo_end_of_frame : in std_logic;
fifo_overflow : in std_logic;
-- sampler
end_of_frame_out : out std_logic;
end_of_frame_out_ack : in std_logic
);
end entity cmos_sensor_input_avalon_st_source;
architecture rtl of cmos_sensor_input_avalon_st_source is
type state_type is (STATE_IDLE, STATE_READY_CYCLE, STATE_WAIT_END_OF_FRAME_ACK);
signal reg_state, next_reg_state : state_type;
signal data_little_endian : std_logic_vector(data'range);
signal data_big_endian : std_logic_vector(data'range);
begin
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
else
reg_state <= next_reg_state;
end if;
end if;
end process;
NEXT_STATE_LOGIC : process(data_big_endian, end_of_frame_out_ack, fifo_empty, fifo_end_of_frame, fifo_overflow, ready, reg_state)
begin
fifo_read <= '0';
valid <= '0';
data <= (others => '0');
end_of_frame_out <= '0';
next_reg_state <= reg_state;
case reg_state is
when STATE_IDLE =>
if ready = '1' then
next_reg_state <= STATE_READY_CYCLE;
end if;
when STATE_READY_CYCLE =>
if ready = '0' then
next_reg_state <= STATE_IDLE;
end if;
if fifo_empty = '0' and fifo_overflow = '0' then
fifo_read <= '1';
valid <= '1';
data <= data_big_endian;
if fifo_end_of_frame = '1' then
next_reg_state <= STATE_WAIT_END_OF_FRAME_ACK;
end if;
end if;
when STATE_WAIT_END_OF_FRAME_ACK =>
end_of_frame_out <= '1';
if end_of_frame_out_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
data_little_endian <= fifo_data;
NETWORK_ORDER : process(data_little_endian)
begin
-- data is an Avalon-ST interface, so it needs to arrange data in
-- network order (a.k.a big-endian).
-- This component is specified to support 8 bits per symbol for its
-- Avalon-ST interface, so data is flipped on 8-bit boundaries.
for i in 0 to (DATA_WIDTH / 8) - 1 loop
data_big_endian(8 * (i + 1) - 1 downto 8 * i) <= data_little_endian(data_little_endian'length - 8 * i - 1 downto data_little_endian'length - 8 * (i + 1));
end loop;
end process;
end architecture rtl;
|
unlicense
|
sahandKashani/TRDB_D5M
|
DE0-Nano/hw/hdl/cmos_sensor_input/hdl/cmos_sensor_input_sampler.vhd
|
5
|
13162
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sampler is
generic(
PIX_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
idle : out std_logic;
wait_irq_ack : out std_logic;
irq_en : in std_logic;
irq_ack : in std_logic;
snapshot : in std_logic;
get_frame_info : in std_logic;
frame_width : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
frame_height : out std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
-- synchronizer
frame_valid : in std_logic;
line_valid : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- debayer / packer / fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_out : out std_logic;
end_of_frame_out : out std_logic;
-- fifo
fifo_overflow : in std_logic;
-- st_source
end_of_frame_in : in std_logic;
end_of_frame_in_ack : out std_logic
);
end entity cmos_sensor_input_sampler;
architecture rtl of cmos_sensor_input_sampler is
-- GFI = get_frame_info
-- SNPSHT = snapshot
type state_type is (STATE_IDLE,
STATE_WAIT_END_FRAME_GFI, STATE_WAIT_START_FRAME_GFI, STATE_DATA_SKIP, STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI,
STATE_WAIT_END_FRAME_SNPSHT, STATE_WAIT_START_FRAME_SNPSHT, STATE_START_OF_FRAME_OUT, STATE_DATA_VALID, STATE_LINE_LINE_BLANK_SNPSHT, STATE_END_OF_FRAME_OUT, STATE_WAIT_END_OF_FRAME_IN, STATE_END_OF_FRAME_IN_ACK,
STATE_WAIT_IRQ_ACK);
signal reg_state, next_reg_state : state_type;
signal reg_frame_width_config, next_reg_frame_width_config : unsigned(frame_width'range);
signal reg_frame_height_config, next_reg_frame_height_config : unsigned(frame_height'range);
signal reg_frame_width_counter, next_reg_frame_width_counter : unsigned(frame_width'range);
signal reg_frame_height_counter, next_reg_frame_height_counter : unsigned(frame_height'range);
signal reg_data_in, next_reg_data_in : std_logic_vector(data_in'range);
begin
process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_config <= (others => '0');
reg_frame_height_config <= (others => '0');
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_data_in <= (others => '0');
else
reg_state <= next_reg_state;
reg_frame_width_config <= next_reg_frame_width_config;
reg_frame_height_config <= next_reg_frame_height_config;
reg_frame_width_counter <= next_reg_frame_width_counter;
reg_frame_height_counter <= next_reg_frame_height_counter;
reg_data_in <= next_reg_data_in;
end if;
end if;
end process;
process(data_in, end_of_frame_in, fifo_overflow, frame_valid, get_frame_info, irq_ack, irq_en, line_valid, reg_data_in, reg_frame_height_config, reg_frame_height_counter, reg_frame_width_config, reg_frame_width_counter, reg_state, snapshot)
begin
idle <= '0';
wait_irq_ack <= '0';
frame_width <= std_logic_vector(reg_frame_width_config);
frame_height <= std_logic_vector(reg_frame_height_config);
valid_out <= '0';
data_out <= (others => '0');
start_of_frame_out <= '0';
end_of_frame_out <= '0';
end_of_frame_in_ack <= '0';
next_reg_state <= reg_state;
next_reg_frame_width_config <= reg_frame_width_config;
next_reg_frame_height_config <= reg_frame_height_config;
next_reg_frame_width_counter <= reg_frame_width_counter;
next_reg_frame_height_counter <= reg_frame_height_counter;
next_reg_data_in <= data_in;
case reg_state is
when STATE_IDLE =>
idle <= '1';
if get_frame_info = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_GFI;
end if;
elsif snapshot = '1' then
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
elsif frame_valid = '1' then
next_reg_state <= STATE_WAIT_END_FRAME_SNPSHT;
end if;
end if;
when STATE_WAIT_END_FRAME_GFI =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_GFI;
end if;
when STATE_WAIT_START_FRAME_GFI =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= to_unsigned(1, next_reg_frame_height_config'length);
end if;
when STATE_DATA_SKIP =>
if frame_valid = '0' then
if line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
end if;
elsif frame_valid = '1' then
if line_valid = '0' then
next_reg_state <= STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI;
elsif line_valid = '1' then
next_reg_frame_width_config <= reg_frame_width_config + 1;
end if;
end if;
when STATE_LINE_LINE_BLANK_OR_LINE_FRAME_BLANK_GFI =>
if frame_valid = '0' and line_valid = '0' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_SKIP;
next_reg_frame_width_config <= to_unsigned(1, next_reg_frame_width_config'length);
next_reg_frame_height_config <= reg_frame_height_config + 1;
end if;
when STATE_WAIT_END_FRAME_SNPSHT =>
if frame_valid = '0' then
next_reg_state <= STATE_WAIT_START_FRAME_SNPSHT;
end if;
when STATE_WAIT_START_FRAME_SNPSHT =>
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_START_OF_FRAME_OUT;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
when STATE_START_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
start_of_frame_out <= '1';
if reg_frame_width_counter < reg_frame_width_config - 1 then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
elsif reg_frame_width_counter = reg_frame_width_config - 1 then
if reg_frame_height_counter = reg_frame_height_config then
next_reg_state <= STATE_END_OF_FRAME_OUT;
end if;
end if;
end if;
when STATE_DATA_VALID =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
if reg_frame_height_counter < reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config then
next_reg_state <= STATE_LINE_LINE_BLANK_SNPSHT;
end if;
elsif reg_frame_height_counter = reg_frame_height_config then
if reg_frame_width_counter = reg_frame_width_config - 1 then
next_reg_state <= STATE_END_OF_FRAME_OUT;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
end if;
end if;
end if;
when STATE_LINE_LINE_BLANK_SNPSHT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if frame_valid = '1' and line_valid = '1' then
next_reg_state <= STATE_DATA_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= reg_frame_height_counter + 1;
end if;
end if;
when STATE_END_OF_FRAME_OUT =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
valid_out <= '1';
data_out <= reg_data_in;
end_of_frame_out <= '1';
next_reg_state <= STATE_WAIT_END_OF_FRAME_IN;
end if;
when STATE_WAIT_END_OF_FRAME_IN =>
if fifo_overflow = '1' then
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
elsif fifo_overflow = '0' then
if end_of_frame_in = '1' then
next_reg_state <= STATE_END_OF_FRAME_IN_ACK;
end if;
end if;
when STATE_END_OF_FRAME_IN_ACK =>
end_of_frame_in_ack <= '1';
if irq_en = '0' then
next_reg_state <= STATE_IDLE;
elsif irq_en = '1' then
next_reg_state <= STATE_WAIT_IRQ_ACK;
end if;
when STATE_WAIT_IRQ_ACK =>
wait_irq_ack <= '1';
if irq_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
end architecture rtl;
|
unlicense
|
sahandKashani/TRDB_D5M
|
DE0-Nano/hw/hdl/cmos_sensor_input/hdl/cmos_sensor_input_packer.vhd
|
5
|
3601
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- sampler / debayer
valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_in : in std_logic;
end_of_frame_in : in std_logic;
-- fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PACK_WIDTH - 1 downto 0);
end_of_frame_out : out std_logic
);
end entity cmos_sensor_input_packer;
architecture rtl of cmos_sensor_input_packer is
constant COMPRESSED_PIX_COUNT : positive := floor_div(data_out'length, PIX_DEPTH);
signal reg_count : unsigned(bit_width(COMPRESSED_PIX_COUNT) - 1 downto 0);
signal reg_data_out : std_logic_vector((COMPRESSED_PIX_COUNT - 1) * PIX_DEPTH - 1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
reg_count <= (others => '0');
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
valid_out <= '0';
data_out <= (others => '0');
end_of_frame_out <= '0';
if stop_and_reset = '1' then
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
else
if valid_in = '1' then
if start_of_frame_in = '1' then
reg_count <= to_unsigned(1, reg_count'length);
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= (others => '0');
elsif end_of_frame_in = '1' then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
end_of_frame_out <= '1';
reg_count <= to_unsigned(0, reg_count'length);
elsif reg_count < COMPRESSED_PIX_COUNT - 1 then
reg_count <= reg_count + 1;
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= reg_data_out(reg_data_out'length - PIX_DEPTH - 1 downto 0);
elsif reg_count = COMPRESSED_PIX_COUNT - 1 then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
unlicense
|
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