repo_name
stringlengths 6
79
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stringlengths 5
236
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stringclasses 54
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stringlengths 1
8
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stringlengths 0
1.04M
⌀ | license
stringclasses 15
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wsoltys/AtomFpga
|
src/DCM/dcm5.vhd
|
2
|
1838
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm5 is
port ( CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm5;
architecture BEHAVIORAL of dcm5 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF, O=>CLK0_OUT);
DCM_INST : DCM
-- DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 16.00 = 32 * 8 / 16
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 8,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AVR8/Memory/prog_mem_init.vhd
|
1
|
69846
|
-- VHDL initialization records.
--
-- Release 11.1i - Data2MEM L.33, build 1.5.8 Jul 23, 2008
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--
-- Command: C:\Users\ZBAND0~1\AppData\Local\Temp\build5746311222132730322.tmp\data2mem.exe -bm bitstreams/custom_bd.bmm -bd out.mem -o h E:\Papilio\Cores\GadgetFactory_Arduino_Timer_Counter\AVR8_SoftCore_TimerCounter_SPI\sources\Memory\prog_mem_init.vhd
--
-- Created on 11/24/12 01:13 pm, from:
--
-- Map file - bitstreams\custom_bd.bmm
-- Data file(s) - out.mem
--
-- Address space 'avrmap.rom_code' [0x00000000:0x00003FFF], 16384 bytes in size.
--
-- Bus width = 16 bits, bit lane width = 16 bits, number of bus blocks = 8.
library ieee;
use ieee.std_logic_1164;
package prog_mem_init_pkg is
-- BRAM 0 in address space [0x00000000:0x000007FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word0 LOC = RAMB16_X0Y4;
constant PM_Inst_RAM_Word0_INIT_00 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C0098940C";
constant PM_Inst_RAM_Word0_INIT_01 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C";
constant PM_Inst_RAM_Word0_INIT_02 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C1644940C00C7940C1539940C";
constant PM_Inst_RAM_Word0_INIT_03 : bit_vector(0 to 255) := x"000000280022003100340037003A0000005C222A2C3B5D5B2F3F3D2B5E3E3C7C";
constant PM_Inst_RAM_Word0_INIT_04 : bit_vector(0 to 255) := x"010101010101002000210030003300360039000000270023003200350038003B";
constant PM_Inst_RAM_Word0_INIT_05 : bit_vector(0 to 255) := x"0505050505050404040404040404030303030303030302020202020202020101";
constant PM_Inst_RAM_Word0_INIT_06 : bit_vector(0 to 255) := x"2010080402018040201008040201804020100804020106060606060606060505";
constant PM_Inst_RAM_Word0_INIT_07 : bit_vector(0 to 255) := x"0000000000008040201008040201804020100804020180402010080402018040";
constant PM_Inst_RAM_Word0_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000005000001000000000000";
constant PM_Inst_RAM_Word0_INIT_09 : bit_vector(0 to 255) := x"E6A0E011BFCDBFDEE0DFEFCFBE1F241116DD1193000000000000000000000000";
constant PM_Inst_RAM_Word0_INIT_0A : bit_vector(0 to 255) := x"E014BE1BF7C907B131A2F3C89631920D95D8C004BF0B9503EF0FE3F2E1E2E0B0";
constant PM_Inst_RAM_Word0_INIT_0B : bit_vector(0 to 255) := x"1901940E2FEC2FFD9722C005E0D1E3C0E011F7E107B131AB921DC001E0B1E1A2";
constant PM_Inst_RAM_Word0_INIT_0C : bit_vector(0 to 255) := x"9001918DC0042FB92FA82FF72FE60000940C1907940C170E940EF7C107D132CC";
constant PM_Inst_RAM_Word0_INIT_0D : bit_vector(0 to 255) := x"9508E0808385E186F02030672FF92FE895080B991B88F7C840505041F4211980";
constant PM_Inst_RAM_Word0_INIT_0E : bit_vector(0 to 255) := x"E090C002FD22B14DB98D7F8CB18D9A70C0019870F4113066C002FD60E0302F26";
constant PM_Inst_RAM_Word0_INIT_0F : bit_vector(0 to 255) := x"93DF93CF931F930F92FF9508E081B98D2B892B8470812F8295279536E092C001";
constant PM_Inst_RAM_Word0_INIT_10 : bit_vector(0 to 255) := x"C008E081F4113F8FB18FCFFE9B77B8FF94FA24FF2FD72FC61581940E2F172F06";
constant PM_Inst_RAM_Word0_INIT_11 : bit_vector(0 to 255) := x"2FF92FE8950890FF910F911F91CF91DFE080F388077117600B7D1B6C1581940E";
constant PM_Inst_RAM_Word0_INIT_12 : bit_vector(0 to 255) := x"2F84B96F2FB92FA8950815FC940EE06181842FF92FE8950815FC940EE0608184";
constant PM_Inst_RAM_Word0_INIT_13 : bit_vector(0 to 255) := x"96324F3F5F2EB98F8181CFFE9B77B98F8180CFFE9B77E030E0202FF92FE82F95";
constant PM_Inst_RAM_Word0_INIT_14 : bit_vector(0 to 255) := x"B98FEF8FCFFE9B77B98FEF8FCFFE9B77B98FEF8FCFFE9B77F78907383020E082";
constant PM_Inst_RAM_Word0_INIT_15 : bit_vector(0 to 255) := x"2F8A9715938C9615E1819508E081F4113085718F971A938C961AB18FCFFE9B77";
constant PM_Inst_RAM_Word0_INIT_16 : bit_vector(0 to 255) := x"2F172F061581940E2FD92FC893DF93CF931F930F92FF9508E0800125940E2F9B";
constant PM_Inst_RAM_Word0_INIT_17 : bit_vector(0 to 255) := x"B18FCFFE9B77B8FFC00CE08FF0104071526D0B711B601581940EC00994FA24FF";
constant PM_Inst_RAM_Word0_INIT_18 : bit_vector(0 to 255) := x"91CF91DFE0800125940E2F9D2F8C838DE08DC007E081F4113F8EF3813F8F878A";
constant PM_Inst_RAM_Word0_INIT_19 : bit_vector(0 to 255) := x"EF4F8538812FB98FEF8FF0D12388818E2FD92FC893DF93CF950890FF910F911F";
constant PM_Inst_RAM_Word0_INIT_1A : bit_vector(0 to 255) := x"CFFE9B77832F8738F3A84092508197012F932F824F3F5F2FB94FCFFE9B77C003";
constant PM_Inst_RAM_Word0_INIT_1B : bit_vector(0 to 255) := x"2FC893DF93CF931F930F92FF92EF92DF950891CF91DF821E0125940E2F9D2F8C";
constant PM_Inst_RAM_Word0_INIT_1C : bit_vector(0 to 255) := x"E071E26C2F9D2F8C011E940E2F9D2F8C0194940E2F152F042EF32EE22ED62FD9";
constant PM_Inst_RAM_Word0_INIT_1D : bit_vector(0 to 255) := x"95B6C0042E022D8E2D9F2FA02FB1E030E128CFFE9B77B98F64802D8D00FB940E";
constant PM_Inst_RAM_Word0_INIT_1E : bit_vector(0 to 255) := x"F41120DDF75907383F28EF8F40305028CFFE9B77B98FF7D2940A9587959795A7";
constant PM_Inst_RAM_Word0_INIT_1F : bit_vector(0 to 255) := x"CFFE9B77B92FEF2FE090CFFE9B77B98FEF8FC001E887F41116D8E088C006E985";
constant PM_Inst_RAM_Word0_INIT_20 : bit_vector(0 to 255) := x"92DF92CF950890DF90EF90FF910F911F91CF91DF878AF7C15091C002FF87B18F";
constant PM_Inst_RAM_Word0_INIT_21 : bit_vector(0 to 255) := x"055115412ED32EC22F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF";
constant PM_Inst_RAM_Word0_INIT_22 : bit_vector(0 to 255) := x"2F8CF7D1952A1F111F001CFF0CEEE029F0393083858BC03DE182F41105710561";
constant PM_Inst_RAM_Word0_INIT_23 : bit_vector(0 to 255) := x"2D4CEF6E2F9D2F8CC026E084F011238801B8940E2D2E2D3F2F402F51E1682F9D";
constant PM_Inst_RAM_Word0_INIT_24 : bit_vector(0 to 255) := x"2F8CC013E185F411238800FB940EE072E5682F9D2F8CF0F12388012C940E2D5D";
constant PM_Inst_RAM_Word0_INIT_25 : bit_vector(0 to 255) := x"2388B18FCFFE9B77B98FEF8FF439238801B8940EE050E040E030E020E06D2F9D";
constant PM_Inst_RAM_Word0_INIT_26 : bit_vector(0 to 255) := x"90CF90DF90EF90FF910F911F91CF91DFE0800125940E2F9D2F8C838DE184F081";
constant PM_Inst_RAM_Word0_INIT_27 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928FCFF1E0810125940E2F9D2F8C9508";
constant PM_Inst_RAM_Word0_INIT_28 : bit_vector(0 to 255) := x"2F80C081F409051115012E932E822ED72EC62EB52EA42FD92FC893DF93CF931F";
constant PM_Inst_RAM_Word0_INIT_29 : bit_vector(0 to 255) := x"0759174881BB81AA81998188F0712388818EC073F008409250811F930F822F91";
constant PM_Inst_RAM_Word0_INIT_2A : bit_vector(0 to 255) := x"E069F0393083858B82DB82CA82B982A8F538069916888598818FF429077B076A";
constant PM_Inst_RAM_Word0_INIT_2B : bit_vector(0 to 255) := x"238801B8940E2D2A2D3B2D4C2D5DE1612F9D2F8CF7D1956A1CDD1CCC1CBB0CAA";
constant PM_Inst_RAM_Word0_INIT_2C : bit_vector(0 to 255) := x"EF8F838EE081821F8618C03FF40923880165940E2F9D2F8CC046838DE083F019";
constant PM_Inst_RAM_Word0_INIT_2D : bit_vector(0 to 255) := x"2FB12FA0838F8798F3C8059915889601B92FCFFE9B77C004EF2F8598818FB98F";
constant PM_Inst_RAM_Word0_INIT_2E : bit_vector(0 to 255) := x"4F3F5F2FB99F83801FF30FE22DFF2DEEB18FCFFE9B77C00BEF9FE030E0209711";
constant PM_Inst_RAM_Word0_INIT_2F : bit_vector(0 to 255) := x"8589832F87381F310F208538812F938C1DBF0DAEB18FCFFE9B77F390073B172A";
constant PM_Inst_RAM_Word0_INIT_30 : bit_vector(0 to 255) := x"C001E0800125940E2F9D2F8CC0060194940E2F9D2F8CF05840325020F0192388";
constant PM_Inst_RAM_Word0_INIT_31 : bit_vector(0 to 255) := x"92FF92EF9508908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE081";
constant PM_Inst_RAM_Word0_INIT_32 : bit_vector(0 to 255) := x"92BF950890EF90FF910F911F0277940EE012E000E030E0202EF32EE2931F930F";
constant PM_Inst_RAM_Word0_INIT_33 : bit_vector(0 to 255) := x"834C821D821E8619861B2EB62FD92FC893DF93CF931F930F92FF92EF92DF92CF";
constant PM_Inst_RAM_Word0_INIT_34 : bit_vector(0 to 255) := x"15D4940EE060E08C0125940E2F9D2F8C15D4940EE061818C2ED72EC61581940E";
constant PM_Inst_RAM_Word0_INIT_35 : bit_vector(0 to 255) := x"E0809870B98DE58315D4940EE061E08A15D4940EE061E08D15D4940EE061E08B";
constant PM_Inst_RAM_Word0_INIT_36 : bit_vector(0 to 255) := x"097D196C1581940EC009011E940E2F9D2F8CF7D1308A5F8FCFFE9B77B99FEF9F";
constant PM_Inst_RAM_Word0_INIT_37 : bit_vector(0 to 255) := x"878A2F1801B8940EE050E040E030E020E0602F9D2F8CC065E081F01040775D61";
constant PM_Inst_RAM_Word0_INIT_38 : bit_vector(0 to 255) := x"E080C010871BC002FF8201B8940EE050E040E031EA2AE0682F9D2F8CF7513081";
constant PM_Inst_RAM_Word0_INIT_39 : bit_vector(0 to 255) := x"858B878BE082C03DE082F0113A9A879AF7C930845F8FB19FCFFE9B77B92FEF2F";
constant PM_Inst_RAM_Word0_INIT_3A : bit_vector(0 to 255) := x"196C1581940EC0092F17E4702D012CF12CE1C00F2711270024FF24EEF0293082";
constant PM_Inst_RAM_Word0_INIT_3B : bit_vector(0 to 255) := x"2F8C01B8940EE050E040E030E020E3672F9D2F8CC024E088F01040775D61097D";
constant PM_Inst_RAM_Word0_INIT_3C : bit_vector(0 to 255) := x"2F9D2F8CF5313082858BF7112388878A01B8940E2D2E2D3F2F402F51E2692F9D";
constant PM_Inst_RAM_Word0_INIT_3D : bit_vector(0 to 255) := x"E0800125940E2F9D2F8C838DE086F041238801B8940EE050E040E030E020E36A";
constant PM_Inst_RAM_Word0_INIT_3E : bit_vector(0 to 255) := x"CFFE9B77B99FEF9FE080878BE083F4113C807C80B18FCFFE9B77B98FEF8FC01C";
constant PM_Inst_RAM_Word0_INIT_3F : bit_vector(0 to 255) := x"911F91CF91DF00D8940E2D6B2F9D2F8C0125940E2F9D2F8CF7C930835F8FB12F";
-- BRAM 0 in address space [0x00000800:0x00000FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word1 LOC = RAMB16_X0Y8;
constant PM_Inst_RAM_Word1_INIT_00 : bit_vector(0 to 255) := x"E220E090E0802FB72FA62FD92FC893DF93CF950890BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word1_INIT_01 : bit_vector(0 to 255) := x"E090E680F019322EC024E040E057F7B90591308B960183201FF90FE82FFB2FEA";
constant PM_Inst_RAM_Word1_INIT_02 : bit_vector(0 to 255) := x"1754F7B923332D3095C896012FF92FE8F1091732C01AE048E05AF131305AC007";
constant PM_Inst_RAM_Word1_INIT_03 : bit_vector(0 to 255) := x"5F4F83201DF10FE42FFB2FEA5220F408318A56812F82F4A0372FF0B03221F0C0";
constant PM_Inst_RAM_Word1_INIT_04 : bit_vector(0 to 255) := x"927F926F950891CF91DF2F89E090C001E091F0193280918CE090F6C923229129";
constant PM_Inst_RAM_Word1_INIT_05 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F";
constant PM_Inst_RAM_Word1_INIT_06 : bit_vector(0 to 255) := x"C07BF40807B707A60795178489BD89AC899B898AC085F4092322812C2F172F06";
constant PM_Inst_RAM_Word1_INIT_07 : bit_vector(0 to 255) := x"8529C06A861C861B861A86198618821F821E821DF4490511050104F114E1C08A";
constant PM_Inst_RAM_Word1_INIT_08 : bit_vector(0 to 255) := x"2E952E842E732E6240504040403050219609E09085858DFB8DEA855C854B853A";
constant PM_Inst_RAM_Word1_INIT_09 : bit_vector(0 to 255) := x"090108F108E194084F5F4F4F4F3F5F2FF7D2940A9467947794879496C0042E08";
constant PM_Inst_RAM_Word1_INIT_0A : bit_vector(0 to 255) := x"1D011CF11CE19408F7D2958A94A794B794C794D6C0042ED12EC02CBF2CAE0911";
constant PM_Inst_RAM_Word1_INIT_0B : bit_vector(0 to 255) := x"838D8DB98DA8899F898EF4490551054105311521F02804D904C804B714A61D11";
constant PM_Inst_RAM_Word1_INIT_0C : bit_vector(0 to 255) := x"2D288D9B8D8A8578816F815E814DC01208D908C808B718A6C01787B883AF839E";
constant PM_Inst_RAM_Word1_INIT_0D : bit_vector(0 to 255) := x"1E9D0E8C2C912E88E085C010F431238808D108C108B108A194080F04940E2D39";
constant PM_Inst_RAM_Word1_INIT_0E : bit_vector(0 to 255) := x"910F911F91CF91DFE080C001E081871C870B86FA86E9F72104D104C104B114A1";
constant PM_Inst_RAM_Word1_INIT_0F : bit_vector(0 to 255) := x"93CFCFE6CF73F00930229508906F907F908F909F90AF90BF90CF90DF90EF90FF";
constant PM_Inst_RAM_Word1_INIT_10 : bit_vector(0 to 255) := x"8989C00AE030E020F41923880CC5940E8998858F857E856D2F462FD92FC893DF";
constant PM_Inst_RAM_Word1_INIT_11 : bit_vector(0 to 255) := x"931F930F950891CF91DF2F932F824F3E5E2CF7E1959A1F330F22E095E0302F28";
constant PM_Inst_RAM_Word1_INIT_12 : bit_vector(0 to 255) := x"E0612F912F80C03DFF878183C043F409238881842FF92FE82F192F0893DF93CF";
constant PM_Inst_RAM_Word1_INIT_13 : bit_vector(0 to 255) := x"8F8C89B589A489938982F440308281842FF12FE0F1B997002FD92FC804FF940E";
constant PM_Inst_RAM_Word1_INIT_14 : bit_vector(0 to 255) := x"27AA2F8A2F9B8DB18DA0899789868F8A8F9B899789862FF12FE08FBF8FAE8F9D";
constant PM_Inst_RAM_Word1_INIT_15 : bit_vector(0 to 255) := x"96482F9D2F8C4F7F5E6A2F7D2F6CF0619730011391F0011291E08B8C8B9D27BB";
constant PM_Inst_RAM_Word1_INIT_16 : bit_vector(0 to 255) := x"91CF91DFE080C0010C64940E8383778F81832FF12FE08B8A8B9B8D998D889509";
constant PM_Inst_RAM_Word1_INIT_17 : bit_vector(0 to 255) := x"950891CF91DFE081821CF0112388051E940E2FD92FC893DF93CF9508910F911F";
constant PM_Inst_RAM_Word1_INIT_18 : bit_vector(0 to 255) := x"D000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F";
constant PM_Inst_RAM_Word1_INIT_19 : bit_vector(0 to 255) := x"C0A1F00930819714918C96142FB92FA82ED72EC62EB52EA42EF92EE8B7DEB7CD";
constant PM_Inst_RAM_Word1_INIT_1A : bit_vector(0 to 255) := x"8483847284612DFF2DEEC097E081F41105B105A19700C0B0C09DFF81918C9613";
constant PM_Inst_RAM_Word1_INIT_1B : bit_vector(0 to 255) := x"918D965A2DBF2DAEC085F4092388044E940E2D4A2D5B2D6C2D7D2D9F2D8E8494";
constant PM_Inst_RAM_Word1_INIT_1C : bit_vector(0 to 255) := x"23880F82940E9759917C916D915D914D9656F49104D104C104B114A1975B919C";
constant PM_Inst_RAM_Word1_INIT_1D : bit_vector(0 to 255) := x"917C916D915D914D96152DBF2DAEC0428E118E108A178A162DFF2DEEC06FF409";
constant PM_Inst_RAM_Word1_INIT_1E : bit_vector(0 to 255) := x"975B91FC91ED965A2DBF2DAEC057F40923880F04940E4F3F5F2F2F3D2F2C9718";
constant PM_Inst_RAM_Word1_INIT_1F : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987817C816B815A8149";
constant PM_Inst_RAM_Word1_INIT_20 : bit_vector(0 to 255) := x"8167815681452DFF2DEEF1B123880F82940E2F9F2F8EF4B0077B076A07591748";
constant PM_Inst_RAM_Word1_INIT_21 : bit_vector(0 to 255) := x"92BD92AD96522DBF2DAEF13123880E5B940EE03FEF2FEF1FEF0F8D938D828570";
constant PM_Inst_RAM_Word1_INIT_22 : bit_vector(0 to 255) := x"2D7DF0912388051E940E2D9F2D8E938C961368809713918C9613975592DC92CD";
constant PM_Inst_RAM_Word1_INIT_23 : bit_vector(0 to 255) := x"044E940E2D9F2D8E2D462D572D682D79F420049D048C047B146A2D4A2D5B2D6C";
constant PM_Inst_RAM_Word1_INIT_24 : bit_vector(0 to 255) := x"90AF90BF90CF90DF90EF90FF910F911F91DF91CF900F900F900F900FE080C001";
constant PM_Inst_RAM_Word1_INIT_25 : bit_vector(0 to 255) := x"F00807B707A60795178489B589A4899389822DFF2DEE9508906F907F908F909F";
constant PM_Inst_RAM_Word1_INIT_26 : bit_vector(0 to 255) := x"92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922FCFDFCF44";
constant PM_Inst_RAM_Word1_INIT_27 : bit_vector(0 to 255) := x"C0EDC0D7FF80818BC0DAF4092388818C2E552E442FD92FC893DF93CF931F930F";
constant PM_Inst_RAM_Word1_INIT_28 : bit_vector(0 to 255) := x"C0BF2C752C641E3D0E2C2C312E27E0752E932E822F372F26085F184E2C5B2C4A";
constant PM_Inst_RAM_Word1_INIT_29 : bit_vector(0 to 255) := x"E0992F152F042EF32EE2818C22B322A22EB6E0612EA6EF6F855C854B853A8529";
constant PM_Inst_RAM_Word1_INIT_2A : bit_vector(0 to 255) := x"1D5F0D4E8D758D648D538D42F44930828DFB8DEAF7D1959A94E794F795079516";
constant PM_Inst_RAM_Word1_INIT_2B : bit_vector(0 to 255) := x"F4490551054105311521F4D920DDF4E904B114A120DE94DA80D4C0411F711F60";
constant PM_Inst_RAM_Word1_INIT_2C : bit_vector(0 to 255) := x"2D222F9F2F8E8578816F815E814DC00D87B883AF839E838D8DB98DA8899F898E";
constant PM_Inst_RAM_Word1_INIT_2D : bit_vector(0 to 255) := x"40704060405050428578816F815E814D8DFB8DEAC080F40923880F04940E2D33";
constant PM_Inst_RAM_Word1_INIT_2E : bit_vector(0 to 255) := x"1F7B1F6A1F590F4889B189A085978586F7D2940A1F771F661F550F44C0048405";
constant PM_Inst_RAM_Word1_INIT_2F : bit_vector(0 to 255) := x"818B2ED92EC8F410059715862CD72CC6099B198AE092E0801D711D611D510D4D";
constant PM_Inst_RAM_Word1_INIT_30 : bit_vector(0 to 255) := x"00FC91B000FB91A000FA919000F99180C080F00906D8E08216C8E080C006FD86";
constant PM_Inst_RAM_Word1_INIT_31 : bit_vector(0 to 255) := x"2CF92CE82D1D2D0C2D3B2D2A0315919003149180C072F409077B076A07591748";
constant PM_Inst_RAM_Word1_INIT_32 : bit_vector(0 to 255) := x"2DA81D5D0D4C2F532F424F3E5E2C2D3B2D2AC0161C9D0C8CF19123880277940E";
constant PM_Inst_RAM_Word1_INIT_33 : bit_vector(0 to 255) := x"E0402D3D2D2C1E9F0E8E0BF31BE2F7D907F517E4938D9181C0022FF32FE22DB9";
constant PM_Inst_RAM_Word1_INIT_34 : bit_vector(0 to 255) := x"1461087D186C87BC87AB879A87891FB51FA41F930F8285BC85AB859A8589E050";
constant PM_Inst_RAM_Word1_INIT_35 : bit_vector(0 to 255) := x"90EF90FF910F911F91CF91DF2F952F84EF5FEF4FC0022D552D44CF3DF0090471";
constant PM_Inst_RAM_Word1_INIT_36 : bit_vector(0 to 255) := x"88CC88BB88AA9508902F903F904F905F906F907F908F909F90AF90BF90CF90DF";
constant PM_Inst_RAM_Word1_INIT_37 : bit_vector(0 to 255) := x"0BA0099F198E2D8A2D9B2DAC2DBDE050E0402F352F24851C850B84FA84E988DD";
constant PM_Inst_RAM_Word1_INIT_38 : bit_vector(0 to 255) := x"23880CC5940EE0402F642F752F862F97CEFCCEF9F40807B507A4079317820BB1";
constant PM_Inst_RAM_Word1_INIT_39 : bit_vector(0 to 255) := x"2ED92EC8B7DEB7CD920F93CF93DF931F930F92FF92EF92DF92CFCFC3CF95F009";
constant PM_Inst_RAM_Word1_INIT_3A : bit_vector(0 to 255) := x"E0414F7F5F6F2F7D2F6C2D9D2D8C8514850384F284E1F080308281842FF92FE8";
constant PM_Inst_RAM_Word1_INIT_3B : bit_vector(0 to 255) := x"90EF90FF910F911F91DF91CF900F2F932F82E030E020F07197010662940EE050";
constant PM_Inst_RAM_Word1_INIT_3C : bit_vector(0 to 255) := x"87B487A3879287811DB11DA1964F85B485A3859285812DFD2DEC950890CF90DF";
constant PM_Inst_RAM_Word1_INIT_3D : bit_vector(0 to 255) := x"F7E195EA1F330F22E0E5E0302F28708F2D8EF7D195FA94E794F795079516E0F5";
constant PM_Inst_RAM_Word1_INIT_3E : bit_vector(0 to 255) := x"2FE6C045F0092388818C2F172F062FD92FC893DF93CF931F930FCFD44F3E5E2C";
constant PM_Inst_RAM_Word1_INIT_3F : bit_vector(0 to 255) := x"0F88E045E0B0E0A08D918D808E198E188A1F8A1E838CE082F4B1318089872FF7";
-- BRAM 0 in address space [0x00001000:0x000017FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word2 LOC = RAMB16_X0Y1;
constant PM_Inst_RAM_Word2_INIT_00 : bit_vector(0 to 255) := x"2FF72FE6838CE083F5413280C0188BBD8BAC8B9B8B8AF7D1954A1FBB1FAA1F99";
constant PM_Inst_RAM_Word2_INIT_01 : bit_vector(0 to 255) := x"0FE8940E2F912F804F3F5E2E2F3D2F2C8F798F688B5F8B4E8D758D648D538D42";
constant PM_Inst_RAM_Word2_INIT_02 : bit_vector(0 to 255) := x"861E861D861C861B861A86198618821F821E821D838BE0818F0A8F1BF0912388";
constant PM_Inst_RAM_Word2_INIT_03 : bit_vector(0 to 255) := x"2F142FD92FC893DF93CF931F9508910F911F91CF91DFE080C0018A198A18861F";
constant PM_Inst_RAM_Word2_INIT_04 : bit_vector(0 to 255) := x"C057F00974822F84F021718185834FFE5EECF7E1957A1FFF0FEEE075E0F02FE6";
constant PM_Inst_RAM_Word2_INIT_05 : bit_vector(0 to 255) := x"E0A0899589848BB887AF879E878D00FC91B000FB91A000FA919000F991808B69";
constant PM_Inst_RAM_Word2_INIT_06 : bit_vector(0 to 255) := x"8F688B5F8B4E2B7B2B6A2B592B48E0B0E0A08D938D82274427552F792F68E0B0";
constant PM_Inst_RAM_Word2_INIT_07 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A8DB78DA68D958D84F451970070907188E09085838F79";
constant PM_Inst_RAM_Word2_INIT_08 : bit_vector(0 to 255) := x"2F81838CE084F0D123880FE8940E8D9B8D8A4F3F5E2E2F3D2F2CF5219740C00D";
constant PM_Inst_RAM_Word2_INIT_09 : bit_vector(0 to 255) := x"2F9D2F8CC00AE081C002FD16861C861B861A86198618821F821E821D838B708F";
constant PM_Inst_RAM_Word2_INIT_0A : bit_vector(0 to 255) := x"2FD92FC893DF93CF9508911F91CF91DFE080C0010580940EE070E060E050E040";
constant PM_Inst_RAM_Word2_INIT_0B : bit_vector(0 to 255) := x"899F898EF0A123881061940EE070E060E050E0418D9B8D8A4F3F5F2B2F392F28";
constant PM_Inst_RAM_Word2_INIT_0C : bit_vector(0 to 255) := x"6880818B8FB98FA88B9F8B8E85B881AF819E818DF45905B105A197008DB98DA8";
constant PM_Inst_RAM_Word2_INIT_0D : bit_vector(0 to 255) := x"92DF92CF92BF92AF929F928F927F925F924F923F922F950891CF91DFE081838B";
constant PM_Inst_RAM_Word2_INIT_0E : bit_vector(0 to 255) := x"835E2F072F162ED92EC8B7DEB7CDD000D000D00093CF93DF931F930F92FF92EF";
constant PM_Inst_RAM_Word2_INIT_0F : bit_vector(0 to 255) := x"2DFD2DECC1B1C191FF81918C9613C195F00930819714918C96142FB92FA8834D";
constant PM_Inst_RAM_Word2_INIT_10 : bit_vector(0 to 255) := x"940E2D9D2D8CF03907B707A60795178485B485A3859285818975896489538942";
constant PM_Inst_RAM_Word2_INIT_11 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DACC132803E802D2E532E422F302F21C17AF4092388044E";
constant PM_Inst_RAM_Word2_INIT_12 : bit_vector(0 to 255) := x"EF7F2278947A8074F7D1951A9587959795A795B6E0192F822F932FA42FB5975B";
constant PM_Inst_RAM_Word2_INIT_13 : bit_vector(0 to 255) := x"914D96152DBD2DACC053F00904911481C057F0092077229322822E97E0712E87";
constant PM_Inst_RAM_Word2_INIT_14 : bit_vector(0 to 255) := x"97002DA091BC900D919D918D9656F48905710561055115419718917C916D915D";
constant PM_Inst_RAM_Word2_INIT_15 : bit_vector(0 to 255) := x"4F3F5F2F2F3D2F2C2F9F2F8EC03587B083A7839683852DFD2DECF17905B105A1";
constant PM_Inst_RAM_Word2_INIT_16 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DAC815C814B813A8129C12EE050E040F41923880F04940E";
constant PM_Inst_RAM_Word2_INIT_17 : bit_vector(0 to 255) := x"074A07391728E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987975B";
constant PM_Inst_RAM_Word2_INIT_18 : bit_vector(0 to 255) := x"E08087508347833683252DFD2DECC105F439238808AC940E2D9D2D8CF038075B";
constant PM_Inst_RAM_Word2_INIT_19 : bit_vector(0 to 255) := x"975B91FC91ED965A2DBD2DAC2EB92EA8F410059315822CB32CA209991988E092";
constant PM_Inst_RAM_Word2_INIT_1A : bit_vector(0 to 255) := x"C00484051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E9718911C910D90FD90ED9615";
constant PM_Inst_RAM_Word2_INIT_1B : bit_vector(0 to 255) := x"1CF10CE71F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEE";
constant PM_Inst_RAM_Word2_INIT_1C : bit_vector(0 to 255) := x"158E00FC91B000FB91A000FA919000F99180F56906B9E09216A9E0901D111D01";
constant PM_Inst_RAM_Word2_INIT_1D : bit_vector(0 to 255) := x"00FC93B000FB93A000FA939000F99380EFBFEFAFEF9FEF8FF46107B107A0059F";
constant PM_Inst_RAM_Word2_INIT_1E : bit_vector(0 to 255) := x"E0A0C09FF4092388020E940E2D352D242D4E2D5F2F602F710315919003149180";
constant PM_Inst_RAM_Word2_INIT_1F : bit_vector(0 to 255) := x"89A48993898285548543853285212DFD2DECF51104911481C0451E5B0E4AE0B2";
constant PM_Inst_RAM_Word2_INIT_20 : bit_vector(0 to 255) := x"930000FA92F000F992E0C083F40923880C64940EF098075B074A0739172889B5";
constant PM_Inst_RAM_Word2_INIT_21 : bit_vector(0 to 255) := x"0CC5940EE0412D6E2D7F2F802F91C00A0316938060810316918000FC931000FB";
constant PM_Inst_RAM_Word2_INIT_22 : bit_vector(0 to 255) := x"C0022FF32FE22DB52DA41D5B0D4A2F532F424F3E5E2C2D392D28C06BF4092388";
constant PM_Inst_RAM_Word2_INIT_23 : bit_vector(0 to 255) := x"2DECE050E0402D3B2D2A083B182A1E5F0E4E0BF31BE2F7D907F517E49381918D";
constant PM_Inst_RAM_Word2_INIT_24 : bit_vector(0 to 255) := x"96192DBD2DAC87B487A3879287811FB51FA41F930F8285B485A3859285812DFD";
constant PM_Inst_RAM_Word2_INIT_25 : bit_vector(0 to 255) := x"17822DA091BC900D919D918D9652CEC2F00904311421971C915C914D913D912D";
constant PM_Inst_RAM_Word2_INIT_26 : bit_vector(0 to 255) := x"01129180C0128383688081838B558B448B338B222DFD2DECF45007B507A40793";
constant PM_Inst_RAM_Word2_INIT_27 : bit_vector(0 to 255) := x"938C961368809713918C96132DBD2DACF0412B89819E818DF0612B8901139190";
constant PM_Inst_RAM_Word2_INIT_28 : bit_vector(0 to 255) := x"2DACE081C007815E814DF0192388051E940E2D9D2D8CC006FF8381832DFD2DEC";
constant PM_Inst_RAM_Word2_INIT_29 : bit_vector(0 to 255) := x"911F91DF91CFBFCDBE0FBFDE94F8B60F96262F952F84EF5FEF4F938C96122DBD";
constant PM_Inst_RAM_Word2_INIT_2A : bit_vector(0 to 255) := x"FD829508902F903F904F905F907F908F909F90AF90BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word2_INIT_2B : bit_vector(0 to 255) := x"08D5940E2F5B2F4A0BBF1BAE9711F7E92000900D2FBF2FAE2FF72FE6CE62CE4D";
constant PM_Inst_RAM_Word2_INIT_2C : bit_vector(0 to 255) := x"900F08D5940EE050E0414F7F5F6F2F7D2F6C8369B7DEB7CD920F93CF93DF9508";
constant PM_Inst_RAM_Word2_INIT_2D : bit_vector(0 to 255) := x"F409238808AC940E2FD92FC893DF93CF931F930F92FF92EF92DF950891DF91CF";
constant PM_Inst_RAM_Word2_INIT_2E : bit_vector(0 to 255) := x"84051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E8518810F80FE80ED8DFB8DEAC050";
constant PM_Inst_RAM_Word2_INIT_2F : bit_vector(0 to 255) := x"80D41F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEEC004";
constant PM_Inst_RAM_Word2_INIT_30 : bit_vector(0 to 255) := x"0C9F940E1D911D811D710D6D2D6E2D7F2F802F91C00D0911090108F108E19408";
constant PM_Inst_RAM_Word2_INIT_31 : bit_vector(0 to 255) := x"1F441F330F22C0048405E050E040E032E0208DFB8DEAF78920DD94DAF0F92388";
constant PM_Inst_RAM_Word2_INIT_32 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A1FB51FA41F930F8289BD89AC899B898AF7D2940A1F55";
constant PM_Inst_RAM_Word2_INIT_33 : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F950890DF90EF90FF910F911F91CF91DFE080C001";
constant PM_Inst_RAM_Word2_INIT_34 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F972BB7DEB7CD93CF93DF931F930F92FF92EF92DF92CF";
constant PM_Inst_RAM_Word2_INIT_35 : bit_vector(0 to 255) := x"2F1D2F0C2F952F84C0F2F0092388918C96142FB92FA82E822ED72EC62EB92EA8";
constant PM_Inst_RAM_Word2_INIT_36 : bit_vector(0 to 255) := x"965B2DBB2DAA8D938D822DFD2DECC0E5F40923880407940E2F712F604F1F5F0F";
constant PM_Inst_RAM_Word2_INIT_37 : bit_vector(0 to 255) := x"2499971C921C921D921D921D96192DBD2DAC8610821782168215975A938E939C";
constant PM_Inst_RAM_Word2_INIT_38 : bit_vector(0 to 255) := x"9516E085C0C0F40997002FF92FE80793940E2D9D2D8CC0492E792E602F912F80";
constant PM_Inst_RAM_Word2_INIT_39 : bit_vector(0 to 255) := x"2DBB2DAAF4992099F4D93E85F01123888180701F2D1EF7D1958A94E794F79507";
constant PM_Inst_RAM_Word2_INIT_3A : bit_vector(0 to 255) := x"935C934D933D932D961D00FC915000FB914000FA913000F991209751931C9651";
constant PM_Inst_RAM_Word2_INIT_3B : bit_vector(0 to 255) := x"2F2800C9940EE050E04B2F7F2F6E2D972D86C02794932499F4C1238881809750";
constant PM_Inst_RAM_Word2_INIT_3C : bit_vector(0 to 255) := x"2DFD2DEC94932499C07E2F612D9B2D8AC086F409338073802D88F4592B232F39";
constant PM_Inst_RAM_Word2_INIT_3D : bit_vector(0 to 255) := x"71822D88CFA7F408071B070A06F916E889B589A4899389828514850384F284E1";
constant PM_Inst_RAM_Word2_INIT_3E : bit_vector(0 to 255) := x"2DACC05FF4A197002F192F0804FF940EE0612D9B2D8AF0512099C06BF0093182";
constant PM_Inst_RAM_Word2_INIT_3F : bit_vector(0 to 255) := x"8A112DFB2DEAC051F40923880AD3940E2D9D2D8CC058F4093082918C96142DBD";
-- BRAM 0 in address space [0x00001800:0x00001FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word3 LOC = RAMB16_X0Y3;
constant PM_Inst_RAM_Word3_INIT_00 : bit_vector(0 to 255) := x"920D9001E08B96312FFD2FEC2FB12FA0F7E9958A921D2FB12FA0E280E011E104";
constant PM_Inst_RAM_Word3_INIT_01 : bit_vector(0 to 255) := x"950996402F912F804F7F5F622F712F60F0499730011391F0011291E0F7E15081";
constant PM_Inst_RAM_Word3_INIT_02 : bit_vector(0 to 255) := x"919C918D96502FB12FA087868797E098E0808B808B912FF12FE0E298E281C00A";
constant PM_Inst_RAM_Word3_INIT_03 : bit_vector(0 to 255) := x"938E939C9657971F919C918D961E9758938E939C96599752938E939C96539751";
constant PM_Inst_RAM_Word3_INIT_04 : bit_vector(0 to 255) := x"962BE080C001083A940E2D4889612DFB2DEA2D9B2D8AF04923880C64940E9756";
constant PM_Inst_RAM_Word3_INIT_05 : bit_vector(0 to 255) := x"909F90AF90BF90CF90DF90EF90FF910F911F91DF91CFBFCDBE0FBFDE94F8B60F";
constant PM_Inst_RAM_Word3_INIT_06 : bit_vector(0 to 255) := x"00FC917000FB916000FA915000F99140F1992388031691809508906F907F908F";
constant PM_Inst_RAM_Word3_INIT_07 : bit_vector(0 to 255) := x"031991600318915003179140F1192388020E940EE031E1240315919003149180";
constant PM_Inst_RAM_Word3_INIT_08 : bit_vector(0 to 255) := x"2388020E940EE031E1240315919003149180F0910571056105511541031A9170";
constant PM_Inst_RAM_Word3_INIT_09 : bit_vector(0 to 255) := x"92EF9508E0809508E08103169210031A9210031992100318921003179210F061";
constant PM_Inst_RAM_Word3_INIT_0A : bit_vector(0 to 255) := x"31E4E0839211E0F1E1E4F0A923880C64940E2F192F082EF72EE6931F930F92FF";
constant PM_Inst_RAM_Word3_INIT_0B : bit_vector(0 to 255) := x"E0810316938060810316918000FC931000FB930000FA92F000F992E0F7D907F8";
constant PM_Inst_RAM_Word3_INIT_0C : bit_vector(0 to 255) := x"91802ED42F192F082EF72EE6931F930F92FF92EF92DF950890EF90FF910F911F";
constant PM_Inst_RAM_Word3_INIT_0D : bit_vector(0 to 255) := x"F0E923880C64940EF0D107B107A0059F158E00FC91B000FB91A000FA919000F9";
constant PM_Inst_RAM_Word3_INIT_0E : bit_vector(0 to 255) := x"00F992E0F0792388031E940EE031E1242D4E2D5F2F602F710315919003149180";
constant PM_Inst_RAM_Word3_INIT_0F : bit_vector(0 to 255) := x"910F911FE080C001E08103169380298D0316918000FC931000FB930000FA92F0";
constant PM_Inst_RAM_Word3_INIT_10 : bit_vector(0 to 255) := x"93DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F950890DF90EF90FF";
constant PM_Inst_RAM_Word3_INIT_11 : bit_vector(0 to 255) := x"F0083045C04124BB24AA24992488F429234403149360031593702F142ED92EC8";
constant PM_Inst_RAM_Word3_INIT_12 : bit_vector(0 to 255) := x"2FFD2FEC9721E0D02FC1C122F40923880CC5940EE040E090E080E070E060C12C";
constant PM_Inst_RAM_Word3_INIT_13 : bit_vector(0 to 255) := x"2B897090778FE09040F15BEE81804FFE54E24FFE5EECF7E1957A1FFF0FEEE074";
constant PM_Inst_RAM_Word3_INIT_14 : bit_vector(0 to 255) := x"0FCCE064C0FFF40805B105A10591368481B381A2819181804FFE53E6C10BF009";
constant PM_Inst_RAM_Word3_INIT_15 : bit_vector(0 to 255) := x"2D9BC0EEF40904B104A10491148180BB80AA809980884FDD52C6F7E1956A1FDD";
constant PM_Inst_RAM_Word3_INIT_16 : bit_vector(0 to 255) := x"F0094092508001209190011F9180C0E4F40923880CC5940EE0402D682D792D8A";
constant PM_Inst_RAM_Word3_INIT_17 : bit_vector(0 to 255) := x"238801219180C0D0F4092B890123919001229180C0D7F409232201249120C0DC";
constant PM_Inst_RAM_Word3_INIT_18 : bit_vector(0 to 255) := x"87452DFD2DEC5F4FC008E070E06186158384012191808B222DFD2DECC0CBF409";
constant PM_Inst_RAM_Word3_INIT_19 : bit_vector(0 to 255) := x"940A1F330F22C0022E042F372F26E090818485452DFD2DECC0B9F00830485041";
constant PM_Inst_RAM_Word3_INIT_1A : bit_vector(0 to 255) := x"01389120C008E050E040F01905311521012B9130012A9120F74107931782F7E2";
constant PM_Inst_RAM_Word3_INIT_1B : bit_vector(0 to 255) := x"012390F0012290E087508347833683252DFD2DEC013B9150013A914001399130";
constant PM_Inst_RAM_Word3_INIT_1C : bit_vector(0 to 255) := x"8F808F9101269190012591808B168B058AF48AE31D1B1D0A1CF90CE8E010E000";
constant PM_Inst_RAM_Word3_INIT_1D : bit_vector(0 to 255) := x"8F848F738F622DFD2DEC1F911F801D7F0D6E18A2940EE090E080E07001249160";
constant PM_Inst_RAM_Word3_INIT_1E : bit_vector(0 to 255) := x"E040952627332F234F3E5021F7E1955A1F330F22E05501269130012591208F95";
constant PM_Inst_RAM_Word3_INIT_1F : bit_vector(0 to 255) := x"E0A0F019970001289190012791808B518B40873787261F591F481F370F26E050";
constant PM_Inst_RAM_Word3_INIT_20 : bit_vector(0 to 255) := x"0AF31AE22CE82CF92D0A2D1B013791B0013691A00135919001349180C008E0B0";
constant PM_Inst_RAM_Word3_INIT_21 : bit_vector(0 to 255) := x"95479556C00484052DFD2DEC1F5B1F4A1F390F282D2E2D3F2F402F510B150B04";
constant PM_Inst_RAM_Word3_INIT_22 : bit_vector(0 to 255) := x"F410075FE0F0074FE0F0073FE0FF3F258754874387328721F7D2940A95279537";
constant PM_Inst_RAM_Word3_INIT_23 : bit_vector(0 to 255) := x"919001409180C011E0818B872DFD2DECE180F430405040404F3F5F25C006E08C";
constant PM_Inst_RAM_Word3_INIT_24 : bit_vector(0 to 255) := x"91CF91DFE080CFEDE2808FB58FA48F938F822DFD2DEC014391B0014291A00141";
constant PM_Inst_RAM_Word3_INIT_25 : bit_vector(0 to 255) := x"928F927F926F925F924F9508908F909F90AF90BF90CF90DF90EF90FF910F911F";
constant PM_Inst_RAM_Word3_INIT_26 : bit_vector(0 to 255) := x"2EE62ED52EC42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F";
constant PM_Inst_RAM_Word3_INIT_27 : bit_vector(0 to 255) := x"960185BC85AB859A8589C077F40805710561055130422E732E622E512E402EF7";
constant PM_Inst_RAM_Word3_INIT_28 : bit_vector(0 to 255) := x"2799F4293180898F895E894D893C892BC06AF40807B707A6079517841DB11DA1";
constant PM_Inst_RAM_Word3_INIT_29 : bit_vector(0 to 255) := x"2E86F7D1951A9567957795879596E0172D6C2D7D2D8E2D9FC00B2D6D2D7E2D8F";
constant PM_Inst_RAM_Word3_INIT_2A : bit_vector(0 to 255) := x"168800FC91B000FB91A000FA919000F991801EB51EA41E930E822EB92EA82E97";
constant PM_Inst_RAM_Word3_INIT_2B : bit_vector(0 to 255) := x"F4513180898FF1A923880CC5940EE0402D682D792D8A2D9BF04906BB06AA0699";
constant PM_Inst_RAM_Word3_INIT_2C : bit_vector(0 to 255) := x"1FFF0FEE70F077EF2DFD2DECC00E824082514FFE5EEC1FFF0FEE70F02DFD2DEC";
constant PM_Inst_RAM_Word3_INIT_2D : bit_vector(0 to 255) := x"F0803082898A0316938060810316918082738262825182404FFE5EEC1FFF0FEE";
constant PM_Inst_RAM_Word3_INIT_2E : bit_vector(0 to 255) := x"031A92B0031992A003189290031792801EBB1EAA1E990E8885B881AF819E818D";
constant PM_Inst_RAM_Word3_INIT_2F : bit_vector(0 to 255) := x"907F908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE080C001E081";
constant PM_Inst_RAM_Word3_INIT_30 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF9508904F905F906F";
constant PM_Inst_RAM_Word3_INIT_31 : bit_vector(0 to 255) := x"F40807B707A6079517841DB11DA1960185BC85AB859A85892ED32EC22F172F06";
constant PM_Inst_RAM_Word3_INIT_32 : bit_vector(0 to 255) := x"2D7F2F802F91C00B2D6F2F702F812799F4293180898F895E894D893C892BC057";
constant PM_Inst_RAM_Word3_INIT_33 : bit_vector(0 to 255) := x"00FA919000F991801F591F481F370F26F7D195EA9567957795879596E0E72D6E";
constant PM_Inst_RAM_Word3_INIT_34 : bit_vector(0 to 255) := x"0CC5940EE0402F622F732F842F95F049075B074A0739172800FC91B000FB91A0";
constant PM_Inst_RAM_Word3_INIT_35 : bit_vector(0 to 255) := x"E0B0E0A0819181804FFE5EEC1FFF0FEE70F02DFF2DEEF4613180898FF1312388";
constant PM_Inst_RAM_Word3_INIT_36 : bit_vector(0 to 255) := x"70BF81B381A2819181804FFE5EEC1FFF0FEE1FFF0FEE70F077EF2DFF2DEEC00F";
constant PM_Inst_RAM_Word3_INIT_37 : bit_vector(0 to 255) := x"90DF90EF90FF910F911F91CF91DFE080C001E08183B383A2839183802DFD2DEC";
constant PM_Inst_RAM_Word3_INIT_38 : bit_vector(0 to 255) := x"B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF950890CF";
constant PM_Inst_RAM_Word3_INIT_39 : bit_vector(0 to 255) := x"83B383A2839183802DFD2DECE0B0E0A0E090E0822F172F062EF52EE42ED92EC8";
constant PM_Inst_RAM_Word3_INIT_3A : bit_vector(0 to 255) := x"23880F04940E2D3B2D2A2D4E2D5F2F602F712D9D2D8C1CB11CA194082EBD2EAC";
constant PM_Inst_RAM_Word3_INIT_3B : bit_vector(0 to 255) := x"80E9F0C923880E5B940EE030E020E010E0002D4E2D5F2F602F712D9D2D8CF139";
constant PM_Inst_RAM_Word3_INIT_3C : bit_vector(0 to 255) := x"E0A0EF9FEF88C004E0BFEFAFEF9FEF88F029318089872DFD2DEC811C810B80FA";
constant PM_Inst_RAM_Word3_INIT_3D : bit_vector(0 to 255) := x"911F91DF91CF900F900F900F900FE080C001E081F278071B070A06F916E8E0B0";
constant PM_Inst_RAM_Word3_INIT_3E : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F925F924F950890AF90BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word3_INIT_3F : bit_vector(0 to 255) := x"835A83492ED92EC8B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF";
-- BRAM 0 in address space [0x00002000:0x000027FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word4 LOC = RAMB16_X0Y2;
constant PM_Inst_RAM_Word4_INIT_00 : bit_vector(0 to 255) := x"2E9AE0A22C811C511C4194082E5D2E4C2711270024FF24EE2E732E62837C836B";
constant PM_Inst_RAM_Word4_INIT_01 : bit_vector(0 to 255) := x"2DAA2DBBF17123880F04940E2D352D242D9D2D8C817C816B815A81492CB12CA1";
constant PM_Inst_RAM_Word4_INIT_02 : bit_vector(0 to 255) := x"1F1B1F0A1EF90EE8F7D2940A1FBB1FAA1F990F88C00484052DFD2DEC2D882D99";
constant PM_Inst_RAM_Word4_INIT_03 : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987815C814B813A8129";
constant PM_Inst_RAM_Word4_INIT_04 : bit_vector(0 to 255) := x"900F900F900F900FE0818313830282F182E02DF72DE6F268075B074A07391728";
constant PM_Inst_RAM_Word4_INIT_05 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF";
constant PM_Inst_RAM_Word4_INIT_06 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F9508";
constant PM_Inst_RAM_Word4_INIT_07 : bit_vector(0 to 255) := x"876C875B874A2E392E28BFCDBE0FBFDE94F8B60F972FB7DEB7CD93CF93DF931F";
constant PM_Inst_RAM_Word4_INIT_08 : bit_vector(0 to 255) := x"2E912E80F0590531052105111501913C912D911D910D2FB32FA2872E873F877D";
constant PM_Inst_RAM_Word4_INIT_09 : bit_vector(0 to 255) := x"861980B380A2809180802FF92FE8C01186191CB11CA11C911C8194082EB32EA2";
constant PM_Inst_RAM_Word4_INIT_0A : bit_vector(0 to 255) := x"900D919D918D96192DB32DA28799E091F41105B105A1970185BD85AC859B858A";
constant PM_Inst_RAM_Word4_INIT_0B : bit_vector(0 to 255) := x"2466245524442CC82CD92CEA2CFB87B883AF839E838D1DB11DA196012DA091BC";
constant PM_Inst_RAM_Word4_INIT_0C : bit_vector(0 to 255) := x"F008067B066A0659164885B485A3859285812DF32DE24F1F5F0F2F1D2F0C2477";
constant PM_Inst_RAM_Word4_INIT_0D : bit_vector(0 to 255) := x"E0B22CB12CA12C912E88E082F45005BF05AE059D158C85B881AF819E818DC0A8";
constant PM_Inst_RAM_Word4_INIT_0E : bit_vector(0 to 255) := x"F40923880F04940E2F312F202D4C2D5D2D6E2D7F2D932D822CF12CE12CD12ECB";
constant PM_Inst_RAM_Word4_INIT_0F : bit_vector(0 to 255) := x"05B105A197004F5F4F4F4F3F5F2F2D2C2D3D2D4E2D5F81BC81AB819A8189C088";
constant PM_Inst_RAM_Word4_INIT_10 : bit_vector(0 to 255) := x"0739172885BD85AC859B858A095B094A09391928C00D2EB52EA42E932E82F029";
constant PM_Inst_RAM_Word4_INIT_11 : bit_vector(0 to 255) := x"2D932D82CFA71CF11CE11CD11CC194081C711C611C511C419408F059075B074A";
constant PM_Inst_RAM_Word4_INIT_12 : bit_vector(0 to 255) := x"2C6E2C5D2C4CC04CF4E123880E5B940EE03FEF2FEF1FEF0F2D7F2D6E2D5D2D4C";
constant PM_Inst_RAM_Word4_INIT_13 : bit_vector(0 to 255) := x"2D0C2D1D2D2E2D3F2D442D552D662D772D932D82087108610851084194082C7F";
constant PM_Inst_RAM_Word4_INIT_14 : bit_vector(0 to 255) := x"914D85BF85AEF30004BF04AE049D148C2CC42CD52CE62CF7F1A923880E5B940E";
constant PM_Inst_RAM_Word4_INIT_15 : bit_vector(0 to 255) := x"0E5B940E2D082D192D2A2D3B2D932D82F0510571056105511541917C916D915D";
constant PM_Inst_RAM_Word4_INIT_16 : bit_vector(0 to 255) := x"1CB11CA11C911C819408F06123FF85F982B382A28291828085FF85EEF0B92388";
constant PM_Inst_RAM_Word4_INIT_17 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F962FE080C001E081971392BC92AD929D928D2DB32DA2";
constant PM_Inst_RAM_Word4_INIT_18 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF";
constant PM_Inst_RAM_Word4_INIT_19 : bit_vector(0 to 255) := x"9380E0B0E0A0E090E082032692100324921003219210032092109508902F903F";
constant PM_Inst_RAM_Word4_INIT_1A : bit_vector(0 to 255) := x"92100345938003469390E091E081033E9210032A93B0032993A0032893900327";
constant PM_Inst_RAM_Word4_INIT_1B : bit_vector(0 to 255) := x"9380E18A10059380E18910049380E18B95080365921003619380036293900349";
constant PM_Inst_RAM_Word4_INIT_1C : bit_vector(0 to 255) := x"1669940EE070E060E255E840E094E08B20109380E083037E9210037F92101006";
constant PM_Inst_RAM_Word4_INIT_1D : bit_vector(0 to 255) := x"E073E16BE093E287032F940EE14CE061E093E18B1895940EE070E660E094E08B";
constant PM_Inst_RAM_Word4_INIT_1E : bit_vector(0 to 255) := x"E073E267E093E4850D04940EE040E073E16BE093E287F43923880D04940EE041";
constant PM_Inst_RAM_Word4_INIT_1F : bit_vector(0 to 255) := x"E963E094E08BF03123880B3A940EE021E050E848E073E465E093E68107E3940E";
constant PM_Inst_RAM_Word4_INIT_20 : bit_vector(0 to 255) := x"E68120199380037D91800662940EE050E041E073E76DE093E6811895940EE070";
constant PM_Inst_RAM_Word4_INIT_21 : bit_vector(0 to 255) := x"E041E073E76DE093E68120189380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_22 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120179380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_23 : bit_vector(0 to 255) := x"E68120159380037D91800662940EE050E041E073E76DE093E68120169380037D";
constant PM_Inst_RAM_Word4_INIT_24 : bit_vector(0 to 255) := x"E041E073E76DE093E68120149380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_25 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120139380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_26 : bit_vector(0 to 255) := x"E68120219380037D91800662940EE050E041E073E76DE093E68120129380037D";
constant PM_Inst_RAM_Word4_INIT_27 : bit_vector(0 to 255) := x"E041E073E76DE093E68120209380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_28 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201F9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_29 : bit_vector(0 to 255) := x"E681201D9380037D91800662940EE050E041E073E76DE093E681201E9380037D";
constant PM_Inst_RAM_Word4_INIT_2A : bit_vector(0 to 255) := x"E041E073E76DE093E681201C9380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_2B : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201B9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_2C : bit_vector(0 to 255) := x"E68120299380037D91800662940EE050E041E073E76DE093E681201A9380037D";
constant PM_Inst_RAM_Word4_INIT_2D : bit_vector(0 to 255) := x"E041E073E76DE093E68120289380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_2E : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120279380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_2F : bit_vector(0 to 255) := x"E68120259380037D91800662940EE050E041E073E76DE093E68120269380037D";
constant PM_Inst_RAM_Word4_INIT_30 : bit_vector(0 to 255) := x"E041E073E76DE093E68120249380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_31 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120239380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_32 : bit_vector(0 to 255) := x"E68120319380037D91800662940EE050E041E073E76DE093E68120229380037D";
constant PM_Inst_RAM_Word4_INIT_33 : bit_vector(0 to 255) := x"E041E073E76DE093E68120309380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_34 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202F9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_35 : bit_vector(0 to 255) := x"E681202D9380037D91800662940EE050E041E073E76DE093E681202E9380037D";
constant PM_Inst_RAM_Word4_INIT_36 : bit_vector(0 to 255) := x"E041E073E76DE093E681202C9380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_37 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202B9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_38 : bit_vector(0 to 255) := x"E070EA65E094E08BF43031802F18931F95080573940EE093E681202A9380037D";
constant PM_Inst_RAM_Word4_INIT_39 : bit_vector(0 to 255) := x"972BB7DEB7CD93CF93DF9508911F1876940EE050E1402F61E094E08B1757940E";
constant PM_Inst_RAM_Word4_INIT_3A : bit_vector(0 to 255) := x"037E9210037F9210C175F0099706037F9190037E9180BFCDBE0FBFDE94F8B60F";
constant PM_Inst_RAM_Word4_INIT_3B : bit_vector(0 to 255) := x"2F5D2F4CE073E465E093E681F7E15081920D9001E08BE0F0E8E896112FBD2FAC";
constant PM_Inst_RAM_Word4_INIT_3C : bit_vector(0 to 255) := x"940EE093E681201891600AC1940EE093E681201991600B3A940EE5224F5F5F4F";
constant PM_Inst_RAM_Word4_INIT_3D : bit_vector(0 to 255) := x"E681201591600AC1940EE093E681201691600AC1940EE093E681201791600AC1";
constant PM_Inst_RAM_Word4_INIT_3E : bit_vector(0 to 255) := x"91600AC1940EE093E681201391600AC1940EE093E681201491600AC1940EE093";
constant PM_Inst_RAM_Word4_INIT_3F : bit_vector(0 to 255) := x"940EE093E681202091600AC1940EE093E681202191600AC1940EE093E6812012";
-- BRAM 0 in address space [0x00002800:0x00002FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word5 LOC = RAMB16_X0Y7;
constant PM_Inst_RAM_Word5_INIT_00 : bit_vector(0 to 255) := x"E681201D91600AC1940EE093E681201E91600AC1940EE093E681201F91600AC1";
constant PM_Inst_RAM_Word5_INIT_01 : bit_vector(0 to 255) := x"91600AC1940EE093E681201B91600AC1940EE093E681201C91600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_02 : bit_vector(0 to 255) := x"940EE093E681202891600AC1940EE093E681202991600AC1940EE093E681201A";
constant PM_Inst_RAM_Word5_INIT_03 : bit_vector(0 to 255) := x"E681202591600AC1940EE093E681202691600AC1940EE093E681202791600AC1";
constant PM_Inst_RAM_Word5_INIT_04 : bit_vector(0 to 255) := x"91600AC1940EE093E681202391600AC1940EE093E681202491600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_05 : bit_vector(0 to 255) := x"940EE093E681203091600AC1940EE093E681203191600AC1940EE093E6812022";
constant PM_Inst_RAM_Word5_INIT_06 : bit_vector(0 to 255) := x"E681202D91600AC1940EE093E681202E91600AC1940EE093E681202F91600AC1";
constant PM_Inst_RAM_Word5_INIT_07 : bit_vector(0 to 255) := x"91600AC1940EE093E681202B91600AC1940EE093E681202C91600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_08 : bit_vector(0 to 255) := x"91801388940E201A91801895940EE070EA67E094E08B0AC1940EE093E681202A";
constant PM_Inst_RAM_Word5_INIT_09 : bit_vector(0 to 255) := x"91801388940E201E91801388940E201D91801388940E201C91801388940E201B";
constant PM_Inst_RAM_Word5_INIT_0A : bit_vector(0 to 255) := x"940EE070EB6CE094E08B1388940E202191801388940E202091801388940E201F";
constant PM_Inst_RAM_Word5_INIT_0B : bit_vector(0 to 255) := x"940E201591801388940E201491801388940E201391801388940E201291801895";
constant PM_Inst_RAM_Word5_INIT_0C : bit_vector(0 to 255) := x"940E201991801388940E201891801388940E201791801388940E201691801388";
constant PM_Inst_RAM_Word5_INIT_0D : bit_vector(0 to 255) := x"91801388940E202B91801388940E202A91801895940EE070ED61E094E08B1388";
constant PM_Inst_RAM_Word5_INIT_0E : bit_vector(0 to 255) := x"91801388940E202F91801388940E202E91801388940E202D91801388940E202C";
constant PM_Inst_RAM_Word5_INIT_0F : bit_vector(0 to 255) := x"940E202291801895940EE070EE65E094E08B1388940E203191801388940E2030";
constant PM_Inst_RAM_Word5_INIT_10 : bit_vector(0 to 255) := x"940E202691801388940E202591801388940E202491801388940E202391801388";
constant PM_Inst_RAM_Word5_INIT_11 : bit_vector(0 to 255) := x"940EE093E6811388940E202991801388940E202891801388940E202791801388";
constant PM_Inst_RAM_Word5_INIT_12 : bit_vector(0 to 255) := x"1591940EE090E080E077ED60037E9380037F93909601037F9190037E91800573";
constant PM_Inst_RAM_Word5_INIT_13 : bit_vector(0 to 255) := x"933F932F2411920FB60F920F921F950891DF91CFBFCDBE0FBFDE94F8B60F962B";
constant PM_Inst_RAM_Word5_INIT_14 : bit_vector(0 to 255) := x"1DA1960103889130038791B0038691A0038591900384918093BF93AF939F938F";
constant PM_Inst_RAM_Word5_INIT_15 : bit_vector(0 to 255) := x"93A00385939003849380038893201DB11DA19601572DF020372D5F2D2F231DB1";
constant PM_Inst_RAM_Word5_INIT_16 : bit_vector(0 to 255) := x"038093801DB11DA19601038391B0038291A00381919003809180038793B00386";
constant PM_Inst_RAM_Word5_INIT_17 : bit_vector(0 to 255) := x"901F900FBE0F900F912F913F918F919F91AF91BF038393B0038293A003819390";
constant PM_Inst_RAM_Word5_INIT_18 : bit_vector(0 to 255) := x"2F952F842F732F62BF8F0387915003869140038591300384912094F8B78F9518";
constant PM_Inst_RAM_Word5_INIT_19 : bit_vector(0 to 255) := x"9160038591500384914094F8B78F2F192F082EF72EE6931F930F92FF92EF9508";
constant PM_Inst_RAM_Word5_INIT_1A : bit_vector(0 to 255) := x"1B84BF2F038791B0038691A0038591900384918094F8B72FBF8F038791700386";
constant PM_Inst_RAM_Word5_INIT_1B : bit_vector(0 to 255) := x"6084B7839478950890EF90FF910F911FF760071B070A06F916E80BB70BA60B95";
constant PM_Inst_RAM_Word5_INIT_1C : bit_vector(0 to 255) := x"BD856082B585BD8F6081B58FBD8E6081B58EBD8E6082B58EBF876081B787BF83";
constant PM_Inst_RAM_Word5_INIT_1D : bit_vector(0 to 255) := x"4F3F56262D9095C82FF92FE84F9F53862F932F82E0302F289508BD856081B585";
constant PM_Inst_RAM_Word5_INIT_1E : bit_vector(0 to 255) := x"95C896312DA095C84FFF59E01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE2";
constant PM_Inst_RAM_Word5_INIT_1F : bit_vector(0 to 255) := x"2F952F84E0502F489508938C2B89918C9508938C23899590918CF42923662DB0";
constant PM_Inst_RAM_Word5_INIT_20 : bit_vector(0 to 255) := x"4F5F56462D9095C82FF92FE84F9F53862F952F842D2095C82FF92FE84F9F5086";
constant PM_Inst_RAM_Word5_INIT_21 : bit_vector(0 to 255) := x"B58FF4213024C004778FB58FF4193023F0B12322F16923332D3095C82FF52FE4";
constant PM_Inst_RAM_Word5_INIT_22 : bit_vector(0 to 255) := x"E0F02FE3BD857D8FB585F4193025C005BF837D8FB783F4213021C00BBD8F7D8F";
constant PM_Inst_RAM_Word5_INIT_23 : bit_vector(0 to 255) := x"9508938C23899590918CF42923662DB095C896312DA095C84FFF58E21FFF0FEE";
constant PM_Inst_RAM_Word5_INIT_24 : bit_vector(0 to 255) := x"91E0B12C93FF93EF939F938F932F2411920FB60F920F921F9508938C2B89918C";
constant PM_Inst_RAM_Word5_INIT_25 : bit_vector(0 to 255) := x"91FF0409939083204FFC57E7E0F0F0311798040A918050E1779F2F9E5FEF0409";
constant PM_Inst_RAM_Word5_INIT_26 : bit_vector(0 to 255) := x"2F242F192F08931F930F92FF92EF9518901F900FBE0F900F912F918F919F91EF";
constant PM_Inst_RAM_Word5_INIT_27 : bit_vector(0 to 255) := x"502118E4940EE090E18EE874E860971590FC90ED96142FB92FA82F572F462F35";
constant PM_Inst_RAM_Word5_INIT_28 : bit_vector(0 to 255) := x"83202DFF2DEE18E4940EE050E040E030E0222F622F732F842F95405040404030";
constant PM_Inst_RAM_Word5_INIT_29 : bit_vector(0 to 255) := x"0F88C002971C900C961C2F952F84E050E0418120971791FC91ED96162FB12FA0";
constant PM_Inst_RAM_Word5_INIT_2A : bit_vector(0 to 255) := x"C002971D900C961D2F952F848120971791FC91ED961683202B28F7E2940A1F99";
constant PM_Inst_RAM_Word5_INIT_2B : bit_vector(0 to 255) := x"1F550F44C002900C961E8180971791FC91ED961683202B28F7E2940A1F990F88";
constant PM_Inst_RAM_Word5_INIT_2C : bit_vector(0 to 255) := x"E090918C852785B185A02FF92FE8950890EF90FF910F911F83802B84F7E2940A";
constant PM_Inst_RAM_Word5_INIT_2D : bit_vector(0 to 255) := x"9390E091E08B950883602DE085F38402CFF6FF80F7E2940A95879595C0022E02";
constant PM_Inst_RAM_Word5_INIT_2E : bit_vector(0 to 255) := x"E28A040F938004109390E090E289040D9380040E9390E093E889040B9380040C";
constant PM_Inst_RAM_Word5_INIT_2F : bit_vector(0 to 255) := x"938004169390E090E28C0413938004149390E090E28B0411938004129390E090";
constant PM_Inst_RAM_Word5_INIT_30 : bit_vector(0 to 255) := x"15BD940E9508041A9380E08504199380E08704189380E08304179380E0840415";
constant PM_Inst_RAM_Word5_INIT_31 : bit_vector(0 to 255) := x"2FA09621C00B2FD72FC62F192F0893DF93CF931F930FCFFD139B940E11B8940E";
constant PM_Inst_RAM_Word5_INIT_32 : bit_vector(0 to 255) := x"910F911F91CF91DFF7912366816895092F912F802DE081F0900191FC91ED2FB1";
constant PM_Inst_RAM_Word5_INIT_33 : bit_vector(0 to 255) := x"2DBF2DAEC0102FD52FC42EF72EE62F192F0893DF93CF931F930F92FF92EF9508";
constant PM_Inst_RAM_Word5_INIT_34 : bit_vector(0 to 255) := x"F7719720972195092F912F802DE081F0900191FC91ED2FB12FA02EFB2EEA916D";
constant PM_Inst_RAM_Word5_INIT_35 : bit_vector(0 to 255) := x"950895092DE081F3800291FC91ED2FB92FA8950890EF90FF910F911F91CF91DF";
constant PM_Inst_RAM_Word5_INIT_36 : bit_vector(0 to 255) := x"931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F";
constant PM_Inst_RAM_Word5_INIT_37 : bit_vector(0 to 255) := x"2EF72EE62ED52EC42E392E28BFCDBE0FBFDE94F8B60F97A0B7DEB7CD93CF93DF";
constant PM_Inst_RAM_Word5_INIT_38 : bit_vector(0 to 255) := x"24992488C06A1821940EE030E020E070E060E050E340F4490571056105511541";
constant PM_Inst_RAM_Word5_INIT_39 : bit_vector(0 to 255) := x"2D6C2D7D2D8E2D9F1D190D081F1D0F0CE010E0012477246624552E4224BB24AA";
constant PM_Inst_RAM_Word5_INIT_3A : bit_vector(0 to 255) := x"2D8E2D9F1CB11CA11C911C81940883602FF12FE018BD940E2D242D352D462D57";
constant PM_Inst_RAM_Word5_INIT_3B : bit_vector(0 to 255) := x"2EFB2EEA2ED92EC82FB52FA42F932F8218BD940E2D242D352D462D572D6C2D7D";
constant PM_Inst_RAM_Word5_INIT_3C : bit_vector(0 to 255) := x"1C6194082E7D2E6C1CF90CE81EFD0EEC2CF12EE8E081F68904F104E104D114C1";
constant PM_Inst_RAM_Word5_INIT_3D : bit_vector(0 to 255) := x"0DEE2DFD2DECC01808D918C82ED92EC809B109A197012D882D992DAA2DBB1C71";
constant PM_Inst_RAM_Word5_INIT_3E : bit_vector(0 to 255) := x"E030E0202D932D822F752F659550FD4727555C49C0015D40F410304A81401DFF";
constant PM_Inst_RAM_Word5_INIT_3F : bit_vector(0 to 255) := x"91DF91CFBFCDBE0FBFDE94F8B60F96A0F729047F146E08F108E194081821940E";
-- BRAM 0 in address space [0x00003000:0x000037FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word6 LOC = RAMB16_X0Y5;
constant PM_Inst_RAM_Word6_INIT_00 : bit_vector(0 to 255) := x"902F903F904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F";
constant PM_Inst_RAM_Word6_INIT_01 : bit_vector(0 to 255) := x"1760940E950895092F642DE081F0900191FC91EDF441053115212FB92FA89508";
constant PM_Inst_RAM_Word6_INIT_02 : bit_vector(0 to 255) := x"F441053115212F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF9508";
constant PM_Inst_RAM_Word6_INIT_03 : bit_vector(0 to 255) := x"E060E050E24DC010FF77F4C90531302AC01E95092F642DE081F0900181F981E8";
constant PM_Inst_RAM_Word6_INIT_04 : bit_vector(0 to 255) := x"2F712F9D2F8C1D111D011CF11CE194E094F0950095101821940EE030E020E070";
constant PM_Inst_RAM_Word6_INIT_05 : bit_vector(0 to 255) := x"2F08931F930F950890EF90FF910F911F91CF91DF1760940EE02A2D4E2D5F2F60";
constant PM_Inst_RAM_Word6_INIT_06 : bit_vector(0 to 255) := x"E020E070E060E050E04A2F912F801821940EE030E020E070E060E050E04D2F19";
constant PM_Inst_RAM_Word6_INIT_07 : bit_vector(0 to 255) := x"2F352F242F192F08931F930F92FF92EF92DF92CF9508910F911F1821940EE030";
constant PM_Inst_RAM_Word6_INIT_08 : bit_vector(0 to 255) := x"910F911F185D940E2F912F801811940E2D4C2D5D2D6E2D7F24FF24EE24DD2EC6";
constant PM_Inst_RAM_Word6_INIT_09 : bit_vector(0 to 255) := x"911F185D940E2F912F801757940E2F192F08931F930F950890CF90DF90EF90FF";
constant PM_Inst_RAM_Word6_INIT_0A : bit_vector(0 to 255) := x"1F551F441F330F221FF51FE41FB30FA2C004FF6027AA27BB27EE27FF9508910F";
constant PM_Inst_RAM_Word6_INIT_0B : bit_vector(0 to 255) := x"1BAA2E1AE2A195082F6A2F7B2F8E2F9FF77107769700F7899567957795879596";
constant PM_Inst_RAM_Word6_INIT_0C : bit_vector(0 to 255) := x"0BE40BB31BA2F02007F507E407B317A21FFF1FEE1FBB1FAAC00D2FFB2FEA1BBB";
constant PM_Inst_RAM_Word6_INIT_0D : bit_vector(0 to 255) := x"2F6A2F592F482F372F269590958095709560F769941A1F991F881F771F660BF5";
constant PM_Inst_RAM_Word6_INIT_0E : bit_vector(0 to 255) := x"95409550F4381C00D00ADFD2D004FD57D00E26052E09FB9795082F9F2F8E2F7B";
constant PM_Inst_RAM_Word6_INIT_0F : bit_vector(0 to 255) := x"0FEE95084F9F4F8F4F7F9561957095809590F7F695084F5F4F4F4F3F95219530";
constant PM_Inst_RAM_Word6_INIT_10 : bit_vector(0 to 255) := x"6944205241542073692073696854CFFF94F89508920F95C8920F963195C81FFF";
constant PM_Inst_RAM_Word6_INIT_11 : bit_vector(0 to 255) := x"50554B43414200656369766564207265746E756F63206C616E6769732065646F";
constant PM_Inst_RAM_Word6_INIT_12 : bit_vector(0 to 255) := x"632065746972570030005458542E50554B4341422064656E65704F005458542E";
constant PM_Inst_RAM_Word6_INIT_13 : bit_vector(0 to 255) := x"552D3770557265746E756F6320657469725700306E442D376E447265746E756F";
constant PM_Inst_RAM_Word6_INIT_14 : bit_vector(0 to 255) := x"63695420657469725700306E442D376E4472656B636954206574697257003070";
constant PM_Inst_RAM_Word6_INIT_15 : bit_vector(0 to 255) := x"1516C90000000017310AB20AC100000000FFFFFFFF003070552D37705572656B";
constant PM_Inst_RAM_Word6_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000173117";
constant PM_Inst_RAM_Word6_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
-- BRAM 0 in address space [0x00003800:0x00003FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word7 LOC = RAMB16_X0Y6;
constant PM_Inst_RAM_Word7_INIT_00 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_01 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_02 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_03 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_04 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_05 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_06 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_07 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_09 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_10 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_11 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_12 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_13 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_14 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_15 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
end prog_mem_init_pkg;
|
apache-2.0
|
rauenzi/VHDL-Communications
|
SPI_display.vhd
|
1
|
4598
|
----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/30/14
--Last Modified: 11/2/14
--
--Description: This takes in 16 bit data and displays them on an external display
-- using GPIO and SPI communication.
--
--Version: 1.1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SPI_display is
Generic (constant BoardClockSpeed : integer := 100000000;
constant SCKSpeed : integer := 250000);
Port ( BoardClock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
SCK : out STD_LOGIC;
SS : out STD_LOGIC;
MOSI : out STD_LOGIC
);
end SPI_display;
architecture Behavioral of SPI_display is
signal clkMax : integer := (BoardClockSpeed/SCKSpeed)-1;
signal clkCnt : integer := 0;
signal StateClock : std_logic :='0';
type state_type is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9,
state10,state11,state12,state13,state14,state15,state16,state17,state18);
signal currentState : state_type :=state0;
signal nextState : state_type;
signal dataSection : std_logic_vector(7 downto 0);
signal byteChoice: integer :=0;
signal byteMax: integer :=8;
begin
ClkEnable : process(BoardClock)
begin
if rising_edge(BoardClock) then
if clkCnt = clkMax then
StateClock <= '1';
clkCnt <= 0;
else
clkCnt<=clkCnt+1;
StateClock <= '0';
end if;
end if;
end process ClkEnable;
StateChange: process (BoardClock,StateClock)
begin
if (rising_edge(BoardClock) and StateClock='1') then
if currentState = state18 then
if byteChoice = byteMax then
byteChoice <= byteChoice-3;
else
byteChoice<=byteChoice+1;
end if;
end if;
currentState <= nextState;
end if;
end process StateChange;
States: process(currentState)
begin
case currentState is
when state0=>
SCK<='0';
SS<='1';
MOSI<='Z';
nextState<=state1;
when state1=>
SCK<='0';
SS<='0';
MOSI<=dataSection(7);
nextState<=state2;
when state2=>
SCK<='1';
SS<='0';
MOSI<=dataSection(7);
nextState<=state3;
when state3=>
SCK<='0';
SS<='0';
MOSI<=dataSection(6);
nextState<=state4;
when state4=>
SCK<='1';
SS<='0';
MOSI<=dataSection(6);
nextState<=state5;
when state5=>
SCK<='0';
SS<='0';
MOSI<=dataSection(5);
nextState<=state6;
when state6=>
SCK<='1';
SS<='0';
MOSI<=dataSection(5);
nextState<=state7;
when state7=>
SCK<='0';
SS<='0';
MOSI<=dataSection(4);
nextState<=state8;
when state8=>
SCK<='1';
SS<='0';
MOSI<=dataSection(4);
nextState<=state9;
when state9=>
SCK<='0';
SS<='0';
MOSI<=dataSection(3);
nextState<=state10;
when state10=>
SCK<='1';
SS<='0';
MOSI<=dataSection(3);
nextState<=state11;
when state11=>
SCK<='0';
SS<='0';
MOSI<=dataSection(2);
nextState<=state12;
when state12=>
SCK<='1';
SS<='0';
MOSI<=dataSection(2);
nextState<=state13;
when state13=>
SCK<='0';
SS<='0';
MOSI<=dataSection(1);
nextState<=state14;
when state14=>
SCK<='1';
SS<='0';
MOSI<=dataSection(1);
nextState<=state15;
when state15=>
SCK<='0';
SS<='0';
MOSI<=dataSection(0);
nextState<=state16;
when state16=>
SCK<='1';
SS<='0';
MOSI<=dataSection(0);
nextState<=state17;
when state17=>
SCK<='0';
SS<='0';
MOSI<=datasection(0);
nextState<=state18;
when state18=>
SCK<='0';
SS<='1';
MOSI<='Z';
nextState<=state1;
end case;
end process States;
ByteSelection: process(byteChoice)
begin
case byteChoice is
when 0 => dataSection<=x"76";
when 1 => dataSection<=x"76";
when 2 => dataSection<=x"76";
when 3 => dataSection<=x"76";
when 4 => dataSection<=x"76";
when 5 => dataSection <=x"0" & Data(15 downto 12);
when 6 => dataSection <=x"0" & Data(11 downto 8);
when 7 => dataSection <=x"0" & Data(7 downto 4);
when 8 => dataSection <=x"0" & Data(3 downto 0);
when others => dataSection <="11111111";
end case;
end process ByteSelection;
end Behavioral;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AtomGodilVideo/src/MC6847/mc6847t1_ntsc_plus_keith.vhd
|
1
|
74344
|
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity mc6847t1_ntsc_plus_keith is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of mc6847t1_ntsc_plus_keith is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"00";
when x"001" => DATA <= x"00";
when x"002" => DATA <= x"38";
when x"003" => DATA <= x"44";
when x"004" => DATA <= x"04";
when x"005" => DATA <= x"34";
when x"006" => DATA <= x"4C";
when x"007" => DATA <= x"4C";
when x"008" => DATA <= x"38";
when x"009" => DATA <= x"00";
when x"00A" => DATA <= x"00";
when x"00B" => DATA <= x"00";
when x"00C" => DATA <= x"00";
when x"00D" => DATA <= x"00";
when x"00E" => DATA <= x"00";
when x"00F" => DATA <= x"00";
when x"010" => DATA <= x"00";
when x"011" => DATA <= x"00";
when x"012" => DATA <= x"10";
when x"013" => DATA <= x"28";
when x"014" => DATA <= x"44";
when x"015" => DATA <= x"44";
when x"016" => DATA <= x"7C";
when x"017" => DATA <= x"44";
when x"018" => DATA <= x"44";
when x"019" => DATA <= x"00";
when x"01A" => DATA <= x"00";
when x"01B" => DATA <= x"00";
when x"01C" => DATA <= x"00";
when x"01D" => DATA <= x"00";
when x"01E" => DATA <= x"00";
when x"01F" => DATA <= x"00";
when x"020" => DATA <= x"00";
when x"021" => DATA <= x"00";
when x"022" => DATA <= x"78";
when x"023" => DATA <= x"24";
when x"024" => DATA <= x"24";
when x"025" => DATA <= x"38";
when x"026" => DATA <= x"24";
when x"027" => DATA <= x"24";
when x"028" => DATA <= x"78";
when x"029" => DATA <= x"00";
when x"02A" => DATA <= x"00";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"00";
when x"02D" => DATA <= x"00";
when x"02E" => DATA <= x"00";
when x"02F" => DATA <= x"00";
when x"030" => DATA <= x"00";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"38";
when x"033" => DATA <= x"44";
when x"034" => DATA <= x"40";
when x"035" => DATA <= x"40";
when x"036" => DATA <= x"40";
when x"037" => DATA <= x"44";
when x"038" => DATA <= x"38";
when x"039" => DATA <= x"00";
when x"03A" => DATA <= x"00";
when x"03B" => DATA <= x"00";
when x"03C" => DATA <= x"00";
when x"03D" => DATA <= x"00";
when x"03E" => DATA <= x"00";
when x"03F" => DATA <= x"00";
when x"040" => DATA <= x"00";
when x"041" => DATA <= x"00";
when x"042" => DATA <= x"78";
when x"043" => DATA <= x"24";
when x"044" => DATA <= x"24";
when x"045" => DATA <= x"24";
when x"046" => DATA <= x"24";
when x"047" => DATA <= x"24";
when x"048" => DATA <= x"78";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"00";
when x"04C" => DATA <= x"00";
when x"04D" => DATA <= x"00";
when x"04E" => DATA <= x"00";
when x"04F" => DATA <= x"00";
when x"050" => DATA <= x"00";
when x"051" => DATA <= x"00";
when x"052" => DATA <= x"7C";
when x"053" => DATA <= x"40";
when x"054" => DATA <= x"40";
when x"055" => DATA <= x"70";
when x"056" => DATA <= x"40";
when x"057" => DATA <= x"40";
when x"058" => DATA <= x"7C";
when x"059" => DATA <= x"00";
when x"05A" => DATA <= x"00";
when x"05B" => DATA <= x"00";
when x"05C" => DATA <= x"00";
when x"05D" => DATA <= x"00";
when x"05E" => DATA <= x"00";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"00";
when x"061" => DATA <= x"00";
when x"062" => DATA <= x"7C";
when x"063" => DATA <= x"40";
when x"064" => DATA <= x"40";
when x"065" => DATA <= x"70";
when x"066" => DATA <= x"40";
when x"067" => DATA <= x"40";
when x"068" => DATA <= x"40";
when x"069" => DATA <= x"00";
when x"06A" => DATA <= x"00";
when x"06B" => DATA <= x"00";
when x"06C" => DATA <= x"00";
when x"06D" => DATA <= x"00";
when x"06E" => DATA <= x"00";
when x"06F" => DATA <= x"00";
when x"070" => DATA <= x"00";
when x"071" => DATA <= x"00";
when x"072" => DATA <= x"38";
when x"073" => DATA <= x"44";
when x"074" => DATA <= x"40";
when x"075" => DATA <= x"40";
when x"076" => DATA <= x"4C";
when x"077" => DATA <= x"44";
when x"078" => DATA <= x"38";
when x"079" => DATA <= x"00";
when x"07A" => DATA <= x"00";
when x"07B" => DATA <= x"00";
when x"07C" => DATA <= x"00";
when x"07D" => DATA <= x"00";
when x"07E" => DATA <= x"00";
when x"07F" => DATA <= x"00";
when x"080" => DATA <= x"00";
when x"081" => DATA <= x"00";
when x"082" => DATA <= x"44";
when x"083" => DATA <= x"44";
when x"084" => DATA <= x"44";
when x"085" => DATA <= x"7C";
when x"086" => DATA <= x"44";
when x"087" => DATA <= x"44";
when x"088" => DATA <= x"44";
when x"089" => DATA <= x"00";
when x"08A" => DATA <= x"00";
when x"08B" => DATA <= x"00";
when x"08C" => DATA <= x"00";
when x"08D" => DATA <= x"00";
when x"08E" => DATA <= x"00";
when x"08F" => DATA <= x"00";
when x"090" => DATA <= x"00";
when x"091" => DATA <= x"00";
when x"092" => DATA <= x"38";
when x"093" => DATA <= x"10";
when x"094" => DATA <= x"10";
when x"095" => DATA <= x"10";
when x"096" => DATA <= x"10";
when x"097" => DATA <= x"10";
when x"098" => DATA <= x"38";
when x"099" => DATA <= x"00";
when x"09A" => DATA <= x"00";
when x"09B" => DATA <= x"00";
when x"09C" => DATA <= x"00";
when x"09D" => DATA <= x"00";
when x"09E" => DATA <= x"00";
when x"09F" => DATA <= x"00";
when x"0A0" => DATA <= x"00";
when x"0A1" => DATA <= x"00";
when x"0A2" => DATA <= x"04";
when x"0A3" => DATA <= x"04";
when x"0A4" => DATA <= x"04";
when x"0A5" => DATA <= x"04";
when x"0A6" => DATA <= x"04";
when x"0A7" => DATA <= x"44";
when x"0A8" => DATA <= x"38";
when x"0A9" => DATA <= x"00";
when x"0AA" => DATA <= x"00";
when x"0AB" => DATA <= x"00";
when x"0AC" => DATA <= x"00";
when x"0AD" => DATA <= x"00";
when x"0AE" => DATA <= x"00";
when x"0AF" => DATA <= x"00";
when x"0B0" => DATA <= x"00";
when x"0B1" => DATA <= x"00";
when x"0B2" => DATA <= x"44";
when x"0B3" => DATA <= x"48";
when x"0B4" => DATA <= x"50";
when x"0B5" => DATA <= x"60";
when x"0B6" => DATA <= x"50";
when x"0B7" => DATA <= x"48";
when x"0B8" => DATA <= x"44";
when x"0B9" => DATA <= x"00";
when x"0BA" => DATA <= x"00";
when x"0BB" => DATA <= x"00";
when x"0BC" => DATA <= x"00";
when x"0BD" => DATA <= x"00";
when x"0BE" => DATA <= x"00";
when x"0BF" => DATA <= x"00";
when x"0C0" => DATA <= x"00";
when x"0C1" => DATA <= x"00";
when x"0C2" => DATA <= x"40";
when x"0C3" => DATA <= x"40";
when x"0C4" => DATA <= x"40";
when x"0C5" => DATA <= x"40";
when x"0C6" => DATA <= x"40";
when x"0C7" => DATA <= x"40";
when x"0C8" => DATA <= x"7C";
when x"0C9" => DATA <= x"00";
when x"0CA" => DATA <= x"00";
when x"0CB" => DATA <= x"00";
when x"0CC" => DATA <= x"00";
when x"0CD" => DATA <= x"00";
when x"0CE" => DATA <= x"00";
when x"0CF" => DATA <= x"00";
when x"0D0" => DATA <= x"00";
when x"0D1" => DATA <= x"00";
when x"0D2" => DATA <= x"44";
when x"0D3" => DATA <= x"6C";
when x"0D4" => DATA <= x"54";
when x"0D5" => DATA <= x"54";
when x"0D6" => DATA <= x"44";
when x"0D7" => DATA <= x"44";
when x"0D8" => DATA <= x"44";
when x"0D9" => DATA <= x"00";
when x"0DA" => DATA <= x"00";
when x"0DB" => DATA <= x"00";
when x"0DC" => DATA <= x"00";
when x"0DD" => DATA <= x"00";
when x"0DE" => DATA <= x"00";
when x"0DF" => DATA <= x"00";
when x"0E0" => DATA <= x"00";
when x"0E1" => DATA <= x"00";
when x"0E2" => DATA <= x"44";
when x"0E3" => DATA <= x"44";
when x"0E4" => DATA <= x"64";
when x"0E5" => DATA <= x"54";
when x"0E6" => DATA <= x"4C";
when x"0E7" => DATA <= x"44";
when x"0E8" => DATA <= x"44";
when x"0E9" => DATA <= x"00";
when x"0EA" => DATA <= x"00";
when x"0EB" => DATA <= x"00";
when x"0EC" => DATA <= x"00";
when x"0ED" => DATA <= x"00";
when x"0EE" => DATA <= x"00";
when x"0EF" => DATA <= x"00";
when x"0F0" => DATA <= x"00";
when x"0F1" => DATA <= x"00";
when x"0F2" => DATA <= x"38";
when x"0F3" => DATA <= x"44";
when x"0F4" => DATA <= x"44";
when x"0F5" => DATA <= x"44";
when x"0F6" => DATA <= x"44";
when x"0F7" => DATA <= x"44";
when x"0F8" => DATA <= x"38";
when x"0F9" => DATA <= x"00";
when x"0FA" => DATA <= x"00";
when x"0FB" => DATA <= x"00";
when x"0FC" => DATA <= x"00";
when x"0FD" => DATA <= x"00";
when x"0FE" => DATA <= x"00";
when x"0FF" => DATA <= x"00";
when x"100" => DATA <= x"00";
when x"101" => DATA <= x"00";
when x"102" => DATA <= x"78";
when x"103" => DATA <= x"44";
when x"104" => DATA <= x"44";
when x"105" => DATA <= x"78";
when x"106" => DATA <= x"40";
when x"107" => DATA <= x"40";
when x"108" => DATA <= x"40";
when x"109" => DATA <= x"00";
when x"10A" => DATA <= x"00";
when x"10B" => DATA <= x"00";
when x"10C" => DATA <= x"00";
when x"10D" => DATA <= x"00";
when x"10E" => DATA <= x"00";
when x"10F" => DATA <= x"00";
when x"110" => DATA <= x"00";
when x"111" => DATA <= x"00";
when x"112" => DATA <= x"38";
when x"113" => DATA <= x"44";
when x"114" => DATA <= x"44";
when x"115" => DATA <= x"44";
when x"116" => DATA <= x"54";
when x"117" => DATA <= x"48";
when x"118" => DATA <= x"34";
when x"119" => DATA <= x"00";
when x"11A" => DATA <= x"00";
when x"11B" => DATA <= x"00";
when x"11C" => DATA <= x"00";
when x"11D" => DATA <= x"00";
when x"11E" => DATA <= x"00";
when x"11F" => DATA <= x"00";
when x"120" => DATA <= x"00";
when x"121" => DATA <= x"00";
when x"122" => DATA <= x"78";
when x"123" => DATA <= x"44";
when x"124" => DATA <= x"44";
when x"125" => DATA <= x"78";
when x"126" => DATA <= x"50";
when x"127" => DATA <= x"48";
when x"128" => DATA <= x"44";
when x"129" => DATA <= x"00";
when x"12A" => DATA <= x"00";
when x"12B" => DATA <= x"00";
when x"12C" => DATA <= x"00";
when x"12D" => DATA <= x"00";
when x"12E" => DATA <= x"00";
when x"12F" => DATA <= x"00";
when x"130" => DATA <= x"00";
when x"131" => DATA <= x"00";
when x"132" => DATA <= x"38";
when x"133" => DATA <= x"44";
when x"134" => DATA <= x"40";
when x"135" => DATA <= x"38";
when x"136" => DATA <= x"04";
when x"137" => DATA <= x"44";
when x"138" => DATA <= x"38";
when x"139" => DATA <= x"00";
when x"13A" => DATA <= x"00";
when x"13B" => DATA <= x"00";
when x"13C" => DATA <= x"00";
when x"13D" => DATA <= x"00";
when x"13E" => DATA <= x"00";
when x"13F" => DATA <= x"00";
when x"140" => DATA <= x"00";
when x"141" => DATA <= x"00";
when x"142" => DATA <= x"7C";
when x"143" => DATA <= x"10";
when x"144" => DATA <= x"10";
when x"145" => DATA <= x"10";
when x"146" => DATA <= x"10";
when x"147" => DATA <= x"10";
when x"148" => DATA <= x"10";
when x"149" => DATA <= x"00";
when x"14A" => DATA <= x"00";
when x"14B" => DATA <= x"00";
when x"14C" => DATA <= x"00";
when x"14D" => DATA <= x"00";
when x"14E" => DATA <= x"00";
when x"14F" => DATA <= x"00";
when x"150" => DATA <= x"00";
when x"151" => DATA <= x"00";
when x"152" => DATA <= x"44";
when x"153" => DATA <= x"44";
when x"154" => DATA <= x"44";
when x"155" => DATA <= x"44";
when x"156" => DATA <= x"44";
when x"157" => DATA <= x"44";
when x"158" => DATA <= x"38";
when x"159" => DATA <= x"00";
when x"15A" => DATA <= x"00";
when x"15B" => DATA <= x"00";
when x"15C" => DATA <= x"00";
when x"15D" => DATA <= x"00";
when x"15E" => DATA <= x"00";
when x"15F" => DATA <= x"00";
when x"160" => DATA <= x"00";
when x"161" => DATA <= x"00";
when x"162" => DATA <= x"44";
when x"163" => DATA <= x"44";
when x"164" => DATA <= x"44";
when x"165" => DATA <= x"28";
when x"166" => DATA <= x"28";
when x"167" => DATA <= x"10";
when x"168" => DATA <= x"10";
when x"169" => DATA <= x"00";
when x"16A" => DATA <= x"00";
when x"16B" => DATA <= x"00";
when x"16C" => DATA <= x"00";
when x"16D" => DATA <= x"00";
when x"16E" => DATA <= x"00";
when x"16F" => DATA <= x"00";
when x"170" => DATA <= x"00";
when x"171" => DATA <= x"00";
when x"172" => DATA <= x"44";
when x"173" => DATA <= x"44";
when x"174" => DATA <= x"44";
when x"175" => DATA <= x"44";
when x"176" => DATA <= x"54";
when x"177" => DATA <= x"6C";
when x"178" => DATA <= x"44";
when x"179" => DATA <= x"00";
when x"17A" => DATA <= x"00";
when x"17B" => DATA <= x"00";
when x"17C" => DATA <= x"00";
when x"17D" => DATA <= x"00";
when x"17E" => DATA <= x"00";
when x"17F" => DATA <= x"00";
when x"180" => DATA <= x"00";
when x"181" => DATA <= x"00";
when x"182" => DATA <= x"44";
when x"183" => DATA <= x"44";
when x"184" => DATA <= x"28";
when x"185" => DATA <= x"10";
when x"186" => DATA <= x"28";
when x"187" => DATA <= x"44";
when x"188" => DATA <= x"44";
when x"189" => DATA <= x"00";
when x"18A" => DATA <= x"00";
when x"18B" => DATA <= x"00";
when x"18C" => DATA <= x"00";
when x"18D" => DATA <= x"00";
when x"18E" => DATA <= x"00";
when x"18F" => DATA <= x"00";
when x"190" => DATA <= x"00";
when x"191" => DATA <= x"00";
when x"192" => DATA <= x"44";
when x"193" => DATA <= x"44";
when x"194" => DATA <= x"28";
when x"195" => DATA <= x"10";
when x"196" => DATA <= x"10";
when x"197" => DATA <= x"10";
when x"198" => DATA <= x"10";
when x"199" => DATA <= x"00";
when x"19A" => DATA <= x"00";
when x"19B" => DATA <= x"00";
when x"19C" => DATA <= x"00";
when x"19D" => DATA <= x"00";
when x"19E" => DATA <= x"00";
when x"19F" => DATA <= x"00";
when x"1A0" => DATA <= x"00";
when x"1A1" => DATA <= x"00";
when x"1A2" => DATA <= x"7C";
when x"1A3" => DATA <= x"04";
when x"1A4" => DATA <= x"08";
when x"1A5" => DATA <= x"10";
when x"1A6" => DATA <= x"20";
when x"1A7" => DATA <= x"40";
when x"1A8" => DATA <= x"7C";
when x"1A9" => DATA <= x"00";
when x"1AA" => DATA <= x"00";
when x"1AB" => DATA <= x"00";
when x"1AC" => DATA <= x"00";
when x"1AD" => DATA <= x"00";
when x"1AE" => DATA <= x"00";
when x"1AF" => DATA <= x"00";
when x"1B0" => DATA <= x"00";
when x"1B1" => DATA <= x"00";
when x"1B2" => DATA <= x"38";
when x"1B3" => DATA <= x"20";
when x"1B4" => DATA <= x"20";
when x"1B5" => DATA <= x"20";
when x"1B6" => DATA <= x"20";
when x"1B7" => DATA <= x"20";
when x"1B8" => DATA <= x"38";
when x"1B9" => DATA <= x"00";
when x"1BA" => DATA <= x"00";
when x"1BB" => DATA <= x"00";
when x"1BC" => DATA <= x"00";
when x"1BD" => DATA <= x"00";
when x"1BE" => DATA <= x"00";
when x"1BF" => DATA <= x"00";
when x"1C0" => DATA <= x"00";
when x"1C1" => DATA <= x"00";
when x"1C2" => DATA <= x"00";
when x"1C3" => DATA <= x"40";
when x"1C4" => DATA <= x"20";
when x"1C5" => DATA <= x"10";
when x"1C6" => DATA <= x"08";
when x"1C7" => DATA <= x"04";
when x"1C8" => DATA <= x"00";
when x"1C9" => DATA <= x"00";
when x"1CA" => DATA <= x"00";
when x"1CB" => DATA <= x"00";
when x"1CC" => DATA <= x"00";
when x"1CD" => DATA <= x"00";
when x"1CE" => DATA <= x"00";
when x"1CF" => DATA <= x"00";
when x"1D0" => DATA <= x"00";
when x"1D1" => DATA <= x"00";
when x"1D2" => DATA <= x"38";
when x"1D3" => DATA <= x"08";
when x"1D4" => DATA <= x"08";
when x"1D5" => DATA <= x"08";
when x"1D6" => DATA <= x"08";
when x"1D7" => DATA <= x"08";
when x"1D8" => DATA <= x"38";
when x"1D9" => DATA <= x"00";
when x"1DA" => DATA <= x"00";
when x"1DB" => DATA <= x"00";
when x"1DC" => DATA <= x"00";
when x"1DD" => DATA <= x"00";
when x"1DE" => DATA <= x"00";
when x"1DF" => DATA <= x"00";
when x"1E0" => DATA <= x"00";
when x"1E1" => DATA <= x"00";
when x"1E2" => DATA <= x"10";
when x"1E3" => DATA <= x"38";
when x"1E4" => DATA <= x"54";
when x"1E5" => DATA <= x"10";
when x"1E6" => DATA <= x"10";
when x"1E7" => DATA <= x"10";
when x"1E8" => DATA <= x"10";
when x"1E9" => DATA <= x"00";
when x"1EA" => DATA <= x"00";
when x"1EB" => DATA <= x"00";
when x"1EC" => DATA <= x"00";
when x"1ED" => DATA <= x"00";
when x"1EE" => DATA <= x"00";
when x"1EF" => DATA <= x"00";
when x"1F0" => DATA <= x"00";
when x"1F1" => DATA <= x"00";
when x"1F2" => DATA <= x"00";
when x"1F3" => DATA <= x"10";
when x"1F4" => DATA <= x"20";
when x"1F5" => DATA <= x"7C";
when x"1F6" => DATA <= x"20";
when x"1F7" => DATA <= x"10";
when x"1F8" => DATA <= x"00";
when x"1F9" => DATA <= x"00";
when x"1FA" => DATA <= x"00";
when x"1FB" => DATA <= x"00";
when x"1FC" => DATA <= x"00";
when x"1FD" => DATA <= x"00";
when x"1FE" => DATA <= x"00";
when x"1FF" => DATA <= x"00";
when x"200" => DATA <= x"00";
when x"201" => DATA <= x"00";
when x"202" => DATA <= x"00";
when x"203" => DATA <= x"00";
when x"204" => DATA <= x"00";
when x"205" => DATA <= x"00";
when x"206" => DATA <= x"00";
when x"207" => DATA <= x"00";
when x"208" => DATA <= x"00";
when x"209" => DATA <= x"00";
when x"20A" => DATA <= x"00";
when x"20B" => DATA <= x"00";
when x"20C" => DATA <= x"00";
when x"20D" => DATA <= x"00";
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when x"655" => DATA <= x"08";
when x"656" => DATA <= x"3E";
when x"657" => DATA <= x"08";
when x"658" => DATA <= x"3E";
when x"659" => DATA <= x"08";
when x"65A" => DATA <= x"00";
when x"65B" => DATA <= x"00";
when x"65C" => DATA <= x"00";
when x"65D" => DATA <= x"00";
when x"65E" => DATA <= x"00";
when x"65F" => DATA <= x"00";
when x"660" => DATA <= x"00";
when x"661" => DATA <= x"00";
when x"662" => DATA <= x"00";
when x"663" => DATA <= x"08";
when x"664" => DATA <= x"08";
when x"665" => DATA <= x"08";
when x"666" => DATA <= x"00";
when x"667" => DATA <= x"08";
when x"668" => DATA <= x"08";
when x"669" => DATA <= x"08";
when x"66A" => DATA <= x"00";
when x"66B" => DATA <= x"00";
when x"66C" => DATA <= x"00";
when x"66D" => DATA <= x"00";
when x"66E" => DATA <= x"00";
when x"66F" => DATA <= x"00";
when x"670" => DATA <= x"00";
when x"671" => DATA <= x"00";
when x"672" => DATA <= x"00";
when x"673" => DATA <= x"1C";
when x"674" => DATA <= x"20";
when x"675" => DATA <= x"1C";
when x"676" => DATA <= x"22";
when x"677" => DATA <= x"1C";
when x"678" => DATA <= x"02";
when x"679" => DATA <= x"1C";
when x"67A" => DATA <= x"00";
when x"67B" => DATA <= x"00";
when x"67C" => DATA <= x"00";
when x"67D" => DATA <= x"00";
when x"67E" => DATA <= x"00";
when x"67F" => DATA <= x"00";
when x"680" => DATA <= x"14";
when x"681" => DATA <= x"14";
when x"682" => DATA <= x"00";
when x"683" => DATA <= x"00";
when x"684" => DATA <= x"00";
when x"685" => DATA <= x"00";
when x"686" => DATA <= x"00";
when x"687" => DATA <= x"00";
when x"688" => DATA <= x"00";
when x"689" => DATA <= x"00";
when x"68A" => DATA <= x"00";
when x"68B" => DATA <= x"00";
when x"68C" => DATA <= x"00";
when x"68D" => DATA <= x"00";
when x"68E" => DATA <= x"00";
when x"68F" => DATA <= x"00";
when x"690" => DATA <= x"00";
when x"691" => DATA <= x"00";
when x"692" => DATA <= x"3E";
when x"693" => DATA <= x"41";
when x"694" => DATA <= x"5D";
when x"695" => DATA <= x"51";
when x"696" => DATA <= x"51";
when x"697" => DATA <= x"5D";
when x"698" => DATA <= x"41";
when x"699" => DATA <= x"3E";
when x"69A" => DATA <= x"00";
when x"69B" => DATA <= x"00";
when x"69C" => DATA <= x"00";
when x"69D" => DATA <= x"00";
when x"69E" => DATA <= x"00";
when x"69F" => DATA <= x"00";
when x"6A0" => DATA <= x"00";
when x"6A1" => DATA <= x"00";
when x"6A2" => DATA <= x"00";
when x"6A3" => DATA <= x"1C";
when x"6A4" => DATA <= x"02";
when x"6A5" => DATA <= x"1E";
when x"6A6" => DATA <= x"22";
when x"6A7" => DATA <= x"1E";
when x"6A8" => DATA <= x"00";
when x"6A9" => DATA <= x"00";
when x"6AA" => DATA <= x"00";
when x"6AB" => DATA <= x"00";
when x"6AC" => DATA <= x"00";
when x"6AD" => DATA <= x"00";
when x"6AE" => DATA <= x"00";
when x"6AF" => DATA <= x"00";
when x"6B0" => DATA <= x"00";
when x"6B1" => DATA <= x"00";
when x"6B2" => DATA <= x"00";
when x"6B3" => DATA <= x"00";
when x"6B4" => DATA <= x"0A";
when x"6B5" => DATA <= x"14";
when x"6B6" => DATA <= x"28";
when x"6B7" => DATA <= x"14";
when x"6B8" => DATA <= x"0A";
when x"6B9" => DATA <= x"00";
when x"6BA" => DATA <= x"00";
when x"6BB" => DATA <= x"00";
when x"6BC" => DATA <= x"00";
when x"6BD" => DATA <= x"00";
when x"6BE" => DATA <= x"00";
when x"6BF" => DATA <= x"00";
when x"6C0" => DATA <= x"00";
when x"6C1" => DATA <= x"00";
when x"6C2" => DATA <= x"00";
when x"6C3" => DATA <= x"00";
when x"6C4" => DATA <= x"00";
when x"6C5" => DATA <= x"00";
when x"6C6" => DATA <= x"3E";
when x"6C7" => DATA <= x"02";
when x"6C8" => DATA <= x"02";
when x"6C9" => DATA <= x"00";
when x"6CA" => DATA <= x"00";
when x"6CB" => DATA <= x"00";
when x"6CC" => DATA <= x"00";
when x"6CD" => DATA <= x"00";
when x"6CE" => DATA <= x"00";
when x"6CF" => DATA <= x"00";
when x"6D0" => DATA <= x"00";
when x"6D1" => DATA <= x"00";
when x"6D2" => DATA <= x"00";
when x"6D3" => DATA <= x"00";
when x"6D4" => DATA <= x"00";
when x"6D5" => DATA <= x"00";
when x"6D6" => DATA <= x"3E";
when x"6D7" => DATA <= x"00";
when x"6D8" => DATA <= x"00";
when x"6D9" => DATA <= x"00";
when x"6DA" => DATA <= x"00";
when x"6DB" => DATA <= x"00";
when x"6DC" => DATA <= x"00";
when x"6DD" => DATA <= x"00";
when x"6DE" => DATA <= x"00";
when x"6DF" => DATA <= x"00";
when x"6E0" => DATA <= x"00";
when x"6E1" => DATA <= x"00";
when x"6E2" => DATA <= x"3E";
when x"6E3" => DATA <= x"41";
when x"6E4" => DATA <= x"5D";
when x"6E5" => DATA <= x"55";
when x"6E6" => DATA <= x"59";
when x"6E7" => DATA <= x"55";
when x"6E8" => DATA <= x"41";
when x"6E9" => DATA <= x"3E";
when x"6EA" => DATA <= x"00";
when x"6EB" => DATA <= x"00";
when x"6EC" => DATA <= x"00";
when x"6ED" => DATA <= x"00";
when x"6EE" => DATA <= x"00";
when x"6EF" => DATA <= x"00";
when x"6F0" => DATA <= x"00";
when x"6F1" => DATA <= x"00";
when x"6F2" => DATA <= x"00";
when x"6F3" => DATA <= x"7E";
when x"6F4" => DATA <= x"00";
when x"6F5" => DATA <= x"00";
when x"6F6" => DATA <= x"00";
when x"6F7" => DATA <= x"00";
when x"6F8" => DATA <= x"00";
when x"6F9" => DATA <= x"00";
when x"6FA" => DATA <= x"00";
when x"6FB" => DATA <= x"00";
when x"6FC" => DATA <= x"00";
when x"6FD" => DATA <= x"00";
when x"6FE" => DATA <= x"00";
when x"6FF" => DATA <= x"00";
when x"700" => DATA <= x"00";
when x"701" => DATA <= x"00";
when x"702" => DATA <= x"00";
when x"703" => DATA <= x"10";
when x"704" => DATA <= x"28";
when x"705" => DATA <= x"10";
when x"706" => DATA <= x"00";
when x"707" => DATA <= x"00";
when x"708" => DATA <= x"00";
when x"709" => DATA <= x"00";
when x"70A" => DATA <= x"00";
when x"70B" => DATA <= x"00";
when x"70C" => DATA <= x"00";
when x"70D" => DATA <= x"00";
when x"70E" => DATA <= x"00";
when x"70F" => DATA <= x"00";
when x"710" => DATA <= x"00";
when x"711" => DATA <= x"00";
when x"712" => DATA <= x"08";
when x"713" => DATA <= x"08";
when x"714" => DATA <= x"3E";
when x"715" => DATA <= x"08";
when x"716" => DATA <= x"08";
when x"717" => DATA <= x"00";
when x"718" => DATA <= x"3E";
when x"719" => DATA <= x"00";
when x"71A" => DATA <= x"00";
when x"71B" => DATA <= x"00";
when x"71C" => DATA <= x"00";
when x"71D" => DATA <= x"00";
when x"71E" => DATA <= x"00";
when x"71F" => DATA <= x"00";
when x"720" => DATA <= x"00";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"00";
when x"723" => DATA <= x"18";
when x"724" => DATA <= x"04";
when x"725" => DATA <= x"08";
when x"726" => DATA <= x"10";
when x"727" => DATA <= x"1C";
when x"728" => DATA <= x"00";
when x"729" => DATA <= x"00";
when x"72A" => DATA <= x"00";
when x"72B" => DATA <= x"00";
when x"72C" => DATA <= x"00";
when x"72D" => DATA <= x"00";
when x"72E" => DATA <= x"00";
when x"72F" => DATA <= x"00";
when x"730" => DATA <= x"00";
when x"731" => DATA <= x"00";
when x"732" => DATA <= x"00";
when x"733" => DATA <= x"18";
when x"734" => DATA <= x"04";
when x"735" => DATA <= x"18";
when x"736" => DATA <= x"04";
when x"737" => DATA <= x"18";
when x"738" => DATA <= x"00";
when x"739" => DATA <= x"00";
when x"73A" => DATA <= x"00";
when x"73B" => DATA <= x"00";
when x"73C" => DATA <= x"00";
when x"73D" => DATA <= x"00";
when x"73E" => DATA <= x"00";
when x"73F" => DATA <= x"00";
when x"740" => DATA <= x"04";
when x"741" => DATA <= x"08";
when x"742" => DATA <= x"00";
when x"743" => DATA <= x"00";
when x"744" => DATA <= x"00";
when x"745" => DATA <= x"00";
when x"746" => DATA <= x"00";
when x"747" => DATA <= x"00";
when x"748" => DATA <= x"00";
when x"749" => DATA <= x"00";
when x"74A" => DATA <= x"00";
when x"74B" => DATA <= x"00";
when x"74C" => DATA <= x"00";
when x"74D" => DATA <= x"00";
when x"74E" => DATA <= x"00";
when x"74F" => DATA <= x"00";
when x"750" => DATA <= x"00";
when x"751" => DATA <= x"00";
when x"752" => DATA <= x"00";
when x"753" => DATA <= x"00";
when x"754" => DATA <= x"00";
when x"755" => DATA <= x"12";
when x"756" => DATA <= x"12";
when x"757" => DATA <= x"12";
when x"758" => DATA <= x"12";
when x"759" => DATA <= x"1C";
when x"75A" => DATA <= x"10";
when x"75B" => DATA <= x"20";
when x"75C" => DATA <= x"00";
when x"75D" => DATA <= x"00";
when x"75E" => DATA <= x"00";
when x"75F" => DATA <= x"00";
when x"760" => DATA <= x"00";
when x"761" => DATA <= x"00";
when x"762" => DATA <= x"00";
when x"763" => DATA <= x"1A";
when x"764" => DATA <= x"2A";
when x"765" => DATA <= x"2A";
when x"766" => DATA <= x"1A";
when x"767" => DATA <= x"0A";
when x"768" => DATA <= x"0A";
when x"769" => DATA <= x"0A";
when x"76A" => DATA <= x"00";
when x"76B" => DATA <= x"00";
when x"76C" => DATA <= x"00";
when x"76D" => DATA <= x"00";
when x"76E" => DATA <= x"00";
when x"76F" => DATA <= x"00";
when x"770" => DATA <= x"00";
when x"771" => DATA <= x"00";
when x"772" => DATA <= x"00";
when x"773" => DATA <= x"00";
when x"774" => DATA <= x"00";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"18";
when x"777" => DATA <= x"18";
when x"778" => DATA <= x"00";
when x"779" => DATA <= x"00";
when x"77A" => DATA <= x"00";
when x"77B" => DATA <= x"00";
when x"77C" => DATA <= x"00";
when x"77D" => DATA <= x"00";
when x"77E" => DATA <= x"00";
when x"77F" => DATA <= x"00";
when x"780" => DATA <= x"00";
when x"781" => DATA <= x"00";
when x"782" => DATA <= x"00";
when x"783" => DATA <= x"00";
when x"784" => DATA <= x"00";
when x"785" => DATA <= x"00";
when x"786" => DATA <= x"00";
when x"787" => DATA <= x"00";
when x"788" => DATA <= x"00";
when x"789" => DATA <= x"00";
when x"78A" => DATA <= x"04";
when x"78B" => DATA <= x"18";
when x"78C" => DATA <= x"00";
when x"78D" => DATA <= x"00";
when x"78E" => DATA <= x"00";
when x"78F" => DATA <= x"00";
when x"790" => DATA <= x"00";
when x"791" => DATA <= x"00";
when x"792" => DATA <= x"00";
when x"793" => DATA <= x"08";
when x"794" => DATA <= x"18";
when x"795" => DATA <= x"08";
when x"796" => DATA <= x"08";
when x"797" => DATA <= x"1C";
when x"798" => DATA <= x"00";
when x"799" => DATA <= x"00";
when x"79A" => DATA <= x"00";
when x"79B" => DATA <= x"00";
when x"79C" => DATA <= x"00";
when x"79D" => DATA <= x"00";
when x"79E" => DATA <= x"00";
when x"79F" => DATA <= x"00";
when x"7A0" => DATA <= x"00";
when x"7A1" => DATA <= x"00";
when x"7A2" => DATA <= x"00";
when x"7A3" => DATA <= x"1C";
when x"7A4" => DATA <= x"22";
when x"7A5" => DATA <= x"22";
when x"7A6" => DATA <= x"22";
when x"7A7" => DATA <= x"1C";
when x"7A8" => DATA <= x"00";
when x"7A9" => DATA <= x"00";
when x"7AA" => DATA <= x"00";
when x"7AB" => DATA <= x"00";
when x"7AC" => DATA <= x"00";
when x"7AD" => DATA <= x"00";
when x"7AE" => DATA <= x"00";
when x"7AF" => DATA <= x"00";
when x"7B0" => DATA <= x"00";
when x"7B1" => DATA <= x"00";
when x"7B2" => DATA <= x"00";
when x"7B3" => DATA <= x"00";
when x"7B4" => DATA <= x"28";
when x"7B5" => DATA <= x"14";
when x"7B6" => DATA <= x"0A";
when x"7B7" => DATA <= x"14";
when x"7B8" => DATA <= x"28";
when x"7B9" => DATA <= x"00";
when x"7BA" => DATA <= x"00";
when x"7BB" => DATA <= x"00";
when x"7BC" => DATA <= x"00";
when x"7BD" => DATA <= x"00";
when x"7BE" => DATA <= x"00";
when x"7BF" => DATA <= x"00";
when x"7C0" => DATA <= x"00";
when x"7C1" => DATA <= x"00";
when x"7C2" => DATA <= x"00";
when x"7C3" => DATA <= x"20";
when x"7C4" => DATA <= x"20";
when x"7C5" => DATA <= x"20";
when x"7C6" => DATA <= x"22";
when x"7C7" => DATA <= x"06";
when x"7C8" => DATA <= x"0E";
when x"7C9" => DATA <= x"02";
when x"7CA" => DATA <= x"00";
when x"7CB" => DATA <= x"00";
when x"7CC" => DATA <= x"00";
when x"7CD" => DATA <= x"00";
when x"7CE" => DATA <= x"00";
when x"7CF" => DATA <= x"00";
when x"7D0" => DATA <= x"00";
when x"7D1" => DATA <= x"00";
when x"7D2" => DATA <= x"00";
when x"7D3" => DATA <= x"20";
when x"7D4" => DATA <= x"20";
when x"7D5" => DATA <= x"20";
when x"7D6" => DATA <= x"2E";
when x"7D7" => DATA <= x"02";
when x"7D8" => DATA <= x"04";
when x"7D9" => DATA <= x"0E";
when x"7DA" => DATA <= x"00";
when x"7DB" => DATA <= x"00";
when x"7DC" => DATA <= x"00";
when x"7DD" => DATA <= x"00";
when x"7DE" => DATA <= x"00";
when x"7DF" => DATA <= x"00";
when x"7E0" => DATA <= x"00";
when x"7E1" => DATA <= x"00";
when x"7E2" => DATA <= x"00";
when x"7E3" => DATA <= x"70";
when x"7E4" => DATA <= x"10";
when x"7E5" => DATA <= x"70";
when x"7E6" => DATA <= x"12";
when x"7E7" => DATA <= x"76";
when x"7E8" => DATA <= x"0E";
when x"7E9" => DATA <= x"02";
when x"7EA" => DATA <= x"00";
when x"7EB" => DATA <= x"00";
when x"7EC" => DATA <= x"00";
when x"7ED" => DATA <= x"00";
when x"7EE" => DATA <= x"00";
when x"7EF" => DATA <= x"00";
when x"7F0" => DATA <= x"00";
when x"7F1" => DATA <= x"00";
when x"7F2" => DATA <= x"00";
when x"7F3" => DATA <= x"08";
when x"7F4" => DATA <= x"00";
when x"7F5" => DATA <= x"08";
when x"7F6" => DATA <= x"08";
when x"7F7" => DATA <= x"10";
when x"7F8" => DATA <= x"12";
when x"7F9" => DATA <= x"0C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
apache-2.0
|
fafaldo/ethernet
|
ethernet4b/tx_test.vhd
|
1
|
4027
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:28:24 08/16/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/git/ethernet/ethernet4b/tx_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: new_tx_fifo_control_unit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tx_test IS
END tx_test;
ARCHITECTURE behavior OF tx_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT new_tx_fifo_control_unit
PORT(
clkA : OUT std_logic;
clkB : OUT std_logic;
enA : OUT std_logic;
enB : OUT std_logic;
weB : OUT std_logic;
addrA : OUT std_logic_vector(11 downto 0);
addrB : OUT std_logic_vector(10 downto 0);
diB : OUT std_logic_vector(7 downto 0);
doA : IN std_logic_vector(3 downto 0);
empty : OUT std_logic;
full : OUT std_logic;
data_in : IN std_logic_vector(7 downto 0);
EOF : IN std_logic;
clk : IN std_logic;
Tx_Clk : IN std_logic;
Tx_En : OUT std_logic;
Tx_D : OUT std_logic_vector(3 downto 0);
PUSH : IN std_logic;
busy : OUT std_logic;
start : IN std_logic;
test : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal doA : std_logic_vector(3 downto 0) := (others => '0');
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal EOF : std_logic := '0';
signal clk : std_logic := '0';
signal Tx_Clk : std_logic := '0';
signal PUSH : std_logic := '0';
signal start : std_logic := '0';
--Outputs
signal clkA : std_logic;
signal clkB : std_logic;
signal enA : std_logic;
signal enB : std_logic;
signal weB : std_logic;
signal addrA : std_logic_vector(11 downto 0);
signal addrB : std_logic_vector(10 downto 0);
signal diB : std_logic_vector(7 downto 0);
signal empty : std_logic;
signal full : std_logic;
signal Tx_En : std_logic;
signal Tx_D : std_logic_vector(3 downto 0);
signal busy : std_logic;
signal test : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
constant Tx_Clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: new_tx_fifo_control_unit PORT MAP (
clkA => clkA,
clkB => clkB,
enA => enA,
enB => enB,
weB => weB,
addrA => addrA,
addrB => addrB,
diB => diB,
doA => doA,
empty => empty,
full => full,
data_in => data_in,
EOF => EOF,
clk => clk,
Tx_Clk => Tx_Clk,
Tx_En => Tx_En,
Tx_D => Tx_D,
PUSH => PUSH,
busy => busy,
start => start,
test => test
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
Tx_Clk_process :process
begin
Tx_Clk <= '0';
wait for Tx_Clk_period/2;
Tx_Clk <= '1';
wait for Tx_Clk_period/2;
end process;
start <= '0', '1' after 70 ns, '0' after 90 ns;
END;
|
apache-2.0
|
fafaldo/ethernet
|
ethernet4b/smi_divider_test.vhd
|
1
|
1952
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:10:19 03/04/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet/smi_divider_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SMI_divider
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY smi_divider_test IS
END smi_divider_test;
ARCHITECTURE behavior OF smi_divider_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SMI_divider
PORT(
clk_in : IN std_logic;
clk_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_in : std_logic := '0';
--Outputs
signal clk_out : std_logic;
-- Clock period definitions
constant clk_in_period : time := 10 ns;
constant clk_out_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SMI_divider PORT MAP (
clk_in => clk_in,
clk_out => clk_out
);
-- Clock process definitions
clk_in_process :process
begin
clk_in <= '0';
wait for clk_in_period/2;
clk_in <= '1';
wait for clk_in_period/2;
end process;
END;
|
apache-2.0
|
fafaldo/ethernet
|
ethernet4b/ipcore_dir/blk_mem_gen_v7_3/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
apache-2.0
|
fafaldo/ethernet
|
ethernet4b/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd
|
1
|
10454
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 4
-- C_READ_WIDTH_A : 4
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 2048
-- C_READ_DEPTH_B : 2048
-- C_ADDRB_WIDTH : 11
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 1
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ENB => ENB,
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
apache-2.0
|
fafaldo/ethernet
|
ethernet4b/MII_RX_v2_test1.vhd
|
1
|
3758
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:39:29 06/19/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/git/ethernet/ethernet4b/MII_RX_v2_test1.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MII_RX_v2
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MII_RX_v2_test1 IS
END MII_RX_v2_test1;
ARCHITECTURE behavior OF MII_RX_v2_test1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MII_RX_v2
PORT(
clkA : IN std_logic;
clkB : IN std_logic;
enA : IN std_logic;
enB : IN std_logic;
weA : IN std_logic;
weB : IN std_logic;
addrA : IN std_logic_vector(11 downto 0);
addrB : IN std_logic_vector(10 downto 0);
diA : IN std_logic_vector(3 downto 0);
diB : IN std_logic_vector(7 downto 0);
doA : OUT std_logic_vector(3 downto 0);
doB : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clkA : std_logic := '0';
signal clkB : std_logic := '0';
signal enA : std_logic := '0';
signal enB : std_logic := '0';
signal weA : std_logic := '0';
signal weB : std_logic := '0';
signal addrA : std_logic_vector(11 downto 0) := (others => '0');
signal addrB : std_logic_vector(10 downto 0) := (others => '0');
signal diA : std_logic_vector(3 downto 0) := (others => '0');
signal diB : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal doA : std_logic_vector(3 downto 0);
signal doB : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clkA_period : time := 100 ns;
constant clkB_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MII_RX_v2 PORT MAP (
clkA => clkA,
clkB => clkB,
enA => enA,
enB => enB,
weA => weA,
weB => weB,
addrA => addrA,
addrB => addrB,
diA => diA,
diB => diB,
doA => doA,
doB => doB
);
-- Clock process definitions
clkA_process :process
begin
clkA <= '0';
wait for clkA_period/2;
clkA <= '1';
wait for clkA_period/2;
end process;
clkB_process :process
begin
clkB <= '0';
wait for clkB_period/2;
clkB <= '1';
wait for clkB_period/2;
end process;
enA <= '1';
weA <= '0', '1' after 50 ns, '0' after 650 ns;
addrA <= "000000000000", "000000000001" after 150 ns, "000000000010" after 250 ns, "000000000011" after 350 ns, "000000000100" after 450 ns, "000000000101" after 550 ns;
diA <= "0000", "0001" after 150 ns, "0010" after 250 ns, "0011" after 350 ns, "0100" after 450 ns, "0101" after 550 ns;
enB <= '0', '1' after 350 ns;
addrB <= "00000000000", "00000000001" after 750 ns, "00000000010" after 850 ns, "00000000011" after 950 ns, "00000000100" after 1050 ns, "00000000101" after 1150 ns;
END;
|
apache-2.0
|
fafaldo/ethernet
|
ethernet4b/new_tx_frame_buffer.vhd
|
1
|
9465
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity new_tx_frame_buffer is
port(
DOA : out std_logic_vector(3 downto 0); -- Port A 4-bit Data Output
DOB : out std_logic_vector(7 downto 0); -- Port B 8-bit Data Output
DOPB : out std_logic_vector(0 downto 0); -- Port B 1-bit Parity Output
ADDRA : in std_logic_vector(11 downto 0); -- Port A 12-bit Address Input
ADDRB : in std_logic_vector(10 downto 0); -- Port B 11-bit Address Input
CLKA : in std_logic; -- Port A Clock
CLKB : in std_logic; -- Port B Clock
DIA : in std_logic_vector(3 downto 0); -- Port A 4-bit Data Input
DIB : in std_logic_vector(7 downto 0); -- Port B 8-bit Data Input
DIPB : in std_logic_vector(0 downto 0); -- Port-B 1-bit parity Input
ENA : in std_logic; -- Port A RAM Enable Input
ENB : in std_logic; -- PortB RAM Enable Input
SSRA : in std_logic; -- Port A Synchronous Set/Reset Input
SSRB : in std_logic; -- Port B Synchronous Set/Reset Input
WEA : in std_logic; -- Port A Write Enable Input
WEB : in std_logic -- Port B Write Enable Input
);
end new_tx_frame_buffer;
architecture Behavioral of new_tx_frame_buffer is
begin
RAMB16_S4_S9_inst : RAMB16_S4_S9
generic map (
INIT_A => X"0", -- Value of output RAM registers on Port A at startup
INIT_B => X"000", -- Value of output RAM registers on Port B at startup
SRVAL_A => X"0", -- Port A output value upon SSR assertion
SRVAL_B => X"000", -- Port B output value upon SSR assertion
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
-- The following INIT_xx declarations specify the initial contents of the RAM
-- Port A Address 0 to 1023, Port B Address 0 to 511
INIT_00 => X"00084500111111110000e200004040003093fc20e7ff11115555555d55555555",
INIT_01 => X"0000edde00000000fddedeeddeed45bf00000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"000000000000000000000000000000000000000000000000da8315e000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 1024 to 2047, Port B Address 512 to 1023
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 2048 to 3071, Port B Address 1024 to 1535
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 3072 to 4095, Port B Address 1536 to 2047
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Port B Address 0 to 511
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port B Address 512 to 1023
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port B Address 1024 to 1535
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port B Address 1536 to 2047
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => DOA, -- Port A 4-bit Data Output
DOB => DOB, -- Port B 8-bit Data Output
DOPB => DOPB, -- Port B 1-bit Parity Output
ADDRA => ADDRA, -- Port A 12-bit Address Input
ADDRB => ADDRB, -- Port B 11-bit Address Input
CLKA => CLKA, -- Port A Clock
CLKB => CLKB, -- Port B Clock
DIA => DIA, -- Port A 4-bit Data Input
DIB => DIB, -- Port B 8-bit Data Input
DIPB => DIPB, -- Port-B 1-bit parity Input
ENA => ENA, -- Port A RAM Enable Input
ENB => ENB, -- PortB RAM Enable Input
SSRA => SSRA, -- Port A Synchronous Set/Reset Input
SSRB => SSRB, -- Port B Synchronous Set/Reset Input
WEA => WEA, -- Port A Write Enable Input
WEB => WEB -- Port B Write Enable Input
);
end Behavioral;
|
apache-2.0
|
fafaldo/ethernet
|
ethernet4b/ICMP_detector.vhd
|
1
|
1595
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ICMP_detector is
port( data_in : in std_logic_vector(7 downto 0);
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
ICMP_detected : out std_logic := '0';
test : out std_logic_vector(7 downto 0) := (others=>'0')
);
end ICMP_detector;
architecture Behavioral of ICMP_detector is
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
signal saved : std_logic := '0';
signal test_i : std_logic_vector(7 downto 0) := (others=>'0');
signal reset_counter : std_logic_vector(7 downto 0) := (others=>'0');
begin
test <= reset_counter;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif enable = '1' then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
ICMP_detected <= '0';
elsif enable = '1' and address_counter = 25 and data_in = x"01" then
ICMP_detected <= '1';
saved <= '1';
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
reset_counter <= reset_counter+1;
end if;
end if;
end process;
end Behavioral;
|
apache-2.0
|
willtmwu/vhdlExamples
|
Basic Logic/test_and2gate.vhd
|
1
|
2299
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:21 08/06/2014
-- Design Name:
-- Module Name: C:/Xilinx/14.7/workspace/prac1_beta/test_and2gate.vhd
-- Project Name: prac1_beta
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: and2gate
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY test_and2gate IS
END test_and2gate;
ARCHITECTURE behavior OF test_and2gate IS
COMPONENT and2gate
PORT(
in1 : IN std_logic;
in2 : IN std_logic;
outAnd : OUT std_logic
);
END COMPONENT;
signal inputs : std_logic_vector(1 downto 0) := "00";
signal outAnd : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: and2gate PORT MAP (
in1 => inputs(0),
in2 => inputs(1),
outAnd => outAnd
);
input_gen : process
begin
inputs <= "00";
--this loop will walk the truth table for the and gate
for I in 1 to 4 loop
wait for 100ps;
if (inputs = "00") then
assert (outAnd = '0') report "bad gate - stuck at 1" severity error;
elsif (inputs = "10") then
assert (outAnd = '0') report "bad gate - stuck at 1 " severity error;
elsif (inputs = "01") then
assert (outAnd = '0') report "bad gate- stuck at 1" severity error;
elsif (inputs = "11") then
assert (outAnd = '1') report "bad gate - stuck at 0" severity error ;
end if;
inputs <= inputs + '1';
end loop;
wait;
end process;
END;
|
apache-2.0
|
willtmwu/vhdlExamples
|
BCD Adder/Simple/hardware_interface.vhd
|
1
|
3915
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component bcd_2_adder port (
Carry_in : in std_logic;
Carry_out : out std_logic;
Adig0: in STD_LOGIC_VECTOR (3 downto 0);
Adig1: in STD_LOGIC_VECTOR (3 downto 0);
Bdig0: in STD_LOGIC_VECTOR (3 downto 0);
Bdig1: in STD_LOGIC_VECTOR (3 downto 0);
Sdig0: out STD_LOGIC_VECTOR (3 downto 0);
Sdig1: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
signal clockScalers : std_logic_vector (26 downto 0);
signal masterReset : std_logic;
signal displayKey : std_logic_vector(15 downto 0);
signal digit5 : std_logic_vector(3 downto 0);
signal digit6 : std_logic_vector(3 downto 0);
signal digit7 : std_logic_vector(3 downto 0);
signal digit8 : std_logic_vector(3 downto 0);
signal buttonA : std_logic;
signal buttonB : std_logic;
signal inA0 : std_logic_vector(3 downto 0);
signal inA1 : std_logic_vector(3 downto 0);
signal inB0 : std_logic_vector(3 downto 0);
signal inB1 : std_logic_vector(3 downto 0);
signal carry_bit : std_logic;
signal mode_selector : std_logic_vector(1 downto 0);
BEGIN
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayKey (3 downto 0),
digit2_p => displayKey (7 downto 4),
digit3_p => displayKey (11 downto 8),
digit4_p => displayKey (15 downto 12),
digit5_p => digit5,
digit6_p => digit6,
digit7_p => digit7,
digit8_p => digit8
);
u2 : bcd_2_adder port map (carry_bit, digit7(0), inA0, inA1, inB0, inB1, digit5, digit6);
LEDs (15 downto 0) <= clockScalers(26 downto 11);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
buttonA <= pushButtons(0);
buttonB <= pushButtons(1);
masterReset <= pushButtons(2);
mode_selector <= slideSwitches(15 downto 14);
carry_bit <= slideSwitches(13);
inA0 <= slideSwitches (3 downto 0) when (buttonA'event and buttonA = '1');
inA1 <= slideSwitches (7 downto 4) when (buttonA'event and buttonA = '1');
inB0 <= slideSwitches (3 downto 0) when (buttonB'event and buttonB = '1');
inB1 <= slideSwitches (7 downto 4) when (buttonB'event and buttonB = '1');
displayKey(3 downto 0) <= inA0;
displayKey(7 downto 4) <= inA1;
displayKey(11 downto 8) <= inB0;
displayKey(15 downto 12) <= inB1;
with mode_selector select
logic_analyzer(3 downto 0) <= inA0 when "01",
inB0 when "10",
digit5 when "11";
with mode_selector select
logic_analyzer(7 downto 4) <= inA1 when "01",
inB1 when "10",
digit6 when "11";
end Behavioral;
|
apache-2.0
|
mattaw/SoCFoundationFlow
|
admin/waf/waf-1.8.14/playground/xilinx-ise/src/top.vhd
|
5
|
663
|
--+-------------------------------------------------------------------------------------------------+
--|
--| VHDL example for waf build automation tool
--|
--+-------------------------------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity waf_demo is
port (
-- buttons
BUTTON_1 : in std_logic;
BUTTON_2 : in std_logic;
-- leds
DLED_2 : out std_logic;
DLED_3 : out std_logic;
DLED_4 : out std_logic;
DLED_5 : out std_logic
);
end waf_demo;
architecture inside of waf_demo is
begin
DLED_5 <= '1';
DLED_4 <= BUTTON_2;
DLED_3 <= '0';
DLED_2 <= not BUTTON_1;
end inside;
|
apache-2.0
|
willtmwu/vhdlExamples
|
Finite State Machines/test_fsm_prac4.vhd
|
1
|
2281
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_fsm_prac4 IS
END test_fsm_prac4;
ARCHITECTURE behavior OF test_fsm_prac4 IS
COMPONENT fsm_prac4
PORT(
X : IN std_logic;
RESET : IN std_logic;
clk100mhz : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
signal X : std_logic := '0';
signal RESET : std_logic := '0';
signal clk100mhz : std_logic := '0';
signal Z : std_logic;
signal check_data_line : std_logic_vector (15 downto 0) := "0110110100011100";
signal check_data_match : std_logic_vector (15 downto 0) := "0000011011000000";
signal check_state_trans : std_logic_vector (19 downto 0) := "11010011101100011010";
constant clk100mhz_period : time := 10 ns;
signal full_check_state : std_logic_vector(31 downto 0) := (others => '0');
subtype counter_bit_int is integer range 0 to 31;
BEGIN
full_check_state(31 downto 16) <= check_data_line;
full_check_state(15 downto 0) <= check_data_match;
uut: fsm_prac4 PORT MAP (
X => X,
RESET => RESET,
clk100mhz => clk100mhz,
Z => Z
);
-- Clock process definitions
clk100mhz_process :process
begin
clk100mhz <= '0';
wait for clk100mhz_period/2;
clk100mhz <= '1';
wait for clk100mhz_period/2;
end process;
RESET <= '1';
-- Stimulus process
stim_proc: process
begin
RESET <= '0' ;
wait for clk100mhz_period*10;
RESET <= '1' ;
wait for clk100mhz_period*10;
FOR I in 19 downto 0 loop
wait until clk100mhz'event;
if clk100mhz = '1' then
X <= check_state_trans(I);
end if;
--assert ( Z = check_data_match(I) ) report "MATCH ERROR" severity error;
END loop;
wait until clk100mhz'event and clk100mhz = '1';
wait for clk100mhz_period*10;
wait;
end process;
-- tester : process (clk100mHz)
-- variable counter : counter_bit_int := 0;
-- begin
-- --wait until submitButton'event and submitButton = '1' ;
-- if (clk100mhz'event and clk100mhz = '1') then
-- if (counter >= 0) then
-- X <= full_check_state(counter);
-- counter := counter - 1;
-- else
-- counter := 31;
-- end if;
-- end if;
-- end process;
END;
|
apache-2.0
|
vaisup/uvmprimer
|
10_An_Object_Oriented_Testbench/tinyalu_dut/single_cycle_add_and_xor.vhd
|
24
|
3045
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
apache-2.0
|
vaisup/uvmprimer
|
16_Analysis_Ports_In_the_Testbench/tinyalu_dut/single_cycle_add_and_xor.vhd
|
24
|
3045
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
apache-2.0
|
google/myelin-acorn-electron-hardware
|
standalone_cartridge_programmer/cpld/tristate_everything.vhd
|
1
|
1502
|
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity standalone_programmer is
Port (
-- cartridge address
cart_nINFC,
cart_nINFD,
cart_ROMQA : out std_logic;
cart_A : out std_logic_vector (13 downto 0);
-- cartridge data
cart_D : inout std_logic_vector(7 downto 0);
-- cartridge clock and memory control
cart_PHI0,
cart_16MHZ,
cart_RnW,
cart_nOE,
cart_nOE2 : out std_logic;
-- avr SPI signals
avr_MOSI,
avr_SCK,
cpld_SS : in std_logic;
avr_MISO : out std_logic
);
end standalone_programmer;
architecture Behavioural of standalone_programmer is
begin
cart_nINFC <= 'Z';
cart_nINFD <= 'Z';
cart_ROMQA <= 'Z';
cart_A <= "ZZZZZZZZZZZZZZ";
cart_D <= "ZZZZZZZZ";
cart_PHI0 <= 'Z';
cart_16MHZ <= 'Z';
cart_RnW <= 'Z';
cart_nOE <= 'Z';
cart_nOE2 <= 'Z';
avr_MISO <= 'Z';
end Behavioural;
|
apache-2.0
|
marzoul/PoC
|
src/mem/ocrom/ocrom_sp.vhdl
|
2
|
4542
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Single-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating single-port read-only memory
--
-- - single clock, clock enable
-- - 1 read port
--
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocrom_sp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end entity;
architecture rtl of ocrom_sp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates single-port memory as expected.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type rom_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return rom_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : rom_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
constant rom : rom_t := ocram_ReadMemFile(FILENAME);
signal a_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
a_reg <= a;
end if;
end if;
end process;
q <= rom(to_integer(a_reg)); -- gets new data
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
assert FALSE report "Do you really want to generate a block of zeros?" severity FAILURE;
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_sp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0));
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_sp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk => clk,
ce => ce,
we => '0',
a => a,
d => (others => '0'),
q => q
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
apache-2.0
|
marzoul/PoC
|
src/io/ddrio/ddrio.pkg.vhdl
|
2
|
3249
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and
-- functions associated to the PoC.io.ddrio namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
package ddrio is
component ddrio_in is
generic (
INIT_VALUES : BIT_VECTOR := ('1', '1');
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
i : in std_logic_vector(WIDTH-1 downto 0);
dh : out std_logic_vector(WIDTH-1 downto 0);
dl : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component ddrio_out is
generic (
NO_OE : boolean := false;
INIT_VALUE : BIT := '1';
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
dh : in std_logic_vector(WIDTH-1 downto 0);
dl : in std_logic_vector(WIDTH-1 downto 0);
oe : in std_logic;
q : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component ddrio_in_xilinx is
generic (
INIT_VALUES : BIT_VECTOR := ('1', '1');
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
i : in std_logic_vector(WIDTH-1 downto 0);
dh : out std_logic_vector(WIDTH-1 downto 0);
dl : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component ddrio_out_xilinx is
generic (
NO_OE : boolean := false;
INIT_VALUE : BIT := '1';
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
dh : in std_logic_vector(WIDTH-1 downto 0);
dl : in std_logic_vector(WIDTH-1 downto 0);
oe : in std_logic;
q : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component ddrio_out_altera is
generic (
INIT_VALUE : BIT := '1';
WIDTH : positive
);
port (
clk : in std_logic;
ce : in std_logic;
dh : in std_logic_vector(WIDTH-1 downto 0);
dl : in std_logic_vector(WIDTH-1 downto 0);
oe : in std_logic;
q : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
end package;
|
apache-2.0
|
marzoul/PoC
|
src/io/io_TimingCounter.vhdl
|
2
|
3254
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: optimized down-counter to control timings for low speed signals
--
-- Description:
-- ------------------------------------
-- This down-counter can be configured with a TIMING_TABLE (a ROM), from which
-- the initial counter value is loaded. The table index can be selected by
-- 'Slot'. 'Timeout' is a registered output. Up to 16 values fit into one ROM
-- consisting of 'log2ceilnz(imax(TIMING_TABLE)) + 1' 6-input LUTs.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.my_config.all;
use PoC.utils.all;
entity io_TimingCounter is
generic (
TIMING_TABLE : T_NATVEC -- timing table
);
port (
Clock : in STD_LOGIC; -- clock
Enable : in STD_LOGIC; -- enable counter
Load : in STD_LOGIC; -- load Timing Value from TIMING_TABLE selected by slot
Slot : in NATURAL range 0 to (TIMING_TABLE'length - 1); --
Timeout : out STD_LOGIC -- timing reached
);
end;
architecture rtl of io_TimingCounter is
function transform(vec : T_NATVEC) return T_INTVEC is
variable Result : T_INTVEC(vec'range);
begin
assert (not MY_VERBOSE) report "TIMING_TABLE (transformed):" severity NOTE;
for i in vec'range loop
Result(I) := vec(I) - 1;
assert (not MY_VERBOSE) report " " & INTEGER'image(I) & " - " & INTEGER'image(Result(I)) severity NOTE;
end loop;
return Result;
end;
constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE);
constant TIMING_MAX : NATURAL := imax(TIMING_TABLE2);
constant COUNTER_BITS : NATURAL := log2ceilnz(TIMING_MAX + 1);
signal Counter_s : SIGNED(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1);
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Load = '1') then
Counter_s <= to_signed(TIMING_TABLE2(Slot), Counter_s'length);
elsif ((Enable = '1') and (Counter_s(Counter_s'high) = '0')) then
Counter_s <= Counter_s - 1;
end if;
end if;
end process;
timeout <= Counter_s(Counter_s'high);
end;
|
apache-2.0
|
marzoul/PoC
|
src/common/strings.vhdl
|
1
|
30077
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- to_digit*
function to_digit_bin(chr : character) return integer;
function to_digit_oct(chr : character) return integer;
function to_digit_dec(chr : character) return integer;
function to_digit_hex(chr : character) return integer;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return integer is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return integer is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return integer is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return integer is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
|
apache-2.0
|
marzoul/PoC
|
src/mem/ocram/ocram_esdp.vhdl
|
2
|
7572
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Enhanced simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating enhanced simple dual-port memory, with:
--
-- * dual clock, clock enable,
-- * 1 read/write port (1st port) plus 1 read port (2nd port).
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- * Same-Port Read-During Write:
-- At rising edge of "clk1", data "d1" written to port 1 (ce1 and we1 = '1')
-- is directly passed to the output "q1". This is also known as write-first
-- mode or read-through write behavior.
--
-- * Mixed-Port Read-During Write:
-- Here, the Altera M512/M4K TriMatrix memory (as found e.g. in Stratix
-- and Stratix II FPGAs) defines the minimum time after which the written data
-- at port 1 can be read-out at port 2 again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d1" written at the rising-edge of "clk1" at address
-- "a1" can be read-out at the 2nd port from the same address with the
-- 2nd rising-edge of "clk2" following the falling-edge of "clk1".
-- If the rising-edge of "clk2" coincides with the falling-edge of "clk1"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "clk2" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_esdp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end ocram_esdp;
architecture rtl of ocram_esdp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates extended simple dual-port
-- memory as expected.
-- RAM can be inferred correctly only for newer FPGAs!
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- gets new data
process (clk2)
begin -- process
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
-- read data is unknown, when reading at write address
q2 <= ram(to_integer(a2_reg));
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
signal a1_reg : unsigned(A_BITS-1 downto 0);
signal a2_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk1)
begin
if rising_edge(clk1) then
if ce1 = '1' then
if we1 = '1' then
ram(to_integer(a1)) <= d1;
end if;
a1_reg <= a1;
end if;
end if;
end process;
q1 <= ram(to_integer(a1_reg)); -- gets new data
process (clk2)
begin -- process
if rising_edge(clk2) then
if ce2 = '1' then
a2_reg <= a2;
end if;
end if;
end process;
-- read data is unknown, when reading at write address
q2 <= ram(to_integer(a2_reg));
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_esdp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_esdp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk1 => clk1,
clk2 => clk2,
ce1 => ce1,
ce2 => ce2,
we1 => we1,
a1 => a1,
a2 => a2,
d1 => d1,
q1 => q1,
q2 => q2
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
apache-2.0
|
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys
|
Project/liaison/src/registers.vhd
|
1
|
1955
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity registers is
port(
voted_data_bit : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
status : in STD_LOGIC_VECTOR(2 downto 0);
control_signals : in STD_LOGIC_VECTOR(9 downto 0);
ECC_signal : in STD_LOGIC_VECTOR(3 downto 0);
voted_data_out : out STD_LOGIC_VECTOR(7 downto 0);
status_out : out STD_LOGIC_VECTOR(2 downto 0);
ECC_out : out STD_LOGIC_VECTOR(3 downto 0)
);
end registers;
architecture registers of registers is
signal voted_data_reg: STD_LOGIC_VECTOR (7 downto 0);
signal status_reg: STD_LOGIC_VECTOR (2 downto 0);
signal ECC_reg: STD_LOGIC_VECTOR (3 downto 0);
begin
-- Connect the registers to the outputs
process(voted_data_reg, status_reg, ECC_reg)
begin
voted_data_out <= voted_data_reg;
status_out <= status_reg;
ECC_out <= ECC_reg;
end process;
-- Add registers for storage of data
process(clk)
begin
if rising_edge(clk) then
if(reset='1') then
voted_data_reg <= "00000000";
status_reg <= "000";
ECC_reg <= "0000";
else
if control_signals(0) = '1' then
voted_data_reg(0) <= voted_data_bit;
end if;
if control_signals(1) = '1' then
voted_data_reg(1) <= voted_data_bit;
end if;
if control_signals(2) = '1' then
voted_data_reg(2) <= voted_data_bit;
end if;
if control_signals(3) = '1' then
voted_data_reg(3) <= voted_data_bit;
end if;
if control_signals(4) = '1' then
voted_data_reg(4) <= voted_data_bit;
end if;
if control_signals(5) = '1' then
voted_data_reg(5) <= voted_data_bit;
end if;
if control_signals(6) = '1' then
voted_data_reg(6) <= voted_data_bit;
end if;
if control_signals(7) = '1' then
voted_data_reg(7) <= voted_data_bit;
end if;
if control_signals(8) = '1' then
status_reg <= status;
end if;
if control_signals(9) = '1' then
ECC_reg <= ECC_signal;
end if;
end if;
end if;
end process;
end registers;
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/fpga/simulate/bin/work/id_reg/_primary.vhd
|
2
|
1642
|
library verilog;
use verilog.vl_types.all;
entity id_reg is
port(
clk : in vl_logic;
reset : in vl_logic;
alu_op : in vl_logic_vector(3 downto 0);
alu_in_0 : in vl_logic_vector(31 downto 0);
alu_in_1 : in vl_logic_vector(31 downto 0);
br_flag : in vl_logic;
mem_op : in vl_logic_vector(1 downto 0);
mem_wr_data : in vl_logic_vector(31 downto 0);
ctrl_op : in vl_logic_vector(1 downto 0);
dst_addr : in vl_logic_vector(4 downto 0);
gpr_we_n : in vl_logic;
exp_code : in vl_logic_vector(2 downto 0);
stall : in vl_logic;
flush : in vl_logic;
if_pc : in vl_logic_vector(29 downto 0);
if_en : in vl_logic;
id_pc : out vl_logic_vector(29 downto 0);
id_en : out vl_logic;
id_alu_op : out vl_logic_vector(3 downto 0);
id_alu_in_0 : out vl_logic_vector(31 downto 0);
id_alu_in_1 : out vl_logic_vector(31 downto 0);
id_br_flag : out vl_logic;
id_mem_op : out vl_logic_vector(1 downto 0);
id_mem_wr_data : out vl_logic_vector(31 downto 0);
id_ctrl_op : out vl_logic_vector(1 downto 0);
id_dst_addr : out vl_logic_vector(4 downto 0);
id_gpr_we_n : out vl_logic;
id_exp_code : out vl_logic_vector(2 downto 0)
);
end id_reg;
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/fpga/simulate/bin/work/bus_master_mux/_primary.vhd
|
2
|
1336
|
library verilog;
use verilog.vl_types.all;
entity bus_master_mux is
port(
m0_addr : in vl_logic_vector(29 downto 0);
m0_as_n : in vl_logic;
m0_rw : in vl_logic;
m0_wr_data : in vl_logic_vector(31 downto 0);
m0_grant_n : in vl_logic;
m1_addr : in vl_logic_vector(29 downto 0);
m1_as_n : in vl_logic;
m1_rw : in vl_logic;
m1_wr_data : in vl_logic_vector(31 downto 0);
m1_grant_n : in vl_logic;
m2_addr : in vl_logic_vector(29 downto 0);
m2_as_n : in vl_logic;
m2_rw : in vl_logic;
m2_wr_data : in vl_logic_vector(31 downto 0);
m2_grant_n : in vl_logic;
m3_addr : in vl_logic_vector(29 downto 0);
m3_as_n : in vl_logic;
m3_rw : in vl_logic;
m3_wr_data : in vl_logic_vector(31 downto 0);
m3_grant_n : in vl_logic;
s_addr : out vl_logic_vector(29 downto 0);
s_as_n : out vl_logic;
s_rw : out vl_logic;
s_wr_data : out vl_logic_vector(31 downto 0)
);
end bus_master_mux;
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/fpga/simulate/bin/work/@environment_sv_unit/_primary.vhd
|
1
|
98
|
library verilog;
use verilog.vl_types.all;
entity Environment_sv_unit is
end Environment_sv_unit;
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/fpga/simulate/bin/work/gpr/_primary.vhd
|
2
|
587
|
library verilog;
use verilog.vl_types.all;
entity gpr is
port(
clk : in vl_logic;
reset : in vl_logic;
rd_addr_0 : in vl_logic_vector(4 downto 0);
rd_data_0 : out vl_logic_vector(31 downto 0);
rd_addr_1 : in vl_logic_vector(4 downto 0);
rd_data_1 : out vl_logic_vector(31 downto 0);
we_n : in vl_logic;
wr_addr : in vl_logic_vector(29 downto 0);
wr_data : in vl_logic_vector(31 downto 0)
);
end gpr;
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/fpga/simulate/bin/work/@monitor_sv_unit/_primary.vhd
|
1
|
90
|
library verilog;
use verilog.vl_types.all;
entity Monitor_sv_unit is
end Monitor_sv_unit;
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/fpga/simulate/bin/work/testcase/_primary.vhd
|
2
|
76
|
library verilog;
use verilog.vl_types.all;
entity testcase is
end testcase;
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/fpga/simulate/bin/work/mem_stage/_primary.vhd
|
2
|
2058
|
library verilog;
use verilog.vl_types.all;
entity mem_stage is
port(
clk : in vl_logic;
reset : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
busy : out vl_logic;
fwd_data : out vl_logic_vector(31 downto 0);
spm_rd_data : in vl_logic_vector(31 downto 0);
spm_addr : out vl_logic_vector(29 downto 0);
spm_as_n : out vl_logic;
spm_rw : out vl_logic;
spm_wr_data : out vl_logic_vector(31 downto 0);
bus_rd_data : in vl_logic_vector(31 downto 0);
bus_rdy_n : in vl_logic;
bus_grant_n : in vl_logic;
bus_req_n : out vl_logic;
bus_addr : out vl_logic_vector(29 downto 0);
bus_as_n : out vl_logic;
bus_rw : out vl_logic;
bus_wr_data : out vl_logic_vector(31 downto 0);
ex_pc : in vl_logic_vector(29 downto 0);
ex_en : in vl_logic;
ex_br_flag : in vl_logic;
ex_mem_op : in vl_logic_vector(1 downto 0);
ex_mem_wr_data : in vl_logic_vector(31 downto 0);
ex_ctrl_op : in vl_logic_vector(1 downto 0);
ex_dst_addr : in vl_logic_vector(4 downto 0);
ex_gpr_we_n : in vl_logic;
ex_exp_code : in vl_logic_vector(2 downto 0);
ex_out : in vl_logic_vector(31 downto 0);
mem_pc : out vl_logic_vector(29 downto 0);
mem_en : out vl_logic;
mem_br_flag : out vl_logic;
mem_ctrl_op : out vl_logic_vector(1 downto 0);
mem_dst_addr : out vl_logic_vector(4 downto 0);
mem_gpr_we_n : out vl_logic;
mem_exp_code : out vl_logic_vector(2 downto 0);
mem_out : out vl_logic_vector(31 downto 0)
);
end mem_stage;
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/fpga/simulate/bin/work/spm/_primary.vhd
|
2
|
675
|
library verilog;
use verilog.vl_types.all;
entity spm is
port(
clk : in vl_logic;
if_spm_addr : in vl_logic_vector(11 downto 0);
if_spm_as_n : in vl_logic;
if_spm_rw : in vl_logic;
if_spm_wr_data : in vl_logic_vector(31 downto 0);
if_spm_rd_data : out vl_logic_vector(31 downto 0);
mem_spm_addr : in vl_logic_vector(11 downto 0);
mem_spm_as_n : in vl_logic;
mem_spm_rw : in vl_logic;
mem_spm_wr_data : in vl_logic_vector(31 downto 0);
mem_spm_rd_data : out vl_logic_vector(31 downto 0)
);
end spm;
|
apache-2.0
|
TanND/Electronic
|
VHDL/D7_C2.vhd
|
1
|
680
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D7_C2 is
port(
SI : in bit;
sel : in bit_VECTOR(2 downto 0);
SO : out bit_vector (7 downto 0)
);
end D7_C2;
architecture D7_C2 of D7_C2 is
begin
SO <= (SI & "0000000") when (sel="000") else
('0' & SI & "000000") when (sel="001") else
("00" & SI & "00000") when (sel="010") else
("000" & SI & "0000") when (sel="011") else
("0000" & SI & "000") when (sel="100") else
("00000" & SI & "00") when (sel="101") else
("000000" & SI & '0') when (sel="110") else
("0000000" & SI) ;
end D7_C2;
-- SI=random 1 ns; sel=random 3 ns;
|
apache-2.0
|
TanND/Electronic
|
VHDL/D11_C2.vhd
|
1
|
311
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D11_C2 is
port(
clk:in std_logic;
s0,s1 : out STD_LOGIC
);
end D11_C2;
architecture D11_C2 of D11_C2 is
begin
process(clk)
begin
if(clk='1') then s0<='1';s1<='1';
else s0<='0';s1<='0';
end if;
end process;
end D11_C2;
-- clk=0.5hz
|
apache-2.0
|
TanND/Electronic
|
VHDL/D3_C1.vhd
|
1
|
1027
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D3_C1 is
port(
rst : in STD_LOGIC;
sel : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D3_C1;
architecture D3_C1 of D3_C1 is
begin
process(rst,clk,sel)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (sel='1') then
if (dem=9) then dem:=0;
else dem:=dem+1;
end if;
elsif (sel='0') then
if(dem=0) then dem:=9;
else dem:=dem-1;
end if;
end if;
end if;
case dem is
when 0 => seg<= x"C0";
when 1 => seg<= x"F9";
when 2 => seg<= x"A4";
when 3 => seg<= x"B0";
when 4 => seg<= x"99";
when 5 => seg<= x"92";
when 6 => seg<= x"82";
when 7 => seg<= x"F8";
when 8 => seg<= x"80";
when others => seg<= x"90";
end case;
end process;
end D3_C1;
-- rst=500Khz; sel=1Mhz; clk=20Mhz;
|
apache-2.0
|
TanND/Electronic
|
VHDL/nt_nt.vhd
|
1
|
421
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nt_nt is
port(
clk : in std_logic;
SI : in BIT;
SO : out BIT
);
end nt_nt;
architecture nt_nt of nt_nt is
signal tmp: bit_vector(7 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
tmp <= tmp(6 downto 0)& SI;
end if;
end process;
SO <= tmp(7);
end nt_nt;
--clk=20Mhz; SI= random 10ns;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/usb_system/usb_system_clocks_dffpipe_l2c/_primary.vhd
|
1
|
344
|
library verilog;
use verilog.vl_types.all;
entity usb_system_clocks_dffpipe_l2c is
port(
clock : in vl_logic;
clrn : in vl_logic;
d : in vl_logic_vector(0 downto 0);
q : out vl_logic_vector(0 downto 0)
);
end usb_system_clocks_dffpipe_l2c;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/finalproject/finalproject_jtag_uart_scfifo_r/_primary.vhd
|
1
|
625
|
library verilog;
use verilog.vl_types.all;
entity finalproject_jtag_uart_scfifo_r is
port(
clk : in vl_logic;
fifo_clear : in vl_logic;
fifo_rd : in vl_logic;
rst_n : in vl_logic;
t_dat : in vl_logic_vector(7 downto 0);
wr_rfifo : in vl_logic;
fifo_EF : out vl_logic;
fifo_rdata : out vl_logic_vector(7 downto 0);
rfifo_full : out vl_logic;
rfifo_used : out vl_logic_vector(5 downto 0)
);
end finalproject_jtag_uart_scfifo_r;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/finalproject/finalproject_keycode/_primary.vhd
|
1
|
538
|
library verilog;
use verilog.vl_types.all;
entity finalproject_keycode is
port(
address : in vl_logic_vector(1 downto 0);
chipselect : in vl_logic;
clk : in vl_logic;
reset_n : in vl_logic;
write_n : in vl_logic;
writedata : in vl_logic_vector(31 downto 0);
out_port : out vl_logic_vector(7 downto 0);
readdata : out vl_logic_vector(31 downto 0)
);
end finalproject_keycode;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/usb_system/usb_system_mm_interconnect_0_rsp_demux_001/_primary.vhd
|
1
|
1165
|
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_rsp_demux_001 is
port(
sink_valid : in vl_logic_vector(0 downto 0);
sink_data : in vl_logic_vector(104 downto 0);
sink_channel : in vl_logic_vector(5 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src0_valid : out vl_logic;
src0_data : out vl_logic_vector(104 downto 0);
src0_channel : out vl_logic_vector(5 downto 0);
src0_startofpacket: out vl_logic;
src0_endofpacket: out vl_logic;
src0_ready : in vl_logic;
src1_valid : out vl_logic;
src1_data : out vl_logic_vector(104 downto 0);
src1_channel : out vl_logic_vector(5 downto 0);
src1_startofpacket: out vl_logic;
src1_endofpacket: out vl_logic;
src1_ready : in vl_logic;
clk : in vl_logic;
reset : in vl_logic
);
end usb_system_mm_interconnect_0_rsp_demux_001;
|
apache-2.0
|
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/BUFIO2 DDR/top_nto1_ddr_diff_tx.vhd
|
1
|
7838
|
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_diff_tx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential output transmitter for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_ddr_diff_tx is port (
reset : in std_logic ; -- reset (active high)
refclkin_p, refclkin_n : in std_logic ; -- frequency generator clock input
dataout_p, dataout_n : out std_logic_vector(7 downto 0) ; -- differential data outputs
clkout_p, clkout_n : out std_logic ) ; -- differential clock output
end top_nto1_ddr_diff_tx ;
architecture arch_top_nto1_ddr_diff_tx of top_nto1_ddr_diff_tx is
component clock_generator_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclkap : out std_logic ; -- A P ioclock from BUFIO2
ioclkan : out std_logic ; -- A N ioclock from BUFIO2
serdesstrobea : out std_logic ; -- A serdes strobe from BUFIO2
ioclkbp : out std_logic ; -- B P ioclock from BUFIO2 - leave open if not required
ioclkbn : out std_logic ; -- B N ioclock from BUFIO2 - leave open if not required
serdesstrobeb : out std_logic ; -- B serdes strobe from BUFIO2 - leave open if not required
gclk : out std_logic) ; -- global clock output from BUFIO2
end component ;
component serdes_n_to_1_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclkp : in std_logic ; -- IO Clock network
txioclkn : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 8 ; -- Set the serdes factor
constant D : integer := 8 ; -- Set the number of inputs and outputs
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal rst : std_logic ;
signal txd : std_logic_vector(DS downto 0) ; -- Registered Data to serdeses
signal txioclkp : std_logic ;
signal txioclkn : std_logic ;
signal tx_serdesstrobe : std_logic ;
signal tx_bufg_x1 : std_logic ;
signal clkoutp : std_logic_vector(0 downto 0) ;
signal clkoutn : std_logic_vector(0 downto 0) ;
-- Parameters for clock generation
constant TX_CLK_GEN : std_logic_vector(S-1 downto 0) := X"AA" ; -- Transmit a constant to make a clock
begin
rst <= reset ;
-- Reference Clock Input genertaes IO clocks via 2 x BUFIO2
inst_clkgen : clock_generator_ddr_s8_diff generic map(
S => S)
port map(
clkin_p => refclkin_p,
clkin_n => refclkin_n,
ioclkap => txioclkp,
ioclkan => txioclkn,
serdesstrobea => tx_serdesstrobe,
ioclkbp => open,
ioclkbn => open,
serdesstrobeb => open,
gclk => tx_bufg_x1) ;
process (tx_bufg_x1, rst) -- Generate some data to transmit
begin
if rst = '1' then
txd <= X"3000000000000001" ;
elsif tx_bufg_x1'event and tx_bufg_x1 = '1' then
txd <= txd(63 downto 60) & txd(58 downto 0) & txd(59) ;
end if ;
end process ;
-- Transmitter Logic - Instantiate serialiser to generate forwarded clock
inst_clkout : serdes_n_to_1_ddr_s8_diff generic map(
S => S,
D => 1)
port map (
dataout_p => clkoutp,
dataout_n => clkoutn,
txioclkp => txioclkp,
txioclkn => txioclkn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => TX_CLK_GEN); -- Transmit a constant to make the clock
clkout_p <= clkoutp(0) ;
clkout_n <= clkoutn(0) ;
-- Instantiate Outputs and output serialisers for output data lines
inst_dataout : serdes_n_to_1_ddr_s8_diff generic map(
S => S,
D => D)
port map (
dataout_p => dataout_p,
dataout_n => dataout_n,
txioclkp => txioclkp,
txioclkn => txioclkn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => txd);
end arch_top_nto1_ddr_diff_tx ;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/usb_system/usb_system_sdram_input_efifo_module/_primary.vhd
|
1
|
616
|
library verilog;
use verilog.vl_types.all;
entity usb_system_sdram_input_efifo_module is
port(
clk : in vl_logic;
rd : in vl_logic;
reset_n : in vl_logic;
wr : in vl_logic;
wr_data : in vl_logic_vector(61 downto 0);
almost_empty : out vl_logic;
almost_full : out vl_logic;
empty : out vl_logic;
full : out vl_logic;
rd_data : out vl_logic_vector(61 downto 0)
);
end usb_system_sdram_input_efifo_module;
|
apache-2.0
|
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/clock_generator_pll_s16_diff.vhd
|
1
|
9838
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_pll_s16_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: PLL Based clock generator. Takes in a differential clock and multiplies it
-- by the amount specified. Instantiates a BUFIO2, BUFPLL and a PLL using
-- INTERNAL feedback
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity clock_generator_pll_s16_diff is generic (
PLLD : integer := 1 ; -- Parameter to set the division factor in the PLL
PLLX : integer := 8 ; -- Parameter to set the multiplication factor in the PLL
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
CLKIN_PERIOD : real := 6.000 ; -- clock period (ns) of input clock on clkin_p
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclk : out std_logic ; -- ioclock from BUFPLL
serdesstrobe : out std_logic ; -- serdes strobe from BUFPLL
gclk1 : out std_logic ; -- global clock output from BUFG x1
gclk2 : out std_logic ; -- global clock output from BUFG x2
bufpll_lckd : out std_logic) ; -- Locked output from BUFPLL
end clock_generator_pll_s16_diff ;
architecture arch_clock_generator_pll_s16_diff of clock_generator_pll_s16_diff is
signal clkint : std_logic ; --
signal dummy : std_logic ; --
signal pllout_xs : std_logic ; --
signal pllout_x1 : std_logic ; --
signal pllout_x2 : std_logic ; --
signal pll_lckd : std_logic ; --
signal gclk2_int : std_logic ; --
signal buf_pll_lckd :std_logic ;
begin
gclk2 <= gclk2_int ;
iob_freqgen_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => clkint);
tx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 0.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => S/2, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => S, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => S, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
COMPENSATION => "INTERNAL", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => dummy, -- general output feedback signal
CLKOUT0 => pllout_xs, -- x7 clock for transmitter
CLKOUT1 => open, --
CLKOUT2 => pllout_x1, -- x1 clock for BUFG
CLKOUT3 => pllout_x2, -- x2 clock for BUFG
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => pll_lckd, -- active high pll lock signal
CLKFBIN => dummy, -- clock feedback input
CLKIN1 => clkint, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_tx_x1 : BUFG port map (I => pllout_x1, O => gclk1 ) ;
bufg_tx_x2 : BUFG port map (I => pllout_x2, O => gclk2_int ) ;
tx_bufpll_inst : BUFPLL generic map(
DIVIDE => S/2) -- PLLIN0 divide-by value to produce SERDESSTROBE (1 to 8); default 1
port map (
PLLIN => pllout_xs, -- PLL Clock input
GCLK => gclk2_int, -- Global Clock input
LOCKED => pll_lckd, -- Clock0 locked input
IOCLK => ioclk, -- Output PLL Clock
LOCK => buf_pll_lckd, -- BUFPLL Clock and strobe locked
SERDESSTROBE => serdesstrobe) ; -- Output SERDES strobe
bufpll_lckd <= buf_pll_lckd and pll_lckd ;
end arch_clock_generator_pll_s16_diff ;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/finalproject/finalproject_mm_interconnect_0_cmd_mux/_primary.vhd
|
1
|
839
|
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_cmd_mux is
port(
sink0_valid : in vl_logic;
sink0_data : in vl_logic_vector(104 downto 0);
sink0_channel : in vl_logic_vector(5 downto 0);
sink0_startofpacket: in vl_logic;
sink0_endofpacket: in vl_logic;
sink0_ready : out vl_logic;
src_valid : out vl_logic;
src_data : out vl_logic_vector(104 downto 0);
src_channel : out vl_logic_vector(5 downto 0);
src_startofpacket: out vl_logic;
src_endofpacket : out vl_logic;
src_ready : in vl_logic;
clk : in vl_logic;
reset : in vl_logic
);
end finalproject_mm_interconnect_0_cmd_mux;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/finalproject/finalproject_cpu_nios2_oci_debug/_primary.vhd
|
1
|
1028
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_debug is
port(
clk : in vl_logic;
dbrk_break : in vl_logic;
debugreq : in vl_logic;
hbreak_enabled : in vl_logic;
jdo : in vl_logic_vector(37 downto 0);
jrst_n : in vl_logic;
ocireg_ers : in vl_logic;
ocireg_mrs : in vl_logic;
reset : in vl_logic;
st_ready_test_idle: in vl_logic;
take_action_ocimem_a: in vl_logic;
take_action_ocireg: in vl_logic;
xbrk_break : in vl_logic;
debugack : out vl_logic;
monitor_error : out vl_logic;
monitor_go : out vl_logic;
monitor_ready : out vl_logic;
oci_hbreak_req : out vl_logic;
resetlatch : out vl_logic;
resetrequest : out vl_logic
);
end finalproject_cpu_nios2_oci_debug;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/finalproject/finalproject_cpu_jtag_debug_module_wrapper/_primary.vhd
|
1
|
1877
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_jtag_debug_module_wrapper is
port(
MonDReg : in vl_logic_vector(31 downto 0);
break_readreg : in vl_logic_vector(31 downto 0);
clk : in vl_logic;
dbrk_hit0_latch : in vl_logic;
dbrk_hit1_latch : in vl_logic;
dbrk_hit2_latch : in vl_logic;
dbrk_hit3_latch : in vl_logic;
debugack : in vl_logic;
monitor_error : in vl_logic;
monitor_ready : in vl_logic;
reset_n : in vl_logic;
resetlatch : in vl_logic;
tracemem_on : in vl_logic;
tracemem_trcdata: in vl_logic_vector(35 downto 0);
tracemem_tw : in vl_logic;
trc_im_addr : in vl_logic_vector(6 downto 0);
trc_on : in vl_logic;
trc_wrap : in vl_logic;
trigbrktype : in vl_logic;
trigger_state_1 : in vl_logic;
jdo : out vl_logic_vector(37 downto 0);
jrst_n : out vl_logic;
st_ready_test_idle: out vl_logic;
take_action_break_a: out vl_logic;
take_action_break_b: out vl_logic;
take_action_break_c: out vl_logic;
take_action_ocimem_a: out vl_logic;
take_action_ocimem_b: out vl_logic;
take_action_tracectrl: out vl_logic;
take_action_tracemem_a: out vl_logic;
take_action_tracemem_b: out vl_logic;
take_no_action_break_a: out vl_logic;
take_no_action_break_b: out vl_logic;
take_no_action_break_c: out vl_logic;
take_no_action_ocimem_a: out vl_logic;
take_no_action_tracemem_a: out vl_logic
);
end finalproject_cpu_jtag_debug_module_wrapper;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/usb_system/usb_system_mm_interconnect_0_router_002_default_decode/_primary.vhd
|
1
|
978
|
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_router_002_default_decode is
generic(
DEFAULT_CHANNEL : integer := 0;
\DEFAULT_WR_CHANNEL\: integer := -1;
\DEFAULT_RD_CHANNEL\: integer := -1;
DEFAULT_DESTID : integer := 0
);
port(
default_destination_id: out vl_logic_vector(2 downto 0);
default_wr_channel: out vl_logic_vector(5 downto 0);
default_rd_channel: out vl_logic_vector(5 downto 0);
default_src_channel: out vl_logic_vector(5 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DEFAULT_CHANNEL : constant is 1;
attribute mti_svvh_generic_type of \DEFAULT_WR_CHANNEL\ : constant is 1;
attribute mti_svvh_generic_type of \DEFAULT_RD_CHANNEL\ : constant is 1;
attribute mti_svvh_generic_type of DEFAULT_DESTID : constant is 1;
end usb_system_mm_interconnect_0_router_002_default_decode;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/usb_system/usb_system_jtag_uart_sim_scfifo_w/_primary.vhd
|
1
|
500
|
library verilog;
use verilog.vl_types.all;
entity usb_system_jtag_uart_sim_scfifo_w is
port(
clk : in vl_logic;
fifo_wdata : in vl_logic_vector(7 downto 0);
fifo_wr : in vl_logic;
fifo_FF : out vl_logic;
r_dat : out vl_logic_vector(7 downto 0);
wfifo_empty : out vl_logic;
wfifo_used : out vl_logic_vector(5 downto 0)
);
end usb_system_jtag_uart_sim_scfifo_w;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/rtl_work/block_@s@m/_primary.vhd
|
1
|
240
|
library verilog;
use verilog.vl_types.all;
entity block_SM is
port(
Clk : in vl_logic;
Reset : in vl_logic;
block_ready : out vl_logic_vector(2 downto 0)
);
end block_SM;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/usb_system/usb_system_cpu/_primary.vhd
|
1
|
1555
|
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu is
port(
clk : in vl_logic;
d_irq : in vl_logic_vector(31 downto 0);
d_readdata : in vl_logic_vector(31 downto 0);
d_waitrequest : in vl_logic;
i_readdata : in vl_logic_vector(31 downto 0);
i_waitrequest : in vl_logic;
jtag_debug_module_address: in vl_logic_vector(8 downto 0);
jtag_debug_module_byteenable: in vl_logic_vector(3 downto 0);
jtag_debug_module_debugaccess: in vl_logic;
jtag_debug_module_read: in vl_logic;
jtag_debug_module_write: in vl_logic;
jtag_debug_module_writedata: in vl_logic_vector(31 downto 0);
reset_n : in vl_logic;
reset_req : in vl_logic;
d_address : out vl_logic_vector(28 downto 0);
d_byteenable : out vl_logic_vector(3 downto 0);
d_read : out vl_logic;
d_write : out vl_logic;
d_writedata : out vl_logic_vector(31 downto 0);
i_address : out vl_logic_vector(28 downto 0);
i_read : out vl_logic;
jtag_debug_module_debugaccess_to_roms: out vl_logic;
jtag_debug_module_readdata: out vl_logic_vector(31 downto 0);
jtag_debug_module_resetrequest: out vl_logic;
jtag_debug_module_waitrequest: out vl_logic;
no_ci_readra : out vl_logic
);
end usb_system_cpu;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/finalproject/finalproject_jtag_uart_scfifo_w/_primary.vhd
|
1
|
582
|
library verilog;
use verilog.vl_types.all;
entity finalproject_jtag_uart_scfifo_w is
port(
clk : in vl_logic;
fifo_clear : in vl_logic;
fifo_wdata : in vl_logic_vector(7 downto 0);
fifo_wr : in vl_logic;
rd_wfifo : in vl_logic;
fifo_FF : out vl_logic;
r_dat : out vl_logic_vector(7 downto 0);
wfifo_empty : out vl_logic;
wfifo_used : out vl_logic_vector(5 downto 0)
);
end finalproject_jtag_uart_scfifo_w;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/usb_system/usb_system_mm_interconnect_0_router_003/_primary.vhd
|
1
|
777
|
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_router_003 is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src_valid : out vl_logic;
src_data : out vl_logic_vector(104 downto 0);
src_channel : out vl_logic_vector(5 downto 0);
src_startofpacket: out vl_logic;
src_endofpacket : out vl_logic;
src_ready : in vl_logic
);
end usb_system_mm_interconnect_0_router_003;
|
apache-2.0
|
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_data_s16_diff.vhd
|
1
|
16663
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_s16_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with differential inputs
-- Takes in 1 bit of differential data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control CAL and the phase detector
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_s16_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16 ; -- Set the number of inputs and outputs
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclk : in std_logic ; -- IO Clock network
rx_serdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
rx_toggle : in std_logic ; -- control line
rx_bufg_pll_x1 : in std_logic ; -- Global clock
rx_bufg_pll_x2 : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0)) ; -- Output data
end serdes_1_to_n_data_s16_diff ;
architecture arch_serdes_1_to_n_data_s16_diff of serdes_1_to_n_data_s16_diff is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal cascade : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal busym : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal lows : std_logic_vector(D-1 downto 0) ;
signal highs : std_logic_vector(D-1 downto 0) ;
signal busyd : std_logic_vector(D-1 downto 0) ;
signal cal_data_sint : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal busy_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal cal_data_master : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal valid_data_d : std_logic ;
signal rst_data : std_logic ;
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal ce_data_inta : std_logic ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal datah : std_logic_vector((D*S/2)-1 downto 0) ;
signal rxd : std_logic_vector((D*S/2)-1 downto 0) ;
signal datain : std_logic_vector((D*S)-1 downto 0) ;
signal flag : std_logic ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
busy_data <= busys ;
data_out <= datain ;
cal_data_slave <= cal_data_sint ;
process (rx_bufg_pll_x1)
begin
if rx_bufg_pll_x1'event and rx_bufg_pll_x1 = '1' then
datain <= rxd & datah ;
end if ;
end process ;
process (rx_bufg_pll_x2)
begin
if rx_bufg_pll_x2'event and rx_bufg_pll_x2 = '1' then
if rx_toggle = '1' then
datah <= rxd ;
end if ;
end if ;
end process ;
process (rx_bufg_pll_x2, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif rx_bufg_pll_x2'event and rx_bufg_pll_x2 = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (rx_bufg_pll_x2, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif rx_bufg_pll_x2'event and rx_bufg_pll_x2 = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' then -- decide whether pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= (others => '1') ;
inc_data_int <= '0' ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => datain_p(i),
IB => datain_n(i),
O => rx_data_in(i));
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x2, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busym(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND" , -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" , -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x2, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i) , -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rx_serdesstrobe,
RST => reset,
CLKDIV => rx_bufg_pll_x2,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rx_serdesstrobe,
RST => reset,
CLKDIV => rx_bufg_pll_x2,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
loop1 : for j in 7 downto (8-(S/2)) generate
rxd(((D*(j+(S/2)-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_s16_diff ;
|
apache-2.0
|
Jawanga/ece385final
|
simulation/modelsim/finalproject/altera_merlin_slave_translator/_primary.vhd
|
1
|
4900
|
library verilog;
use verilog.vl_types.all;
entity altera_merlin_slave_translator is
generic(
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W: integer := 4;
AV_READLATENCY : integer := 1;
AV_READ_WAIT_CYCLES: integer := 0;
AV_WRITE_WAIT_CYCLES: integer := 0;
AV_SETUP_WAIT_CYCLES: integer := 0;
AV_DATA_HOLD_CYCLES: integer := 0;
USE_READDATAVALID: integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE: integer := 0;
USE_WRITERESPONSE: integer := 0;
AV_SYMBOLS_PER_WORD: integer := 4;
AV_ADDRESS_SYMBOLS: integer := 0;
AV_BURSTCOUNT_SYMBOLS: integer := 0;
BITS_PER_WORD : vl_notype;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W: integer := 10;
UAV_DATA_W : integer := 32;
AV_CONSTANT_BURST_BEHAVIOR: integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR: integer := 0;
CHIPSELECT_THROUGH_READLATENCY: integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES: integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
uav_address : in vl_logic_vector;
uav_writedata : in vl_logic_vector;
uav_write : in vl_logic;
uav_read : in vl_logic;
uav_burstcount : in vl_logic_vector;
uav_byteenable : in vl_logic_vector;
uav_lock : in vl_logic;
uav_debugaccess : in vl_logic;
uav_clken : in vl_logic;
uav_readdatavalid: out vl_logic;
uav_waitrequest : out vl_logic;
uav_readdata : out vl_logic_vector;
uav_response : out vl_logic_vector(1 downto 0);
uav_writeresponsevalid: out vl_logic;
av_address : out vl_logic_vector;
av_writedata : out vl_logic_vector;
av_write : out vl_logic;
av_read : out vl_logic;
av_burstcount : out vl_logic_vector;
av_byteenable : out vl_logic_vector;
av_writebyteenable: out vl_logic_vector;
av_begintransfer: out vl_logic;
av_chipselect : out vl_logic;
av_beginbursttransfer: out vl_logic;
av_lock : out vl_logic;
av_clken : out vl_logic;
av_debugaccess : out vl_logic;
av_outputenable : out vl_logic;
av_readdata : in vl_logic_vector;
av_readdatavalid: in vl_logic;
av_waitrequest : in vl_logic;
av_response : in vl_logic_vector(1 downto 0);
av_writeresponsevalid: in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of AV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of AV_READLATENCY : constant is 1;
attribute mti_svvh_generic_type of AV_READ_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_WRITE_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_SETUP_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_HOLD_CYCLES : constant is 1;
attribute mti_svvh_generic_type of USE_READDATAVALID : constant is 1;
attribute mti_svvh_generic_type of USE_WAITREQUEST : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of AV_SYMBOLS_PER_WORD : constant is 1;
attribute mti_svvh_generic_type of AV_ADDRESS_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_WORD : constant is 3;
attribute mti_svvh_generic_type of UAV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of UAV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of UAV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of CHIPSELECT_THROUGH_READLATENCY : constant is 1;
attribute mti_svvh_generic_type of USE_UAV_CLKEN : constant is 1;
attribute mti_svvh_generic_type of AV_REQUIRE_UNALIGNED_ADDRESSES : constant is 1;
end altera_merlin_slave_translator;
|
apache-2.0
|
fabianschuiki/moore
|
test/vhdl/arch_body.vhd
|
1
|
802
|
architecture DataFlow of Full_Adder is
signal A,B: Bit;
begin
A <= X xor Y;
B <= A and Cin;
Sum <= A xor Cin;
Cout <= B or (X and Y);
end architecture DataFlow;
architecture Structure of TestBench is
component C is end component C;
component Full_Adder
port (X, Y, Cin: Bit; Cout, Sum: out Bit);
end component;
signal A,B,C,D,E,F,G: Bit;
signal OK: Boolean;
begin
UUT: Full_Adder port map (A,B,C,D,E);
Generator: AdderTest port map (A,B,C,F,G);
Comparator: AdderCheck port map (D,E,F,G,OK);
end Structure;
architecture Behavior of AndGate is begin
process (Inputs)
variable Temp: Bit;
begin
Temp := '1';
for i in Inputs'Range loop
if Inputs(i) = '0' then
Temp := '0';
exit;
end if;
end loop;
Result <= Temp after 10 ns;
end process;
end Behavior;
|
apache-2.0
|
fabianschuiki/moore
|
test/vhdl/exprs.vhd
|
1
|
3732
|
package pkg is
type SMALLINT is range 0 to 3;
constant two : SMALLINT := 2;
end;
library work;
use work.pkg;
entity foo is end;
architecture bar of foo is
--type BOOLEAN is (false, true);
--type BIT is ('0', '1');
--type BIT2 is ('1', '2');
--type BIT3 is ('X', '0');
--type INTEGER is range -256 to 255;
--type BIT_VECTOR is array (INTEGER range <>) of BIT;
subtype TRIBITS is BIT_VECTOR (0 to 2);
subtype PENTABITS is BIT_VECTOR (0 to 4);
type REC is record
a : BIT;
b : BIT;
c : BIT;
end record;
--attribute STUFF : BIT;
--attribute STUFF of BIT : type is '0';
-- primary literal
constant s00 : INTEGER := 123;
constant s01 : BIT := '0';
--constant s02 : BIT_VECTOR(0 to 4) := "00100";
-- primary name
constant s10 : INTEGER := s00;
--constant s11 : BIT := BIT'STUFF;
constant s12 : INTEGER := pkg.two;
-- primary aggregate
constant s20 : REC := ('0', '1', '0');
constant s21 : REC := (a => '0', b => '1', c => '0');
constant s22 : REC := ('0', c => '0', b => '1');
constant s23 : TRIBITS := ('0', '1', '0');
constant s24 : TRIBITS := (0 => '0', 1 => '1', 2 => '0');
constant s25 : TRIBITS := ('0', 2 => '1', 1 => '0');
-- primary function call
constant s30 : INTEGER := square(2);
-- primary qualified expression
constant s40 : INTEGER := INTEGER'(123);
constant s41 : REC := REC'('0', '1', '0');
constant s42 : REC := REC'(a => '0', b => '1', c => '0');
constant s43 : REC := REC'('0', c => '0', b => '1');
constant s44 : TRIBITS := TRIBITS'('0', '1', '0');
constant s45 : TRIBITS := TRIBITS'(0 => '0', 1 => '1', 2 => '0');
constant s46 : TRIBITS := TRIBITS'('0', 2 => '1', 1 => '0');
-- primary type conversion
--constant s50 : INTEGER := INTEGER('0');
constant s51 : INTEGER := INTEGER(123);
-- primary allocator
constant s60 : INTEGER := new INTEGER;
constant s61 : INTEGER := new INTEGER'(123);
-- primary parenthesized
constant s70 : INTEGER := (123);
constant s71 : INTEGER := (s10);
-- factor
constant s80 : INTEGER := 2 ** 4;
constant s81 : INTEGER := abs s00;
constant s82 : TRIBITS := not s23;
constant s83 : TRIBITS := and s23;
constant s84 : TRIBITS := or s23;
constant s85 : TRIBITS := nand s23;
constant s86 : TRIBITS := nor s23;
constant s87 : TRIBITS := xor s23;
constant s88 : TRIBITS := xnor s23;
-- term
constant s90 : INTEGER := 2 * 2;
constant s91 : INTEGER := 8 / 2;
constant s92 : INTEGER := 8 mod 2;
constant s93 : INTEGER := 8 rem 2;
-- simple expression
constant s100 : INTEGER := -2;
constant s101 : INTEGER := +2;
constant s102 : INTEGER := 2 + 2;
constant s103 : INTEGER := 4 + 2;
constant s104 : BIT_VECTOR := "00" & "100";
-- shift expression
constant s110 : TRIBITS := s23 sll 4;
constant s111 : TRIBITS := s23 srl 4;
constant s112 : TRIBITS := s23 sla 4;
constant s113 : TRIBITS := s23 sra 4;
constant s114 : TRIBITS := s23 rol 4;
constant s115 : TRIBITS := s23 ror 4;
-- relation
constant s120 : INTEGER := 8 = 4;
constant s121 : INTEGER := 8 /= 4;
constant s122 : INTEGER := 8 < 4;
constant s123 : INTEGER := 8 <= 4;
constant s124 : INTEGER := 8 > 4;
constant s125 : INTEGER := 8 >= 4;
constant s126 : BIT := '0' ?= '1';
constant s127 : BIT := '0' ?/= '1';
constant s128 : BIT := s23 ?= s23;
constant s129 : BIT := s23 ?/= s23;
constant s12A : BIT := '0' ?< '1';
constant s12B : BIT := '0' ?<= '1';
constant s12C : BIT := '0' ?> '1';
constant s12D : BIT := '0' ?>= '1';
-- logical expression
constant s130 : BIT := '0' and '1';
constant s131 : BIT := '0' or '1';
constant s132 : BIT := '0' xor '1';
constant s133 : BIT := '0' nand '1';
constant s134 : BIT := '0' nor '1';
constant s135 : BIT := '0' xnor '1';
-- condition
constant s140 : BOOLEAN := ?? 123;
begin end;
|
apache-2.0
|
fabianschuiki/moore
|
test/vhdl/process_0.vhd
|
1
|
236
|
entity foo is
end;
architecture bar of foo is
begin
empty : process
begin
end process;
end;
--@ +elab foo(bar)
--| proc @foo_bar_empty () () {
--| }
--|
--| entity @foo_bar () () {
--| %empty = inst @foo_bar_empty () ()
--| }
|
apache-2.0
|
fabianschuiki/moore
|
test/vhdl/decls_pkg_body.vhd
|
1
|
1349
|
-- This file tests package body declarative items.
package pkg is end;
package body pkg is
type BIT is ('0', '1');
-- subprogram_declaration
procedure proc_a;
function func_a return BIT;
-- subprogram_body
procedure proc_a is begin
end;
function func_a return BIT is begin
end;
-- subprogram_instantiation_declaration
procedure proc_b is new proc_a;
function func_b is new func_a;
-- package_declaration
package pkg_a is end;
-- package_body
package body pkg_a is end;
-- package_instantiation_declaration
package pkg_b is new pkg_a;
-- type_declaration
type NUM is range 0 to 100;
-- subtype_declaration
subtype ANS is NUM range 0 to 42;
-- constant_declaration
--constant const_a : BIT;
-- variable_declaration
--variable var_a : BIT;
-- file_declaration
--file file_a : BIT;
-- alias_declaration
--alias alias_a is pkg_a;
-- attribute_declaration
--attribute attr_a : BIT;
-- attribute_specification
--attribute attr_a of NUM : type is '0';
-- use_clause
use work.pkg.all;
-- group_template_declaration
--group grp_tmp_a is (signal, signal);
-- group_declaration
--group grp_a : grp_tmp_a (sig_a, sig_a);
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
-- Currently the architecture is required to trigger typeck of the entire
-- library.
begin end;
|
apache-2.0
|
sbates130272/capi-textswap
|
rtl/processors.vhd
|
1
|
7136
|
--------------------------------------------------------------------------------
--
-- Copyright 2015 PMC-Sierra, Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License"); you
-- may not use this file except in compliance with the License. You may
-- obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0 Unless required by
-- applicable law or agreed to in writing, software distributed under the
-- License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for
-- the specific language governing permissions and limitations under the
-- License.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company: PMC-Sierra, Inc.
-- Engineer: Logan Gunthorpe
--
-- Description:
-- Processor Multiplexor Block
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library capi;
use capi.misc.all;
entity processors is
port (
clk : in std_logic;
clear : in std_logic;
idata : in std_logic_vector(0 to 511);
ivalid : in std_logic;
idone : in std_logic;
iready : out std_logic;
odata : out std_logic_vector(0 to 511);
ovalid : out std_logic;
odirty : out std_logic;
oready : in std_logic;
odone : out std_logic;
len : in unsigned(0 to 31);
flags : in std_logic_vector(0 to 7);
-- Register Interface
reg_en : in std_logic;
reg_addr : in unsigned(0 to 5);
reg_dw : in std_logic;
reg_write : in std_logic;
reg_wdata : in std_logic_vector(0 to 63);
reg_read : in std_logic;
reg_rdata : out std_logic_vector(0 to 63);
reg_read_ack : out std_logic
);
end entity processors;
architecture main of processors is
signal memcpy_en : std_logic;
signal memcpy_iready : std_logic;
signal memcpy_odata : std_logic_vector(odata'range);
signal memcpy_ovalid : std_logic;
signal memcpy_odirty : std_logic;
signal memcpy_done : std_logic;
signal lfsr_en : std_logic;
signal lfsr_iready : std_logic;
signal lfsr_odata : std_logic_vector(odata'range);
signal lfsr_ovalid : std_logic;
signal lfsr_odirty : std_logic;
signal lfsr_done : std_logic;
signal text_en : std_logic;
signal text_iready : std_logic;
signal text_odata : std_logic_vector(odata'range);
signal text_ovalid : std_logic;
signal text_odirty : std_logic;
signal text_done : std_logic;
signal reg_lfsr_seed : std_logic_vector(0 to 63);
signal reg_lfsr_seed_set : std_logic;
signal reg_text_search : std_logic_vector(0 to 127);
signal reg_text_clear : std_logic;
begin
proc_memcpy_i: entity work.proc_memcpy
port map (
clk => clk,
en => memcpy_en,
idata => idata,
ivalid => ivalid,
idone => idone,
iready => memcpy_iready,
odata => memcpy_odata,
ovalid => memcpy_ovalid,
odirty => memcpy_odirty,
odone => memcpy_done,
oready => oready,
len => len);
proc_lfsr_i: entity work.proc_lfsr
port map (
clk => clk,
en => lfsr_en,
idata => idata,
ivalid => ivalid,
idone => idone,
iready => lfsr_iready,
odata => lfsr_odata,
ovalid => lfsr_ovalid,
odirty => lfsr_odirty,
odone => lfsr_done,
oready => oready,
len => len,
reg_lfsr_seed => reg_lfsr_seed,
reg_lfsr_seed_set => reg_lfsr_seed_set
);
proc_text_i: entity work.proc_text
port map (
clk => clk,
en => text_en,
idata => idata,
ivalid => ivalid,
idone => idone,
iready => text_iready,
odata => text_odata,
ovalid => text_ovalid,
odirty => text_odirty,
odone => text_done,
oready => oready,
len => len,
reg_text_search => reg_text_search,
reg_text_clear => reg_text_clear
);
iready <= memcpy_iready or
lfsr_iready or
text_iready;
odata <= memcpy_odata or
lfsr_odata or
text_odata;
ovalid <= memcpy_ovalid or
lfsr_ovalid or
text_ovalid;
odirty <= memcpy_odirty or
lfsr_odirty or
text_odirty;
odone <= memcpy_done or
lfsr_done or
text_done;
process (clk) is
begin
if rising_edge(clk) then
memcpy_en <= '0';
lfsr_en <= '0';
text_en <= '0';
if clear = '0' then
if flags(0) = '1' then
lfsr_en <= '1';
elsif flags(1) = '1' then
memcpy_en <= '1';
else
text_en <= '1';
end if;
end if;
end if;
end process;
REG_READ_P: process (clk) is
begin
if rising_edge(clk) then
reg_read_ack <= '0';
reg_rdata <= (others=>'0');
if reg_en = '1' then
reg_read_ack <= reg_read;
case to_integer(reg_addr(0 to 4)) is
when 0 => reg_rdata <= reg_lfsr_seed;
when 1 => reg_rdata <= endian_swap(reg_text_search(0 to 63));
when 2 => reg_rdata <= endian_swap(reg_text_search(64 to 127));
when others => reg_rdata <= (others=>'0');
end case;
end if;
end if;
end process REG_READ_P;
REG_WRITE_P: process (clk) is
begin
if rising_edge(clk) then
reg_lfsr_seed_set <= '0';
reg_text_clear <= '0';
if reg_en = '1' and reg_write = '1' then
case to_integer(reg_addr(0 to 4)) is
--We're a little lazy here as we only support 64 bit writes
when 0 =>
reg_lfsr_seed <= reg_wdata;
reg_lfsr_seed_set <= '1';
when 1 =>
reg_text_search(0 to 63) <= endian_swap(reg_wdata);
reg_text_clear <= '1';
when 2 =>
reg_text_search(64 to 127) <= endian_swap(reg_wdata);
reg_text_clear <= '1';
when others => null;
end case;
end if;
end if;
end process REG_WRITE_P;
end architecture main;
|
apache-2.0
|
DaniilLeksin/gc
|
wx/tools/Editra/tests/syntax/vhdl.vhdl
|
9
|
985
|
-- Syntax Highlighting Test File for VHDL
-- Comments are like this
-- Hello World in VHDL
entity hello_world is
end;
architecture hello_world of hello_world is
begin
stimulus : process
begin
assert false report "Hello World By Deepak"
severity note;
wait;
end process stimulus;
end hello_world;
-- A simple counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav;
|
apache-2.0
|
hhanff/software
|
vhdl/funcs.vhd
|
1
|
55806
|
-----------------------------------------------------------------------
-- Package that declares some special functions needed for RTL netlisting
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package FUNCS is
--- RTL netlister functions
function mux_s
(inputs : std_logic_vector;
sel : unsigned) return std_logic;
function mux_v
(inputs : unsigned;
sel : std_logic) return unsigned;
function mux_v
(inputs : unsigned;
sel : unsigned) return unsigned;
function mux_v
(inputs : signed;
sel : signed) return signed;
function mux1hot_s
(inputs : unsigned;
sel : unsigned) return std_logic;
function mux1hot_v
(inputs : unsigned;
sel : unsigned) return unsigned;
function mux1hot_v
(inputs : signed;
sel : signed) return signed;
type integers is array (positive range <>) of integer;
function muxv_s
(inputs : unsigned;
choices_nb : integers;
choices : unsigned;
sel : unsigned) return std_logic;
function muxv_v
(inputs : unsigned;
choices_nb : integers;
choices : unsigned;
sel : unsigned) return unsigned;
function lat_s
(input : std_logic;
clk : std_logic;
output : std_logic) return std_logic;
function lat_v
(input : unsigned;
clk : std_logic;
output: unsigned) return unsigned;
function tri_s
(input : std_logic;
control : std_logic) return std_logic;
function tri_v
(input : unsigned;
control : std_logic) return unsigned;
FUNCTION to_stdlogic ( arg1 : BOOLEAN ) RETURN STD_LOGIC;
FUNCTION maximum ( arg1, arg2 : INTEGER) RETURN INTEGER;
FUNCTION minimum ( arg1, arg2 : INTEGER) RETURN INTEGER;
FUNCTION "xor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "xor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED;
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "and" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "and" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "nand" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "nand" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "or" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "or" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "nor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "nor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "xnor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "xnor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION nand_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
FUNCTION nand_reduce(arg : SIGNED) RETURN STD_LOGIC;
FUNCTION eq ( l, r : UNSIGNED ) RETURN BOOLEAN ;
--attribute builtin_subprogram of "="[UNSIGNED, UNSIGNED return BOOLEAN]: function is "stdarith_eq_uu";
FUNCTION eq ( l, r : SIGNED ) RETURN BOOLEAN ;
--attribute builtin_subprogram of "="[SIGNED, SIGNED return BOOLEAN]: function is "stdarith_eq_ss";
-- Vectorized Overloaded Arithmetic Operators
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC;
FUNCTION "-" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC;
FUNCTION "/" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "/" ( l, r : SIGNED ) RETURN SIGNED;
FUNCTION "MOD" ( l, r : SIGNED ) RETURN SIGNED;
FUNCTION "MOD" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "REM" ( l, r : SIGNED ) RETURN SIGNED;
FUNCTION "REM" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "**" ( l, r : SIGNED ) RETURN SIGNED;
FUNCTION "**" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
--
-- In general, objects in this package are required to be functions.
-- For synthesizability reasons, we want the "flipflop" functions to be
-- procedures. There is a special kludge in the rtl netlister to let
-- this work.
--
procedure flipflop
(signal input : in std_logic;
signal clk : in std_logic;
signal output : out std_logic);
procedure flipflop
(signal input : in unsigned;
signal clk : in std_logic;
signal output : out unsigned);
procedure flipflop
(signal input : in std_logic;
signal clk : in std_logic;
signal output : out std_logic;
signal rst : in std_logic;
signal value : in std_logic);
procedure flipflop
(signal input : in unsigned;
signal clk : in std_logic;
signal output : out unsigned;
signal rst : in std_logic;
signal value : in unsigned);
--
-- This is used in the special case when we need to pick a vector that
-- has been changed into a constant. This is because the VHDL language
-- doesn't allow one to say "bits"[index]
--
function readindex
(input : unsigned;
index : natural) return std_logic;
--
-- The following procedures insert n consecutive wait until edge
-- statements into the process. 'phase' gives the active edge ie it
-- should be either '1' or '0'
--
procedure wait_clock_cycles
(constant n : natural;
signal clk : in std_logic;
constant phase : in std_logic);
procedure wait_clock_cycles
(constant n : natural;
signal clk : in bit;
constant phase : in bit);
-- Declare Exemplar Synthesis Directive attributes
attribute SYNTHESIS_RETURN : STRING ;
attribute IS_SIGNED : BOOLEAN ;
end FUNCS;
package body FUNCS is
function mux_s
(inputs : std_logic_vector;
sel : unsigned) return std_logic is
variable result : std_logic;
attribute SYNTHESIS_RETURN of result:variable is "mux";
begin
result := inputs ( conv_integer ( '0'&sel ));
return result;
end;
function mux_v
(inputs : unsigned;
sel : std_logic) return unsigned is
constant nb_inputs : positive := 2;
constant size : positive := inputs'length/nb_inputs;
variable value : integer;
variable ins : unsigned(0 to inputs'length-1) := inputs;
variable result : unsigned(0 to size-1);
variable left, right : integer;
attribute SYNTHESIS_RETURN of result:variable is "mux";
begin
if (sel = '1')
then
value := 1;
else
value := 0;
end if;
left := value*size;
right := (value + 1)*size -1;
for i in left to right loop
result(i-left) := ins(i);
end loop;
--result := ins (value*size to (value+1)*size-1);
return result;
end;
function mux_v
(inputs : unsigned;
sel : unsigned) return unsigned is
variable value : natural := conv_integer (unsigned(sel));
constant nb_inputs : positive := 2 ** sel'length;
constant size : positive := inputs'length/nb_inputs;
variable ins : unsigned(0 to inputs'length-1) := inputs;
variable result : unsigned(0 to size-1);
variable left, right : natural;
attribute SYNTHESIS_RETURN of result:variable is "mux";
begin
left := value*size;
right := (value + 1)*size -1;
for i in left to right loop
result(i-left) := ins(i);
end loop;
--result := ins (value*size to (value+1)*size-1);
return result;
end;
function mux_v
(inputs : signed;
sel : signed) return signed is
variable value : natural := conv_integer (unsigned(sel));
constant nb_inputs : positive := 2 ** sel'length;
constant size : positive := inputs'length/nb_inputs;
variable ins : signed(0 to inputs'length-1) := inputs;
variable result : signed(0 to size-1);
variable left, right : natural;
attribute SYNTHESIS_RETURN of result:variable is "mux";
begin
left := value*size;
right := (value + 1)*size -1;
for i in left to right loop
result(i-left) := ins(i);
end loop;
--result := ins (value*size to (value+1)*size-1);
return result;
end;
function mux1hot_s
(inputs : unsigned;
sel : unsigned) return std_logic is
variable ins : unsigned(0 to inputs'length-1) := inputs;
variable s : unsigned(0 to sel'length-1) := sel;
variable result : std_logic;
attribute SYNTHESIS_RETURN of result:variable is "mux1hot";
begin
for i in s'range loop
if s(i) = '1' then
result := ins (i);
return result;
end if;
end loop;
return '0';
end;
function mux1hot_v
(inputs : unsigned;
sel : unsigned) return unsigned is
constant size : positive := inputs'length/sel'length;
variable ins : unsigned(0 to inputs'length-1) := inputs;
variable s : unsigned(0 to sel'length-1) := sel;
variable result : unsigned(0 to size-1);
variable left, right : integer;
attribute SYNTHESIS_RETURN of result:variable is "mux1hot";
begin
for i in s'range loop
if (s(i) = '1') then
left := i*size;
right := (i+1)*size-1;
for j in left to right loop
result(j-left) := ins(j);
end loop;
--result := ins (i*size to (i+1)*size-1);
return result;
end if;
end loop;
result := (others=>'0');
return result;
end;
function mux1hot_v
(inputs : signed;
sel : signed) return signed is
constant size : positive := inputs'length/sel'length;
variable ins : signed(0 to inputs'length-1) := inputs;
variable s : signed(0 to sel'length-1) := sel;
variable result : signed(0 to size-1);
variable left, right : integer;
attribute SYNTHESIS_RETURN of result:variable is "mux1hot";
begin
for i in s'range loop
if (s(i) = '1') then
left := i*size;
right := (i+1)*size-1;
for j in left to right loop
result(j-left) := ins(j);
end loop;
--result := ins (i*size to (i+1)*size-1);
return result;
end if;
end loop;
result := (others=>'0');
return result;
end;
function muxv_s
(inputs : unsigned;
choices_nb : integers;
choices : unsigned;
sel : unsigned) return std_logic is
variable ins : unsigned(0 to inputs'length-1) := inputs;
variable chs : unsigned(0 to choices'length-1) := choices;
variable ch : unsigned(0 to sel'length-1);
variable choice_index : integer := 0;
variable result : std_logic;
attribute SYNTHESIS_RETURN of result:variable is "muxv";
begin
for i in 0 to choices_nb'length-1 loop
for j in 1 to choices_nb(i) loop
ch := chs (choice_index*sel'length to
(choice_index+1)*sel'length);
if (sel = ch) then
result := ins (i);
return result;
end if;
choice_index := choice_index + 1;
end loop;
end loop;
result := ins (choices_nb'length-1);
return result;
end;
function muxv_v
(inputs : unsigned;
choices_nb : integers;
choices : unsigned;
sel : unsigned) return unsigned is
constant size : positive := inputs'length/choices_nb'length;
variable ins : unsigned(0 to inputs'length-1) := inputs;
variable chs : unsigned(0 to choices'length-1) := choices;
variable ch : unsigned(0 to sel'length-1);
variable choice_index : integer := 0;
variable result : unsigned(0 to size-1);
variable left, right : integer;
attribute SYNTHESIS_RETURN of result:variable is "muxv";
begin
for i in 0 to choices_nb'length-1 loop
for j in 1 to choices_nb(i) loop
left := choice_index*sel'length;
right := (choice_index+1)*sel'length;
for k in left to right loop
ch(k-left) := chs(k);
end loop;
--ch := chs (choice_index*sel'length to
-- (choice_index+1)*sel'length);
if (sel = ch) then
left := i * size;
right := (i+1)*size-1;
for k in left to right loop
result(k-left) := ins(k);
end loop;
--result := ins (i*size to (i+1)*size-1);
return result;
end if;
choice_index := choice_index + 1;
end loop;
end loop;
left := (choices_nb'length-1)*size;
right := choices_nb'length*size-1;
for j in left to right loop
result(j-left) := ins(j);
end loop;
--result := ins ((choices_nb'length-1)*size to choices_nb'length*size-1);
return result;
end;
function lat_s
(input : std_logic;
clk : std_logic;
output : std_logic) return std_logic is
variable result : std_logic;
attribute SYNTHESIS_RETURN of result:variable is "lat";
begin
if (clk = '1') then
result := input;
return result;
else
result := output;
return result;
end if;
end;
function lat_v
(input : unsigned;
clk : std_logic;
output: unsigned) return unsigned is
variable result : unsigned(output'range);
attribute SYNTHESIS_RETURN of result:variable is "lat";
begin
if (clk = '1') then
result := input;
return result;
else
result := output;
return result;
end if;
end;
function tri_s
(input : std_logic;
control : std_logic) return std_logic is
variable result : std_logic;
attribute SYNTHESIS_RETURN of result:variable is "tri";
begin
if (control = '1') then
result := input;
return result;
else
result := 'Z';
return result;
end if;
end;
function tri_v
(input : unsigned;
control : std_logic) return unsigned is
variable result : unsigned(input'range);
attribute SYNTHESIS_RETURN of result:variable is "tri";
begin
if (control = '1') then
result := input;
return result;
else
result := (others => 'Z');
return result;
end if;
end;
--
-- Arithmetic, other functions missing from ieee.std_logic_arith
--
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
TYPE stdlogic_boolean_table IS ARRAY(std_ulogic, std_ulogic) OF BOOLEAN;
CONSTANT eq_table : stdlogic_boolean_table := (
--
----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
--
----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | D |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1D :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H D |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
VARIABLE result : STD_LOGIC ;
-- Arithmetic addition of two logic types. Works as XOR.
ATTRIBUTE synthesis_return OF result:VARIABLE IS "XOR" ;
BEGIN
result := xor_table( arg1, arg2 );
RETURN result ;
END "+";
FUNCTION "-" ( arg1, arg2 : std_logic ) RETURN std_logic IS
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- Arithmetic addition of logic types. Same as XOR.
VARIABLE result : std_logic ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "XOR" ;
BEGIN
result := xor_table( arg1, arg2 );
RETURN result ;
END "-";
FUNCTION zxt( q : UNSIGNED; i : INTEGER ) RETURN UNSIGNED IS
VARIABLE qs : UNSIGNED (1 TO i);
VARIABLE qt : UNSIGNED (1 TO q'length);
-- Hidden function. Synthesis directives are present in its callers
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>'0');
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN IS
-- Equal for two logic types
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "EQ" ;
BEGIN
result := eq_table( l, r );
RETURN result ;
END;
FUNCTION eq ( l,r : UNSIGNED ) RETURN BOOLEAN IS
CONSTANT ml : INTEGER := maximum( l'length, r'length );
VARIABLE lt : UNSIGNED ( 1 TO ml );
VARIABLE rt : UNSIGNED ( 1 TO ml );
-- Arithmetic Equal for two Unsigned vectors
VARIABLE result : BOOLEAN ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "EQ" ;
BEGIN
lt := zxt( l, ml );
rt := zxt( r, ml );
FOR i IN lt'range LOOP
IF NOT eq( lt(i), rt(i) ) THEN
result := FALSE ;
RETURN result;
END IF;
END LOOP;
RETURN TRUE;
END;
FUNCTION eq ( l,r : SIGNED ) RETURN BOOLEAN IS
CONSTANT len : INTEGER := maximum( l'length, r'length );
VARIABLE lt, rt : UNSIGNED ( len-1 downto 0 ) := (OTHERS => '0');
-- Arithmetic Equal for two Signed vectors
VARIABLE result : BOOLEAN ;
ATTRIBUTE is_signed OF l:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF r:CONSTANT IS TRUE ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "EQ" ;
BEGIN
assert l'length > 1 AND r'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
lt := (OTHERS => l(l'left)) ;
lt(l'length - 1 DOWNTO 0) := UNSIGNED(l);
rt := (OTHERS => r(r'left)) ;
rt(r'length - 1 DOWNTO 0) := UNSIGNED(r);
result := (eq( lt, rt ));
RETURN result ;
END;
FUNCTION "not" ( arg1 : SIGNED ) RETURN SIGNED IS
VARIABLE result : SIGNED ( arg1'RANGE ) := (Others => 'X');
-- Vector-wide NOT
-- Synthesizable as is.
ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOT" ;
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "not" ( arg1 : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE result : UNSIGNED ( arg1'RANGE ) := (Others => 'X');
-- Vector-wide NOT
-- Synthesizable as is.
ATTRIBUTE synthesis_return OF result:VARIABLE IS "NOT" ;
begin
for i in result'range loop
result(i) := not_table( arg1(i) );
end loop;
return result;
end "not";
FUNCTION "and" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
-- Vector-wide AND with zero-extend
ATTRIBUTE synthesis_return OF res:VARIABLE IS "AND" ;
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := and_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "and";
FUNCTION "nand" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
-- Vector-wide NAND with zero-extend
ATTRIBUTE synthesis_return OF res:VARIABLE IS "NAND" ;
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( and_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nand";
FUNCTION "or" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
-- Vector-wide OR with zero-extend
ATTRIBUTE synthesis_return OF res:VARIABLE IS "OR" ;
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := or_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "or";
FUNCTION "nor" ( arg1,arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
-- Vector-wide NOR with zero-extend
ATTRIBUTE synthesis_return OF res:VARIABLE IS "NOR" ;
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( or_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "nor";
FUNCTION "and" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
-- Vector-wide AND with sign extend
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF arg2:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF answer:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF answer:VARIABLE IS "AND" ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a and b);
RETURN (answer);
end "and";
FUNCTION "nand" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
-- Vector-wide NAND with sign extend
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF arg2:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF answer:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF answer:VARIABLE IS "NAND" ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nand b);
RETURN (answer);
end "nand";
FUNCTION "or" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
-- Vector-wide OR with sign extend
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF arg2:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF answer:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF answer:VARIABLE IS "OR" ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a or b);
RETURN (answer);
end "or";
FUNCTION "nor" ( arg1,arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
-- Vector-wide NOR with sign extend
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF arg2:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF answer:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF answer:VARIABLE IS "NOR" ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a nor b);
RETURN (answer);
end "nor";
FUNCTION "xnor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
-- Vector-wide XNOR with zero extend
ATTRIBUTE synthesis_return OF res:VARIABLE IS "XNOR" ;
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := not_table( xor_table( lt(i), rt(i) ) );
END LOOP;
RETURN res;
end "xnor";
FUNCTION "xnor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
-- Vector-wide XNOR with sign extend
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF arg2:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF answer:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF answer:VARIABLE IS "XNOR" ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xnor b);
RETURN (answer);
end "xnor";
FUNCTION and_reduce(arg: SIGNED) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_AND" ;
BEGIN
result := '1';
FOR i IN arg'RANGE LOOP
result := result AND arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nand_reduce(arg: SIGNED) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NAND" ;
BEGIN
result := NOT and_reduce(arg);
RETURN result;
END;
FUNCTION and_reduce(arg: UNSIGNED) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_AND" ;
BEGIN
result := '1';
FOR i IN arg'RANGE LOOP
result := result AND arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nand_reduce(arg: UNSIGNED) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NAND" ;
BEGIN
result := NOT and_reduce(arg);
RETURN result;
END;
FUNCTION hasx( v : SIGNED ) RETURN BOOLEAN IS
-- Synthesizable as is. Normal synthesis rules apply for
-- comparison of metalogical values.
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION hasx( v : UNSIGNED ) RETURN BOOLEAN IS
-- Synthesizable as is. Normal synthesis rules apply for
-- comparison of metalogical values.
BEGIN
FOR i IN v'range LOOP
IF v(i) = '0' OR v(i) = '1' OR v(i) = 'L' OR v(i) = 'H'THEN
NULL;
ELSE
RETURN TRUE;
END IF;
END LOOP;
RETURN FALSE;
END hasx;
FUNCTION sxt( q : SIGNED; i : INTEGER ) RETURN SIGNED IS
VARIABLE qs : SIGNED (1 TO i);
VARIABLE qt : SIGNED (1 TO q'length);
-- Hidden function for synthesis; Directives set for its callers
BEGIN
qt := q;
IF i < q'length THEN
qs := qt( (q'length-i+1) TO qt'right);
ELSIF i > q'length THEN
qs := (OTHERS=>q(q'left));
qs := qs(1 TO (i-q'length)) & qt;
ELSE
qs := qt;
END IF;
RETURN qs;
END;
FUNCTION "abs" (arg1:SIGNED) RETURN SIGNED IS
constant len : integer := arg1'length;
VARIABLE answer, tmp : SIGNED( len-1 downto 0 ) := (others=>'0');
VARIABLE index : integer := len;
-- Absolute value of Signed vector
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE ;
-- Return a UNsigned vector that is abs of the input vector
ATTRIBUTE synthesis_return OF answer:VARIABLE IS "ABS" ;
BEGIN
assert arg1'length > 1
report "SIGNED vector must be atleast 2 bits wide"
severity ERROR;
IF hasx(arg1) THEN
answer := (OTHERS => 'X');
ELSIF (arg1(arg1'left) = '0' OR arg1(arg1'left) = 'L') THEN
answer := arg1;
ELSE
tmp := arg1;
lp1 : FOR i IN answer'REVERSE_RANGE LOOP
IF (tmp(i) = '1' OR tmp(i) = 'H') THEN
index := i+1;
answer(i downto 0) := tmp(i downto 0);
exit;
END IF;
END LOOP lp1;
answer(len-1 downto index) := NOT tmp(len-1 downto index);
end if;
RETURN (answer);
END ;
FUNCTION to_stdlogic (arg1:BOOLEAN) RETURN STD_LOGIC IS
-- Synthesizable as is.
BEGIN
IF(arg1) THEN
RETURN('1') ;
ELSE
RETURN('0') ;
END IF ;
END ;
FUNCTION maximum (arg1,arg2:INTEGER) RETURN INTEGER IS
BEGIN
IF(arg1 > arg2) THEN
RETURN(arg1) ;
ELSE
RETURN(arg2) ;
END IF;
END ;
FUNCTION minimum (arg1,arg2:INTEGER) RETURN INTEGER IS
BEGIN
IF(arg1 < arg2) THEN
RETURN(arg1) ;
ELSE
RETURN(arg2) ;
END IF;
END ;
FUNCTION "xor" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED IS
CONSTANT ml : integer := maximum( arg1'LENGTH, arg2'LENGTH );
VARIABLE lt : UNSIGNED ( 1 to ml );
VARIABLE rt : UNSIGNED ( 1 to ml );
VARIABLE res : UNSIGNED ( 1 to ml );
-- Vector-wide XOR with zero-extend
ATTRIBUTE synthesis_return OF res:VARIABLE IS "XOR" ;
begin
lt := zxt( arg1, ml );
rt := zxt( arg2, ml );
FOR i IN res'RANGE LOOP
res(i) := xor_table( lt(i), rt(i) );
END LOOP;
RETURN res;
end "xor";
FUNCTION "xor" ( arg1, arg2 : SIGNED ) RETURN SIGNED IS
CONSTANT len : INTEGER := maximum(arg1'length,arg2'length) ;
VARIABLE a,b : UNSIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
VARIABLE answer : SIGNED(len-1 DOWNTO 0) := (OTHERS => '0') ;
-- Vector-wide XOR with sign extend
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF arg2:CONSTANT IS TRUE ;
ATTRIBUTE is_signed OF answer:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF answer:VARIABLE IS "XOR" ;
BEGIN
a := (OTHERS => arg1(arg1'left)) ;
a(arg1'length - 1 DOWNTO 0) := UNSIGNED(arg1);
b := (OTHERS => arg2(arg2'left)) ;
b(arg2'length - 1 DOWNTO 0) := UNSIGNED(arg2);
answer := SIGNED(a xor b);
RETURN (answer);
end "xor";
FUNCTION shift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
-- Hidden function. Synthesis directives set for its callers.
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
FUNCTION shift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
-- Hidden function. Synthesis directives set for its callers.
BEGIN
FOR i IN (v'left+1) TO v'right LOOP
v1(i-1) := v(i);
END LOOP;
v1(v1'right) := '0';
RETURN v1;
END shift;
FUNCTION rshift( v : UNSIGNED ) RETURN UNSIGNED IS
VARIABLE v1 : UNSIGNED( v'range );
-- Hidden function for synthesis; Directives set for its callers
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION rshift( v : SIGNED ) RETURN SIGNED IS
VARIABLE v1 : SIGNED( v'range );
-- Hidden function for synthesis; Directives set for its callers
BEGIN
FOR i IN v'left TO v'right-1 LOOP
v1(i+1) := v(i);
END LOOP;
v1(v1'left) := '0';
RETURN v1;
END rshift;
FUNCTION "/" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
VARIABLE quote : UNSIGNED(1 TO ml) := (OTHERS=>'X');
VARIABLE tmp : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
VARIABLE n : UNSIGNED(0 TO ml+1) := (OTHERS=>'0');
-- Division of Unsigned vectors.
ATTRIBUTE synthesis_return OF quote:VARIABLE IS "DIV" ;
BEGIN
if (eq(r,"0")) then
ASSERT false
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
ELSIF NOT (hasx(l) OR hasx(r)) THEN
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
n := (OTHERS=>'0');
n(n'right) := '1';
WHILE rt <= lt LOOP
rt := shift(rt);
n := shift(n);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
n := rshift(n);
tmp := tmp + n;
END LOOP;
quote := tmp(2 TO ml+1);
END IF;
RETURN quote;
END "/";
FUNCTION "MOD" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
-- Modulo with unsigned vectors
VARIABLE result : UNSIGNED(2 to ml+1) := (OTHERS=>'X');
ATTRIBUTE synthesis_return OF result:VARIABLE IS "MOD" ;
BEGIN
if (eq(r,"00")) then
ASSERT false
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
ELSIF NOT (hasx(l) OR hasx(r)) THEN
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
result := lt(2 TO ml+1);
END IF;
RETURN result ;
END "MOD";
FUNCTION "REM" (l, r :UNSIGNED) RETURN UNSIGNED IS
CONSTANT ml : INTEGER := maximum(l'length,r'length);
VARIABLE lt : UNSIGNED(0 TO ml+1);
VARIABLE rt : UNSIGNED(0 TO ml+1);
-- Remainder with unsigned vectors
VARIABLE result : UNSIGNED(2 to ml+1) := (OTHERS=>'X');
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REM" ;
BEGIN
if (eq(r,"0")) then
ASSERT false
REPORT "Attempted divide by ZERO"
SEVERITY ERROR;
ELSIF NOT (hasx(l) OR hasx(r)) THEN
lt := zxt( l, ml+2 );
WHILE lt >= r LOOP
rt := zxt( r, ml+2 );
WHILE rt <= lt LOOP
rt := shift(rt);
END LOOP;
rt := rshift(rt);
lt := lt - rt;
END LOOP;
result := lt(2 TO ml+1);
END IF;
RETURN result ;
END "REM";
FUNCTION "**" (l, r :UNSIGNED) RETURN UNSIGNED IS
VARIABLE return_vector : UNSIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : UNSIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
-- Power with unsigned vectors
ATTRIBUTE synthesis_return OF return_vector:VARIABLE IS "POWER" ;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := conv_integer(r);
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
FUNCTION "**" (l, r :SIGNED) RETURN SIGNED IS
VARIABLE return_vector : SIGNED(l'range) := (OTHERS=>'0');
VARIABLE tmp : SIGNED(1 TO (2 * l'length)) := (OTHERS=>'0');
CONSTANT lsh_l : INTEGER := l'length+1;
CONSTANT lsh_r : INTEGER := 2 * l'length;
VARIABLE pow : INTEGER;
-- Power with signed vectors
ATTRIBUTE is_signed OF l:CONSTANT IS TRUE;
ATTRIBUTE is_signed OF r:CONSTANT IS TRUE;
-- Return a signed vector that is power of the input vectors
ATTRIBUTE is_signed OF return_vector:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF return_vector:VARIABLE IS "POWER" ;
BEGIN
IF (hasx(l) OR hasx(r)) THEN
FOR i IN return_vector'range LOOP
return_vector(i) := 'X';
END LOOP;
ELSE
pow := conv_integer(r);
tmp( tmp'right ) := '1';
FOR i IN 1 TO pow LOOP
tmp := tmp(lsh_l TO lsh_r) * l;
END LOOP;
return_vector := tmp(lsh_l TO lsh_r);
END IF;
RETURN return_vector;
END "**";
--
-- Shift Left (arithmetic) Functions
--
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
-- VHDL 93 SLA
VARIABLE result : UNSIGNED (1 to len) ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "SLA" ;
BEGIN
IF (arg2 >= len) THEN
ASSERT FALSE
REPORT "shift is further than array size."
SEVERITY WARNING ;
result := se;
ELSIF (arg2 = 0) THEN
result := arg1;
ELSE
result := ans(arg2+1 to len) & se(1 to arg2);
END IF;
RETURN result ;
END ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'right));
VARIABLE ans : SIGNED(1 to len) := arg1;
-- VHDL 93 SLA
VARIABLE result : SIGNED (1 to len) ;
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE;
ATTRIBUTE is_signed OF result:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "SLA" ;
BEGIN
IF (arg2 >= len) THEN
ASSERT FALSE
REPORT "shift is further than array size."
SEVERITY WARNING ;
result := se;
ELSIF (arg2 = 0) THEN
result := arg1;
ELSE
result := ans(arg2+1 to len) & se(1 to arg2);
END IF;
RETURN result ;
END ;
--
-- Shift Right (arithmetics) Functions
--
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : UNSIGNED(1 to len) := arg1;
-- VHDL 93 SRA
VARIABLE result : UNSIGNED (1 to len) ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "SRA" ;
BEGIN
IF (arg2 >= len) THEN
ASSERT FALSE
REPORT "shift is further than array size."
SEVERITY WARNING ;
result := (se);
ELSIF (arg2 = 0) THEN
result := (arg1);
ELSE
result := (se(1 to arg2) & ans(1 to len-arg2));
END IF;
RETURN result ;
END ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => arg1(arg1'left));
VARIABLE ans : SIGNED(1 to len) := arg1;
-- VHDL 93 SRA
VARIABLE result : SIGNED (1 to len) ;
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE;
ATTRIBUTE is_signed OF result:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "SRA" ;
BEGIN
IF (arg2 >= len) THEN
ASSERT FALSE
REPORT "shift is further than array size."
SEVERITY WARNING ;
result := (se);
ELSIF (arg2 = 0) THEN
result := (arg1);
ELSE
result := (se(1 to arg2) & ans(1 to len-arg2));
END IF;
RETURN result ;
END ;
--
-- Shift Left (logical) Functions
--
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others =>'0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
-- VHDL 93 SLL
VARIABLE result : UNSIGNED (1 to len) ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "SLL" ;
BEGIN
IF (arg2 >= len) THEN
ASSERT FALSE
REPORT "shift is further than array size."
SEVERITY WARNING ;
result := (se);
ELSIF (arg2 = 0) THEN
result := (arg1);
ELSE
result := (ans(arg2+1 to len) & se(1 to arg2));
END IF;
RETURN result ;
END ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others =>'0');
VARIABLE ans : SIGNED(1 to len) := arg1;
-- VHDL 93 SLL
VARIABLE result : SIGNED (1 to len) ;
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE;
ATTRIBUTE is_signed OF result:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "SLL" ;
BEGIN
IF (arg2 >= len) THEN
ASSERT FALSE
REPORT "shift is further than array size."
SEVERITY WARNING ;
result := (se);
ELSIF (arg2 = 0) THEN
result := (arg1);
ELSE
result := (ans(arg2+1 to len) & se(1 to arg2));
END IF;
RETURN result ;
END ;
--
-- Shift Right (logical) Functions
--
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : UNSIGNED(1 to len) := (others => '0');
VARIABLE ans : UNSIGNED(1 to len) := arg1;
-- VHDL 93 SRL
VARIABLE result : UNSIGNED (1 to len) ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "SRL" ;
BEGIN
IF (arg2 >= len) THEN
ASSERT FALSE
REPORT "shift is further than array size."
SEVERITY WARNING ;
result := (se);
ELSIF (arg2 = 0) THEN
result := (arg1);
ELSE
result := (se(1 to arg2) & ans(1 to len-arg2));
END IF;
RETURN result ;
END ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT se : SIGNED(1 to len) := (others => '0');
VARIABLE ans : SIGNED(1 to len) := arg1;
-- VHDL 93 SRL
VARIABLE result : SIGNED (1 to len) ;
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE;
ATTRIBUTE is_signed OF result:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "SRL" ;
BEGIN
IF (arg2 >= len) THEN
ASSERT FALSE
REPORT "shift is further than array size."
SEVERITY WARNING ;
result := (se);
ELSIF (arg2 = 0) THEN
result := (arg1);
ELSE
result := (se(1 to arg2) & ans(1 to len-arg2));
END IF;
RETURN result ;
END ;
--
-- Rotate Left (Logical) Functions
--
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
-- VHDL 93 ROL
VARIABLE result : UNSIGNED (1 to len) ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "ROL" ;
BEGIN
ASSERT arg2 <= len
REPORT "rotate is further than array size."
SEVERITY WARNING ;
IF (marg2 = 0) THEN
result := (arg1);
ELSE
result := (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
RETURN result ;
END ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
-- VHDL 93 ROL
VARIABLE result : SIGNED (1 to len) ;
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE;
ATTRIBUTE is_signed OF result:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "ROL" ;
BEGIN
ASSERT arg2 <= len
REPORT "rotate is further than array size."
SEVERITY WARNING ;
IF (marg2 = 0) THEN
result := (arg1);
ELSE
result := (ans(marg2+1 to len) & ans(1 to marg2));
END IF;
RETURN result ;
END ;
--
-- Rotate Right (Logical) Functions
--
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : UNSIGNED(1 to len) := arg1;
-- VHDL 93 ROR
VARIABLE result : UNSIGNED (1 to len) ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "ROR" ;
BEGIN
ASSERT arg2 <= len
REPORT "rotate is further than array size."
SEVERITY WARNING ;
IF (marg2 = 0) THEN
result := (arg1);
ELSE
result := (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
RETURN result ;
END ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED IS
CONSTANT len : INTEGER := arg1'length ;
CONSTANT marg2 : integer := arg2 mod len;
VARIABLE ans : SIGNED(1 to len) := arg1;
-- VHDL 93 ROR
VARIABLE result : SIGNED (1 to len) ;
ATTRIBUTE is_signed OF arg1:CONSTANT IS TRUE;
ATTRIBUTE is_signed OF result:VARIABLE IS TRUE ;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "ROR" ;
BEGIN
ASSERT arg2 <= len
REPORT "rotate is further than array size."
SEVERITY WARNING ;
IF (marg2 = 0) THEN
result := (arg1);
ELSE
result := (ans(len-marg2+1 to len) & ans(1 to len-marg2));
END IF;
RETURN result ;
END ;
--
-- In general, objects in this package are required to be functions.
-- For synthesizability reasons, we want the "flipflop" functions to be
-- procedures. There is a special kludge in the rtl netlister to let
-- this work.
--
procedure flipflop
(signal input : in std_logic;
signal clk : in std_logic;
signal output : out std_logic) is
attribute SYNTHESIS_RETURN of output:signal is "flipflop";
begin
if (clk'last_value = '0' and clk = '1') then
output <= input;
end if;
end;
procedure flipflop
(signal input : in unsigned;
signal clk : in std_logic;
signal output : out unsigned) is
attribute SYNTHESIS_RETURN of output:signal is "flipflop";
begin
if (clk'last_value = '0' and clk = '1') then
output <= input;
end if;
end;
procedure flipflop
(signal input : in std_logic;
signal clk : in std_logic;
signal output : out std_logic;
signal rst : in std_logic;
signal value : in std_logic) is
attribute SYNTHESIS_RETURN of output:signal is "flipflop";
begin
if (rst = '1') then
output <= value;
elsif (clk'event and clk = '1') then
output <= input;
end if;
end;
procedure flipflop
(signal input : in unsigned;
signal clk : in std_logic;
signal output : out unsigned;
signal rst : in std_logic;
signal value : in unsigned) is
attribute SYNTHESIS_RETURN of output:signal is "flipflop";
begin
if (rst = '1') then
output <= value;
elsif (clk'event and clk = '1') then
output <= input;
end if;
end;
--
-- This is used in the special case when we need to pick a vector that
-- has been changed into a constant. This is because the VHDL language
-- doesn't allow one to say "bits"[index]
--
function readindex
(input : unsigned;
index : natural) return std_logic is
variable result : std_logic;
attribute SYNTHESIS_RETURN of result:variable is "readindex";
begin
result := input(index);
return result;
end;
--
-- The following procedures insert n consecutive wait until edge
-- statements into the process. 'phase' gives the active edge ie it
-- should be either '1' or '0'
--
procedure wait_clock_cycles
(constant n : natural;
signal clk : in std_logic;
constant phase : in std_logic) is
-- pragma built_in synch
begin
for i in 1 to n loop
wait until clk'event and clk=phase;
end loop;
end;
procedure wait_clock_cycles
(constant n : natural;
signal clk : in bit;
constant phase : in bit) is
-- pragma built_in synch
begin
for i in 1 to n loop
wait until clk'event and clk=phase;
end loop;
end;
end FUNCS;
|
apache-2.0
|
chipsalliance/Surelog
|
third_party/tests/YosysTestSuite/sva/basic05.vhd
|
11
|
473
|
library ieee;
use ieee.std_logic_1164.all;
entity demo is
port (
clock : in std_logic;
ctrl : in std_logic;
x : out std_logic
);
end entity;
architecture rtl of demo is
signal read : std_logic := '0';
signal write : std_logic := '0';
signal ready : std_logic := '0';
begin
process (clock) begin
if (rising_edge(clock)) then
read <= not ctrl;
write <= ctrl;
ready <= write;
end if;
end process;
x <= read xor write xor ready;
end architecture;
|
apache-2.0
|
thinkoco/de1_soc_opencl
|
de1soc_sharedonly_vga/system/system_inst.vhd
|
1
|
20729
|
component system is
port (
clk_50_clk : in std_logic := 'X'; -- clk
kernel_clk_clk : out std_logic; -- clk
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
reset_50_reset_n : in std_logic := 'X'; -- reset_n
acl_iface_alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
acl_iface_alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(31 downto 0); -- vid_data
acl_iface_alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
acl_iface_alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
acl_iface_alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
acl_iface_clock_130_clk : in std_logic := 'X' -- clk
);
end component system;
u0 : component system
port map (
clk_50_clk => CONNECTED_TO_clk_50_clk, -- clk_50.clk
kernel_clk_clk => CONNECTED_TO_kernel_clk_clk, -- kernel_clk.clk
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CLK, -- peripheral.hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD => CONNECTED_TO_peripheral_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK => CONNECTED_TO_peripheral_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK => CONNECTED_TO_peripheral_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP => CONNECTED_TO_peripheral_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR => CONNECTED_TO_peripheral_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT => CONNECTED_TO_peripheral_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX => CONNECTED_TO_peripheral_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX => CONNECTED_TO_peripheral_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_peripheral_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
reset_50_reset_n => CONNECTED_TO_reset_50_reset_n, -- reset_50.reset_n
acl_iface_alt_vip_itc_0_clocked_video_vid_clk => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_clk, -- acl_iface_alt_vip_itc_0_clocked_video.vid_clk
acl_iface_alt_vip_itc_0_clocked_video_vid_data => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_data, -- .vid_data
acl_iface_alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_underflow, -- .underflow
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid, -- .vid_datavalid
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync, -- .vid_v_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync, -- .vid_h_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_f => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_f, -- .vid_f
acl_iface_alt_vip_itc_0_clocked_video_vid_h => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_h, -- .vid_h
acl_iface_alt_vip_itc_0_clocked_video_vid_v => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_v, -- .vid_v
acl_iface_clock_130_clk => CONNECTED_TO_acl_iface_clock_130_clk -- acl_iface_clock_130.clk
);
|
apache-2.0
|
zhlinh/vhdl_course
|
Assignment/FREQ_CNT/D_LATCH.vhd
|
1
|
720
|
--Latch
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY D_LATCH IS
PORT( LATCH_EN: IN STD_LOGIC;
D1_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D1_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY D_LATCH;
ARCHITECTURE ART1 OF D_LATCH IS
BEGIN
PROCESS(LATCH_EN)
BEGIN
IF (LATCH_EN='1') THEN
D1_OUT <= D1_IN;
D2_OUT <= D2_IN;
D3_OUT <= D3_IN;
ELSE
D1_OUT <= "0000";
D2_OUT <= "0000";
D3_OUT <= "0000";
END IF;
END PROCESS;
END ARCHITECTURE ART1;
|
apache-2.0
|
SurajRepo/frapid
|
src/Frapid.Web/scripts/ace-1.2.2/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
apache-2.0
|
zhlinh/vhdl_course
|
Assignment/FREQ_CNT/DIV_FREQ.vhd
|
1
|
624
|
--Frequency Divider
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DIV_FREQ IS
PORT( CLK_IN_1HZ :IN STD_LOGIC;
RST :IN STD_LOGIC;
CLK_OUT_05HZ:OUT STD_LOGIC);
END ENTITY DIV_FREQ;
ARCHITECTURE ART1 OF DIV_FREQ IS
BEGIN
PROCESS (CLK_IN_1HZ,RST)
VARIABLE CLK_OUT_TEMP:STD_LOGIC_VECTOR (1 DOWNTO 0):="00";
BEGIN
IF(RST='1')THEN
CLK_OUT_TEMP:="00";
ELSE IF(CLK_IN_1HZ 'EVENT AND CLK_IN_1HZ='1')THEN
CLK_OUT_TEMP := CLK_OUT_TEMP + "01";
END IF;
END IF;
CLK_OUT_05HZ <= CLK_OUT_TEMP(0);
END PROCESS;
END ARCHITECTURE ART1;
|
apache-2.0
|
zhlinh/vhdl_course
|
Assignment/IMG_LSB/RGB2YUV.vhd
|
1
|
1678
|
--RGB2YUV entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.MYTYPE.ALL;
ENTITY RGB2YUV IS
PORT(RESET: IN STD_LOGIC;
CLK: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
Y_OUT: OUT COLOR;
U_OUT: OUT COLOR;
V_OUT: OUT COLOR);
END ENTITY RGB2YUV;
ARCHITECTURE ART1 OF RGB2YUV IS
BEGIN
CLOCK: PROCESS(CLK,RESET,ENABLE)
VARIABLE Y_REG: COLOR;
VARIABLE U_REG: COLOR;
VARIABLE V_REG: COLOR;
VARIABLE TEMP: INTEGER RANGE -512 TO 512;
BEGIN
IF(RESET='1' OR ENABLE='0') THEN
Y_OUT<=0;
U_OUT<=0;
V_OUT<=0;
ELSIF(CLK'EVENT AND CLK='1') THEN
TEMP:=(299*R_IN + 587*G_IN + 114*B_IN)/1000;
--调整
IF(TEMP<0) THEN
Y_REG:=0;
ELSIF(TEMP>255) THEN
Y_REG:=255;
ELSE
Y_REG:=TEMP;
END IF;
TEMP:=(-169*R_IN - 331*G_IN + 500*B_IN)/1000 + 128;
--调整
IF(TEMP<0) THEN
U_REG:=0;
ELSIF(TEMP>255) THEN
U_REG:=255;
ELSE
U_REG:=TEMP;
END IF;
TEMP:=(500*R_IN - 419*G_IN - 81*B_IN)/1000 + 128;
--调整
IF(TEMP<0) THEN
V_REG:=0;
ELSIF(TEMP>255) THEN
V_REG:=255;
ELSE
V_REG:=TEMP;
END IF;
Y_OUT<=Y_REG;
U_OUT<=U_REG;
V_OUT<=V_REG;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
|
apache-2.0
|
zhlinh/vhdl_course
|
Assignment/LED_CNT/LED_DEC.vhd
|
1
|
813
|
--LED Decoder Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED_DEC IS
PORT ( NUM : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END ENTITY LED_DEC;
ARCHITECTURE ART1 OF LED_DEC IS
BEGIN
PROCESS(NUM)
BEGIN
CASE(NUM) IS
WHEN "0000" =>
DOUT <= "1111110";
WHEN "0001" =>
DOUT <= "0110000";
WHEN "0010" =>
DOUT <= "1101101";
WHEN "0011" =>
DOUT <= "1111001";
WHEN "0100" =>
DOUT <= "0110011";
WHEN "0101" =>
DOUT <= "1011011";
WHEN "0110" =>
DOUT <= "1011111";
WHEN "0111" =>
DOUT <= "1110000";
WHEN "1000" =>
DOUT <= "1111111";
WHEN "1001" =>
DOUT <= "1111011";
WHEN OTHERS =>
DOUT <= (OTHERS=> '0');
END CASE;
END PROCESS;
END ARCHITECTURE ART1;
|
apache-2.0
|
sudov/options-accel
|
final_design/verilog/ieee_FP_pkg/fixed_float_types_c.vhd
|
6
|
1411
|
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 1.1 $
-- Date : $Date: 2010/09/22 18:44:20 $
-- --------------------------------------------------------------------
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;
|
apache-2.0
|
hoangt/PoC
|
src/io/io_Debounce.vhdl
|
2
|
5080
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Module: Debounce module for BITS many bouncing input pins.
--
-- Description:
-- ------------------------------------
-- This module debounces several input pins preventing input changes
-- following a previous one within the configured BOUNCE_TIME to pass.
-- Internally, the forwarded state is locked for, at least, this BOUNCE_TIME.
-- As the backing timer is restarted on every input fluctuation, the next
-- passing input update must have seen a stabilized input.
--
-- The parameter COMMON_LOCK uses a single internal timer for all processed
-- inputs. Thus, all inputs must stabilize before any one may pass changed.
-- This option is usually fully acceptable for user inputs such as push buttons.
--
-- The parameter ADD_INPUT_SYNCHRONIZERS triggers the optional instantiation
-- of a two-FF input synchronizer on each input bit.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
entity io_Debounce is
generic (
CLOCK_FREQ : freq;
BOUNCE_TIME : time;
BITS : positive := 1;
ADD_INPUT_SYNCHRONIZERS : boolean := true;
COMMON_LOCK : boolean := false
);
port (
Clock : in std_logic;
Reset : in std_logic := '0';
Input : in std_logic_vector(BITS-1 downto 0);
Output : out std_logic_vector(BITS-1 downto 0)
);
end;
architecture rtl of io_Debounce is
-- Number of required locking cycles
constant LOCK_COUNT_X : integer := TimingToCycles(BOUNCE_TIME, CLOCK_FREQ) - 1;
-- Input Refinements
signal sync : std_logic_vector(Input'range); -- Synchronized
signal prev : std_logic_vector(Input'range) := (others => '0'); -- Delayed
signal active : std_logic_vector(Input'range); -- Allow Output Updates
begin
-----------------------------------------------------------------------------
-- Input Synchronization
genNoSync: if not ADD_INPUT_SYNCHRONIZERS generate
sync <= Input;
end generate;
genSync: if ADD_INPUT_SYNCHRONIZERS generate
sync_i : entity PoC.sync_Bits
generic map (
BITS => BITS
)
port map (
Clock => Clock, -- Clock to be synchronized to
Input => Input, -- Data to be synchronized
Output => sync -- synchronised data
);
end generate;
-----------------------------------------------------------------------------
-- Bounce Filter
process(Clock)
begin
if rising_edge(Clock) then
prev <= sync;
if (Reset = '1') then
Output <= sync;
else
for i in Output'range loop
if active(i) = '1' then
Output(i) <= sync(i);
end if;
end loop;
end if;
end if;
end process;
genNoLock: if LOCK_COUNT_X <= 0 generate
active <= (others => '1');
end generate genNoLock;
genLock: if LOCK_COUNT_X > 0 generate
constant LOCKS : positive := ite(COMMON_LOCK, 1, BITS);
signal toggle : std_logic_vector(LOCKS-1 downto 0);
signal locked : std_logic_vector(LOCKS-1 downto 0);
begin
genOneLock: if COMMON_LOCK generate
toggle(0) <= '1' when prev /= sync else '0';
active <= (others => not locked(0));
end generate genOneLock;
genManyLocks: if not COMMON_LOCK generate
toggle <= prev xor sync;
active <= not locked;
end generate genManyLocks;
genLocks: for i in 0 to LOCKS-1 generate
signal Lock : signed(log2ceil(LOCK_COUNT_X+1) downto 0) := (others => '0');
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Lock <= (others => '0');
else
if toggle(i) = '1' then
Lock <= to_signed(-LOCK_COUNT_X, Lock'length);
elsif locked(i) = '1' then
Lock <= Lock + 1;
end if;
end if;
end if;
end process;
locked(i) <= Lock(Lock'left);
end generate genLocks;
end generate genLock;
end;
|
apache-2.0
|
hoangt/PoC
|
src/io/uart/uart_ft245.vhdl
|
1
|
7680
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- ===========================================================================
--
-- Authors: Peter Reichel
-- Jan Schirok
-- Steffen Koehler
--
-- Module: UART controller for FTDI FT245M UART-over-USB converter.
--
-- License:
-- ===========================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity uart_ft245 is
generic (
CLK_FREQ : positive
);
port (
-- common signals
clk : in std_logic;
rst : in std_logic;
-- send data
snd_ready : out std_logic;
snd_strobe : in std_logic;
snd_data : in std_logic_vector(7 downto 0);
-- receive data
rec_strobe : out std_logic;
rec_data : out std_logic_vector(7 downto 0);
-- connection to ft245
ft245_data : inout std_logic_vector(7 downto 0);
ft245_rdn : out std_logic;
ft245_wrn : out std_logic;
ft245_rxfn : in std_logic;
ft245_txen : in std_logic;
ft245_pwrenn : in std_logic
);
end entity;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of uart_ft245 is
-- clock frequency (MHz)
constant CLK_FREQ_MHZ : integer := CLK_FREQ / 1000000;
-- FT245 communication delay cycles (minimum delay is 50 ns = 1/20 us)
constant DELAY_CYCLES : integer := CLK_FREQ_MHZ / 20;
-- delay register width
constant DELAY_WIDTH : integer := log2ceilnz(DELAY_CYCLES + 1);
-- delay register load value
constant DELAY_LOAD : unsigned(DELAY_WIDTH-1 downto 0) :=
to_unsigned(DELAY_CYCLES, DELAY_WIDTH);
-- delay register
signal reg_delay : unsigned(DELAY_WIDTH-1 downto 0);
-- FSM
type tState is ( IDLE, RD1, RD2, RD3, RD4, WR1, WR2, WR3, WR4 );
signal fsm_state : tState := IDLE;
signal fsm_nextstate : tState;
-- registers
signal reg_data_snd : std_logic_vector(7 downto 0);
signal reg_data_rec : std_logic_vector(7 downto 0);
signal reg_ld_rec : std_logic;
signal reg_dto_b : std_logic := '1'; -- low-active
signal reg_wr_b : std_logic := '1'; -- low-active
signal reg_rd_b : std_logic := '1'; -- low-active
signal ff_susp : std_logic := '1'; -- low-active
signal ff_rxf : std_logic := '1'; -- low-active
signal ff_txe : std_logic := '1'; -- low-active
-- control signals
signal ctrl_ld_rec : std_logic;
signal ctrl_delay : std_logic;
signal ctrl_rd : std_logic;
signal ctrl_wr : std_logic;
signal ctrl_dto : std_logic;
signal data_in : std_logic_vector(7 downto 0);
begin
----------------------------------------------
-- Synchronize Inputs
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
-- Neutral PowerUp / Reset
ff_susp <= '1';
ff_rxf <= '1';
ff_txe <= '1';
else
-- Wait for Initilization to Complete
ff_susp <= ft245_pwrenn;
-- Now forward Fill Signals
ff_rxf <= ft245_rxfn;
ff_txe <= ft245_txen;
end if;
end if;
end process;
process(fsm_state, snd_strobe, reg_delay, ff_susp, ff_rxf, ff_txe)
begin
fsm_nextstate <= fsm_state;
ctrl_ld_rec <= '0';
ctrl_rd <= '0';
ctrl_wr <= '0';
ctrl_dto <= '0';
ctrl_delay <= '0';
case fsm_state is
when IDLE =>
if ff_susp = '0' then
if ff_rxf = '0' then
-- receive data
fsm_nextstate <= RD1;
elsif ff_txe = '0' and snd_strobe = '1' then
-- ok, send...
fsm_nextstate <= WR1;
end if;
end if;
when RD1 =>
-- load delay counter
ctrl_rd <= '1';
ctrl_delay <= '1';
fsm_nextstate <= RD2;
when RD2 =>
-- wait until delay counter has expired
ctrl_rd <= '1';
if reg_delay = 0 then
fsm_nextstate <= RD3;
end if;
when RD3 =>
-- data is valid now => load
ctrl_rd <= '1';
ctrl_ld_rec <= '1';
-- load delay counter again
ctrl_delay <= '1';
fsm_nextstate <= RD4;
when RD4 =>
-- wait until delay counter has expired
if reg_delay = 0 then
fsm_nextstate <= IDLE;
end if;
when WR1 =>
-- load delay counter
ctrl_dto <= '1';
ctrl_delay <= '1';
fsm_nextstate <= WR2;
when WR2 =>
-- set wr (active pulse)
ctrl_dto <= '1';
ctrl_wr <= '1';
-- wait until delay counter has expired
if reg_delay = 0 then
fsm_nextstate <= WR3;
end if;
when WR3 =>
-- clear wr (pre-charge time)
ctrl_dto <= '1';
-- load delay counter again
ctrl_delay <= '1';
fsm_nextstate <= WR4;
when WR4 =>
-- wait until delay counter has expired
if reg_delay = 0 then
fsm_nextstate <= IDLE;
end if;
end case;
end process;
----------------------------------------------
-- registers
process(clk)
begin
if rising_edge(clk) then
-- control signals
if rst = '1' then
fsm_state <= IDLE;
reg_rd_b <= '1';
reg_wr_b <= '1';
reg_dto_b <= '1';
reg_ld_rec <= '0';
else
fsm_state <= fsm_nextstate;
reg_rd_b <= not ctrl_rd;
reg_wr_b <= not ctrl_wr;
reg_dto_b <= not ctrl_dto;
reg_ld_rec <= ctrl_ld_rec;
end if;
-- delay counter
if ctrl_delay = '1' then
reg_delay <= DELAY_LOAD;
else
reg_delay <= reg_delay - 1;
end if;
-- received data
if ctrl_ld_rec = '1' then
reg_data_rec <= data_in;
end if;
-- data to send
if snd_strobe = '1' then
reg_data_snd <= snd_data;
end if;
end if;
end process;
----------------------------------------------
-- tristate driver and output assignments
ft245_data <= reg_data_snd when reg_dto_b = '0' else (others => 'Z');
data_in <= ft245_data;
ft245_rdn <= reg_rd_b;
ft245_wrn <= reg_wr_b;
rec_data <= reg_data_rec;
rec_strobe <= reg_ld_rec;
snd_ready <= ff_rxf and not ff_txe and not ff_susp
when fsm_state = IDLE else '0';
end rtl;
|
apache-2.0
|
hoangt/PoC
|
src/io/ddrio/ddrio_inout.vhdl
|
2
|
3850
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Chip-Specific DDR Input and Output Registers
--
-- Description:
-- ------------------------------------
-- Instantiates chip-specific DDR input and output registers.
--
-- "OutputEnable" (Tri-State) is high-active. It is automatically inverted if
-- necessary. If an output enable is not required, you may save some logic by
-- setting NO_OUTPUT_ENABLE = true. However, "OutputEnable" must be set to '1'.
--
-- Both data "DataOut_high/low" as well as "OutputEnable" are sampled with
-- the rising_edge(Clock) from the on-chip logic. "DataOut_high" is brought
-- out with this rising edge. "DataOut_low" is brought out with the falling
-- edge.
--
-- "Pad" must be connected to a PAD because FPGAs only have these registers in
-- IOBs.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.config.all;
use PoC.ddrio.all;
entity ddrio_out is
generic (
NO_OUTPUT_ENABLE : BOOLEAN := false;
BITS : POSITIVE;
INIT_VALUE_OUT : BIT_VECTOR := "1";
INIT_VALUE_IN_HIGH : BIT_VECTOR := "1";
INIT_VALUE_IN_LOW : BIT_VECTOR := "1"
);
port (
Clock : in STD_LOGIC;
ClockEnable : in STD_LOGIC;
OutputEnable : in STD_LOGIC;
DataOut_high : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataOut_low : in STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_high : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
DataIn_low : out STD_LOGIC_VECTOR(BITS - 1 downto 0);
Pad : inout STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of ddrio_out is
begin
assert (VENDOR = VENDOR_XILINX) or (VENDOR = VENDOR_ALTERA)
report "PoC.io.ddrio.inout is not implemented for given DEVICE."
severity FAILURE;
genXilinx : if (VENDOR = VENDOR_XILINX) generate
inst : ddrio_inout_xilinx
generic map (
NO_OUTPUT_ENABLE => NO_OUTPUT_ENABLE,
BITS => BITS,
INIT_VALUE_OUT => INIT_VALUE_OUT,
INIT_VALUE_IN_HIGH => INIT_VALUE_IN_HIGH,
INIT_VALUE_IN_LOW => INIT_VALUE_IN_LOW
)
port map (
Clock => Clock,
ClockEnable => ClockEnable,
OutputEnable => OutputEnable,
DataOut_high => DataOut_high,
DataOut_low => DataOut_low,
DataIn_high => DataIn_high,
DataIn_low => DataIn_low,
Pad => Pad
);
end generate;
genAltera : if (VENDOR = VENDOR_ALTERA) generate
inst : ddrio_inout_altera
generic map (
BITS => BITS
)
port map (
Clock => Clock,
ClockEnable => ClockEnable,
OutputEnable => OutputEnable,
DataOut_high => DataOut_high,
DataOut_low => DataOut_low,
DataIn_high => DataIn_high,
DataIn_low => DataIn_low,
Pad => Pad
);
end generate;
end architecture;
|
apache-2.0
|
IAIK/ascon_hardware
|
asconv1/ascon_128_xlow_area/ascon_shift_register_w_overwrite.vhdl
|
1
|
3013
|
-------------------------------------------------------------------------------
-- Title : Ascon Shift Register
-- Project :
-------------------------------------------------------------------------------
-- File : ascon_shift_register.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2014-05-20
-- Last update: 2014-05-23
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-20 1.0 Hannes Gross Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon_shift_register_w_overwrite is
generic (
RESET_VALUE : std_logic_vector(63 downto 0) := x"0000000000000000";
DATA_WIDTH : integer := 64);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
OverwriteENxSI : in std_logic;
OverwriteDataxSI : in std_logic_vector(DATA_WIDTH-1 downto 0);
ShiftEnablexSI : in std_logic;
ShiftRegINxDI : in std_logic;
ShiftRegOUTxDO : out std_logic_vector(DATA_WIDTH-1 downto 0));
end entity ascon_shift_register_w_overwrite;
architecture structural of ascon_shift_register_w_overwrite is
signal DataxDP : std_logic_vector(DATA_WIDTH-1 downto 0);
begin -- architecture structural
ShiftRegOUTxDO <= DataxDP;
-- purpose: Left shift each cycle
-- type : sequential
-- inputs : ClkxCI, RstxRBI
-- outputs: DataOUTxDO
shift_p: process (ClkxCI, RstxRBI) is
begin -- process shift_p
if RstxRBI = '0' then -- asynchronous reset (active low)
DataxDP <= RESET_VALUE;
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
if OverwriteENxSI = '1' then -- Overwrite register
DataxDP <= OverwriteDataxSI;
elsif ShiftEnablexSI = '1' then
DataxDP <= DataxDP(DATA_WIDTH-2 downto 0) & ShiftRegINxDI; -- shift left
end if;
end if;
end process shift_p;
end architecture structural;
|
apache-2.0
|
hoangt/PoC
|
src/io/uart/uart_fifo.vhdl
|
1
|
9997
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: UART Wrapper with Embedded FIFOs and Optional Flow Control
--
-- Description:
-- ------------------------------------
-- Small FIFOs are included in this module, if larger or asynchronous
-- transmit / receive FIFOs are required, then they must be connected
-- externally.
--
-- old comments:
-- UART BAUD rate generator
-- bclk = bit clock is rising
-- bclk_x8 = bit clock times 8 is rising
--
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.uart.all;
entity uart_fifo is
generic (
-- Communication Parameters
CLOCK_FREQ : FREQ;
BAUDRATE : BAUD;
-- Buffer Dimensioning
TX_MIN_DEPTH : positive := 16;
TX_ESTATE_BITS : natural := 0;
RX_MIN_DEPTH : positive := 16;
RX_FSTATE_BITS : natural := 0;
-- Flow Control
FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE;
SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q
SWFC_XON_TRIGGER : real := 0.0625;
SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13"; -- ^S
SWFC_XOFF_TRIGGER : real := 0.75
);
port (
Clock : in std_logic;
Reset : in std_logic;
-- FIFO interface
TX_put : in STD_LOGIC;
TX_Data : in STD_LOGIC_VECTOR(7 downto 0);
TX_Full : out STD_LOGIC;
TX_EmptyState : out STD_LOGIC_VECTOR(TX_ESTATE_BITS - 1 downto 0);
RX_Valid : out STD_LOGIC;
RX_Data : out STD_LOGIC_VECTOR(7 downto 0);
RX_got : in STD_LOGIC;
RX_FullState : out STD_LOGIC_VECTOR(RX_FSTATE_BITS - 1 downto 0);
RX_Overflow : out std_logic;
-- External pins
UART_TX : out std_logic;
UART_RX : in std_logic
);
end entity;
architecture rtl of uart_fifo is
signal FC_TX_Strobe : STD_LOGIC;
signal FC_TX_Data : T_SLV_8;
signal FC_TX_got : STD_LOGIC;
signal FC_RX_put : STD_LOGIC;
signal FC_RX_Data : T_SLV_8;
signal TXFIFO_Valid : STD_LOGIC;
signal TXFIFO_Data : T_SLV_8;
signal RXFIFO_Full : STD_LOGIC;
signal TXUART_Full : STD_LOGIC;
signal RXUART_Strobe : STD_LOGIC;
signal RXUART_Data : T_SLV_8;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX_sync : STD_LOGIC;
begin
assert FALSE report "uart_fifo: BAUDRATE=: " & to_string(BAUDRATE, 3) severity NOTE;
-- ===========================================================================
-- Transmit and Receive FIFOs
-- ===========================================================================
TXFIFO : entity PoC.fifo_cc_got
generic map (
D_BITS => 8, -- Data Width
MIN_DEPTH => TX_MIN_DEPTH, -- Minimum FIFO Depth
DATA_REG => TRUE, -- Store Data Content in Registers
STATE_REG => FALSE, -- Registered Full/Empty Indicators
OUTPUT_REG => FALSE, -- Registered FIFO Output
ESTATE_WR_BITS => TX_ESTATE_BITS, -- Empty State Bits
FSTATE_RD_BITS => 0 -- Full State Bits
)
port map (
rst => Reset,
clk => Clock,
put => TX_put,
din => TX_Data,
full => TX_Full,
estate_wr => TX_EmptyState,
valid => TXFIFO_Valid,
dout => TXFIFO_Data,
got => FC_TX_got,
fstate_rd => open
);
RXFIFO : entity PoC.fifo_cc_got
generic map (
D_BITS => 8, -- Data Width
MIN_DEPTH => RX_MIN_DEPTH, -- Minimum FIFO Depth
DATA_REG => TRUE, -- Store Data Content in Registers
STATE_REG => FALSE, -- Registered Full/Empty Indicators
OUTPUT_REG => FALSE, -- Registered FIFO Output
ESTATE_WR_BITS => 0, -- Empty State Bits
FSTATE_RD_BITS => RX_FSTATE_BITS -- Full State Bits
)
port map (
rst => Reset,
clk => Clock,
put => FC_RX_put,
din => FC_RX_Data,
full => RXFIFO_Full,
estate_wr => open,
valid => RX_Valid,
dout => RX_Data,
got => RX_got,
fstate_rd => RX_FullState
);
genNOFC : if (FLOWCONTROL = UART_FLOWCONTROL_NONE) generate
signal Overflow_r : std_logic := '0';
begin
FC_TX_Strobe <= TXFIFO_Valid and not TXUART_Full;
FC_TX_Data <= TXFIFO_Data;
FC_TX_got <= FC_TX_Strobe;
FC_RX_put <= RXUART_Strobe;
FC_RX_Data <= RXUART_Data;
Overflow_r <= ffrs(q => Overflow_r, rst => Reset, set => (RXUART_Strobe and RXFIFO_Full)) when rising_edge(Clock);
RX_Overflow <= Overflow_r;
end generate;
-- ===========================================================================
-- Software Flow Control
-- ===========================================================================
genSWFC : if (FLOWCONTROL = UART_FLOWCONTROL_XON_XOFF) generate
constant XON : std_logic_vector(7 downto 0) := x"11"; -- ^Q
constant XOFF : std_logic_vector(7 downto 0) := x"13"; -- ^S
constant XON_TRIG : integer := integer(SWFC_XON_TRIGGER * real(2**RX_FSTATE_BITS));
constant XOFF_TRIG : integer := integer(SWFC_XOFF_TRIGGER * real(2**RX_FSTATE_BITS));
signal send_xoff : std_logic;
signal send_xon : std_logic;
signal set_xoff_transmitted : std_logic;
signal clr_xoff_transmitted : std_logic;
signal discard_user : std_logic;
signal set_overflow : std_logic;
-- registers
signal xoff_transmitted : std_logic;
begin
-- -- send XOFF only once when fill state goes above trigger level
-- send_xoff <= (not xoff_transmitted) when (rf_fs >= XOFF_TRIG) else '0';
-- set_xoff_transmitted <= tx_rdy when (rf_fs >= XOFF_TRIG) else '0';
--
-- -- send XON only once when receive FIFO is almost empty
-- send_xon <= xoff_transmitted when (rf_fs = XON_TRIG) else '0';
-- clr_xoff_transmitted <= tx_rdy when (rf_fs = XON_TRIG) else '0';
--
-- -- discard any user supplied XON/XOFF
-- discard_user <= '1' when (tf_dout = SWFC_XON_CHAR) or (tf_dout = SWFC_XOFF_CHAR) else '0';
--
-- -- tx / tf control
-- tx_din <= SWFC_XOFF_CHAR when (send_xoff = '1') else
-- SWFC_XON_CHAR when (send_xon = '1') else
-- tf_dout;
--
-- tx_stb <= send_xoff or send_xon or (tf_valid and (not discard_user));
-- tf_got <= (send_xoff nor send_xon) and
-- tf_valid and tx_rdy; -- always check tf_valid
--
-- -- rx / rf control
-- rf_put <= (not rf_full) and rx_dos; -- always check rf_full
-- rf_din <= rx_dout;
--
-- set_overflow <= rf_full and rx_dos;
--
-- -- registers
-- process (Clock)
-- begin -- process
-- if rising_edge(Clock) then
-- if (rst or set_xoff_transmitted) = '1' then
-- -- send a XON after reset
-- xoff_transmitted <= '1';
-- elsif clr_xoff_transmitted = '1' then
-- xoff_transmitted <= '0';
-- end if;
--
-- if rst = '1' then
-- overflow <= '0';
-- elsif set_overflow = '1' then
-- overflow <= '1';
-- end if;
-- end if;
-- end process;
end generate;
-- ===========================================================================
-- Hardware Flow Control
-- ===========================================================================
genHWFC1 : if (FLOWCONTROL = UART_FLOWCONTROL_RTS_CTS) generate
begin
end generate;
-- ===========================================================================
-- Hardware Flow Control
-- ===========================================================================
genHWFC2 : if (FLOWCONTROL = UART_FLOWCONTROL_RTR_CTS) generate
begin
end generate;
-- ===========================================================================
-- BitClock, Transmitter, Receiver
-- ===========================================================================
genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate
UART_RX_sync <= UART_RX;
end generate;
genSync: if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate
sync_i : entity PoC.sync_Bits
port map (
Clock => Clock, -- Clock to be synchronized to
Input(0) => UART_RX, -- Data to be synchronized
Output(0) => UART_RX_sync -- synchronised data
);
end generate;
-- ===========================================================================
-- BitClock, Transmitter, Receiver
-- ===========================================================================
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
TX : entity PoC.uart_tx
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
tx => UART_TX
di => FC_TX_Data,
put => FC_TX_Strobe,
ful => TXUART_Full
);
RX : entity PoC.uart_rx
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
rx => UART_RX_sync,
do => RXUART_Data,
stb => RXUART_Strobe
);
end architecture;
|
apache-2.0
|
wrousseau/a14-2-vhdl
|
Filter.vhd
|
1
|
2245
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:34:18 10/20/2014
-- Design Name:
-- Module Name: filter - arc1
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY Filter is
PORT ( clk : in STD_LOGIC;
R0 : in STD_LOGIC_VECTOR (31 downto 0);
R1 : in STD_LOGIC_VECTOR (31 downto 0);
R2 : in STD_LOGIC_VECTOR (31 downto 0);
R3 : out STD_LOGIC_VECTOR (31 downto 0)
);
end Filter;
architecture arc1 of Filter is
signal ready : STD_LOGIC := '0';
signal k0, k1, k2, k3, k4, k5, k6, k7, k8 : STD_LOGIC_VECTOR(7 downto 0);
signal result : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
COMPONENT Mask is
PORT (
ready : in STD_LOGIC;
k0, k1, k2, k3, k4, k5, k6, k7, k8 : in STD_LOGIC_VECTOR (7 downto 0);
result : out STD_LOGIC_VECTOR (7 downto 0)
);
END COMPONENT Mask;
BEGIN theMask : Mask PORT MAP (
ready => ready,
result => result,
k0 => k0,
k1 => k1,
k2 => k2,
k3 => k3,
k4 => k4,
k5 => k5,
k6 => k6,
k7 => k7,
k8 => k8
);
PROCESS(R2) is
BEGIN
R3 <= (others=>'0');
for j in 3 downto 0 loop
k0 <= R0(j*8 + 7 downto j*8);
k1 <= R0(j*8 + 7 downto j*8);
k2 <= R0(j*8 + 7 downto j*8);
k3 <= R1(j*8 + 7 downto j*8);
k4 <= R1(j*8 + 7 downto j*8);
k5 <= R1(j*8 + 7 downto j*8);
k6 <= R2(j*8 + 7 downto j*8);
k7 <= R2(j*8 + 7 downto j*8);
k8 <= R2(j*8 + 7 downto j*8);
end loop;
END PROCESS;
PROCESS is
BEGIN
for j in 3 downto 0 loop
wait on result;
R3( j*8 + 7 downto j*8 ) <= result;
end loop;
END PROCESS;
end arc1;
|
apache-2.0
|
h397wang/Lab2
|
Fanzhe/lab3.vhd
|
1
|
1037
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Lab3 is port (
ledr: out std_logic_vector(1 downto 0); -- displays the operator and result on the other end
ledg: out std_logic_vector(0 downto 0);
sw : in std_logic_vector(3 downto 0); -- 4 dip switches
);
end Lab3;
architecture SimpleCircuit of Lab3 is
-- signal declaration
signal Current, NextF: std_logic_vector(1 downto 0);
signal Enable, Down, Up: std_logic_vector(0 downto 0);
begin
CurrentFloor <= sw(1 downto 0);
NextFloor <= sw(3 downto 2);
-- w is current[1]
-- x is current[0]
-- y is next[1]
-- z is next[0]
Down <= (Current(1) and not NextF and NextF(0)) or
(Current(1) and Current(0)and NextF(1) and not NextF(0));
Up <= (not Current(1) and Current(0) and NextF(1)) or
(current(1) and not Current(0) and NextF(1) and NextF(0));
-- motor = (w'x' + y'z')' is this correct? consider when Current == NextF
-- down = w y' z + w x y z'
-- up = w'xy + wx'yz
end SimpleCircuit
|
apache-2.0
|
hoangt/PoC
|
src/fifo/fifo_cc_got_tempgot.vhdl
|
2
|
13813
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Module: FIFO, common clock (cc), pipelined interface,
-- reads only become effective after explicit commit
--
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- As uncommitted reads occupy FIFO space that is not yet available for
-- writing, an instance of this FIFO can, indeed, report 'full' and 'not vld'
-- at the same time. While a 'commit' would eventually make space available for
-- writing ('not ful'), a 'rollback' would re-iterate data for reading
-- ('vld').
--
-- 'commit' and 'rollback' are inclusive and apply to all reads ('got') since
-- the previous 'commit' or 'rollback' up to and including a potentially
-- simultaneous read.
--
-- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is
-- *undefined*!
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
use poc.utils.all;
use poc.ocram.ocram_sdp;
entity fifo_cc_got_tempgot is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0);
commit : in std_logic;
rollback : in std_logic
);
end fifo_cc_got_tempgot;
architecture rtl of fifo_cc_got_tempgot is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-- Commited Read Pointer (Commit Marker)
signal OPm : unsigned(A_BITS-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
OP0 <= (others => '0');
OPm <= (others => '0');
else
-- Update Input Pointer upon Write
if we = '1' then
IP0 <= IP1;
end if;
-- Update Output Pointer upon Read or Rollback
if rollback = '1' then
OP0 <= OPm;
elsif re = '1' then
OP0 <= OP1;
end if;
-- Update Commit Marker
if commit = '1' then
if re = '1' then
OPm <= OP1;
else
OPm <= OP0;
end if;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(fulli, IP0, OP0, OPm)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
-- Available Space
if ESTATE_WR_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OPm); -- true number of valid entries
end if;
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
else
estate_wr <= (others => 'X');
end if;
-- Available Content
if FSTATE_RD_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
else
fstate_rd <= (others => 'X');
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
--
-- The STATE_REG generic is ignored as two different comparators are
-- needed to compare IP with OPm (full) and IP with OP (empty) anyways.
-- So the register implementation is always used.
blkState: block
signal Ful : std_logic := '0';
signal Pnd : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Pnd <= '0';
Avl <= '0';
else
-- Pending Indicator for uncommitted Data
if commit = '1' or rollback = '1' then
Pnd <= '0';
elsif re = '1' then
Pnd <= '1';
end if;
-- Update Full Indicator
if commit = '1' and (re = '1' or Pnd = '1') then
Ful <= '0';
elsif we = '1' and IP1 = OPm then
Ful <= '1';
end if;
-- Update Empty Indicator
if we = '1' or (rollback = '1' and Pnd = '1') then
Avl <= '1';
elsif re = '1' and we = '0' and OP1 = IP0 then
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end block;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
|
apache-2.0
|
BogdanArdelean/FPWAM
|
hardware/src/hdl/GPR.vhd
|
1
|
1976
|
-------------------------------------------------------------------------------
-- FILE NAME : GPR.vhd
-- MODULE NAME : GPR
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : General Purpose Registers
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity GPR is
generic
(
kAddressWidth : natural := 4;
kWordWidth : natural := 16
);
port
(
--Common
clk : in std_logic;
address1 : in std_logic_vector(kAddressWidth - 1 downto 0);
wr1 : in std_logic;
input_word1 : in std_logic_vector(kWordWidth - 1 downto 0);
output_word1 : out std_logic_vector(kWordWidth - 1 downto 0);
address2 : in std_logic_vector(kAddressWidth - 1 downto 0);
wr2 : in std_logic;
input_word2 : in std_logic_vector(kWordWidth - 1 downto 0);
output_word2 : out std_logic_vector(kWordWidth - 1 downto 0)
);
end GPR;
architecture Behavioral of GPR is
type sram is array (0 to 2**kAddressWidth) of std_logic_vector(kWordWidth - 1 downto 0);
signal RAM : sram := (others => (others => '0'));
begin
WRITE_PROCESS: process(clk)
begin
if rising_edge(clk) then
if wr1 = '1' then
RAM(to_integer(unsigned(address1))) <= input_word1;
end if;
if wr2 = '1' then
RAM(to_integer(unsigned(address2))) <= input_word2;
end if;
end if;
end process;
output_word1 <= RAM(to_integer(unsigned(address1)));
output_word2 <= RAM(to_integer(unsigned(address2)));
end Behavioral;
|
apache-2.0
|
hoangt/PoC
|
src/io/io_TimingCounter.vhdl
|
2
|
3254
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: optimized down-counter to control timings for low speed signals
--
-- Description:
-- ------------------------------------
-- This down-counter can be configured with a TIMING_TABLE (a ROM), from which
-- the initial counter value is loaded. The table index can be selected by
-- 'Slot'. 'Timeout' is a registered output. Up to 16 values fit into one ROM
-- consisting of 'log2ceilnz(imax(TIMING_TABLE)) + 1' 6-input LUTs.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.my_config.all;
use PoC.utils.all;
entity io_TimingCounter is
generic (
TIMING_TABLE : T_NATVEC -- timing table
);
port (
Clock : in STD_LOGIC; -- clock
Enable : in STD_LOGIC; -- enable counter
Load : in STD_LOGIC; -- load Timing Value from TIMING_TABLE selected by slot
Slot : in NATURAL range 0 to (TIMING_TABLE'length - 1); --
Timeout : out STD_LOGIC -- timing reached
);
end;
architecture rtl of io_TimingCounter is
function transform(vec : T_NATVEC) return T_INTVEC is
variable Result : T_INTVEC(vec'range);
begin
assert (not MY_VERBOSE) report "TIMING_TABLE (transformed):" severity NOTE;
for i in vec'range loop
Result(I) := vec(I) - 1;
assert (not MY_VERBOSE) report " " & INTEGER'image(I) & " - " & INTEGER'image(Result(I)) severity NOTE;
end loop;
return Result;
end;
constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE);
constant TIMING_MAX : NATURAL := imax(TIMING_TABLE2);
constant COUNTER_BITS : NATURAL := log2ceilnz(TIMING_MAX + 1);
signal Counter_s : SIGNED(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1);
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Load = '1') then
Counter_s <= to_signed(TIMING_TABLE2(Slot), Counter_s'length);
elsif ((Enable = '1') and (Counter_s(Counter_s'high) = '0')) then
Counter_s <= Counter_s - 1;
end if;
end if;
end process;
timeout <= Counter_s(Counter_s'high);
end;
|
apache-2.0
|
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl_hs/PreProcessor.vhd
|
1
|
37499
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features activation
G_ENABLE_PAD : boolean := False; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
--! The number of bits required to hold block size expressed in
--! bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4;
--! Padding options
G_PAD_STYLE : integer := 0; --! Pad style
G_PAD_AD : integer := 1; --! Padding behavior for AD
G_PAD_D : integer := 1 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! CipherCore
--! Key
key : out std_logic_vector(G_KEY_SIZE -1 downto 0);
key_ready : in std_logic;
key_valid : out std_logic;
key_update : out std_logic;
--! BDI
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
decrypt : out std_logic;
bdi_ready : in std_logic;
bdi_valid : out std_logic;
bdi_type : out std_logic_vector(3 -1 downto 0);
bdi_partial : out std_logic;
bdi_eot : out std_logic;
bdi_eoi : out std_logic;
bdi_size : out std_logic_vector(G_LBS_BYTES+1-1 downto 0);
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8-1 downto 0);
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8-1 downto 0);
--! CMD FIFO
cmd : out std_logic_vector(24 -1 downto 0);
cmd_ready : in std_logic;
cmd_valid : out std_logic
);
end entity PreProcessor;
architecture structure of PreProcessor is
constant DSIZE : integer := G_DBLK_SIZE;
constant ASIZE : integer := G_ABLK_SIZE;
constant WB : integer := G_W/8; --! Word bytes
constant LOG2_WB : integer := log2_ceil(WB);
constant LOG2_KEYBYTES : integer := log2_ceil(512/8);
constant CNT_AWORDS : integer := (G_ABLK_SIZE+(G_W-1))/G_W;
constant CNT_DWORDS : integer := (G_DBLK_SIZE+(G_W-1))/G_W;
constant CNT_KWORDS : integer := (G_KEY_SIZE+(G_SW-1))/G_SW;
constant A_EQ_D : boolean := (DSIZE = ASIZE);
constant P_IS_BUFFER : boolean := not (G_W = DSIZE);
constant S_IS_BUFFER : boolean := not (G_SW = G_KEY_SIZE);
--! =======================================================================
type t_lookup is array (0 to (WB-1))
of std_logic_vector(WB-1 downto 0);
function getVbytesLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
if (i = 0) then
ret(i) := (others => '0');
else
ret(i)(size/8-1 downto size/8-i) := (others => '1');
ret(i)(size/8-i-1 downto 0) := (others => '0');
end if;
end loop;
return ret;
end function getVbytesLookup;
function getPlocLookup(size: integer) return t_lookup is
variable ret : t_lookup;
begin
for i in 0 to ((size/8)-1) loop
ret(i) := (others => '0');
ret(i)((size/8-i)-1) := '1';
--ret(i) := (((size/8-i)-1) => '1', others => '0');
end loop;
return ret;
end function getPlocLookup;
constant VBYTES_LOOKUP : t_lookup := getVbytesLookup(G_W);
constant PLOC_LOOKUP : t_lookup := getPlocLookup(G_W);
--! =======================================================================
--! Control status registers
--! Public
signal sgmt_type : std_logic_vector(4 -1 downto 0);
signal sgmt_pt : std_logic;
signal sgmt_eoi : std_logic;
signal sgmt_eot : std_logic;
signal sgmt_lst : std_logic;
signal sgmt_len : std_logic_vector(16 -1 downto 0);
signal is_decrypt : std_logic;
--! Secret
signal reg_key_update : std_logic;
signal reg_key_valid : std_logic;
--! =======================================================================
--! Control signals
--! Pad
signal set_extra : std_logic;
signal set_req_pad : std_logic;
signal req_pad : std_logic;
signal is_extra : std_logic;
signal sel_pad : std_logic;
signal is_pad : std_logic;
signal en_len : std_logic;
signal en_zero : std_logic;
signal reg_sel_zero : std_logic;
--! Public
signal pdi_rdy : std_logic;
signal bdi_vld : std_logic;
signal set_key_upd : std_logic;
signal ld_sgmt_info : std_logic;
signal ld_ctr : std_logic;
signal en_ctr : std_logic;
signal en_ps : std_logic;
signal en_data : std_logic;
signal ctr : std_logic_vector
(log2_ceil(CNT_DWORDS)-1 downto 0);
signal sel_end : std_logic;
signal ld_end : std_logic;
--! (unused)
signal en_last_word : std_logic;
--! Secret
signal sdi_rdy : std_logic;
signal ld_ctr2 : std_logic;
signal ld_slen : std_logic;
signal en_ctr2 : std_logic;
signal en_slen : std_logic;
signal en_ss : std_logic;
signal en_key : std_logic;
signal slen : std_logic_vector(LOG2_KEYBYTES+1 -1 downto 0);
signal ctr2 : std_logic_vector
(log2_ceil(CNT_KWORDS)-1 downto 0);
--! Cmd
signal wr_cmd : std_logic;
--! =======================================================================
--! State
type t_ps is (S_WAIT_INSTR, S_WAIT_HDR, S_PREP, S_DATA, S_WAIT_READY);
type t_ss is (S_WAIT_INSTR, S_WAIT_HDR, S_DATA, S_WAIT_READY);
signal ps : t_ps; --! Public State
signal nps : t_ps; --! Next Public State
signal ss : t_ss; --! Next Secret State
signal nss : t_ss; --! Next Secret State
--! =======================================================================
--! Data padding
signal word_size : std_logic_vector(LOG2_WB -1 downto 0);
signal data : std_logic_vector(G_W -1 downto 0);
--! Incoming data word
signal pdata : std_logic_vector(G_W -1 downto 0);
signal vbytes : std_logic_vector(WB -1 downto 0);
signal ploc : std_logic_vector(WB -1 downto 0);
--! Additional padding selection when ASIZE /= DSIZE
signal pdata2 : std_logic_vector(G_W -1 downto 0);
signal vbytes2 : std_logic_vector(WB -1 downto 0);
signal ploc2 : std_logic_vector(WB -1 downto 0);
--! Output regs
--! Prep status
signal mux_vbytes : std_logic_vector(WB -1 downto 0);
signal mux_ploc : std_logic_vector(WB -1 downto 0);
signal mux_size : std_logic_vector(LOG2_WB+1 -1 downto 0);
signal size : std_logic_vector(LOG2_WB+1 -1 downto 0);
--! Status
signal reg_bdi_valid : std_logic;
signal reg_size : std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
signal reg_vbytes : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
signal reg_ploc : std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! Data / info
signal reg_key : std_logic_vector(G_KEY_SIZE -1 downto 0);
signal reg_data : std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! =======================================================================
--! Signal aliases
signal p_instr_opcode : std_logic_vector(4 -1 downto 0);
signal p_sgmt_type : std_logic_vector(4 -1 downto 0);
signal p_sgmt_pt : std_logic;
signal p_sgmt_eoi : std_logic;
signal p_sgmt_eot : std_logic;
signal p_sgmt_lst : std_logic;
signal p_sgmt_len : std_logic_vector(16 -1 downto 0);
signal s_instr_opcode : std_logic_vector(4 -1 downto 0);
signal s_sgmt_type : std_logic_vector(4 -1 downto 0);
signal s_sgmt_eot : std_logic;
signal s_sgmt_lst : std_logic;
signal s_sgmt_len : std_logic_vector(LOG2_KEYBYTES+1 -1 downto 0);
begin
--! =======================================================================
--! Datapath (Core)
--! =======================================================================
data <= pdi_data when reg_sel_zero = '0' else (others => '0');
gPad0: if (not G_ENABLE_PAD) generate
pdata <= data;
end generate;
gPad1: if (G_ENABLE_PAD) generate
begin
gPadMode0: if (G_PAD_STYLE = 0) generate
pdata <= data;
end generate;
gPadMode1: if (G_PAD_STYLE = 1) generate
gLoop: for i in WB-1 downto 0 generate
pdata(i*8+7)
<= ploc(i) or data(i*8+7);
pdata(i*8+6 downto i*8)
<= data(i*8+6 downto i*8);
end generate;
end generate;
end generate;
mux_vbytes <= VBYTES_LOOKUP(to_integer(unsigned(word_size)))
when sel_pad = '1'
else (others => '1');
mux_ploc <= PLOC_LOOKUP(to_integer(unsigned(word_size)))
when (sel_pad = '1' and req_pad = '1')
else (others => '0');
mux_size <= '0' & word_size
when sel_pad = '1'
else (LOG2_WB => '1', others => '0');
process(clk)
begin
if rising_edge(clk) then
if (en_len = '1') then
vbytes <= mux_vbytes;
ploc <= mux_ploc;
size <= mux_size;
end if;
if (en_data = '1') then
if ((DSIZE > G_W) and (DSIZE MOD G_W) = 0) then
reg_data <= reg_data(DSIZE-G_W-1 downto 0) & pdata;
reg_vbytes<= reg_vbytes(DSIZE/8-WB-1 downto 0) & vbytes;
reg_ploc <= reg_ploc (DSIZE/8-WB-1 downto 0) & ploc;
elsif ((DSIZE MOD G_W) /= 0) then
if (en_last_word = '0') then
reg_data (DSIZE-1 downto (DSIZE MOD G_W )) <=
reg_data(DSIZE-G_W-1 downto (DSIZE MOD G_W))
& pdata2;
reg_vbytes(DSIZE/8-1 downto ((DSIZE/8) MOD WB)) <=
reg_vbytes(DSIZE/8-WB-1 downto ((DSIZE/8) MOD WB))
& vbytes2;
reg_ploc(DSIZE/8-1 downto ((DSIZE/8) MOD WB)) <=
reg_ploc(DSIZE/8-WB-1 downto ((DSIZE/8) MOD WB))
& ploc2;
else
reg_data ((DSIZE mod G_W)-1 downto 0) <=
pdata2(G_W -1 downto G_W /2);
reg_vbytes(((DSIZE/8) mod WB)-1 downto 0) <=
vbytes(WB-1 downto WB/2);
reg_ploc(((DSIZE/8) mod WB)-1 downto 0) <=
ploc2(WB-1 downto WB/2);
end if;
end if;
end if;
if (en_key = '1') then
if (G_SW < G_KEY_SIZE) then
reg_key <= reg_key(G_KEY_SIZE-G_SW-1 downto 0) & sdi_data;
end if;
end if;
end if;
end process;
--! =======================================================================
--! Registers with rst for controller and datapath
--! =======================================================================
gSyncRst:
if (not G_ASYNC_RSTN) generate
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
--! Datapath
reg_size <= (others => '0');
reg_bdi_valid <= '0';
reg_key_update <= '0';
reg_key_valid <= '0';
--! Control
req_pad <= '0';
ps <= S_WAIT_INSTR;
ss <= S_WAIT_INSTR;
else
--! Datapath
if (en_data = '1') then
reg_size <= std_logic_vector(
unsigned(reg_size) + unsigned(size));
elsif (bdi_ready = '1') then
reg_size <= (others => '0');
end if;
--! BDI valid register
if (en_ps = '1' and nps = S_WAIT_READY) then
reg_bdi_valid <= '1';
elsif (reg_bdi_valid = '1' and bdi_ready = '1') then
reg_bdi_valid <= '0';
end if;
--! Key update register
if (set_key_upd = '1') then
reg_key_update <= '1';
elsif (key_ready = '1'
and ((S_IS_BUFFER and reg_key_valid = '1')
or (not S_IS_BUFFER and sdi_valid = '1')))
then
reg_key_update <= '0';
end if;
--! Key valid register
if (en_ss = '1' and nss = S_WAIT_READY) then
reg_key_valid <= '1';
elsif (key_ready = '1' and reg_key_valid = '1') then
reg_key_valid <= '0';
end if;
--! Control
if (set_req_pad = '1') then
req_pad <= '1';
elsif (en_len = '1' and sel_pad = '1')
or ps = S_WAIT_INSTR
then
req_pad <= '0';
end if;
if (en_ps = '1') then
ps <= nps;
end if;
if (en_ss = '1') then
ss <= nss;
end if;
end if;
end if;
end process;
end generate;
gAsyncRstn:
if (G_ASYNC_RSTN) generate
process(clk, rst)
begin
if (rst = '0') then
--! Datapath
reg_size <= (others => '0');
reg_bdi_valid <= '0';
reg_key_update <= '0';
reg_key_valid <= '0';
--! Control
req_pad <= '0';
ps <= S_WAIT_INSTR;
ss <= S_WAIT_INSTR;
elsif rising_edge(clk) then
--! Datapath
if (en_data = '1') then
reg_size <= std_logic_vector(
unsigned(reg_size) + unsigned(size));
elsif (bdi_ready = '1') then
reg_size <= (others => '0');
end if;
--! BDI valid register
if (en_ps = '1' and nps = S_WAIT_READY) then
reg_bdi_valid <= '1';
elsif (reg_bdi_valid = '1' and bdi_ready = '1') then
reg_bdi_valid <= '0';
end if;
--! Key update register
if (set_key_upd = '1') then
reg_key_update <= '1';
elsif (key_ready = '1'
and ((S_IS_BUFFER and reg_key_valid = '1')
or (not S_IS_BUFFER and sdi_valid = '1')))
then
reg_key_update <= '0';
end if;
--! Key valid register
if (en_ss = '1' and nss = S_WAIT_READY) then
reg_key_valid <= '1';
elsif (key_ready = '1' and reg_key_valid = '1') then
reg_key_valid <= '0';
end if;
--! Control
if (set_req_pad = '1') then
req_pad <= '1';
elsif (en_len = '1' and sel_pad = '1')
or ps = S_WAIT_INSTR
then
req_pad <= '0';
end if;
if (en_ps = '1') then
ps <= nps;
end if;
if (en_ss = '1') then
ss <= nss;
end if;
end if;
end process;
end generate;
--! =======================================================================
--! Datapath (Output)
--! =======================================================================
pdi_ready <= pdi_rdy;
sdi_ready <= sdi_rdy;
--! Public
decrypt <= is_decrypt;
gDsizeEq:
if (not P_IS_BUFFER) generate
bdi <= pdata;
bdi_vld <= pdi_valid when (ps = S_DATA) else '0';
bdi_type <= sgmt_type(3 downto 1);
gNotCiph:
if (not G_CIPH_EXP) generate
bdi_eot <= sgmt_eot
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_eoi <= sgmt_eoi
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
end generate;
gCiph:
if (G_CIPH_EXP) generate
bdi_eot <= sgmt_eot or sgmt_eoi
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_eoi <= sgmt_lst
when (ps = S_DATA and unsigned(sgmt_len) = 0)
else '0';
bdi_partial <= sgmt_pt;
end generate;
bdi_size <= size;
bdi_valid_bytes <= vbytes;
bdi_pad_loc <= ploc;
end generate;
gDsizeNeq:
if (P_IS_BUFFER) generate
signal en_eoi_last : std_logic;
signal en_eot_last : std_logic;
begin
bdi <= reg_data;
bdi_vld <= reg_bdi_valid;
bdi_type <= sgmt_type(3 downto 1);
pEnd:
process(clk)
begin
if rising_edge(clk) then
if (ld_end = '1') then
if (not G_CIPH_EXP) then
bdi_eot <= sgmt_eot and sel_end;
bdi_eoi <= sgmt_eoi and sel_end;
else
bdi_eot <= (sgmt_eot or en_eot_last) and sel_end;
bdi_eoi <= (sgmt_eoi or en_eoi_last) and sel_end;
end if;
end if;
end if;
end process;
gCiph:
if (G_CIPH_EXP) generate
en_eot_last <= '1' when
((sgmt_eoi = '1' and sgmt_type = ST_NPUB)
or (sgmt_eoi = '1' and G_ENABLE_PAD
and sgmt_type(3 downto 2) = ST_A
and G_PAD_AD /= 2 and G_PAD_AD /= 4)
or (sgmt_eoi = '1' and G_ENABLE_PAD
and sgmt_type(3 downto 2) = ST_D
and G_PAD_D /= 2 and G_PAD_D /= 4))
else '0';
en_eoi_last <= '1' when en_eot_last = '1' and is_decrypt = '0'
else '0';
bdi_partial <= sgmt_pt;
end generate;
bdi_size <= reg_size;
bdi_valid_bytes <= reg_vbytes;
bdi_pad_loc <= reg_ploc;
end generate;
bdi_valid <= bdi_vld;
--! Secret
gTsizeEq:
if (S_IS_BUFFER) generate
key_valid <= reg_key_valid;
key <= reg_key;
end generate;
gTsizeNeq:
if (not S_IS_BUFFER) generate
key_valid <= sdi_valid when (ss = S_DATA) else '0';
key <= sdi_data;
end generate;
key_update <= reg_key_update;
--! CMD FIFO
cmd <= pdi_data(G_W-1 downto G_W-5) & '0'
& pdi_data(G_W-7 downto G_W-8)
& pdi_data(G_W-17 downto G_W-32);
cmd_valid <= wr_cmd;
--! =======================================================================
--! Control
--! =======================================================================
process(clk)
begin
if rising_edge(clk) then
--! Operation register
if (ps = S_WAIT_INSTR) then
is_decrypt <= p_instr_opcode(0);
end if;
--! Length register
if (ld_sgmt_info = '1') then
sgmt_type <= p_sgmt_type;
if (G_CIPH_EXP) then
sgmt_pt <= p_sgmt_pt;
end if;
sgmt_eoi <= p_sgmt_eoi;
sgmt_eot <= p_sgmt_eot;
sgmt_lst <= p_sgmt_lst;
sgmt_len <= p_sgmt_len;
else
if (en_len = '1') then
if (sel_pad = '1') then
sgmt_len <= (others => '0');
else
sgmt_len <= std_logic_vector(unsigned(sgmt_len)-WB);
end if;
end if;
end if;
--! Padding activation register
if (en_len = '1') then
is_pad <= sel_pad;
end if;
--! Select zero register
if (ld_sgmt_info = '1')
or (P_IS_BUFFER and not A_EQ_D
and bdi_ready = '1' and unsigned(sgmt_len) > 0)
then
reg_sel_zero <= '0';
elsif (unsigned(sgmt_len) = 0 and en_len = '1')
or (not A_EQ_D and en_zero = '1')
then
reg_sel_zero <= '1';
end if;
--! Secret length register
if (ld_slen = '1') then
slen <= s_sgmt_len;
elsif (en_slen = '1') then
slen <= std_logic_vector(unsigned(slen)-G_KEY_SIZE/8);
end if;
--! Extra block register
if (ld_sgmt_info = '1' or (bdi_ready = '1' and bdi_vld = '1')) then
is_extra <= '0';
elsif (set_extra = '1') then
is_extra <= '1';
end if;
--! Public data input counter register
if (ld_ctr = '1') then
ctr <= (others => '0');
elsif (en_ctr = '1') then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
--! Secret data input counter register
if (ld_ctr2 = '1') then
ctr2 <= (others => '0');
elsif (en_ctr2 = '1') then
ctr2 <= std_logic_vector(unsigned(ctr2) + 1);
end if;
end if;
end process;
sel_pad <= '1' when (unsigned(sgmt_len) < WB) else '0';
word_size <= sgmt_len(LOG2_WB-1 downto 0);
--! HDR Dissection
p_instr_opcode <= pdi_data(G_W-1 downto G_W-4);
p_sgmt_type <= pdi_data(G_W-1 downto G_W-4);
p_sgmt_pt <= pdi_data(G_W-5);
p_sgmt_eoi <= pdi_data(G_W-6);
p_sgmt_eot <= pdi_data(G_W-7);
p_sgmt_lst <= pdi_data(G_W-8);
p_sgmt_len <= pdi_data(G_W-17 downto G_W-32);
s_instr_opcode <= sdi_data(G_SW-1 downto G_SW-4);
s_sgmt_type <= sdi_data(G_SW-1 downto G_SW-4);
s_sgmt_eot <= sdi_data(G_SW-7);
s_sgmt_lst <= sdi_data(G_SW-8);
s_sgmt_len <= sdi_data(G_SW-32+LOG2_KEYBYTES downto G_SW-32);
gPdiComb:
process(ps, p_instr_opcode, pdi_valid,
sgmt_len, sgmt_type, sgmt_eot, sgmt_lst,
p_sgmt_eot, p_sgmt_type,
bdi_ready, cmd_ready, reg_sel_zero,
is_extra, ctr)
begin
nps <= ps;
pdi_rdy <= '1';
set_key_upd <= '0';
set_req_pad <= '0';
ld_sgmt_info <= '0';
if (P_IS_BUFFER) then
ld_end <= '0';
set_extra <= '0';
end if;
ld_ctr <= '0';
en_data <= '0';
en_ps <= '0';
en_len <= '0';
en_ctr <= '0';
en_zero <= '0';
wr_cmd <= '0';
case ps is
when S_WAIT_INSTR =>
ld_ctr <= '1';
if (p_instr_opcode(3 downto 1) = OP_ENCDEC) then
nps <= S_WAIT_HDR;
end if;
if (p_instr_opcode = OP_ACTKEY) then
set_key_upd <= '1';
end if;
if (cmd_ready = '0') then
pdi_rdy <= '0';
end if;
if (pdi_valid = '1') then
en_ps <= '1';
wr_cmd <= '1';
end if;
when S_WAIT_HDR =>
ld_sgmt_info <= '1';
nps <= S_PREP;
if (cmd_ready = '0') then
pdi_rdy <= '0';
end if;
if (pdi_valid = '1' and cmd_ready = '1') then
en_ps <= '1';
if (p_sgmt_type(3 downto 2) = ST_D
or p_sgmt_type(3 downto 1) = ST_NSEC)
then
wr_cmd <= '1';
end if;
end if;
if (G_ENABLE_PAD) then
if (p_sgmt_eot = '1') then
if (p_sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 0)
or (p_sgmt_type(3 downto 2) = ST_D and G_PAD_D > 0)
then
set_req_pad <= '1';
end if;
end if;
end if;
when S_PREP =>
pdi_rdy <= '0';
--! state transition
if (unsigned(sgmt_len) = 0) then
if (G_ENABLE_PAD) and
--! Add a new block based on padding behavior
((sgmt_type(3 downto 2) = ST_A
and (G_PAD_AD = 2 or G_PAD_AD = 4))
or (sgmt_type(3 downto 2) = ST_D
and (G_PAD_D = 2 or G_PAD_D = 4)))
then
nps <= S_DATA;
else
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
nps <= S_DATA;
end if;
en_len <= '1';
en_ps <= '1';
when S_DATA =>
if (not P_IS_BUFFER) then
--! Without buffer
if (reg_sel_zero = '1'
or (not P_IS_BUFFER
and (pdi_valid = '0' or bdi_ready = '0')))
then
pdi_rdy <= '0';
end if;
if (unsigned(sgmt_len) = 0)
and not (req_pad = '1' and G_ENABLE_PAD
and ((sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 2)
or (sgmt_type(3 downto 2) = ST_D and G_PAD_D > 2)))
then
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
--! With buffer
if (reg_sel_zero = '1') then
pdi_rdy <= '0';
end if;
if (unsigned(ctr) = CNT_DWORDS-1) then
nps <= S_WAIT_READY;
end if;
if (unsigned(ctr) = CNT_DWORDS-2) then
ld_end <= '1';
end if;
if (unsigned(sgmt_len) = WB and G_ENABLE_PAD
and sgmt_eot = '1'
and ((sgmt_type(3 downto 2) = ST_A and G_PAD_AD > 2)
or (sgmt_type(3 downto 2) = ST_D
and G_PAD_D > 2
and (not G_CIPH_EXP
or (G_CIPH_EXP and is_decrypt = '0')))))
then
if (A_EQ_D) then
if unsigned(ctr) = CNT_DWORDS-2 then
set_extra <= '1';
end if;
else
if ((sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) = CNT_AWORDS-2)
or (sgmt_type(3 downto 2) = ST_D
and unsigned(ctr) = CNT_DWORDS-2))
then
set_extra <= '1';
end if;
end if;
end if;
--! if ASIZE < DSIZE
if (not A_EQ_D) then
if (sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) >= CNT_AWORDS-1)
then
en_zero <= '1';
end if;
end if;
end if;
if (reg_sel_zero = '1'
or (pdi_valid = '1'
and (P_IS_BUFFER
or (not P_IS_BUFFER and bdi_ready = '1'))))
then
if (sgmt_type(3 downto 2) /= ST_A
and sgmt_type(3 downto 2) /= ST_D)
then
--! Not AD or D segment
if (P_IS_BUFFER) then
if (unsigned(ctr) /= CNT_DWORDS-1) then
en_len <= '1';
end if;
else
en_len <= '1';
end if;
else
--! AD or D segment
if (P_IS_BUFFER) then
if (A_EQ_D) then
if (unsigned(ctr) /= CNT_DWORDS-1) then
en_len <= '1';
end if;
else
if ((sgmt_type(3 downto 2) = ST_A
and unsigned(ctr) < CNT_AWORDS-1)
or (sgmt_type(3 downto 2) /= ST_A
and unsigned(ctr) /= CNT_DWORDS-1))
then
en_len <= '1';
end if;
end if;
else
en_len <= '1';
end if;
end if;
if (P_IS_BUFFER) then
en_ctr <= '1';
en_data <= '1';
end if;
en_ps <= '1';
end if;
when S_WAIT_READY =>
pdi_rdy <= '0';
ld_ctr <= '1';
if (unsigned(sgmt_len) = 0) then
if ((G_ENABLE_PAD and (G_PAD_AD > 2 or G_PAD_D > 2))
and is_extra = '1')
then
nps <= S_DATA;
else
if (sgmt_lst = '1') then
nps <= S_WAIT_INSTR;
else
nps <= S_WAIT_HDR;
end if;
end if;
else
nps <= S_DATA;
end if;
if (bdi_ready = '1') then
en_len <= '1';
en_ps <= '1';
end if;
end case;
end process;
sel_end <= '1' when (unsigned(sgmt_len) <= WB
and (is_extra = '0' and set_extra = '0'))
else '0';
gSdiComb:
process(ss, s_instr_opcode, sdi_valid, ctr2, key_ready, slen)
begin
nss <= ss;
sdi_rdy <= '0';
en_key <= '0';
ld_ctr2 <= '0';
ld_slen <= '0';
en_ctr2 <= '0';
en_slen <= '0';
en_ss <= '0';
case ss is
when S_WAIT_INSTR =>
ld_ctr2 <= '1';
sdi_rdy <= '1';
if (s_instr_opcode = OP_LDKEY) then
nss <= S_WAIT_HDR;
end if;
if (sdi_valid = '1') then
en_ss <= '1';
end if;
when S_WAIT_HDR =>
nss <= S_DATA;
ld_slen <= '1';
sdi_rdy <= '1';
if (sdi_valid = '1') then
en_ss <= '1';
end if;
when S_DATA =>
if (not S_IS_BUFFER) then
nss <= S_WAIT_INSTR;
if (sdi_valid = '1' and key_ready = '1') then
en_slen <= '1';
sdi_rdy <= '1';
if (unsigned(slen) = G_KEY_SIZE/8) then
en_ss <= '1';
end if;
end if;
else
sdi_rdy <= '1';
nss <= S_WAIT_READY;
if (sdi_valid = '1') then
en_ctr2 <= '1';
en_key <= '1';
if (unsigned(ctr2) = CNT_KWORDS-1) then
en_ss <= '1';
end if;
end if;
end if;
when S_WAIT_READY =>
if (unsigned(slen) = G_KEY_SIZE/8) then
nss <= S_WAIT_INSTR;
else
nss <= S_DATA;
end if;
ld_ctr2 <= '1';
if (key_ready = '1') then
en_ss <= '1';
en_slen <= '1';
end if;
end case;
end process;
end architecture structure;
|
apache-2.0
|
hoangt/PoC
|
tb/arith/arith_convert_bin2bcd_tb.vhdl
|
2
|
4567
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Testbench: Converter Binary to BCD.
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Automated testbench for PoC.arith_converter_bin2bcd
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.simulation.all;
entity arith_convert_bin2bcd_tb is
end;
architecture test of arith_convert_bin2bcd_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
constant INPUT_1 : INTEGER := 38442113;
constant INPUT_2 : INTEGER := 78734531;
constant INPUT_3 : INTEGER := 14902385;
constant CONV1_BITS : POSITIVE := 30;
constant CONV1_DIGITS : POSITIVE := 8;
constant CONV2_BITS : POSITIVE := 27;
constant CONV2_DIGITS : POSITIVE := 8;
signal SimStop : std_logic := '0';
signal Clock : STD_LOGIC := '1';
signal Reset : STD_LOGIC := '0';
signal Start : STD_LOGIC := '0';
signal Conv1_Binary : STD_LOGIC_VECTOR(CONV1_BITS - 1 downto 0);
signal Conv1_BCDDigits : T_BCD_VECTOR(CONV1_DIGITS - 1 DOWNTO 0);
signal Conv1_Sign : STD_LOGIC;
signal Conv2_Binary : STD_LOGIC_VECTOR(CONV2_BITS - 1 downto 0);
signal Conv2_BCDDigits : T_BCD_VECTOR(CONV2_DIGITS - 1 DOWNTO 0);
signal Conv2_Sign : STD_LOGIC;
begin
blkClock : block
constant CLOCK_PERIOD : TIME := to_time(CLOCK_FREQ);
begin
Clock <= Clock xnor SimStop after CLOCK_PERIOD / 2.0;
end block;
process
begin
wait until rising_edge(Clock);
Reset <= '1';
wait until rising_edge(Clock);
Reset <= '0';
wait until rising_edge(Clock);
Start <= '1';
Conv1_Binary <= to_slv(INPUT_1, CONV1_BITS);
Conv2_Binary <= to_slv(INPUT_1, CONV2_BITS);
wait until rising_edge(Clock);
Start <= '0';
wait until rising_edge(Clock);
for i in 0 to (CONV1_BITS - 1) loop
wait until rising_edge(Clock);
end loop;
Start <= '1';
Conv1_Binary <= to_slv(INPUT_2, CONV1_BITS);
Conv2_Binary <= to_slv(INPUT_2, CONV2_BITS);
wait until rising_edge(Clock);
Start <= '0';
wait until rising_edge(Clock);
for i in 0 to (CONV1_BITS - 1) loop
wait until rising_edge(Clock);
end loop;
Start <= '1';
Conv1_Binary <= to_slv(INPUT_3, CONV1_BITS);
Conv2_Binary <= to_slv(INPUT_3, CONV2_BITS);
wait until rising_edge(Clock);
Start <= '0';
wait until rising_edge(Clock);
for i in 0 to (CONV1_BITS - 1) loop
wait until rising_edge(Clock);
end loop;
wait until rising_edge(Clock);
wait until rising_edge(Clock);
-- Report overall simulation result
tbPrintResult;
SimStop <= '1';
wait;
end process;
conv1 : entity PoC.arith_convert_bin2bcd
generic map (
BITS => CONV1_BITS,
DIGITS => CONV1_DIGITS,
RADIX => 8
)
port map (
Clock => Clock,
Reset => Reset,
Start => Start,
Busy => open,
Binary => Conv1_Binary,
IsSigned => '0',
BCDDigits => Conv1_BCDDigits,
Sign => Conv1_Sign
);
conv2 : entity PoC.arith_convert_bin2bcd
generic map (
BITS => CONV2_BITS,
DIGITS => CONV2_DIGITS,
RADIX => 2
)
port map (
Clock => Clock,
Reset => Reset,
Start => Start,
Busy => open,
Binary => Conv2_Binary,
IsSigned => '1',
BCDDigits => Conv2_BCDDigits,
Sign => Conv2_Sign
);
end;
|
apache-2.0
|
IAIK/ascon_hardware
|
caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/AEAD_Wrapper.vhd
|
2
|
3037
|
-------------------------------------------------------------------------------
--! @file AEAD_Wrapper.vhd
--! @brief 5-bit wrapper for AEAD.vhd
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD_Wrapper is
generic (
G_W : integer := 32;
G_SW : integer := 32
);
port (
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! SERDES signals
sin : in std_logic;
ssel : in std_logic;
sout : out std_logic
);
end entity AEAD_Wrapper;
architecture structure of AEAD_Wrapper is
signal sipo : std_logic_vector(G_W+G_SW+3 -1 downto 0);
signal piso : std_logic_vector(G_W+3 -1 downto 0);
signal piso_data : std_logic_vector(G_W+3 -1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
sipo <= sin & sipo(sipo'high downto 1);
if (ssel = '1') then
piso <= piso_data;
else
piso <= '0' & piso(piso'high downto 1);
end if;
end if;
end process;
sout <= piso(0);
u_aead:
entity work.AEAD(structure)
generic map (
G_W => G_W ,
G_SW => G_SW
)
port map (
clk => clk ,
rst => rst ,
--! Input signals
pdi_data => sipo( G_W-1 downto 0),
sdi_data => sipo( G_SW+G_W-1 downto G_W),
pdi_valid => sipo(1+G_SW+G_W-1) ,
sdi_valid => sipo(2+G_SW+G_W-1) ,
do_ready => sipo(3+G_SW+G_W-1) ,
--! Output signals
do_data => piso_data( G_W-1 downto 0),
pdi_ready => piso_data(1+G_W-1) ,
sdi_ready => piso_data(2+G_W-1) ,
do_valid => piso_data(3+G_W-1)
);
end structure;
|
apache-2.0
|
hoangt/PoC
|
src/misc/sync/sync_Reset_Altera.vhdl
|
2
|
3095
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Reset_Altera
--
-- Description:
-- ------------------------------------
-- This is a clock-domain-crossing circuit for reset signals optimized for
-- Altera FPGAs. It infers 2 flip flops with asynchronous preset and notifies
-- Quartus II, that these flip flops are synchronizer flip flops. If you need
-- a platform independent version of this synchronizer, please use
-- 'PoC.misc.sync.sync_Reset', which internally instantiates this module if
-- a Altera FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for reset signals.
--
-- CONSTRAINTS:
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Reset_Altera is
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC; -- Data to be synchronized
Output : out STD_LOGIC -- synchronised data
);
end entity;
architecture rtl of sync_Reset_Altera is
attribute altera_attribute : STRING;
attribute preserve : BOOLEAN;
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := '1';
signal Data_sync : STD_LOGIC := '1';
-- Apply a SDC constraint to meta stable flip flop
--attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to *|sync_Reset_Altera:*|Data_meta """;
-- Notity the synthesizer / timing analysator to identity a synchronizer circuit
attribute altera_attribute of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
-- preserve both registers (no optimization, shift register extraction, ...)
attribute preserve of Data_meta : signal is TRUE;
attribute preserve of Data_sync : signal is TRUE;
begin
Data_async <= '0';
process(Clock)
begin
if (Input = '1') then
Data_meta <= '1';
Data_sync <= '1';
elsif rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output <= Data_sync;
end architecture;
|
apache-2.0
|
nsensfel/tabellion
|
data/test/CNE_01400/valid.vhd
|
1
|
373
|
library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
generic
(
clock_speed0: std_logic; -- $SOL:0:0$
clock_speed1: std_logic := '0'; -- $SOL:1:0$
clock_g_speed2: natural; -- $SOL:2:0$
clock_g_speed3: natural := 3; -- $SOL:3:0$
i_g_g_param : std_logic -- $SOL:4:0$
);
end;
architecture RTL of valid is
begin
end architecture;
|
apache-2.0
|
Paebbels/PicoBlaze-Library
|
vhdl/IO Adapter/pb_GPIO_Adapter.vhdl
|
1
|
5029
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze General Perpose I/O Adapter
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_GPIO_Adapter is
generic (
DEBUG : BOOLEAN := TRUE;
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
BITS : POSITIVE := 8
);
port (
Clock : IN STD_LOGIC;
Reset : IN STD_LOGIC;
-- PicoBlaze interface
Address : IN T_SLV_8;
WriteStrobe : IN STD_LOGIC;
WriteStrobe_K : IN STD_LOGIC;
ReadStrobe : IN STD_LOGIC;
DataIn : IN T_SLV_8;
DataOut : OUT T_SLV_8;
Interrupt : OUT STD_LOGIC;
Interrupt_Ack : IN STD_LOGIC;
Message : OUT T_SLV_8;
-- GPIO interface
GPIO_Out : OUT STD_LOGIC_VECTOR(BITS - 1 downto 0);
GPIO_In : IN STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of pb_GPIO_Adapter is
constant REG_RW_DATAOUT : UNSIGNED(0 downto 0) := "0";
constant REG_RO_DATAIN : UNSIGNED(0 downto 0) := "1";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_DataOut : T_SLV_8 := (others => '0');
signal Reg_DataIn : T_SLV_8 := (others => '0');
begin
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Reg_DataOut <= (others => '0');
Reg_DataIn <= (others => '0');
else
if (AdrDec_we = '1') THEN
case unsigned(AdrDec_WriteAddress(0 downto 0)) is
when REG_RW_DATAOUT =>
Reg_DataOut <= AdrDec_Data;
when others =>
null;
end case;
end if;
Reg_DataIn <= GPIO_In;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_DataIn, Reg_DataOut)
begin
DataOut <= Reg_DataIn;
case unsigned(AdrDec_ReadAddress(0 downto 0)) is
when REG_RW_DATAOUT =>
DataOut <= Reg_DataOut;
when REG_RO_DATAIN =>
DataOut <= Reg_DataIn;
when others =>
null;
end case;
end process;
Interrupt <= '0';
Message <= x"00";
GPIO_Out <= Reg_DataOut;
end;
|
apache-2.0
|
kb3gtn/fpga_edc
|
tb/mojo_top_tb/mojo_top_tb.vhd
|
1
|
5141
|
--------------------------------------------------------
-- FPGA_EDC top level test bench
--
--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
component mojo_top is
Port (
clk50m : in STD_LOGIC;
rst_n : in STD_LOGIC;
cclk : in STD_LOGIC; -- spi/fpga programming clock (not used).
led : out STD_LOGIC_VECTOR (7 downto 0); -- board LEDs
-- RS232
serial_tx : out STD_LOGIC; -- pin 7 on SV2
serial_rx : in STD_LOGIC; -- pin 5 on SV2
-- SPI1 signals
spi1_miso : in STD_LOGIC; -- pin 11 on SV2
spi1_mosi : out STD_LOGIC; -- pin 13 on SV2
spi1_sclk : out STD_LOGIC; -- pin 9 on SV2
spi1_cs_n : out STD_LOGIC_VECTOR( 3 downto 0) -- pins 10,12,14,16 on SV2
);
end component mojo_top;
-- signals
signal clk50m : std_logic;
signal rst_n : std_logic;
signal serial_tx : std_logic;
signal serial_rx : std_logic;
signal spi1_miso : std_logic;
signal spi1_mosi : std_logic;
signal spi1_sclk : std_logic;
signal spi1_cs_n : std_logic_vector( 3 downto 0);
constant tx_bit_period : time := 8.680555 us;
signal serial_ce : std_logic; -- clock enable for serial generation procedure
-- procedure to send a byte of data as a rs232 serial stream
procedure serial_send (
constant input_byte : in std_logic_vector(7 downto 0);
signal tx_out : out std_logic
) is
begin
tx_out <= '1'; -- idle state;
wait until rising_edge( serial_ce );
tx_out <= '0'; -- tx start bit.
wait until rising_edge( serial_ce );
tx_out <= input_byte(0);
wait until rising_edge( serial_ce );
tx_out <= input_byte(1);
wait until rising_edge( serial_ce );
tx_out <= input_byte(2);
wait until rising_edge( serial_ce );
tx_out <= input_byte(3);
wait until rising_edge( serial_ce );
tx_out <= input_byte(4);
wait until rising_edge( serial_ce );
tx_out <= input_byte(5);
wait until rising_edge( serial_ce );
tx_out <= input_byte(6);
wait until rising_edge( serial_ce );
tx_out <= input_byte(7);
wait until rising_edge( serial_ce );
tx_out <= '0'; -- stop bit
wait until rising_edge( serial_ce );
tx_out <= '1'; -- back to idle
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
wait until rising_edge( serial_ce );
end procedure;
BEGIN
serial_ce_gen : process
begin
serial_ce <= '0';
wait for tx_bit_period/2;
serial_ce <= '1';
wait for tx_bit_period/2;
end process;
-- clock and reset generation
clk50_gen : process
begin
clk50m <= '0';
wait for 10 ns; -- 1/2 50 MHz clock period
clk50m <= '1';
wait for 10 ns; -- 1/2 50 MHz clock period
end process;
-- Component Instantiation
mojo_unit : mojo_top
port map (
clk50m => clk50m,
rst_n => rst_n,
cclk => '1',
serial_tx => serial_tx,
serial_rx => serial_rx,
spi1_miso => spi1_miso,
spi1_mosi => spi1_mosi,
spi1_sclk => spi1_sclk,
spi1_cs_n => spi1_cs_n
);
tb_stim : process
begin
rst_n <= '0'; -- reset active
wait for 80 ns; -- wait for 4 clock cycles
rst_n <= '1'; -- reset de-asserted..
wait for 80 ns; -- wait for 4 clock cycles
-- turn LEDs on ( address 0x03 )
serial_send( x"03", serial_rx );
serial_send( x"55", serial_rx );
serial_send( x"03", serial_rx );
serial_send( x"AA", serial_rx );
-- read back value from led register
serial_send( x"83", serial_rx );
-- send a write to address 2 ( spi1_baud_reg )
-- cmd format (R/!W <7 bits of address> )
serial_send( x"02", serial_rx ); -- address 2 as a write
serial_send( x"19", serial_rx ); -- set spi baud register to 25 -> 500 KHz spi clock
-- now issue a serial read of the buad register (addr 02)
serial_send( x"82", serial_rx );
wait for tx_bit_period*10; -- should get a byte back from the data bus on the uart..
wait for 1 us;
rst_n <= '0'; -- assert reset
wait; -- stop simulation
end process;
END ARCHITECTURE;
|
apache-2.0
|
project-oak/silveroak
|
investigations/kami/counter/counter4_top.vhdl
|
1
|
2774
|
--
-- Copyright 2019 The Project Oak Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- A simple test program for the Xilinx ZCU104605 development board that
-- makes the user GPIO LEDs flash for the binary sequence 0..7, with a
-- reset from the push button GPIO_PB_SW3 SW18 at a 1 second frequency.
library ieee;
use ieee.std_logic_1164.all;
package counter_package is
subtype count_type is natural range 0 to 15;
component mkModule1 is
port(signal CLK : in std_ulogic;
signal RST_N : in std_ulogic;
signal EN_count_value : in std_ulogic;
signal count_value : out count_type;
signal RDY_count_value : out std_ulogic);
end component mkModule1;
end package counter_package;
library ieee;
use ieee.std_logic_1164.all;
use work.counter_package.all;
entity counter4 is
port (signal CLK_125_P : in std_ulogic; -- 125MHz clock P at pin H11 LVDS
signal CLK_125_N : in std_ulogic; -- 125MHz clock N at pin G11 LVDS
signal GPIO_PB_SW3 : in std_ulogic; -- pin C3 LVCMOS33 connected to push-button GPIO_PB_SW3 SW18
signal GPIO_LED : out count_type -- LEDs at pins D5 (LSB), D6, A5, B5 (MSB) LVCMOS33
);
end entity counter4;
library unisim;
use unisim.vcomponents.all;
architecture behavioral of counter4 is
signal count : count_type;
signal clk125MHz, clk1Hz : std_ulogic := '0';
signal inv_rest : std_ulogic;
signal en : std_ulogic := '1';
signal inv_reset : std_ulogic;
begin
clock_buffer : ibufgds port map (o => clk125MHz, i => CLK_125_P, ib => CLK_125_N);
clock_divider : process is
variable divider_count : natural := 0;
begin
wait until clk125MHz'event and clk125MHz = '1';
if divider_count = 62500000 then
clk1Hz <= not clk1Hz;
divider_count := 0;
else
divider_count := divider_count + 1;
end if;
end process clock_divider;
inv_reset <= not GPIO_PB_SW3;
kami_counter : mkModule1 port map (CLK => clk1Hz,
RST_N => inv_reset,
EN_count_value => en,
count_value => count,
RDY_count_value => open);
GPIO_LED <= count;
end architecture behavioral;
|
apache-2.0
|
vikene/vhdl
|
Gates and drivers/DRIVER.vhd
|
1
|
335
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DRIVER IS
PORT(A:IN STD_LOGIC;
B:OUT STD_LOGIC);
END DRIVER;
ARCHITECTURE DRIVE OF DRIVER IS
BEGIN
B <= A;
END DRIVE;
|
apache-2.0
|
Paebbels/PicoBlaze-Library
|
netlist/XC6SLX45-3CSG324/CSP_PB_Tracer_ILA.vhdl
|
1
|
1261
|
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_PB_Tracer_ILA.vhd
-- /___/ /\ Timestamp : Sat Jun 27 15:57:29 Mitteleuropäische Sommerzeit 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_PB_Tracer_ILA IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(62 downto 0);
TRIG0: in std_logic_vector(14 downto 0);
TRIG1: in std_logic_vector(7 downto 0);
TRIG2: in std_logic_vector(5 downto 0);
TRIG3: in std_logic_vector(15 downto 0);
TRIG_OUT: out std_logic);
END CSP_PB_Tracer_ILA;
ARCHITECTURE CSP_PB_Tracer_ILA_a OF CSP_PB_Tracer_ILA IS
BEGIN
END CSP_PB_Tracer_ILA_a;
|
apache-2.0
|
keedio/hue
|
tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ipshared/f4d9/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd
|
1
|
157442
|
-------------------------------------------------------------------------------
-- lmb_bram_if_funcs.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: lmb_bram_if_funcs.vhd
--
-- Description: Support functions for lmb_bram_if_cntlr
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_funcs.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package lmb_bram_if_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
VIRTEX7,
KINTEX7,
ARTIX7,
ZYNQ,
VIRTEXU,
KINTEXU,
ZYNQUPLUS,
VIRTEXUPLUS,
KINTEXUPLUS,
SPARTAN7,
-- pragma xilinx_rtl_on
RTL
);
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
end package lmb_bram_if_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body lmb_bram_if_funcs is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END Equal_String;
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
begin -- function String_To_Family
if ((Select_RTL) or Equal_String(S, "rtl")) then
return RTL;
elsif Equal_String(S, "virtex7") or Equal_String(S, "qvirtex7") then
return VIRTEX7;
elsif Equal_String(S, "kintex7") or Equal_String(S, "kintex7l") or
Equal_String(S, "qkintex7") or Equal_String(S, "qkintex7l") then
return KINTEX7;
elsif Equal_String(S, "artix7") or Equal_String(S, "artix7l") or Equal_String(S, "aartix7") or
Equal_String(S, "qartix7") or Equal_String(S, "qartix7l") then
return ARTIX7;
elsif Equal_String(S, "zynq") or Equal_String(S, "azynq") or Equal_String(S, "qzynq") then
return ZYNQ;
elsif Equal_String(S, "virtexu") or Equal_String(S, "qvirtexu") then
return VIRTEXU;
elsif Equal_String(S, "kintexu") or Equal_String(S, "kintexul") or
Equal_String(S, "qkintexu") or Equal_String(S, "qkintexul") then
return KINTEXU;
elsif Equal_String(S, "zynquplus") then
return ZYNQUPLUS;
elsif Equal_String(S, "virtexuplus") then
return VIRTEXUPLUS;
elsif Equal_String(S, "kintexuplus") then
return KINTEXUPLUS;
elsif Equal_String(S, "spartan7") then
return SPARTAN7;
else
-- assert (false) report "No known target family" severity failure;
return RTL;
end if;
end function String_To_Family;
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer is
begin
return 6;
end function Family_To_LUT_Size;
end package body lmb_bram_if_funcs;
-------------------------------------------------------------------------------
-- primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: primitives.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- rolandp 2015-01-22 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
----- entity LUT6 -----
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end entity MB_LUT6;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_LUT6 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
begin
process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
variable I0_v, I1_v, I2_v, I3_v, I4_v, I5_v : std_logic;
begin
-- Filter unknowns
if I0 = '0' then I0_v := '0'; else I0_v := '1'; end if;
if I1 = '0' then I1_v := '0'; else I1_v := '1'; end if;
if I2 = '0' then I2_v := '0'; else I2_v := '1'; end if;
if I3 = '0' then I3_v := '0'; else I3_v := '1'; end if;
if I4 = '0' then I4_v := '0'; else I4_v := '1'; end if;
if I5 = '0' then I5_v := '0'; else I5_v := '1'; end if;
I_reg := TO_STDLOGICVECTOR(I5_v & I4_v & I3_v & I2_v & I1_v & I0_v);
O <= INIT_reg(TO_INTEGER(unsigned(I_reg)));
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: LUT6
generic map(
INIT => INIT
)
port map(
O => O,
I0 => I0,
I1 => I1,
I2 => I2,
I3 => I3,
I4 => I4,
I5 => I5
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end entity MB_MUXCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
LO <= DI when S = '0' else CI;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXCY_L
port map(
LO => LO,
CI => CI,
DI => DI,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity XORCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end entity MB_XORCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_XORCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= (CI xor LI);
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: XORCY
port map(
O => O,
CI => CI,
LI => LI
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXF7 -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end entity MB_MUXF7;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXF7 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= I0 when S = '0' else I1;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXF7
port map(
O => O,
I0 => I0,
I1 => I1,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXF8 -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end entity MB_MUXF8;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXF8 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= I0 when S = '0' else I1;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXF8
port map(
O => O,
I0 => I0,
I1 => I1,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity FDRE -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_FDRE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end entity MB_FDRE;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_FDRE is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
function To_StdLogic(A : in bit ) return std_logic is
begin
if( A = '1' ) then
return '1';
end if;
return '0';
end;
signal q_o : std_logic := To_StdLogic(INIT);
begin
Q <= q_o;
process(C)
begin
if (rising_edge(C)) then
if (R = '1') then
q_o <= '0';
elsif (CE = '1') then
q_o <= D;
end if;
end if;
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: FDRE
generic map(
INIT => INIT
)
port map(
Q => Q,
C => C,
CE => CE,
D => D,
R => R
);
end generate Using_FPGA;
end architecture IMP;
-------------------------------------------------------------------------------
-- xor18.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: xor18.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- xor18.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity XOR18 is
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end entity XOR18;
architecture IMP of XOR18 is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
component MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component MB_XORCY;
begin -- architecture IMP
Using_FPGA: if ( C_TARGET /= RTL ) generate
signal xor6_1 : std_logic;
signal xor6_2 : std_logic;
signal xor6_3 : std_logic;
signal xor18_c1 : std_logic;
signal xor18_c2 : std_logic;
begin -- generate Using_LUT6
XOR6_1_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_1,
I0 => InA(17),
I1 => InA(16),
I2 => InA(15),
I3 => InA(14),
I4 => InA(13),
I5 => InA(12));
XOR_1st_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => '1',
CI => '0',
S => xor6_1,
LO => xor18_c1);
XOR6_2_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_2,
I0 => InA(11),
I1 => InA(10),
I2 => InA(9),
I3 => InA(8),
I4 => InA(7),
I5 => InA(6));
XOR_2nd_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => xor6_1,
CI => xor18_c1,
S => xor6_2,
LO => xor18_c2);
XOR6_3_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_3,
I0 => InA(5),
I1 => InA(4),
I2 => InA(3),
I3 => InA(2),
I4 => InA(1),
I5 => InA(0));
XOR18_XORCY : MB_XORCY
generic map(
C_TARGET => C_TARGET)
port map (
LI => xor6_3,
CI => xor18_c2,
O => res);
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);
end generate Using_RTL;
end architecture IMP;
-------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
-------------------------------------------------------------------------------
-- parityenable.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity ParityEnable is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 4
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic
);
end entity ParityEnable;
architecture IMP of ParityEnable is
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
begin -- architecture IMP
Using_FPGA: if ( C_TARGET /= RTL ) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 5 generate
signal inA5 : std_logic_vector(0 to 4);
begin
Assign_InA : process (InA) is
begin
inA5 <= (others => '0');
inA5(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699600000000")
port map(
O => Res,
I0 => InA5(4),
I1 => inA5(3),
I2 => inA5(2),
I3 => inA5(1),
I4 => inA5(0),
I5 => Enable);
end generate Single_LUT6;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= Enable and ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
-------------------------------------------------------------------------------
-- checkbit_handler.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: gen_checkbits.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- gen_checkbits.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean := true);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
architecture IMP of checkbit_handler is
component XOR18 is
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
component ParityEnable
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic);
end component ParityEnable;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (
C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_TARGET => C_TARGET) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
-- Unused
Syndrome <= (others => '0');
UE <= '0';
CE <= '0';
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6);
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_3_to_5 : std_logic_vector(3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
Parity_chk3_3 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 2)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
Parity_chk6_7 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
Syndrome <= syndrome_i;
syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101") else
'0';
CE <= '0' when (Enable_ECC = '0') else
(syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else
CE_Q;
ue_i_0 <= '0' when (Enable_ECC = '0') else
'1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else
UE_Q;
ue_i_1 <= '0' when (Enable_ECC = '0') else
(syndrome_3_to_5_multi or UE_Q);
Use_FPGA: if (C_TARGET /= RTL) generate
UE_MUXF7 : MB_MUXF7
generic map (
C_TARGET => C_TARGET)
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => syndrome_i(6),
O => UE);
end generate Use_FPGA;
Use_RTL: if (C_TARGET = RTL) generate
UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0;
end generate Use_RTL;
-- Unused
CheckOut <= (others => '0');
end generate Decode_Bits;
end architecture IMP;
-------------------------------------------------------------------------------
-- correct_one_bit.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- correct_one_bit
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity Correct_One_Bit is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
component MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component MB_XORCY;
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : MB_XORCY
generic map(
C_TARGET => C_TARGET)
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
-------------------------------------------------------------------------------
-- pselect_mask.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 63) := X"0000000000020000";
C_MASK : std_logic_vector(0 to 63) := X"000000000007C000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
architecture imp of pselect_mask is
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK(64 - C_AW to 63));
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in 0 to C_AW - 1 loop
if (C_MASK(64 - C_AW + I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(64 - C_AW + I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
CS <= Valid when A_Bus=BAR else '0';
end imp;
-------------------------------------------------------------------------------
-- axi_interface.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: axi_interface.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_interface.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity axi_interface is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- lmb_bram_if_cntlr signals
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_interface;
architecture IMP of axi_interface is
component MB_FDRE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component MB_FDRE;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal ongoing_write : std_logic;
signal ongoing_read : std_logic;
signal S_AXI_RVALID_i : std_logic;
signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Only allow one access at a time
new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Store register address and write data
Reg: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
RegAddr <= (others => '0');
RegWrData <= (others => '0');
elsif new_write_access = '1' then
RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
elsif new_read_access = '1' then
RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
end if;
end if;
end process Reg;
-- Handle write access.
WriteAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_write <= '0';
elsif new_write_access = '1' then
ongoing_write <= '1';
elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
ongoing_write <= '0';
end if;
RegWr <= new_write_access;
end if;
end process WriteAccess;
S_AXI_BVALID <= ongoing_write;
S_AXI_BRESP <= (others => '0');
-- Handle read access
ReadAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
elsif new_read_access = '1' then
ongoing_read <= '1';
S_AXI_RVALID_i <= '0';
elsif ongoing_read = '1' then
if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
else
S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
end if;
end if;
end if;
end process ReadAccess;
S_AXI_RVALID <= S_AXI_RVALID_i;
S_AXI_RRESP <= (others => '0');
Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_Bits_Are_Used;
RegRdData_i <= RegRdData; -- Swap to - downto
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : MB_FDRE
generic map (
C_TARGET => C_TARGET)
port map (
Q => S_AXI_RDATA(I),
C => LMB_Clk,
CE => ongoing_read,
D => RegRdData_i(I),
R => LMB_Rst);
end generate S_AXI_RDATA_DFF;
end architecture IMP;
-------------------------------------------------------------------------------
-- lmb_mux.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_mux.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_mux.vhd
-- pselct_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
C_MASK : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end entity lmb_mux;
architecture imp of lmb_mux is
component pselect_mask
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 63) := X"0000000000000000";
C_MASK : std_logic_vector(0 to 63) := X"0000000000800000");
port (
A : in std_logic_vector(0 to C_AW - 1);
CS : out std_logic;
Valid : in std_logic);
end component;
signal one : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
LMB1_no: if (C_NUM_LMB < 2) generate
Sl1_DBus <= (others => '0');
Sl1_Ready <= '0';
Sl1_Wait <= '0';
Sl1_UE <= '0';
Sl1_CE <= '0';
end generate LMB1_no;
LMB2_no: if (C_NUM_LMB < 3) generate
Sl2_DBus <= (others => '0');
Sl2_Ready <= '0';
Sl2_Wait <= '0';
Sl2_UE <= '0';
Sl2_CE <= '0';
end generate LMB2_no;
LMB3_no: if (C_NUM_LMB < 4) generate
Sl3_DBus <= (others => '0');
Sl3_Ready <= '0';
Sl3_Wait <= '0';
Sl3_UE <= '0';
Sl3_CE <= '0';
end generate LMB3_no;
one <= '1';
one_lmb: if (C_NUM_LMB = 1) generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_MASK)
port map (
A => LMB0_ABus,
CS => lmb_select,
Valid => one);
LMB_ABus <= LMB0_ABus;
LMB_WriteDBus <= LMB0_WriteDBus;
LMB_AddrStrobe <= LMB0_AddrStrobe;
LMB_ReadStrobe <= LMB0_ReadStrobe;
LMB_WriteStrobe <= LMB0_WriteStrobe;
LMB_BE <= LMB0_BE;
Sl0_DBus <= Sl_DBus;
Sl0_Ready <= Sl_Ready;
Sl0_Wait <= Sl_Wait;
Sl0_UE <= Sl_UE;
Sl0_CE <= Sl_CE;
end generate one_lmb;
more_than_one_lmb: if (C_NUM_LMB > 1) generate
type C_Mask_Vec_T is array (0 to 3) of std_logic_vector(0 to 63);
constant C_Mask_Vec : C_MASK_Vec_T := (C_MASK, C_MASK1, C_MASK2, C_MASK3);
type ABus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_AWIDTH - 1);
type DBus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH - 1);
type BE_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH/8 - 1);
signal LMB_ABus_vec : ABus_vec_T;
signal LMB_ABus_vec_i : ABus_vec_T;
signal LMB_ABus_vec_Q : ABus_vec_T;
signal LMB_WriteDBus_vec : DBus_vec_T;
signal LMB_WriteDBus_vec_i : DBus_vec_T;
signal LMB_WriteDBus_vec_Q : DBus_vec_T;
signal LMB_AddrStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_BE_vec : BE_vec_T;
signal LMB_BE_vec_i : BE_vec_T;
signal LMB_BE_vec_Q : BE_vec_T;
signal Sl_DBus_vec : DBus_vec_T;
signal Sl_Ready_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_Wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_UE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_CE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal as_and_lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal ongoing : natural range 0 to C_NUM_LMB-1;
signal ongoing_new : natural range 0 to C_NUM_LMB-1;
signal ongoing_Q : natural range 0 to C_NUM_LMB-1;
begin
LMB_ABus_vec(0) <= LMB0_ABus;
LMB_WriteDBus_vec(0) <= LMB0_WriteDBus;
LMB_AddrStrobe_vec(0) <= LMB0_AddrStrobe;
LMB_ReadStrobe_vec(0) <= LMB0_ReadStrobe;
LMB_WriteStrobe_vec(0) <= LMB0_WriteStrobe;
LMB_BE_vec(0) <= LMB0_BE;
Sl0_DBus <= Sl_DBus_vec(0);
Sl0_Ready <= Sl_Ready_vec(0);
Sl0_Wait <= Sl_Wait_vec(0);
Sl0_UE <= Sl_UE_vec(0);
Sl0_CE <= Sl_CE_vec(0);
LMB_ABus_vec(1) <= LMB1_ABus;
LMB_WriteDBus_vec(1) <= LMB1_WriteDBus;
LMB_AddrStrobe_vec(1) <= LMB1_AddrStrobe;
LMB_ReadStrobe_vec(1) <= LMB1_ReadStrobe;
LMB_WriteStrobe_vec(1) <= LMB1_WriteStrobe;
LMB_BE_vec(1) <= LMB1_BE;
Sl1_DBus <= Sl_DBus_vec(1);
Sl1_Ready <= Sl_Ready_vec(1);
Sl1_Wait <= Sl_Wait_vec(1);
Sl1_UE <= Sl_UE_vec(1);
Sl1_CE <= Sl_CE_vec(1);
LMB2_yes: if (C_NUM_LMB > 2) generate
LMB_ABus_vec(2) <= LMB2_ABus;
LMB_WriteDBus_vec(2) <= LMB2_WriteDBus;
LMB_AddrStrobe_vec(2) <= LMB2_AddrStrobe;
LMB_ReadStrobe_vec(2) <= LMB2_ReadStrobe;
LMB_WriteStrobe_vec(2) <= LMB2_WriteStrobe;
LMB_BE_vec(2) <= LMB2_BE;
Sl2_DBus <= Sl_DBus_vec(2);
Sl2_Ready <= Sl_Ready_vec(2);
Sl2_Wait <= Sl_Wait_vec(2);
Sl2_UE <= Sl_UE_vec(2);
Sl2_CE <= Sl_CE_vec(2);
end generate LMB2_yes;
LMB3_yes: if (C_NUM_LMB > 3) generate
LMB_ABus_vec(3) <= LMB3_ABus;
LMB_WriteDBus_vec(3) <= LMB3_WriteDBus;
LMB_AddrStrobe_vec(3) <= LMB3_AddrStrobe;
LMB_ReadStrobe_vec(3) <= LMB3_ReadStrobe;
LMB_WriteStrobe_vec(3) <= LMB3_WriteStrobe;
LMB_BE_vec(3) <= LMB3_BE;
Sl3_DBus <= Sl_DBus_vec(3);
Sl3_Ready <= Sl_Ready_vec(3);
Sl3_Wait <= Sl_Wait_vec(3);
Sl3_UE <= Sl_UE_vec(3);
Sl3_CE <= Sl_CE_vec(3);
end generate LMB3_yes;
lmb_mux_generate: for I in 0 to C_NUM_LMB-1 generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_Mask_Vec(I))
port map (
A => LMB_ABus_vec(I),
CS => lmb_select_vec(I),
Valid => one);
as_and_lmb_select_vec(I) <= lmb_select_vec(I) and LMB_AddrStrobe_vec(I);
remember_access : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
LMB_ABus_vec_Q(I) <= (others => '0');
LMB_WriteDBus_vec_Q(I) <= (others => '0');
LMB_AddrStrobe_vec_Q(I) <= '0';
LMB_ReadStrobe_vec_Q(I) <= '0';
LMB_WriteStrobe_vec_Q(I) <= '0';
LMB_BE_vec_Q(I) <= (others => '0');
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
LMB_ABus_vec_Q(I) <= LMB_ABus_vec(I);
LMB_WriteDBus_vec_Q(I) <= LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_Q(I) <= LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_Q(I) <= LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_Q(I) <= LMB_WriteStrobe_vec(I);
LMB_BE_vec_Q(I) <= LMB_BE_vec(I);
end if;
end if;
end process remember_access;
wait_proc : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
wait_vec(I) <= '0';
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
wait_vec(I) <= '1';
elsif (wait_vec(I) = '1' and ongoing = I) then
wait_vec(I) <= '0';
end if;
end if;
end process wait_proc;
LMB_ABus_vec_i(I) <= LMB_ABus_vec_Q(I) when wait_vec(I) = '1' else
LMB_ABus_vec(I);
LMB_WriteDBus_vec_i(I) <= LMB_WriteDBus_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_i(I) <= LMB_AddrStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_i(I) <= LMB_ReadStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_i(I) <= LMB_WriteStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteStrobe_vec(I);
LMB_BE_vec_i(I) <= LMB_BE_vec_Q(I) when wait_vec(I) = '1' else
LMB_BE_vec(I);
-- Assign selected LMB from internal signals
Sl_DBus_vec(I) <= Sl_DBus;
Sl_Ready_vec(I) <= Sl_Ready when ongoing_Q = I else
'0';
Sl_Wait_vec(I) <= Sl_Wait when ongoing_Q = I else
wait_vec(I);
Sl_UE_vec(I) <= Sl_UE when ongoing_Q = I else
'0';
Sl_CE_vec(I) <= Sl_CE when ongoing_Q = I else
'0';
end generate lmb_mux_generate;
OnGoing_Reg : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
ongoing_Q <= 0;
else
ongoing_Q <= ongoing;
end if;
end if;
end process OnGoing_Reg;
Arbit : process (as_and_lmb_select_vec, wait_vec) is
variable N : natural range 0 to C_NUM_LMB-1;
begin
ongoing_new <= 0;
for N in 0 to C_NUM_LMB - 1 loop
if as_and_lmb_select_vec(N) = '1' or wait_vec(N) = '1' then
ongoing_new <= N;
exit;
end if;
end loop;
end process Arbit;
ongoing <= ongoing_Q when Sl_Wait = '1' and Sl_Ready = '0' else
ongoing_new;
-- Assign selected LMB
LMB_ABus <= LMB_ABus_vec_i(ongoing);
LMB_WriteDBus <= LMB_WriteDBus_vec_i(ongoing);
LMB_AddrStrobe <= LMB_AddrStrobe_vec_i(ongoing);
LMB_ReadStrobe <= LMB_ReadStrobe_vec_i(ongoing);
LMB_WriteStrobe <= LMB_WriteStrobe_vec_i(ongoing);
LMB_BE <= LMB_BE_vec_i(ongoing);
lmb_select <= lmb_select_vec(ongoing) or wait_vec(ongoing);
end generate more_than_one_lmb;
end imp;
-------------------------------------------------------------------------------
-- lmb_bram_if_cntlr.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 63) := X"0000000000000000";
C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
C_MASK : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- BRAM generic
C_BRAM_AWIDTH : integer := 32;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_BRAM_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
C_MASK : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
assert C_LMB_AWIDTH >= C_BRAM_AWIDTH
report "C_LMB_AWIDTH must be greater than or equal to C_BRAM_AWIDTH"
severity failure;
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i(C_LMB_AWIDTH - C_BRAM_AWIDTH to C_LMB_AWIDTH - 1);
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
assert C_LMB_DWIDTH = 32 report "C_LMB_DWIDTH must be 32 when C_ECC = 1" severity failure;
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => false) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_TARGET => C_TARGET,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr(C_LMB_AWIDTH - C_BRAM_AWIDTH to C_LMB_AWIDTH - 1);
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => true) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
BRAM_Dout_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_TARGET => C_TARGET,
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ip/system_dlmb_bram_if_cntlr_0/sim/system_dlmb_bram_if_cntlr_0.vhd
|
1
|
12257
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0_10;
USE lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_cntlr;
ENTITY system_dlmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END system_dlmb_bram_if_cntlr_0;
ARCHITECTURE system_dlmb_bram_if_cntlr_0_arch OF system_dlmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_BASEADDR : STD_LOGIC_VECTOR;
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR;
C_MASK1 : STD_LOGIC_VECTOR;
C_MASK2 : STD_LOGIC_VECTOR;
C_MASK3 : STD_LOGIC_VECTOR;
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_BRAM_AWIDTH : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"0000000000007FFF",
C_BASEADDR => X"0000000000000000",
C_NUM_LMB => 1,
C_MASK => X"00000000c0000000",
C_MASK1 => X"0000000000800000",
C_MASK2 => X"0000000000800000",
C_MASK3 => X"0000000000800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_BRAM_AWIDTH => 32,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END system_dlmb_bram_if_cntlr_0_arch;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_wiz_0_0_family_support.vhd
|
1
|
404661
|
--------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.system_xadc_wiz_0_0_family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.system_xadc_wiz_0_0_family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package system_xadc_wiz_0_0_family_support is
type families_type is
(
nofamily
, virtex
, spartan2
, spartan2e
, virtexe
, virtex2
, qvirtex2 -- Taken to be identical to the virtex2 primitive set.
, qrvirtex2 -- Taken to be identical to the virtex2 primitive set.
, virtex2p
, spartan3
, aspartan3
, virtex4
, virtex4lx
, virtex4fx
, virtex4sx
, spartan3e
, virtex5
, spartan3a
, spartan3an
, spartan3adsp
, aspartan3e
, aspartan3a
, aspartan3adsp
, qvirtex4
, qrvirtex4
, spartan6
, virtex6
, spartan6l
, qspartan6
, aspartan6
, virtex6l
, qspartan6l
, qvirtex5
, qvirtex6
, qrvirtex5
, virtex5tx
, virtex5fx
, virtex6cx
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artix7
, aartix7
, artix7l
, qartix7
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 798;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package system_xadc_wiz_0_0_family_support;
package body system_xadc_wiz_0_0_family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2 => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2e => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtexe => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2p => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4lx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4fx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4sx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3an => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5tx => (
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n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5fx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6cx => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
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kintex7l => (
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artix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtex => return "virtex" ;
when spartan2 => return "spartan2" ;
when spartan2e => return "spartan2e" ;
when virtexe => return "virtexe" ;
when virtex2 => return "virtex2" ;
when qvirtex2 => return "qvirtex2" ;
when qrvirtex2 => return "qrvirtex2" ;
when virtex2p => return "virtex2p" ;
when spartan3 => return "spartan3" ;
when aspartan3 => return "aspartan3" ;
when spartan3e => return "spartan3e" ;
when virtex4 => return "virtex4" ;
when virtex4lx => return "virtex4lx" ;
when virtex4fx => return "virtex4fx" ;
when virtex4sx => return "virtex4sx" ;
when virtex5 => return "virtex5" ;
when spartan3a => return "spartan3a" ;
when spartan3an => return "spartan3an" ;
when spartan3adsp => return "spartan3adsp" ;
when aspartan3e => return "aspartan3e" ;
when aspartan3a => return "aspartan3a" ;
when aspartan3adsp => return "aspartan3adsp";
when qvirtex4 => return "qvirtex4" ;
when qrvirtex4 => return "qrvirtex4" ;
when spartan6 => return "spartan6" ;
when virtex6 => return "virtex6" ;
when spartan6l => return "spartan6l" ;
when qspartan6 => return "qspartan6" ;
when aspartan6 => return "aspartan6" ;
when virtex6l => return "virtex6l" ;
when qspartan6l => return "qspartan6l" ;
when qvirtex5 => return "qvirtex5" ;
when qvirtex6 => return "qvirtex6" ;
when qrvirtex5 => return "qrvirtex5" ;
when virtex5tx => return "virtex5tx" ;
when virtex5fx => return "virtex5fx" ;
when virtex6cx => return "virtex6cx" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- spartan3 Root family
if (equalIgnoringCase(family_in, "spartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3an" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3e" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3e" )) Then return "spartan3" ;
-- virtex4 Root family
Elsif (equalIgnoringCase(family_in, "virtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4lx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4fx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4sx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qvirtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex4" )) Then return "virtex4" ;
-- virtex5 Root family
Elsif (equalIgnoringCase(family_in, "virtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5tx" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5fx" )) Then return "virtex5" ;
-- virtex6 Root family
Elsif (equalIgnoringCase(family_in, "virtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6l" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "qvirtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6cx" )) Then return "virtex6" ;
-- spartan6 Root family
Elsif (equalIgnoringCase(family_in, "spartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "spartan6l" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "aspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6l" )) Then return "spartan6" ;
-- Virtex7 Root family
Elsif (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package system_xadc_wiz_0_0_family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body system_xadc_wiz_0_0_family_support;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_quad_spi_shield_0/system_axi_quad_spi_shield_0_stub.vhdl
|
1
|
2843
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:54 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_quad_spi_shield_0/system_axi_quad_spi_shield_0_stub.vhdl
-- Design : system_axi_quad_spi_shield_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_axi_quad_spi_shield_0 is
Port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
end system_axi_quad_spi_shield_0;
architecture stub of system_axi_quad_spi_shield_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2016.4";
begin
end;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_uartlite_0_0/system_axi_uartlite_0_0_sim_netlist.vhdl
|
1
|
125504
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:56 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_uartlite_0_0/system_axi_uartlite_0_0_sim_netlist.vhdl
-- Design : system_axi_uartlite_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_baudrate is
port (
en_16x_Baud : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_baudrate : entity is "baudrate";
end system_axi_uartlite_0_0_baudrate;
architecture STRUCTURE of system_axi_uartlite_0_0_baudrate is
signal \^en_16x_baud\ : STD_LOGIC;
signal count : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \count[2]_i_2_n_0\ : STD_LOGIC;
signal \count[4]_i_2_n_0\ : STD_LOGIC;
signal \count[4]_i_3_n_0\ : STD_LOGIC;
signal \count[9]_i_2_n_0\ : STD_LOGIC;
signal count_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \count[2]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \count[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \count[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \count[4]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \count[9]_i_2\ : label is "soft_lutpair11";
begin
EN_16x_Baud_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \count[9]_i_2_n_0\,
I1 => count(5),
I2 => count(6),
I3 => count(9),
I4 => count(7),
I5 => count(8),
O => \^en_16x_baud\
);
EN_16x_Baud_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^en_16x_baud\,
Q => en_16x_Baud,
R => SR(0)
);
\count[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF0000FFFE"
)
port map (
I0 => count(3),
I1 => count(4),
I2 => \count[2]_i_2_n_0\,
I3 => count(2),
I4 => count(0),
I5 => count(1),
O => count_0(0)
);
\count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count(1),
I1 => count(0),
O => count_0(1)
);
\count[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E1E1E1E1E1E1E1E0"
)
port map (
I0 => count(1),
I1 => count(0),
I2 => count(2),
I3 => \count[2]_i_2_n_0\,
I4 => count(4),
I5 => count(3),
O => count_0(2)
);
\count[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => count(9),
I1 => count(7),
I2 => count(8),
I3 => count(6),
I4 => count(5),
O => \count[2]_i_2_n_0\
);
\count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => count(3),
I1 => count(1),
I2 => count(0),
I3 => count(2),
O => count_0(3)
);
\count[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A9A9A9A9A9A9A9A8"
)
port map (
I0 => count(4),
I1 => count(3),
I2 => \count[4]_i_2_n_0\,
I3 => \count[4]_i_3_n_0\,
I4 => count(6),
I5 => count(5),
O => count_0(4)
);
\count[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => count(1),
I1 => count(0),
I2 => count(2),
O => \count[4]_i_2_n_0\
);
\count[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => count(8),
I1 => count(7),
I2 => count(9),
O => \count[4]_i_3_n_0\
);
\count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00000000FFFE"
)
port map (
I0 => count(9),
I1 => count(7),
I2 => count(8),
I3 => count(6),
I4 => count(5),
I5 => \count[9]_i_2_n_0\,
O => count_0(5)
);
\count[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A9A9A9A9A9A9A9A8"
)
port map (
I0 => count(6),
I1 => count(5),
I2 => \count[9]_i_2_n_0\,
I3 => count(8),
I4 => count(7),
I5 => count(9),
O => count_0(6)
);
\count[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => count(7),
I1 => count(6),
I2 => count(5),
I3 => \count[9]_i_2_n_0\,
O => count_0(7)
);
\count[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FE01FF00FE00"
)
port map (
I0 => \count[9]_i_2_n_0\,
I1 => count(5),
I2 => count(6),
I3 => count(8),
I4 => count(7),
I5 => count(9),
O => count_0(8)
);
\count[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F0F0F0E1"
)
port map (
I0 => count(8),
I1 => count(7),
I2 => count(9),
I3 => count(6),
I4 => count(5),
I5 => \count[9]_i_2_n_0\,
O => count_0(9)
);
\count[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => count(4),
I1 => count(3),
I2 => count(2),
I3 => count(0),
I4 => count(1),
O => \count[9]_i_2_n_0\
);
\count_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(0),
Q => count(0),
R => SR(0)
);
\count_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(1),
Q => count(1),
R => SR(0)
);
\count_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(2),
Q => count(2),
R => SR(0)
);
\count_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(3),
Q => count(3),
R => SR(0)
);
\count_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(4),
Q => count(4),
R => SR(0)
);
\count_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(5),
Q => count(5),
R => SR(0)
);
\count_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(6),
Q => count(6),
R => SR(0)
);
\count_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(7),
Q => count(7),
R => SR(0)
);
\count_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(8),
Q => count(8),
R => SR(0)
);
\count_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(9),
Q => count(9),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_cdc_sync is
port (
p_26_out : out STD_LOGIC;
scndry_out : out STD_LOGIC;
start_Edge_Detected : in STD_LOGIC;
EN_16x_Baud_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rx : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_cdc_sync : entity is "cdc_sync";
end system_axi_uartlite_0_0_cdc_sync;
architecture STRUCTURE of system_axi_uartlite_0_0_cdc_sync is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rx,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
\SERIAL_TO_PARALLEL[1].fifo_din[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00CE00"
)
port map (
I0 => \^scndry_out\,
I1 => start_Edge_Detected,
I2 => EN_16x_Baud_reg,
I3 => s_axi_aresetn,
I4 => \in\(0),
O => p_26_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_cntr_incr_decr_addn_f is
port (
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
fifo_full_p1 : out STD_LOGIC;
tx_Start0 : out STD_LOGIC;
reset_TX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
fifo_Read : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
tx_Buffer_Full : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
tx_Data_Enable_reg : in STD_LOGIC;
tx_DataBits : in STD_LOGIC;
tx_Start : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_cntr_incr_decr_addn_f : entity is "cntr_incr_decr_addn_f";
end system_axi_uartlite_0_0_cntr_incr_decr_addn_f;
architecture STRUCTURE of system_axi_uartlite_0_0_cntr_incr_decr_addn_f is
signal \FIFO_Full_i_2__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal addr_i_p1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[1]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[3]_i_2__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_3__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_4__0\ : label is "soft_lutpair19";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
SS(0) <= \^ss\(0);
FIFO_Full_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004090000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
I1 => \^q\(0),
I2 => \^q\(4),
I3 => fifo_Read,
I4 => \^q\(3),
I5 => \FIFO_Full_i_2__0_n_0\,
O => fifo_full_p1
);
\FIFO_Full_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => \FIFO_Full_i_2__0_n_0\
);
\INFERRED_GEN.cnt_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB4BBBB444B4444"
)
port map (
I0 => \^q\(4),
I1 => fifo_Read,
I2 => tx_Buffer_Full,
I3 => Bus_RNW_reg,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I5 => \^q\(0),
O => addr_i_p1(0)
);
\INFERRED_GEN.cnt_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA9A65AA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(4),
I2 => fifo_Read,
I3 => \^q\(0),
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
O => addr_i_p1(1)
);
\INFERRED_GEN.cnt_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4FF0B00FFBF0040"
)
port map (
I0 => \^q\(4),
I1 => fifo_Read,
I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(1),
O => addr_i_p1(2)
);
\INFERRED_GEN.cnt_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
I5 => \^q\(0),
O => addr_i_p1(3)
);
\INFERRED_GEN.cnt_i[3]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(4),
I1 => fifo_Read,
O => \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\
);
\INFERRED_GEN.cnt_i[4]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => reset_TX_FIFO_reg,
I1 => s_axi_aresetn,
O => \^ss\(0)
);
\INFERRED_GEN.cnt_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0FAFAF003F0F0"
)
port map (
I0 => \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\,
I1 => fifo_Read,
I2 => \^q\(4),
I3 => \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\,
I4 => \^q\(0),
I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
O => addr_i_p1(4)
);
\INFERRED_GEN.cnt_i[4]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \^q\(3),
I1 => fifo_Read,
I2 => \^q\(2),
I3 => \^q\(1),
O => \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\
);
\INFERRED_GEN.cnt_i[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(3),
O => \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\
);
\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(0),
Q => \^q\(0),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(1),
Q => \^q\(1),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(2),
Q => \^q\(2),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(3),
Q => \^q\(3),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(4),
Q => \^q\(4),
S => \^ss\(0)
);
tx_Start_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0F02"
)
port map (
I0 => tx_Data_Enable_reg,
I1 => \^q\(4),
I2 => tx_DataBits,
I3 => tx_Start,
O => tx_Start0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2 is
port (
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
fifo_full_p1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
Interrupt0 : out STD_LOGIC;
reset_RX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
fifo_Write : in STD_LOGIC;
FIFO_Full_reg : in STD_LOGIC;
valid_rx : in STD_LOGIC;
rx_Data_Present_Pre : in STD_LOGIC;
enable_interrupts : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_Buffer_Empty_Pre : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2 : entity is "cntr_incr_decr_addn_f";
end system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2;
architecture STRUCTURE of system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2 is
signal FIFO_Full_i_2_n_0 : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_4_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_6_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal addr_i_p1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of FIFO_Full_i_2 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_5__0\ : label is "soft_lutpair17";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
SS(0) <= \^ss\(0);
\FIFO_Full_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000009040000"
)
port map (
I0 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
I1 => \^q\(0),
I2 => \^q\(4),
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I4 => \^q\(3),
I5 => FIFO_Full_i_2_n_0,
O => fifo_full_p1
);
FIFO_Full_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => FIFO_Full_i_2_n_0
);
\INFERRED_GEN.cnt_i[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F70808F7"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I2 => \^q\(4),
I3 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
I4 => \^q\(0),
O => addr_i_p1(0)
);
\INFERRED_GEN.cnt_i[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA6A5595AAAA"
)
port map (
I0 => \^q\(1),
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \^q\(4),
I4 => \^q\(0),
I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
O => addr_i_p1(1)
);
\INFERRED_GEN.cnt_i[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE017F80"
)
port map (
I0 => \^q\(0),
I1 => Bus_RNW_reg_reg,
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
O => addr_i_p1(2)
);
\INFERRED_GEN.cnt_i[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E178F0F0F0"
)
port map (
I0 => \^q\(0),
I1 => Bus_RNW_reg_reg,
I2 => \^q\(3),
I3 => \^q\(1),
I4 => \^q\(2),
I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
O => addr_i_p1(3)
);
\INFERRED_GEN.cnt_i[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => reset_RX_FIFO_reg,
I1 => s_axi_aresetn,
O => \^ss\(0)
);
\INFERRED_GEN.cnt_i[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F4F4F00AF0F0"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I1 => \INFERRED_GEN.cnt_i[4]_i_4_n_0\,
I2 => \^q\(4),
I3 => \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\,
I4 => \^q\(0),
I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
O => addr_i_p1(4)
);
\INFERRED_GEN.cnt_i[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(3),
O => \INFERRED_GEN.cnt_i[4]_i_4_n_0\
);
\INFERRED_GEN.cnt_i[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(3),
O => \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\
);
\INFERRED_GEN.cnt_i[4]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => fifo_Write,
I1 => FIFO_Full_reg,
I2 => valid_rx,
O => \INFERRED_GEN.cnt_i[4]_i_6_n_0\
);
\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(0),
Q => \^q\(0),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(1),
Q => \^q\(1),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(2),
Q => \^q\(2),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(3),
Q => \^q\(3),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(4),
Q => \^q\(4),
S => \^ss\(0)
);
Interrupt_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"1010F010"
)
port map (
I0 => rx_Data_Present_Pre,
I1 => \^q\(4),
I2 => enable_interrupts,
I3 => \INFERRED_GEN.cnt_i_reg[4]_0\(0),
I4 => tx_Buffer_Empty_Pre,
O => Interrupt0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_dynshreg_f is
port (
mux_Out : out STD_LOGIC;
p_4_in : in STD_LOGIC;
\mux_sel_reg[2]\ : in STD_LOGIC;
\mux_sel_reg[0]\ : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_dynshreg_f : entity is "dynshreg_f";
end system_axi_uartlite_0_0_dynshreg_f;
architecture STRUCTURE of system_axi_uartlite_0_0_dynshreg_f is
signal fifo_DOut : STD_LOGIC_VECTOR ( 0 to 7 );
signal serial_Data_i_2_n_0 : STD_LOGIC;
signal serial_Data_i_3_n_0 : STD_LOGIC;
signal serial_Data_i_4_n_0 : STD_LOGIC;
signal serial_Data_i_5_n_0 : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name : string;
attribute srl_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ";
begin
\INFERRED_GEN.data_reg[15][0]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(0),
Q => fifo_DOut(7)
);
\INFERRED_GEN.data_reg[15][1]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(1),
Q => fifo_DOut(6)
);
\INFERRED_GEN.data_reg[15][2]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(2),
Q => fifo_DOut(5)
);
\INFERRED_GEN.data_reg[15][3]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(3),
Q => fifo_DOut(4)
);
\INFERRED_GEN.data_reg[15][4]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(4),
Q => fifo_DOut(3)
);
\INFERRED_GEN.data_reg[15][5]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(5),
Q => fifo_DOut(2)
);
\INFERRED_GEN.data_reg[15][6]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(6),
Q => fifo_DOut(1)
);
\INFERRED_GEN.data_reg[15][7]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(7),
Q => fifo_DOut(0)
);
serial_Data_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => serial_Data_i_2_n_0,
I1 => serial_Data_i_3_n_0,
I2 => serial_Data_i_4_n_0,
I3 => serial_Data_i_5_n_0,
O => mux_Out
);
serial_Data_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"44400040"
)
port map (
I0 => \mux_sel_reg[2]\,
I1 => p_4_in,
I2 => fifo_DOut(2),
I3 => \mux_sel_reg[0]\,
I4 => fifo_DOut(6),
O => serial_Data_i_2_n_0
);
serial_Data_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"88800080"
)
port map (
I0 => \mux_sel_reg[0]\,
I1 => \mux_sel_reg[2]\,
I2 => fifo_DOut(5),
I3 => p_4_in,
I4 => fifo_DOut(7),
O => serial_Data_i_3_n_0
);
serial_Data_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"44400040"
)
port map (
I0 => \mux_sel_reg[0]\,
I1 => \mux_sel_reg[2]\,
I2 => fifo_DOut(1),
I3 => p_4_in,
I4 => fifo_DOut(3),
O => serial_Data_i_4_n_0
);
serial_Data_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"000A000C"
)
port map (
I0 => fifo_DOut(4),
I1 => fifo_DOut(0),
I2 => p_4_in,
I3 => \mux_sel_reg[2]\,
I4 => \mux_sel_reg[0]\,
O => serial_Data_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_dynshreg_f_3 is
port (
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
valid_rx : in STD_LOGIC;
FIFO_Full_reg : in STD_LOGIC;
fifo_Write : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 7 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_dynshreg_f_3 : entity is "dynshreg_f";
end system_axi_uartlite_0_0_dynshreg_f_3;
architecture STRUCTURE of system_axi_uartlite_0_0_dynshreg_f_3 is
signal fifo_wr : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name : string;
attribute srl_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ";
begin
\INFERRED_GEN.data_reg[15][0]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(7),
Q => \out\(0)
);
\INFERRED_GEN.data_reg[15][0]_srl16_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => valid_rx,
I1 => FIFO_Full_reg,
I2 => fifo_Write,
O => fifo_wr
);
\INFERRED_GEN.data_reg[15][1]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(6),
Q => \out\(1)
);
\INFERRED_GEN.data_reg[15][2]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(5),
Q => \out\(2)
);
\INFERRED_GEN.data_reg[15][3]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(4),
Q => \out\(3)
);
\INFERRED_GEN.data_reg[15][4]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(3),
Q => \out\(4)
);
\INFERRED_GEN.data_reg[15][5]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(2),
Q => \out\(5)
);
\INFERRED_GEN.data_reg[15][6]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(1),
Q => \out\(6)
);
\INFERRED_GEN.data_reg[15][7]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(0),
Q => \out\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_dynshreg_i_f is
port (
p_20_out : out STD_LOGIC;
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ : out STD_LOGIC;
p_17_out : out STD_LOGIC;
p_14_out : out STD_LOGIC;
p_11_out : out STD_LOGIC;
p_8_out : out STD_LOGIC;
p_5_out : out STD_LOGIC;
p_2_out : out STD_LOGIC;
status_reg_reg0 : out STD_LOGIC;
fifo_Write0 : out STD_LOGIC;
stop_Bit_Position_reg : out STD_LOGIC;
frame_err_ocrd_reg : out STD_LOGIC;
running_reg : out STD_LOGIC;
en_16x_Baud : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 7 );
start_Edge_Detected : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
stop_Bit_Position_reg_0 : in STD_LOGIC;
scndry_out : in STD_LOGIC;
clr_Status : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
valid_rx : in STD_LOGIC;
frame_err_ocrd : in STD_LOGIC;
running_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_dynshreg_i_f : entity is "dynshreg_i_f";
end system_axi_uartlite_0_0_dynshreg_i_f;
architecture STRUCTURE of system_axi_uartlite_0_0_dynshreg_i_f is
signal \INFERRED_GEN.data_reg[14][0]_srl15_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.data_reg[15]\ : STD_LOGIC;
signal \^serial_to_parallel[2].fifo_din_reg[2]\ : STD_LOGIC;
signal recycle : STD_LOGIC;
signal \status_reg[1]_i_2_n_0\ : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14] ";
attribute srl_name : string;
attribute srl_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15 ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[14][0]_srl15_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of fifo_Write_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of frame_err_ocrd_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of running_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \status_reg[1]_i_2\ : label is "soft_lutpair15";
begin
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ <= \^serial_to_parallel[2].fifo_din_reg[2]\;
\INFERRED_GEN.data_reg[14][0]_srl15\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
CE => en_16x_Baud,
CLK => s_axi_aclk,
D => recycle,
Q => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\
);
\INFERRED_GEN.data_reg[14][0]_srl15_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => stop_Bit_Position_reg_0,
I1 => valid_rx,
I2 => \INFERRED_GEN.data_reg[15]\,
I3 => start_Edge_Detected,
O => recycle
);
\INFERRED_GEN.data_reg[15][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\,
Q => \INFERRED_GEN.data_reg[15]\,
R => '0'
);
\SERIAL_TO_PARALLEL[2].fifo_din[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(1),
I1 => \in\(0),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_20_out
);
\SERIAL_TO_PARALLEL[3].fifo_din[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(2),
I1 => \in\(1),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_17_out
);
\SERIAL_TO_PARALLEL[4].fifo_din[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(3),
I1 => \in\(2),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_14_out
);
\SERIAL_TO_PARALLEL[5].fifo_din[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(4),
I1 => \in\(3),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_11_out
);
\SERIAL_TO_PARALLEL[6].fifo_din[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(5),
I1 => \in\(4),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_8_out
);
\SERIAL_TO_PARALLEL[7].fifo_din[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(6),
I1 => \in\(5),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_5_out
);
\SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(7),
I1 => \in\(6),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_2_out
);
\SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => en_16x_Baud,
I1 => \INFERRED_GEN.data_reg[15]\,
I2 => stop_Bit_Position_reg_0,
O => \^serial_to_parallel[2].fifo_din_reg[2]\
);
fifo_Write_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \INFERRED_GEN.data_reg[15]\,
I1 => en_16x_Baud,
I2 => stop_Bit_Position_reg_0,
I3 => scndry_out,
O => fifo_Write0
);
frame_err_ocrd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0080"
)
port map (
I0 => \INFERRED_GEN.data_reg[15]\,
I1 => en_16x_Baud,
I2 => stop_Bit_Position_reg_0,
I3 => scndry_out,
I4 => frame_err_ocrd,
O => frame_err_ocrd_reg
);
running_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFA0A0"
)
port map (
I0 => start_Edge_Detected,
I1 => \INFERRED_GEN.data_reg[15]\,
I2 => en_16x_Baud,
I3 => stop_Bit_Position_reg_0,
I4 => running_reg_0,
O => running_reg
);
\status_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F000200"
)
port map (
I0 => \status_reg[1]_i_2_n_0\,
I1 => scndry_out,
I2 => clr_Status,
I3 => s_axi_aresetn,
I4 => status_reg(0),
O => status_reg_reg0
);
\status_reg[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => stop_Bit_Position_reg_0,
I1 => en_16x_Baud,
I2 => \INFERRED_GEN.data_reg[15]\,
O => \status_reg[1]_i_2_n_0\
);
stop_Bit_Position_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2CCC"
)
port map (
I0 => \in\(7),
I1 => stop_Bit_Position_reg_0,
I2 => en_16x_Baud,
I3 => \INFERRED_GEN.data_reg[15]\,
O => stop_Bit_Position_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\ is
port (
tx_Data_Enable_reg : out STD_LOGIC;
en_16x_Baud : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_Data_Enable_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\ : entity is "dynshreg_i_f";
end \system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\;
architecture STRUCTURE of \system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\ is
signal \INFERRED_GEN.data_reg[14][0]_srl15_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.data_reg_n_0_[15][0]\ : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14] ";
attribute srl_name : string;
attribute srl_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15 ";
begin
\INFERRED_GEN.data_reg[14][0]_srl15\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0001"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
CE => en_16x_Baud,
CLK => s_axi_aclk,
D => \INFERRED_GEN.data_reg_n_0_[15][0]\,
Q => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\
);
\INFERRED_GEN.data_reg[15][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\,
Q => \INFERRED_GEN.data_reg_n_0_[15][0]\,
R => '0'
);
tx_Data_Enable_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \INFERRED_GEN.data_reg_n_0_[15][0]\,
I1 => tx_Data_Enable_reg_0,
I2 => en_16x_Baud,
O => tx_Data_Enable_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_pselect_f is
port (
ce_expnd_i_3 : out STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
start2 : in STD_LOGIC;
\bus2ip_addr_i_reg[3]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_pselect_f : entity is "pselect_f";
end system_axi_uartlite_0_0_pselect_f;
architecture STRUCTURE of system_axi_uartlite_0_0_pselect_f is
begin
CS: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => start2,
I2 => \bus2ip_addr_i_reg[3]\,
O => ce_expnd_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_uartlite_0_0_pselect_f__parameterized1\ is
port (
ce_expnd_i_1 : out STD_LOGIC;
\bus2ip_addr_i_reg[3]\ : in STD_LOGIC;
start2 : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_uartlite_0_0_pselect_f__parameterized1\ : entity is "pselect_f";
end \system_axi_uartlite_0_0_pselect_f__parameterized1\;
architecture STRUCTURE of \system_axi_uartlite_0_0_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \bus2ip_addr_i_reg[3]\,
I1 => start2,
I2 => \bus2ip_addr_i_reg[2]\,
O => ce_expnd_i_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_address_decoder is
port (
tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
\s_axi_rresp_i_reg[1]\ : out STD_LOGIC;
enable_interrupts_reg : out STD_LOGIC;
ip2bus_error : out STD_LOGIC;
fifo_wr : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
\state_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC;
FIFO_Full_reg : out STD_LOGIC;
reset_TX_FIFO : out STD_LOGIC;
reset_RX_FIFO : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts_reg_0 : out STD_LOGIC;
tx_Buffer_Empty_Pre_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
\s_axi_bresp_i_reg[1]\ : out STD_LOGIC;
rx_Data_Present_Pre_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_Buffer_Full : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rx_Buffer_Full : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC;
\state_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[0]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rvalid_i_reg_0 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
s_axi_bresp : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i : in STD_LOGIC;
\bus2ip_addr_i_reg[3]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_address_decoder : entity is "address_decoder";
end system_axi_uartlite_0_0_address_decoder;
architecture STRUCTURE of system_axi_uartlite_0_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \^enable_interrupts_reg\ : STD_LOGIC;
signal \^ip2bus_error\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_rresp_i_reg[1]\ : STD_LOGIC;
signal \^tx_buffer_empty_pre_reg\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_5\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[15][0]_srl16_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of clr_Status_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of enable_interrupts_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of reset_RX_FIFO_i_1 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of reset_TX_FIFO_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \s_axi_rdata_i[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axi_rresp_i[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of tx_Buffer_Empty_Pre_i_1 : label is "soft_lutpair6";
begin
enable_interrupts_reg <= \^enable_interrupts_reg\;
ip2bus_error <= \^ip2bus_error\;
s_axi_arready <= \^s_axi_arready\;
s_axi_awready <= \^s_axi_awready\;
\s_axi_rresp_i_reg[1]\ <= \^s_axi_rresp_i_reg[1]\;
tx_Buffer_Empty_Pre_reg <= \^tx_buffer_empty_pre_reg\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i,
I1 => start2,
I2 => \^enable_interrupts_reg\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^enable_interrupts_reg\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => ce_expnd_i_3,
Q => \^s_axi_rresp_i_reg[1]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[2]\,
I2 => \bus2ip_addr_i_reg[3]\,
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => ce_expnd_i_2,
Q => \^tx_buffer_empty_pre_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I1 => \^tx_buffer_empty_pre_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^s_axi_rresp_i_reg[1]\,
I4 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \bus2ip_addr_i_reg[3]\,
I1 => start2,
I2 => \bus2ip_addr_i_reg[2]\,
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
R => cs_ce_clr
);
\INFERRED_GEN.cnt_i[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \^enable_interrupts_reg\,
I1 => \^s_axi_rresp_i_reg[1]\,
I2 => Q(0),
O => \INFERRED_GEN.cnt_i_reg[2]_0\
);
\INFERRED_GEN.cnt_i[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^s_axi_rresp_i_reg[1]\,
I1 => \^enable_interrupts_reg\,
O => FIFO_Full_reg
);
\INFERRED_GEN.cnt_i[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \^tx_buffer_empty_pre_reg\,
I1 => \^enable_interrupts_reg\,
I2 => tx_Buffer_Full,
O => \INFERRED_GEN.cnt_i_reg[2]\
);
\INFERRED_GEN.data_reg[15][0]_srl16_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => tx_Buffer_Full,
I1 => \^enable_interrupts_reg\,
I2 => \^tx_buffer_empty_pre_reg\,
O => fifo_wr
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.system_axi_uartlite_0_0_pselect_f
port map (
\bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg[2]\,
\bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg[3]\,
ce_expnd_i_3 => ce_expnd_i_3,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_uartlite_0_0_pselect_f__parameterized1\
port map (
\bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg[2]\,
\bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg[3]\,
ce_expnd_i_1 => ce_expnd_i_1,
start2 => start2
);
clr_Status_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \^enable_interrupts_reg\,
O => bus2ip_rdce(0)
);
enable_interrupts_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => \^enable_interrupts_reg\,
I3 => enable_interrupts,
O => enable_interrupts_reg_0
);
reset_RX_FIFO_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^enable_interrupts_reg\,
I1 => s_axi_wdata(1),
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
O => reset_RX_FIFO
);
reset_TX_FIFO_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^enable_interrupts_reg\,
I1 => s_axi_wdata(0),
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
O => reset_TX_FIFO
);
rx_Data_Present_Pre_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_rresp_i_reg[1]\,
I2 => \^enable_interrupts_reg\,
I3 => Q(0),
O => rx_Data_Present_Pre_reg
);
s_axi_arready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0F0E0"
)
port map (
I0 => \^s_axi_rresp_i_reg[1]\,
I1 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I2 => \^enable_interrupts_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I4 => \^tx_buffer_empty_pre_reg\,
O => \^s_axi_arready\
);
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^ip2bus_error\,
I1 => \state_reg[1]_1\(1),
I2 => \state_reg[1]_1\(0),
I3 => s_axi_bresp(0),
O => \s_axi_bresp_i_reg[1]\
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_awready\,
I1 => \state_reg[1]_1\(1),
I2 => \state_reg[1]_1\(0),
I3 => s_axi_bready,
I4 => s_axi_bvalid_i_reg_0,
O => s_axi_bvalid_i_reg
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5C005000"
)
port map (
I0 => Q(0),
I1 => \out\(0),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(0)
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => rx_Buffer_Full,
I1 => \out\(1),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(1)
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => \INFERRED_GEN.cnt_i_reg[4]\(0),
I1 => \out\(2),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(2)
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => tx_Buffer_Full,
I1 => \out\(3),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(3)
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => enable_interrupts,
I1 => \out\(4),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(4)
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => status_reg(0),
I1 => \out\(5),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(5)
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => status_reg(1),
I1 => \out\(6),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(6)
);
\s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^s_axi_rresp_i_reg[1]\,
I1 => \^enable_interrupts_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \out\(7),
O => D(7)
);
\s_axi_rresp_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0880088"
)
port map (
I0 => \^tx_buffer_empty_pre_reg\,
I1 => tx_Buffer_Full,
I2 => \^s_axi_rresp_i_reg[1]\,
I3 => \^enable_interrupts_reg\,
I4 => Q(0),
O => \^ip2bus_error\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]_1\(0),
I2 => \state_reg[1]_1\(1),
I3 => s_axi_rready,
I4 => s_axi_rvalid_i_reg_0,
O => s_axi_rvalid_i_reg
);
s_axi_wready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I1 => \^tx_buffer_empty_pre_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^s_axi_rresp_i_reg[1]\,
I4 => \^enable_interrupts_reg\,
O => \^s_axi_awready\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CEFFCEFC"
)
port map (
I0 => \^s_axi_awready\,
I1 => \state_reg[0]\,
I2 => \state_reg[1]_1\(0),
I3 => \state_reg[1]_1\(1),
I4 => s_axi_arvalid,
O => \state_reg[1]\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CEFCCEFCCEFFCEFC"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]_0\,
I2 => \state_reg[1]_1\(1),
I3 => \state_reg[1]_1\(0),
I4 => s_axi_wvalid,
I5 => s_axi_arvalid,
O => \state_reg[1]\(1)
);
tx_Buffer_Empty_Pre_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"8088"
)
port map (
I0 => \INFERRED_GEN.cnt_i_reg[4]\(0),
I1 => s_axi_aresetn,
I2 => \^enable_interrupts_reg\,
I3 => \^tx_buffer_empty_pre_reg\,
O => tx_Buffer_Empty_Pre_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_srl_fifo_rbu_f is
port (
tx_Buffer_Full : out STD_LOGIC;
mux_Out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
tx_Start0 : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
p_4_in : in STD_LOGIC;
\mux_sel_reg[2]\ : in STD_LOGIC;
\mux_sel_reg[0]\ : in STD_LOGIC;
reset_TX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
fifo_Read : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
tx_Data_Enable_reg : in STD_LOGIC;
tx_DataBits : in STD_LOGIC;
tx_Start : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_srl_fifo_rbu_f : entity is "srl_fifo_rbu_f";
end system_axi_uartlite_0_0_srl_fifo_rbu_f;
architecture STRUCTURE of system_axi_uartlite_0_0_srl_fifo_rbu_f is
signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_4 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_5 : STD_LOGIC;
signal TX_FIFO_Reset : STD_LOGIC;
signal fifo_full_p1 : STD_LOGIC;
signal \^tx_buffer_full\ : STD_LOGIC;
begin
tx_Buffer_Full <= \^tx_buffer_full\;
CNTR_INCR_DECR_ADDN_F_I: entity work.system_axi_uartlite_0_0_cntr_incr_decr_addn_f
port map (
Bus_RNW_reg => Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q(4) => Q(0),
Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_2,
Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_3,
Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_4,
Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_5,
SS(0) => TX_FIFO_Reset,
fifo_Read => fifo_Read,
fifo_full_p1 => fifo_full_p1,
reset_TX_FIFO_reg => reset_TX_FIFO_reg,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
tx_Buffer_Full => \^tx_buffer_full\,
tx_DataBits => tx_DataBits,
tx_Data_Enable_reg => tx_Data_Enable_reg,
tx_Start => tx_Start,
tx_Start0 => tx_Start0
);
DYNSHREG_F_I: entity work.system_axi_uartlite_0_0_dynshreg_f
port map (
Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_2,
Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_3,
Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_4,
Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_5,
fifo_wr => fifo_wr,
mux_Out => mux_Out,
\mux_sel_reg[0]\ => \mux_sel_reg[0]\,
\mux_sel_reg[2]\ => \mux_sel_reg[2]\,
p_4_in => p_4_in,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
);
FIFO_Full_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_full_p1,
Q => \^tx_buffer_full\,
R => TX_FIFO_Reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_srl_fifo_rbu_f_1 is
port (
\status_reg_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
Interrupt0 : out STD_LOGIC;
\status_reg_reg[2]_0\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset_RX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
valid_rx : in STD_LOGIC;
fifo_Write : in STD_LOGIC;
rx_Data_Present_Pre : in STD_LOGIC;
enable_interrupts : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_Buffer_Empty_Pre : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
clr_Status : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 7 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_srl_fifo_rbu_f_1 : entity is "srl_fifo_rbu_f";
end system_axi_uartlite_0_0_srl_fifo_rbu_f_1;
architecture STRUCTURE of system_axi_uartlite_0_0_srl_fifo_rbu_f_1 is
signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_4 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_5 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_6 : STD_LOGIC;
signal RX_FIFO_Reset : STD_LOGIC;
signal fifo_full_p1 : STD_LOGIC;
signal \^status_reg_reg[2]\ : STD_LOGIC;
begin
\status_reg_reg[2]\ <= \^status_reg_reg[2]\;
CNTR_INCR_DECR_ADDN_F_I: entity work.system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
FIFO_Full_reg => \^status_reg_reg[2]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\INFERRED_GEN.cnt_i_reg[4]_0\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Interrupt0 => Interrupt0,
Q(4) => Q(0),
Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_3,
Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_4,
Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_5,
Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_6,
SS(0) => RX_FIFO_Reset,
enable_interrupts => enable_interrupts,
fifo_Write => fifo_Write,
fifo_full_p1 => fifo_full_p1,
reset_RX_FIFO_reg => reset_RX_FIFO_reg,
rx_Data_Present_Pre => rx_Data_Present_Pre,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
valid_rx => valid_rx
);
DYNSHREG_F_I: entity work.system_axi_uartlite_0_0_dynshreg_f_3
port map (
FIFO_Full_reg => \^status_reg_reg[2]\,
Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_3,
Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_4,
Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_5,
Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_6,
fifo_Write => fifo_Write,
\in\(0 to 7) => \in\(0 to 7),
\out\(7 downto 0) => \out\(7 downto 0),
s_axi_aclk => s_axi_aclk,
valid_rx => valid_rx
);
FIFO_Full_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_full_p1,
Q => \^status_reg_reg[2]\,
R => RX_FIFO_Reset
);
\status_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EA00"
)
port map (
I0 => status_reg(0),
I1 => fifo_Write,
I2 => \^status_reg_reg[2]\,
I3 => s_axi_aresetn,
I4 => clr_Status,
O => \status_reg_reg[2]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_slave_attachment is
port (
tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
\s_axi_rresp_i_reg[1]_0\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
fifo_wr : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
FIFO_Full_reg : out STD_LOGIC;
reset_TX_FIFO : out STD_LOGIC;
reset_RX_FIFO : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts_reg_0 : out STD_LOGIC;
tx_Buffer_Empty_Pre_reg_0 : out STD_LOGIC;
rx_Data_Present_Pre_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_Buffer_Full : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rx_Buffer_Full : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_slave_attachment : entity is "slave_attachment";
end system_axi_uartlite_0_0_slave_attachment;
architecture STRUCTURE of system_axi_uartlite_0_0_slave_attachment is
signal I_DECODER_n_15 : STD_LOGIC;
signal I_DECODER_n_16 : STD_LOGIC;
signal I_DECODER_n_25 : STD_LOGIC;
signal I_DECODER_n_26 : STD_LOGIC;
signal I_DECODER_n_27 : STD_LOGIC;
signal SIn_DBus : STD_LOGIC_VECTOR ( 0 to 7 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_2_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[2]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[3]\ : STD_LOGIC;
signal bus2ip_rnw_i : STD_LOGIC;
signal bus2ip_rnw_i_i_1_n_0 : STD_LOGIC;
signal ip2bus_error : STD_LOGIC;
signal rst : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair9";
begin
s_axi_bresp(0) <= \^s_axi_bresp\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
I_DECODER: entity work.system_axi_uartlite_0_0_address_decoder
port map (
D(7) => SIn_DBus(0),
D(6) => SIn_DBus(1),
D(5) => SIn_DBus(2),
D(4) => SIn_DBus(3),
D(3) => SIn_DBus(4),
D(2) => SIn_DBus(5),
D(1) => SIn_DBus(6),
D(0) => SIn_DBus(7),
FIFO_Full_reg => FIFO_Full_reg,
\INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\,
\INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Q(0) => Q(0),
\bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg_n_0_[2]\,
\bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg_n_0_[3]\,
bus2ip_rdce(0) => bus2ip_rdce(0),
bus2ip_rnw_i => bus2ip_rnw_i,
enable_interrupts => enable_interrupts,
enable_interrupts_reg => enable_interrupts_reg,
enable_interrupts_reg_0 => enable_interrupts_reg_0,
fifo_wr => fifo_wr,
ip2bus_error => ip2bus_error,
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO => reset_RX_FIFO,
reset_TX_FIFO => reset_TX_FIFO,
rx_Buffer_Full => rx_Buffer_Full,
rx_Data_Present_Pre_reg => rx_Data_Present_Pre_reg,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(0),
\s_axi_bresp_i_reg[1]\ => I_DECODER_n_27,
s_axi_bvalid_i_reg => I_DECODER_n_26,
s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\,
s_axi_rready => s_axi_rready,
\s_axi_rresp_i_reg[1]\ => \s_axi_rresp_i_reg[1]_0\,
s_axi_rvalid_i_reg => I_DECODER_n_25,
s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\,
s_axi_wdata(2 downto 0) => s_axi_wdata(2 downto 0),
s_axi_wvalid => \state[1]_i_3_n_0\,
start2 => start2,
\state_reg[0]\ => \state[0]_i_2_n_0\,
\state_reg[1]\(1) => I_DECODER_n_15,
\state_reg[1]\(0) => I_DECODER_n_16,
\state_reg[1]_0\ => \state[1]_i_2_n_0\,
\state_reg[1]_1\(1 downto 0) => state(1 downto 0),
status_reg(1 downto 0) => status_reg(1 downto 0),
tx_Buffer_Empty_Pre_reg => tx_Buffer_Empty_Pre_reg,
tx_Buffer_Empty_Pre_reg_0 => tx_Buffer_Empty_Pre_reg_0,
tx_Buffer_Full => tx_Buffer_Full
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \bus2ip_addr_i[3]_i_2_n_0\,
I2 => s_axi_araddr(0),
I3 => start2_i_1_n_0,
I4 => \bus2ip_addr_i_reg_n_0_[2]\,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \bus2ip_addr_i[3]_i_2_n_0\,
I2 => s_axi_araddr(1),
I3 => start2_i_1_n_0,
I4 => \bus2ip_addr_i_reg_n_0_[3]\,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => state(1),
I1 => state(0),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[2]\,
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[3]\,
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF7000000F0"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
I5 => bus2ip_rnw_i,
O => bus2ip_rnw_i_i_1_n_0
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_rnw_i_i_1_n_0,
Q => bus2ip_rnw_i,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset,
Q => rst,
R => '0'
);
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_27,
Q => \^s_axi_bresp\(0),
R => rst
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_26,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(7),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(6),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(5),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(4),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(3),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(2),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(1),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(0),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => ip2bus_error,
Q => s_axi_rresp(0),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_25,
Q => \^s_axi_rvalid\,
R => rst
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(0),
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(1),
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_16,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_15,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_srl_fifo_f is
port (
tx_Buffer_Full : out STD_LOGIC;
mux_Out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
tx_Start0 : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
p_4_in : in STD_LOGIC;
\mux_sel_reg[2]\ : in STD_LOGIC;
\mux_sel_reg[0]\ : in STD_LOGIC;
reset_TX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
fifo_Read : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
tx_Data_Enable_reg : in STD_LOGIC;
tx_DataBits : in STD_LOGIC;
tx_Start : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_srl_fifo_f : entity is "srl_fifo_f";
end system_axi_uartlite_0_0_srl_fifo_f;
architecture STRUCTURE of system_axi_uartlite_0_0_srl_fifo_f is
begin
I_SRL_FIFO_RBU_F: entity work.system_axi_uartlite_0_0_srl_fifo_rbu_f
port map (
Bus_RNW_reg => Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q(0) => Q(0),
fifo_Read => fifo_Read,
fifo_wr => fifo_wr,
mux_Out => mux_Out,
\mux_sel_reg[0]\ => \mux_sel_reg[0]\,
\mux_sel_reg[2]\ => \mux_sel_reg[2]\,
p_4_in => p_4_in,
reset_TX_FIFO_reg => reset_TX_FIFO_reg,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
tx_Buffer_Full => tx_Buffer_Full,
tx_DataBits => tx_DataBits,
tx_Data_Enable_reg => tx_Data_Enable_reg,
tx_Start => tx_Start,
tx_Start0 => tx_Start0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_srl_fifo_f_0 is
port (
\status_reg_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
Interrupt0 : out STD_LOGIC;
\status_reg_reg[2]_0\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset_RX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
valid_rx : in STD_LOGIC;
fifo_Write : in STD_LOGIC;
rx_Data_Present_Pre : in STD_LOGIC;
enable_interrupts : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_Buffer_Empty_Pre : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
clr_Status : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 7 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_srl_fifo_f_0 : entity is "srl_fifo_f";
end system_axi_uartlite_0_0_srl_fifo_f_0;
architecture STRUCTURE of system_axi_uartlite_0_0_srl_fifo_f_0 is
begin
I_SRL_FIFO_RBU_F: entity work.system_axi_uartlite_0_0_srl_fifo_rbu_f_1
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Interrupt0 => Interrupt0,
Q(0) => Q(0),
clr_Status => clr_Status,
enable_interrupts => enable_interrupts,
fifo_Write => fifo_Write,
\in\(0 to 7) => \in\(0 to 7),
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO_reg => reset_RX_FIFO_reg,
rx_Data_Present_Pre => rx_Data_Present_Pre,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
status_reg(0) => status_reg(0),
\status_reg_reg[2]\ => \status_reg_reg[2]\,
\status_reg_reg[2]_0\ => \status_reg_reg[2]_0\,
tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
valid_rx => valid_rx
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
fifo_wr : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
FIFO_Full_reg : out STD_LOGIC;
reset_TX_FIFO : out STD_LOGIC;
reset_RX_FIFO : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts_reg : out STD_LOGIC;
tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
rx_Data_Present_Pre_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_Buffer_Full : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rx_Buffer_Full : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_uartlite_0_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_uartlite_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_uartlite_0_0_slave_attachment
port map (
FIFO_Full_reg => FIFO_Full_reg,
\INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\,
\INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Q(0) => Q(0),
bus2ip_rdce(0) => bus2ip_rdce(0),
bus2ip_reset => bus2ip_reset,
enable_interrupts => enable_interrupts,
enable_interrupts_reg => Bus_RNW_reg,
enable_interrupts_reg_0 => enable_interrupts_reg,
fifo_wr => fifo_wr,
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO => reset_RX_FIFO,
reset_TX_FIFO => reset_TX_FIFO,
rx_Buffer_Full => rx_Buffer_Full,
rx_Data_Present_Pre_reg => rx_Data_Present_Pre_reg,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(1 downto 0) => s_axi_araddr(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(1 downto 0) => s_axi_awaddr(1 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
\s_axi_rresp_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(2 downto 0) => s_axi_wdata(2 downto 0),
s_axi_wvalid => s_axi_wvalid,
status_reg(1 downto 0) => status_reg(1 downto 0),
tx_Buffer_Empty_Pre_reg => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
tx_Buffer_Empty_Pre_reg_0 => tx_Buffer_Empty_Pre_reg,
tx_Buffer_Full => tx_Buffer_Full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_uartlite_rx is
port (
\status_reg_reg[2]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
status_reg_reg0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
Interrupt0 : out STD_LOGIC;
\status_reg_reg[2]_0\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
en_16x_Baud : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
clr_Status : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
reset_RX_FIFO_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
rx_Data_Present_Pre : in STD_LOGIC;
enable_interrupts : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_Buffer_Empty_Pre : in STD_LOGIC;
rx : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_uartlite_rx : entity is "uartlite_rx";
end system_axi_uartlite_0_0_uartlite_rx;
architecture STRUCTURE of system_axi_uartlite_0_0_uartlite_rx is
signal DELAY_16_I_n_1 : STD_LOGIC;
signal DELAY_16_I_n_10 : STD_LOGIC;
signal DELAY_16_I_n_11 : STD_LOGIC;
signal DELAY_16_I_n_12 : STD_LOGIC;
signal RX_D2 : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal fifo_Write : STD_LOGIC;
signal fifo_Write0 : STD_LOGIC;
signal fifo_din : STD_LOGIC_VECTOR ( 1 to 8 );
signal frame_err_ocrd : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_17_out : STD_LOGIC;
signal p_20_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal running_reg_n_0 : STD_LOGIC;
signal rx_1 : STD_LOGIC;
signal rx_2 : STD_LOGIC;
signal rx_3 : STD_LOGIC;
signal rx_4 : STD_LOGIC;
signal rx_5 : STD_LOGIC;
signal rx_6 : STD_LOGIC;
signal rx_7 : STD_LOGIC;
signal rx_8 : STD_LOGIC;
signal rx_9 : STD_LOGIC;
signal start_Edge_Detected : STD_LOGIC;
signal start_Edge_Detected0 : STD_LOGIC;
signal start_Edge_Detected_i_2_n_0 : STD_LOGIC;
signal stop_Bit_Position_reg_n_0 : STD_LOGIC;
signal valid_rx : STD_LOGIC;
signal valid_rx_i_1_n_0 : STD_LOGIC;
begin
SR(0) <= \^sr\(0);
DELAY_16_I: entity work.system_axi_uartlite_0_0_dynshreg_i_f
port map (
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ => DELAY_16_I_n_1,
clr_Status => clr_Status,
en_16x_Baud => en_16x_Baud,
fifo_Write0 => fifo_Write0,
frame_err_ocrd => frame_err_ocrd,
frame_err_ocrd_reg => DELAY_16_I_n_11,
\in\(0 to 7) => fifo_din(1 to 8),
p_11_out => p_11_out,
p_14_out => p_14_out,
p_17_out => p_17_out,
p_20_out => p_20_out,
p_2_out => p_2_out,
p_5_out => p_5_out,
p_8_out => p_8_out,
running_reg => DELAY_16_I_n_12,
running_reg_0 => running_reg_n_0,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
scndry_out => RX_D2,
start_Edge_Detected => start_Edge_Detected,
status_reg(0) => status_reg(1),
status_reg_reg0 => status_reg_reg0,
stop_Bit_Position_reg => DELAY_16_I_n_10,
stop_Bit_Position_reg_0 => stop_Bit_Position_reg_n_0,
valid_rx => valid_rx
);
INPUT_DOUBLE_REGS3: entity work.system_axi_uartlite_0_0_cdc_sync
port map (
EN_16x_Baud_reg => DELAY_16_I_n_1,
\in\(0) => fifo_din(1),
p_26_out => p_26_out,
rx => rx,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
scndry_out => RX_D2,
start_Edge_Detected => start_Edge_Detected
);
Interrupt_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\SERIAL_TO_PARALLEL[1].fifo_din_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_26_out,
Q => fifo_din(1),
R => '0'
);
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_20_out,
Q => fifo_din(2),
R => '0'
);
\SERIAL_TO_PARALLEL[3].fifo_din_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_17_out,
Q => fifo_din(3),
R => '0'
);
\SERIAL_TO_PARALLEL[4].fifo_din_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_14_out,
Q => fifo_din(4),
R => '0'
);
\SERIAL_TO_PARALLEL[5].fifo_din_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_11_out,
Q => fifo_din(5),
R => '0'
);
\SERIAL_TO_PARALLEL[6].fifo_din_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_8_out,
Q => fifo_din(6),
R => '0'
);
\SERIAL_TO_PARALLEL[7].fifo_din_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_5_out,
Q => fifo_din(7),
R => '0'
);
\SERIAL_TO_PARALLEL[8].fifo_din_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_2_out,
Q => fifo_din(8),
R => '0'
);
SRL_FIFO_I: entity work.system_axi_uartlite_0_0_srl_fifo_f_0
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Interrupt0 => Interrupt0,
Q(0) => Q(0),
clr_Status => clr_Status,
enable_interrupts => enable_interrupts,
fifo_Write => fifo_Write,
\in\(0 to 7) => fifo_din(1 to 8),
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO_reg => reset_RX_FIFO_reg,
rx_Data_Present_Pre => rx_Data_Present_Pre,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
status_reg(0) => status_reg(0),
\status_reg_reg[2]\ => \status_reg_reg[2]\,
\status_reg_reg[2]_0\ => \status_reg_reg[2]_0\,
tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
valid_rx => valid_rx
);
fifo_Write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_Write0,
Q => fifo_Write,
R => \^sr\(0)
);
frame_err_ocrd_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => DELAY_16_I_n_11,
Q => frame_err_ocrd,
R => \^sr\(0)
);
running_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => DELAY_16_I_n_12,
Q => running_reg_n_0,
R => \^sr\(0)
);
rx_1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => RX_D2,
Q => rx_1,
R => \^sr\(0)
);
rx_2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_1,
Q => rx_2,
R => \^sr\(0)
);
rx_3_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_2,
Q => rx_3,
R => \^sr\(0)
);
rx_4_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_3,
Q => rx_4,
R => \^sr\(0)
);
rx_5_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_4,
Q => rx_5,
R => \^sr\(0)
);
rx_6_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_5,
Q => rx_6,
R => \^sr\(0)
);
rx_7_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_6,
Q => rx_7,
R => \^sr\(0)
);
rx_8_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_7,
Q => rx_8,
R => \^sr\(0)
);
rx_9_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_8,
Q => rx_9,
R => \^sr\(0)
);
start_Edge_Detected_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => rx_8,
I1 => rx_2,
I2 => start_Edge_Detected_i_2_n_0,
I3 => rx_3,
I4 => rx_1,
I5 => frame_err_ocrd,
O => start_Edge_Detected0
);
start_Edge_Detected_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => rx_5,
I1 => rx_7,
I2 => rx_9,
I3 => running_reg_n_0,
I4 => rx_6,
I5 => rx_4,
O => start_Edge_Detected_i_2_n_0
);
start_Edge_Detected_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => start_Edge_Detected0,
Q => start_Edge_Detected,
R => \^sr\(0)
);
stop_Bit_Position_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => DELAY_16_I_n_10,
Q => stop_Bit_Position_reg_n_0,
R => \^sr\(0)
);
valid_rx_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => start_Edge_Detected,
I1 => fifo_Write,
I2 => valid_rx,
O => valid_rx_i_1_n_0
);
valid_rx_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => valid_rx_i_1_n_0,
Q => valid_rx,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_uartlite_tx is
port (
tx_Buffer_Full : out STD_LOGIC;
tx : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
en_16x_Baud : in STD_LOGIC;
reset_TX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_uartlite_tx : entity is "uartlite_tx";
end system_axi_uartlite_0_0_uartlite_tx;
architecture STRUCTURE of system_axi_uartlite_0_0_uartlite_tx is
signal MID_START_BIT_SRL16_I_n_0 : STD_LOGIC;
signal TX0 : STD_LOGIC;
signal fifo_Read : STD_LOGIC;
signal fifo_Read0 : STD_LOGIC;
signal mux_Out : STD_LOGIC;
signal \mux_sel[0]_i_1_n_0\ : STD_LOGIC;
signal \mux_sel[1]_i_1_n_0\ : STD_LOGIC;
signal \mux_sel[2]_i_1_n_0\ : STD_LOGIC;
signal \mux_sel_reg_n_0_[0]\ : STD_LOGIC;
signal \mux_sel_reg_n_0_[2]\ : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal serial_Data : STD_LOGIC;
signal tx_DataBits : STD_LOGIC;
signal tx_DataBits0 : STD_LOGIC;
signal tx_Data_Enable_reg_n_0 : STD_LOGIC;
signal tx_Start : STD_LOGIC;
signal tx_Start0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \mux_sel[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \mux_sel[1]_i_1\ : label is "soft_lutpair20";
begin
MID_START_BIT_SRL16_I: entity work.\system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\
port map (
en_16x_Baud => en_16x_Baud,
s_axi_aclk => s_axi_aclk,
tx_Data_Enable_reg => MID_START_BIT_SRL16_I_n_0,
tx_Data_Enable_reg_0 => tx_Data_Enable_reg_n_0
);
SRL_FIFO_I: entity work.system_axi_uartlite_0_0_srl_fifo_f
port map (
Bus_RNW_reg => Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q(0) => Q(0),
fifo_Read => fifo_Read,
fifo_wr => fifo_wr,
mux_Out => mux_Out,
\mux_sel_reg[0]\ => \mux_sel_reg_n_0_[0]\,
\mux_sel_reg[2]\ => \mux_sel_reg_n_0_[2]\,
p_4_in => p_4_in,
reset_TX_FIFO_reg => reset_TX_FIFO_reg,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
tx_Buffer_Full => tx_Buffer_Full,
tx_DataBits => tx_DataBits,
tx_Data_Enable_reg => tx_Data_Enable_reg_n_0,
tx_Start => tx_Start,
tx_Start0 => tx_Start0
);
TX_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"31"
)
port map (
I0 => tx_DataBits,
I1 => tx_Start,
I2 => serial_Data,
O => TX0
);
TX_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => TX0,
Q => tx,
S => SR(0)
);
fifo_Read_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => \mux_sel_reg_n_0_[0]\,
I1 => \mux_sel_reg_n_0_[2]\,
I2 => p_4_in,
I3 => tx_Data_Enable_reg_n_0,
O => fifo_Read0
);
fifo_Read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_Read0,
Q => fifo_Read,
R => SR(0)
);
\mux_sel[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1F0F1F0"
)
port map (
I0 => p_4_in,
I1 => \mux_sel_reg_n_0_[2]\,
I2 => \mux_sel_reg_n_0_[0]\,
I3 => tx_Data_Enable_reg_n_0,
I4 => tx_DataBits,
O => \mux_sel[0]_i_1_n_0\
);
\mux_sel[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"99AAABAA"
)
port map (
I0 => p_4_in,
I1 => \mux_sel_reg_n_0_[2]\,
I2 => \mux_sel_reg_n_0_[0]\,
I3 => tx_Data_Enable_reg_n_0,
I4 => tx_DataBits,
O => \mux_sel[1]_i_1_n_0\
);
\mux_sel[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7777888C"
)
port map (
I0 => tx_DataBits,
I1 => tx_Data_Enable_reg_n_0,
I2 => \mux_sel_reg_n_0_[0]\,
I3 => p_4_in,
I4 => \mux_sel_reg_n_0_[2]\,
O => \mux_sel[2]_i_1_n_0\
);
\mux_sel_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \mux_sel[0]_i_1_n_0\,
Q => \mux_sel_reg_n_0_[0]\,
S => SR(0)
);
\mux_sel_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \mux_sel[1]_i_1_n_0\,
Q => p_4_in,
S => SR(0)
);
\mux_sel_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \mux_sel[2]_i_1_n_0\,
Q => \mux_sel_reg_n_0_[2]\,
S => SR(0)
);
serial_Data_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mux_Out,
Q => serial_Data,
R => SR(0)
);
tx_DataBits_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0F08"
)
port map (
I0 => tx_Start,
I1 => tx_Data_Enable_reg_n_0,
I2 => fifo_Read,
I3 => tx_DataBits,
O => tx_DataBits0
);
tx_DataBits_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_DataBits0,
Q => tx_DataBits,
R => SR(0)
);
tx_Data_Enable_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => MID_START_BIT_SRL16_I_n_0,
Q => tx_Data_Enable_reg_n_0,
R => SR(0)
);
tx_Start_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_Start0,
Q => tx_Start,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_uartlite_core is
port (
status_reg : out STD_LOGIC_VECTOR ( 1 downto 0 );
bus2ip_reset : out STD_LOGIC;
rx_Buffer_Full : out STD_LOGIC;
tx_Buffer_Full : out STD_LOGIC;
tx : out STD_LOGIC;
interrupt : out STD_LOGIC;
enable_interrupts : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
FIFO_Full_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset_TX_FIFO : in STD_LOGIC;
reset_RX_FIFO : in STD_LOGIC;
bus2ip_rdce : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
rx : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_uartlite_core : entity is "uartlite_core";
end system_axi_uartlite_0_0_uartlite_core;
architecture STRUCTURE of system_axi_uartlite_0_0_uartlite_core is
signal Interrupt0 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal UARTLITE_RX_I_n_5 : STD_LOGIC;
signal \^bus2ip_reset\ : STD_LOGIC;
signal clr_Status : STD_LOGIC;
signal en_16x_Baud : STD_LOGIC;
signal \^enable_interrupts\ : STD_LOGIC;
signal reset_RX_FIFO_reg_n_0 : STD_LOGIC;
signal reset_TX_FIFO_reg_n_0 : STD_LOGIC;
signal rx_Data_Present_Pre : STD_LOGIC;
signal \^status_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal status_reg_reg0 : STD_LOGIC;
signal tx_Buffer_Empty_Pre : STD_LOGIC;
begin
Q(0) <= \^q\(0);
bus2ip_reset <= \^bus2ip_reset\;
enable_interrupts <= \^enable_interrupts\;
status_reg(1 downto 0) <= \^status_reg\(1 downto 0);
BAUD_RATE_I: entity work.system_axi_uartlite_0_0_baudrate
port map (
SR(0) => \^bus2ip_reset\,
en_16x_Baud => en_16x_Baud,
s_axi_aclk => s_axi_aclk
);
Interrupt_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Interrupt0,
Q => interrupt,
R => \^bus2ip_reset\
);
UARTLITE_RX_I: entity work.system_axi_uartlite_0_0_uartlite_rx
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \^q\(0),
Interrupt0 => Interrupt0,
Q(0) => FIFO_Full_reg(0),
SR(0) => \^bus2ip_reset\,
clr_Status => clr_Status,
en_16x_Baud => en_16x_Baud,
enable_interrupts => \^enable_interrupts\,
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO_reg => reset_RX_FIFO_reg_n_0,
rx => rx,
rx_Data_Present_Pre => rx_Data_Present_Pre,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
status_reg(1 downto 0) => \^status_reg\(1 downto 0),
status_reg_reg0 => status_reg_reg0,
\status_reg_reg[2]\ => rx_Buffer_Full,
\status_reg_reg[2]_0\ => UARTLITE_RX_I_n_5,
tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre
);
UARTLITE_TX_I: entity work.system_axi_uartlite_0_0_uartlite_tx
port map (
Bus_RNW_reg => Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q(0) => \^q\(0),
SR(0) => \^bus2ip_reset\,
en_16x_Baud => en_16x_Baud,
fifo_wr => fifo_wr,
reset_TX_FIFO_reg => reset_TX_FIFO_reg_n_0,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
tx => tx,
tx_Buffer_Full => tx_Buffer_Full
);
clr_Status_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_rdce(0),
Q => clr_Status,
R => \^bus2ip_reset\
);
enable_interrupts_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\,
Q => \^enable_interrupts\,
R => \^bus2ip_reset\
);
reset_RX_FIFO_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => reset_RX_FIFO,
Q => reset_RX_FIFO_reg_n_0,
S => \^bus2ip_reset\
);
reset_TX_FIFO_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => reset_TX_FIFO,
Q => reset_TX_FIFO_reg_n_0,
S => \^bus2ip_reset\
);
rx_Data_Present_Pre_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
Q => rx_Data_Present_Pre,
R => '0'
);
\status_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => status_reg_reg0,
Q => \^status_reg\(1),
R => '0'
);
\status_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => UARTLITE_RX_I_n_5,
Q => \^status_reg\(0),
R => '0'
);
tx_Buffer_Empty_Pre_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.cnt_i_reg[4]\,
Q => tx_Buffer_Empty_Pre,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_axi_uartlite is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
attribute C_BAUDRATE : integer;
attribute C_BAUDRATE of system_axi_uartlite_0_0_axi_uartlite : entity is 9600;
attribute C_DATA_BITS : integer;
attribute C_DATA_BITS of system_axi_uartlite_0_0_axi_uartlite : entity is 8;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_uartlite_0_0_axi_uartlite : entity is "artix7";
attribute C_ODD_PARITY : integer;
attribute C_ODD_PARITY of system_axi_uartlite_0_0_axi_uartlite : entity is 0;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of system_axi_uartlite_0_0_axi_uartlite : entity is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_uartlite_0_0_axi_uartlite : entity is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_uartlite_0_0_axi_uartlite : entity is 32;
attribute C_USE_PARITY : integer;
attribute C_USE_PARITY of system_axi_uartlite_0_0_axi_uartlite : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_axi_uartlite : entity is "axi_uartlite";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_uartlite_0_0_axi_uartlite : entity is "yes";
end system_axi_uartlite_0_0_axi_uartlite;
architecture STRUCTURE of system_axi_uartlite_0_0_axi_uartlite is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_9 : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \UARTLITE_RX_I/rx_Data_Empty\ : STD_LOGIC;
signal \UARTLITE_TX_I/fifo_wr\ : STD_LOGIC;
signal bus2ip_rdce : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal enable_interrupts : STD_LOGIC;
signal reset_RX_FIFO : STD_LOGIC;
signal reset_TX_FIFO : STD_LOGIC;
signal rx_Buffer_Full : STD_LOGIC;
signal rx_Data : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal status_reg : STD_LOGIC_VECTOR ( 1 to 2 );
signal tx_Buffer_Empty : STD_LOGIC;
signal tx_Buffer_Full : STD_LOGIC;
begin
s_axi_awready <= \^s_axi_awready\;
s_axi_bresp(1) <= \^s_axi_bresp\(1);
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \^s_axi_rresp\(1);
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_awready\;
AXI_LITE_IPIF_I: entity work.system_axi_uartlite_0_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
FIFO_Full_reg => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\INFERRED_GEN.cnt_i_reg[2]\ => AXI_LITE_IPIF_I_n_8,
\INFERRED_GEN.cnt_i_reg[2]_0\ => AXI_LITE_IPIF_I_n_9,
\INFERRED_GEN.cnt_i_reg[4]\(0) => tx_Buffer_Empty,
Q(0) => \UARTLITE_RX_I/rx_Data_Empty\,
bus2ip_rdce(0) => bus2ip_rdce(1),
bus2ip_reset => bus2ip_reset,
enable_interrupts => enable_interrupts,
enable_interrupts_reg => AXI_LITE_IPIF_I_n_16,
fifo_wr => \UARTLITE_TX_I/fifo_wr\,
\out\(7) => rx_Data(0),
\out\(6) => rx_Data(1),
\out\(5) => rx_Data(2),
\out\(4) => rx_Data(3),
\out\(3) => rx_Data(4),
\out\(2) => rx_Data(5),
\out\(1) => rx_Data(6),
\out\(0) => rx_Data(7),
reset_RX_FIFO => reset_RX_FIFO,
reset_TX_FIFO => reset_TX_FIFO,
rx_Buffer_Full => rx_Buffer_Full,
rx_Data_Present_Pre_reg => AXI_LITE_IPIF_I_n_18,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(1),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => \^s_axi_rresp\(1),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(2) => s_axi_wdata(4),
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0),
s_axi_wvalid => s_axi_wvalid,
status_reg(1) => status_reg(1),
status_reg(0) => status_reg(2),
tx_Buffer_Empty_Pre_reg => AXI_LITE_IPIF_I_n_17,
tx_Buffer_Full => tx_Buffer_Full
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
UARTLITE_CORE_I: entity work.system_axi_uartlite_0_0_uartlite_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_9,
FIFO_Full_reg(0) => \UARTLITE_RX_I/rx_Data_Empty\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_18,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI_LITE_IPIF_I_n_8,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ => AXI_LITE_IPIF_I_n_16,
\INFERRED_GEN.cnt_i_reg[4]\ => AXI_LITE_IPIF_I_n_17,
Q(0) => tx_Buffer_Empty,
bus2ip_rdce(0) => bus2ip_rdce(1),
bus2ip_reset => bus2ip_reset,
enable_interrupts => enable_interrupts,
fifo_wr => \UARTLITE_TX_I/fifo_wr\,
interrupt => interrupt,
\out\(7) => rx_Data(0),
\out\(6) => rx_Data(1),
\out\(5) => rx_Data(2),
\out\(4) => rx_Data(3),
\out\(3) => rx_Data(4),
\out\(2) => rx_Data(5),
\out\(1) => rx_Data(6),
\out\(0) => rx_Data(7),
reset_RX_FIFO => reset_RX_FIFO,
reset_TX_FIFO => reset_TX_FIFO,
rx => rx,
rx_Buffer_Full => rx_Buffer_Full,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
status_reg(1) => status_reg(1),
status_reg(0) => status_reg(2),
tx => tx,
tx_Buffer_Full => tx_Buffer_Full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_uartlite_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_uartlite_0_0 : entity is "system_axi_uartlite_0_0,axi_uartlite,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_uartlite_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_uartlite_0_0 : entity is "axi_uartlite,Vivado 2016.4";
end system_axi_uartlite_0_0;
architecture STRUCTURE of system_axi_uartlite_0_0 is
attribute C_BAUDRATE : integer;
attribute C_BAUDRATE of U0 : label is 9600;
attribute C_DATA_BITS : integer;
attribute C_DATA_BITS of U0 : label is 8;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_ODD_PARITY : integer;
attribute C_ODD_PARITY of U0 : label is 0;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of U0 : label is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_USE_PARITY : integer;
attribute C_USE_PARITY of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_axi_uartlite_0_0_axi_uartlite
port map (
interrupt => interrupt,
rx => rx,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(3 downto 0) => s_axi_araddr(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(3 downto 0) => s_axi_awaddr(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
tx => tx
);
end STRUCTURE;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_0/system_microblaze_0_0_stub.vhdl
|
1
|
8989
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:30 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_0/system_microblaze_0_0_stub.vhdl
-- Design : system_microblaze_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_microblaze_0_0 is
Port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
Dbg_Disable : in STD_LOGIC;
M_AXI_IC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_AWLOCK : out STD_LOGIC;
M_AXI_IC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWVALID : out STD_LOGIC;
M_AXI_IC_AWREADY : in STD_LOGIC;
M_AXI_IC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_WLAST : out STD_LOGIC;
M_AXI_IC_WVALID : out STD_LOGIC;
M_AXI_IC_WREADY : in STD_LOGIC;
M_AXI_IC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_BVALID : in STD_LOGIC;
M_AXI_IC_BREADY : out STD_LOGIC;
M_AXI_IC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_ARLOCK : out STD_LOGIC;
M_AXI_IC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARVALID : out STD_LOGIC;
M_AXI_IC_ARREADY : in STD_LOGIC;
M_AXI_IC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_RLAST : in STD_LOGIC;
M_AXI_IC_RVALID : in STD_LOGIC;
M_AXI_IC_RREADY : out STD_LOGIC;
M_AXI_DC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_AWLOCK : out STD_LOGIC;
M_AXI_DC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWVALID : out STD_LOGIC;
M_AXI_DC_AWREADY : in STD_LOGIC;
M_AXI_DC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_WLAST : out STD_LOGIC;
M_AXI_DC_WVALID : out STD_LOGIC;
M_AXI_DC_WREADY : in STD_LOGIC;
M_AXI_DC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_BVALID : in STD_LOGIC;
M_AXI_DC_BREADY : out STD_LOGIC;
M_AXI_DC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_ARLOCK : out STD_LOGIC;
M_AXI_DC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARVALID : out STD_LOGIC;
M_AXI_DC_ARREADY : in STD_LOGIC;
M_AXI_DC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_RLAST : in STD_LOGIC;
M_AXI_DC_RVALID : in STD_LOGIC;
M_AXI_DC_RREADY : out STD_LOGIC
);
end system_microblaze_0_0;
architecture stub of system_microblaze_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Clk,Reset,Interrupt,Interrupt_Address[0:31],Interrupt_Ack[0:1],Instr_Addr[0:31],Instr[0:31],IFetch,I_AS,IReady,IWAIT,ICE,IUE,Data_Addr[0:31],Data_Read[0:31],Data_Write[0:31],D_AS,Read_Strobe,Write_Strobe,DReady,DWait,DCE,DUE,Byte_Enable[0:3],M_AXI_DP_AWADDR[31:0],M_AXI_DP_AWPROT[2:0],M_AXI_DP_AWVALID,M_AXI_DP_AWREADY,M_AXI_DP_WDATA[31:0],M_AXI_DP_WSTRB[3:0],M_AXI_DP_WVALID,M_AXI_DP_WREADY,M_AXI_DP_BRESP[1:0],M_AXI_DP_BVALID,M_AXI_DP_BREADY,M_AXI_DP_ARADDR[31:0],M_AXI_DP_ARPROT[2:0],M_AXI_DP_ARVALID,M_AXI_DP_ARREADY,M_AXI_DP_RDATA[31:0],M_AXI_DP_RRESP[1:0],M_AXI_DP_RVALID,M_AXI_DP_RREADY,Dbg_Clk,Dbg_TDI,Dbg_TDO,Dbg_Reg_En[0:7],Dbg_Shift,Dbg_Capture,Dbg_Update,Debug_Rst,Dbg_Disable,M_AXI_IC_AWID[0:0],M_AXI_IC_AWADDR[31:0],M_AXI_IC_AWLEN[7:0],M_AXI_IC_AWSIZE[2:0],M_AXI_IC_AWBURST[1:0],M_AXI_IC_AWLOCK,M_AXI_IC_AWCACHE[3:0],M_AXI_IC_AWPROT[2:0],M_AXI_IC_AWQOS[3:0],M_AXI_IC_AWVALID,M_AXI_IC_AWREADY,M_AXI_IC_WDATA[31:0],M_AXI_IC_WSTRB[3:0],M_AXI_IC_WLAST,M_AXI_IC_WVALID,M_AXI_IC_WREADY,M_AXI_IC_BID[0:0],M_AXI_IC_BRESP[1:0],M_AXI_IC_BVALID,M_AXI_IC_BREADY,M_AXI_IC_ARID[0:0],M_AXI_IC_ARADDR[31:0],M_AXI_IC_ARLEN[7:0],M_AXI_IC_ARSIZE[2:0],M_AXI_IC_ARBURST[1:0],M_AXI_IC_ARLOCK,M_AXI_IC_ARCACHE[3:0],M_AXI_IC_ARPROT[2:0],M_AXI_IC_ARQOS[3:0],M_AXI_IC_ARVALID,M_AXI_IC_ARREADY,M_AXI_IC_RID[0:0],M_AXI_IC_RDATA[31:0],M_AXI_IC_RRESP[1:0],M_AXI_IC_RLAST,M_AXI_IC_RVALID,M_AXI_IC_RREADY,M_AXI_DC_AWID[0:0],M_AXI_DC_AWADDR[31:0],M_AXI_DC_AWLEN[7:0],M_AXI_DC_AWSIZE[2:0],M_AXI_DC_AWBURST[1:0],M_AXI_DC_AWLOCK,M_AXI_DC_AWCACHE[3:0],M_AXI_DC_AWPROT[2:0],M_AXI_DC_AWQOS[3:0],M_AXI_DC_AWVALID,M_AXI_DC_AWREADY,M_AXI_DC_WDATA[31:0],M_AXI_DC_WSTRB[3:0],M_AXI_DC_WLAST,M_AXI_DC_WVALID,M_AXI_DC_WREADY,M_AXI_DC_BRESP[1:0],M_AXI_DC_BID[0:0],M_AXI_DC_BVALID,M_AXI_DC_BREADY,M_AXI_DC_ARID[0:0],M_AXI_DC_ARADDR[31:0],M_AXI_DC_ARLEN[7:0],M_AXI_DC_ARSIZE[2:0],M_AXI_DC_ARBURST[1:0],M_AXI_DC_ARLOCK,M_AXI_DC_ARCACHE[3:0],M_AXI_DC_ARPROT[2:0],M_AXI_DC_ARQOS[3:0],M_AXI_DC_ARVALID,M_AXI_DC_ARREADY,M_AXI_DC_RID[0:0],M_AXI_DC_RDATA[31:0],M_AXI_DC_RRESP[1:0],M_AXI_DC_RLAST,M_AXI_DC_RVALID,M_AXI_DC_RREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "MicroBlaze,Vivado 2016.4";
begin
end;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/hdl/system_wrapper.vhd
|
1
|
50648
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Mar 20 20:54:09 2017
--Host : N73-PC running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_cas_n : out STD_LOGIC;
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
Vaux0_v_n : in STD_LOGIC;
Vaux0_v_p : in STD_LOGIC;
Vaux10_v_n : in STD_LOGIC;
Vaux10_v_p : in STD_LOGIC;
Vaux12_v_n : in STD_LOGIC;
Vaux12_v_p : in STD_LOGIC;
Vaux13_v_n : in STD_LOGIC;
Vaux13_v_p : in STD_LOGIC;
Vaux14_v_n : in STD_LOGIC;
Vaux14_v_p : in STD_LOGIC;
Vaux15_v_n : in STD_LOGIC;
Vaux15_v_p : in STD_LOGIC;
Vaux1_v_n : in STD_LOGIC;
Vaux1_v_p : in STD_LOGIC;
Vaux2_v_n : in STD_LOGIC;
Vaux2_v_p : in STD_LOGIC;
Vaux4_v_n : in STD_LOGIC;
Vaux4_v_p : in STD_LOGIC;
Vaux5_v_n : in STD_LOGIC;
Vaux5_v_p : in STD_LOGIC;
Vaux6_v_n : in STD_LOGIC;
Vaux6_v_p : in STD_LOGIC;
Vaux7_v_n : in STD_LOGIC;
Vaux7_v_p : in STD_LOGIC;
Vaux9_v_n : in STD_LOGIC;
Vaux9_v_p : in STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC;
dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_io : inout STD_LOGIC;
eth_mii_col : in STD_LOGIC;
eth_mii_crs : in STD_LOGIC;
eth_mii_rst_n : out STD_LOGIC;
eth_mii_rx_clk : in STD_LOGIC;
eth_mii_rx_dv : in STD_LOGIC;
eth_mii_rx_er : in STD_LOGIC;
eth_mii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mii_tx_clk : in STD_LOGIC;
eth_mii_tx_en : out STD_LOGIC;
eth_mii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 );
eth_ref_clk : out STD_LOGIC;
i2c_pullups_tri_io : inout STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_scl_io : inout STD_LOGIC;
i2c_sda_io : inout STD_LOGIC;
led_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 );
push_buttons_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
qspi_flash_io0_io : inout STD_LOGIC;
qspi_flash_io1_io : inout STD_LOGIC;
qspi_flash_io2_io : inout STD_LOGIC;
qspi_flash_io3_io : inout STD_LOGIC;
qspi_flash_sck_io : inout STD_LOGIC;
qspi_flash_ss_io : inout STD_LOGIC;
reset : in STD_LOGIC;
rgb_led_tri_io : inout STD_LOGIC_VECTOR ( 11 downto 0 );
shield_dp0_dp19_tri_io : inout STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp26_dp41_tri_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
spi_io0_io : inout STD_LOGIC;
spi_io1_io : inout STD_LOGIC;
spi_sck_io : inout STD_LOGIC;
spi_ss_io : inout STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_cas_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
Vaux0_v_n : in STD_LOGIC;
Vaux0_v_p : in STD_LOGIC;
Vaux1_v_n : in STD_LOGIC;
Vaux1_v_p : in STD_LOGIC;
Vaux2_v_n : in STD_LOGIC;
Vaux2_v_p : in STD_LOGIC;
Vaux4_v_n : in STD_LOGIC;
Vaux4_v_p : in STD_LOGIC;
Vaux5_v_n : in STD_LOGIC;
Vaux5_v_p : in STD_LOGIC;
Vaux6_v_n : in STD_LOGIC;
Vaux6_v_p : in STD_LOGIC;
Vaux7_v_n : in STD_LOGIC;
Vaux7_v_p : in STD_LOGIC;
Vaux9_v_n : in STD_LOGIC;
Vaux9_v_p : in STD_LOGIC;
Vaux10_v_n : in STD_LOGIC;
Vaux10_v_p : in STD_LOGIC;
Vaux12_v_n : in STD_LOGIC;
Vaux12_v_p : in STD_LOGIC;
Vaux13_v_n : in STD_LOGIC;
Vaux13_v_p : in STD_LOGIC;
Vaux14_v_n : in STD_LOGIC;
Vaux14_v_p : in STD_LOGIC;
Vaux15_v_n : in STD_LOGIC;
Vaux15_v_p : in STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC;
dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
eth_mii_col : in STD_LOGIC;
eth_mii_crs : in STD_LOGIC;
eth_mii_rst_n : out STD_LOGIC;
eth_mii_rx_clk : in STD_LOGIC;
eth_mii_rx_dv : in STD_LOGIC;
eth_mii_rx_er : in STD_LOGIC;
eth_mii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mii_tx_clk : in STD_LOGIC;
eth_mii_tx_en : out STD_LOGIC;
eth_mii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 );
i2c_scl_i : in STD_LOGIC;
i2c_scl_o : out STD_LOGIC;
i2c_scl_t : out STD_LOGIC;
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC;
i2c_sda_t : out STD_LOGIC;
i2c_pullups_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_pullups_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_pullups_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
led_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
led_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
push_buttons_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
qspi_flash_io0_i : in STD_LOGIC;
qspi_flash_io0_o : out STD_LOGIC;
qspi_flash_io0_t : out STD_LOGIC;
qspi_flash_io1_i : in STD_LOGIC;
qspi_flash_io1_o : out STD_LOGIC;
qspi_flash_io1_t : out STD_LOGIC;
qspi_flash_io2_i : in STD_LOGIC;
qspi_flash_io2_o : out STD_LOGIC;
qspi_flash_io2_t : out STD_LOGIC;
qspi_flash_io3_i : in STD_LOGIC;
qspi_flash_io3_o : out STD_LOGIC;
qspi_flash_io3_t : out STD_LOGIC;
qspi_flash_sck_i : in STD_LOGIC;
qspi_flash_sck_o : out STD_LOGIC;
qspi_flash_sck_t : out STD_LOGIC;
qspi_flash_ss_i : in STD_LOGIC;
qspi_flash_ss_o : out STD_LOGIC;
qspi_flash_ss_t : out STD_LOGIC;
rgb_led_tri_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
rgb_led_tri_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
rgb_led_tri_t : out STD_LOGIC_VECTOR ( 11 downto 0 );
shield_dp0_dp19_tri_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp0_dp19_tri_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp0_dp19_tri_t : out STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp26_dp41_tri_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
shield_dp26_dp41_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
shield_dp26_dp41_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
spi_io0_i : in STD_LOGIC;
spi_io0_o : out STD_LOGIC;
spi_io0_t : out STD_LOGIC;
spi_io1_i : in STD_LOGIC;
spi_io1_o : out STD_LOGIC;
spi_io1_t : out STD_LOGIC;
spi_sck_i : in STD_LOGIC;
spi_sck_o : out STD_LOGIC;
spi_sck_t : out STD_LOGIC;
spi_ss_i : in STD_LOGIC;
spi_ss_o : out STD_LOGIC;
spi_ss_t : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC
);
end component system;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal eth_mdio_mdc_mdio_i : STD_LOGIC;
signal eth_mdio_mdc_mdio_o : STD_LOGIC;
signal eth_mdio_mdc_mdio_t : STD_LOGIC;
signal i2c_pullups_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_pullups_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal i2c_pullups_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_pullups_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal i2c_pullups_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_pullups_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal i2c_pullups_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_pullups_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal i2c_scl_i : STD_LOGIC;
signal i2c_scl_o : STD_LOGIC;
signal i2c_scl_t : STD_LOGIC;
signal i2c_sda_i : STD_LOGIC;
signal i2c_sda_o : STD_LOGIC;
signal i2c_sda_t : STD_LOGIC;
signal led_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal led_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal led_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal led_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal led_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal led_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal led_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal led_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal led_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal led_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal led_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal led_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal led_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal led_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal led_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal led_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal qspi_flash_io0_i : STD_LOGIC;
signal qspi_flash_io0_o : STD_LOGIC;
signal qspi_flash_io0_t : STD_LOGIC;
signal qspi_flash_io1_i : STD_LOGIC;
signal qspi_flash_io1_o : STD_LOGIC;
signal qspi_flash_io1_t : STD_LOGIC;
signal qspi_flash_io2_i : STD_LOGIC;
signal qspi_flash_io2_o : STD_LOGIC;
signal qspi_flash_io2_t : STD_LOGIC;
signal qspi_flash_io3_i : STD_LOGIC;
signal qspi_flash_io3_o : STD_LOGIC;
signal qspi_flash_io3_t : STD_LOGIC;
signal qspi_flash_sck_i : STD_LOGIC;
signal qspi_flash_sck_o : STD_LOGIC;
signal qspi_flash_sck_t : STD_LOGIC;
signal qspi_flash_ss_i : STD_LOGIC;
signal qspi_flash_ss_o : STD_LOGIC;
signal qspi_flash_ss_t : STD_LOGIC;
signal rgb_led_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal rgb_led_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal rgb_led_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal rgb_led_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal rgb_led_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal rgb_led_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal rgb_led_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal rgb_led_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal rgb_led_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal rgb_led_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal rgb_led_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal rgb_led_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal rgb_led_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal rgb_led_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal rgb_led_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal rgb_led_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal rgb_led_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal rgb_led_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal rgb_led_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal rgb_led_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal rgb_led_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal rgb_led_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal rgb_led_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal rgb_led_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp0_dp19_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp0_dp19_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp0_dp19_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp0_dp19_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp0_dp19_tri_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp0_dp19_tri_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp0_dp19_tri_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp0_dp19_tri_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp0_dp19_tri_i_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal shield_dp0_dp19_tri_i_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal shield_dp0_dp19_tri_i_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal shield_dp0_dp19_tri_i_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal shield_dp0_dp19_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp0_dp19_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp0_dp19_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp0_dp19_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp0_dp19_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp0_dp19_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp0_dp19_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp0_dp19_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp0_dp19_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp0_dp19_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp0_dp19_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp0_dp19_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp0_dp19_tri_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp0_dp19_tri_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp0_dp19_tri_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp0_dp19_tri_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp0_dp19_tri_io_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal shield_dp0_dp19_tri_io_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal shield_dp0_dp19_tri_io_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal shield_dp0_dp19_tri_io_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal shield_dp0_dp19_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp0_dp19_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp0_dp19_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp0_dp19_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp0_dp19_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp0_dp19_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp0_dp19_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp0_dp19_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp0_dp19_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp0_dp19_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp0_dp19_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp0_dp19_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp0_dp19_tri_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp0_dp19_tri_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp0_dp19_tri_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp0_dp19_tri_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp0_dp19_tri_o_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal shield_dp0_dp19_tri_o_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal shield_dp0_dp19_tri_o_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal shield_dp0_dp19_tri_o_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal shield_dp0_dp19_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp0_dp19_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp0_dp19_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp0_dp19_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp0_dp19_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp0_dp19_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp0_dp19_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp0_dp19_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp0_dp19_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp0_dp19_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp0_dp19_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp0_dp19_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp0_dp19_tri_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp0_dp19_tri_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp0_dp19_tri_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp0_dp19_tri_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp0_dp19_tri_t_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal shield_dp0_dp19_tri_t_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal shield_dp0_dp19_tri_t_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal shield_dp0_dp19_tri_t_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal shield_dp0_dp19_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp0_dp19_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp0_dp19_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp0_dp19_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp0_dp19_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp0_dp19_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp0_dp19_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp0_dp19_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp26_dp41_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp26_dp41_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp26_dp41_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp26_dp41_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp26_dp41_tri_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp26_dp41_tri_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp26_dp41_tri_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp26_dp41_tri_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp26_dp41_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp26_dp41_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp26_dp41_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp26_dp41_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp26_dp41_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp26_dp41_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp26_dp41_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp26_dp41_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp26_dp41_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp26_dp41_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp26_dp41_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp26_dp41_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp26_dp41_tri_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp26_dp41_tri_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp26_dp41_tri_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp26_dp41_tri_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp26_dp41_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp26_dp41_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp26_dp41_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp26_dp41_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp26_dp41_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp26_dp41_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp26_dp41_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp26_dp41_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp26_dp41_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp26_dp41_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp26_dp41_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp26_dp41_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp26_dp41_tri_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp26_dp41_tri_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp26_dp41_tri_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp26_dp41_tri_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp26_dp41_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp26_dp41_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp26_dp41_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp26_dp41_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp26_dp41_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp26_dp41_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp26_dp41_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp26_dp41_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp26_dp41_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp26_dp41_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp26_dp41_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp26_dp41_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp26_dp41_tri_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp26_dp41_tri_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp26_dp41_tri_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp26_dp41_tri_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp26_dp41_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp26_dp41_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp26_dp41_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp26_dp41_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp26_dp41_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp26_dp41_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp26_dp41_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp26_dp41_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal spi_io0_i : STD_LOGIC;
signal spi_io0_o : STD_LOGIC;
signal spi_io0_t : STD_LOGIC;
signal spi_io1_i : STD_LOGIC;
signal spi_io1_o : STD_LOGIC;
signal spi_io1_t : STD_LOGIC;
signal spi_sck_i : STD_LOGIC;
signal spi_sck_o : STD_LOGIC;
signal spi_sck_t : STD_LOGIC;
signal spi_ss_i : STD_LOGIC;
signal spi_ss_o : STD_LOGIC;
signal spi_ss_t : STD_LOGIC;
begin
eth_mdio_mdc_mdio_iobuf: component IOBUF
port map (
I => eth_mdio_mdc_mdio_o,
IO => eth_mdio_mdc_mdio_io,
O => eth_mdio_mdc_mdio_i,
T => eth_mdio_mdc_mdio_t
);
i2c_pullups_tri_iobuf_0: component IOBUF
port map (
I => i2c_pullups_tri_o_0(0),
IO => i2c_pullups_tri_io(0),
O => i2c_pullups_tri_i_0(0),
T => i2c_pullups_tri_t_0(0)
);
i2c_pullups_tri_iobuf_1: component IOBUF
port map (
I => i2c_pullups_tri_o_1(1),
IO => i2c_pullups_tri_io(1),
O => i2c_pullups_tri_i_1(1),
T => i2c_pullups_tri_t_1(1)
);
i2c_scl_iobuf: component IOBUF
port map (
I => i2c_scl_o,
IO => i2c_scl_io,
O => i2c_scl_i,
T => i2c_scl_t
);
i2c_sda_iobuf: component IOBUF
port map (
I => i2c_sda_o,
IO => i2c_sda_io,
O => i2c_sda_i,
T => i2c_sda_t
);
led_4bits_tri_iobuf_0: component IOBUF
port map (
I => led_4bits_tri_o_0(0),
IO => led_4bits_tri_io(0),
O => led_4bits_tri_i_0(0),
T => led_4bits_tri_t_0(0)
);
led_4bits_tri_iobuf_1: component IOBUF
port map (
I => led_4bits_tri_o_1(1),
IO => led_4bits_tri_io(1),
O => led_4bits_tri_i_1(1),
T => led_4bits_tri_t_1(1)
);
led_4bits_tri_iobuf_2: component IOBUF
port map (
I => led_4bits_tri_o_2(2),
IO => led_4bits_tri_io(2),
O => led_4bits_tri_i_2(2),
T => led_4bits_tri_t_2(2)
);
led_4bits_tri_iobuf_3: component IOBUF
port map (
I => led_4bits_tri_o_3(3),
IO => led_4bits_tri_io(3),
O => led_4bits_tri_i_3(3),
T => led_4bits_tri_t_3(3)
);
qspi_flash_io0_iobuf: component IOBUF
port map (
I => qspi_flash_io0_o,
IO => qspi_flash_io0_io,
O => qspi_flash_io0_i,
T => qspi_flash_io0_t
);
qspi_flash_io1_iobuf: component IOBUF
port map (
I => qspi_flash_io1_o,
IO => qspi_flash_io1_io,
O => qspi_flash_io1_i,
T => qspi_flash_io1_t
);
qspi_flash_io2_iobuf: component IOBUF
port map (
I => qspi_flash_io2_o,
IO => qspi_flash_io2_io,
O => qspi_flash_io2_i,
T => qspi_flash_io2_t
);
qspi_flash_io3_iobuf: component IOBUF
port map (
I => qspi_flash_io3_o,
IO => qspi_flash_io3_io,
O => qspi_flash_io3_i,
T => qspi_flash_io3_t
);
qspi_flash_sck_iobuf: component IOBUF
port map (
I => qspi_flash_sck_o,
IO => qspi_flash_sck_io,
O => qspi_flash_sck_i,
T => qspi_flash_sck_t
);
qspi_flash_ss_iobuf: component IOBUF
port map (
I => qspi_flash_ss_o,
IO => qspi_flash_ss_io,
O => qspi_flash_ss_i,
T => qspi_flash_ss_t
);
rgb_led_tri_iobuf_0: component IOBUF
port map (
I => rgb_led_tri_o_0(0),
IO => rgb_led_tri_io(0),
O => rgb_led_tri_i_0(0),
T => rgb_led_tri_t_0(0)
);
rgb_led_tri_iobuf_1: component IOBUF
port map (
I => rgb_led_tri_o_1(1),
IO => rgb_led_tri_io(1),
O => rgb_led_tri_i_1(1),
T => rgb_led_tri_t_1(1)
);
rgb_led_tri_iobuf_10: component IOBUF
port map (
I => rgb_led_tri_o_10(10),
IO => rgb_led_tri_io(10),
O => rgb_led_tri_i_10(10),
T => rgb_led_tri_t_10(10)
);
rgb_led_tri_iobuf_11: component IOBUF
port map (
I => rgb_led_tri_o_11(11),
IO => rgb_led_tri_io(11),
O => rgb_led_tri_i_11(11),
T => rgb_led_tri_t_11(11)
);
rgb_led_tri_iobuf_2: component IOBUF
port map (
I => rgb_led_tri_o_2(2),
IO => rgb_led_tri_io(2),
O => rgb_led_tri_i_2(2),
T => rgb_led_tri_t_2(2)
);
rgb_led_tri_iobuf_3: component IOBUF
port map (
I => rgb_led_tri_o_3(3),
IO => rgb_led_tri_io(3),
O => rgb_led_tri_i_3(3),
T => rgb_led_tri_t_3(3)
);
rgb_led_tri_iobuf_4: component IOBUF
port map (
I => rgb_led_tri_o_4(4),
IO => rgb_led_tri_io(4),
O => rgb_led_tri_i_4(4),
T => rgb_led_tri_t_4(4)
);
rgb_led_tri_iobuf_5: component IOBUF
port map (
I => rgb_led_tri_o_5(5),
IO => rgb_led_tri_io(5),
O => rgb_led_tri_i_5(5),
T => rgb_led_tri_t_5(5)
);
rgb_led_tri_iobuf_6: component IOBUF
port map (
I => rgb_led_tri_o_6(6),
IO => rgb_led_tri_io(6),
O => rgb_led_tri_i_6(6),
T => rgb_led_tri_t_6(6)
);
rgb_led_tri_iobuf_7: component IOBUF
port map (
I => rgb_led_tri_o_7(7),
IO => rgb_led_tri_io(7),
O => rgb_led_tri_i_7(7),
T => rgb_led_tri_t_7(7)
);
rgb_led_tri_iobuf_8: component IOBUF
port map (
I => rgb_led_tri_o_8(8),
IO => rgb_led_tri_io(8),
O => rgb_led_tri_i_8(8),
T => rgb_led_tri_t_8(8)
);
rgb_led_tri_iobuf_9: component IOBUF
port map (
I => rgb_led_tri_o_9(9),
IO => rgb_led_tri_io(9),
O => rgb_led_tri_i_9(9),
T => rgb_led_tri_t_9(9)
);
shield_dp0_dp19_tri_iobuf_0: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_0(0),
IO => shield_dp0_dp19_tri_io(0),
O => shield_dp0_dp19_tri_i_0(0),
T => shield_dp0_dp19_tri_t_0(0)
);
shield_dp0_dp19_tri_iobuf_1: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_1(1),
IO => shield_dp0_dp19_tri_io(1),
O => shield_dp0_dp19_tri_i_1(1),
T => shield_dp0_dp19_tri_t_1(1)
);
shield_dp0_dp19_tri_iobuf_10: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_10(10),
IO => shield_dp0_dp19_tri_io(10),
O => shield_dp0_dp19_tri_i_10(10),
T => shield_dp0_dp19_tri_t_10(10)
);
shield_dp0_dp19_tri_iobuf_11: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_11(11),
IO => shield_dp0_dp19_tri_io(11),
O => shield_dp0_dp19_tri_i_11(11),
T => shield_dp0_dp19_tri_t_11(11)
);
shield_dp0_dp19_tri_iobuf_12: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_12(12),
IO => shield_dp0_dp19_tri_io(12),
O => shield_dp0_dp19_tri_i_12(12),
T => shield_dp0_dp19_tri_t_12(12)
);
shield_dp0_dp19_tri_iobuf_13: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_13(13),
IO => shield_dp0_dp19_tri_io(13),
O => shield_dp0_dp19_tri_i_13(13),
T => shield_dp0_dp19_tri_t_13(13)
);
shield_dp0_dp19_tri_iobuf_14: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_14(14),
IO => shield_dp0_dp19_tri_io(14),
O => shield_dp0_dp19_tri_i_14(14),
T => shield_dp0_dp19_tri_t_14(14)
);
shield_dp0_dp19_tri_iobuf_15: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_15(15),
IO => shield_dp0_dp19_tri_io(15),
O => shield_dp0_dp19_tri_i_15(15),
T => shield_dp0_dp19_tri_t_15(15)
);
shield_dp0_dp19_tri_iobuf_16: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_16(16),
IO => shield_dp0_dp19_tri_io(16),
O => shield_dp0_dp19_tri_i_16(16),
T => shield_dp0_dp19_tri_t_16(16)
);
shield_dp0_dp19_tri_iobuf_17: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_17(17),
IO => shield_dp0_dp19_tri_io(17),
O => shield_dp0_dp19_tri_i_17(17),
T => shield_dp0_dp19_tri_t_17(17)
);
shield_dp0_dp19_tri_iobuf_18: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_18(18),
IO => shield_dp0_dp19_tri_io(18),
O => shield_dp0_dp19_tri_i_18(18),
T => shield_dp0_dp19_tri_t_18(18)
);
shield_dp0_dp19_tri_iobuf_19: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_19(19),
IO => shield_dp0_dp19_tri_io(19),
O => shield_dp0_dp19_tri_i_19(19),
T => shield_dp0_dp19_tri_t_19(19)
);
shield_dp0_dp19_tri_iobuf_2: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_2(2),
IO => shield_dp0_dp19_tri_io(2),
O => shield_dp0_dp19_tri_i_2(2),
T => shield_dp0_dp19_tri_t_2(2)
);
shield_dp0_dp19_tri_iobuf_3: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_3(3),
IO => shield_dp0_dp19_tri_io(3),
O => shield_dp0_dp19_tri_i_3(3),
T => shield_dp0_dp19_tri_t_3(3)
);
shield_dp0_dp19_tri_iobuf_4: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_4(4),
IO => shield_dp0_dp19_tri_io(4),
O => shield_dp0_dp19_tri_i_4(4),
T => shield_dp0_dp19_tri_t_4(4)
);
shield_dp0_dp19_tri_iobuf_5: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_5(5),
IO => shield_dp0_dp19_tri_io(5),
O => shield_dp0_dp19_tri_i_5(5),
T => shield_dp0_dp19_tri_t_5(5)
);
shield_dp0_dp19_tri_iobuf_6: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_6(6),
IO => shield_dp0_dp19_tri_io(6),
O => shield_dp0_dp19_tri_i_6(6),
T => shield_dp0_dp19_tri_t_6(6)
);
shield_dp0_dp19_tri_iobuf_7: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_7(7),
IO => shield_dp0_dp19_tri_io(7),
O => shield_dp0_dp19_tri_i_7(7),
T => shield_dp0_dp19_tri_t_7(7)
);
shield_dp0_dp19_tri_iobuf_8: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_8(8),
IO => shield_dp0_dp19_tri_io(8),
O => shield_dp0_dp19_tri_i_8(8),
T => shield_dp0_dp19_tri_t_8(8)
);
shield_dp0_dp19_tri_iobuf_9: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_9(9),
IO => shield_dp0_dp19_tri_io(9),
O => shield_dp0_dp19_tri_i_9(9),
T => shield_dp0_dp19_tri_t_9(9)
);
shield_dp26_dp41_tri_iobuf_0: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_0(0),
IO => shield_dp26_dp41_tri_io(0),
O => shield_dp26_dp41_tri_i_0(0),
T => shield_dp26_dp41_tri_t_0(0)
);
shield_dp26_dp41_tri_iobuf_1: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_1(1),
IO => shield_dp26_dp41_tri_io(1),
O => shield_dp26_dp41_tri_i_1(1),
T => shield_dp26_dp41_tri_t_1(1)
);
shield_dp26_dp41_tri_iobuf_10: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_10(10),
IO => shield_dp26_dp41_tri_io(10),
O => shield_dp26_dp41_tri_i_10(10),
T => shield_dp26_dp41_tri_t_10(10)
);
shield_dp26_dp41_tri_iobuf_11: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_11(11),
IO => shield_dp26_dp41_tri_io(11),
O => shield_dp26_dp41_tri_i_11(11),
T => shield_dp26_dp41_tri_t_11(11)
);
shield_dp26_dp41_tri_iobuf_12: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_12(12),
IO => shield_dp26_dp41_tri_io(12),
O => shield_dp26_dp41_tri_i_12(12),
T => shield_dp26_dp41_tri_t_12(12)
);
shield_dp26_dp41_tri_iobuf_13: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_13(13),
IO => shield_dp26_dp41_tri_io(13),
O => shield_dp26_dp41_tri_i_13(13),
T => shield_dp26_dp41_tri_t_13(13)
);
shield_dp26_dp41_tri_iobuf_14: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_14(14),
IO => shield_dp26_dp41_tri_io(14),
O => shield_dp26_dp41_tri_i_14(14),
T => shield_dp26_dp41_tri_t_14(14)
);
shield_dp26_dp41_tri_iobuf_15: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_15(15),
IO => shield_dp26_dp41_tri_io(15),
O => shield_dp26_dp41_tri_i_15(15),
T => shield_dp26_dp41_tri_t_15(15)
);
shield_dp26_dp41_tri_iobuf_2: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_2(2),
IO => shield_dp26_dp41_tri_io(2),
O => shield_dp26_dp41_tri_i_2(2),
T => shield_dp26_dp41_tri_t_2(2)
);
shield_dp26_dp41_tri_iobuf_3: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_3(3),
IO => shield_dp26_dp41_tri_io(3),
O => shield_dp26_dp41_tri_i_3(3),
T => shield_dp26_dp41_tri_t_3(3)
);
shield_dp26_dp41_tri_iobuf_4: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_4(4),
IO => shield_dp26_dp41_tri_io(4),
O => shield_dp26_dp41_tri_i_4(4),
T => shield_dp26_dp41_tri_t_4(4)
);
shield_dp26_dp41_tri_iobuf_5: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_5(5),
IO => shield_dp26_dp41_tri_io(5),
O => shield_dp26_dp41_tri_i_5(5),
T => shield_dp26_dp41_tri_t_5(5)
);
shield_dp26_dp41_tri_iobuf_6: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_6(6),
IO => shield_dp26_dp41_tri_io(6),
O => shield_dp26_dp41_tri_i_6(6),
T => shield_dp26_dp41_tri_t_6(6)
);
shield_dp26_dp41_tri_iobuf_7: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_7(7),
IO => shield_dp26_dp41_tri_io(7),
O => shield_dp26_dp41_tri_i_7(7),
T => shield_dp26_dp41_tri_t_7(7)
);
shield_dp26_dp41_tri_iobuf_8: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_8(8),
IO => shield_dp26_dp41_tri_io(8),
O => shield_dp26_dp41_tri_i_8(8),
T => shield_dp26_dp41_tri_t_8(8)
);
shield_dp26_dp41_tri_iobuf_9: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_9(9),
IO => shield_dp26_dp41_tri_io(9),
O => shield_dp26_dp41_tri_i_9(9),
T => shield_dp26_dp41_tri_t_9(9)
);
spi_io0_iobuf: component IOBUF
port map (
I => spi_io0_o,
IO => spi_io0_io,
O => spi_io0_i,
T => spi_io0_t
);
spi_io1_iobuf: component IOBUF
port map (
I => spi_io1_o,
IO => spi_io1_io,
O => spi_io1_i,
T => spi_io1_t
);
spi_sck_iobuf: component IOBUF
port map (
I => spi_sck_o,
IO => spi_sck_io,
O => spi_sck_i,
T => spi_sck_t
);
spi_ss_iobuf: component IOBUF
port map (
I => spi_ss_o,
IO => spi_ss_io,
O => spi_ss_i,
T => spi_ss_t
);
system_i: component system
port map (
DDR3_addr(13 downto 0) => DDR3_addr(13 downto 0),
DDR3_ba(2 downto 0) => DDR3_ba(2 downto 0),
DDR3_cas_n => DDR3_cas_n,
DDR3_ck_n(0) => DDR3_ck_n(0),
DDR3_ck_p(0) => DDR3_ck_p(0),
DDR3_cke(0) => DDR3_cke(0),
DDR3_cs_n(0) => DDR3_cs_n(0),
DDR3_dm(1 downto 0) => DDR3_dm(1 downto 0),
DDR3_dq(15 downto 0) => DDR3_dq(15 downto 0),
DDR3_dqs_n(1 downto 0) => DDR3_dqs_n(1 downto 0),
DDR3_dqs_p(1 downto 0) => DDR3_dqs_p(1 downto 0),
DDR3_odt(0) => DDR3_odt(0),
DDR3_ras_n => DDR3_ras_n,
DDR3_reset_n => DDR3_reset_n,
DDR3_we_n => DDR3_we_n,
Vaux0_v_n => Vaux0_v_n,
Vaux0_v_p => Vaux0_v_p,
Vaux10_v_n => Vaux10_v_n,
Vaux10_v_p => Vaux10_v_p,
Vaux12_v_n => Vaux12_v_n,
Vaux12_v_p => Vaux12_v_p,
Vaux13_v_n => Vaux13_v_n,
Vaux13_v_p => Vaux13_v_p,
Vaux14_v_n => Vaux14_v_n,
Vaux14_v_p => Vaux14_v_p,
Vaux15_v_n => Vaux15_v_n,
Vaux15_v_p => Vaux15_v_p,
Vaux1_v_n => Vaux1_v_n,
Vaux1_v_p => Vaux1_v_p,
Vaux2_v_n => Vaux2_v_n,
Vaux2_v_p => Vaux2_v_p,
Vaux4_v_n => Vaux4_v_n,
Vaux4_v_p => Vaux4_v_p,
Vaux5_v_n => Vaux5_v_n,
Vaux5_v_p => Vaux5_v_p,
Vaux6_v_n => Vaux6_v_n,
Vaux6_v_p => Vaux6_v_p,
Vaux7_v_n => Vaux7_v_n,
Vaux7_v_p => Vaux7_v_p,
Vaux9_v_n => Vaux9_v_n,
Vaux9_v_p => Vaux9_v_p,
Vp_Vn_v_n => Vp_Vn_v_n,
Vp_Vn_v_p => Vp_Vn_v_p,
dip_switches_4bits_tri_i(3 downto 0) => dip_switches_4bits_tri_i(3 downto 0),
eth_mdio_mdc_mdc => eth_mdio_mdc_mdc,
eth_mdio_mdc_mdio_i => eth_mdio_mdc_mdio_i,
eth_mdio_mdc_mdio_o => eth_mdio_mdc_mdio_o,
eth_mdio_mdc_mdio_t => eth_mdio_mdc_mdio_t,
eth_mii_col => eth_mii_col,
eth_mii_crs => eth_mii_crs,
eth_mii_rst_n => eth_mii_rst_n,
eth_mii_rx_clk => eth_mii_rx_clk,
eth_mii_rx_dv => eth_mii_rx_dv,
eth_mii_rx_er => eth_mii_rx_er,
eth_mii_rxd(3 downto 0) => eth_mii_rxd(3 downto 0),
eth_mii_tx_clk => eth_mii_tx_clk,
eth_mii_tx_en => eth_mii_tx_en,
eth_mii_txd(3 downto 0) => eth_mii_txd(3 downto 0),
eth_ref_clk => eth_ref_clk,
i2c_pullups_tri_i(1) => i2c_pullups_tri_i_1(1),
i2c_pullups_tri_i(0) => i2c_pullups_tri_i_0(0),
i2c_pullups_tri_o(1) => i2c_pullups_tri_o_1(1),
i2c_pullups_tri_o(0) => i2c_pullups_tri_o_0(0),
i2c_pullups_tri_t(1) => i2c_pullups_tri_t_1(1),
i2c_pullups_tri_t(0) => i2c_pullups_tri_t_0(0),
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_scl_t => i2c_scl_t,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
led_4bits_tri_i(3) => led_4bits_tri_i_3(3),
led_4bits_tri_i(2) => led_4bits_tri_i_2(2),
led_4bits_tri_i(1) => led_4bits_tri_i_1(1),
led_4bits_tri_i(0) => led_4bits_tri_i_0(0),
led_4bits_tri_o(3) => led_4bits_tri_o_3(3),
led_4bits_tri_o(2) => led_4bits_tri_o_2(2),
led_4bits_tri_o(1) => led_4bits_tri_o_1(1),
led_4bits_tri_o(0) => led_4bits_tri_o_0(0),
led_4bits_tri_t(3) => led_4bits_tri_t_3(3),
led_4bits_tri_t(2) => led_4bits_tri_t_2(2),
led_4bits_tri_t(1) => led_4bits_tri_t_1(1),
led_4bits_tri_t(0) => led_4bits_tri_t_0(0),
push_buttons_4bits_tri_i(3 downto 0) => push_buttons_4bits_tri_i(3 downto 0),
qspi_flash_io0_i => qspi_flash_io0_i,
qspi_flash_io0_o => qspi_flash_io0_o,
qspi_flash_io0_t => qspi_flash_io0_t,
qspi_flash_io1_i => qspi_flash_io1_i,
qspi_flash_io1_o => qspi_flash_io1_o,
qspi_flash_io1_t => qspi_flash_io1_t,
qspi_flash_io2_i => qspi_flash_io2_i,
qspi_flash_io2_o => qspi_flash_io2_o,
qspi_flash_io2_t => qspi_flash_io2_t,
qspi_flash_io3_i => qspi_flash_io3_i,
qspi_flash_io3_o => qspi_flash_io3_o,
qspi_flash_io3_t => qspi_flash_io3_t,
qspi_flash_sck_i => qspi_flash_sck_i,
qspi_flash_sck_o => qspi_flash_sck_o,
qspi_flash_sck_t => qspi_flash_sck_t,
qspi_flash_ss_i => qspi_flash_ss_i,
qspi_flash_ss_o => qspi_flash_ss_o,
qspi_flash_ss_t => qspi_flash_ss_t,
reset => reset,
rgb_led_tri_i(11) => rgb_led_tri_i_11(11),
rgb_led_tri_i(10) => rgb_led_tri_i_10(10),
rgb_led_tri_i(9) => rgb_led_tri_i_9(9),
rgb_led_tri_i(8) => rgb_led_tri_i_8(8),
rgb_led_tri_i(7) => rgb_led_tri_i_7(7),
rgb_led_tri_i(6) => rgb_led_tri_i_6(6),
rgb_led_tri_i(5) => rgb_led_tri_i_5(5),
rgb_led_tri_i(4) => rgb_led_tri_i_4(4),
rgb_led_tri_i(3) => rgb_led_tri_i_3(3),
rgb_led_tri_i(2) => rgb_led_tri_i_2(2),
rgb_led_tri_i(1) => rgb_led_tri_i_1(1),
rgb_led_tri_i(0) => rgb_led_tri_i_0(0),
rgb_led_tri_o(11) => rgb_led_tri_o_11(11),
rgb_led_tri_o(10) => rgb_led_tri_o_10(10),
rgb_led_tri_o(9) => rgb_led_tri_o_9(9),
rgb_led_tri_o(8) => rgb_led_tri_o_8(8),
rgb_led_tri_o(7) => rgb_led_tri_o_7(7),
rgb_led_tri_o(6) => rgb_led_tri_o_6(6),
rgb_led_tri_o(5) => rgb_led_tri_o_5(5),
rgb_led_tri_o(4) => rgb_led_tri_o_4(4),
rgb_led_tri_o(3) => rgb_led_tri_o_3(3),
rgb_led_tri_o(2) => rgb_led_tri_o_2(2),
rgb_led_tri_o(1) => rgb_led_tri_o_1(1),
rgb_led_tri_o(0) => rgb_led_tri_o_0(0),
rgb_led_tri_t(11) => rgb_led_tri_t_11(11),
rgb_led_tri_t(10) => rgb_led_tri_t_10(10),
rgb_led_tri_t(9) => rgb_led_tri_t_9(9),
rgb_led_tri_t(8) => rgb_led_tri_t_8(8),
rgb_led_tri_t(7) => rgb_led_tri_t_7(7),
rgb_led_tri_t(6) => rgb_led_tri_t_6(6),
rgb_led_tri_t(5) => rgb_led_tri_t_5(5),
rgb_led_tri_t(4) => rgb_led_tri_t_4(4),
rgb_led_tri_t(3) => rgb_led_tri_t_3(3),
rgb_led_tri_t(2) => rgb_led_tri_t_2(2),
rgb_led_tri_t(1) => rgb_led_tri_t_1(1),
rgb_led_tri_t(0) => rgb_led_tri_t_0(0),
shield_dp0_dp19_tri_i(19) => shield_dp0_dp19_tri_i_19(19),
shield_dp0_dp19_tri_i(18) => shield_dp0_dp19_tri_i_18(18),
shield_dp0_dp19_tri_i(17) => shield_dp0_dp19_tri_i_17(17),
shield_dp0_dp19_tri_i(16) => shield_dp0_dp19_tri_i_16(16),
shield_dp0_dp19_tri_i(15) => shield_dp0_dp19_tri_i_15(15),
shield_dp0_dp19_tri_i(14) => shield_dp0_dp19_tri_i_14(14),
shield_dp0_dp19_tri_i(13) => shield_dp0_dp19_tri_i_13(13),
shield_dp0_dp19_tri_i(12) => shield_dp0_dp19_tri_i_12(12),
shield_dp0_dp19_tri_i(11) => shield_dp0_dp19_tri_i_11(11),
shield_dp0_dp19_tri_i(10) => shield_dp0_dp19_tri_i_10(10),
shield_dp0_dp19_tri_i(9) => shield_dp0_dp19_tri_i_9(9),
shield_dp0_dp19_tri_i(8) => shield_dp0_dp19_tri_i_8(8),
shield_dp0_dp19_tri_i(7) => shield_dp0_dp19_tri_i_7(7),
shield_dp0_dp19_tri_i(6) => shield_dp0_dp19_tri_i_6(6),
shield_dp0_dp19_tri_i(5) => shield_dp0_dp19_tri_i_5(5),
shield_dp0_dp19_tri_i(4) => shield_dp0_dp19_tri_i_4(4),
shield_dp0_dp19_tri_i(3) => shield_dp0_dp19_tri_i_3(3),
shield_dp0_dp19_tri_i(2) => shield_dp0_dp19_tri_i_2(2),
shield_dp0_dp19_tri_i(1) => shield_dp0_dp19_tri_i_1(1),
shield_dp0_dp19_tri_i(0) => shield_dp0_dp19_tri_i_0(0),
shield_dp0_dp19_tri_o(19) => shield_dp0_dp19_tri_o_19(19),
shield_dp0_dp19_tri_o(18) => shield_dp0_dp19_tri_o_18(18),
shield_dp0_dp19_tri_o(17) => shield_dp0_dp19_tri_o_17(17),
shield_dp0_dp19_tri_o(16) => shield_dp0_dp19_tri_o_16(16),
shield_dp0_dp19_tri_o(15) => shield_dp0_dp19_tri_o_15(15),
shield_dp0_dp19_tri_o(14) => shield_dp0_dp19_tri_o_14(14),
shield_dp0_dp19_tri_o(13) => shield_dp0_dp19_tri_o_13(13),
shield_dp0_dp19_tri_o(12) => shield_dp0_dp19_tri_o_12(12),
shield_dp0_dp19_tri_o(11) => shield_dp0_dp19_tri_o_11(11),
shield_dp0_dp19_tri_o(10) => shield_dp0_dp19_tri_o_10(10),
shield_dp0_dp19_tri_o(9) => shield_dp0_dp19_tri_o_9(9),
shield_dp0_dp19_tri_o(8) => shield_dp0_dp19_tri_o_8(8),
shield_dp0_dp19_tri_o(7) => shield_dp0_dp19_tri_o_7(7),
shield_dp0_dp19_tri_o(6) => shield_dp0_dp19_tri_o_6(6),
shield_dp0_dp19_tri_o(5) => shield_dp0_dp19_tri_o_5(5),
shield_dp0_dp19_tri_o(4) => shield_dp0_dp19_tri_o_4(4),
shield_dp0_dp19_tri_o(3) => shield_dp0_dp19_tri_o_3(3),
shield_dp0_dp19_tri_o(2) => shield_dp0_dp19_tri_o_2(2),
shield_dp0_dp19_tri_o(1) => shield_dp0_dp19_tri_o_1(1),
shield_dp0_dp19_tri_o(0) => shield_dp0_dp19_tri_o_0(0),
shield_dp0_dp19_tri_t(19) => shield_dp0_dp19_tri_t_19(19),
shield_dp0_dp19_tri_t(18) => shield_dp0_dp19_tri_t_18(18),
shield_dp0_dp19_tri_t(17) => shield_dp0_dp19_tri_t_17(17),
shield_dp0_dp19_tri_t(16) => shield_dp0_dp19_tri_t_16(16),
shield_dp0_dp19_tri_t(15) => shield_dp0_dp19_tri_t_15(15),
shield_dp0_dp19_tri_t(14) => shield_dp0_dp19_tri_t_14(14),
shield_dp0_dp19_tri_t(13) => shield_dp0_dp19_tri_t_13(13),
shield_dp0_dp19_tri_t(12) => shield_dp0_dp19_tri_t_12(12),
shield_dp0_dp19_tri_t(11) => shield_dp0_dp19_tri_t_11(11),
shield_dp0_dp19_tri_t(10) => shield_dp0_dp19_tri_t_10(10),
shield_dp0_dp19_tri_t(9) => shield_dp0_dp19_tri_t_9(9),
shield_dp0_dp19_tri_t(8) => shield_dp0_dp19_tri_t_8(8),
shield_dp0_dp19_tri_t(7) => shield_dp0_dp19_tri_t_7(7),
shield_dp0_dp19_tri_t(6) => shield_dp0_dp19_tri_t_6(6),
shield_dp0_dp19_tri_t(5) => shield_dp0_dp19_tri_t_5(5),
shield_dp0_dp19_tri_t(4) => shield_dp0_dp19_tri_t_4(4),
shield_dp0_dp19_tri_t(3) => shield_dp0_dp19_tri_t_3(3),
shield_dp0_dp19_tri_t(2) => shield_dp0_dp19_tri_t_2(2),
shield_dp0_dp19_tri_t(1) => shield_dp0_dp19_tri_t_1(1),
shield_dp0_dp19_tri_t(0) => shield_dp0_dp19_tri_t_0(0),
shield_dp26_dp41_tri_i(15) => shield_dp26_dp41_tri_i_15(15),
shield_dp26_dp41_tri_i(14) => shield_dp26_dp41_tri_i_14(14),
shield_dp26_dp41_tri_i(13) => shield_dp26_dp41_tri_i_13(13),
shield_dp26_dp41_tri_i(12) => shield_dp26_dp41_tri_i_12(12),
shield_dp26_dp41_tri_i(11) => shield_dp26_dp41_tri_i_11(11),
shield_dp26_dp41_tri_i(10) => shield_dp26_dp41_tri_i_10(10),
shield_dp26_dp41_tri_i(9) => shield_dp26_dp41_tri_i_9(9),
shield_dp26_dp41_tri_i(8) => shield_dp26_dp41_tri_i_8(8),
shield_dp26_dp41_tri_i(7) => shield_dp26_dp41_tri_i_7(7),
shield_dp26_dp41_tri_i(6) => shield_dp26_dp41_tri_i_6(6),
shield_dp26_dp41_tri_i(5) => shield_dp26_dp41_tri_i_5(5),
shield_dp26_dp41_tri_i(4) => shield_dp26_dp41_tri_i_4(4),
shield_dp26_dp41_tri_i(3) => shield_dp26_dp41_tri_i_3(3),
shield_dp26_dp41_tri_i(2) => shield_dp26_dp41_tri_i_2(2),
shield_dp26_dp41_tri_i(1) => shield_dp26_dp41_tri_i_1(1),
shield_dp26_dp41_tri_i(0) => shield_dp26_dp41_tri_i_0(0),
shield_dp26_dp41_tri_o(15) => shield_dp26_dp41_tri_o_15(15),
shield_dp26_dp41_tri_o(14) => shield_dp26_dp41_tri_o_14(14),
shield_dp26_dp41_tri_o(13) => shield_dp26_dp41_tri_o_13(13),
shield_dp26_dp41_tri_o(12) => shield_dp26_dp41_tri_o_12(12),
shield_dp26_dp41_tri_o(11) => shield_dp26_dp41_tri_o_11(11),
shield_dp26_dp41_tri_o(10) => shield_dp26_dp41_tri_o_10(10),
shield_dp26_dp41_tri_o(9) => shield_dp26_dp41_tri_o_9(9),
shield_dp26_dp41_tri_o(8) => shield_dp26_dp41_tri_o_8(8),
shield_dp26_dp41_tri_o(7) => shield_dp26_dp41_tri_o_7(7),
shield_dp26_dp41_tri_o(6) => shield_dp26_dp41_tri_o_6(6),
shield_dp26_dp41_tri_o(5) => shield_dp26_dp41_tri_o_5(5),
shield_dp26_dp41_tri_o(4) => shield_dp26_dp41_tri_o_4(4),
shield_dp26_dp41_tri_o(3) => shield_dp26_dp41_tri_o_3(3),
shield_dp26_dp41_tri_o(2) => shield_dp26_dp41_tri_o_2(2),
shield_dp26_dp41_tri_o(1) => shield_dp26_dp41_tri_o_1(1),
shield_dp26_dp41_tri_o(0) => shield_dp26_dp41_tri_o_0(0),
shield_dp26_dp41_tri_t(15) => shield_dp26_dp41_tri_t_15(15),
shield_dp26_dp41_tri_t(14) => shield_dp26_dp41_tri_t_14(14),
shield_dp26_dp41_tri_t(13) => shield_dp26_dp41_tri_t_13(13),
shield_dp26_dp41_tri_t(12) => shield_dp26_dp41_tri_t_12(12),
shield_dp26_dp41_tri_t(11) => shield_dp26_dp41_tri_t_11(11),
shield_dp26_dp41_tri_t(10) => shield_dp26_dp41_tri_t_10(10),
shield_dp26_dp41_tri_t(9) => shield_dp26_dp41_tri_t_9(9),
shield_dp26_dp41_tri_t(8) => shield_dp26_dp41_tri_t_8(8),
shield_dp26_dp41_tri_t(7) => shield_dp26_dp41_tri_t_7(7),
shield_dp26_dp41_tri_t(6) => shield_dp26_dp41_tri_t_6(6),
shield_dp26_dp41_tri_t(5) => shield_dp26_dp41_tri_t_5(5),
shield_dp26_dp41_tri_t(4) => shield_dp26_dp41_tri_t_4(4),
shield_dp26_dp41_tri_t(3) => shield_dp26_dp41_tri_t_3(3),
shield_dp26_dp41_tri_t(2) => shield_dp26_dp41_tri_t_2(2),
shield_dp26_dp41_tri_t(1) => shield_dp26_dp41_tri_t_1(1),
shield_dp26_dp41_tri_t(0) => shield_dp26_dp41_tri_t_0(0),
spi_io0_i => spi_io0_i,
spi_io0_o => spi_io0_o,
spi_io0_t => spi_io0_t,
spi_io1_i => spi_io1_i,
spi_io1_o => spi_io1_o,
spi_io1_t => spi_io1_t,
spi_sck_i => spi_sck_i,
spi_sck_o => spi_sck_o,
spi_sck_t => spi_sck_t,
spi_ss_i => spi_ss_i,
spi_ss_o => spi_ss_o,
spi_ss_t => spi_ss_t,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
end STRUCTURE;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_quad_spi_flash_0/synth/system_axi_quad_spi_flash_0.vhd
|
1
|
17774
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_10;
USE axi_quad_spi_v3_2_10.axi_quad_spi;
ENTITY system_axi_quad_spi_flash_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_axi_quad_spi_flash_0;
ARCHITECTURE system_axi_quad_spi_flash_0_arch OF system_axi_quad_spi_flash_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_quad_spi_flash_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_DUAL_QUAD_MODE : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_USE_STARTUP_EXT : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
io0_1_i : IN STD_LOGIC;
io0_1_o : OUT STD_LOGIC;
io0_1_t : OUT STD_LOGIC;
io1_1_i : IN STD_LOGIC;
io1_1_o : OUT STD_LOGIC;
io1_1_t : OUT STD_LOGIC;
io2_1_i : IN STD_LOGIC;
io2_1_o : OUT STD_LOGIC;
io2_1_t : OUT STD_LOGIC;
io3_1_i : IN STD_LOGIC;
io3_1_o : OUT STD_LOGIC;
io3_1_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ss_1_i : IN STD_LOGIC;
ss_1_o : OUT STD_LOGIC;
ss_1_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_quad_spi_flash_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_quad_spi_flash_0_arch : ARCHITECTURE IS "system_axi_quad_spi_flash_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_quad_spi_flash_0_arch: ARCHITECTURE IS "system_axi_quad_spi_flash_0,axi_quad_spi,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,Async_Clk=0,C_FAMILY=artix7,C_SELECT_XPM=0,C_SUB_FAMILY=artix7,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_UC_FAMILY=0,C_FIFO_DEPTH=16,C_SCK_RATIO=2,C_DUAL_QUAD_MODE=0,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=2,C_USE_STARTUP=0,C_USE_STARTU" &
"P_EXT=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=1,C_SHARED_STARTUP=0,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000,C_LSB_STUP=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF io2_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_I";
ATTRIBUTE X_INTERFACE_INFO OF io2_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_O";
ATTRIBUTE X_INTERFACE_INFO OF io2_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_T";
ATTRIBUTE X_INTERFACE_INFO OF io3_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_I";
ATTRIBUTE X_INTERFACE_INFO OF io3_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_O";
ATTRIBUTE X_INTERFACE_INFO OF io3_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 0,
C_FAMILY => "artix7",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "artix7",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 2,
C_DUAL_QUAD_MODE => 0,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 2,
C_USE_STARTUP => 0,
C_USE_STARTUP_EXT => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => io2_i,
io2_o => io2_o,
io2_t => io2_t,
io3_i => io3_i,
io3_o => io3_o,
io3_t => io3_t,
io0_1_i => '0',
io1_1_i => '0',
io2_1_i => '0',
io3_1_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ss_1_i => '0',
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END system_axi_quad_spi_flash_0_arch;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_xlconcat_0/sim/system_microblaze_0_xlconcat_0.vhd
|
1
|
7924
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY system_microblaze_0_xlconcat_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END system_microblaze_0_xlconcat_0;
ARCHITECTURE system_microblaze_0_xlconcat_0_arch OF system_microblaze_0_xlconcat_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT xlconcat;
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 7,
NUM_PORTS => 7
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => In6,
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END system_microblaze_0_xlconcat_0_arch;
|
apache-2.0
|
nishtahir/arty-blaze
|
src/bd/system/ipshared/a811/hdl/axi_intc_v4_1_vh_rfs.vhd
|
1
|
182883
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : double_synchronizer.vhd
-- Version : v3.0
-- Description: The double_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- RESET_2 signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity double_synchronizer is
generic (
C_DWIDTH : integer range 1 to 32 := 1
);
port (
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active_low
DATA_IN : in std_logic_vector(C_DWIDTH-1 downto 0);
SYNC_DATA_OUT : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity;
-------------------------------------------------------------------------------
architecture RTL of double_synchronizer is
signal RESET_2_p : std_logic;
signal data_in_d1 : std_logic_vector(C_DWIDTH-1 downto 0);
-----
begin
-----
-- active high Reset
RESET_2_p <= not RESET_2_n;
REG_GEN : for i in 0 to (C_DWIDTH - 1) generate
BLOCK_GEN: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FIRST_FLOP_i : label is "TRUE";
begin
FIRST_FLOP_i: component FDR
port map (
Q => data_in_d1(i),
C => CLK_2,
D => DATA_IN(i),
R => RESET_2_p
);
SECOND_FLOP_i: component FDR
port map (
Q => SYNC_DATA_OUT(i),
C => CLK_2,
D => data_in_d1(i),
R => RESET_2_p
);
end block BLOCK_GEN;
end generate REG_GEN;
-------------------------------------------------------------------------------
end RTL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : pulse_synchronizer.vhd
-- Version : v3.0
-- Description: The pulse_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.all;
entity pulse_synchronizer is
port (
CLK_1 : in std_logic;
RESET_1_n : in std_logic; -- active low reset
DATA_IN : in std_logic;
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active low reset
SYNC_DATA_OUT : out std_logic
);
end entity;
architecture RTL of pulse_synchronizer is
signal data_in_toggle : std_logic;
signal data_in_toggle_sync : std_logic;
signal data_in_toggle_sync_d1 : std_logic;
signal data_in_toggle_sync_vec : std_logic_vector(0 downto 0);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
begin
TOGGLE_DATA_IN_REG:process(CLK_1)
begin
if(CLK_1'event and CLK_1 = '1') then
if(RESET_1_n = '0') then
data_in_toggle <= '0';
else
data_in_toggle <= DATA_IN xor data_in_toggle;
end if;
end if;
end process TOGGLE_DATA_IN_REG;
DOUBLE_SYNC_I : entity axi_intc_v4_1_9.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => CLK_2,
RESET_2_n => RESET_2_n,
DATA_IN => scalar_to_vector(data_in_toggle),
SYNC_DATA_OUT => data_in_toggle_sync_vec
);
data_in_toggle_sync <= data_in_toggle_sync_vec(0);
SYNC_DATA_REG:process(CLK_2)
begin
if(CLK_2'event and CLK_2 = '1') then
if(RESET_2_n = '0') then
data_in_toggle_sync_d1 <= '0';
else
data_in_toggle_sync_d1 <= data_in_toggle_sync;
end if;
end if;
end process SYNC_DATA_REG;
SYNC_DATA_OUT <= data_in_toggle_sync xor data_in_toggle_sync_d1;
end RTL;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: intc_core.vhd
-- Version: v3.1
-- Description: Interrupt controller without a bus interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- ~~~~~~
-- - Initial release of v2.00.a
-- - Updated by pkaruna
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support in v3.1 version of the core
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.std_logic_misc.all;
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- Intc Parameters
-- C_DWIDTH -- Data bus width
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits
-- Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits
-- Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- Clk -- Clock
-- Rst -- Reset
-- Intc Interface Signals
-- Intr -- Input Interruput request
-- Reg_addr -- Address bus
-- Bus2ip_rdce -- Read
-- Bus2ip_wrce -- Write
-- Wr_data -- Write data bus
-- Rd_data -- Read data bus
-- Irq -- Output Interruput request
-- Processor_clk -- input same as processor clock
-- Processor_rst -- input same as processor reset
-- Processor_ack -- input Connected to processor ACK
-- Interrupt_address -- output Connected to processor interrupt address pins
-- Interrupt_address_in -- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- Processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------
entity intc_core is
generic
(
C_FAMILY : string := "virtex6";
C_DWIDTH : integer := 32;
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 0;
C_HAS_FAST : integer range 0 to 1 := 0;
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
);
port
(
-- Inputs
Clk : in std_logic; --- AXI Clock
Rst_n : in std_logic; --- active low AXI Reset
Intr : in std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
Reg_addr : in std_logic_vector(6 downto 0);
Bus2ip_rdce : in std_logic_vector(0 to 16);
Bus2ip_wrce : in std_logic_vector(0 to 16);
Wr_data : in std_logic_vector(C_DWIDTH - 1 downto 0);
-- Outputs
Rd_data : out std_logic_vector(C_DWIDTH - 1 downto 0);
Processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- active high MB rst, reset from MicroBlaze
Irq : out std_logic;
Processor_ack : in std_logic_vector(1 downto 0); --- added for fast interrupt mode
Interrupt_address : out std_logic_vector(31 downto 0); --- added for fast interrupt mode
--
Interrupt_address_in : in std_logic_vector(31 downto 0);
Processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
attribute buffer_type: string;
attribute buffer_type of Intr: signal is "none";
end intc_core;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture imp of intc_core is
-- Component Declarations
-- ======================
constant C_NUM_INTR : integer := C_NUM_INTR_INPUTS + C_NUM_SW_INTR;
constant RESET_ACTIVE : std_logic := '0';
CONSTANT INDEX_BIT : INTEGER := INTEGER(CEIL(LOG2(REAL(C_NUM_INTR+1))));
constant MICROBLAZE_FIXED_ADDRESS : std_logic_vector := X"00000010";
CONSTANT IVR_ALL_ONES : std_logic_vector(INDEX_BIT-1 downto 0) := (others => '1');
--- *** --- Decision is pending for logic used - mail sent to Bsb on 3rd Oct, 2012
CONSTANT C_USE_METHOD : integer := 1;
--- *** ---
-- Signal declaration
-- ==================
signal processor_rst_n : std_logic;
signal ack_b01 : std_logic;
signal first_ack : std_logic;
signal first_ack_active : std_logic;
signal second_ack : std_logic;
signal first_ack_sync : std_logic;
signal second_ack_sync : std_logic;
signal second_ack_sync_d1 : std_logic;
signal second_ack_sync_d2 : std_logic;
signal second_ack_sync_d3 : std_logic;
signal second_ack_sync_mb_clk : std_logic;
signal Irq_i : std_logic;
signal ivr_data_in : std_logic_vector(INDEX_BIT - 1 downto 0);
signal wr_data_int : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal mer_int : std_logic_vector(1 downto 0);
signal mer : std_logic_vector(C_DWIDTH - 1 downto 0);
signal sie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal cie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal iar : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ier : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal isr_en : std_logic;
signal hw_intr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_data_in : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ivr : std_logic_vector(INDEX_BIT - 1 downto 0);
signal ivr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ilr : std_logic_vector(INDEX_BIT downto 0);
signal ilr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal imr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal imr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ipr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal irq_gen_i : std_logic;
signal irq_gen : std_logic;
signal irq_gen_sync : std_logic;
signal read : std_logic;
signal ier_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ack_or_i : std_logic;
signal ack_or : std_logic;
signal ack_or_sync : std_logic;
signal read_ivar : std_logic;
signal write_ivar : std_logic;
signal isr_or : std_logic;
signal ivar_index_mb_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal ivar_index_axi_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal in_idle : std_logic;
signal in_idle_axi_clk : std_logic;
signal idle_and_irq : std_logic;
signal idle_and_irq_d1 : std_logic;
signal ivar_index_sample_en_i : std_logic;
signal ivar_index_sample_en : std_logic;
signal ivar_index_sample_en_mb_clk : std_logic;
signal irq_dis_sample_mb_clk : std_logic;
signal ivar_rd_addr_mb_clk : std_logic_vector(4 downto 0);
signal mer_0_sync : std_logic;
--signal bus2ip_rdce_fast : std_logic_vector(0 to 31);
--signal bus2ip_wrce_fast : std_logic_vector(0 to 31);
signal bus2ip_rdce_fast : std_logic;
signal bus2ip_wrce_fast : std_logic;
signal ivar_rd_data_axi_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ivar_rd_data_mb_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_ored_30_0_bits : std_logic;
signal Interrupt_address_in_reg_int : std_logic_vector(31 downto 0);
signal intr_31_deassert_info : std_logic;
signal intr_31_deasserted_d1 : std_logic;
signal intr_31_deasserted : std_logic;
-- --------------------------------------------------------------------------------------
-- -- Function to find logic OR of 32 bit width vector
-- --------------------------------------------------------------------------------------
-- Function OR32_VEC2STDLOGIC (vec_in : std_logic_vector) return std_logic is
-- variable or_out : std_logic := '0';
-- begin
-- for i in 0 to 31 loop
-- or_out := vec_in(i) or or_out;
-- end loop;
-- return or_out;
-- end function Or32_vec2stdlogic;
-- --------------------------------------------------------------------------------------
FUNCTION calc_ivar_ram_addr_bits (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 5;
else
RETURN 4;
end if;
end FUNCTION calc_ivar_ram_addr_bits;
-------------------------------------
FUNCTION calc_ivar_ram_depth (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 32;
else
RETURN 16;
end if;
end FUNCTION calc_ivar_ram_depth;
---------------------------------
CONSTANT IVAR_MEM_ADDR_LINES : INTEGER := calc_ivar_ram_addr_bits (C_NUM_INTR);
CONSTANT IVAR_MEM_DEPTH : INTEGER := calc_ivar_ram_depth (C_NUM_INTR);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
-- Begin of architecture
begin
-----
-- active low reset
processor_rst_n <= not Processor_rst;
read <= bus2ip_rdce(0) or -- for ISR
bus2ip_rdce(1) or -- for IPR
bus2ip_rdce(2) or -- for IER
bus2ip_rdce(6) or -- for IVR
bus2ip_rdce(7) or -- for MER
bus2ip_rdce(8) or -- for IMR
bus2ip_rdce(9); -- for ILR
--------------------------------------------------------------------------
-- GENERATING ALL REGISTERS
--------------------------------------------------------------------------
wr_data_int <= Wr_data(C_NUM_INTR - 1 downto 0);
-------------------------------------------------------------------------
-- GENERATING IVAR READ ENABLES
-------------------------------------------------------------------------
bus2ip_rdce_fast <= bus2ip_rdce(16);
bus2ip_wrce_fast <= bus2ip_wrce(16);
write_ivar <= bus2ip_wrce_fast;
read_ivar <= bus2ip_rdce_fast;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------
NO_CASCADE_MASTER_MODE : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------------------------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
-----------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
-----------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
-----------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
-----------------------------------------
end generate NO_CASCADE_MASTER_MODE;
-----------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) & -- to avoide any delay the processor is
(Processor_ack(0) and (not isr_ored_30_0_bits)) ; -- simply passed to below modules
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
--------------------------------------------
end generate ACK_EN_SYNC_EN_GEN;
--------------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
--------------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
--------------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
--------------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
--------------------------------------------
end generate CASCADE_MASTER_MODE_10;
-----------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
------------------------------------
end generate CASCADE_MASTER_MODE_11;
-----------------------------
end generate ACK_EN_SYNC_ON_MB_CLK_GEN;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
NO_CASCADE_MASTER : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate NO_CASCADE_MASTER;
-------------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate CASCADE_MASTER_MODE_10;
-------------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')-- and
--(isr(31) = '0') and
--(ier(31) = '0') -- and
-- (isr_ored_30_0_bits = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
-----------------------------------
end generate CASCADE_MASTER_MODE_11;
-------------------------------
----------------------------------------
end generate ACK_EN_SYNC_ON_AXI_CLK_GEN;
SECOND_ACK_FAST_0_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
second_ack_sync_mb_clk <= ack_or_sync;
Processor_ack_out <= (others => '0');
end generate SECOND_ACK_FAST_0_GEN;
--------------------------------------------------------------------------
-- Process MER_ME_P for MER ME bit generation
--------------------------------------------------------------------------
MER_ME_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(0) <= '0';
elsif (bus2ip_wrce(7) = '1') then
mer_int(0) <= Wr_data(0);
end if;
end if;
end process MER_ME_P;
--------------------------------------------------------------------------
-- Process MER_HIE_P for generating MER HIE bit
--------------------------------------------------------------------------
MER_HIE_P: process (Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(1) <= '0';
elsif ((bus2ip_wrce(7) = '1') and (mer_int(1) = '0')) then
mer_int(1) <= Wr_data(1);
end if;
end if;
end process MER_HIE_P;
-----------------------------------
mer(1 downto 0) <= mer_int;
mer(C_DWIDTH - 1 downto 2) <= (others => '0');
-----------------------------------
----------------------------------------------------------------------
-- Generate SIE if (C_HAS_SIE = 1)
----------------------------------------------------------------------
SIE_GEN: if (C_HAS_SIE = 1) generate
-----
begin
-----
SIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
--------------------------------------------------------------
-- Process SIE_P for generating SIE register
--------------------------------------------------------------
SIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (sie(i) = '1')) then
sie(i) <= '0';
elsif (bus2ip_wrce(4) = '1') then
sie(i) <= wr_data_int(i);
end if;
end if;
end process SIE_P;
end generate SIE_BIT_GEN;
end generate SIE_GEN;
----------------------------------------------------------------------
-- Assign sie_out ALL ZEROS if (C_HAS_SIE = 0)
----------------------------------------------------------------------
SIE_NO_GEN: if (C_HAS_SIE = 0) generate
-----
begin
-----
sie <= (others => '0');
end generate SIE_NO_GEN;
----------------------------------------------------------------------
-- Generate CIE if (C_HAS_CIE = 1)
----------------------------------------------------------------------
CIE_GEN: if (C_HAS_CIE = 1) generate
-----
begin
-----
CIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
------------------------------------------------------------------
-- Process CIE_P for generating CIE register
------------------------------------------------------------------
CIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
cie(i) <= '0';
elsif (bus2ip_wrce(5) = '1') then
cie(i) <= wr_data_int(i);
end if;
end if;
end process CIE_P;
end generate CIE_BIT_GEN;
end generate CIE_GEN;
----------------------------------------------------------------------
-- Assign cie_out ALL ZEROS if (C_HAS_CIE = 0)
----------------------------------------------------------------------
CIE_NO_GEN: if (C_HAS_CIE = 0) generate
cie <= (others => '0');
end generate CIE_NO_GEN;
-- Generating write enable & data input for ISR
isr_en <= mer(1) or bus2ip_wrce(0);
isr_data_in <= hw_intr when mer(1) = '1' else
Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Generate Registers of width equal C_NUM_INTR
--------------------------------------------------------------------------
REG_GEN : for i in 0 to (C_NUM_INTR - 1) generate
-----
begin
-----
--IAR_NORMAL_MODE_GEN: if ((C_HAS_FAST = 0) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
IAR_NORMAL_MODE_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_NORMAL_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1')) then
iar(i) <= wr_data_int(i);
else
iar(i) <= '0';
end if;
end if;
end process IAR_NORMAL_BIT_P;
-----------------------------------
end generate IAR_NORMAL_MODE_GEN;
---------------------------------
IAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_FAST_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1') and (imr(i) = '0')) then
iar(i) <= wr_data_int(i);
elsif (imr(i) = '1') then
if (((C_KIND_OF_INTR(i) = '1') and (first_ack_sync = '1')) or
((C_KIND_OF_INTR(i) = '0') and (second_ack_sync = '1'))) then
if (i = TO_INTEGER(unsigned(ivar_index_axi_clk))) then -- -- clearing IAR based on Processor_ack in FAST_INTERRUPT mode
iar(i) <= '1';
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
end if;
end process IAR_FAST_BIT_P;
-----------------------------------
end generate IAR_FAST_MODE_GEN;
-------------------------------
----------------------------------------------------------------------
-- Process IER_BIT_P for generating IER register
----------------------------------------------------------------------
IER_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
ier(i) <= '0';
elsif (sie(i) = '1') then
ier(i) <= '1';
elsif (bus2ip_wrce(2) = '1') then
ier(i) <= wr_data_int(i);
end if;
end if;
end process IER_BIT_P;
----------------------------------------------------------------------
-- Process ISR_P for generating ISR register
----------------------------------------------------------------------
ISR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (iar(i) = '1')) then
isr(i) <= '0';
elsif (i < C_NUM_INTR_INPUTS) then
if (isr_en = '1') then
isr(i) <= isr_data_in(i);
end if;
elsif (i >= C_NUM_INTR_INPUTS) then
if (bus2ip_wrce(0) = '1') then
isr(i) <= Wr_data(i);
end if;
end if;
end if;
end process ISR_P;
----------------------------------------------------------------------
-- Process IMR_P for generating IMR(Interrrupt Mode Register) Register
----------------------------------------------------------------------
IMR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IMR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
imr(i) <= '0';
elsif bus2ip_wrce(8) = '1' then
imr(i) <= wr_data_int(i);
end if;
end if;
end process IMR_P;
end generate IMR_FAST_MODE_GEN;
-----------------------------------
end generate REG_GEN;
---------------------
---------------------------------------------------------------------------
-- Proces IVAR_REG_P for generating IVAR Registers
---------------------------------------------------------------------------
IVAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IVAR_REG_MEM_MB_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 0) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1_9.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Processor_clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_MB_CLK_GEN;
IVAR_REG_MEM_AXI_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 1) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1_9.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_AXI_CLK_GEN;
end generate IVAR_FAST_MODE_GEN;
-----------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR /= C_DWIDTH
-----------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR: if (C_NUM_INTR /= C_DWIDTH) generate
-----
begin
-----
ier_out(C_NUM_INTR - 1 downto 0) <= ier;
ier_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_out(C_NUM_INTR - 1 downto 0) <= isr;
isr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
imr_out(C_NUM_INTR - 1 downto 0) <= imr;
imr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-1 downto 0));
end generate REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR;
------------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR = C_DWIDTH
------------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_EQ_NUM_INTR: if (C_NUM_INTR = C_DWIDTH) generate
-----
begin
-----
ier_out <= ier;
isr_out <= isr;
imr_out <= imr;
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-2 downto 0));
end generate REG_OUT_GEN_DWIDTH_EQ_NUM_INTR;
ilr_out (INDEX_BIT-1 downto 0) <= ilr(INDEX_BIT - 1 downto 0);
ilr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ilr(INDEX_BIT) = '1' else
(others => '0');
ivr_out (INDEX_BIT-1 downto 0) <= ivr;
ivr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ((ivr = IVR_ALL_ONES)) else
(others => '0');
--------------------------------------------------------------------------
-- Generate IPR if (C_HAS_IPR = 1)
--------------------------------------------------------------------------
IPR_GEN: if (C_HAS_IPR = 1) generate
----------------------------------------------------------------------
-- Process IPR_P for generating IPR register
----------------------------------------------------------------------
IPR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ipr <= (others => '0');
else
ipr <= isr_out and ier_out;
end if;
end if;
end process IPR_P;
------------------
end generate IPR_GEN;
---------------------
--------------------------------------------------------------------------
-- Assign IPR ALL ZEROS if (C_HAS_IPR = 0)
--------------------------------------------------------------------------
IPR_NO_GEN: if (C_HAS_IPR = 0) generate
ipr <= (others => '0');
end generate IPR_NO_GEN;
--------------------------------------------------------------------------
-- Generate IVR if (C_HAS_IVR = 1 or C_HAS_FAST = 1)
--------------------------------------------------------------------------
IVR_GEN: if ((C_HAS_IVR = 1) or (C_HAS_FAST = 1)) generate
begin
----------------------------------------------------------------------
-- Process IVR_DATA_GEN_P for generating interrupt vector address
----------------------------------------------------------------------
IVR_DATA_GEN_P: process (isr, ier) is
variable ivr_in : std_logic_vector(INDEX_BIT - 1 downto 0)
:= (others => '1');
-----
begin
-----
for i in natural range 0 to (C_NUM_INTR - 1) loop
if ((isr(i) = '1') and (ier(i) = '1')) then
--ivr_in := CONV_STD_LOGIC_VECTOR(i, INDEX_BIT);
ivr_in := std_logic_vector(to_unsigned(i, INDEX_BIT));
exit;
else
ivr_in := (others => '1');
end if;
end loop;
ivr_data_in <= ivr_in;
end process IVR_DATA_GEN_P;
----------------------------------------------------------------------
-- Process IVR_P for generating IVR register
----------------------------------------------------------------------
IVR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivr <= (others => '1');
else
ivr <= ivr_data_in;
end if;
end if;
end process IVR_P;
end generate IVR_GEN;
--------------------------------------------------------------------------
-- Assign IVR ALL ONES if (C_HAS_IVR = 0) and (C_HAS_FAST = 0)
--------------------------------------------------------------------------
IVR_NO_GEN: if ((C_HAS_IVR = 0) and (C_HAS_FAST = 0)) generate
ivr <= (others => '1');
end generate IVR_NO_GEN;
--------------------------------------------------------------------------
-- Generate ILR if (C_HAS_ILR = 1)
--------------------------------------------------------------------------
ILR_GEN: if (C_HAS_ILR = 1) generate
begin
----------------------------------------------------------------------
-- Process ILR_P for generating ILR register
----------------------------------------------------------------------
ILR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ilr <= (others => '1');
elsif (bus2ip_wrce(9) = '1') then
ilr <= Wr_data(INDEX_BIT downto 0);
end if;
end if;
end process ILR_P;
end generate ILR_GEN;
--------------------------------------------------------------------------
-- Assign ILR ALL ONES if (C_HAS_ILR = 0)
--------------------------------------------------------------------------
ILR_NO_GEN: if (C_HAS_ILR = 0) generate
begin
ilr <= (others => '1');
end generate ILR_NO_GEN;
--------------------------------------------------------------------------
-- DETECTING HW INTERRUPT
--------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Detecting the interrupts
---------------------------------------------------------------------------
INTR_DETECT_GEN: for i in 0 to C_NUM_INTR_INPUTS - 1 generate
signal synced_intr : std_logic := '0';
begin
-----------------------------------------------------------------------
-- Generating the synchronization flip-flops if C_ASYNC_INTR(i) = 1
-----------------------------------------------------------------------
ASYNC_GEN: if C_ASYNC_INTR(i) = '1' and C_NUM_SYNC_FF > 0 generate
signal intr_ff : std_logic_vector(0 to C_NUM_SYNC_FF - 1) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of intr_ff : signal is "TRUE";
begin
--------------------------------------------
-- Process SYNC_P to synchronize hw_intr
--------------------------------------------
SYNC_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
intr_ff(0) <= Intr(i);
for k in intr_ff'left to intr_ff'right - 1 loop
intr_ff(k + 1) <= intr_ff(k);
end loop;
end if;
end process SYNC_P;
synced_intr <= intr_ff(intr_ff'right);
------------------------------
end generate ASYNC_GEN;
-----------------------------------------------------------------------
-- No synchronization flip-flops if C_ASYNC_INTR(i) = 0
-----------------------------------------------------------------------
SYNC_GEN: if C_ASYNC_INTR(i) = '0' or C_NUM_SYNC_FF = 0 generate
begin
synced_intr <= Intr(i);
end generate SYNC_GEN;
-----------------------------------------------------------------------
-- Generating the edge triggered interrupts if C_KIND_OF_INTR(i) = 1
-----------------------------------------------------------------------
EDGE_DETECT_GEN: if C_KIND_OF_INTR(i) = '1' generate
signal intr_d1 : std_logic;
signal intr_edge : std_logic;
begin
----------------------------------------------------------------
-- Process REG_INTR_EDGE_P to register the interrupt signal edge
----------------------------------------------------------------
REG_INTR_EDGE_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if Rst_n = RESET_ACTIVE then
intr_d1 <= not C_KIND_OF_EDGE(i);
else
intr_d1 <= synced_intr;
end if;
end if;
end process REG_INTR_EDGE_P;
-- Creating one-shot edge triggered interrupt
intr_edge <= '1' when (synced_intr = C_KIND_OF_EDGE(i)) and
(intr_d1 = not C_KIND_OF_EDGE(i)) else
'0';
-----------------------------------------------------------------
-- Process DETECT_INTR_P to generate the edge triggered interrupt
-----------------------------------------------------------------
DETECT_INTR_P : process (Clk) is
begin
if Clk'event and Clk='1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif (intr_edge = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process DETECT_INTR_P;
--------------------------
end generate EDGE_DETECT_GEN;
----------------------------------------------------------------------
-- Generating the Level trigeered interrupts if C_KIND_OF_INTR(i) = 0
----------------------------------------------------------------------
LVL_DETECT_GEN: if C_KIND_OF_INTR(i) = '0' generate
begin
------------------------------------------------------------------
-- Process LVL_P to generate hw_intr (active high or low)
------------------------------------------------------------------
LVL_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif synced_intr = C_KIND_OF_LVL(i) then
hw_intr(i) <= '1';
end if;
end if;
end process LVL_P;
------------------
end generate LVL_DETECT_GEN;
end generate INTR_DETECT_GEN;
--------------------------------------------------------------------------
-- Checking Active Interrupt/Interrupts
--------------------------------------------------------------------------
IRQ_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
-----
begin
-----
irq_gen_i<= isr(0) and ier(0) and ilr(0);
end generate IRQ_ONE_INTR_GEN;
IRQ_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process IRQ_GEN_P to generate irq_gen
--------------------------------------------------------------
IRQ_GEN_P: process (isr, ier, ilr) is
variable ilr_value : integer;
variable irq_gen_int : std_logic;
-----
begin
-----
ilr_value := TO_INTEGER(unsigned( ilr(INDEX_BIT - 1 downto 0) ));
irq_gen_int := '0';
for i in 0 to (isr'length - 1) loop
if (C_HAS_ILR = 1) then
exit when (i = ilr_value) and (ilr(INDEX_BIT) = '0');
end if;
irq_gen_int := irq_gen_int or (isr(i) and ier(i));
end loop;
irq_gen_i <= irq_gen_int;
end process IRQ_GEN_P;
----------------------
end generate IRQ_MULTI_INTR_GEN;
--------------------------------
-- Registering irq_gen_i as it will be going through double synchronizer
IRQ_GEN_REG_P : Process(Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_gen <= '0';
else
irq_gen <= irq_gen_i;
end if;
end if;
end process IRQ_GEN_REG_P;
--------------------------
--------------------------------------------------------------
-- Synchronizing irq_gen
--------------------------------------------------------------
IRQ_GEN_SYNC_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
signal irq_gen_sync_vec : std_logic_vector(0 downto 0);
-----
begin
-----
-- Synchronize irq_gen to Processor clock domain
IRQ_GEN_DOUBLE_SYNC_I: entity axi_intc_v4_1_9.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(irq_gen),
SYNC_DATA_OUT => irq_gen_sync_vec
);
irq_gen_sync <= irq_gen_sync_vec(0);
end generate IRQ_GEN_SYNC_GEN;
IRQ_GEN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
irq_gen_sync <= irq_gen;
end generate IRQ_GEN_SYNC_DISABLE_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-----
begin
-----
IN_IDLE_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
signal in_idle_axi_clk_vec : std_logic_vector(0 downto 0);
begin
IN_IDLE_DOUBLE_SYNC_I: entity axi_intc_v4_1_9.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Clk,
RESET_2_n => Rst_n,
DATA_IN => scalar_to_vector(in_idle),
SYNC_DATA_OUT => in_idle_axi_clk_vec
);
in_idle_axi_clk <= in_idle_axi_clk_vec(0);
end generate IN_IDLE_SYNC_EN_GEN;
---------------------------------
IN_IDLE_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
in_idle_axi_clk <= in_idle;
end generate IN_IDLE_SYNC_DISABLE_GEN;
--------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen_i and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
------------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
------------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
------------------------------------
IVAR_INDEX_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ivar_index_sample_en,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ivar_index_sample_en_mb_clk
);
end generate IVAR_INDEX_SYNC_EN_GEN;
------------------------------------
IVAR_INDEX_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
end generate IVAR_INDEX_SYNC_DISABLE_GEN;
------------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr_data_in;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
------------------------------------
IVAR_INDEX_MB_REG_P : Process(Processor_clk)
begin
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
ivar_index_mb_clk <= (others => '0');
else
if (ivar_index_sample_en_mb_clk = '1') then
ivar_index_mb_clk <= ivar_index_axi_clk;
else
ivar_index_mb_clk <= ivar_index_mb_clk;
end if;
end if;
end if;
end process IVAR_INDEX_MB_REG_P;
------------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
------------------------------------
end generate IVAR_INDEX_SYNC_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen_i;
IDLE_NOT_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_NOT_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
IRQ_DIS_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => irq_dis_sample,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => irq_dis_sample_mb_clk
);
end generate IRQ_DIS_SYNC_EN_GEN;
IRQ_DIS_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_DISABLE_GEN;
end generate IRQ_DIS_SYNC_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
in_idle_axi_clk <= in_idle;
------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
--------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
--------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
--------------------------------
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
--------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
--------------------------------
ivar_index_mb_clk <= ivar_index_axi_clk;
--------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
end generate IVAR_INDEX_SYNC_ON_AXI_CLK_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen;
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_ON_AXI_CLK_GEN;
NO_IRQ_DIS_SYNC: if (C_HAS_FAST = 0) or (C_HAS_ILR = 0) generate
begin
irq_dis_sample_mb_clk <= '0';
end generate NO_IRQ_DIS_SYNC;
----------------------------------------------------------------------
-- MER_0_DOUBLE_SYNC_I to synchronize MER(0) with Processor_clk
----------------------------------------------------------------------
MER_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
signal mer_0_sync_vec : std_logic_vector(0 downto 0);
begin
--Synchronize mer(0) to Processor clock domain
MER_0_DOUBLE_SYNC_I: entity axi_intc_v4_1_9.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(mer(0)),
SYNC_DATA_OUT => mer_0_sync_vec
);
mer_0_sync <= mer_0_sync_vec(0);
end generate MER_SYNC_EN_GEN;
------------------------------
MER_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
mer_0_sync <= mer(0);
end generate MER_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating LEVEL interrupt if C_IRQ_IS_LEVEL = 1
--------------------------------------------------------------------------
IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1) generate
-- Level IRQ generation if C_HAS_FAST is 1
IRQ_LEVEL_FAST_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((ivar_index_sample_en_mb_clk = '1')) then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-----------------------------
GEN_LEVEL_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
-----------------------------
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-- local signal declaration
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
end generate IRQ_LEVEL_FAST_ON_MB_CLK_GEN;
------------------------------------------------------------------
IRQ_LEVEL_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-------------------------------
GEN_LEVEL_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
----------------------------
-- Interrupt_address <= ivar_rd_data_mb_clk;
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
-------------------------------------------
end generate IRQ_LEVEL_FAST_ON_AXI_CLK_GEN;
-- Level IRQ generation if C_HAS_FAST is 0
IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_P: process (Processor_clk) is
begin
if(Processor_clk'event and Processor_clk = '1') then
if ((processor_rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_P;
-------------------------------------
Interrupt_address <= (others => '0');
-------------------------------------
end generate IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN;
IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_ON_AXI_P: process (Clk) is
begin
if(Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_ON_AXI_P;
Interrupt_address <= (others => '0');
end generate IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN;
end generate IRQ_LEVEL_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR = 1
----------------------------------------------------------------------
ACK_OR_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
ack_or_i <= iar(0);
end generate ACK_OR_ONE_INTR_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR > 1
----------------------------------------------------------------------
ACK_OR_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process ACK_OR_GEN_P to generate ack_or (ORed Acks)
--------------------------------------------------------------
ACK_OR_GEN_P: process (iar)
variable ack_or_int : std_logic := '0';
begin
ack_or_int := iar(0);
for i in 1 to (iar'length - 1) loop
ack_or_int := ack_or_int or (iar(i));
end loop;
ack_or_i <= ack_or_int;
end process ACK_OR_GEN_P;
end generate ACK_OR_MULTI_INTR_GEN;
----------------------------------
ACK_OR_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ack_or <= '0';
else
ack_or <= ack_or_i;
end if;
end if;
end process ACK_OR_REG_P;
-------------------------
ACK_OR_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
ACK_OR_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ack_or,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ack_or_sync
);
end generate ACK_OR_SYNC_EN_GEN;
ACK_OR_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
ack_or_sync <= ack_or;
end generate ACK_OR_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating EDGE interrupt if C_IRQ_IS_LEVEL = 0
--------------------------------------------------------------------------
IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0) generate
IRQ_EDGE_FAST_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
GEN_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------
end generate IRQ_EDGE_FAST_GEN;
IRQ_EDGE_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
---------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
---------------------------
GEN_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-----------------------
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------------------
end generate IRQ_EDGE_FAST_ON_AXI_CLK_GEN;
--IRQ_EDGE_NORMAL_GEN: if (C_HAS_FAST = 0) generate
IRQ_EDGE_NO_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_NO_MB_CLK_GEN;
IRQ_EDGE_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK, WAIT_SYNC);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
if (C_DISABLE_SYNCHRONIZERS = 1) then
current_state <= IDLE;
else
current_state <= WAIT_SYNC;
end if;
else
current_state <= WAIT_ACK;
end if;
when WAIT_SYNC => current_state <= IDLE;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_MB_CLK_GEN;
--end generate IRQ_EDGE_NORMAL_GEN;
end generate IRQ_EDGE_GEN;
--Read data in Normal mode (C_HAS_FAST = 0)
OUTPUT_DATA_NORMAL_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read, Reg_addr, isr_out, ipr, ier_out,
ilr_out, ivr_out, mer) is
-----
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate OUTPUT_DATA_NORMAL_GEN;
--Read data in mixed mode (C_HAS_FAST = 1) and C_EN_CASCADE_MODE = 1 and C_CASCADE_MASTER = 1
CASCADE_OP_DATA_FAST_GEN: if ((C_HAS_FAST = 1) and
(C_EN_CASCADE_MODE = 1)
) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk,
Interrupt_address_in_reg_int,
ier ,
isr ,
isr_ored_30_0_bits) is
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then -- read IVAR of 31st bit in case the interrupt is present
if((isr(31) = '1') and -- else to read IVAR of lower modules the processor has to
(ier(31) = '1') and -- initiate the transaction for lower module separately
(isr_ored_30_0_bits = '0')
)then
Rd_data <= Interrupt_address_in_reg_int;
else
Rd_data <= ivar_rd_data_axi_clk;
end if;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
NO_CASCADE_OP_DATA_FAST_GEN: if (C_HAS_FAST = 1) and
(C_CASCADE_MASTER = 0) and
(C_EN_CASCADE_MODE = 0)
generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk) is
begin
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then
Rd_data <= ivar_rd_data_axi_clk;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate NO_CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
end imp;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_intc.vhd
-- Version: v3.1
-- Description: Interrupt controller interfaced to AXI.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- PB 09/21/10
--
-- - updated the axi_lite_ipif from v1.00.a to v1.01.a
-- ~~~~~~
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
-- SA 12/26/15
--
-- 1. Simplified cascade connections by adding Irq_in port
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------
-- Library axi_lite_ipif_v3_0_4 is used because it contains the
-- axi_lite_ipif which interraces intc_core to AXI.
-------------------------------------------------------------------------
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------
-- Library axi_intc_v4_1_9 is used because it contains the intc_core.
-- The complete interrupt controller logic is designed in intc_core.
-------------------------------------------------------------------------
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.intc_core;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- System Parameter
-- C_FAMILY -- Target FPGA family
-- AXI Parameters
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- Intc Parameters
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - Active Low Reset
-- Axi interface signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Intc Interface Signals
-- intr -- Input Interruput request
-- irq -- Output Interruput request
-- processor_clk -- in put same as processor clock
-- processor_rst -- in put same as processor reset
-- processor_ack -- input Connected to processor ACK
-- interrupt_address -- output Connected to processor interrupt address pins
-- interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity axi_intc is
generic
(
-- System Parameter
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_intc_inst";
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 9; -- 9
C_S_AXI_DATA_WIDTH : integer := 32;
-- Intc Parameters
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 1;
C_HAS_FAST : integer range 0 to 1 := 0;
-- The below parameter is unused in RTL but required in Vivado Native
C_ENABLE_ASYNC : integer range 0 to 1 := 0; --not used for EDK, used only for Vivado
--
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
--
);
port
(
-- system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi interface signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector (8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Intc Interface signals
intr : in std_logic_vector(C_NUM_INTR_INPUTS-1 downto 0);
processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- MB rst, reset from MicroBlaze
irq : out std_logic;
processor_ack : in std_logic_vector(1 downto 0);
interrupt_address : out std_logic_vector(31 downto 0);
-- Cascade Interface signals
irq_in : in std_logic;
interrupt_address_in : in std_logic_vector(31 downto 0);
processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of S_AXI_ACLK : signal is "10000";
ATTRIBUTE MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
-- SIGIS attribute for specifying clocks,interrupts,resets for EDK
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of axi_intc : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of axi_intc : entity is "PERIPHERAL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of axi_intc : entity is "VHDL";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of axi_intc : entity is "HDL";
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST of axi_intc : entity is "TRUE";
ATTRIBUTE RUN_NGCBUILD : string;
ATTRIBUTE RUN_NGCBUILD of axi_intc : entity is "TRUE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of S_AXI_ACLK : signal is "Clk";
ATTRIBUTE SIGIS of S_AXI_ARESETN : signal is "Rstn";
end axi_intc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_intc is
---------------------------------------------------------------------------
-- Constant Declarations
---------------------------------------------------------------------------
function calc_num_intr_inputs return integer is
begin -- function calc_num_intr_inputs
if C_EN_CASCADE_MODE = 1 and C_NUM_INTR_INPUTS = 31 then
return 32; -- add input for cascaded interrupt from Irq_in
end if;
return C_NUM_INTR_INPUTS;
end function calc_num_intr_inputs;
constant ZERO_ADDR_PAD : std_logic_vector(31 downto 0)
:= (others => '0');
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := (0 => 1);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= (
ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & (X"00000000" or X"0000003F"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"00000100"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"0000017F") --- changed the high address
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (16, 1); --- changed no. of chip enables
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000017F"; --- changed min memory size required
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 8;
constant RESET_ACTIVE : std_logic := '0';
constant NUM_INTR_INPUTS : integer := calc_num_intr_inputs;
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal register_addr : std_logic_vector(6 downto 0); -- changed
signal read_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal write_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector((
(ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal word_access : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int_d1 : std_logic;
signal ip2bus_wrack_int_d1 : std_logic;
signal ip2bus_rdack_prev2 : std_logic;
signal ip2bus_wrack_prev2 : std_logic;
signal intr_i : std_logic_vector(NUM_INTR_INPUTS-1 downto 0);
function Or128_vec2stdlogic (vec_in : std_logic_vector) return std_logic is
variable or_out : std_logic := '0';
begin
for i in 0 to 16 loop
or_out := vec_in(i) or or_out;
end loop;
return or_out;
end function Or128_vec2stdlogic;
------------------------------------------------------------------------------
-----
begin
-----
assert C_NUM_SW_INTR + C_NUM_INTR_INPUTS <= 32
report "C_NUM_SW_INTR + C_NUM_INTR_INPUTS must be less than or equal to 32"
severity error;
register_addr <= bus2ip_addr(8 downto 2); -- changed the range as no. of register increased
--- Internal ack signals
ip2bus_rdack_int <= Or128_vec2stdlogic(bus2ip_rdce); -- changed, utilized function as no. chip enables increased
ip2bus_wrack_int <= Or128_vec2stdlogic(bus2ip_wrce); -- changed, utilized function as no. chip enables increased
-- Error signal generation
word_access <= bus2ip_be(0) and
bus2ip_be(1) and
bus2ip_be(2) and
bus2ip_be(3);
ip2bus_error <= not word_access;
-- Intr input signal generation
Combine_Intr: process (Intr, Irq_in) is
begin -- process Combine_Intr
intr_i(C_NUM_INTR_INPUTS - 1 downto 0) <= Intr;
if C_EN_CASCADE_MODE = 1 and C_NUM_INTR_INPUTS = 31 then
intr_i(NUM_INTR_INPUTS - 1) <= Irq_in;
end if;
end process Combine_Intr;
--------------------------------------------------------------------------
-- Process DACK_DELAY_P for generating write and read data acknowledge
-- signals.
--------------------------------------------------------------------------
DACK_DELAY_P: process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk='1' then
if bus2ip_resetn = RESET_ACTIVE then
ip2bus_rdack_int_d1 <= '0';
ip2bus_wrack_int_d1 <= '0';
ip2bus_rdack <= '0';
ip2bus_wrack <= '0';
else
ip2bus_rdack_int_d1 <= ip2bus_rdack_int;
ip2bus_wrack_int_d1 <= ip2bus_wrack_int;
ip2bus_rdack <= ip2bus_rdack_prev2;
ip2bus_wrack <= ip2bus_wrack_prev2;
end if;
end if;
end process DACK_DELAY_P;
-- Detecting rising edge by creating one shot
ip2bus_rdack_prev2 <= ip2bus_rdack_int and (not ip2bus_rdack_int_d1);
ip2bus_wrack_prev2 <= ip2bus_wrack_int and (not ip2bus_wrack_int_d1);
---------------------------------------------------------------------------
-- Component Instantiations
---------------------------------------------------------------------------
-----------------------------------------------------------------
-- Instantiating intc_core from axi_intc_v4_1_9
-----------------------------------------------------------------
INTC_CORE_I : entity axi_intc_v4_1_9.intc_core
generic map
(
C_FAMILY => C_FAMILY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_INTR_INPUTS => NUM_INTR_INPUTS,
C_NUM_SW_INTR => C_NUM_SW_INTR,
C_KIND_OF_INTR => C_KIND_OF_INTR,
C_KIND_OF_EDGE => C_KIND_OF_EDGE,
C_KIND_OF_LVL => C_KIND_OF_LVL,
C_ASYNC_INTR => C_ASYNC_INTR,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HAS_IPR => C_HAS_IPR,
C_HAS_SIE => C_HAS_SIE,
C_HAS_CIE => C_HAS_CIE,
C_HAS_IVR => C_HAS_IVR,
C_HAS_ILR => C_HAS_ILR,
C_IRQ_IS_LEVEL => C_IRQ_IS_LEVEL,
C_IRQ_ACTIVE => C_IRQ_ACTIVE,
C_DISABLE_SYNCHRONIZERS => C_DISABLE_SYNCHRONIZERS,
C_MB_CLK_NOT_CONNECTED => C_MB_CLK_NOT_CONNECTED,
C_HAS_FAST => C_HAS_FAST,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE,
--
C_EN_CASCADE_MODE => C_EN_CASCADE_MODE,
C_CASCADE_MASTER => C_CASCADE_MASTER
--
)
port map
(
-- Intc Interface Signals
Clk => bus2ip_clk,
Rst_n => bus2ip_resetn,
Intr => intr_i,
Reg_addr => register_addr,
Bus2ip_rdce => bus2ip_rdce,
Bus2ip_wrce => bus2ip_wrce,
Wr_data => write_data,
Rd_data => read_data,
Processor_clk => processor_clk,
Processor_rst => processor_rst,
Irq => Irq,
Processor_ack => processor_ack,
Interrupt_address => interrupt_address,
Interrupt_address_in => interrupt_address_in,
Processor_ack_out => processor_ack_out
);
-----------------------------------------------------------------
--Instantiating axi_lite_ipif from axi_lite_ipif_v3_0_4
-----------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
--System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
-- AXI interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- Controls to the IP/IPIF modules
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
Bus2IP_Data => write_data,
IP2Bus_Data => read_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error
);
end imp;
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apache-2.0
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