repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
its2mc/PCFG
|
tw_8254_cnt.vhd
|
1
|
5148
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TW_8254_CNT is
Port ( m_clk : in STD_LOGIC;
m_reset : in STD_LOGIC;
m_gate : in STD_LOGIC;
m_out : out STD_LOGIC;
m_data : in STD_LOGIC_VECTOR (7 downto 0);
m_cw : in std_logic;
m_wr_b : in STD_LOGIC);
end TW_8254_CNT;
architecture Behavioral of TW_8254_CNT is
signal s_cw : std_logic;
signal s_wr : std_logic;
signal s_out2 : std_logic;
signal s_out3 : std_logic;
signal s_gate : std_logic;
signal s_wr_M : std_logic;
signal s_wr_L : std_logic;
signal s_wr_LM : std_logic;
signal s_wr_wait : std_logic;
signal s_mode : std_logic; -- 0 : mode2, 1 : mode3
signal s_REG : std_logic_vector(15 downto 0);
signal s_CNT2 : std_logic_vector(15 downto 0);
signal s_CNT3_1 : std_logic_vector(15 downto 0);
signal s_CNT3_2 : std_logic_vector(15 downto 0);
signal s_CNT3_1_rst : STD_LOGIC_VECTOR(15 downto 0);
signal s_CNT3_2_rst : STD_LOGIC_VECTOR(15 downto 0);
signal s_even : std_logic;
signal s_CNT3 : std_logic_vector(15 downto 0);
signal s_CNT3_U : std_logic_vector(14 downto 0);
signal s_CNT3_D : std_logic_vector(14 downto 0);
signal s_CNT3_UD : std_logic;
signal s_temp1 : std_logic;
signal s_temp2 : std_logic;
constant c_0 : std_logic_vector(15 downto 0):=(others=>'0');
constant c_1 : std_logic_vector(15 downto 0):=(0=>'1',others=>'0');
constant c_1_2 : std_logic_vector(14 downto 0) :=(0=>'1',others=>'0');
constant c_0_2 : std_logic_vector(14 downto 0) :=(others=>'0');
begin
-- signal / port
s_gate <= m_gate;
s_cw <= m_cw;
m_out <= s_out2 when s_mode='0' and s_gate='1' else
s_out3 when s_mode='1' and s_gate='1' else '1';
s_wr <= not m_wr_b;
-- control LSB, MSB reg ( not for control word )
process(s_wr,m_reset)
begin
if m_reset='1' then
s_REG(15 downto 8) <= (8=>'1',others=>'0');
s_REG(7 downto 0) <= conv_std_logic_vector(4,8);
s_wr_wait <= '0';
elsif rising_edge(s_wr) then
if s_cw='0' then
s_wr_wait <='0';
if s_wr_L='1' and s_wr_LM='0' then
s_REG(7 downto 0) <= m_data;
elsif s_wr_M='1' and s_wr_LM='0' then
s_REG(15 downto 8) <= m_data;
elsif s_wr_LM='1' and s_wr_wait='0' then
s_REG(7 downto 0) <= m_data;
s_wr_wait<='1';
elsif s_wr_LM='1' and s_wr_wait='1' then
s_REG(15 downto 8) <= m_data;
end if;
end if;
end if;
end process;
-- control mode and write command
process(m_reset,s_wr)
begin
if m_reset='1' then
s_mode <= '0'; -- default mode : rate gen.
s_wr_L <='0';
s_wr_M <='0';
elsif rising_edge(s_wr) then
if s_cw='1' then
s_mode <= m_data(1);
s_wr_L <= m_data(4);
s_wr_M <= m_data(5);
end if;
end if;
end process;
s_wr_LM <= '1' when s_wr_L='1' and s_wr_M='1' else '0';
-----------------------------------------------------------------------------
-- MODE 2
process(m_reset,m_clk)
begin
if m_reset='1' then
s_CNT2 <= "0000000100000100";
elsif falling_edge(m_clk) then
if s_gate = '1' and s_mode='0' then
s_CNT2 <= s_CNT2 - '1' ;
if s_CNT2=c_1 then
s_CNT2<=s_REG;
end if;
end if;
end if;
end process;
s_out2 <= '0' when s_CNT2=c_1 OR (s_mode='0' and (s_REG=c_1 OR s_REG=c_0)) else '1';
------------------------------------------------------------------------------
-- MODE 3
s_CNT3_1 <= s_REG + '1';
s_CNT3_2 <= s_REG - '1';
s_CNT3_1_rst <= x"0105";
s_CNT3_2_rst <= x"0103";
s_even <= s_REG(0); -- 1 : odd, 0 : even
process(m_reset,m_clk)
begin
if falling_edge(m_clk) then
if m_reset='1' then
s_CNT3 <= x"0104";--s_REG;
s_CNT3_UD <= '1';
if s_even='1' then
s_CNT3_U <= s_CNT3_1_rst(15 downto 1);
s_CNT3_D <= s_CNT3_2_rst(15 downto 1);
else
s_CNT3_U <= ("000"&x"082");--s_REG(15 downto 1);
s_CNT3_D <= ("000"&x"082");--s_REG(15 downto 1);
end if;
elsif s_gate='1' and s_even='1' and s_mode='1' then -- odd
s_CNT3_D <= s_CNT3_D - 1;
s_CNT3_UD <='0';
if s_CNT3_D = c_1_2 and s_CNT3_U = c_0_2 then
s_CNT3_U <= s_CNT3_1(15 downto 1);
s_CNT3_D <= s_CNT3_2(15 downto 1);
elsif s_CNT3_D = c_1_2 then
s_CNT3_U <= s_CNT3_U - 1;
s_CNT3_D <= c_1_2(14 downto 0);
s_CNT3_UD <='1';
end if;
elsif s_gate='1' and s_even='0' and s_mode='1' then -- even
s_CNT3_D <= s_CNT3_D - 1;
s_CNT3_UD <='0';
if s_CNT3_U = c_0_2 then
s_CNT3_U <= s_REG(15 downto 1);
s_CNT3_D <= s_REG(15 downto 1);
elsif s_CNT3_D = c_1_2 then
s_CNT3_U <= s_CNT3_U - 1;
s_CNT3_D <= c_1_2;
s_CNT3_UD <='1';
end if;
end if;
end if;
end process;
s_out3 <= m_clk when ((s_REG=c_1 OR s_REG=c_0) and s_mode='1') else s_CNT3_UD;
end Behavioral;
|
apache-2.0
|
ariefsetya/copasin
|
public/assets/ace-builds-master/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
apache-2.0
|
open-power/snap
|
actions/hdl_nvme_example/hw/action_axi_slave.vhd
|
1
|
27032
|
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY action_axi_slave IS
GENERIC (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
PORT (
reg_0x10_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x14_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x20_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x30_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x34_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x38_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x3c_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x40_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x44_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x48_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x4c_req_error_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
reg_0x4c_nvme_error_i : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
reg_0x4c_completion_i : IN STD_LOGIC_VECTOR( 4 DOWNTO 0);
reg_0x4c_rd_strobe_o : OUT STD_LOGIC;
reg_0x50_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
reg_0x54_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
int_enable_o : OUT STD_LOGIC;
app_start_o : OUT STD_LOGIC;
app_done_i : IN STD_LOGIC;
app_ready_i : IN STD_LOGIC;
app_idle_i : IN STD_LOGIC;
-- AXI Slave interface
-- Global Clock Signal
S_AXI_ACLK : IN STD_LOGIC;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : IN STD_LOGIC;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : IN STD_LOGIC;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : OUT STD_LOGIC;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : IN STD_LOGIC_VECTOR((C_S_AXI_DATA_WIDTH/8)-1 DOWNTO 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : IN STD_LOGIC;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : OUT STD_LOGIC;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : OUT STD_LOGIC;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : IN STD_LOGIC;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : IN STD_LOGIC;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : OUT STD_LOGIC;
-- Read data (issued by slave)
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : OUT STD_LOGIC;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : IN STD_LOGIC
);
END action_axi_slave;
ARCHITECTURE action_axi_slave OF action_axi_slave IS
-- AXI4LITE signals
SIGNAL axi_awaddr : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL axi_awready : STD_LOGIC;
SIGNAL axi_wready : STD_LOGIC;
SIGNAL axi_bresp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL axi_bvalid : STD_LOGIC;
SIGNAL axi_araddr : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL axi_arready : STD_LOGIC;
SIGNAL axi_rdata : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL axi_rresp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL axi_rvalid : STD_LOGIC;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
CONSTANT ADDR_LSB : INTEGER := (C_S_AXI_DATA_WIDTH/32)+ 1;
CONSTANT OPT_MEM_ADDR_BITS : INTEGER := 6;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 16
SIGNAL slv_reg0 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg0_new : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg1 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg2 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg3 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg8 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg12 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg13 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg14 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg15 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg16 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg17 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg18 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg19 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL slv_reg_rden : STD_LOGIC;
SIGNAL slv_reg_wren : STD_LOGIC;
SIGNAL reg_data_out : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL byte_index : INTEGER;
SIGNAL idle_q : STD_LOGIC;
SIGNAL app_start_q : STD_LOGIC;
SIGNAL app_done_q : STD_LOGIC;
BEGIN
-- I/O Connections assignments
int_enable_o <= slv_reg1(0);
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_awready = '0' AND S_AXI_AWVALID = '1' AND S_AXI_WVALID = '1') THEN
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
ELSE
axi_awready <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_awready <= '0';
END IF;
END IF;
END PROCESS;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_awready = '0' AND S_AXI_AWVALID = '1' AND S_AXI_WVALID = '1') THEN
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_awaddr <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_wready = '0' AND S_AXI_WVALID = '1' AND S_AXI_AWVALID = '1') THEN
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
ELSE
axi_wready <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_wready <= '0';
END IF;
END IF;
END PROCESS;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready AND S_AXI_WVALID AND axi_awready AND S_AXI_AWVALID ;
PROCESS (S_AXI_ACLK)
VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0);
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB);
IF (slv_reg_wren = '1') THEN
CASE loc_addr IS
WHEN b"000000" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 0
slv_reg0(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"000001" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 1
slv_reg1(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"000010" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 2
slv_reg2(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"000011" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 3
slv_reg3(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001000" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 8
slv_reg8(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001100" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 12
slv_reg12(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001101" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 13
slv_reg13(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001110" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 14
slv_reg14(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"001111" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 15
slv_reg15(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"010000" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 16
slv_reg16(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"010001" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 17
slv_reg17(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"010010" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 18
slv_reg18(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN b"010011" =>
FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP
IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN
-- Respective byte enables are asserted as per write strobes
-- slave register 19
slv_reg19(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8);
END IF;
END LOOP;
WHEN OTHERS =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg8 <= slv_reg8;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
END CASE;
END IF;
IF app_start_q = '1' THEN
slv_reg0(0) <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
slv_reg0 <= (OTHERS => '0');
slv_reg1 <= (OTHERS => '0');
slv_reg2 <= (OTHERS => '0');
slv_reg3 <= (OTHERS => '0');
slv_reg8 <= (OTHERS => '0');
slv_reg12 <= (OTHERS => '0');
slv_reg13 <= (OTHERS => '0');
slv_reg14 <= (OTHERS => '0');
slv_reg15 <= (OTHERS => '0');
slv_reg16 <= (OTHERS => '0');
slv_reg17 <= (OTHERS => '0');
slv_reg18 <= (OTHERS => '0');
slv_reg19 <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_awready = '1' AND S_AXI_AWVALID = '1' AND axi_wready = '1' AND S_AXI_WVALID = '1' AND axi_bvalid = '0' ) THEN
axi_bvalid <= '1';
axi_bresp <= "00";
ELSIF (S_AXI_BREADY = '1' AND axi_bvalid = '1') THEN --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
END IF;
END IF;
END PROCESS;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_arready = '0' AND S_AXI_ARVALID = '1') THEN
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
ELSE
axi_arready <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_arready <= '0';
axi_araddr <= (OTHERS => '1');
END IF;
END IF;
END PROCESS;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
IF (axi_arready = '1' AND S_AXI_ARVALID = '1' AND axi_rvalid = '0') THEN
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
ELSIF (axi_rvalid = '1' AND S_AXI_RREADY = '1') THEN
-- Read data is accepted by the master
axi_rvalid <= '0';
END IF;
IF S_AXI_ARESETN = '0' THEN
axi_rvalid <= '0';
axi_rresp <= "00";
END IF;
END IF;
END PROCESS;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready AND S_AXI_ARVALID AND (NOT axi_rvalid) ;
PROCESS (slv_reg0_new, slv_reg1, slv_reg2, slv_reg3, reg_0x10_i, reg_0x14_i, slv_reg8, slv_reg12,
slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, reg_0x48_i, slv_reg19, axi_araddr,
reg_0x4c_completion_i, reg_0x4c_req_error_i, reg_0x4c_nvme_error_i,
reg_0x50_i, reg_0x54_i)
VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0);
VARIABLE loc_idx : integer RANGE 0 TO 511;
BEGIN
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB);
loc_idx := to_integer(unsigned(axi_araddr(5 DOWNTO 2))) * 32;
CASE loc_addr IS
WHEN b"000000" =>
reg_data_out <= slv_reg0_new; -- 0x00
WHEN b"000001" =>
reg_data_out <= slv_reg1; -- 0x04
WHEN b"000010" =>
reg_data_out <= slv_reg2; -- 0x08
WHEN b"000011" =>
reg_data_out <= slv_reg3; -- 0x0c
WHEN b"000100" =>
reg_data_out <= reg_0x10_i; -- 0x10
WHEN b"000101" =>
reg_data_out <= reg_0x14_i; -- 0x14
WHEN b"001000" =>
reg_data_out <= slv_reg8; -- 0x20
WHEN b"001100" =>
reg_data_out <= slv_reg12; -- 0x30
WHEN b"001101" =>
reg_data_out <= slv_reg13; -- 0x34
WHEN b"001110" =>
reg_data_out <= slv_reg14; -- 0x38
WHEN b"001111" =>
reg_data_out <= slv_reg15; -- 0x3c
WHEN b"010000" =>
reg_data_out <= slv_reg16; -- 0x40
WHEN b"010001" =>
reg_data_out <= slv_reg17; -- 0x44
WHEN b"010010" =>
reg_data_out <= reg_0x48_i; -- 0x48 : Tracking slots with NVMe read error (bits 31:16) / NVMe write error (bits 15:0)
WHEN b"010011" =>
reg_data_out <= reg_0x4c_req_error_i & slv_reg19(15 DOWNTO 11) & reg_0x4c_nvme_error_i & slv_reg19(7 DOWNTO 5) & reg_0x4c_completion_i; -- 0x4c
WHEN b"010100" =>
reg_data_out <= reg_0x50_i; -- 0x50 : Request tracking register
-- for slot in {0,...,15}:
-- bit slot+32 = '1' means: request from application for slot got initiated
-- bit is reset when the applications request is completed
-- bit slot = '1' means: request is an NVMe read request (NVMe writer request, otherwise)
WHEN b"010101" =>
reg_data_out <= reg_0x54_i; -- 0x54 : NVMe request / response register
-- for slot in {0,...,15}:
-- bit slot+32 = '1' means: request to Nvme host controller for slot initiated
-- bit is reset when the applications request is completed
-- bit slot = '1' means: response from Nvme host controler for slot arrived
-- bit is reset when the applications request is completed
-- WHEN b"010111" =>
-- reg_data_out <= reg_0x5c_i; -- 0x5c : NVMe host controller debug register 0x4c (snd tracking info)
-- -- for slot in {0,...,15}:
-- -- bit slot+32 = '1' means: request to Nvme drive for slot initiated (=>WRITE_SQ)
-- -- bit is reset when the drive signals receive of request
-- -- bit slot = '1' means: request to Nvme drive for slot completed (=>WRITE_SQ_DOORBELL)
-- -- bit is reset when the drive signals receive of request
WHEN OTHERS =>
reg_data_out <= (OTHERS => '0');
END CASE;
END PROCESS;
reg_0x4c_rd_strobe_o <= '1' WHEN slv_reg_rden = '1' AND axi_araddr(7 DOWNTO 0) = x"4c" ELSE '0';
-- Output register or memory read data
PROCESS( S_AXI_ACLK ) IS
BEGIN
IF (rising_edge (S_AXI_ACLK)) THEN
IF (slv_reg_rden = '1') THEN
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
END IF;
IF ( S_AXI_ARESETN = '0' ) THEN
axi_rdata <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
app_start_o <= app_start_q;
reg_0x20_o <= slv_reg8;
reg_0x30_o <= slv_reg12;
reg_0x34_o <= slv_reg13;
reg_0x38_o <= slv_reg14;
reg_0x3c_o <= slv_reg15;
reg_0x40_o <= slv_reg16;
reg_0x44_o <= slv_reg17;
PROCESS( S_AXI_ACLK ) IS
VARIABLE app_done_i_q : std_logic;
VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0);
BEGIN
IF (rising_edge (S_AXI_ACLK)) THEN
app_start_q <= app_start_q;
idle_q <= app_idle_i;
app_done_i_q := app_done_i;
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB);
-- clear app_done bit when register is read
IF slv_reg_rden = '1' AND loc_addr = "00000" THEN
app_done_q <= '0';
END IF;
IF (app_done_i_q = '0' AND app_done_i = '1') THEN
app_done_q <= '1';
END IF;
IF slv_reg0(0) = '1' THEN
app_start_q <= '1';
END IF;
IF idle_q = '1' AND app_idle_i = '0' THEN
app_start_q <= '0';
END IF;
IF ( S_AXI_ARESETN = '0' ) THEN
app_start_q <= '0';
app_done_q <= '0';
app_done_i_q := '0';
idle_q <= '0';
END IF;
END IF;
END PROCESS;
slv_reg0_new <= slv_reg0 (31 DOWNTO 4) & app_ready_i & idle_q & app_done_q & app_start_q ;
END action_axi_slave;
|
apache-2.0
|
VLSI-EDA/PoC-Examples
|
src/mem/sdram/memtest_s3esk_clockgen.vhdl
|
1
|
15781
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
--
-- Module: Clock Generator for Memory Test on Spartan-3E Starter Kit
--
-- Description:
-- ------------------------------------
-- DCM configuration for module 'memtest_s3esk'.
--
-- The DCMs dcm_mem* have either unstable input clocks upon configuration and/or
-- external feedback, and thus must be reset accordingly. So we do not use
-- the STARTUP_WAIT feature at all.
--
-- After startup the clocks are unstable. Thus, the logic
-- clocked by clk_* must be hold in reset until rst_* is deasserted.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
-------------------------------------------------------------------------------
-- Naming Conventions:
-- (Based on: Keating and Bricaud: "Reuse Methodology Manual")
--
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: all UPPERCASE
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- output of a register: "*_r"
-- asynchronous signal: "*_a"
-- pipelined or register delay signals: "*_p#"
-- data before being registered into register with the same name: "*_nxt"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- tristate internal signal "*_z"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
entity memtest_s3esk_clockgen is
port (
clk_in : in std_logic;
sd_ck_fb : in std_logic;
user_rst : in std_logic;
clk_sys : out std_logic;
clk_mem : out std_logic;
clk_mem_n : out std_logic;
clk_mem90 : out std_logic;
clk_mem90_n : out std_logic;
clk_memfb90 : out std_logic;
clk_memfb90_n : out std_logic;
rst_sys : out std_logic;
rst_mem : out std_logic;
rst_mem90 : out std_logic;
rst_mem180 : out std_logic;
rst_mem270 : out std_logic;
rst_memfb90 : out std_logic;
rst_memfb270 : out std_logic;
locked : out std_logic);
end memtest_s3esk_clockgen;
library unisim;
use unisim.VComponents.all;
architecture rtl of memtest_s3esk_clockgen is
-- input buffer
signal clk_in_bufo : std_logic;
signal sd_ck_fb_bufo : std_logic;
-- clock buffer inputs
signal clk_sys_bufi : std_logic;
signal clk_dv_bufi : std_logic;
signal clk_mem_bufi : std_logic;
signal clk_mem90_bufi : std_logic;
signal clk_memfb90_bufi : std_logic;
signal clk_memfb90_n_bufi : std_logic;
-- global clocks (internal signals)
signal clk_sys_i : std_logic;
signal clk_mem_i : std_logic;
signal clk_mem_n_i : std_logic;
signal clk_mem90_i : std_logic;
signal clk_mem90_n_i : std_logic;
signal clk_memfb90_i : std_logic;
signal clk_memfb90_n_i : std_logic;
-- dcm reset
signal dcm_mem_rst : std_logic;
signal dcm_memfb_rst : std_logic;
-- locked signals
signal dcm_sys_locked : std_logic;
signal dcm_mem_locked : std_logic;
signal dcm_mem90_locked : std_logic;
signal dcm_memfb_locked : std_logic;
-- reset synchronizers for clk_sys, clk_mem* and clk_memfb*
signal rst_sys_r : std_logic_vector(1 downto 0);
signal rst_mem_r : std_logic_vector(1 downto 0);
signal rst_mem90_r : std_logic_vector(1 downto 0);
signal rst_mem180_r : std_logic_vector(1 downto 0);
signal rst_mem270_r : std_logic_vector(1 downto 0);
signal rst_memfb90_r : std_logic_vector(1 downto 0);
signal rst_memfb270_r : std_logic_vector(1 downto 0);
-- internal version of output signals
signal locked_i : std_logic;
-- do reset
signal do_rst : std_logic;
begin
-----------------------------------------------------------------------------
-- 0. Input Clock buffer and system clock.
-----------------------------------------------------------------------------
clk_in_buf : IBUFG port map (
I => clk_in,
O => clk_in_bufo);
-----------------------------------------------------------------------------
-- 1. System clock.
-----------------------------------------------------------------------------
dcm_sys : DCM_SP
generic map (
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0, -- period of input clock (50 Mhz)
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "NONE",
PHASE_SHIFT => 0,
CLKDV_DIVIDE => 2.0,
FACTORY_JF => X"C080") -- ?
port map (
CLK0 => clk_sys_bufi,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => clk_dv_bufi,
CLKFX => open,
CLKFX180 => open,
LOCKED => dcm_sys_locked,
PSDONE => open,
STATUS => open,
CLKFB => clk_sys_i,
CLKIN => clk_in_bufo,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => '0');
clk_sys_buf : BUFG port map (
I => clk_sys_bufi,
O => clk_sys_i);
clk_sys <= clk_sys_i;
-- clk_sys is stable as soon as GWE (Global Write Enable) is asserted.
-- See documentation in file header.
-----------------------------------------------------------------------------
-- 2. Generate memory clocks.
--
-- The reset logic for this DCM has to wait until clk_sys gets stable.
-- The reset must be asserted for three valid CLKIN cycles or longer.
--
-- IMPORTANT NOTE:
-- Yes dcm_mem and dcm_mem90 might be merged, if doubled input clock is
-- generated by dcm_sys and then clk0 and clk90 DCM outputs are used. But
-- these requires a DCM input clock of 100 MHz, which is out of specification
-- for Spartan-3E stepping 0.
-----------------------------------------------------------------------------
dcm_mem_rst_gen : SRLC16E
generic map (
INIT => x"FFFF") -- hold reset for 16 clock cycles
port map (
clk => clk_sys_i,
ce => dcm_sys_locked, -- wait until clk_sys is stable
d => '0', -- finished
a0 => '1',
a1 => '1',
a2 => '1',
a3 => '1',
q => open,
q15 => dcm_mem_rst);
dcm_mem : DCM_SP
generic map (
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0, -- 50 MHz
DLL_FREQUENCY_MODE => "LOW", -- no specification found in manual
DUTY_CYCLE_CORRECTION => FALSE, -- already 50 %
CLK_FEEDBACK => "2X",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "NONE",
PHASE_SHIFT => 0,
FACTORY_JF => X"C080") -- ?
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk_mem_bufi,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => dcm_mem_locked,
PSDONE => open,
STATUS => open,
CLKFB => clk_mem_i,
CLKIN => clk_sys_i,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => dcm_mem_rst);
dcm_mem90 : DCM_SP
generic map (
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0, -- 50 MHz
DLL_FREQUENCY_MODE => "LOW", -- no specification found in manual
DUTY_CYCLE_CORRECTION => FALSE, -- already 50 %
CLK_FEEDBACK => "2X",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED",
PHASE_SHIFT => 32, -- 90° @ CLK2x
FACTORY_JF => X"C080") -- ?
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk_mem90_bufi,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => dcm_mem90_locked,
PSDONE => open,
STATUS => open,
CLKFB => clk_mem90_i,
CLKIN => clk_sys_i,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => dcm_mem_rst);
clk_mem_buf : BUFG port map (
I => clk_mem_bufi,
O => clk_mem_i);
clk_mem_n_i <= not clk_mem_i;
clk_mem90_buf : BUFG port map (
I => clk_mem90_bufi,
O => clk_mem90_i);
clk_mem90_n_i <= not clk_mem90_i;
clk_mem <= clk_mem_i;
clk_mem_n <= clk_mem_n_i;
clk_mem90 <= clk_mem90_i;
clk_mem90_n <= clk_mem90_n_i;
-----------------------------------------------------------------------------
-- 3. Synchronized read clock for DDR-SDRAM controller.
--
-- The reset logic for this DCM has to wait until clk_mem gets stable.
-- The reset must be asserted for three valid CLKIN cycles or longer.
-- Due to the external feedback, the number of cycles should be greater.
-----------------------------------------------------------------------------
dcm_memfb_rst_gen : SRLC16E
generic map (
INIT => x"FFFF") -- hold reset for 16 clock cycles
port map (
clk => clk_mem_i,
ce => dcm_mem_locked, -- wait until clk_mem is stable
d => '0', -- finished
a0 => '1',
a1 => '1',
a2 => '1',
a3 => '1',
q => open,
q15 => dcm_memfb_rst);
sd_ck_fb_buf : IBUFG port map (
I => sd_ck_fb,
O => sd_ck_fb_bufo);
dcm_memfb : DCM_SP
generic map (
CLKIN_DIVIDE_BY_2 => TRUE,
CLKIN_PERIOD => 10.0, -- period of input clock (100 Mhz)
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => FALSE, -- already 50 %
CLK_FEEDBACK => "2X",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- no deskew
CLKOUT_PHASE_SHIFT => "FIXED",
PHASE_SHIFT => 32+5, -- 90° +/- x @ CLK2X
FACTORY_JF => X"C080")
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk_memfb90_bufi,
CLK2X180 => clk_memfb90_n_bufi,
CLK90 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => dcm_memfb_locked,
PSDONE => open,
STATUS => open,
CLKFB => clk_memfb90_i,
CLKIN => sd_ck_fb_bufo,
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => dcm_memfb_rst);
clk_memfb90_buf : BUFG port map (
I => clk_memfb90_bufi,
O => clk_memfb90_i);
clk_memfb90_n_buf : BUFG port map (
I => clk_memfb90_n_bufi,
O => clk_memfb90_n_i);
clk_memfb90 <= clk_memfb90_i;
clk_memfb90_n <= clk_memfb90_n_i;
-----------------------------------------------------------------------------
-- 4. Locked & Resets
--
-- Coordinated Reset removal:
-- - First, remove reset of clk_mem*, because it always waits for commands
-- before it writes anything to the read FIFO.
-- - Second, remove reset from clk_sys because it writes to the command FIFO
-- as soon as possible. But at this time, the rst_rd from that FIFO must
-- not be asserted, so that the write_addr is correctly transfered between
-- the clock domains (gray-encoding is kept).
-----------------------------------------------------------------------------
locked_i <= dcm_sys_locked and dcm_mem_locked and dcm_mem90_locked and dcm_memfb_locked;
locked <= locked_i;
do_rst <= (not locked_i) or user_rst;
-- synchronize locked_i with clock domain clk_sys
process (do_rst, clk_sys_i)
begin -- process
if do_rst = '1' then
rst_sys_r <= (others => '1');
elsif rising_edge(clk_sys_i) then
rst_sys_r(0) <= rst_mem_r(rst_mem_r'left); -- release as second
rst_sys_r(rst_sys_r'left downto 1) <=
rst_sys_r(rst_sys_r'left-1 downto 0);
end if;
end process;
rst_sys <= rst_sys_r(rst_sys_r'left);
-- synchronize locked_i with clock domain clk_mem
process (do_rst, clk_mem_i)
begin -- process
if do_rst = '1' then
rst_mem_r <= (others => '1');
elsif rising_edge(clk_mem_i) then
rst_mem_r(0) <= '0';
rst_mem_r(rst_mem_r'left downto 1) <=
rst_mem_r(rst_mem_r'left-1 downto 0);
end if;
end process;
rst_mem <= rst_mem_r(rst_mem_r'left);
-- synchronize locked_i with clock domain clk_mem90
process (do_rst, clk_mem90_i)
begin -- process
if do_rst = '1' then
rst_mem90_r <= (others => '1');
elsif rising_edge(clk_mem90_i) then
rst_mem90_r(0) <= '0';
rst_mem90_r(rst_mem90_r'left downto 1) <=
rst_mem90_r(rst_mem90_r'left-1 downto 0);
end if;
end process;
rst_mem90 <= rst_mem90_r(rst_mem90_r'left);
-- synchronize locked_i with clock domain clk_mem_n
process (do_rst, clk_mem_n_i)
begin -- process
if do_rst = '1' then
rst_mem180_r <= (others => '1');
elsif falling_edge(clk_mem_n_i) then
rst_mem180_r(0) <= '0';
rst_mem180_r(rst_mem180_r'left downto 1) <=
rst_mem180_r(rst_mem180_r'left-1 downto 0);
end if;
end process;
rst_mem180 <= rst_mem180_r(rst_mem180_r'left);
-- synchronize locked_i with clock domain clk_mem90_n
process (do_rst, clk_mem90_n_i)
begin -- process
if do_rst = '1' then
rst_mem270_r <= (others => '1');
elsif falling_edge(clk_mem90_n_i) then
rst_mem270_r(0) <= '0';
rst_mem270_r(rst_mem270_r'left downto 1) <=
rst_mem270_r(rst_mem270_r'left-1 downto 0);
end if;
end process;
rst_mem270 <= rst_mem270_r(rst_mem270_r'left);
-- synchronize locked_i with clock domain clk_memfb90
process (do_rst, clk_memfb90_i)
begin -- process
if do_rst = '1' then
rst_memfb90_r <= (others => '1');
elsif rising_edge(clk_memfb90_i) then
rst_memfb90_r(0) <= '0';
rst_memfb90_r(rst_memfb90_r'left downto 1) <=
rst_memfb90_r(rst_memfb90_r'left-1 downto 0);
end if;
end process;
rst_memfb90 <= rst_memfb90_r(rst_memfb90_r'left);
-- synchronize locked_i with clock domain clk_memfb90_n
process (do_rst, clk_memfb90_n_i)
begin -- process
if do_rst = '1' then
rst_memfb270_r <= (others => '1');
elsif rising_edge(clk_memfb90_n_i) then
rst_memfb270_r(0) <= '0';
rst_memfb270_r(rst_memfb270_r'left downto 1) <=
rst_memfb270_r(rst_memfb270_r'left-1 downto 0);
end if;
end process;
rst_memfb270 <= rst_memfb270_r(rst_memfb270_r'left);
end rtl;
|
apache-2.0
|
open-power/snap
|
hardware/hdl/core/mmio_to_axi_master.vhd
|
1
|
13299
|
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
USE work.psl_accel_types.ALL;
USE work.snap_core_types.all;
entity mmio_to_axi_master is
generic (
NUM_OF_ACTIONS : integer range 1 to 8 := 1
);
port (
clk : IN std_logic;
rst : IN std_logic;
mmx_d_i : IN MMX_D_T;
xmm_d_o : OUT XMM_D_T;
xk_d_o : out XK_D_T;
kx_d_i : in KX_D_T;
xj_c_o : out XJ_C_T;
jx_c_i : in JX_C_T;
xn_d_o : out XN_D_T;
nx_d_i : in NX_D_T
);
end mmio_to_axi_master;
architecture implementation of mmio_to_axi_master is
type fsm_t is ( AXI_IDLE, AXI_WR_DATA, AXI_WR_RESP, AXI_RD_REQ, AXI_RD_DATA );
signal axi_master_fsm_q : fsm_t ;
-- AXI4LITE signals
--write address valid
signal axi_awvalid_q : std_logic;
--write data valid
signal axi_wvalid_q : std_logic;
--read address valid
signal axi_arvalid_q : std_logic;
--read data acceptance
signal axi_rready_q : std_logic;
--write response acceptance
signal axi_bready_q : std_logic;
--write address
signal axi_address_q : std_logic_vector(31 downto 0);
signal saved_address_q : std_logic_vector(31 downto 0);
signal axi_wr_data_q : std_logic_vector(31 downto 0);
signal mmio_ack_q : std_logic;
signal mmio_rd_data_q : std_logic_vector(31 downto 0);
signal mmio_error_q : std_logic_vector( 1 downto 0);
signal poll_addr_q : std_logic_vector( 3 downto 0);
signal idle_vector_q : std_logic_vector( 4 downto 0);
signal poll_active_q : boolean;
signal poll_done_q : std_logic;
signal addr_32b_q : boolean;
signal wr_pending_q : std_logic;
signal rd_pending_q : std_logic;
signal max_actions : std_logic_vector(3 downto 0);
signal running_status_q : std_logic_vector(15 downto 0);
signal wr_pulse_q : std_logic;
signal wr_addr_q : std_logic_vector(17 downto 0);
signal start_bit_q : std_logic;
signal rvalid_q : std_logic;
signal nvme_q : std_logic;
begin
xk_d_o.M_AXI_AWADDR <= x"0000" & axi_address_q(15 downto 0);
xn_d_o.M_AXI_AWADDR <= axi_address_q;
--AXI 4 write data
xk_d_o.M_AXI_WDATA <= axi_wr_data_q;
xn_d_o.M_AXI_WDATA <= axi_wr_data_q;
xk_d_o.M_AXI_AWPROT <= "000";
xn_d_o.M_AXI_AWPROT <= "000";
xk_d_o.M_AXI_AWVALID <= axi_awvalid_q and not nvme_q;
xn_d_o.M_AXI_AWVALID <= axi_awvalid_q and nvme_q;
--Write Data(W)
xk_d_o.M_AXI_WVALID <= axi_wvalid_q and not nvme_q;
xn_d_o.M_AXI_WVALID <= axi_wvalid_q and nvme_q;
--Set all byte strobes in this example
xk_d_o.M_AXI_WSTRB <= "1111";
xn_d_o.M_AXI_WSTRB <= "1111";
--Write Response (B)
xk_d_o.M_AXI_BREADY <= axi_bready_q and not nvme_q;
xn_d_o.M_AXI_BREADY <= axi_bready_q and nvme_q;
--Read Address (AR)
xk_d_o.M_AXI_ARADDR <= x"0000" & axi_address_q(15 downto 0);
xn_d_o.M_AXI_ARADDR <= axi_address_q;
xk_d_o.M_AXI_ARVALID <= axi_arvalid_q and not nvme_q;
xn_d_o.M_AXI_ARVALID <= axi_arvalid_q and nvme_q;
xk_d_o.M_AXI_ARPROT <= "001";
xn_d_o.M_AXI_ARPROT <= "001";
--Read and Read Response (R)
xk_d_o.M_AXI_RREADY <= axi_rready_q and not nvme_q;
xn_d_o.M_AXI_RREADY <= axi_rready_q and nvme_q;
--Example design I/O
xmm_d_o.ack <= mmio_ack_q;
xmm_d_o.data <= mmio_rd_data_q;
xmm_d_o.error <= mmio_error_q;
max_actions <= std_logic_vector(to_unsigned(NUM_OF_ACTIONS - 1,4));
xj_c_o.valid <= idle_vector_q(4);
xj_c_o.action <= idle_vector_q(3 downto 0);
process(clk)
begin
if rising_edge(clk) then
rvalid_q <= '0';
mmio_ack_q <= '0';
if nvme_q = '0' then
mmio_rd_data_q <= kx_d_i.M_AXI_RDATA;
else
mmio_rd_data_q <= nx_d_i.M_AXI_RDATA;
end if;
if rst = '1' then
axi_master_fsm_q <= AXI_IDLE;
axi_awvalid_q <= '0';
axi_wvalid_q <= '0';
axi_bready_q <= '0';
axi_arvalid_q <= '0';
mmio_ack_q <= '0';
axi_rready_q <= '0';
poll_active_q <= false;
addr_32b_q <= false;
poll_addr_q <= (others => '0');
poll_done_q <= '0';
wr_pending_q <= '0';
rd_pending_q <= '0';
nvme_q <= '0';
else
if mmx_d_i.wr_strobe = '1' then
if mmx_d_i.addr(17 downto 16 ) = "11" then
-- indirect write
if mmx_d_i.addr(2) = '0' then
saved_address_q <= std_logic_vector(mmx_d_i.data);
mmio_ack_q <= '1';
else
wr_pending_q <= '1';
end if;
-- write address register
addr_32b_q <= true;
else
-- direct write
wr_pending_q <= '1';
addr_32b_q <= false;
end if;
end if;
if mmx_d_i.rd_strobe = '1' then
rd_pending_q <= '1';
if mmx_d_i.addr(17 downto 16 ) = "11" then
addr_32b_q <= true;
else
addr_32b_q <= false;
end if;
end if;
case axi_master_fsm_q is
when AXI_IDLE =>
if addr_32b_q then
axi_address_q <= saved_address_q;
-- 32 bit request goes always to the NVMe port
nvme_q <= '1';
else
axi_address_q <= std_logic_vector(mmx_d_i.addr);
if mmx_d_i.addr(29 downto 28) = "00" then
axi_address_q(17) <= '0';
end if;
-- address is eq or gt than 0x20000 --> is NVMe access
nvme_q <= mmx_d_i.addr(17);
end if;
axi_wr_data_q <= std_logic_vector(mmx_d_i.data);
axi_awvalid_q <= '0';
axi_wvalid_q <= '0';
axi_bready_q <= '0';
axi_arvalid_q <= '0';
axi_rready_q <= '0';
if wr_pending_q = '1' then
-- mmio write
axi_master_fsm_q <= AXI_WR_DATA;
axi_awvalid_q <= '1';
axi_wvalid_q <= '1';
elsif rd_pending_q = '1' then
-- mmio read
axi_master_fsm_q <= AXI_RD_REQ;
axi_arvalid_q <= '1';
elsif (running_status_q /= x"0000") and (jx_c_i.check_for_idle(to_integer(unsigned(poll_addr_q))) = '1') then
-- poll idle bit when no rd request is pending
axi_master_fsm_q <= AXI_RD_REQ;
axi_arvalid_q <= '1';
poll_active_q <= true;
axi_address_q <= x"0000" & poll_addr_q & x"000";
end if;
when AXI_RD_REQ =>
if(kx_d_i.M_AXI_ARREADY = '1' and nvme_q = '0') or (nx_d_i.M_AXI_ARREADY = '1' and nvme_q = '1') then
axi_master_fsm_q <= AXI_RD_DATA;
axi_arvalid_q <= '0';
axi_rready_q <= '1';
end if;
when AXI_RD_DATA =>
if (kx_d_i.M_AXI_RVALID = '1' and nvme_q = '0') or (nx_d_i.M_AXI_RVALID = '1' and nvme_q = '1') then
rvalid_q <= '1';
axi_master_fsm_q <= AXI_IDLE;
axi_rready_q <= '0';
if poll_active_q then
poll_active_q <= false;
if poll_addr_q = max_actions then
poll_addr_q <= (others => '0');
else
poll_addr_q <= poll_addr_q + '1';
end if;
else
mmio_ack_q <= '1';
rd_pending_q <= '0';
end if;
if nvme_q = '0' then
mmio_error_q <= kx_d_i.M_AXI_BRESP;
else
mmio_error_q <= nx_d_i.M_AXI_BRESP;
end if;
end if;
when AXI_WR_DATA =>
if (kx_d_i.M_AXI_AWREADY = '1' and nvme_q = '0') or (nx_d_i.M_AXI_AWREADY = '1' and nvme_q = '1') then
axi_awvalid_q <= '0';
end if;
if (kx_d_i.M_AXI_WREADY = '1' and nvme_q = '0') or (nx_d_i.M_AXI_WREADY = '1' and nvme_q = '1') then
axi_wvalid_q <= '0';
end if;
if axi_awvalid_q = '0' and axi_wvalid_q = '0' then
axi_master_fsm_q <= AXI_WR_RESP;
axi_bready_q <= '1';
end if;
when AXI_WR_RESP =>
if (kx_d_i.M_AXI_BVALID = '1' and nvme_q = '0') or (nx_d_i.M_AXI_BVALID = '1' and nvme_q = '1') then
axi_master_fsm_q <= AXI_IDLE;
axi_bready_q <= '0';
mmio_ack_q <= '1';
if nvme_q = '0' then
mmio_error_q <= kx_d_i.M_AXI_BRESP;
else
mmio_error_q <= nx_d_i.M_AXI_BRESP;
end if;
wr_pending_q <= '0';
end if;
when others => null;
end case;
if jx_c_i.check_for_idle(to_integer(unsigned(poll_addr_q))) = '0' then
if poll_addr_q = max_actions then
poll_addr_q <= (others => '0');
else
poll_addr_q <= poll_addr_q + '1';
end if;
end if;
end if; -- rst
end if; -- clk
end process;
-- process to observe which action is running
-- if an action goes to idle, notify job manager
process(clk)
begin
if rising_edge(clk) then
idle_vector_q(4) <= '0';
if rst = '1' then
running_status_q <= (others => '0');
else
wr_pulse_q <= mmx_d_i.wr_strobe;
wr_addr_q <= std_logic_vector(mmx_d_i.addr(17 downto 0));
start_bit_q <= std_logic(mmx_d_i.data(0));
if wr_pulse_q = '1' and wr_addr_q(11 downto 0) = x"000" and
wr_addr_q(17 downto 16) = "01" then
-- capture which action was started
running_status_q(to_integer(unsigned(wr_addr_q(15 downto 12)))) <= start_bit_q;
end if;
if mmio_rd_data_q(2) = '1' and axi_address_q(11 downto 0 ) = x"000" and
rvalid_q = '1' and
running_status_q(to_integer(unsigned(axi_address_q(15 downto 12)))) = '1' then
-- turn off the running bit
running_status_q(to_integer(unsigned(axi_address_q(15 downto 12)))) <= '0';
-- valid pulse
idle_vector_q(4) <= jx_c_i.check_for_idle(to_integer(unsigned(axi_address_q(15 downto 19))));
idle_vector_q(3 downto 0) <= axi_address_q(15 downto 12);
end if;
end if;
end if;
end process;
end implementation;
|
apache-2.0
|
sergev/vak-opensource
|
hardware/dlx/reg_3_out-behaviour.vhdl
|
1
|
1851
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: reg_3_out-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:14:21 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of register with three tri-state outputs.
--
architecture behaviour of reg_3_out is
begin
reg: process (d, latch_en, out_en1, out_en2, out_en3)
variable latched_value : dlx_word;
begin
if latch_en = '1' then
latched_value := d;
end if;
if out_en1 = '1' then
q1 <= latched_value after Tpd;
else
q1 <= null after Tpd;
end if;
if out_en2 = '1' then
q2 <= latched_value after Tpd;
else
q2 <= null after Tpd;
end if;
if out_en3 = '1' then
q3 <= latched_value after Tpd;
else
q3 <= null after Tpd;
end if;
end process reg;
end behaviour;
|
apache-2.0
|
sergev/vak-opensource
|
hardware/dlx/cache-behaviour.vhdl
|
1
|
10543
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: cache-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 22:13:32 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture for cache.
--
use work.bv_arithmetic.bv_to_natural,
work.bv_arithmetic.natural_to_bv;
architecture behaviour of cache is
begin -- behaviour
cache_behaviour : process
constant words_per_line : positive := line_size / 4;
constant number_of_sets : positive := cache_size / line_size / associativity;
subtype word_offset_range is natural range 0 to words_per_line-1;
subtype entry_index_range is natural range 0 to associativity-1;
subtype set_index_range is natural range 0 to number_of_sets-1;
type line is array (word_offset_range) of dlx_word;
type entry is record
tag : natural;
valid : boolean;
dirty : boolean;
data : line;
end record;
type store_array is array (set_index_range, entry_index_range) of entry;
variable store : store_array;
variable cpu_address : natural;
variable word_offset : word_offset_range;
variable set_index : set_index_range;
variable cpu_tag : natural;
variable entry_index : entry_index_range;
variable hit : boolean;
variable next_replacement_entry_index : entry_index_range := 0;
procedure do_read_hit is
begin
cpu_d <= store(set_index, entry_index).data(word_offset);
cpu_ready <= '1' after Tpd_clk_out;
wait until phi2 = '0';
cpu_d <= null after Tpd_clk_out;
cpu_ready <= '0' after Tpd_clk_out;
end do_read_hit;
procedure do_write_through is
begin
wait until phi1 = '1';
if reset = '1' then
return;
end if;
mem_a <= cpu_a after Tpd_clk_out;
mem_width <= cpu_width after Tpd_clk_out;
mem_d <= cpu_d after Tpd_clk_out;
mem_write <= '1' after Tpd_clk_out;
mem_burst <= '0' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
wait until mem_ready = '1' or reset = '1';
cpu_ready <= mem_ready after Tpd_clk_out;
wait until phi2 = '0';
mem_d <= null after Tpd_clk_out;
mem_write <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
cpu_ready <= '0' after Tpd_clk_out;
end do_write_through;
procedure do_write_hit is
begin
case cpu_width is
when width_word =>
store(set_index, entry_index).data(word_offset) := cpu_d;
when width_halfword =>
if cpu_a(1) = '0' then -- ms half word
store(set_index, entry_index).data(word_offset)(0 to 15) := cpu_d(0 to 15);
else -- ls half word
store(set_index, entry_index).data(word_offset)(16 to 23) := cpu_d(16 to 23);
end if;
when width_byte =>
if cpu_a(1) = '0' then -- ms half word
if cpu_a(0) = '0' then -- byte 0
store(set_index, entry_index).data(word_offset)(0 to 7) := cpu_d(0 to 7);
else -- byte 1
store(set_index, entry_index).data(word_offset)(8 to 15) := cpu_d(8 to 15);
end if;
else -- ls half word
if cpu_a(0) = '0' then -- byte 2
store(set_index, entry_index).data(word_offset)(16 to 23) := cpu_d(16 to 23);
else -- byte 3
store(set_index, entry_index).data(word_offset)(24 to 31) := cpu_d(24 to 31);
end if;
end if;
end case;
if write_strategy = copy_back then
store(set_index, entry_index).dirty := true;
end if;
--
-- if write_through cache, also update main memory
if write_strategy = write_through then
do_write_through;
else -- copy_back cache
cpu_ready <= '1' after Tpd_clk_out;
wait until phi2 = '0';
cpu_ready <= '0' after Tpd_clk_out;
end if;
end do_write_hit;
procedure copy_back_line is
variable next_address : natural;
variable old_word_offset : natural;
begin
next_address := (store(set_index, entry_index).tag * number_of_sets
+ set_index) * line_size;
wait until phi1 = '1';
if reset = '1' then
return;
end if;
mem_width <= width_word after Tpd_clk_out;
mem_write <= '1' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
mem_burst <= '1' after Tpd_clk_out;
old_word_offset := 0;
burst_loop : loop
if old_word_offset = words_per_line-1 then
mem_burst <= '0' after Tpd_clk_out;
end if;
mem_a <= natural_to_bv(next_address, mem_a'length) after Tpd_clk_out;
mem_d <= store(set_index, entry_index).data(old_word_offset) after Tpd_clk_out;
wait_loop : loop
wait until phi2 = '0';
exit burst_loop when reset = '1'
or (mem_ready = '1' and old_word_offset = words_per_line-1);
exit wait_loop when mem_ready = '1';
end loop wait_loop;
old_word_offset := old_word_offset + 1;
next_address := next_address + 4;
end loop burst_loop;
store(set_index, entry_index).dirty := false;
mem_d <= null after Tpd_clk_out;
mem_write <= '0' after Tpd_clk_out;
mem_enable <= '0' after Tpd_clk_out;
end copy_back_line;
procedure fetch_line is
variable next_address : natural;
variable new_word_offset : natural;
begin
next_address := (cpu_address / line_size) * line_size;
wait until phi1 = '1';
if reset = '1' then
return;
end if;
mem_width <= width_word after Tpd_clk_out;
mem_write <= '0' after Tpd_clk_out;
mem_enable <= '1' after Tpd_clk_out;
mem_burst <= '1' after Tpd_clk_out;
new_word_offset := 0;
burst_loop : loop
if new_word_offset = words_per_line-1 then
mem_burst <= '0' after Tpd_clk_out;
end if;
mem_a <= natural_to_bv(next_address, mem_a'length) after Tpd_clk_out;
wait_loop : loop
wait until phi2 = '0';
store(set_index, entry_index).data(new_word_offset) := mem_d;
exit burst_loop when reset = '1'
or (mem_ready = '1' and new_word_offset = words_per_line-1);
exit wait_loop when mem_ready = '1';
end loop wait_loop;
new_word_offset := new_word_offset + 1;
next_address := next_address + 4;
end loop burst_loop;
store(set_index, entry_index).valid := true;
store(set_index, entry_index).tag := cpu_tag;
store(set_index, entry_index).dirty := false;
mem_enable <= '0' after Tpd_clk_out;
end fetch_line;
procedure replace_line is
begin
-- first chose an entry using "random" number generator
entry_index := next_replacement_entry_index;
next_replacement_entry_index
:= (next_replacement_entry_index + 1) mod associativity;
if store(set_index, entry_index).dirty then
copy_back_line;
end if;
fetch_line;
end replace_line;
procedure do_read_miss is
begin
replace_line;
if reset = '1' then
return;
end if;
do_read_hit;
end do_read_miss;
procedure do_write_miss is
begin
-- if write_through cache, just update main memory
if write_strategy = write_through then
do_write_through;
else -- copy_back cache
replace_line;
if reset = '1' then
return;
end if;
do_write_hit;
end if;
end do_write_miss;
begin -- process cache_behaviour
-- reset: initialize outputs and the cache store valid bits
cpu_ready <= '0';
cpu_d <= null;
mem_enable <= '0';
mem_width <= width_word;
mem_write <= '0';
mem_burst <= '0';
mem_a <= X"00000000";
mem_d <= null;
for init_set_index in set_index_range loop
for init_entry_index in entry_index_range loop
store(init_set_index, init_entry_index).valid := false;
store(init_set_index, init_entry_index).dirty := false;
end loop; -- init_entry_index
end loop; -- init_set_index
--
loop
-- wait for a cpu request
wait until phi2 = '1' and cpu_enable = '1';
-- decode address
cpu_address := bv_to_natural(cpu_a);
word_offset := (cpu_address mod line_size) / 4;
set_index := (cpu_address / line_size) mod number_of_sets;
cpu_tag := cpu_address / line_size / number_of_sets;
-- check for hit
hit := false;
for lookup_entry_index in entry_index_range loop
if store(set_index, lookup_entry_index).valid
and store(set_index, lookup_entry_index).tag = cpu_tag then
hit := true;
entry_index := lookup_entry_index;
exit;
end if;
end loop; -- lookup_entry
--
if hit then
if cpu_write = '1' then
do_write_hit;
else
do_read_hit;
end if;
else
if cpu_write = '1' then
do_write_miss;
else
do_read_miss;
end if;
end if;
exit when reset = '1';
end loop;
-- loop exited on reset: wait until it goes inactive
-- then start again
wait until phi2 = '0' and reset = '0';
end process cache_behaviour;
end behaviour;
|
apache-2.0
|
sergev/vak-opensource
|
hardware/dlx/clock_gen-behaviour.vhdl
|
1
|
1605
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: clock_gen-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:29:05 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture body for clock generator
--
architecture behaviour of clock_gen is
constant clock_period : Time := 2*(Tpw+Tps);
begin
reset_driver:
reset <= '1', '0' after 2*clock_period + Tpw+Tps;
clock_driver : process
begin
phi1 <= '1', '0' after Tpw;
phi2 <= '1' after Tpw+Tps, '0' after Tpw+Tps+Tpw;
wait for clock_period;
end process clock_driver;
end behaviour;
|
apache-2.0
|
sergev/vak-opensource
|
hardware/vhdl/adder.vhdl
|
1
|
453
|
entity adder is
-- i0, i1 and the carry-in ci are inputs of the adder.
-- s is the sum output, co is the carry-out.
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end adder;
architecture rtl of adder is
begin
-- This full-adder architecture contains two concurrent assignment.
-- Compute the sum.
s <= i0 xor i1 xor ci;
-- Compute the carry.
co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
end rtl;
|
apache-2.0
|
paulino/digilentinc-peripherals
|
examples/test1/test1.vhd
|
1
|
3091
|
-------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
--
-- Description: Demo/test to run in Basys2 Digilent prototype board.
-- This test transfers the data set from switches to one peripheral when a
-- button is pressed:
-- - When BTN0 is pressed the switches value set is copied to the leds
-- - When BTN1 is pressed the switches value set is copied to the LSB display
-- - When BTN2 is pressed the switches value set is copied to the MSB display
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use work.digilent_peripherals_pk.all;
entity demo1_digilent is
port(
clk : in std_logic;
leds_out : out std_logic_vector (7 downto 0);
seg_out : out std_logic_vector (6 downto 0);
dp_out : out std_logic;
an_out : out std_logic_vector (3 downto 0);
sw_in : in std_logic_vector (7 downto 0);
btn_in : in std_logic_vector (3 downto 0)
);
end demo1_digilent;
architecture behavioral of demo1_digilent is
-- Internal signals
signal port_display_enable : std_logic;
signal port_switches_out : std_logic_vector(7 downto 0);
signal port_buttons_out : std_logic_vector(7 downto 0);
begin
-- leds
u_leds: port_leds_dig port map (
clk => clk,
enable => '1',
w => port_buttons_out(0),
port_in => port_switches_out,
leds_out => leds_out);
-- Display enabled when BTN1 ot BNT2 is pressed
port_display_enable <= port_buttons_out(1) or port_buttons_out(2);
u_display : port_display_dig port map (
clk => clk,
enable => port_display_enable,
digit_in => port_switches_out,
w_msb => port_buttons_out(2),
w_lsb => port_buttons_out(1),
seg_out => seg_out,
dp_out => dp_out,
an_out => an_out
);
-- Switches
u_switches : port_switches_dig port map(
clk => clk,
enable => '1',
r => '1',
port_out => port_switches_out,
switches_in => sw_in);
-- Buttons
u_buttons : port_buttons_dig port map(
clk => clk,
enable => '1',
r => '1',
port_out => port_buttons_out,
buttons_in => btn_in);
end behavioral;
|
apache-2.0
|
hoglet67/AtomGodilVideo
|
src/DCM/DCM2.vhd
|
1
|
2128
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM2 is
port (CLKIN_IN : in std_logic;
RST : in std_logic := '0';
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED : out std_logic
);
end DCM2;
architecture BEHAVIORAL of DCM2 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_MULTIPLY => 3,
CLKFX_DIVIDE => 7,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => RST,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => LOCKED,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
apache-2.0
|
hoglet67/AtomGodilVideo
|
src/DCM/DCMSID0.vhd
|
1
|
2128
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCMSID0 is
port (CLKIN_IN : in std_logic;
RST : in std_logic := '0';
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED : out std_logic
);
end DCMSID0;
architecture BEHAVIORAL of DCMSID0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => RST,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => LOCKED,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
apache-2.0
|
paulino/digilentinc-peripherals
|
rtl/port_display_dig.vhd
|
1
|
3582
|
-------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <[email protected]>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity port_display_dig is port ( clk : in std_logic;
enable : in std_logic;
digit_in : in std_logic_vector (7 downto 0);
w_msb : in std_logic;
w_lsb : in std_logic;
seg_out : out std_logic_vector (6 downto 0);
dp_out : out std_logic;
an_out : out std_logic_vector (3 downto 0));
end port_display_dig;
architecture Behavioral of port_display_dig is
signal counter : unsigned (23 downto 0);
signal counter4: unsigned (1 downto 0);
signal digit_lsb : std_logic_vector (7 downto 0);
signal digit_msb : std_logic_vector (7 downto 0);
signal conv_in : std_logic_vector (3 downto 0);
signal divider : std_logic;
begin
-- Writer process
write_proc : process (clk,enable)
begin
if falling_edge(clk) and enable='1' then
if w_msb='1' then
digit_msb <= digit_in;
end if;
if w_lsb='1' then
digit_lsb <= digit_in;
end if;
end if;
end process;
-- Clock divider process
div_proc : process (clk,counter)
begin
if falling_edge(clk) then
if(counter > x"0000ffff") then
counter <= x"000000";
divider <= '1';
else
counter <= counter + 1;
divider <= '0';
end if;
end if;
end process;
div2_proc : process(clk,divider)
begin
if falling_edge(clk) then
if divider='1' then
counter4 <= counter4 +1;
end if;
end if;
end process;
-- Anode control
mux_proc: process (counter4,digit_lsb,digit_msb)
begin
case counter4 is
when "00" =>
an_out <= "1110";
conv_in <= digit_lsb(3 downto 0);
when "01" =>
an_out <= "1101";
conv_in <= digit_lsb(7 downto 4);
when "10" =>
an_out <= "1011";
conv_in <= digit_msb(3 downto 0);
when others =>
an_out <= "0111";
conv_in <= digit_msb(7 downto 4);
end case;
end process;
-- Binary to seven seg converter
with conv_in select
seg_out <= "1000000" when "0000", --0
"1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when others; --F
dp_out <= '1';
end Behavioral;
|
apache-2.0
|
hoglet67/AtomGodilVideo
|
src/mouse/resolution_mouse_informer.vhd
|
1
|
8237
|
------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltn
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic that send the mouse_controller new
-- position of the mouse and new maximum values for the position
-- when resolution changes, so that the mouse will be centered on the
-- screen and the bounds for the new resolution are properly set.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- This module implements the logic that sets the position of the mouse
-- when the fpga is powered-up and when the resolution changes. It
-- also sets the bounds of the mouse corresponding to the currently used
-- resolution.
-- The mouse is centered for the currently selected resolution and the
-- bounds are set appropriately. This way the mouse will first appear
-- in the center in the screen at start-up and when resolution is
-- changed and cannot leave the screen.
-- The position (and similarly the bounds) is set by placing and number
-- representing the middle of the screen dimension on the value output
-- and activation the corresponding set signal (setx for horizontal
-- position, sety for vertical position, setmax_x for horizontal
-- maximum value, setmax_y for the veritcal maximum value).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal
-- rst - reset signal
-- resolution - input pin, from resolution_switcher
-- - 0 for 640x480 selected resolution
-- - 1 for 800x600 selected resolution
-- switch - input pin, from resolution_switcher
-- - active for one clock period when resolution changes
-- value - output pin, 10 bits, to mouse_controller
-- - position on x or y, max value for x or y
-- - that is sent to the mouse_controller
-- setx - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - position of the mouse cursor is valid on value output
-- sety - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - position of the mouse cursor is valid on value output
-- setmax_x - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - maximum position of the mouse cursor is valid on
-- - value output
-- setmax_y - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - maximum position of the mouse cursor is valid on
-- - value output
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
--library UNISIM;
--use UNISIM.VComponents.all;
-- the resolution_mouse_informer entity declaration
-- read above for behavioral description and port definitions.
entity resolution_mouse_informer is
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end resolution_mouse_informer;
architecture Behavioral of resolution_mouse_informer is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- center horizontal position of the mouse for 640x480 and 256x192
constant POS_X_640: std_logic_vector(9 downto 0) := "0101000000"; -- 320
constant POS_X_800: std_logic_vector(9 downto 0) := "0010000000"; -- 128
-- center vertical position of the mouse for 640x480 and 800x600
constant POS_Y_640: std_logic_vector(9 downto 0) := "0011110000"; -- 240
constant POS_Y_800: std_logic_vector(9 downto 0) := "0001100000"; -- 96
-- maximum horizontal position of the mouse for 640x480 and 800x600
constant MAX_X_640: std_logic_vector(9 downto 0) := "1001111111"; -- 639
constant MAX_X_800: std_logic_vector(9 downto 0) := "0011111111"; -- 255
-- maximum vertical position of the mouse for 640x480 and 800x600
constant MAX_Y_640: std_logic_vector(9 downto 0) := "0111011111"; -- 479
constant MAX_Y_800: std_logic_vector(9 downto 0) := "0010111111"; -- 191
constant RES_640 : std_logic := '0';
constant RES_800 : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
type fsm_state is (sReset,sIdle,sSetX,sSetY,sSetMaxX,sSetMaxY);
-- signal that holds the current state of the FSM
signal state: fsm_state := sIdle;
begin
-- value receives the horizontal position of the mouse, the vertical
-- position, the maximum horizontal value and maximum vertical
-- value for the active resolution when in the apropriate state
value <= POS_X_640 when state = sSetX and resolution = RES_640 else
POS_X_800 when state = sSetX and resolution = RES_800 else
POS_Y_640 when state = sSetY and resolution = RES_640 else
POS_Y_800 when state = sSetY and resolution = RES_800 else
MAX_X_640 when state = sSetMaxX and resolution = RES_640 else
MAX_X_800 when state = sSetMaxX and resolution = RES_800 else
MAX_Y_640 when state = sSetMaxY and resolution = RES_640 else
MAX_Y_800 when state = sSetMaxY and resolution = RES_800 else
(others => '0');
-- when in state sSetX, set the horizontal value for the mouse
setx <= '1' when state = sSetX else '0';
-- when in state sSetY, set the vertical value for the mouse
sety <= '1' when state = sSetY else '0';
-- when in state sSetMaxX, set the horizontal max value for the mouse
setmax_x <= '1' when state = sSetMaxX else '0';
-- when in state sSetMaxX, set the vertical max value for the mouse
setmax_y <= '1' when state = sSetMaxY else '0';
-- when a resolution switch occurs (even to the same resolution)
-- leave the idle state
-- if just powered up or reset occures go to reset state and
-- from there set the position and bounds for the mouse
manage_fsm: process(clk,rst)
begin
if(rst = '1') then
state <= sReset;
elsif(rising_edge(clk)) then
case state is
-- when reset occurs (or power-up) set the position
-- and bounds for the mouse.
when sReset =>
state <= sSetX;
-- remain in idle while switch is not active.
when sIdle =>
if(switch = '1') then
state <= sSetX;
else
state <= sIdle;
end if;
when sSetX =>
state <= sSetY;
when sSetY =>
state <= sSetMaxX;
when sSetMaxX =>
state <= sSetMaxY;
when sSetMaxY =>
state <= sIdle;
when others =>
state <= sIdle;
end case;
end if;
end process;
end Behavioral;
|
apache-2.0
|
sergev/vak-opensource
|
hardware/dlx/dlx_instr-body.vhdl
|
1
|
10542
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_instr-body.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 22:35:21 $
--
--------------------------------------------------------------------------
--
-- Package body for DLX instructions
--
use std.textio.all,
work.bv_arithmetic.bv_to_natural,
work.bv_arithmetic.bv_to_integer;
package body dlx_instr is
constant opcode_names : opcode_name_array :=
( "SPECIAL ", "FPARITH ", "J ", "JAL ",
"BEQZ ", "BNEZ ", "BFPT ", "BFPF ",
"ADDI ", "ADDUI ", "SUBI ", "SUBUI ",
"ANDI ", "ORI ", "XORI ", "LHI ",
"RFE ", "TRAP ", "JR ", "JALR ",
"SLLI ", "UNDEF_15", "SRLI ", "SRAI ",
"SEQI ", "SNEI ", "SLTI ", "SGTI ",
"SLEI ", "SGEI ", "UNDEF_1E", "UNDEF_1F",
"LB ", "LH ", "UNDEF_22", "LW ",
"LBU ", "LHU ", "LF ", "LD ",
"SB ", "SH ", "UNDEF_2A", "SW ",
"UNDEF_2C", "UNDEF_2D", "SF ", "SD ",
"SEQUI ", "SNEUI ", "SLTUI ", "SGTUI ",
"SLEUI ", "SGEUI ", "UNDEF_36", "UNDEF_37",
"UNDEF_38", "UNDEF_39", "UNDEF_3A", "UNDEF_3B",
"UNDEF_3C", "UNDEF_3D", "UNDEF_3E", "UNDEF_3F" );
constant sp_func_names : sp_func_name_array :=
( "NOP ", "UNDEF_01", "UNDEF_02", "UNDEF_03",
"SLL ", "UNDEF_05", "SRL ", "SRA ",
"UNDEF_08", "UNDEF_09", "UNDEF_0A", "UNDEF_0B",
"UNDEF_0C", "UNDEF_0D", "UNDEF_0E", "UNDEF_0F",
"SEQU ", "SNEU ", "SLTU ", "SGTU ",
"SLEU ", "SGEU ", "UNDEF_16", "UNDEF_17",
"UNDEF_18", "UNDEF_19", "UNDEF_1A", "UNDEF_1B",
"UNDEF_1C", "UNDEF_1D", "UNDEF_1E", "UNDEF_1F",
"ADD ", "ADDU ", "SUB ", "SUBU ",
"AND ", "OR ", "XOR ", "UNDEF_27",
"SEQ ", "SNE ", "SLT ", "SGT ",
"SLE ", "SGE ", "UNDEF_2E", "UNDEF_2F",
"MOVI2S ", "MOVS2I ", "MOVF ", "MOVD ",
"MOVFP2I ", "MOVI2FP ", "UNDEF_36", "UNDEF_37",
"UNDEF_38", "UNDEF_39", "UNDEF_3A", "UNDEF_3B",
"UNDEF_3C", "UNDEF_3D", "UNDEF_3E", "UNDEF_3F" );
constant fp_func_names : fp_func_name_array :=
( "ADDF ", "SUBF ", "MULTF ", "DIVF ",
"ADDD ", "SUBD ", "MULTD ", "DIVD ",
"CVTF2D ", "CVTF2I ", "CVTD2F ", "CVTD2I ",
"CVTI2F ", "CVTI2D ", "MULT ", "DIV ",
"EQF ", "NEF ", "LTF ", "GTF ",
"LEF ", "GEF ", "MULTU ", "DIVU ",
"EQD ", "NED ", "LTD ", "GTD ",
"LED ", "GED ", "UNDEF_1E", "UNDEF_1F" );
procedure write_reg (L : inout line; reg : reg_index) is
begin
write(L, 'R');
write(L, reg);
end write_reg;
procedure write_freg (L : inout line; freg : reg_index) is
begin
write(L, 'F');
write(L, freg);
end write_freg;
procedure write_special_reg (L : inout line; reg : reg_index) is
begin
case reg is
when 0 =>
write(L, string'("IAR"));
WHEN 1 =>
write(L, string'("FSR"));
when others =>
write(L, string'("SR"));
write(L, reg);
end case;
end write_special_reg;
procedure write_instr (L : inout line; instr : in dlx_word) is
alias instr_opcode : dlx_opcode is instr(0 to 5);
alias instr_sp_func : dlx_sp_func is instr(26 to 31);
alias instr_fp_func : dlx_fp_func is instr(27 to 31);
alias instr_rs1 : dlx_reg_addr is instr(6 to 10);
alias instr_rs2 : dlx_reg_addr is instr(11 to 15);
alias instr_Itype_rd : dlx_reg_addr is instr(11 to 15);
alias instr_Rtype_rd : dlx_reg_addr is instr(16 to 20);
alias instr_immed16 : dlx_immed16 is instr(16 to 31);
alias instr_immed26 : dlx_immed26 is instr(6 to 31);
variable instr_opcode_num : dlx_opcode_num;
variable instr_sp_func_num : dlx_sp_func_num;
variable instr_fp_func_num : dlx_fp_func_num;
variable rs1 : reg_index;
variable rs2 : reg_index;
variable Itype_rd : reg_index;
variable Rtype_rd : reg_index;
begin
instr_opcode_num := bv_to_natural(instr_opcode);
instr_sp_func_num := bv_to_natural(instr_sp_func);
instr_fp_func_num := bv_to_natural(instr_fp_func);
rs1 := bv_to_natural(instr_rs1);
rs2 := bv_to_natural(instr_rs2);
Itype_rd := bv_to_natural(instr_Itype_rd);
Rtype_rd := bv_to_natural(instr_Rtype_rd);
--
if (instr_opcode /= op_special) and (instr_opcode /= op_fparith) then
write(L, opcode_names(instr_opcode_num));
write(L, ' ');
end if;
case instr_opcode is
when op_special =>
write(L, sp_func_names(instr_sp_func_num));
write(L, ' ');
case instr_sp_func is
when sp_func_nop =>
null;
when sp_func_sll | sp_func_srl | sp_func_sra |
sp_func_sequ | sp_func_sneu | sp_func_sltu |
sp_func_sgtu | sp_func_sleu | sp_func_sgeu |
sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu |
sp_func_and | sp_func_or | sp_func_xor |
sp_func_seq | sp_func_sne | sp_func_slt |
sp_func_sgt | sp_func_sle | sp_func_sge =>
write_reg(L, Rtype_rd); write(L, string'(", "));
write_reg(L, rs1); write(L, string'(", "));
write_reg(L, rs2);
when sp_func_movi2s =>
write_special_reg(L, Rtype_rd); write(L, string'(", "));
write_reg(L, rs1);
when sp_func_movs2i =>
write_reg(L, Rtype_rd); write(L, string'(", "));
write_special_reg(L, rs1);
when sp_func_movf | sp_func_movd =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1);
when sp_func_movfp2i =>
write_reg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1);
when sp_func_movi2fp =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_reg(L, rs1);
when others =>
null;
end case;
when op_fparith =>
write(L, fp_func_names(instr_fp_func_num));
write(L, ' ');
case instr_fp_func is
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
fp_func_mult | fp_func_div | fp_func_multu | fp_func_divu =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1); write(L, string'(", "));
write_freg(L, rs2);
when fp_func_cvtf2d | fp_func_cvtd2f =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1);
when fp_func_cvtf2i | fp_func_cvtd2i =>
write_reg(L, Rtype_rd); write(L, string'(", "));
write_freg(L, rs1);
when fp_func_cvti2f | fp_func_cvti2d =>
write_freg(L, Rtype_rd); write(L, string'(", "));
write_reg(L, rs1);
when fp_func_eqf | fp_func_nef | fp_func_ltf |
fp_func_gtf | fp_func_lef | fp_func_gef |
fp_func_eqd | fp_func_ned | fp_func_ltd |
fp_func_gtd | fp_func_led | fp_func_ged =>
write_freg(L, rs1); write(L, string'(", "));
write_freg(L, rs2);
when others =>
null;
end case;
when op_j | op_jal =>
write(L, bv_to_integer(instr_immed26));
when op_beqz | op_bnez =>
write_reg(L, rs1); write(L, string'(", "));
write(L, bv_to_integer(instr_immed16));
when op_bfpt | op_bfpf =>
write(L, bv_to_integer(instr_immed16));
when op_slli | op_srli | op_srai =>
write_reg(L, Itype_rd); write(L, string'(", "));
write_reg(L, rs1); write(L, string'(", "));
write(L, bv_to_natural(instr_immed16(11 to 15)));
when op_addi | op_subi |
op_seqi | op_snei | op_slti | op_sgti | op_slei | op_sgei =>
write_reg(L, Itype_rd); write(L, string'(", "));
write_reg(L, rs1); write(L, string'(", "));
write(L, bv_to_integer(instr_immed16));
when op_addui | op_subui | op_andi | op_ori | op_xori |
op_sequi | op_sneui | op_sltui | op_sgtui | op_sleui | op_sgeui =>
write_reg(L, Itype_rd); write(L, string'(", "));
write_reg(L, rs1); write(L, string'(", "));
write(L, bv_to_natural(instr_immed16));
when op_lhi =>
write_reg(L, Itype_rd); write(L, string'(", "));
write(L, bv_to_natural(instr_immed16));
when op_rfe =>
null;
when op_trap =>
write(L, bv_to_natural(instr_immed26));
when op_jr | op_jalr =>
write_reg(L, rs1);
when op_lb | op_lh | op_lw |
op_lbu | op_lhu | op_lf | op_ld =>
write_reg(L, Itype_rd); write(L, string'(", "));
write(L, bv_to_integer(instr_immed16)); write(L, '(');
write_reg(L, rs1); write(L, ')');
when op_sb | op_sh | op_sw | op_sf | op_sd =>
write(L, bv_to_integer(instr_immed16));
write(L, '('); write_reg(L, rs1); write(L, string'("), "));
write_reg(L, Itype_rd);
when others =>
null;
end case;
end write_instr;
end dlx_instr;
|
apache-2.0
|
Cognoscan/BoostDSP
|
vhdl/src/comm_systems/simple_tx_ea.vhd
|
1
|
5178
|
--! @file simple_tx_ea.vhd
--! @brief Instantiates a simple RF transmitter.
--! @author Scott Teal ([email protected])
--! @date 2013-11-06
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
--! All prerequisite packages in BoostDSP
use work.fixed_pkg.all;
use work.util_pkg.all;
use work.rf_blocks_pkg;
use work.basic_pkg;
--! A simple RF transmitter. It uses rf_blocks_pkg.frame_tx and basic_pkg.mapper
--! to generate I and Q values from a buffered set of data. Setting INCLUDE_DDS
--! to true causes these I and Q symbol values to be used to modulate the output
--! from a DDS (rf_blocks_pkg.dds). This is mostly useful for the purposes of
--! simulation and for systems that output directly to RF.
entity simple_tx is
generic (
INCLUDE_DDS : boolean := false;
MAP_VALUES_I : real_vector;
MAP_VALUES_Q : real_vector
);
port (
clk : in std_logic; --! System clock
rst : in std_logic; --! System reset
frame_size : in unsigned; --! Size of frame to transmit
clks_per_symbol : in unsigned; --! Clock cycles per symbol transmitted
start : in std_logic; --! Strobe high to start transmitting.
abort : in std_logic; --! Strobe high to abort transmitting.
frame_tx_complete : out std_logic; --! High when not transmitting.
buffer_addr : in std_logic_vector; --! Address to read/write to.
buffer_we : in std_logic; --! High when write, low when read.
buffer_write_data : in std_logic_vector; --! Data to write.
buffer_read_data : out std_logic_vector; --! Data read from address.
buffer_strobe : in std_logic; --! Strobe high to cycle bus.
buffer_done : out std_logic; --! Strobe high when read/write complete.
freq : in ufixed; --! Only needed if DDS is used
i_out : out sfixed; --! In-phase data
q_out : out sfixed --! Quadrature-phase data
);
end entity;
architecture rtl of simple_tx is
constant symbol_size : positive := integer(log2(real(map_values_i'length)));
signal symbol_data : std_logic_vector((symbol_size - 1) downto 0);
signal mapped_i : sfixed(i_out'range);
signal mapped_q : sfixed(q_out'range);
signal dds_i : sfixed(i_out'range);
signal dds_q : sfixed(q_out'range);
begin
-- State assumptions first
assert MAP_VALUES_I'length = MAP_VALUES_Q'length
report "Map value vectors must be of same length"
severity error;
select_dds : if INCLUDE_DDS = true generate
dds_1 : rf_blocks_pkg.dds
port map (
clk => clk,
rst => rst,
freq => freq,
phase => to_ufixed(0,-1,-2),
i_out => dds_i,
q_out => dds_q
);
--! Modulation process. Multiplies DDS outputs by mapped I and Q values.
modulate : process (clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
i_out <= to_sfixed(0, i_out);
q_out <= to_sfixed(0, q_out);
else
i_out <= resize(mapped_i * dds_i, i_out);
q_out <= resize(mapped_q * dds_q, q_out);
end if; -- rst
end if; -- clk
end process;
end generate;
--! If there's no DDS, modulation is unnecessary.
no_dds : if INCLUDE_DDS = false generate
i_out <= mapped_i;
q_out <= mapped_q;
end generate;
frame_tx_1 : rf_blocks_pkg.frame_tx
port map (
clk => clk,
rst => rst,
frame_size => frame_size,
clks_per_symbol => clks_per_symbol,
start => start,
abort => abort,
frame_tx_complete => frame_tx_complete,
buffer_addr => buffer_addr,
buffer_we => buffer_we,
buffer_write_data => buffer_write_data,
buffer_read_data => buffer_read_data,
buffer_strobe => buffer_strobe,
buffer_done => buffer_done,
symbol_out => symbol_data
);
mapper_1 : basic_pkg.mapper
generic map (
map_values_i => MAP_VALUES_I,
map_values_q => MAP_VALUES_Q
)
port map (
clk => clk,
rst => rst,
data => symbol_data,
i_out => mapped_i,
q_out => mapped_q
);
end rtl;
|
apache-2.0
|
Cognoscan/BoostDSP
|
vhdl/src/basic/fir_ea.vhd
|
1
|
6600
|
--! @file fir_ea.vhd
--! @brief Pipelined FIR filter
--! @author Scott Teal ([email protected])
--! @date 2013-12-16
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use work.fixed_pkg.all;
use work.util_pkg.all;
--! Pipelined FIR filter. Can be configured to be a symmetric filter, and takes
--! in coefficients as it runs. The upper and lower bits of the fixed-point
--! accumulators must be set by the user. The recommended values of these are
--! vendor- and application-dependent, and thus cannot be calculated within this
--! entity.
--!
--! If using the symmetric option, make sure to correctly set whether there is
--! an even or odd **total** number of coefficients. The entity will not function as
--! expected otherwise.
--!
--! Example: 64-tap filter can be described with 32 coefficients if it is
--! symmetric. Set EVEN to true so that the entity knows it was originally
--! a 64-tap filter.
--!
--! Example: 63-tap filter can also be described with 32 coefficients if it is
--! symmetric. Set EVEN to false so that the entity knows it was originally
--! a 63-tap filter, and not a 64-tap.
--!
entity fir is
generic (
SYMMETRIC : boolean := false; --! Symmetric filter
EVEN : boolean := false; --! Even or odd number of total coefficients
UPPER_BIT : integer; --! Upper bit of accumulator
LOWER_BIT : integer --! Lower bit of accumulator
);
port (
clk : in std_logic; --! Clock line
rst : in std_logic; --! Reset line
coeff : in sfixed_vector; --! Coefficient vector
din : in sfixed; --! Data into FIR filter
dout : out sfixed --! Filtered data
);
end entity fir;
architecture rtl of fir is
signal in_line : sfixed_vector(coeff'range)(din'range);
signal delay0 : sfixed_vector(coeff'range)(din'range);
signal coeff_reg : sfixed_vector(coeff'range)(coeff'element'range);
signal mul_reg : sfixed_vector(coeff'range)(UPPER_BIT downto LOWER_BIT);
signal add_reg : sfixed_vector(coeff'range)(UPPER_BIT downto LOWER_BIT);
signal symmetric_delay : sfixed_vector(0 to (coeff'high * 2 + 1))(din'range);
signal symmetric_input : sfixed_vector(coeff'range)(din'range);
signal preadd_reg : sfixed_vector(coeff'range)(
sfixed_high(din'high, din'low, '+', din'high, din'low) downto
sfixed_low(din'high, din'low, '+', din'high, din'low));
begin
pipeline : process(clk,rst)
begin
if rising_edge(clk) then
if rst = '1' then
-- Zero everything out
in_line <= (others => to_sfixed(0,
in_line'element'high, in_line'element'low));
delay0 <= (others => to_sfixed(0,
delay0'element'high, delay0'element'low));
coeff_reg <= (others => to_sfixed(0,
coeff_reg'element'high, coeff_reg'element'low));
mul_reg <= (others => to_sfixed(0,
mul_reg'element'high, mul_reg'element'low));
add_reg <= (others => to_sfixed(0,
add_reg'element'high, add_reg'element'low));
else
for i in coeff'range loop
-- Input data pipeline
if i = 0 then
in_line(i) <= din; -- Feed data in to delay line
else
in_line(i) <= delay0(i-1); -- Build up delay line registers
end if;
delay0(i) <= in_line(i); -- Delay input by 1
coeff_reg(i) <= coeff(i); -- Register all coefficients
-- Multiplier & preadder are different depending on whether the filter
-- is symmetric or not
if SYMMETRIC then
if ((not EVEN) and (i = coeff'high)) then
preadd_reg(i) <= resize(delay0(i),
preadd_reg'element'high,
preadd_reg'element'low);
else
preadd_reg(i) <= delay0(i) + symmetric_input(i);
end if;
-- Multiply data by coefficients
mul_reg(i) <= resize(preadd_reg(i) * coeff_reg(i),
UPPER_BIT, LOWER_BIT);
else
-- Multiply data by coefficients
mul_reg(i) <= resize(delay0(i) * coeff_reg(i),
UPPER_BIT, LOWER_BIT);
end if;
-- Adders
if i = 0 then
-- First adder has no previous adder output
add_reg(i) <= resize(mul_reg(i),
UPPER_BIT, LOWER_BIT);
else
-- Build up adder chain
add_reg(i) <= resize(mul_reg(i) + add_reg(i-1),
UPPER_BIT, LOWER_BIT);
end if;
end loop;
end if;
end if;
end process;
symmetric_delay_pipeline_gen : if SYMMETRIC generate
symmetric_delay_pipeline : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
symmetric_delay <= (others => to_sfixed(0,
symmetric_delay'element'high,
symmetric_delay'element'low));
symmetric_input <= (others => to_sfixed(0,
symmetric_input'element'high,
symmetric_input'element'low));
else
for i in symmetric_delay'range loop
if i = 0 then
symmetric_delay(i) <= din;
else
symmetric_delay(i) <= symmetric_delay(i - 1);
end if;
end loop;
for i in symmetric_input'range loop
if EVEN then
symmetric_input(i) <= symmetric_delay(symmetric_delay'high);
else
symmetric_input(i) <= symmetric_delay(symmetric_delay'high-1);
end if;
end loop;
end if; -- rst
end if; -- clk
end process; -- pipeline
end generate; -- generate
--! Final output is output from highest adder
dout <= add_reg(add_reg'high(1))(dout'high downto dout'low);
end rtl;
|
apache-2.0
|
Cognoscan/BoostDSP
|
vhdl/src/rf_blocks/poly_dds_ea.vhd
|
1
|
5402
|
--! @file poly_dds_ea.vhd
--! @brief Polyphase Direct Digital Synthesizer
--! @author Scott Teal ([email protected])
--! @date 2013-12-17
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.fixed_float_types.all;
--! Local version of the fixed point package
use work.fixed_pkg.all;
--! Utility package
use work.util_pkg.all;
--! Basic design elements
use work.basic_pkg;
--! Polyphase Direct Digital Synthesizer. For each phase channel, generates
--! 2 sinusoidal waves 90 degrees out of phase with each other. Frequency is
--! determined by freq, which should be some value between 0 and 1.
entity poly_dds is
port (
clk : in std_logic; --! Clock line
rst : in std_logic; --! Reset line
freq : in ufixed; --! Frequency input
phase : in ufixed; --! Additional phase offset
i_out : out sfixed_vector; --! I Sinusoidal output vector
q_out : out sfixed_vector --! Q Sinusoidal output vector
);
end entity poly_dds;
--! Phase accumulator-base DDS architecture. Uses a phase accumulator that adds
--! freq to phase_acc every clock cycle. The phase offset is then added on to
--! get the angle. This signal angle is then used along with multiples of freq
--! to get the various phase-offset angles to feed to the trigometric look-up
--! tables. The outputs of these look-up tables are the polyphase DDS outputs.
architecture rtl of poly_dds is
--! Registered freq value
signal freq_reg : ufixed(freq'range);
--! Scaled freq value to increment the phase accumulator by
signal phase_acc_freq : ufixed(freq'range);
--! Scaled freq values for use in finding phases
signal scaled_freqs : ufixed_vector(i_out'range)(freq'range);
--! Angle of DDS before adding phase offset (phase accumulator)
signal phase_acc : ufixed(-1 downto freq'low);
--! Current angle of DDS (primary phase register)
signal angle : ufixed(-1 downto freq'low);
--! Adjusted angles of DDS
signal phases : ufixed_vector(i_out'range)(-1 downto freq'low);
begin
--! State assumptions
assert freq'high < 0
report "Frequency bits above -1 not used (freq = 0 to 1)"
severity warning;
assert i_out'high = q_out'high
report "Not equal number of i_out and q_out (high indices don't match"
severity error;
assert i_out'low = q_out'low
report "Not equal number of i_out and q_out (low indices don't match"
severity error;
assert i_out'low = 0
report "Low index of i_out & q_out must be 0"
severity error;
--! Frequency register pipeline
freq_pipeline : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
freq_reg <= to_ufixed(0, freq_reg);
phase_acc_freq <= to_ufixed(0, phase_acc_freq'high, phase_acc_freq'low);
scaled_freqs <= (others => to_ufixed(0,
scaled_freqs'element'high, scaled_freqs'element'low));
else
freq_reg <= freq;
phase_acc_freq <= resize(freq_reg *
to_ufixed(i_out'length, get_counter_width(i_out'high), 0),
phase_acc_freq'high, phase_acc_freq'low,
fixed_wrap, fixed_truncate);
for i in i_out'range loop
scaled_freqs(i) <= resize(freq_reg *
to_ufixed(i, get_counter_width(i_out'high), 0),
scaled_freqs(i)'high, scaled_freqs(i)'low,
fixed_wrap, fixed_truncate);
end loop;
end if; -- rst
end if; -- clk
end process;
--! Phase incrementers
phase_inc : process (clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
phase_acc <= to_ufixed(0, phase_acc);
angle <= to_ufixed(0, angle);
phases <= (others => to_ufixed(0,
phases'element'high, phases'element'low));
else
phase_acc <= resize(phase_acc + phase_acc_freq,
phase_acc'high, phase_acc'low,
fixed_wrap, fixed_truncate);
angle <= resize(phase_acc + phase, angle'high, angle'low,
fixed_wrap, fixed_truncate);
for i in i_out'range loop
phases(i) <= resize(angle + scaled_freqs(i),
phases(i)'high, phases(i)'low,
fixed_wrap, fixed_truncate);
end loop;
end if;
end if;
end process;
--! Generate Trig Lookup Tables
trig_table_gen : for i in i_out'range generate
trig_table_x : basic_pkg.trig_table
port map (
clk => clk,
rst => rst,
angle => phases(i),
sine => q_out(i),
cosine => i_out(i)
);
end generate;
end rtl;
|
apache-2.0
|
AntonMause/tcl4soc
|
vhdl/myDffCnt.vhd
|
1
|
1648
|
----------------------------------------------------------------------
-- myDffCnt
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Generate chain of N D-FlipFlip to create toggle counter.
-- !! This source is simplified for demonstration purpose !!
-- !! It is not intended to become part of real designs !!
--
-- WatchOut : Instantiation of myDff() passes arguments by index.
-- This can lead to trouble when modifying parameters in component.
--
-- WatchOut : In reality the output signal timing is weak/unknown.
-- The outputs of this entity will switch some time after i_clk.
-- Every bit is its own clock domain, worst case for synchr designs.
-- OK to toggle LEDs or to divide clock, unproper for compare/control.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity myDffCnt is
generic (N : Integer:=8);
port ( i_rst_n, i_clk : in std_logic;
o_q : out std_logic_vector(N-1 downto 0) );
end entity myDffCnt;
----------------------------------------------------------------------
architecture rtl of myDffCnt is
component myDff
port (i_rst_n, i_clk, i_d : in std_logic;
o_q, o_nq : out std_logic);
end component myDff;
signal s : std_logic_vector(N downto 0);
begin
s(0) <= i_clk;
GEN_FF : for I in N-1 downto 0 generate
D_FF : myDff port map
(i_rst_n, s(I), s(I+1), o_q(I), s(I+1));
end generate;
end architecture rtl;
----------------------------------------------------------------------
|
apache-2.0
|
AntonMause/tcl4soc
|
g4dev/brdConst_pkg.vhd
|
1
|
1637
|
----------------------------------------------------------------------
-- brdConst_pkg (for first huge Dev Kit with PoE)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
constant BRD_OSC_CLK_MHZ : positive := 50_000_000; -- direct
--constant BRD_OSC_CLK_MHZ : positive := 25_000_000; -- divided
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '0';
-- polarity of push button switches
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '1';
end brdConst_pkg;
----------------------------------------------------------------------
|
apache-2.0
|
AntonMause/tcl4soc
|
g4img/brdLexSwx.vhd
|
1
|
901
|
----------------------------------------------------------------------
-- brdLexSwx (for IMG Dev Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '1';
end rtl;
|
apache-2.0
|
AntonMause/tcl4soc
|
g4adv/brdLexSwx.vhd
|
1
|
906
|
----------------------------------------------------------------------
-- brdLexSwx (for Advanced Dev Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '1';
end rtl;
|
apache-2.0
|
AntonMause/tcl4soc
|
g4start/brdConst_pkg.vhd
|
1
|
1629
|
----------------------------------------------------------------------
-- brdConst_pkg (for EmCraft SoC FG896 Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
constant BRD_OSC_CLK_MHZ : positive := 50_000_000; -- direct
--constant BRD_OSC_CLK_MHZ : positive := 25_000_000; -- divided
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '1';
end brdConst_pkg;
----------------------------------------------------------------------
|
apache-2.0
|
AntonMause/tcl4soc
|
g4adv/brdRstClk.vhd
|
1
|
1660
|
----------------------------------------------------------------------
-- brdRstClk (for Advanced Dev Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Board dependend reset and clock manipulation file.
-- Adjust i_clk from some known clock, so o_clk has BRD_OSC_CLK_MHZ.
-- See "brdConst_pkg.vhd" for specific BRD_OSC_CLK_MHZ values.
-- Sync up o_rst_n to fit to rising edge of o_clk.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;
----------------------------------------------------------------------
entity brdRstClk is
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic);
end brdRstClk;
----------------------------------------------------------------------
architecture rtl of brdRstClk is
component SYSRESET
port( DEVRST_N : in std_logic;
POWER_ON_RESET_N : out std_logic );
end component;
signal s_tgl, s_dly_n, s_rst_n : std_logic;
begin
SYSRESET_0 : SYSRESET
port map(
DEVRST_N => i_rst_n,
POWER_ON_RESET_N => s_rst_n );
process(i_clk, s_rst_n)
begin
if s_rst_n = '0' then
s_dly_n <= '0';
s_tgl <= '0';
o_rst_n <= '0';
elsif (i_clk'event and i_clk = '1') then
s_dly_n <= '1';
s_tgl <= not s_tgl;
o_rst_n <= s_dly_n;
end if;
end process;
-- edit BRD_OSC_CLK_MHZ in brdConst_pkg too
o_clk <= i_clk; -- 50MHz, direct
--o_clk <= s_tgl; -- 25MHz, divided
end rtl;
----------------------------------------------------------------------
|
apache-2.0
|
AntonMause/tcl4soc
|
g3icicle/brdConst_pkg.vhd
|
1
|
1620
|
----------------------------------------------------------------------
-- brdConst_pkg (for Icicle Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
constant BRD_OSC_CLK_MHZ : positive := 20_000_000; -- direct
--constant BRD_OSC_CLK_MHZ : positive := 10_000_000; -- divided
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '0';
-- polarity of push button switches
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '1';
end brdConst_pkg;
----------------------------------------------------------------------
|
apache-2.0
|
AntonMause/tcl4soc
|
vhdl/mySynRst.vhd
|
1
|
775
|
----------------------------------------------------------------------
-- mySynRst
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- synchronise reset to clock
--
----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mySynRst is
port(i_rst_n, i_clk : in std_logic;
o_rst_n : out std_logic);
end mySynRst;
architecture rtl of mySynRst is
signal s_dly_n, s_rst_n : std_logic;
begin
process(i_clk, i_rst_n)
begin
if i_rst_n = '0' then
s_dly_n <= '0';
s_rst_n <= '0';
elsif (i_clk'event and i_clk = '1') then
s_dly_n <= '1';
s_rst_n <= s_dly_n;
end if;
end process;
o_rst_n <= s_rst_n;
end rtl;
|
apache-2.0
|
AntonMause/tcl4soc
|
g4img/brdRstClk.vhd
|
1
|
3024
|
----------------------------------------------------------------------
-- brdRstClk (for IMG Dev Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Board dependend reset and clock manipulation file.
-- Adjust i_clk from some known input clock rate so o_clk runs at 50MHz.
-- Sync up o_rst_n to fit to rising edge of o_clk.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library smartfusion2;
use smartfusion2.all;
----------------------------------------------------------------------
-- 125 MHz xTal Input => 50 MHz Output => divide by 2.5
-- 1 2 3 4 5 6 7 8 9 10
-- 01010101010101010101
--
-- 00011000110001100011
-- 0 1 0 2 0 3 0 4
-- 0.0.1.0.1.0.0.1.0.1.
-- .0.1.0.0.1.0.1.0.0.1
-- 00011000110001100011
-- 0 1 0 2 0 3 0 4
-- 01234567890123456789
-- 0.1.2.3.4.5.6.7.8.9.
--
-- .0.1.0.1.0.0.1.0.1.0 -- failing if starting at wrong edge
-- 1.0.1.0.0.1.0.1.0.0.
-- 10011001001001100100 -- wrong pattern with spikes
-- 00011000110001100011 -- rigth pattern
-- *------****------*** -- <= mismatch
----------------------------------------------------------------------
entity brdRstClk is
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic );
end brdRstClk;
----------------------------------------------------------------------
architecture behavioral of brdRstClk is
component SYSRESET
port( DEVRST_N : in std_logic;
POWER_ON_RESET_N : out std_logic );
end component;
signal s_rst_in, s_dly_n, s_rst_n, s_clk : std_logic;
-- FLASH FPGA tools will not synthesise := "00101" !!!
-- With G3 expext random values, with G4 all ZEROs.
-- Looks OK with Modelsim PRE synthesis, NOT in reality.
signal s_one : std_logic_vector(4 downto 0) := "00101";
signal s_two : std_logic_vector(4 downto 0) := "01001";
-- not using := increases chance to find uninitialized values
begin
SYSRESET_0 : SYSRESET
port map(
DEVRST_N => i_rst_n,
POWER_ON_RESET_N => s_rst_in );
process(i_clk, s_rst_in) -- sync s_rst_n to i_clk
begin
if s_rst_in = '0' then
s_dly_n <= '0';
s_rst_n <= '0';
elsif (i_clk'event and i_clk = '1') then
s_dly_n <= '1';
s_rst_n <= s_dly_n;
end if;
end process;
process(i_clk, s_rst_n) -- divide clock by shifting pattern
begin
if (s_rst_n = '0') then
s_one <= "00101";
elsif (i_clk'event and i_clk = '1') then
s_one <= s_one(0) & s_one(4 downto 1);
end if;
end process;
process(i_clk, s_rst_n)
begin
if (s_rst_n = '0') then
s_two <= "01001";
elsif (i_clk'event and i_clk = '0') then
s_two <= s_two(0) & s_two(4 downto 1);
end if;
end process;
s_clk <= s_one(0) AND s_two(0);
-- decide if second RESET sync block here
o_rst_n <= s_rst_n;
-- edit BRD_OSC_CLK_MHZ in brdConst_pkg too
--o_clk <= i_clk; -- 125MHz, direct
o_clk <= s_clk; -- 50MHz, divided
end behavioral;
|
apache-2.0
|
estradjm/Class-Work
|
HDL/Traffic Intersection/ControlTraffic.vhdl
|
1
|
6454
|
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity TrafficControl is
PORT (EffClock: IN STD_LOGIC;
Clock : IN STD_LOGIC;
crosswalktraffic : IN STD_LOGIC;
lowpriortraffic : IN STD_LOGIC;
reset : IN STD_LOGIC;
HIP : OUT STD_LOGIC;
LOWP : OUT STD_LOGIC;
PED : OUT STD_LOGIC;
HiDone : OUT STD_LOGIC;
LowDone : OUT STD_LOGIC;
PedDone : OUT STD_LOGIC;
HiCount : OUT STD_LOGIC_VECTOR (3 downto 0);
LowCount : OUT STD_LOGIC_VECTOR (3 downto 0);
PedCount : OUT STD_LOGIC_VECTOR (3 downto 0));
end TrafficControl;
architecture Behavioral of TrafficControl is
type State is (HighPriority, LowPriority, Pedestrian, COUNTDOWN5Ped, COUNTDOWN5Low, L2Ped);
signal CurrentState , NextState : State;
signal countdown9 : std_logic_vector (3 downto 0);
signal countdown4 : std_logic_vector (3 downto 0);
signal countdown5 : std_logic_vector (3 downto 0);
signal resetsig : std_logic;
signal HiEnable : std_logic;
signal LowEnable : std_logic;
signal PedEnable : std_logic;
signal register5 : std_logic;
signal register9 : std_logic;
signal register4 : std_logic;
signal trip5 : std_logic;
signal trip9 : std_logic;
signal trip4 : std_logic;
signal Go2Ped : std_logic;
begin
HiCount <= countdown5;
LowCount <= countdown9;
PedCount <= countdown4;
resetsig <= reset;
Works : process (Go2Ped, reset, CurrentState, countdown4, countdown5, countdown9, NextState, crosswalktraffic, lowpriortraffic, Clock)
begin
case CurrentState is
when HighPriority =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HIenable <= '0';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '1';
trip4 <= '1';
trip9 <= '1';
Go2Ped <= '0';
if crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;
elsif lowpriortraffic = '1' then
NextState <= COUNTDOWN5Low;
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when Pedestrian =>
NextState <= CurrentState;
HIP <= '0';
LOWP <= '0';
PED <= '1';
HiDone <= '1';
LowDone <= '1';
PedDone <= '0';
HIenable <= '0';
LowEnable <= '0';
PedEnable <= '1';
trip4 <= '0';
Go2Ped <= '0';
if countdown4 = 0 and lowpriortraffic = '1' then
NextState <= LowPriority;
trip4 <= '1';
elsif countdown4 = 0 and lowpriortraffic = '0' then
NextState <= HighPriority;
trip4 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when LowPriority =>
NextState <= CurrentState;
HIP <= '0';
LOWP <= '1';
PED <= '0';
HiDone <= '1';
LowDone <= '0';
PEDdone <= '1';
HiEnable <= '0';
LowEnable <= '1';
PedEnable <= '0';
trip9 <= '0';
if countdown9 = 0 and Go2Ped = '0' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
elsif countdown9 = 0 and Go2Ped = '1' then
NextState <= L2Ped;
trip4 <='1';
trip5 <='1';
trip9 <='1';
elsif crosswalktraffic = '1' then
Go2Ped <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when COUNTDOWN5Ped =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '0';
Go2Ped <= '0';
if countdown5 = 0 then
NextState <= pedestrian;
trip5 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when COUNTDOWN5low =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5 <= '0';
Go2Ped <= '0';
if countdown5 = 0 then
NextState <= LowPriority;
trip5 <='1';
elsif crosswalktraffic = '1' then
NextState <= COUNTDOWN5Ped;
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
when L2Ped =>
NextState <= CurrentState;
HIP <= '1';
LOWP <= '0';
PED <= '0';
HiDone <= '0';
LowDone <= '1';
PedDone <= '1';
HiEnable <= '1';
LowEnable <= '0';
PedEnable <= '0';
trip5<='0';
if countdown5 = 0 then
NextState <= Pedestrian;
trip5 <= '1';
elsif reset = '1' then
NextState <= HighPriority;
trip4 <='1';
trip5 <='1';
trip9 <='1';
end if;
end case;
end process;
CountDOWN5Down : process (EffClock, HiEnable, resetsig, countdown5, trip5)
begin
if register5 = '1' or resetsig = '1' then
countdown5 <= "0101";
elsif (RISING_EDGE (EffClock)) and HiEnable = '1' THEN
if countdown5 = 0 then
countdown5 <= "0101";
else
countdown5 <= countdown5 - 1;
end if;
end if;
end process;
count9Down : process (EffClock, LowEnable, resetsig, countdown9, trip9)
begin
if register9 = '1' or resetsig = '1' then
countdown9 <= "1001";
elsif (Rising_Edge(EffClock)) and LowEnable = '1' THEN
if countdown9 = 0 then
countdown9 <= "1001";
else
countdown9 <= countdown9 - 1;
end if;
end if;
end process;
count4Down : process (EffClock, PedEnable, resetsig, countdown4, trip4)
begin
if register4 = '1' or resetsig = '1' then
countdown4 <= "0100";
elsif (rising_edge (EffClock)) and PedEnable = '1' THEN
if countdown4 = 0 then
countdown4 <= "0100";
else
countdown4 <= countdown4 - 1;
end if;
end if;
end process;
PROCESS(Clock)
begin
IF Rising_Edge(Clock) THEN
CurrentState <= NextState;
register5 <= trip5;
register4 <= trip4;
register9 <= trip9;
END IF;
END PROCESS;
end Behavioral;
|
apache-2.0
|
estradjm/Class-Work
|
HDL/Traffic Intersection/clockCounter.vhdl
|
1
|
557
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY ClockCounter IS
GENERIC (UpperBound: integer);
PORT ( Clock: IN std_logic;
Enable: OUT std_logic);
END ClockCounter;
ARCHITECTURE behavior OF ClockCounter IS
signal count : integer range 0 to(UpperBound-1);
BEGIN
PROCESS (Clock)
BEGIN
IF (rising_edge(Clock)) then
IF(count = (UpperBound-1)) then
count <= 0;
Enable <= '1';
else
count <= count+1;
Enable <= '0';
end if;
end if;
END PROCESS;
END behavior;
|
apache-2.0
|
yongshengwang/hue
|
tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
apache-2.0
|
HackLinux/THCO-MIPS-CPU
|
src/CPU_CORE.vhd
|
2
|
43733
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:28:54 11/19/2013
-- Design Name:
-- Module Name: CPU_CORE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU_CORE is
Port ( CLK_IN : in STD_LOGIC;
RAM1_Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM1_EN : out STD_LOGIC;
RAM1_WE : out STD_LOGIC;
RAM1_OE : out STD_LOGIC;
RAM1_Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2_Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM2_EN : out STD_LOGIC;
RAM2_WE : out STD_LOGIC;
RAM2_OE : out STD_LOGIC;
RAM2_Data : inout STD_LOGIC_VECTOR (15 downto 0);
com_data_ready : in STD_LOGIC;
com_rdn : out STD_LOGIC;
com_tbre : in STD_LOGIC;
com_tsre : in STD_LOGIC;
com_wrn : out STD_LOGIC;
DISP1 : inout std_logic_vector(6 downto 0) := "0111111";
DISP2 : inout std_logic_vector(6 downto 0) := "0111111";
LED : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000");
end CPU_CORE;
architecture Behavioral of CPU_CORE is
COMPONENT CLK_MODULE
Port ( CLK_IN : in STD_LOGIC;
CLK : inout STD_LOGIC
);
END COMPONENT;
COMPONENT PC_Register
Port ( PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_OR_NOT : in STD_LOGIC;
CLK : in STD_LOGIC
);
END COMPONENT;
COMPONENT MUX_2
Port ( SELEC : in STD_LOGIC;
SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_3
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0);
SELEC : in STD_LOGIC_VECTOR (1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_4
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0);
SELEC : in STD_LOGIC_VECTOR (1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_6
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_5 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_6 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (2 downto 0) := "111";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
END COMPONENT;
COMPONENT RAM1_Visitor
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
DataReady: in std_logic;
WriteData: in std_logic_vector(15 downto 0);
TSRE: in std_logic;
TBRE: in std_logic;
---output
RAM1_Enable: out std_logic;
RAM1_ReadEnable: out std_logic;
RAM1_WriteEnable: out std_logic;
SPort_WriteEnable:out std_logic;
SPort_ReadEnable: out std_logic;
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT RAM2_Visitor
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0);
---output
RAM2_Enable: out std_logic := '1';
RAM2_ReadEnable: out std_logic := '1';
RAM2_WriteEnable: out std_logic := '1';
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT PC_Adder
Port ( OLD_PC : in STD_LOGIC_VECTOR (15 downto 0);
NEW_PC : out STD_LOGIC_VECTOR (15 downto 0)
);
END COMPONENT;
COMPONENT IF_ID_Register
Port ( NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_PC_OR_NOT : in STD_LOGIC;
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
CLK : in STD_LOGIC;
INST_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_IR_OR_NOT : in STD_LOGIC;
WRITE_IR_SRC_SELEC : in STD_LOGIC;
INST_OUT_CODE : out STD_LOGIC_VECTOR(4 downto 0);
INST_OUT_RS : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_RT : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_RD : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_FUNC : out STD_LOGIC_VECTOR(1 downto 0));
END COMPONENT;
COMPONENT Imm_Extend
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
rd : in STD_LOGIC_VECTOR(2 downto 0);
func : in STD_LOGIC_VECTOR(1 downto 0);
imm : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT adder
port(
pc : in STD_LOGIC_VECTOR(15 downto 0);
imm : in STD_LOGIC_VECTOR(15 downto 0);
res : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Hazard_Detector
Port ( STALL_OR_NOT_FU : in STD_LOGIC;
CUR_INST_CODE : in STD_LOGIC_VECTOR (4 downto 0);
CUR_INST_RS : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_RT : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_RD : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_FUNC : in STD_LOGIC_VECTOR (1 downto 0);
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0);
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0);
LAST_LAST_DM_VISIT_ADDR : in STD_LOGIC_VECTOR (15 downto 0);
CUR_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0);
CUR_DM_WRITE_DATA_SRC : in STD_LOGIC_VECTOR(1 downto 0);
JUMP_OR_NOT : in STD_LOGIC;
WRITE_PC_OR_NOT : out STD_LOGIC;
NEW_PC_SRC_SELEC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_IR_OR_NOT : out STD_LOGIC;
WRITE_IR_SRC_SELEC : out STD_LOGIC;
COMMAND_ORIGIN_OR_NOP : out STD_LOGIC;
DM_DATA_RESULT_SELEC : out STD_LOGIC;
IM_ADDR_SELEC : out STD_LOGIC;
IM_DATA_SELEC : out STD_LOGIC;
IM_READ_WRITE_SELEC : out STD_LOGIC_VECTOR(1 downto 0)
);
END COMPONENT;
COMPONENT Controller
Port ( INST_CODE : in STD_LOGIC_VECTOR(4 downto 0);
INST_RS : in STD_LOGIC_VECTOR(2 downto 0);
INST_RT : in STD_LOGIC_VECTOR(2 downto 0);
INST_RD : in STD_LOGIC_VECTOR(2 downto 0);
INST_FUNC : in STD_LOGIC_VECTOR(1 downto 0);
ALU_OP : out STD_LOGIC_VECTOR (3 downto 0);
ALU_A_SRC : out STD_LOGIC_VECTOR (2 downto 0);
ALU_B_SRC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_REGS_DEST : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_DM_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_RA_OR_NOT : out STD_LOGIC;
WRITE_IH_OR_NOT : out STD_LOGIC;
WRITE_T_OR_NOT : out STD_LOGIC;
WRITE_SP_OR_NOT : out STD_LOGIC;
WRITE_T_SRC : out STD_LOGIC;
DATA_MEM_READ_WRITE : out STD_LOGIC_VECTOR(1 downto 0);
REGS_WRITE_OR_NOT : out STD_LOGIC;
REGS_WRITE_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT Common_Register
port(
clk : in STD_LOGIC;
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
write_flag : in STD_LOGIC;
write_reg : in STD_LOGIC_VECTOR(2 downto 0);
write_data : in STD_LOGIC_VECTOR(15 downto 0);
a : out STD_LOGIC_VECTOR(15 downto 0);
b : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Comparator
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
write_t : in STD_LOGIC;
t : in STD_LOGIC_VECTOR(15 downto 0);
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(15 downto 0);
jump : out STD_LOGIC
);
END COMPONENT;
COMPONENT ID_EXE_Register
port(
clk : in STD_LOGIC;
--cmd cmd
command_origin_or_nop : in STD_LOGIC;
--common input
in_pc : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_a : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_b : in STD_LOGIC_VECTOR(15 downto 0);
in_imm : in STD_LOGIC_VECTOR(15 downto 0);
in_rs : in STD_LOGIC_VECTOR(2 downto 0);
in_rt : in STD_LOGIC_VECTOR(2 downto 0);
in_rd : in STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
in_alu : in STD_LOGIC_VECTOR(3 downto 0);
in_a_src : in STD_LOGIC_VECTOR(2 downto 0);
in_b_src : in STD_LOGIC_VECTOR(1 downto 0);
in_reg_result : in STD_LOGIC_VECTOR(1 downto 0);
in_mem_src : in STD_LOGIC_VECTOR(1 downto 0);
in_flag_RA : in STD_LOGIC;
in_flag_IH : in STD_LOGIC;
in_flag_T : in STD_LOGIC;
in_flag_SP : in STD_LOGIC;
in_T_src : in STD_LOGIC;
--mem cmd
in_mem_cmd : in STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
in_flag_reg : in STD_LOGIC;
in_reg_src : in STD_LOGIC_VECTOR(1 downto 0);
--common output
out_pc : out STD_LOGIC_VECTOR(15 downto 0);
out_imm : out STD_LOGIC_VECTOR(15 downto 0);
out_reg_a : out STD_LOGIC_VECTOR(15 downto 0);
out_reg_b : out STD_LOGIC_VECTOR(15 downto 0);
--memory data
out_mem_data : out STD_LOGIC_VECTOR(15 downto 0);
--result register
out_res_reg : out STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
out_alu : out STD_LOGIC_VECTOR(3 downto 0);
out_a_src : out STD_LOGIC_VECTOR(2 downto 0);
out_b_src : out STD_LOGIC_VECTOR(1 downto 0);
out_flag_RA : out STD_LOGIC;
out_flag_IH : out STD_LOGIC;
out_flag_T : out STD_LOGIC;
out_flag_SP : out STD_LOGIC;
out_T_src : out STD_LOGIC;
--mem cmd
out_mem_cmd : out STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
out_flag_reg : out STD_LOGIC;
out_reg_src : out STD_LOGIC_VECTOR(1 downto 0);
cur_rs_num : out STD_LOGIC_VECTOR(2 downto 0);
cur_rt_num : out STD_LOGIC_VECTOR(2 downto 0)
);
END COMPONENT;
COMPONENT alu
port(
a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(15 downto 0);
op : in STD_LOGIC_VECTOR(3 downto 0);
zf : out STD_LOGIC;
sf : out STD_LOGIC;
c : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Special_Register
port(
clk : in STD_LOGIC;
T_cmd_write : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
RA_cmd_write : in STD_LOGIC;
RA_src : in STD_LOGIC_VECTOR(15 downto 0);
IH_cmd_write : in STD_LOGIC;
IH_src : in STD_LOGIC_VECTOR(15 downto 0);
SP_cmd_write : in STD_LOGIC;
SP_src : in STD_LOGIC_VECTOR(15 downto 0);
T_value : out STD_LOGIC_VECTOR(15 downto 0);
RA_value : out STD_LOGIC_VECTOR(15 downto 0);
IH_value : out STD_LOGIC_VECTOR(15 downto 0);
SP_value : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Forward_Unit
Port ( -- current instruction info, if use reg as alu src, conflict may exist
CUR_RS_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0);
CUR_RT_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0);
CUR_ALU_A_SRC_SELECT : in STD_LOGIC_VECTOR (2 downto 0);
CUR_ALU_B_SRC_SELECT : in STD_LOGIC_VECTOR (1 downto 0);
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0);
-- last last instruction info, if write regs, conflict may exist
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
STALL_OR_NOT : out STD_LOGIC;
ALU_A_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0);
ALU_B_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT EXE_MEM_Register
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_REG_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0);
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0);
DATA_MEM_READ_WRITE_IN : in STD_LOGIC_VECTOR(1 downto 0);
REGS_READ_WRITE_IN : in STD_LOGIC;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0);
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_REG_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DATA_MEM_READ_WRITE_OUT : out STD_LOGIC_VECTOR(1 downto 0);
REGS_READ_WRITE_OUT : out STD_LOGIC;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT MEM_WB_Register
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_REGS_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0);
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0);
DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
REGS_READ_WRITE_IN : in STD_LOGIC;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0);
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_REGS_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
REGS_READ_WRITE_OUT : out STD_LOGIC;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
--controller, all to id/exe reg
signal alu_op_controller : std_logic_vector(3 downto 0) := ALU_NULL;
signal alu_a_src_select_controller : std_logic_vector(2 downto 0) := ALU_A_SRC_ZERO;
signal alu_b_src_select_controller : std_logic_vector(1 downto 0) := ALU_B_SRC_ZERO;
signal write_regs_dest_select_controller : std_logic_vector(1 downto 0) := WRITE_REGS_DEST_RS;
signal write_dm_data_src_select_controller : std_logic_vector(1 downto 0) := WRITE_DM_DATA_SRC_Z;
signal write_ra_or_not_select_controller : std_logic := WRITE_RA_NO;
signal write_ih_or_not_select_controller : std_logic := WRITE_IH_NO;
signal write_t_or_not_select_controller : std_logic := WRITE_T_NO;
signal write_sp_or_not_select_controller : std_logic := WRITE_SP_NO;
signal write_t_src_select_controller : std_logic := T_SRC_IS_SF;
signal data_mem_read_write_select_controller : std_logic_vector(1 downto 0) := MEM_NONE;
signal regs_read_write_select_controller : std_logic := WRITE_REGS_NO;
signal regs_write_data_src_select_controller : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- hazard detector
-- to PC reg
signal write_pc_or_not_hazard_detector : std_logic := WRITE_PC_YES;
-- to PC mux
signal new_pc_src_select_hazard_detector : std_logic_vector(1 downto 0) := NEW_PC_SRC_SELEC_PC_ADD_ONE;
-- to if/id reg
signal write_ir_or_not_hazard_detector : std_logic := WRITE_IR_YES;
signal write_ir_src_select_hazard_detector : std_logic := WRITE_IR_SRC_SELEC_ORIGIN;
-- to id/exe reg
signal command_origin_or_nop_hazard_detector : std_logic := COMMAND_ORIGIN;
-- to mem/wb reg
signal dm_visit_data_result_select_hazard_detector : std_logic := DM_DATA_RESULT_DM;
-- to im
signal im_visit_data_select_hazard_detector : std_logic :=IM_DATA_Z;
signal im_visit_addr_select_hazard_detector : std_logic := IM_ADDR_PC;
signal im_read_write_select_hazard_detector : std_logic_vector(1 downto 0) := MEM_READ;
-- forward unit
-- to hazard detector
signal stall_or_not_forward_unit : std_logic := STALL_NO;
-- to alu a src mux 2
signal alu_a_src_select_final_forward_unit : std_logic_vector(1 downto 0) := ALU_A_SRC_SELECT_FINAL_ORIGIN;
-- to alu b src mux 2
signal alu_b_src_select_final_forward_unit : std_logic_vector(1 downto 0) := ALU_B_SRC_SELECT_FINAL_ORIGIN;
-- comparator
-- to hazard detector
signal jump_or_not_comparator : std_logic := JUMP_FALSE;
-- if
-- PC to IM, PC Adder
signal pc_value_pc_reg_to_im : std_logic_vector(15 downto 0) := ZERO;
-- PC Adder to if/id reg, PC mux
signal pc_value_pc_adder_to_if_id_reg : std_logic_vector(15 downto 0) := ZERO;
-- IM to if/id reg
signal inst_im_to_if_id_reg : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- PC mux to PC
signal pc_value_pc_mux_to_pc : std_logic_vector(15 downto 0) := ZERO;
-- id
-- if/id reg to controller, imm extender, id/exe reg(rs, rt, rd),
--comparator(code), hazard detector, common regs(rs, st)
signal inst_code_if_id_reg_to_controller : std_logic_vector(4 downto 0) := NOP_INST(15 downto 11);
signal inst_rs_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(10 downto 8);
signal inst_rt_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(7 downto 5);
signal inst_rd_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(4 downto 2);
signal inst_func_if_id_reg_to_controller : std_logic_vector(1 downto 0) := NOP_INST(1 downto 0);
-- if/id reg to id/exe reg, PC IMM Adder, to special regs(RA)
signal pc_value_if_id_reg_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- imm extender to id/exe reg, PC IMM Adder
signal imm_imm_extend_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- PC IMM Adder to PC mux
signal pc_value_pc_imm_adder_to_pc_mux : std_logic_vector(15 downto 0) := ZERO;
-- common regs to id/exe reg, comparator(A), PC mux(A)
signal a_reg_common_regs_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
signal b_reg_common_regs_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- if/id reg to im
--signal inst_if_id_reg_to_im : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- if/id reg to forward unit
signal cur_rs_num_if_id_reg_to_forward_unit : std_logic_vector(2 downto 0) := "ZZZ";
signal cur_rt_num_if_id_reg_to_forward_unit : std_logic_vector(2 downto 0) := "ZZZ";
-- exe
-- id/exe reg to alu src mux 1
signal alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(2 downto 0) := ALU_A_SRC_ZERO;
signal alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1 : std_logic_vector(1 downto 0) := ALU_B_SRC_ZERO;
signal a_reg_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
signal b_reg_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
signal imm_id_exe_reg_to_alu_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
-- id/exe reg to exe/mem reg
signal pc_value_id_exe_reg_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
signal write_dm_data_id_exe_reg_to_exe_mem_reg : std_logic_vector(15 downto 0) := HIGH_RESIST;
signal regs_read_write_select_id_exe_reg_to_exe_mem_reg : std_logic := WRITE_REGS_NO;
signal write_regs_num_id_exe_reg_to_exe_mem_reg : std_logic_vector(2 downto 0) := "ZZZ";
signal regs_write_data_src_select_id_exe_reg_to_exe_mem_reg : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
signal data_mem_read_write_select_id_exe_reg_to_exe_mem_reg : std_logic_vector(1 downto 0) := MEM_NONE;
-- id/exe reg to alu
signal alu_op_id_exe_reg_to_alu : std_logic_vector(3 downto 0) := ALU_NULL;
-- id/exe to special regs, to comparator(write t or not)
signal write_t_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_T_NO;
signal write_t_src_select_id_exe_reg_to_special_regs : std_logic := T_SRC_IS_SF;
signal write_ra_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_RA_NO;
signal write_ih_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_IH_NO;
signal write_sp_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_SP_NO;
-- constant to alu src mux 1
signal all_zeros : std_logic_vector(15 downto 0) := ZERO;
-- special regs to alu src mux 1(SP)
signal sp_reg_special_regs_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
-- special regs to exe/mem reg(IH)
signal ih_reg_special_regs_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- special regs to comparator(T)
signal t_reg_special_regs_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- alu src mux 1 to alu src mux 2
signal alu_a_src_value_mux1_to_mux2 : std_logic_vector(15 downto 0) := ZERO;
signal alu_b_src_value_mux1_to_mux2 : std_logic_vector(15 downto 0) := ZERO;
-- alu mux 2 to alu
signal alu_a_src_alu_mux2_to_alu : std_logic_vector(15 downto 0) := ZERO;
signal alu_b_src_alu_mux2_to_alu : std_logic_vector(15 downto 0) := ZERO;
-- alu to exe/mem reg
signal alu_result_alu_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- alu to special regs(T)
signal alu_sf_alu_to_special_regs : std_logic := '0';
signal alu_zf_alu_to_special_regs : std_logic := '0';
-- mem in exe/mem reg
-- to RAM_Visitor
signal data_mem_read_write_select_exe_mem_reg_to_dm : std_logic_vector(1 downto 0) := MEM_NONE;
-- as data memory address, to mem/wb reg
signal alu_result_exe_mem_reg_to_dm : std_logic_vector(15 downto 0) := ZERO;
-- as data memory data, to mem/wb reg
signal write_dm_data_exe_mem_reg_to_dm : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- to mem/wb reg
signal regs_read_write_select_exe_mem_reg_to_mem_wb_reg : std_logic := WRITE_REGS_NO;
signal write_regs_num_exe_mem_reg_to_mem_wb_reg : std_logic_vector(2 downto 0) := "ZZZ";
signal regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
signal ih_reg_exe_mem_reg_to_mem_wb_reg : std_logic_vector(15 downto 0) := ZERO;
signal pc_value_exe_mem_reg_mem_wb_reg : std_logic_vector(15 downto 0) := ZERO;
-- lw/sw to IM
signal im_visit_addr_im_mux_to_im : std_logic_vector(15 downto 0);
signal im_visit_data_im_mux_to_im : std_logic_vector(15 downto 0);
-- DM to mem/wb reg
signal read_dm_data_dm_to_mem_wb_reg : std_logic_vector(15 downto 0);
signal dm_visit_data_dm_mux_to_mem_wb_reg : std_logic_vector(15 downto 0);
-- wb in mem/wb reg
-- to common regs write src mux
signal ih_reg_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
signal alu_result_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
--alse to special regs(IH, SP)
signal dm_data_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
-- also to alu src mux 2
signal pc_value_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
signal regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- to common regs
signal regs_read_write_select_mem_wb_reg_to_common_regs : std_logic := WRITE_REGS_NO;
signal write_regs_num_mem_wb_reg_to_common_regs : std_logic_vector(2 downto 0) := "ZZZ";
-- common regs write src mux to common regs
signal write_regs_data_src_mux_to_regs : std_logic_vector(15 downto 0) := ZERO;
-- not used
signal ra_reg_special_regs_to_where : std_logic_vector(15 downto 0) := ZERO;
signal watch_info : std_logic_vector(15 downto 0) := ZERO;
signal high_resist_port : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- signal write_pc_force : std_logic := '1';
-- signal write_ir_force : std_logic := '1';
-- signal write_ir_origin_force : std_logic := '0';
-- signal write_pc_add_one_force : std_logic_vector(1 downto 0) := "00";
signal led_ram_visitor_to_cpu_core : std_logic_vector(7 downto 0) := "00000000";
signal useless_pin : std_logic_vector(4 downto 0) := "11111";
signal CLK : std_logic := '1';
-- signal step_disp1 : std_logic_vector(6 downto 0) := "0111111";
-- signal step_disp1 : std_logic_vector(6 downto 0) := "0111111";
begin
Unit_CLK_MODULE : CLK_MODULE port map (
CLK_IN => CLK_IN,
CLK => CLK
);
Unit_New_PC_Src_Mux3 : MUX_3 port map (
-- PC + 1
SRC_1 => pc_value_pc_adder_to_if_id_reg,
-- PC + IMM
SRC_2 => pc_value_pc_imm_adder_to_pc_mux,
-- A reg
SRC_3 => a_reg_common_regs_to_id_exe_reg,
SELEC => new_pc_src_select_hazard_detector, --write_pc_add_one_force,--
OUTPUT => pc_value_pc_mux_to_pc
);
Unit_PC_Register : PC_Register port map (
PC_IN => pc_value_pc_mux_to_pc,
PC_OUT => pc_value_pc_reg_to_im,
WRITE_OR_NOT => write_pc_or_not_hazard_detector, --write_pc_force,--
CLK => CLK
);
Unit_PC_Adder : PC_Adder port map (
OLD_PC => pc_value_pc_reg_to_im,
NEW_PC => pc_value_pc_adder_to_if_id_reg
);
Unit_IM_Addr_Mux : MUX_2 port map(
SELEC => im_visit_addr_select_hazard_detector,
SRC_1 => pc_value_pc_reg_to_im,
SRC_2 => alu_result_exe_mem_reg_to_dm,
OUTPUT => im_visit_addr_im_mux_to_im
);
Unit_IM_Data_Mux : MUX_2 port map(
SELEC => im_visit_data_select_hazard_detector,
SRC_1 => high_resist_port,
SRC_2 => write_dm_data_exe_mem_reg_to_dm,
OUTPUT => im_visit_data_im_mux_to_im
);
Unit_RAM1_Visitor : RAM1_Visitor port map (
---input
clk => CLK,
DMemReadWrite => data_mem_read_write_select_exe_mem_reg_to_dm,
EXandMEM_AluRes => alu_result_exe_mem_reg_to_dm,
DataReady => com_data_ready,
WriteData => write_dm_data_exe_mem_reg_to_dm,
TSRE => com_tsre,
TBRE => com_tbre,
---output
RAM1_Enable => RAM1_EN,
RAM1_ReadEnable => RAM1_OE,
RAM1_WriteEnable => RAM1_WE,
SPort_WriteEnable => com_wrn,
SPort_ReadEnable => com_rdn,
DMemData => RAM1_Data,
DMemAddr => RAM1_Addr(15 downto 0)
);
Unit_RAM2_Visitor : RAM2_Visitor port map (
---input
clk => CLK,
DMemReadWrite => im_read_write_select_hazard_detector,
EXandMEM_AluRes => im_visit_addr_im_mux_to_im,
-- DataReady => useless_pin(4),
WriteData => im_visit_data_im_mux_to_im,
-- TSRE => useless_pin(3),
-- TBRE => useless_pin(2),
---output
RAM1_Enable => RAM2_EN,
RAM1_ReadEnable => RAM2_OE,
RAM1_WriteEnable => RAM2_WE,
-- SPort_WriteEnable => useless_pin(1),
-- SPort_ReadEnable => useless_pin(0),
DMemData => RAM2_Data,
DMemAddr => RAM2_Addr(15 downto 0)
);
RAM1_Addr(17 downto 16) <= "00";
RAM2_Addr(17 downto 16) <= "00";
-- LED(15 downto 8) <= led_ram_visitor_to_cpu_core;
Unit_IF_ID_Register : IF_ID_Register port map (
NEW_PC_IN => pc_value_pc_adder_to_if_id_reg,
WRITE_PC_OR_NOT => write_pc_or_not_hazard_detector,
NEW_PC_OUT => pc_value_if_id_reg_to_id_exe_reg,
CLK => CLK,
INST_IN => inst_im_to_if_id_reg,
WRITE_IR_OR_NOT => write_ir_or_not_hazard_detector, --write_ir_force,--
WRITE_IR_SRC_SELEC => write_ir_src_select_hazard_detector, --write_ir_origin_force,--
INST_OUT_CODE => inst_code_if_id_reg_to_controller,
INST_OUT_RS => inst_rs_if_id_reg_to_controller,
INST_OUT_RT => inst_rt_if_id_reg_to_controller,
INST_OUT_RD => inst_rd_if_id_reg_to_controller,
INST_OUT_FUNC => inst_func_if_id_reg_to_controller
);
-- detect before id, just after INST could be read rightly
Unit_Hazard_Detector : Hazard_Detector port map (
STALL_OR_NOT_FU => stall_or_not_forward_unit,
CUR_INST_CODE => inst_code_if_id_reg_to_controller,
CUR_INST_RS => inst_rs_if_id_reg_to_controller,
CUR_INST_RT => inst_rt_if_id_reg_to_controller,
CUR_INST_RD => inst_rd_if_id_reg_to_controller,
CUR_INST_FUNC => inst_func_if_id_reg_to_controller,
-- in id/exe reg
LAST_WRITE_REGS_OR_NOT => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
LAST_WRITE_REGS_TARGET => write_regs_num_id_exe_reg_to_exe_mem_reg,
LAST_VISIT_DM_OR_NOT => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
-- in exe/mem reg
LAST_LAST_WRITE_REGS_OR_NOT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
LAST_LAST_WRITE_REGS_TARGET => write_regs_num_exe_mem_reg_to_mem_wb_reg,
-- in exe/mem reg
LAST_LAST_VISIT_DM_OR_NOT => data_mem_read_write_select_exe_mem_reg_to_dm,
LAST_LAST_DM_VISIT_ADDR => alu_result_exe_mem_reg_to_dm,
CUR_DM_READ_WRITE => data_mem_read_write_select_controller,
CUR_DM_WRITE_DATA_SRC => write_dm_data_src_select_controller,
JUMP_OR_NOT => jump_or_not_comparator,
WRITE_PC_OR_NOT => write_pc_or_not_hazard_detector,
NEW_PC_SRC_SELEC => new_pc_src_select_hazard_detector,
WRITE_IR_OR_NOT => write_ir_or_not_hazard_detector,
WRITE_IR_SRC_SELEC => write_ir_src_select_hazard_detector,
COMMAND_ORIGIN_OR_NOP => command_origin_or_nop_hazard_detector,
DM_DATA_RESULT_SELEC => dm_visit_data_result_select_hazard_detector,
IM_ADDR_SELEC => im_visit_addr_select_hazard_detector,
IM_DATA_SELEC => im_visit_data_select_hazard_detector,
IM_READ_WRITE_SELEC => im_read_write_select_hazard_detector
);
Unit_Controller : Controller port map (
INST_CODE => inst_code_if_id_reg_to_controller,
INST_RS => inst_rs_if_id_reg_to_controller,
INST_RT => inst_rt_if_id_reg_to_controller,
INST_RD => inst_rd_if_id_reg_to_controller,
INST_FUNC => inst_func_if_id_reg_to_controller,
ALU_OP => alu_op_controller,
ALU_A_SRC => alu_a_src_select_controller,
ALU_B_SRC => alu_b_src_select_controller,
WRITE_REGS_DEST => write_regs_dest_select_controller,
WRITE_DM_DATA_SRC => write_dm_data_src_select_controller,
WRITE_RA_OR_NOT => write_ra_or_not_select_controller,
WRITE_IH_OR_NOT => write_ih_or_not_select_controller,
WRITE_T_OR_NOT => write_t_or_not_select_controller,
WRITE_SP_OR_NOT => write_sp_or_not_select_controller,
WRITE_T_SRC => write_t_src_select_controller,
DATA_MEM_READ_WRITE => data_mem_read_write_select_controller,
REGS_WRITE_OR_NOT => regs_read_write_select_controller,
REGS_WRITE_DATA_SRC => regs_write_data_src_select_controller
);
Unit_Imm_Extend : Imm_Extend port map (
code => inst_code_if_id_reg_to_controller,
rs => inst_rs_if_id_reg_to_controller,
rt => inst_rt_if_id_reg_to_controller,
rd => inst_rd_if_id_reg_to_controller,
func => inst_func_if_id_reg_to_controller,
imm => imm_imm_extend_to_id_exe_reg
);
Unit_adder : adder port map (
pc => pc_value_if_id_reg_to_id_exe_reg,
imm => imm_imm_extend_to_id_exe_reg,
res => pc_value_pc_imm_adder_to_pc_mux
);
Unit_Common_regs_write_src_Mux4 : MUX_4 port map (
-- ALU result
SRC_1 => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
-- DM data
SRC_2 => dm_data_mem_wb_reg_to_common_regs_write_src_mux,
-- IH
SRC_3 => ih_reg_mem_wb_reg_to_common_regs_write_src_mux,
-- PC
SRC_4 => pc_value_mem_wb_reg_to_common_regs_write_src_mux,
SELEC => regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux,
OUTPUT => write_regs_data_src_mux_to_regs
);
Unit_Common_Register : Common_Register port map (
clk => CLK,
rs => inst_rs_if_id_reg_to_controller,
rt => inst_rt_if_id_reg_to_controller,
write_flag => regs_read_write_select_mem_wb_reg_to_common_regs,
write_reg => write_regs_num_mem_wb_reg_to_common_regs,
write_data => write_regs_data_src_mux_to_regs,
a => a_reg_common_regs_to_id_exe_reg,
b => b_reg_common_regs_to_id_exe_reg
);
Unit_Comparator : Comparator port map (
code => inst_code_if_id_reg_to_controller,
write_t => write_t_or_not_select_id_exe_reg_to_special_regs,
t => t_reg_special_regs_to_exe_mem_reg,
-- could not be given as one value
T_src_SF => alu_sf_alu_to_special_regs,
T_src_ZF => alu_zf_alu_to_special_regs,
T_cmd_src => write_t_src_select_id_exe_reg_to_special_regs,
a => a_reg_common_regs_to_id_exe_reg,
jump => jump_or_not_comparator
);
Unit_ID_EXE_Register : ID_EXE_Register port map (
clk => CLK,
--cmd cmd
command_origin_or_nop => command_origin_or_nop_hazard_detector,
--common input
in_pc => pc_value_if_id_reg_to_id_exe_reg,
in_reg_a => a_reg_common_regs_to_id_exe_reg,
in_reg_b => b_reg_common_regs_to_id_exe_reg,
in_imm => imm_imm_extend_to_id_exe_reg,
in_rs => inst_rs_if_id_reg_to_controller,
in_rt => inst_rt_if_id_reg_to_controller,
in_rd => inst_rd_if_id_reg_to_controller,
--exe cmd
in_alu => alu_op_controller,
in_a_src => alu_a_src_select_controller,
in_b_src => alu_b_src_select_controller,
in_reg_result => write_regs_dest_select_controller,
in_mem_src => write_dm_data_src_select_controller,
in_flag_RA => write_ra_or_not_select_controller,
in_flag_IH => write_ih_or_not_select_controller,
in_flag_T => write_t_or_not_select_controller,
in_flag_SP => write_sp_or_not_select_controller,
in_T_src => write_t_src_select_controller,
--mem cmd
in_mem_cmd => data_mem_read_write_select_controller,
--wb cmd
in_flag_reg => regs_read_write_select_controller,
in_reg_src => regs_write_data_src_select_controller,
--common output
out_pc => pc_value_id_exe_reg_to_exe_mem_reg,
out_imm => imm_id_exe_reg_to_alu_src_mux_1,
out_reg_a => a_reg_id_exe_reg_to_alu_a_src_mux_1,
out_reg_b => b_reg_id_exe_reg_to_alu_a_src_mux_1,
--memory data
out_mem_data => write_dm_data_id_exe_reg_to_exe_mem_reg,
--result register
out_res_reg => write_regs_num_id_exe_reg_to_exe_mem_reg,
--exe cmd
out_alu => alu_op_id_exe_reg_to_alu,
out_a_src => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,
out_b_src => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,
out_flag_RA => write_ra_or_not_select_id_exe_reg_to_special_regs,
out_flag_IH => write_ih_or_not_select_id_exe_reg_to_special_regs,
out_flag_T => write_t_or_not_select_id_exe_reg_to_special_regs,
out_flag_SP => write_sp_or_not_select_id_exe_reg_to_special_regs,
out_T_src => write_t_src_select_id_exe_reg_to_special_regs,
--mem cmd
out_mem_cmd => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
--wb cmd
out_flag_reg => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
out_reg_src => regs_write_data_src_select_id_exe_reg_to_exe_mem_reg,
cur_rs_num => cur_rs_num_if_id_reg_to_forward_unit,
cur_rt_num => cur_rt_num_if_id_reg_to_forward_unit
);
all_zeros <= ZERO;
Unit_ALU_A_Src_Select1_Mux6 : MUX_6 port map (
-- A
SRC_1 => a_reg_id_exe_reg_to_alu_a_src_mux_1,
-- IMM
SRC_2 => imm_id_exe_reg_to_alu_src_mux_1,
-- 0
SRC_3 => all_zeros,
-- SP
SRC_4 => sp_reg_special_regs_to_alu_a_src_mux_1,
-- PC
SRC_5 => pc_value_id_exe_reg_to_exe_mem_reg,
-- IH
SRC_6 => ih_reg_special_regs_to_exe_mem_reg,
SELEC => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,
OUTPUT => alu_a_src_value_mux1_to_mux2
);
Unit_ALU_B_Src_Select1_Mux3 : MUX_3 port map (
-- B
SRC_1 => b_reg_id_exe_reg_to_alu_a_src_mux_1,
-- IMM
SRC_2 => imm_id_exe_reg_to_alu_src_mux_1,
-- 0
SRC_3 => all_zeros,
SELEC => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,
OUTPUT => alu_b_src_value_mux1_to_mux2
);
Unit_ALU_A_Src_Select2_Mux3 : MUX_3 port map (
-- origin, regs output
SRC_1 => alu_a_src_value_mux1_to_mux2,
-- exe/mem reg, alu result
SRC_2 => alu_result_exe_mem_reg_to_dm,
-- mem/wb reg, write back value
SRC_3 => write_regs_data_src_mux_to_regs,
SELEC => alu_a_src_select_final_forward_unit,
OUTPUT => alu_a_src_alu_mux2_to_alu
);
Unit_ALU_B_Src_Select2_Mux3 : MUX_3 port map (
-- origin, regs output
SRC_1 => alu_b_src_value_mux1_to_mux2,
-- exe/mem reg, alu result
SRC_2 => alu_result_exe_mem_reg_to_dm,
-- mem/wb reg, write back value
SRC_3 => write_regs_data_src_mux_to_regs,
SELEC => alu_b_src_select_final_forward_unit,
OUTPUT => alu_b_src_alu_mux2_to_alu
);
Unit_ALU : alu port map (
a => alu_a_src_alu_mux2_to_alu,
b => alu_b_src_alu_mux2_to_alu,
op => alu_op_id_exe_reg_to_alu,
zf => alu_zf_alu_to_special_regs,
sf => alu_sf_alu_to_special_regs,
c => alu_result_alu_to_exe_mem_reg
);
Unit_Special_Register : Special_Register port map (
clk => CLK,
T_cmd_write => write_t_or_not_select_id_exe_reg_to_special_regs,
T_cmd_src => write_t_src_select_id_exe_reg_to_special_regs,
T_src_SF => alu_sf_alu_to_special_regs,
T_src_ZF => alu_zf_alu_to_special_regs,
-- from controller, id/exe reg is too late
RA_cmd_write => write_ra_or_not_select_controller,
RA_src => pc_value_if_id_reg_to_id_exe_reg,
IH_cmd_write => write_ih_or_not_select_id_exe_reg_to_special_regs,
IH_src => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
SP_cmd_write => write_sp_or_not_select_id_exe_reg_to_special_regs,
SP_src => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
T_value => t_reg_special_regs_to_exe_mem_reg,
RA_value => ra_reg_special_regs_to_where,
IH_value => ih_reg_special_regs_to_exe_mem_reg,
SP_value => sp_reg_special_regs_to_alu_a_src_mux_1
);
-- judge before update id/exe reg, to stop next inst get in
Unit_Forward_Unit : Forward_Unit port map (
-- current instruction info, if use reg as alu src, conflict may exist
-- get from if/id reg
-- detect early, stop early
CUR_RS_REG_NUM => cur_rs_num_if_id_reg_to_forward_unit,--inst_rs_if_id_reg_to_controller,
CUR_RT_REG_NUM => cur_rt_num_if_id_reg_to_forward_unit,--inst_rt_if_id_reg_to_controller,
-- get it from controller, from id/exe reg is too late
CUR_ALU_A_SRC_SELECT => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,--alu_a_src_select_controller,
CUR_ALU_B_SRC_SELECT => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,--alu_b_src_select_controller,
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
-- from id/exe reg
--
--
LAST_WRITE_REGS_OR_NOT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,--regs_read_write_select_id_exe_reg_to_exe_mem_reg,
LAST_WRITE_REGS_TARGET => write_regs_num_exe_mem_reg_to_mem_wb_reg,--write_regs_num_id_exe_reg_to_exe_mem_reg,
LAST_DM_READ_WRITE => data_mem_read_write_select_exe_mem_reg_to_dm,--data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
-- last last instruction info, if write regs, conflict may exist
-- from exe/mem reg
LAST_LAST_WRITE_REGS_OR_NOT => regs_read_write_select_mem_wb_reg_to_common_regs, --regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
LAST_LAST_WRITE_REGS_TARGET => write_regs_num_mem_wb_reg_to_common_regs, --write_regs_num_exe_mem_reg_to_mem_wb_reg,
STALL_OR_NOT => stall_or_not_forward_unit,
ALU_A_SRC_SELECT_FINAL => alu_a_src_select_final_forward_unit,
ALU_B_SRC_SELECT_FINAL => alu_b_src_select_final_forward_unit
);
Unit_EXE_MEM_Register : EXE_MEM_Register port map (
CLK => CLK,
NEW_PC_IN => pc_value_id_exe_reg_to_exe_mem_reg,
WRITE_DM_DATA_IN => write_dm_data_id_exe_reg_to_exe_mem_reg,
WRITE_REG_NUM_IN => write_regs_num_id_exe_reg_to_exe_mem_reg,
ALU_RESULT_IN => alu_result_alu_to_exe_mem_reg,
IH_REG_IN => ih_reg_special_regs_to_exe_mem_reg,
DATA_MEM_READ_WRITE_IN => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
REGS_READ_WRITE_IN => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
REGS_WRITE_DATA_SRC_IN => regs_write_data_src_select_id_exe_reg_to_exe_mem_reg,
NEW_PC_OUT => pc_value_exe_mem_reg_mem_wb_reg,
WRITE_DM_DATA_OUT => write_dm_data_exe_mem_reg_to_dm,
WRITE_REG_NUM_OUT => write_regs_num_exe_mem_reg_to_mem_wb_reg,
ALU_RESULT_OUT => alu_result_exe_mem_reg_to_dm,
IH_REG_OUT => ih_reg_exe_mem_reg_to_mem_wb_reg,
DATA_MEM_READ_WRITE_OUT => data_mem_read_write_select_exe_mem_reg_to_dm,
REGS_READ_WRITE_OUT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
REGS_WRITE_DATA_SRC_OUT => regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg
);
Unit_DM_Data_Result_Mux : MUX_2 port map(
SELEC => dm_visit_data_result_select_hazard_detector,
SRC_1 => read_dm_data_dm_to_mem_wb_reg,
SRC_2 => inst_im_to_if_id_reg,
OUTPUT => dm_visit_data_dm_mux_to_mem_wb_reg
);
Unit_MEM_WB_Register : MEM_WB_Register port map (
CLK => CLK,
NEW_PC_IN => pc_value_exe_mem_reg_mem_wb_reg,
WRITE_REGS_NUM_IN => write_regs_num_exe_mem_reg_to_mem_wb_reg,
ALU_RESULT_IN => alu_result_exe_mem_reg_to_dm,
IH_REG_IN => ih_reg_exe_mem_reg_to_mem_wb_reg,
DM_DATA_IN => dm_visit_data_dm_mux_to_mem_wb_reg,
-- cmd
REGS_READ_WRITE_IN => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
REGS_WRITE_DATA_SRC_IN => regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg,
NEW_PC_OUT => pc_value_mem_wb_reg_to_common_regs_write_src_mux,
WRITE_REGS_NUM_OUT => write_regs_num_mem_wb_reg_to_common_regs,
ALU_RESULT_OUT => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
IH_REG_OUT => ih_reg_mem_wb_reg_to_common_regs_write_src_mux,
DM_DATA_OUT => dm_data_mem_wb_reg_to_common_regs_write_src_mux,
REGS_READ_WRITE_OUT => regs_read_write_select_mem_wb_reg_to_common_regs,
REGS_WRITE_DATA_SRC_OUT => regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux
);
read_dm_data_dm_to_mem_wb_reg <= RAM1_Data;
inst_im_to_if_id_reg <= RAM2_Data;
process (CLK, inst_im_to_if_id_reg, pc_value_pc_reg_to_im, write_pc_or_not_hazard_detector, write_ir_or_not_hazard_detector)
--variable step : integer := 0;
begin
if (CLK'event and CLK = '0') then
-- IF
watch_info <= watch_info + "0000000000000001";
-- LED(15 downto 11) <= inst_code_if_id_reg_to_controller;
-- LED(10 downto 8) <= inst_rs_if_id_reg_to_controller;
-- LED(7 downto 5) <= inst_rt_if_id_reg_to_controller;
-- LED(4 downto 2) <= inst_rd_if_id_reg_to_controller;
-- LED(1 downto 0) <= inst_func_if_id_reg_to_controller;
LED <= pc_value_pc_reg_to_im;
case DISP1 is
when "0111111" =>
DISP1 <= "0000110";
when "0000110" =>
DISP1 <= "1011011";
when "1011011" =>
DISP1 <= "1001111";
when "1001111" =>
DISP1 <= "1100110";
when "1100110" =>
DISP1 <= "1101101";
when "1101101" =>
DISP1 <= "1111101";
when "1111101" =>
DISP1 <= "0000111";
when "0000111" =>
DISP1 <= "1111111";
when "1111111" =>
DISP1 <= "1101111";
when "1101111" =>
DISP1 <= "0111111";
case DISP2 is
when "1101111" =>
DISP2 <= "0111111";
when "0111111" =>
DISP2 <= "0000110";
when "0000110" =>
DISP2 <= "1011011";
when "1011011" =>
DISP2 <= "1001111";
when "1001111" =>
DISP2 <= "1100110";
when "1100110" =>
DISP2 <= "1101101";
when "1101101" =>
DISP2 <= "1111101";
when "1111101" =>
DISP2 <= "0000111";
when "0000111" =>
DISP2 <= "1111111";
when "1111111" =>
DISP2 <= "1101111";
when others =>
DISP2 <= "0111111";
end case;
when others =>
DISP1 <= "0111111";
end case;
elsif (CLK = '1') then
high_resist_port <= HIGH_RESIST;
end if;
end process;
end Behavioral;
|
apache-2.0
|
HackLinux/THCO-MIPS-CPU
|
src/TestOfCpuCore.vhd
|
2
|
49386
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:24:17 11/24/2013
-- Design Name:
-- Module Name: D:/Src/Computer/computer_work/CPU/TestOfCpuCore.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CPU_CORE
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestOfCpuCore IS
END TestOfCpuCore;
ARCHITECTURE behavior OF TestOfCpuCore IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CPU_CORE
PORT(
CLK : IN std_logic;
RAM1_Addr : OUT std_logic_vector(17 downto 0);
RAM1_EN : OUT std_logic;
RAM1_WE : OUT std_logic;
RAM1_OE : OUT std_logic;
RAM1_Data : INOUT std_logic_vector(15 downto 0);
RAM2_Addr : OUT std_logic_vector(17 downto 0);
RAM2_EN : OUT std_logic;
RAM2_WE : OUT std_logic;
RAM2_OE : OUT std_logic;
RAM2_Data : INOUT std_logic_vector(15 downto 0);
com_data_ready : IN std_logic;
com_rdn : OUT std_logic;
com_tbre : IN std_logic;
com_tsre : IN std_logic;
com_wrn : OUT std_logic;
LED : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal com_data_ready : std_logic := '0';
signal com_tbre : std_logic := '0';
signal com_tsre : std_logic := '0';
--BiDirs
signal RAM1_Data : std_logic_vector(15 downto 0);
signal RAM2_Data : std_logic_vector(15 downto 0);
--Outputs
signal RAM1_Addr : std_logic_vector(17 downto 0);
signal RAM1_EN : std_logic;
signal RAM1_WE : std_logic;
signal RAM1_OE : std_logic;
signal RAM2_Addr : std_logic_vector(17 downto 0);
signal RAM2_EN : std_logic;
signal RAM2_WE : std_logic;
signal RAM2_OE : std_logic;
signal com_rdn : std_logic;
signal com_wrn : std_logic;
signal LED : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CPU_CORE PORT MAP (
CLK => CLK,
RAM1_Addr => RAM1_Addr,
RAM1_EN => RAM1_EN,
RAM1_WE => RAM1_WE,
RAM1_OE => RAM1_OE,
RAM1_Data => RAM1_Data,
RAM2_Addr => RAM2_Addr,
RAM2_EN => RAM2_EN,
RAM2_WE => RAM2_WE,
RAM2_OE => RAM2_OE,
RAM2_Data => RAM2_Data,
com_data_ready => com_data_ready,
com_rdn => com_rdn,
com_tbre => com_tbre,
com_tsre => com_tsre,
com_wrn => com_wrn,
LED => LED
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
-- insert stimulus here
wait for CLK_period/3;
-- SW到IM
RAM1_Data <= ZERO;
RAM2_Data <= "0110100101000000"; --LI R1 40 6940
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011000100100000"; --SLL R1 R1 0000 3120
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101010000000"; --LI R2 80
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101100101000000"; --SW R1 R2 0000
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101100000001"; --LI R3 01
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101100000010"; --LI R3 02
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101100000011"; --LI R3 03
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110101100000100"; --LI R3 04
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
--kernel
RAM1_Data <= ZERO;
RAM2_Data <= "0000000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0000000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0001000001000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1111000000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100100000010000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110010000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011011011000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100111000010000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000011";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000101";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100111100000011";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0001000001001010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011011011000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100111000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1001111000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110111000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "1110100011001100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0010000011111000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "1110111100000000"; --JR R7
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110111101000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- test of JR
-------------------------------------------TESTW
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111"; -- LI R6 BF
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0011011011000000"; -- SLL R6 R6 0x0000
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0100111000000001"; --ADDIU R6 0x0001
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "1001111000000000"; --LW R6 R0 0x0000
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110111000000001"; --LI R6 0x0001
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "1110100011001100"; --AND R0 R6
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0010000011111000"; --BEQZ R0 TESTW
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-------------------------------------------访存到IM内
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000001"; -- LI R0
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-- RAM1_Data <= ZERO;
--RAM2_Data <= "1001100101000001"; -- LW from IM OK
RAM2_Data <= "1101100100000001"; -- SW to
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100100000011";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100100000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100100000101";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100100000111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-------------------------------------------条件跳转 OK
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000001"; -- LI R0
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0010000000001111"; --BEQZ R0 1111
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
wait for CLK_period;
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000101";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-------------------------------------------写后读 OK
RAM1_Data <= ZERO;
RAM2_Data <= "1001100100000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000000101001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000000101001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000000101001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
-------------------------------------------写后读
RAM1_Data <= ZERO;
RAM2_Data <= "1110100000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000101000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110001000100001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1001100000100010";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1001100001000011";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000101000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110001000100001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000101000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110001000100001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110100000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110000101000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1110001000100001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
--kernel
RAM1_Data <= ZERO;
RAM2_Data <= "0000000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0000000000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0001000001000100";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100000000111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1111000000000001";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110100010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= NOP_INST;
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0110111010111111";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0011011011000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "0100111000010000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
RAM1_Data <= ZERO;
RAM2_Data <= "1101111000000000";
com_data_ready <= '1';
com_tbre <= '1';
com_tsre <= '1';
wait for CLK_period;
wait;
end process;
END;
|
apache-2.0
|
Fju/LeafySan
|
src/vhdl/interfaces/audio.vhdl
|
1
|
15754
|
-----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Audio Interface
-- Author : Jan Dürre
-- Last update : 18.04.2016
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity audio is
port (
-- global
clock : in std_ulogic;
clock_audio : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
-- IRQ handling
iobus_irq_left : out std_ulogic;
iobus_irq_right : out std_ulogic;
iobus_ack_left : in std_ulogic;
iobus_ack_right : in std_ulogic;
-- connections to audio codec
aud_xclk : out std_ulogic;
aud_bclk : in std_ulogic;
aud_adc_lrck : in std_ulogic;
aud_adc_dat : in std_ulogic;
aud_dac_lrck : in std_ulogic;
aud_dac_dat : out std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : inout std_logic
);
end entity audio;
architecture rtl of audio is
-- internal register for audiodata
signal audio_left_in : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_left_in_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_right_in : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_right_in_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_left_out : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_left_out_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_left_out_buf : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_left_out_buf_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_right_out : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_right_out_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_right_out_buf : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
signal audio_right_out_buf_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
-- counter for retrieval of serial audio data
signal counter_left : unsigned(to_log2(CW_AUDIO_SAMPLE)-1 downto 0);
signal counter_left_nxt : unsigned(to_log2(CW_AUDIO_SAMPLE)-1 downto 0);
signal counter_right : unsigned(to_log2(CW_AUDIO_SAMPLE)-1 downto 0);
signal counter_right_nxt : unsigned(to_log2(CW_AUDIO_SAMPLE)-1 downto 0);
-- register for interrupt signals
signal irq_left, irq_left_nxt : std_ulogic;
signal irq_right, irq_right_nxt : std_ulogic;
-- register for configuration purpose
signal config : std_ulogic_vector(7 downto 0); --bit 0: select mic-in; bit 1: activate mic-boost
signal config_nxt : std_ulogic_vector(7 downto 0);
signal config_old : std_ulogic_vector(7 downto 0);
signal config_old_nxt : std_ulogic_vector(7 downto 0);
signal last_bit_left : std_ulogic;
signal last_bit_left_nxt : std_ulogic;
signal last_bit_right : std_ulogic;
signal last_bit_right_nxt : std_ulogic;
-- connection signals to i2c master
signal i2c_busy : std_ulogic;
signal i2c_cs : std_ulogic;
signal i2c_mode : std_ulogic_vector(1 downto 0);
signal i2c_slave_addr : std_ulogic_vector(6 downto 0);
signal i2c_bytes_tx : unsigned(4 downto 0);
signal i2c_bytes_rx : unsigned(4 downto 0);
signal i2c_tx_data : std_ulogic_vector(7 downto 0);
signal i2c_tx_data_valid : std_ulogic;
signal i2c_rx_data : std_ulogic_vector(7 downto 0);
signal i2c_rx_data_valid : std_ulogic;
signal i2c_rx_data_en : std_ulogic;
signal i2c_error : std_ulogic;
component i2c_master is
generic (
GV_SYS_CLOCK_RATE : natural := 50000000;
GV_I2C_CLOCK_RATE : natural := 400000; -- standard mode: (100000) 100 kHz; fast mode: 400000 Hz (400 kHz)
GW_SLAVE_ADDR : natural := 7;
GV_MAX_BYTES : natural := 16;
GB_USE_INOUT : boolean := true;
GB_TIMEOUT : boolean := false
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
-- i2c master
i2c_clk : inout std_logic;
-- separated in / out
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
-- inout
i2c_dat : inout std_logic;
-- separated in / out
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
-- interface
busy : out std_ulogic;
cs : in std_ulogic;
mode : in std_ulogic_vector(1 downto 0); -- 00: only read; 01: only write; 10: first read, second write; 11: first write, second read
slave_addr : in std_ulogic_vector(GW_SLAVE_ADDR-1 downto 0);
bytes_tx : in unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
bytes_rx : in unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
tx_data : in std_ulogic_vector(7 downto 0);
tx_data_valid : in std_ulogic;
rx_data : out std_ulogic_vector(7 downto 0);
rx_data_valid : out std_ulogic;
rx_data_en : in std_ulogic;
error : out std_ulogic
);
end component i2c_master;
-- connection signals to acodec configurator
signal configurator_busy : std_ulogic;
signal configurator_reg_addr : std_ulogic_vector(6 downto 0);
signal configurator_reg_data : std_ulogic_vector(8 downto 0);
signal configurator_valid : std_ulogic;
component wm8731_configurator is
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
-- simple interface to write configurations to
busy : out std_ulogic;
reg_addr : in std_ulogic_vector(6 downto 0);
reg_data : in std_ulogic_vector(8 downto 0);
valid : in std_ulogic;
-- interface to i2c master
i2c_busy : in std_ulogic;
i2c_cs : out std_ulogic;
i2c_mode : out std_ulogic_vector(1 downto 0);
i2c_slave_addr : out std_ulogic_vector(6 downto 0);
i2c_bytes_tx : out unsigned(4 downto 0);
i2c_bytes_rx : out unsigned(4 downto 0);
i2c_tx_data : out std_ulogic_vector(7 downto 0);
i2c_tx_data_valid : out std_ulogic;
i2c_rx_data : in std_ulogic_vector(7 downto 0);
i2c_rx_data_valid : in std_ulogic;
i2c_rx_data_en : out std_ulogic;
i2c_error : in std_ulogic
);
end component wm8731_configurator;
-- connection signals for acodec_interface
signal ain_left_sync : std_ulogic;
signal ain_left_data : std_ulogic;
signal ain_right_sync : std_ulogic;
signal ain_right_data : std_ulogic;
signal aout_left_sync : std_ulogic;
signal aout_left_data : std_ulogic;
signal aout_right_sync : std_ulogic;
signal aout_right_data : std_ulogic;
component i2s_slave is
port (
-- general signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- input signals from adc
aud_bclk : in std_ulogic;
aud_adc_lrck : in std_ulogic;
aud_adc_dat : in std_ulogic;
-- output signals to dac
aud_dac_lrck : in std_ulogic;
aud_dac_dat : out std_ulogic;
-- audio sample inputs
ain_left_sync : out std_ulogic;
ain_left_data : out std_ulogic;
ain_right_sync : out std_ulogic;
ain_right_data : out std_ulogic;
-- audio sample outputs
aout_left_sync : in std_ulogic;
aout_left_data : in std_ulogic;
aout_right_sync : in std_ulogic;
aout_right_data : in std_ulogic
);
end component i2s_slave;
begin
aud_xclk <= clock_audio;
-- i2c master
i2c_master_inst : i2c_master
generic map (
GV_SYS_CLOCK_RATE => CV_SYS_CLOCK_RATE,
GV_I2C_CLOCK_RATE => 400000,
GW_SLAVE_ADDR => 7,
GV_MAX_BYTES => 16,
GB_USE_INOUT => true,
GB_TIMEOUT => false
)
port map (
clock => clock,
reset_n => reset_n,
i2c_clk => i2c_sclk,
i2c_clk_ctrl => open,
i2c_clk_in => '0',
i2c_clk_out => open,
i2c_dat => i2c_sdat,
i2c_dat_ctrl => open,
i2c_dat_in => '0',
i2c_dat_out => open,
busy => i2c_busy,
cs => i2c_cs,
mode => i2c_mode,
slave_addr => i2c_slave_addr,
bytes_tx => i2c_bytes_tx,
bytes_rx => i2c_bytes_rx,
tx_data => i2c_tx_data,
tx_data_valid => i2c_tx_data_valid,
rx_data => i2c_rx_data,
rx_data_valid => i2c_rx_data_valid,
rx_data_en => i2c_rx_data_en,
error => i2c_error
);
-- wm8731_configurator
acodec_configurator_inst : wm8731_configurator
port map (
clock => clock,
reset_n => reset_n,
busy => configurator_busy,
reg_addr => configurator_reg_addr,
reg_data => configurator_reg_data,
valid => configurator_valid,
i2c_busy => i2c_busy,
i2c_cs => i2c_cs,
i2c_mode => i2c_mode,
i2c_slave_addr => i2c_slave_addr,
i2c_bytes_tx => i2c_bytes_tx,
i2c_bytes_rx => i2c_bytes_rx,
i2c_tx_data => i2c_tx_data,
i2c_tx_data_valid => i2c_tx_data_valid,
i2c_rx_data => i2c_rx_data,
i2c_rx_data_valid => i2c_rx_data_valid,
i2c_rx_data_en => i2c_rx_data_en,
i2c_error => i2c_error
);
-- i2s_slave
i2s_slave_inst : i2s_slave
port map (
clock => clock,
reset_n => reset_n,
aud_bclk => aud_bclk,
aud_adc_lrck => aud_adc_lrck,
aud_adc_dat => aud_adc_dat,
aud_dac_lrck => aud_dac_lrck,
aud_dac_dat => aud_dac_dat,
ain_left_sync => ain_left_sync,
ain_left_data => ain_left_data,
ain_right_sync => ain_right_sync,
ain_right_data => ain_right_data,
aout_left_sync => aout_left_sync,
aout_left_data => aout_left_data,
aout_right_sync => aout_right_sync,
aout_right_data => aout_right_data);
-- register
process(clock, reset_n)
begin
if reset_n = '0' then
audio_left_in <= (others => '0');
audio_right_in <= (others => '0');
audio_left_out <= (others => '0');
audio_left_out_buf <= (others => '0');
audio_right_out <= (others => '0');
audio_right_out_buf <= (others => '0');
counter_left <= (others => '0');
counter_right <= (others => '0');
irq_left <= '0';
irq_right <= '0';
config <= (others => '0');
config_old <= (others => '0');
last_bit_left <= '0';
last_bit_right <= '0';
elsif rising_edge(clock) then
audio_left_in <= audio_left_in_nxt;
audio_right_in <= audio_right_in_nxt;
audio_left_out <= audio_left_out_nxt;
audio_left_out_buf <= audio_left_out_buf_nxt;
audio_right_out <= audio_right_out_nxt;
audio_right_out_buf <= audio_right_out_buf_nxt;
counter_left <= counter_left_nxt;
counter_right <= counter_right_nxt;
irq_left <= irq_left_nxt;
irq_right <= irq_right_nxt;
config <= config_nxt;
config_old <= config_old_nxt;
last_bit_left <= last_bit_left_nxt;
last_bit_right <= last_bit_right_nxt;
end if;
end process;
-- handling of incoming audio data --
iobus_irq_left <= irq_left;
iobus_irq_right <= irq_right;
-- counter
counter_left_nxt <= to_unsigned(CW_AUDIO_SAMPLE-1, counter_left'length) when ain_left_sync = '1' else
counter_left - to_unsigned(1, counter_left'length) when counter_left > to_unsigned(0, counter_left'length) else
counter_left;
counter_right_nxt <= to_unsigned(CW_AUDIO_SAMPLE-1, counter_right'length) when ain_right_sync = '1' else
counter_right - to_unsigned(1, counter_right'length) when counter_right > to_unsigned(0, counter_right'length) else
counter_right;
last_bit_left_nxt <= '1' when counter_left = to_unsigned(1, counter_left'length) else
'0';
last_bit_right_nxt <= '1' when counter_right = to_unsigned(1, counter_right'length) else
'0';
-- shift register
audio_left_in_nxt <= audio_left_in(CW_AUDIO_SAMPLE-2 downto 0) & ain_left_data when (ain_left_sync = '1') or (counter_left > to_unsigned(0, counter_left'length)) else
audio_left_in;
audio_right_in_nxt <= audio_right_in(CW_AUDIO_SAMPLE-2 downto 0) & ain_right_data when (ain_right_sync = '1') or (counter_right > to_unsigned(0, counter_right'length)) else
audio_right_in;
-- interrupt
irq_left_nxt <= '1' when last_bit_left = '1' else
'0' when iobus_ack_left = '1' else
irq_left;
irq_right_nxt <= '1' when last_bit_right = '1' else
'0' when iobus_ack_right = '1' else
irq_right;
-- buffer audio-data for serialization (to prevent change of data during serialization)
audio_left_out_buf_nxt <= audio_left_out when ain_left_sync = '1' else audio_left_out_buf;
audio_right_out_buf_nxt <= audio_right_out when ain_right_sync = '1' else audio_right_out_buf;
-- handling of outgoing audio data
aout_left_sync <= '1' when ain_left_sync = '1' else
'0';
aout_left_data <= audio_left_out(CW_AUDIO_SAMPLE-1) when ain_left_sync = '1' else
audio_left_out_buf(to_integer(counter_left)-1) when counter_left > to_unsigned(0, counter_left'length) else
'0';
aout_right_sync <= '1' when ain_right_sync = '1' else
'0';
aout_right_data <= audio_right_out(CW_AUDIO_SAMPLE-1) when ain_right_sync = '1' else
audio_right_out_buf(to_integer(counter_right)-1) when counter_right > to_unsigned(0, counter_right'length) else
'0';
configurator_reg_data <= "000010" & config(0) & '0' & config(1) when (config_old /= config) else
(others => '0');
configurator_reg_addr <= "0000100" when (config_old /= config) else
(others => '0');
configurator_valid <= '1' when ((configurator_busy = '0') and (config_old /= config)) else
'0';
config_old_nxt <= config when ((configurator_busy = '0') and (config_old /= config)) else
config_old;
-- iobus
process(iobus_cs, iobus_wr, iobus_addr, iobus_din, audio_left_out, audio_right_out, config, audio_left_in, audio_right_in)
begin
audio_left_out_nxt <= audio_left_out;
audio_right_out_nxt <= audio_right_out;
config_nxt <= config;
iobus_dout <= (others => '0');
-- chipselect
if iobus_cs = '1' then
-- write outgoing register / config reg
if iobus_wr = '1' then
-- left channel
if iobus_addr = std_ulogic_vector(to_unsigned(0, iobus_addr'length)) then
audio_left_out_nxt <= iobus_din(CW_AUDIO_SAMPLE-1 downto 0);
-- right channel
elsif iobus_addr = std_ulogic_vector(to_unsigned(1, iobus_addr'length)) then
audio_right_out_nxt <= iobus_din(CW_AUDIO_SAMPLE-1 downto 0);
-- config register
else
config_nxt <= iobus_din(config'length-1 downto 0);
end if;
--read register
else
-- left channel
if iobus_addr = std_ulogic_vector(to_unsigned(0, iobus_addr'length)) then
iobus_dout(CW_AUDIO_SAMPLE-1 downto 0) <= audio_left_in;
-- right channel
elsif iobus_addr = std_ulogic_vector(to_unsigned(1, iobus_addr'length)) then
iobus_dout(CW_AUDIO_SAMPLE-1 downto 0) <= audio_right_in;
-- config register
else
iobus_dout(config'length-1 downto 0) <= config;
end if;
end if; -- wr
end if; -- cs
end process;
end rtl;
|
apache-2.0
|
ahmed-mahran/hue
|
tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/AVR8/JTAG_OCD_Prg/Resync16b_TCK.vhd
|
4
|
1103
|
--**********************************************************************************************
-- Resynchronizer(16 bit,TCK clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end Resync16b_TCK;
architecture RTL of Resync16b_TCK is
signal DIn_Tmp : std_logic_vector(DIn'range);
begin
ResynchronizerStageOne:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(Falling edge)
DIn_Tmp <= DIn; -- Stage 1
end if;
end process;
ResynchronizerStageTwo:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(Rising edge)
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/RamRom_Atom2015.vhd
|
1
|
6607
|
--------------------------------------------------------------------------------
-- Copyright (c) 2016 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : RamRom_Atom2015
-- /___/ /\ Timestamp : 04/07/2016
-- \ \ / \
-- \___\/\___\
--
--Design Name: RamRom_Atom2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RamRom_Atom2015 is
generic (
InitBFFE : std_logic_vector(7 downto 0) := x"00";
InitBFFF : std_logic_vector(7 downto 0) := x"00"
);
port (clock : in std_logic;
reset_n : in std_logic;
-- signals from/to 6502
cpu_addr : in std_logic_vector (15 downto 0);
cpu_we : in std_logic;
cpu_dout : in std_logic_vector (7 downto 0);
cpu_din : out std_logic_vector (7 downto 0);
-- signals from/to external memory system
ExternCE : out std_logic;
ExternWE : out std_logic;
ExternA : out std_logic_vector (18 downto 0);
ExternDin : out std_logic_vector (7 downto 0);
ExternDout : in std_logic_vector (7 downto 0);
-- turbo mode control
turbo_in : in std_logic_vector(1 downto 0);
turbo_out : out std_logic_vector(1 downto 0)
);
end RamRom_Atom2015;
architecture behavioral of RamRom_Atom2015 is
signal BFFE_Enable : std_logic;
signal BFFF_Enable : std_logic;
signal RegBFFE : std_logic_vector (7 downto 0) := InitBFFE;
signal RegBFFF : std_logic_vector (7 downto 0) := InitBFFF;
signal WriteProt : std_logic; -- Write protects #A000, #C000-#FFFF
signal OSInRam : std_logic; -- #C000-#FFFF in RAM
signal OSRomBank : std_logic; -- bank0 or bank1
signal ExRamBank : std_logic_vector (1 downto 0); -- #4000-#7FFF bank select
signal RomLatch : std_logic_vector (2 downto 0); -- #A000-#AFFF bank select
signal turbo_in_old : std_logic_vector(1 downto 0);
begin
-- Mapping to External SRAM...
-- 0x00000 - Atom #A000 Bank 0
-- 0x01000 - Atom #A000 Bank 1
-- 0x02000 - Atom #A000 Bank 2
-- 0x03000 - Atom #A000 Bank 3
-- 0x04000 - Atom #A000 Bank 4
-- 0x05000 - Atom #A000 Bank 5
-- 0x06000 - Atom #A000 Bank 6
-- 0x07000 - Atom #A000 Bank 7
-- 0x08000 - BBC #6000 Bank 0 (ExtROM1)
-- 0x09000 - BBC #6000 Bank 1 (ExtROM1)
-- 0x0A000 - BBC #6000 Bank 2 (ExtROM1)
-- 0x0B000 - BBC #6000 Bank 3 (ExtROM1)
-- 0x0C000 - BBC #6000 Bank 4 (ExtROM1)
-- 0x0D000 - BBC #6000 Bank 5 (ExtROM1)
-- 0x0E000 - BBC #6000 Bank 6 (ExtROM1)
-- 0x0F000 - BBC #6000 Bank 7 (ExtROM1)
-- 0x10000 - Atom Basic (DskRomEn=1)
-- 0x11000 - Atom FP (DskRomEn=1)
-- 0x12000 - Atom MMC (DskRomEn=1)
-- 0x13000 - Atom Kernel (DskRomEn=1)
-- 0x14000 - Atom Basic (DskRomEn=0)
-- 0x15000 - Atom FP (DskRomEn=0)
-- 0x16000 - unused
-- 0x17000 - Atom Kernel (DskRomEn=0)
-- 0x18000 - unused
-- 0x19000 - BBC #7000 (ExtROM2)
-- 0x1A000 - BBC Basic 1/4
-- 0x1B000 - unused
-- 0x1C000 - BBC Basic 2/4
-- 0x1D000 - BBC Basic 3/4
-- 0x1E000 - BBC Basic 4/4
-- 0x1F000 - BBC MOS 3.0
-- currently only the following are implemented:
-- Atom #A000 banks 0..7
-- Atom Basic, FP, MMC, Kernel (DskRomEn=1)
-------------------------------------------------
-- External address decoding
--
-- external address bus is 18..0 (512KB)
-- bit 18 indicates an unmapped access (e.g to I/O space)
-- bit 17 selects between ROM (0) and RAM (1)
-- bits 16..0 select with 128KB block
-------------------------------------------------
ExternCE <= '1' when cpu_addr(15 downto 14) = "11" else
'1' when cpu_addr(15 downto 12) = "1010" else
'1' when cpu_addr(15) = '0' else
'0';
ExternWE <= '0' when cpu_addr(15 downto 14) = "11" and OsInRam = '0' else
'0' when cpu_addr(15) = '1' and WriteProt = '1' else
cpu_we;
ExternA <= "0010" & OSRomBank & cpu_addr(13 downto 0) when cpu_addr(15 downto 14) = "11" and OSInRam = '0' else
"01111" & cpu_addr(13 downto 0) when cpu_addr(15 downto 14) = "11" and OSInRam = '1' else
"0110" & RomLatch & cpu_addr(11 downto 0) when cpu_addr(15 downto 12) = "1010" else
"010" & ExRamBank & cpu_addr(13 downto 0) when cpu_addr(15 downto 14) = "01" else
"01110" & cpu_addr(13 downto 0) when cpu_addr(15 downto 14) = "00" else
"111" & cpu_addr(15 downto 0);
ExternDin <= cpu_dout;
cpu_din <= RegBFFE when BFFE_Enable = '1' else
RegBFFF when BFFF_Enable = '1' else
ExternDout;
-------------------------------------------------
-- RAM/ROM Board Registers
-------------------------------------------------
BFFE_Enable <= '1' when cpu_addr(15 downto 0) = "1011111111111110" else '0';
BFFF_Enable <= '1' when cpu_addr(15 downto 0) = "1011111111111111" else '0';
RomLatchProcess : process (reset_n, clock)
begin
if reset_n = '0' then
RegBFFE(3 downto 0) <= InitBFFE(3 downto 0);
RegBFFF <= InitBFFF;
elsif rising_edge(clock) then
if BFFE_Enable = '1' and cpu_we = '1' then
RegBFFE <= cpu_dout;
end if;
if BFFF_Enable = '1' and cpu_we = '1' then
RegBFFF <= cpu_dout;
end if;
-- Track changes to the manual turbo settings
if turbo_in /= turbo_in_old then
RegBFFE(6) <= turbo_in(0);
RegBFFE(5) <= turbo_in(1);
end if;
turbo_in_old <= turbo_in;
end if;
end process;
-------------------------------------------------
-- BFFE and BFFF registers
--
-- See http://stardot.org.uk/forums/viewtopic.php?f=44&t=9341
--
-------------------------------------------------
WriteProt <= RegBFFE(7);
OSRomBank <= RegBFFE(3);
OSInRam <= RegBFFE(2);
ExRamBank <= RegBFFE(1 downto 0);
RomLatch <= RegBFFF(2 downto 0);
turbo_out <= RegBFFE(5) & RegBFFE(6);
end behavioral;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/ROM/kernel_2015.vhd
|
1
|
172875
|
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity atomkernal is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of atomkernal is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"50";
when x"001" => DATA <= x"4C";
when x"002" => DATA <= x"4F";
when x"003" => DATA <= x"54";
when x"004" => DATA <= x"F5";
when x"005" => DATA <= x"4E";
when x"006" => DATA <= x"44";
when x"007" => DATA <= x"52";
when x"008" => DATA <= x"41";
when x"009" => DATA <= x"57";
when x"00A" => DATA <= x"F5";
when x"00B" => DATA <= x"42";
when x"00C" => DATA <= x"4D";
when x"00D" => DATA <= x"4F";
when x"00E" => DATA <= x"56";
when x"00F" => DATA <= x"45";
when x"010" => DATA <= x"F5";
when x"011" => DATA <= x"46";
when x"012" => DATA <= x"43";
when x"013" => DATA <= x"4C";
when x"014" => DATA <= x"45";
when x"015" => DATA <= x"41";
when x"016" => DATA <= x"52";
when x"017" => DATA <= x"F6";
when x"018" => DATA <= x"7B";
when x"019" => DATA <= x"44";
when x"01A" => DATA <= x"49";
when x"01B" => DATA <= x"4D";
when x"01C" => DATA <= x"F0";
when x"01D" => DATA <= x"AE";
when x"01E" => DATA <= x"5B";
when x"01F" => DATA <= x"F2";
when x"020" => DATA <= x"A1";
when x"021" => DATA <= x"4F";
when x"022" => DATA <= x"4C";
when x"023" => DATA <= x"44";
when x"024" => DATA <= x"F5";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"57";
when x"027" => DATA <= x"41";
when x"028" => DATA <= x"49";
when x"029" => DATA <= x"54";
when x"02A" => DATA <= x"F1";
when x"02B" => DATA <= x"4C";
when x"02C" => DATA <= x"C5";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"A4";
when x"02F" => DATA <= x"5E";
when x"030" => DATA <= x"B1";
when x"031" => DATA <= x"05";
when x"032" => DATA <= x"C9";
when x"033" => DATA <= x"40";
when x"034" => DATA <= x"90";
when x"035" => DATA <= x"12";
when x"036" => DATA <= x"C9";
when x"037" => DATA <= x"5B";
when x"038" => DATA <= x"B0";
when x"039" => DATA <= x"0E";
when x"03A" => DATA <= x"C8";
when x"03B" => DATA <= x"D1";
when x"03C" => DATA <= x"05";
when x"03D" => DATA <= x"D0";
when x"03E" => DATA <= x"09";
when x"03F" => DATA <= x"20";
when x"040" => DATA <= x"8B";
when x"041" => DATA <= x"F0";
when x"042" => DATA <= x"20";
when x"043" => DATA <= x"4F";
when x"044" => DATA <= x"C9";
when x"045" => DATA <= x"4C";
when x"046" => DATA <= x"62";
when x"047" => DATA <= x"C9";
when x"048" => DATA <= x"4C";
when x"049" => DATA <= x"24";
when x"04A" => DATA <= x"CA";
when x"04B" => DATA <= x"A2";
when x"04C" => DATA <= x"FF";
when x"04D" => DATA <= x"A4";
when x"04E" => DATA <= x"5E";
when x"04F" => DATA <= x"C6";
when x"050" => DATA <= x"5E";
when x"051" => DATA <= x"B1";
when x"052" => DATA <= x"05";
when x"053" => DATA <= x"C9";
when x"054" => DATA <= x"40";
when x"055" => DATA <= x"90";
when x"056" => DATA <= x"09";
when x"057" => DATA <= x"C9";
when x"058" => DATA <= x"5B";
when x"059" => DATA <= x"B0";
when x"05A" => DATA <= x"05";
when x"05B" => DATA <= x"C8";
when x"05C" => DATA <= x"D1";
when x"05D" => DATA <= x"05";
when x"05E" => DATA <= x"F0";
when x"05F" => DATA <= x"25";
when x"060" => DATA <= x"A4";
when x"061" => DATA <= x"5E";
when x"062" => DATA <= x"E8";
when x"063" => DATA <= x"C8";
when x"064" => DATA <= x"BD";
when x"065" => DATA <= x"00";
when x"066" => DATA <= x"F0";
when x"067" => DATA <= x"30";
when x"068" => DATA <= x"0C";
when x"069" => DATA <= x"D1";
when x"06A" => DATA <= x"05";
when x"06B" => DATA <= x"F0";
when x"06C" => DATA <= x"F5";
when x"06D" => DATA <= x"E8";
when x"06E" => DATA <= x"BD";
when x"06F" => DATA <= x"FF";
when x"070" => DATA <= x"EF";
when x"071" => DATA <= x"10";
when x"072" => DATA <= x"FA";
when x"073" => DATA <= x"D0";
when x"074" => DATA <= x"EB";
when x"075" => DATA <= x"85";
when x"076" => DATA <= x"53";
when x"077" => DATA <= x"BD";
when x"078" => DATA <= x"01";
when x"079" => DATA <= x"F0";
when x"07A" => DATA <= x"85";
when x"07B" => DATA <= x"52";
when x"07C" => DATA <= x"84";
when x"07D" => DATA <= x"03";
when x"07E" => DATA <= x"A6";
when x"07F" => DATA <= x"04";
when x"080" => DATA <= x"E6";
when x"081" => DATA <= x"5E";
when x"082" => DATA <= x"6C";
when x"083" => DATA <= x"52";
when x"084" => DATA <= x"00";
when x"085" => DATA <= x"20";
when x"086" => DATA <= x"8B";
when x"087" => DATA <= x"F0";
when x"088" => DATA <= x"4C";
when x"089" => DATA <= x"F1";
when x"08A" => DATA <= x"C3";
when x"08B" => DATA <= x"C8";
when x"08C" => DATA <= x"84";
when x"08D" => DATA <= x"03";
when x"08E" => DATA <= x"E9";
when x"08F" => DATA <= x"40";
when x"090" => DATA <= x"48";
when x"091" => DATA <= x"20";
when x"092" => DATA <= x"BC";
when x"093" => DATA <= x"C8";
when x"094" => DATA <= x"68";
when x"095" => DATA <= x"A8";
when x"096" => DATA <= x"B5";
when x"097" => DATA <= x"15";
when x"098" => DATA <= x"0A";
when x"099" => DATA <= x"36";
when x"09A" => DATA <= x"24";
when x"09B" => DATA <= x"0A";
when x"09C" => DATA <= x"36";
when x"09D" => DATA <= x"24";
when x"09E" => DATA <= x"18";
when x"09F" => DATA <= x"79";
when x"0A0" => DATA <= x"EB";
when x"0A1" => DATA <= x"02";
when x"0A2" => DATA <= x"95";
when x"0A3" => DATA <= x"15";
when x"0A4" => DATA <= x"B5";
when x"0A5" => DATA <= x"24";
when x"0A6" => DATA <= x"79";
when x"0A7" => DATA <= x"06";
when x"0A8" => DATA <= x"03";
when x"0A9" => DATA <= x"95";
when x"0AA" => DATA <= x"24";
when x"0AB" => DATA <= x"B0";
when x"0AC" => DATA <= x"D7";
when x"0AD" => DATA <= x"60";
when x"0AE" => DATA <= x"A5";
when x"0AF" => DATA <= x"01";
when x"0B0" => DATA <= x"05";
when x"0B1" => DATA <= x"02";
when x"0B2" => DATA <= x"F0";
when x"0B3" => DATA <= x"22";
when x"0B4" => DATA <= x"20";
when x"0B5" => DATA <= x"34";
when x"0B6" => DATA <= x"C4";
when x"0B7" => DATA <= x"90";
when x"0B8" => DATA <= x"1E";
when x"0B9" => DATA <= x"20";
when x"0BA" => DATA <= x"BC";
when x"0BB" => DATA <= x"C8";
when x"0BC" => DATA <= x"CA";
when x"0BD" => DATA <= x"CA";
when x"0BE" => DATA <= x"86";
when x"0BF" => DATA <= x"04";
when x"0C0" => DATA <= x"B4";
when x"0C1" => DATA <= x"16";
when x"0C2" => DATA <= x"38";
when x"0C3" => DATA <= x"A5";
when x"0C4" => DATA <= x"23";
when x"0C5" => DATA <= x"99";
when x"0C6" => DATA <= x"21";
when x"0C7" => DATA <= x"03";
when x"0C8" => DATA <= x"75";
when x"0C9" => DATA <= x"17";
when x"0CA" => DATA <= x"85";
when x"0CB" => DATA <= x"23";
when x"0CC" => DATA <= x"A5";
when x"0CD" => DATA <= x"24";
when x"0CE" => DATA <= x"99";
when x"0CF" => DATA <= x"3C";
when x"0D0" => DATA <= x"03";
when x"0D1" => DATA <= x"75";
when x"0D2" => DATA <= x"26";
when x"0D3" => DATA <= x"4C";
when x"0D4" => DATA <= x"19";
when x"0D5" => DATA <= x"F1";
when x"0D6" => DATA <= x"00";
when x"0D7" => DATA <= x"A4";
when x"0D8" => DATA <= x"03";
when x"0D9" => DATA <= x"B1";
when x"0DA" => DATA <= x"05";
when x"0DB" => DATA <= x"C9";
when x"0DC" => DATA <= x"40";
when x"0DD" => DATA <= x"90";
when x"0DE" => DATA <= x"F7";
when x"0DF" => DATA <= x"C9";
when x"0E0" => DATA <= x"5B";
when x"0E1" => DATA <= x"B0";
when x"0E2" => DATA <= x"F3";
when x"0E3" => DATA <= x"C8";
when x"0E4" => DATA <= x"D1";
when x"0E5" => DATA <= x"05";
when x"0E6" => DATA <= x"D0";
when x"0E7" => DATA <= x"EE";
when x"0E8" => DATA <= x"E9";
when x"0E9" => DATA <= x"40";
when x"0EA" => DATA <= x"48";
when x"0EB" => DATA <= x"C8";
when x"0EC" => DATA <= x"84";
when x"0ED" => DATA <= x"03";
when x"0EE" => DATA <= x"20";
when x"0EF" => DATA <= x"BC";
when x"0F0" => DATA <= x"C8";
when x"0F1" => DATA <= x"68";
when x"0F2" => DATA <= x"A8";
when x"0F3" => DATA <= x"A5";
when x"0F4" => DATA <= x"23";
when x"0F5" => DATA <= x"99";
when x"0F6" => DATA <= x"EB";
when x"0F7" => DATA <= x"02";
when x"0F8" => DATA <= x"A5";
when x"0F9" => DATA <= x"24";
when x"0FA" => DATA <= x"99";
when x"0FB" => DATA <= x"06";
when x"0FC" => DATA <= x"03";
when x"0FD" => DATA <= x"CA";
when x"0FE" => DATA <= x"86";
when x"0FF" => DATA <= x"04";
when x"100" => DATA <= x"B4";
when x"101" => DATA <= x"16";
when x"102" => DATA <= x"C8";
when x"103" => DATA <= x"D0";
when x"104" => DATA <= x"02";
when x"105" => DATA <= x"F6";
when x"106" => DATA <= x"25";
when x"107" => DATA <= x"98";
when x"108" => DATA <= x"0A";
when x"109" => DATA <= x"36";
when x"10A" => DATA <= x"25";
when x"10B" => DATA <= x"0A";
when x"10C" => DATA <= x"36";
when x"10D" => DATA <= x"25";
when x"10E" => DATA <= x"18";
when x"10F" => DATA <= x"65";
when x"110" => DATA <= x"23";
when x"111" => DATA <= x"85";
when x"112" => DATA <= x"23";
when x"113" => DATA <= x"B5";
when x"114" => DATA <= x"25";
when x"115" => DATA <= x"65";
when x"116" => DATA <= x"24";
when x"117" => DATA <= x"B0";
when x"118" => DATA <= x"BD";
when x"119" => DATA <= x"85";
when x"11A" => DATA <= x"24";
when x"11B" => DATA <= x"A0";
when x"11C" => DATA <= x"00";
when x"11D" => DATA <= x"A9";
when x"11E" => DATA <= x"AA";
when x"11F" => DATA <= x"91";
when x"120" => DATA <= x"23";
when x"121" => DATA <= x"D1";
when x"122" => DATA <= x"23";
when x"123" => DATA <= x"D0";
when x"124" => DATA <= x"F7";
when x"125" => DATA <= x"4A";
when x"126" => DATA <= x"91";
when x"127" => DATA <= x"23";
when x"128" => DATA <= x"D1";
when x"129" => DATA <= x"23";
when x"12A" => DATA <= x"D0";
when x"12B" => DATA <= x"F0";
when x"12C" => DATA <= x"20";
when x"12D" => DATA <= x"34";
when x"12E" => DATA <= x"C4";
when x"12F" => DATA <= x"B0";
when x"130" => DATA <= x"A5";
when x"131" => DATA <= x"A4";
when x"132" => DATA <= x"03";
when x"133" => DATA <= x"B1";
when x"134" => DATA <= x"05";
when x"135" => DATA <= x"C9";
when x"136" => DATA <= x"2C";
when x"137" => DATA <= x"D0";
when x"138" => DATA <= x"05";
when x"139" => DATA <= x"E6";
when x"13A" => DATA <= x"03";
when x"13B" => DATA <= x"4C";
when x"13C" => DATA <= x"AE";
when x"13D" => DATA <= x"F0";
when x"13E" => DATA <= x"4C";
when x"13F" => DATA <= x"58";
when x"140" => DATA <= x"C5";
when x"141" => DATA <= x"A5";
when x"142" => DATA <= x"0D";
when x"143" => DATA <= x"85";
when x"144" => DATA <= x"23";
when x"145" => DATA <= x"A5";
when x"146" => DATA <= x"0E";
when x"147" => DATA <= x"85";
when x"148" => DATA <= x"24";
when x"149" => DATA <= x"4C";
when x"14A" => DATA <= x"83";
when x"14B" => DATA <= x"CE";
when x"14C" => DATA <= x"20";
when x"14D" => DATA <= x"E4";
when x"14E" => DATA <= x"C4";
when x"14F" => DATA <= x"20";
when x"150" => DATA <= x"66";
when x"151" => DATA <= x"FE";
when x"152" => DATA <= x"4C";
when x"153" => DATA <= x"5B";
when x"154" => DATA <= x"C5";
when x"155" => DATA <= x"1C";
when x"156" => DATA <= x"8A";
when x"157" => DATA <= x"1C";
when x"158" => DATA <= x"23";
when x"159" => DATA <= x"5D";
when x"15A" => DATA <= x"8B";
when x"15B" => DATA <= x"1B";
when x"15C" => DATA <= x"A1";
when x"15D" => DATA <= x"9D";
when x"15E" => DATA <= x"8A";
when x"15F" => DATA <= x"1D";
when x"160" => DATA <= x"23";
when x"161" => DATA <= x"9D";
when x"162" => DATA <= x"8B";
when x"163" => DATA <= x"1D";
when x"164" => DATA <= x"A1";
when x"165" => DATA <= x"00";
when x"166" => DATA <= x"29";
when x"167" => DATA <= x"19";
when x"168" => DATA <= x"AE";
when x"169" => DATA <= x"69";
when x"16A" => DATA <= x"A8";
when x"16B" => DATA <= x"19";
when x"16C" => DATA <= x"23";
when x"16D" => DATA <= x"24";
when x"16E" => DATA <= x"53";
when x"16F" => DATA <= x"1B";
when x"170" => DATA <= x"23";
when x"171" => DATA <= x"24";
when x"172" => DATA <= x"53";
when x"173" => DATA <= x"19";
when x"174" => DATA <= x"A1";
when x"175" => DATA <= x"00";
when x"176" => DATA <= x"1A";
when x"177" => DATA <= x"5B";
when x"178" => DATA <= x"5B";
when x"179" => DATA <= x"A5";
when x"17A" => DATA <= x"69";
when x"17B" => DATA <= x"24";
when x"17C" => DATA <= x"24";
when x"17D" => DATA <= x"AE";
when x"17E" => DATA <= x"AE";
when x"17F" => DATA <= x"A8";
when x"180" => DATA <= x"AD";
when x"181" => DATA <= x"29";
when x"182" => DATA <= x"00";
when x"183" => DATA <= x"7C";
when x"184" => DATA <= x"00";
when x"185" => DATA <= x"15";
when x"186" => DATA <= x"9C";
when x"187" => DATA <= x"6D";
when x"188" => DATA <= x"9C";
when x"189" => DATA <= x"A5";
when x"18A" => DATA <= x"69";
when x"18B" => DATA <= x"29";
when x"18C" => DATA <= x"53";
when x"18D" => DATA <= x"84";
when x"18E" => DATA <= x"13";
when x"18F" => DATA <= x"34";
when x"190" => DATA <= x"11";
when x"191" => DATA <= x"A5";
when x"192" => DATA <= x"69";
when x"193" => DATA <= x"23";
when x"194" => DATA <= x"A0";
when x"195" => DATA <= x"D8";
when x"196" => DATA <= x"62";
when x"197" => DATA <= x"5A";
when x"198" => DATA <= x"48";
when x"199" => DATA <= x"26";
when x"19A" => DATA <= x"62";
when x"19B" => DATA <= x"94";
when x"19C" => DATA <= x"88";
when x"19D" => DATA <= x"54";
when x"19E" => DATA <= x"44";
when x"19F" => DATA <= x"C8";
when x"1A0" => DATA <= x"54";
when x"1A1" => DATA <= x"68";
when x"1A2" => DATA <= x"44";
when x"1A3" => DATA <= x"E8";
when x"1A4" => DATA <= x"94";
when x"1A5" => DATA <= x"00";
when x"1A6" => DATA <= x"B4";
when x"1A7" => DATA <= x"08";
when x"1A8" => DATA <= x"84";
when x"1A9" => DATA <= x"74";
when x"1AA" => DATA <= x"B4";
when x"1AB" => DATA <= x"28";
when x"1AC" => DATA <= x"6E";
when x"1AD" => DATA <= x"74";
when x"1AE" => DATA <= x"F4";
when x"1AF" => DATA <= x"CC";
when x"1B0" => DATA <= x"4A";
when x"1B1" => DATA <= x"72";
when x"1B2" => DATA <= x"F2";
when x"1B3" => DATA <= x"A4";
when x"1B4" => DATA <= x"8A";
when x"1B5" => DATA <= x"00";
when x"1B6" => DATA <= x"AA";
when x"1B7" => DATA <= x"A2";
when x"1B8" => DATA <= x"A2";
when x"1B9" => DATA <= x"74";
when x"1BA" => DATA <= x"74";
when x"1BB" => DATA <= x"74";
when x"1BC" => DATA <= x"72";
when x"1BD" => DATA <= x"44";
when x"1BE" => DATA <= x"68";
when x"1BF" => DATA <= x"B2";
when x"1C0" => DATA <= x"32";
when x"1C1" => DATA <= x"B2";
when x"1C2" => DATA <= x"00";
when x"1C3" => DATA <= x"22";
when x"1C4" => DATA <= x"00";
when x"1C5" => DATA <= x"1A";
when x"1C6" => DATA <= x"1A";
when x"1C7" => DATA <= x"26";
when x"1C8" => DATA <= x"26";
when x"1C9" => DATA <= x"72";
when x"1CA" => DATA <= x"72";
when x"1CB" => DATA <= x"88";
when x"1CC" => DATA <= x"C8";
when x"1CD" => DATA <= x"C4";
when x"1CE" => DATA <= x"CA";
when x"1CF" => DATA <= x"26";
when x"1D0" => DATA <= x"48";
when x"1D1" => DATA <= x"44";
when x"1D2" => DATA <= x"44";
when x"1D3" => DATA <= x"A2";
when x"1D4" => DATA <= x"C8";
when x"1D5" => DATA <= x"00";
when x"1D6" => DATA <= x"02";
when x"1D7" => DATA <= x"00";
when x"1D8" => DATA <= x"08";
when x"1D9" => DATA <= x"F2";
when x"1DA" => DATA <= x"FF";
when x"1DB" => DATA <= x"80";
when x"1DC" => DATA <= x"01";
when x"1DD" => DATA <= x"C0";
when x"1DE" => DATA <= x"E2";
when x"1DF" => DATA <= x"C0";
when x"1E0" => DATA <= x"C0";
when x"1E1" => DATA <= x"FF";
when x"1E2" => DATA <= x"00";
when x"1E3" => DATA <= x"00";
when x"1E4" => DATA <= x"08";
when x"1E5" => DATA <= x"00";
when x"1E6" => DATA <= x"10";
when x"1E7" => DATA <= x"80";
when x"1E8" => DATA <= x"40";
when x"1E9" => DATA <= x"C0";
when x"1EA" => DATA <= x"00";
when x"1EB" => DATA <= x"C0";
when x"1EC" => DATA <= x"00";
when x"1ED" => DATA <= x"40";
when x"1EE" => DATA <= x"00";
when x"1EF" => DATA <= x"00";
when x"1F0" => DATA <= x"E4";
when x"1F1" => DATA <= x"20";
when x"1F2" => DATA <= x"80";
when x"1F3" => DATA <= x"00";
when x"1F4" => DATA <= x"FC";
when x"1F5" => DATA <= x"00";
when x"1F6" => DATA <= x"08";
when x"1F7" => DATA <= x"08";
when x"1F8" => DATA <= x"F8";
when x"1F9" => DATA <= x"FC";
when x"1FA" => DATA <= x"F4";
when x"1FB" => DATA <= x"0C";
when x"1FC" => DATA <= x"10";
when x"1FD" => DATA <= x"04";
when x"1FE" => DATA <= x"F4";
when x"1FF" => DATA <= x"00";
when x"200" => DATA <= x"20";
when x"201" => DATA <= x"10";
when x"202" => DATA <= x"00";
when x"203" => DATA <= x"00";
when x"204" => DATA <= x"0F";
when x"205" => DATA <= x"01";
when x"206" => DATA <= x"01";
when x"207" => DATA <= x"01";
when x"208" => DATA <= x"11";
when x"209" => DATA <= x"11";
when x"20A" => DATA <= x"02";
when x"20B" => DATA <= x"02";
when x"20C" => DATA <= x"11";
when x"20D" => DATA <= x"11";
when x"20E" => DATA <= x"02";
when x"20F" => DATA <= x"12";
when x"210" => DATA <= x"02";
when x"211" => DATA <= x"00";
when x"212" => DATA <= x"08";
when x"213" => DATA <= x"10";
when x"214" => DATA <= x"18";
when x"215" => DATA <= x"20";
when x"216" => DATA <= x"28";
when x"217" => DATA <= x"30";
when x"218" => DATA <= x"38";
when x"219" => DATA <= x"40";
when x"21A" => DATA <= x"48";
when x"21B" => DATA <= x"50";
when x"21C" => DATA <= x"58";
when x"21D" => DATA <= x"60";
when x"21E" => DATA <= x"68";
when x"21F" => DATA <= x"70";
when x"220" => DATA <= x"78";
when x"221" => DATA <= x"80";
when x"222" => DATA <= x"88";
when x"223" => DATA <= x"90";
when x"224" => DATA <= x"98";
when x"225" => DATA <= x"A0";
when x"226" => DATA <= x"A8";
when x"227" => DATA <= x"B0";
when x"228" => DATA <= x"B8";
when x"229" => DATA <= x"C0";
when x"22A" => DATA <= x"C8";
when x"22B" => DATA <= x"D0";
when x"22C" => DATA <= x"D8";
when x"22D" => DATA <= x"E0";
when x"22E" => DATA <= x"E8";
when x"22F" => DATA <= x"F0";
when x"230" => DATA <= x"F8";
when x"231" => DATA <= x"0C";
when x"232" => DATA <= x"2C";
when x"233" => DATA <= x"4C";
when x"234" => DATA <= x"4C";
when x"235" => DATA <= x"8C";
when x"236" => DATA <= x"AC";
when x"237" => DATA <= x"CC";
when x"238" => DATA <= x"EC";
when x"239" => DATA <= x"8A";
when x"23A" => DATA <= x"9A";
when x"23B" => DATA <= x"AA";
when x"23C" => DATA <= x"BA";
when x"23D" => DATA <= x"CA";
when x"23E" => DATA <= x"DA";
when x"23F" => DATA <= x"EA";
when x"240" => DATA <= x"FA";
when x"241" => DATA <= x"0E";
when x"242" => DATA <= x"2E";
when x"243" => DATA <= x"4E";
when x"244" => DATA <= x"6E";
when x"245" => DATA <= x"8E";
when x"246" => DATA <= x"AE";
when x"247" => DATA <= x"CE";
when x"248" => DATA <= x"EE";
when x"249" => DATA <= x"0D";
when x"24A" => DATA <= x"2D";
when x"24B" => DATA <= x"4D";
when x"24C" => DATA <= x"6D";
when x"24D" => DATA <= x"8D";
when x"24E" => DATA <= x"AD";
when x"24F" => DATA <= x"CD";
when x"250" => DATA <= x"ED";
when x"251" => DATA <= x"0D";
when x"252" => DATA <= x"0D";
when x"253" => DATA <= x"0C";
when x"254" => DATA <= x"0D";
when x"255" => DATA <= x"0E";
when x"256" => DATA <= x"0D";
when x"257" => DATA <= x"0C";
when x"258" => DATA <= x"0D";
when x"259" => DATA <= x"0D";
when x"25A" => DATA <= x"0D";
when x"25B" => DATA <= x"0C";
when x"25C" => DATA <= x"0D";
when x"25D" => DATA <= x"0D";
when x"25E" => DATA <= x"0D";
when x"25F" => DATA <= x"0C";
when x"260" => DATA <= x"0D";
when x"261" => DATA <= x"0F";
when x"262" => DATA <= x"0D";
when x"263" => DATA <= x"0C";
when x"264" => DATA <= x"0D";
when x"265" => DATA <= x"09";
when x"266" => DATA <= x"0D";
when x"267" => DATA <= x"0C";
when x"268" => DATA <= x"0D";
when x"269" => DATA <= x"08";
when x"26A" => DATA <= x"0D";
when x"26B" => DATA <= x"0C";
when x"26C" => DATA <= x"0D";
when x"26D" => DATA <= x"08";
when x"26E" => DATA <= x"0D";
when x"26F" => DATA <= x"0C";
when x"270" => DATA <= x"0D";
when x"271" => DATA <= x"0F";
when x"272" => DATA <= x"06";
when x"273" => DATA <= x"0B";
when x"274" => DATA <= x"0B";
when x"275" => DATA <= x"04";
when x"276" => DATA <= x"0A";
when x"277" => DATA <= x"08";
when x"278" => DATA <= x"08";
when x"279" => DATA <= x"0D";
when x"27A" => DATA <= x"0D";
when x"27B" => DATA <= x"0D";
when x"27C" => DATA <= x"0D";
when x"27D" => DATA <= x"0D";
when x"27E" => DATA <= x"0F";
when x"27F" => DATA <= x"0D";
when x"280" => DATA <= x"0F";
when x"281" => DATA <= x"07";
when x"282" => DATA <= x"07";
when x"283" => DATA <= x"07";
when x"284" => DATA <= x"07";
when x"285" => DATA <= x"05";
when x"286" => DATA <= x"09";
when x"287" => DATA <= x"03";
when x"288" => DATA <= x"03";
when x"289" => DATA <= x"01";
when x"28A" => DATA <= x"01";
when x"28B" => DATA <= x"01";
when x"28C" => DATA <= x"01";
when x"28D" => DATA <= x"02";
when x"28E" => DATA <= x"01";
when x"28F" => DATA <= x"01";
when x"290" => DATA <= x"01";
when x"291" => DATA <= x"A4";
when x"292" => DATA <= x"03";
when x"293" => DATA <= x"B1";
when x"294" => DATA <= x"05";
when x"295" => DATA <= x"E6";
when x"296" => DATA <= x"03";
when x"297" => DATA <= x"C9";
when x"298" => DATA <= x"20";
when x"299" => DATA <= x"F0";
when x"29A" => DATA <= x"F6";
when x"29B" => DATA <= x"60";
when x"29C" => DATA <= x"E6";
when x"29D" => DATA <= x"03";
when x"29E" => DATA <= x"4C";
when x"29F" => DATA <= x"1B";
when x"2A0" => DATA <= x"C3";
when x"2A1" => DATA <= x"B1";
when x"2A2" => DATA <= x"05";
when x"2A3" => DATA <= x"C9";
when x"2A4" => DATA <= x"5D";
when x"2A5" => DATA <= x"F0";
when x"2A6" => DATA <= x"F5";
when x"2A7" => DATA <= x"20";
when x"2A8" => DATA <= x"F6";
when x"2A9" => DATA <= x"C4";
when x"2AA" => DATA <= x"C6";
when x"2AB" => DATA <= x"03";
when x"2AC" => DATA <= x"20";
when x"2AD" => DATA <= x"8E";
when x"2AE" => DATA <= x"F3";
when x"2AF" => DATA <= x"C6";
when x"2B0" => DATA <= x"03";
when x"2B1" => DATA <= x"A5";
when x"2B2" => DATA <= x"52";
when x"2B3" => DATA <= x"48";
when x"2B4" => DATA <= x"A5";
when x"2B5" => DATA <= x"53";
when x"2B6" => DATA <= x"48";
when x"2B7" => DATA <= x"AD";
when x"2B8" => DATA <= x"21";
when x"2B9" => DATA <= x"03";
when x"2BA" => DATA <= x"48";
when x"2BB" => DATA <= x"A9";
when x"2BC" => DATA <= x"00";
when x"2BD" => DATA <= x"85";
when x"2BE" => DATA <= x"34";
when x"2BF" => DATA <= x"85";
when x"2C0" => DATA <= x"43";
when x"2C1" => DATA <= x"A9";
when x"2C2" => DATA <= x"05";
when x"2C3" => DATA <= x"8D";
when x"2C4" => DATA <= x"21";
when x"2C5" => DATA <= x"03";
when x"2C6" => DATA <= x"A5";
when x"2C7" => DATA <= x"01";
when x"2C8" => DATA <= x"85";
when x"2C9" => DATA <= x"16";
when x"2CA" => DATA <= x"A5";
when x"2CB" => DATA <= x"02";
when x"2CC" => DATA <= x"85";
when x"2CD" => DATA <= x"25";
when x"2CE" => DATA <= x"20";
when x"2CF" => DATA <= x"89";
when x"2D0" => DATA <= x"C5";
when x"2D1" => DATA <= x"20";
when x"2D2" => DATA <= x"79";
when x"2D3" => DATA <= x"F3";
when x"2D4" => DATA <= x"68";
when x"2D5" => DATA <= x"8D";
when x"2D6" => DATA <= x"21";
when x"2D7" => DATA <= x"03";
when x"2D8" => DATA <= x"68";
when x"2D9" => DATA <= x"20";
when x"2DA" => DATA <= x"7E";
when x"2DB" => DATA <= x"F3";
when x"2DC" => DATA <= x"68";
when x"2DD" => DATA <= x"20";
when x"2DE" => DATA <= x"76";
when x"2DF" => DATA <= x"F3";
when x"2E0" => DATA <= x"A0";
when x"2E1" => DATA <= x"00";
when x"2E2" => DATA <= x"C4";
when x"2E3" => DATA <= x"00";
when x"2E4" => DATA <= x"F0";
when x"2E5" => DATA <= x"09";
when x"2E6" => DATA <= x"B9";
when x"2E7" => DATA <= x"66";
when x"2E8" => DATA <= x"00";
when x"2E9" => DATA <= x"20";
when x"2EA" => DATA <= x"76";
when x"2EB" => DATA <= x"F3";
when x"2EC" => DATA <= x"C8";
when x"2ED" => DATA <= x"D0";
when x"2EE" => DATA <= x"F3";
when x"2EF" => DATA <= x"C0";
when x"2F0" => DATA <= x"03";
when x"2F1" => DATA <= x"F0";
when x"2F2" => DATA <= x"0C";
when x"2F3" => DATA <= x"20";
when x"2F4" => DATA <= x"79";
when x"2F5" => DATA <= x"F3";
when x"2F6" => DATA <= x"20";
when x"2F7" => DATA <= x"4C";
when x"2F8" => DATA <= x"CA";
when x"2F9" => DATA <= x"20";
when x"2FA" => DATA <= x"4C";
when x"2FB" => DATA <= x"CA";
when x"2FC" => DATA <= x"C8";
when x"2FD" => DATA <= x"D0";
when x"2FE" => DATA <= x"F0";
when x"2FF" => DATA <= x"A0";
when x"300" => DATA <= x"00";
when x"301" => DATA <= x"B1";
when x"302" => DATA <= x"05";
when x"303" => DATA <= x"C9";
when x"304" => DATA <= x"3B";
when x"305" => DATA <= x"F0";
when x"306" => DATA <= x"0A";
when x"307" => DATA <= x"C9";
when x"308" => DATA <= x"0D";
when x"309" => DATA <= x"F0";
when x"30A" => DATA <= x"06";
when x"30B" => DATA <= x"20";
when x"30C" => DATA <= x"4C";
when x"30D" => DATA <= x"CA";
when x"30E" => DATA <= x"C8";
when x"30F" => DATA <= x"D0";
when x"310" => DATA <= x"F0";
when x"311" => DATA <= x"20";
when x"312" => DATA <= x"54";
when x"313" => DATA <= x"CD";
when x"314" => DATA <= x"20";
when x"315" => DATA <= x"E4";
when x"316" => DATA <= x"C4";
when x"317" => DATA <= x"88";
when x"318" => DATA <= x"B1";
when x"319" => DATA <= x"05";
when x"31A" => DATA <= x"C8";
when x"31B" => DATA <= x"C9";
when x"31C" => DATA <= x"3B";
when x"31D" => DATA <= x"F0";
when x"31E" => DATA <= x"0C";
when x"31F" => DATA <= x"A5";
when x"320" => DATA <= x"06";
when x"321" => DATA <= x"C9";
when x"322" => DATA <= x"01";
when x"323" => DATA <= x"D0";
when x"324" => DATA <= x"03";
when x"325" => DATA <= x"4C";
when x"326" => DATA <= x"CF";
when x"327" => DATA <= x"C2";
when x"328" => DATA <= x"20";
when x"329" => DATA <= x"1D";
when x"32A" => DATA <= x"C5";
when x"32B" => DATA <= x"4C";
when x"32C" => DATA <= x"A1";
when x"32D" => DATA <= x"F2";
when x"32E" => DATA <= x"20";
when x"32F" => DATA <= x"91";
when x"330" => DATA <= x"F2";
when x"331" => DATA <= x"85";
when x"332" => DATA <= x"66";
when x"333" => DATA <= x"20";
when x"334" => DATA <= x"91";
when x"335" => DATA <= x"F2";
when x"336" => DATA <= x"C5";
when x"337" => DATA <= x"66";
when x"338" => DATA <= x"D0";
when x"339" => DATA <= x"10";
when x"33A" => DATA <= x"C9";
when x"33B" => DATA <= x"40";
when x"33C" => DATA <= x"90";
when x"33D" => DATA <= x"0C";
when x"33E" => DATA <= x"C9";
when x"33F" => DATA <= x"5B";
when x"340" => DATA <= x"B0";
when x"341" => DATA <= x"08";
when x"342" => DATA <= x"38";
when x"343" => DATA <= x"20";
when x"344" => DATA <= x"8E";
when x"345" => DATA <= x"F0";
when x"346" => DATA <= x"20";
when x"347" => DATA <= x"CB";
when x"348" => DATA <= x"C3";
when x"349" => DATA <= x"A0";
when x"34A" => DATA <= x"00";
when x"34B" => DATA <= x"AD";
when x"34C" => DATA <= x"31";
when x"34D" => DATA <= x"03";
when x"34E" => DATA <= x"91";
when x"34F" => DATA <= x"52";
when x"350" => DATA <= x"AD";
when x"351" => DATA <= x"4C";
when x"352" => DATA <= x"03";
when x"353" => DATA <= x"C8";
when x"354" => DATA <= x"91";
when x"355" => DATA <= x"52";
when x"356" => DATA <= x"A9";
when x"357" => DATA <= x"00";
when x"358" => DATA <= x"C8";
when x"359" => DATA <= x"91";
when x"35A" => DATA <= x"52";
when x"35B" => DATA <= x"C8";
when x"35C" => DATA <= x"91";
when x"35D" => DATA <= x"52";
when x"35E" => DATA <= x"D0";
when x"35F" => DATA <= x"36";
when x"360" => DATA <= x"20";
when x"361" => DATA <= x"91";
when x"362" => DATA <= x"F2";
when x"363" => DATA <= x"C9";
when x"364" => DATA <= x"3B";
when x"365" => DATA <= x"F0";
when x"366" => DATA <= x"04";
when x"367" => DATA <= x"C9";
when x"368" => DATA <= x"0D";
when x"369" => DATA <= x"D0";
when x"36A" => DATA <= x"F5";
when x"36B" => DATA <= x"AD";
when x"36C" => DATA <= x"31";
when x"36D" => DATA <= x"03";
when x"36E" => DATA <= x"85";
when x"36F" => DATA <= x"52";
when x"370" => DATA <= x"AD";
when x"371" => DATA <= x"4C";
when x"372" => DATA <= x"03";
when x"373" => DATA <= x"85";
when x"374" => DATA <= x"53";
when x"375" => DATA <= x"60";
when x"376" => DATA <= x"20";
when x"377" => DATA <= x"7E";
when x"378" => DATA <= x"F3";
when x"379" => DATA <= x"A9";
when x"37A" => DATA <= x"20";
when x"37B" => DATA <= x"4C";
when x"37C" => DATA <= x"4C";
when x"37D" => DATA <= x"CA";
when x"37E" => DATA <= x"A2";
when x"37F" => DATA <= x"FF";
when x"380" => DATA <= x"48";
when x"381" => DATA <= x"4A";
when x"382" => DATA <= x"4A";
when x"383" => DATA <= x"4A";
when x"384" => DATA <= x"4A";
when x"385" => DATA <= x"20";
when x"386" => DATA <= x"F9";
when x"387" => DATA <= x"C5";
when x"388" => DATA <= x"68";
when x"389" => DATA <= x"29";
when x"38A" => DATA <= x"0F";
when x"38B" => DATA <= x"4C";
when x"38C" => DATA <= x"F9";
when x"38D" => DATA <= x"C5";
when x"38E" => DATA <= x"A2";
when x"38F" => DATA <= x"00";
when x"390" => DATA <= x"86";
when x"391" => DATA <= x"00";
when x"392" => DATA <= x"86";
when x"393" => DATA <= x"64";
when x"394" => DATA <= x"86";
when x"395" => DATA <= x"65";
when x"396" => DATA <= x"20";
when x"397" => DATA <= x"91";
when x"398" => DATA <= x"F2";
when x"399" => DATA <= x"C9";
when x"39A" => DATA <= x"3A";
when x"39B" => DATA <= x"F0";
when x"39C" => DATA <= x"91";
when x"39D" => DATA <= x"C9";
when x"39E" => DATA <= x"3B";
when x"39F" => DATA <= x"F0";
when x"3A0" => DATA <= x"CA";
when x"3A1" => DATA <= x"C9";
when x"3A2" => DATA <= x"0D";
when x"3A3" => DATA <= x"F0";
when x"3A4" => DATA <= x"C6";
when x"3A5" => DATA <= x"C9";
when x"3A6" => DATA <= x"5C";
when x"3A7" => DATA <= x"F0";
when x"3A8" => DATA <= x"B7";
when x"3A9" => DATA <= x"A0";
when x"3AA" => DATA <= x"05";
when x"3AB" => DATA <= x"38";
when x"3AC" => DATA <= x"69";
when x"3AD" => DATA <= x"00";
when x"3AE" => DATA <= x"0A";
when x"3AF" => DATA <= x"0A";
when x"3B0" => DATA <= x"0A";
when x"3B1" => DATA <= x"0A";
when x"3B2" => DATA <= x"26";
when x"3B3" => DATA <= x"6A";
when x"3B4" => DATA <= x"26";
when x"3B5" => DATA <= x"69";
when x"3B6" => DATA <= x"88";
when x"3B7" => DATA <= x"D0";
when x"3B8" => DATA <= x"F8";
when x"3B9" => DATA <= x"E8";
when x"3BA" => DATA <= x"E0";
when x"3BB" => DATA <= x"03";
when x"3BC" => DATA <= x"D0";
when x"3BD" => DATA <= x"D8";
when x"3BE" => DATA <= x"06";
when x"3BF" => DATA <= x"6A";
when x"3C0" => DATA <= x"26";
when x"3C1" => DATA <= x"69";
when x"3C2" => DATA <= x"A2";
when x"3C3" => DATA <= x"40";
when x"3C4" => DATA <= x"A5";
when x"3C5" => DATA <= x"69";
when x"3C6" => DATA <= x"DD";
when x"3C7" => DATA <= x"54";
when x"3C8" => DATA <= x"F1";
when x"3C9" => DATA <= x"F0";
when x"3CA" => DATA <= x"04";
when x"3CB" => DATA <= x"CA";
when x"3CC" => DATA <= x"D0";
when x"3CD" => DATA <= x"F8";
when x"3CE" => DATA <= x"00";
when x"3CF" => DATA <= x"BC";
when x"3D0" => DATA <= x"94";
when x"3D1" => DATA <= x"F1";
when x"3D2" => DATA <= x"C4";
when x"3D3" => DATA <= x"6A";
when x"3D4" => DATA <= x"D0";
when x"3D5" => DATA <= x"F5";
when x"3D6" => DATA <= x"BD";
when x"3D7" => DATA <= x"10";
when x"3D8" => DATA <= x"F2";
when x"3D9" => DATA <= x"85";
when x"3DA" => DATA <= x"66";
when x"3DB" => DATA <= x"BC";
when x"3DC" => DATA <= x"50";
when x"3DD" => DATA <= x"F2";
when x"3DE" => DATA <= x"84";
when x"3DF" => DATA <= x"0F";
when x"3E0" => DATA <= x"66";
when x"3E1" => DATA <= x"64";
when x"3E2" => DATA <= x"66";
when x"3E3" => DATA <= x"65";
when x"3E4" => DATA <= x"88";
when x"3E5" => DATA <= x"D0";
when x"3E6" => DATA <= x"F9";
when x"3E7" => DATA <= x"A4";
when x"3E8" => DATA <= x"0F";
when x"3E9" => DATA <= x"C0";
when x"3EA" => DATA <= x"0D";
when x"3EB" => DATA <= x"D0";
when x"3EC" => DATA <= x"05";
when x"3ED" => DATA <= x"A2";
when x"3EE" => DATA <= x"00";
when x"3EF" => DATA <= x"4C";
when x"3F0" => DATA <= x"9B";
when x"3F1" => DATA <= x"F4";
when x"3F2" => DATA <= x"20";
when x"3F3" => DATA <= x"91";
when x"3F4" => DATA <= x"F2";
when x"3F5" => DATA <= x"C9";
when x"3F6" => DATA <= x"40";
when x"3F7" => DATA <= x"F0";
when x"3F8" => DATA <= x"5B";
when x"3F9" => DATA <= x"C9";
when x"3FA" => DATA <= x"28";
when x"3FB" => DATA <= x"F0";
when x"3FC" => DATA <= x"65";
when x"3FD" => DATA <= x"A2";
when x"3FE" => DATA <= x"01";
when x"3FF" => DATA <= x"C9";
when x"400" => DATA <= x"41";
when x"401" => DATA <= x"F0";
when x"402" => DATA <= x"EC";
when x"403" => DATA <= x"C6";
when x"404" => DATA <= x"03";
when x"405" => DATA <= x"20";
when x"406" => DATA <= x"8B";
when x"407" => DATA <= x"C7";
when x"408" => DATA <= x"20";
when x"409" => DATA <= x"91";
when x"40A" => DATA <= x"F2";
when x"40B" => DATA <= x"C9";
when x"40C" => DATA <= x"2C";
when x"40D" => DATA <= x"D0";
when x"40E" => DATA <= x"31";
when x"40F" => DATA <= x"20";
when x"410" => DATA <= x"91";
when x"411" => DATA <= x"F2";
when x"412" => DATA <= x"A4";
when x"413" => DATA <= x"25";
when x"414" => DATA <= x"F0";
when x"415" => DATA <= x"15";
when x"416" => DATA <= x"A2";
when x"417" => DATA <= x"09";
when x"418" => DATA <= x"C9";
when x"419" => DATA <= x"58";
when x"41A" => DATA <= x"F0";
when x"41B" => DATA <= x"7F";
when x"41C" => DATA <= x"CA";
when x"41D" => DATA <= x"C9";
when x"41E" => DATA <= x"59";
when x"41F" => DATA <= x"D0";
when x"420" => DATA <= x"79";
when x"421" => DATA <= x"A5";
when x"422" => DATA <= x"0F";
when x"423" => DATA <= x"C9";
when x"424" => DATA <= x"09";
when x"425" => DATA <= x"D0";
when x"426" => DATA <= x"74";
when x"427" => DATA <= x"A2";
when x"428" => DATA <= x"0E";
when x"429" => DATA <= x"D0";
when x"42A" => DATA <= x"70";
when x"42B" => DATA <= x"A2";
when x"42C" => DATA <= x"04";
when x"42D" => DATA <= x"C9";
when x"42E" => DATA <= x"58";
when x"42F" => DATA <= x"F0";
when x"430" => DATA <= x"6A";
when x"431" => DATA <= x"C9";
when x"432" => DATA <= x"59";
when x"433" => DATA <= x"D0";
when x"434" => DATA <= x"65";
when x"435" => DATA <= x"CA";
when x"436" => DATA <= x"A4";
when x"437" => DATA <= x"0F";
when x"438" => DATA <= x"C0";
when x"439" => DATA <= x"03";
when x"43A" => DATA <= x"B0";
when x"43B" => DATA <= x"5F";
when x"43C" => DATA <= x"A2";
when x"43D" => DATA <= x"08";
when x"43E" => DATA <= x"D0";
when x"43F" => DATA <= x"5B";
when x"440" => DATA <= x"C6";
when x"441" => DATA <= x"03";
when x"442" => DATA <= x"A2";
when x"443" => DATA <= x"02";
when x"444" => DATA <= x"A4";
when x"445" => DATA <= x"0F";
when x"446" => DATA <= x"C0";
when x"447" => DATA <= x"0C";
when x"448" => DATA <= x"F0";
when x"449" => DATA <= x"51";
when x"44A" => DATA <= x"A2";
when x"44B" => DATA <= x"05";
when x"44C" => DATA <= x"A5";
when x"44D" => DATA <= x"25";
when x"44E" => DATA <= x"F0";
when x"44F" => DATA <= x"4B";
when x"450" => DATA <= x"A2";
when x"451" => DATA <= x"0C";
when x"452" => DATA <= x"D0";
when x"453" => DATA <= x"47";
when x"454" => DATA <= x"20";
when x"455" => DATA <= x"8B";
when x"456" => DATA <= x"C7";
when x"457" => DATA <= x"A5";
when x"458" => DATA <= x"0F";
when x"459" => DATA <= x"A2";
when x"45A" => DATA <= x"06";
when x"45B" => DATA <= x"C9";
when x"45C" => DATA <= x"01";
when x"45D" => DATA <= x"F0";
when x"45E" => DATA <= x"3C";
when x"45F" => DATA <= x"E8";
when x"460" => DATA <= x"D0";
when x"461" => DATA <= x"39";
when x"462" => DATA <= x"20";
when x"463" => DATA <= x"8B";
when x"464" => DATA <= x"C7";
when x"465" => DATA <= x"20";
when x"466" => DATA <= x"91";
when x"467" => DATA <= x"F2";
when x"468" => DATA <= x"C9";
when x"469" => DATA <= x"29";
when x"46A" => DATA <= x"F0";
when x"46B" => DATA <= x"16";
when x"46C" => DATA <= x"C9";
when x"46D" => DATA <= x"2C";
when x"46E" => DATA <= x"D0";
when x"46F" => DATA <= x"2A";
when x"470" => DATA <= x"20";
when x"471" => DATA <= x"91";
when x"472" => DATA <= x"F2";
when x"473" => DATA <= x"C9";
when x"474" => DATA <= x"58";
when x"475" => DATA <= x"D0";
when x"476" => DATA <= x"23";
when x"477" => DATA <= x"20";
when x"478" => DATA <= x"91";
when x"479" => DATA <= x"F2";
when x"47A" => DATA <= x"C9";
when x"47B" => DATA <= x"29";
when x"47C" => DATA <= x"D0";
when x"47D" => DATA <= x"1C";
when x"47E" => DATA <= x"A2";
when x"47F" => DATA <= x"0B";
when x"480" => DATA <= x"D0";
when x"481" => DATA <= x"19";
when x"482" => DATA <= x"A2";
when x"483" => DATA <= x"0D";
when x"484" => DATA <= x"A5";
when x"485" => DATA <= x"0F";
when x"486" => DATA <= x"C9";
when x"487" => DATA <= x"0B";
when x"488" => DATA <= x"F0";
when x"489" => DATA <= x"11";
when x"48A" => DATA <= x"A2";
when x"48B" => DATA <= x"0A";
when x"48C" => DATA <= x"20";
when x"48D" => DATA <= x"91";
when x"48E" => DATA <= x"F2";
when x"48F" => DATA <= x"C9";
when x"490" => DATA <= x"2C";
when x"491" => DATA <= x"D0";
when x"492" => DATA <= x"07";
when x"493" => DATA <= x"20";
when x"494" => DATA <= x"91";
when x"495" => DATA <= x"F2";
when x"496" => DATA <= x"C9";
when x"497" => DATA <= x"59";
when x"498" => DATA <= x"F0";
when x"499" => DATA <= x"01";
when x"49A" => DATA <= x"00";
when x"49B" => DATA <= x"20";
when x"49C" => DATA <= x"60";
when x"49D" => DATA <= x"F3";
when x"49E" => DATA <= x"BD";
when x"49F" => DATA <= x"D5";
when x"4A0" => DATA <= x"F1";
when x"4A1" => DATA <= x"F0";
when x"4A2" => DATA <= x"04";
when x"4A3" => DATA <= x"25";
when x"4A4" => DATA <= x"64";
when x"4A5" => DATA <= x"D0";
when x"4A6" => DATA <= x"07";
when x"4A7" => DATA <= x"BD";
when x"4A8" => DATA <= x"E4";
when x"4A9" => DATA <= x"F1";
when x"4AA" => DATA <= x"25";
when x"4AB" => DATA <= x"65";
when x"4AC" => DATA <= x"F0";
when x"4AD" => DATA <= x"EC";
when x"4AE" => DATA <= x"18";
when x"4AF" => DATA <= x"BD";
when x"4B0" => DATA <= x"F3";
when x"4B1" => DATA <= x"F1";
when x"4B2" => DATA <= x"65";
when x"4B3" => DATA <= x"66";
when x"4B4" => DATA <= x"85";
when x"4B5" => DATA <= x"66";
when x"4B6" => DATA <= x"BD";
when x"4B7" => DATA <= x"02";
when x"4B8" => DATA <= x"F2";
when x"4B9" => DATA <= x"A2";
when x"4BA" => DATA <= x"00";
when x"4BB" => DATA <= x"86";
when x"4BC" => DATA <= x"04";
when x"4BD" => DATA <= x"A4";
when x"4BE" => DATA <= x"16";
when x"4BF" => DATA <= x"84";
when x"4C0" => DATA <= x"67";
when x"4C1" => DATA <= x"A4";
when x"4C2" => DATA <= x"25";
when x"4C3" => DATA <= x"84";
when x"4C4" => DATA <= x"68";
when x"4C5" => DATA <= x"C9";
when x"4C6" => DATA <= x"0F";
when x"4C7" => DATA <= x"F0";
when x"4C8" => DATA <= x"23";
when x"4C9" => DATA <= x"29";
when x"4CA" => DATA <= x"0F";
when x"4CB" => DATA <= x"A8";
when x"4CC" => DATA <= x"C8";
when x"4CD" => DATA <= x"84";
when x"4CE" => DATA <= x"00";
when x"4CF" => DATA <= x"C0";
when x"4D0" => DATA <= x"02";
when x"4D1" => DATA <= x"D0";
when x"4D2" => DATA <= x"04";
when x"4D3" => DATA <= x"A4";
when x"4D4" => DATA <= x"68";
when x"4D5" => DATA <= x"D0";
when x"4D6" => DATA <= x"C3";
when x"4D7" => DATA <= x"A0";
when x"4D8" => DATA <= x"00";
when x"4D9" => DATA <= x"B9";
when x"4DA" => DATA <= x"66";
when x"4DB" => DATA <= x"00";
when x"4DC" => DATA <= x"91";
when x"4DD" => DATA <= x"52";
when x"4DE" => DATA <= x"C8";
when x"4DF" => DATA <= x"EE";
when x"4E0" => DATA <= x"31";
when x"4E1" => DATA <= x"03";
when x"4E2" => DATA <= x"D0";
when x"4E3" => DATA <= x"03";
when x"4E4" => DATA <= x"EE";
when x"4E5" => DATA <= x"4C";
when x"4E6" => DATA <= x"03";
when x"4E7" => DATA <= x"C4";
when x"4E8" => DATA <= x"00";
when x"4E9" => DATA <= x"D0";
when x"4EA" => DATA <= x"EE";
when x"4EB" => DATA <= x"60";
when x"4EC" => DATA <= x"A9";
when x"4ED" => DATA <= x"02";
when x"4EE" => DATA <= x"85";
when x"4EF" => DATA <= x"00";
when x"4F0" => DATA <= x"38";
when x"4F1" => DATA <= x"A5";
when x"4F2" => DATA <= x"67";
when x"4F3" => DATA <= x"ED";
when x"4F4" => DATA <= x"31";
when x"4F5" => DATA <= x"03";
when x"4F6" => DATA <= x"85";
when x"4F7" => DATA <= x"67";
when x"4F8" => DATA <= x"A5";
when x"4F9" => DATA <= x"68";
when x"4FA" => DATA <= x"ED";
when x"4FB" => DATA <= x"4C";
when x"4FC" => DATA <= x"03";
when x"4FD" => DATA <= x"85";
when x"4FE" => DATA <= x"68";
when x"4FF" => DATA <= x"38";
when x"500" => DATA <= x"A5";
when x"501" => DATA <= x"67";
when x"502" => DATA <= x"E9";
when x"503" => DATA <= x"02";
when x"504" => DATA <= x"85";
when x"505" => DATA <= x"67";
when x"506" => DATA <= x"A8";
when x"507" => DATA <= x"A5";
when x"508" => DATA <= x"68";
when x"509" => DATA <= x"E9";
when x"50A" => DATA <= x"00";
when x"50B" => DATA <= x"F0";
when x"50C" => DATA <= x"1F";
when x"50D" => DATA <= x"C9";
when x"50E" => DATA <= x"FF";
when x"50F" => DATA <= x"F0";
when x"510" => DATA <= x"16";
when x"511" => DATA <= x"20";
when x"512" => DATA <= x"D1";
when x"513" => DATA <= x"F7";
when x"514" => DATA <= x"4F";
when x"515" => DATA <= x"55";
when x"516" => DATA <= x"54";
when x"517" => DATA <= x"20";
when x"518" => DATA <= x"4F";
when x"519" => DATA <= x"46";
when x"51A" => DATA <= x"20";
when x"51B" => DATA <= x"52";
when x"51C" => DATA <= x"41";
when x"51D" => DATA <= x"4E";
when x"51E" => DATA <= x"47";
when x"51F" => DATA <= x"45";
when x"520" => DATA <= x"3A";
when x"521" => DATA <= x"0A";
when x"522" => DATA <= x"0D";
when x"523" => DATA <= x"84";
when x"524" => DATA <= x"67";
when x"525" => DATA <= x"30";
when x"526" => DATA <= x"B0";
when x"527" => DATA <= x"98";
when x"528" => DATA <= x"30";
when x"529" => DATA <= x"AD";
when x"52A" => DATA <= x"10";
when x"52B" => DATA <= x"E5";
when x"52C" => DATA <= x"98";
when x"52D" => DATA <= x"10";
when x"52E" => DATA <= x"A8";
when x"52F" => DATA <= x"30";
when x"530" => DATA <= x"E0";
when x"531" => DATA <= x"20";
when x"532" => DATA <= x"E4";
when x"533" => DATA <= x"C4";
when x"534" => DATA <= x"88";
when x"535" => DATA <= x"84";
when x"536" => DATA <= x"52";
when x"537" => DATA <= x"A5";
when x"538" => DATA <= x"12";
when x"539" => DATA <= x"85";
when x"53A" => DATA <= x"53";
when x"53B" => DATA <= x"98";
when x"53C" => DATA <= x"C8";
when x"53D" => DATA <= x"91";
when x"53E" => DATA <= x"52";
when x"53F" => DATA <= x"4C";
when x"540" => DATA <= x"9B";
when x"541" => DATA <= x"CD";
when x"542" => DATA <= x"A2";
when x"543" => DATA <= x"05";
when x"544" => DATA <= x"D0";
when x"545" => DATA <= x"02";
when x"546" => DATA <= x"A2";
when x"547" => DATA <= x"0C";
when x"548" => DATA <= x"86";
when x"549" => DATA <= x"16";
when x"54A" => DATA <= x"E6";
when x"54B" => DATA <= x"04";
when x"54C" => DATA <= x"D0";
when x"54D" => DATA <= x"06";
when x"54E" => DATA <= x"20";
when x"54F" => DATA <= x"BC";
when x"550" => DATA <= x"C8";
when x"551" => DATA <= x"20";
when x"552" => DATA <= x"31";
when x"553" => DATA <= x"C2";
when x"554" => DATA <= x"20";
when x"555" => DATA <= x"BC";
when x"556" => DATA <= x"C8";
when x"557" => DATA <= x"20";
when x"558" => DATA <= x"31";
when x"559" => DATA <= x"C2";
when x"55A" => DATA <= x"20";
when x"55B" => DATA <= x"BC";
when x"55C" => DATA <= x"C8";
when x"55D" => DATA <= x"20";
when x"55E" => DATA <= x"E4";
when x"55F" => DATA <= x"C4";
when x"560" => DATA <= x"B5";
when x"561" => DATA <= x"15";
when x"562" => DATA <= x"85";
when x"563" => DATA <= x"5C";
when x"564" => DATA <= x"B5";
when x"565" => DATA <= x"24";
when x"566" => DATA <= x"85";
when x"567" => DATA <= x"5D";
when x"568" => DATA <= x"B5";
when x"569" => DATA <= x"14";
when x"56A" => DATA <= x"85";
when x"56B" => DATA <= x"5A";
when x"56C" => DATA <= x"B5";
when x"56D" => DATA <= x"23";
when x"56E" => DATA <= x"85";
when x"56F" => DATA <= x"5B";
when x"570" => DATA <= x"A2";
when x"571" => DATA <= x"00";
when x"572" => DATA <= x"86";
when x"573" => DATA <= x"04";
when x"574" => DATA <= x"A2";
when x"575" => DATA <= x"03";
when x"576" => DATA <= x"BD";
when x"577" => DATA <= x"C1";
when x"578" => DATA <= x"03";
when x"579" => DATA <= x"95";
when x"57A" => DATA <= x"52";
when x"57B" => DATA <= x"CA";
when x"57C" => DATA <= x"10";
when x"57D" => DATA <= x"F8";
when x"57E" => DATA <= x"A5";
when x"57F" => DATA <= x"16";
when x"580" => DATA <= x"29";
when x"581" => DATA <= x"04";
when x"582" => DATA <= x"D0";
when x"583" => DATA <= x"13";
when x"584" => DATA <= x"A2";
when x"585" => DATA <= x"02";
when x"586" => DATA <= x"18";
when x"587" => DATA <= x"B5";
when x"588" => DATA <= x"5A";
when x"589" => DATA <= x"75";
when x"58A" => DATA <= x"52";
when x"58B" => DATA <= x"95";
when x"58C" => DATA <= x"5A";
when x"58D" => DATA <= x"B5";
when x"58E" => DATA <= x"5B";
when x"58F" => DATA <= x"75";
when x"590" => DATA <= x"53";
when x"591" => DATA <= x"95";
when x"592" => DATA <= x"5B";
when x"593" => DATA <= x"CA";
when x"594" => DATA <= x"CA";
when x"595" => DATA <= x"10";
when x"596" => DATA <= x"EF";
when x"597" => DATA <= x"A2";
when x"598" => DATA <= x"03";
when x"599" => DATA <= x"B5";
when x"59A" => DATA <= x"5A";
when x"59B" => DATA <= x"9D";
when x"59C" => DATA <= x"C1";
when x"59D" => DATA <= x"03";
when x"59E" => DATA <= x"CA";
when x"59F" => DATA <= x"10";
when x"5A0" => DATA <= x"F8";
when x"5A1" => DATA <= x"A5";
when x"5A2" => DATA <= x"16";
when x"5A3" => DATA <= x"29";
when x"5A4" => DATA <= x"03";
when x"5A5" => DATA <= x"F0";
when x"5A6" => DATA <= x"0B";
when x"5A7" => DATA <= x"85";
when x"5A8" => DATA <= x"5E";
when x"5A9" => DATA <= x"A5";
when x"5AA" => DATA <= x"16";
when x"5AB" => DATA <= x"29";
when x"5AC" => DATA <= x"08";
when x"5AD" => DATA <= x"F0";
when x"5AE" => DATA <= x"06";
when x"5AF" => DATA <= x"20";
when x"5B0" => DATA <= x"78";
when x"5B1" => DATA <= x"F6";
when x"5B2" => DATA <= x"4C";
when x"5B3" => DATA <= x"5B";
when x"5B4" => DATA <= x"C5";
when x"5B5" => DATA <= x"A2";
when x"5B6" => DATA <= x"02";
when x"5B7" => DATA <= x"38";
when x"5B8" => DATA <= x"B5";
when x"5B9" => DATA <= x"5A";
when x"5BA" => DATA <= x"F5";
when x"5BB" => DATA <= x"52";
when x"5BC" => DATA <= x"B4";
when x"5BD" => DATA <= x"52";
when x"5BE" => DATA <= x"94";
when x"5BF" => DATA <= x"5A";
when x"5C0" => DATA <= x"95";
when x"5C1" => DATA <= x"52";
when x"5C2" => DATA <= x"B4";
when x"5C3" => DATA <= x"53";
when x"5C4" => DATA <= x"B5";
when x"5C5" => DATA <= x"5B";
when x"5C6" => DATA <= x"F5";
when x"5C7" => DATA <= x"53";
when x"5C8" => DATA <= x"94";
when x"5C9" => DATA <= x"5B";
when x"5CA" => DATA <= x"95";
when x"5CB" => DATA <= x"53";
when x"5CC" => DATA <= x"95";
when x"5CD" => DATA <= x"56";
when x"5CE" => DATA <= x"10";
when x"5CF" => DATA <= x"0D";
when x"5D0" => DATA <= x"A9";
when x"5D1" => DATA <= x"00";
when x"5D2" => DATA <= x"38";
when x"5D3" => DATA <= x"F5";
when x"5D4" => DATA <= x"52";
when x"5D5" => DATA <= x"95";
when x"5D6" => DATA <= x"52";
when x"5D7" => DATA <= x"A9";
when x"5D8" => DATA <= x"00";
when x"5D9" => DATA <= x"F5";
when x"5DA" => DATA <= x"53";
when x"5DB" => DATA <= x"95";
when x"5DC" => DATA <= x"53";
when x"5DD" => DATA <= x"CA";
when x"5DE" => DATA <= x"CA";
when x"5DF" => DATA <= x"10";
when x"5E0" => DATA <= x"D6";
when x"5E1" => DATA <= x"A5";
when x"5E2" => DATA <= x"54";
when x"5E3" => DATA <= x"C5";
when x"5E4" => DATA <= x"52";
when x"5E5" => DATA <= x"A5";
when x"5E6" => DATA <= x"55";
when x"5E7" => DATA <= x"E5";
when x"5E8" => DATA <= x"53";
when x"5E9" => DATA <= x"90";
when x"5EA" => DATA <= x"31";
when x"5EB" => DATA <= x"A9";
when x"5EC" => DATA <= x"00";
when x"5ED" => DATA <= x"E5";
when x"5EE" => DATA <= x"54";
when x"5EF" => DATA <= x"85";
when x"5F0" => DATA <= x"57";
when x"5F1" => DATA <= x"A9";
when x"5F2" => DATA <= x"00";
when x"5F3" => DATA <= x"E5";
when x"5F4" => DATA <= x"55";
when x"5F5" => DATA <= x"38";
when x"5F6" => DATA <= x"6A";
when x"5F7" => DATA <= x"85";
when x"5F8" => DATA <= x"59";
when x"5F9" => DATA <= x"66";
when x"5FA" => DATA <= x"57";
when x"5FB" => DATA <= x"20";
when x"5FC" => DATA <= x"78";
when x"5FD" => DATA <= x"F6";
when x"5FE" => DATA <= x"A5";
when x"5FF" => DATA <= x"5C";
when x"600" => DATA <= x"CD";
when x"601" => DATA <= x"C3";
when x"602" => DATA <= x"03";
when x"603" => DATA <= x"D0";
when x"604" => DATA <= x"0A";
when x"605" => DATA <= x"A5";
when x"606" => DATA <= x"5D";
when x"607" => DATA <= x"CD";
when x"608" => DATA <= x"C4";
when x"609" => DATA <= x"03";
when x"60A" => DATA <= x"D0";
when x"60B" => DATA <= x"03";
when x"60C" => DATA <= x"4C";
when x"60D" => DATA <= x"5B";
when x"60E" => DATA <= x"C5";
when x"60F" => DATA <= x"20";
when x"610" => DATA <= x"55";
when x"611" => DATA <= x"F6";
when x"612" => DATA <= x"A5";
when x"613" => DATA <= x"59";
when x"614" => DATA <= x"30";
when x"615" => DATA <= x"E5";
when x"616" => DATA <= x"20";
when x"617" => DATA <= x"44";
when x"618" => DATA <= x"F6";
when x"619" => DATA <= x"4C";
when x"61A" => DATA <= x"FB";
when x"61B" => DATA <= x"F5";
when x"61C" => DATA <= x"A5";
when x"61D" => DATA <= x"53";
when x"61E" => DATA <= x"4A";
when x"61F" => DATA <= x"85";
when x"620" => DATA <= x"59";
when x"621" => DATA <= x"A5";
when x"622" => DATA <= x"52";
when x"623" => DATA <= x"6A";
when x"624" => DATA <= x"85";
when x"625" => DATA <= x"57";
when x"626" => DATA <= x"20";
when x"627" => DATA <= x"78";
when x"628" => DATA <= x"F6";
when x"629" => DATA <= x"A5";
when x"62A" => DATA <= x"5A";
when x"62B" => DATA <= x"CD";
when x"62C" => DATA <= x"C1";
when x"62D" => DATA <= x"03";
when x"62E" => DATA <= x"D0";
when x"62F" => DATA <= x"07";
when x"630" => DATA <= x"A5";
when x"631" => DATA <= x"5B";
when x"632" => DATA <= x"CD";
when x"633" => DATA <= x"C2";
when x"634" => DATA <= x"03";
when x"635" => DATA <= x"F0";
when x"636" => DATA <= x"D5";
when x"637" => DATA <= x"20";
when x"638" => DATA <= x"44";
when x"639" => DATA <= x"F6";
when x"63A" => DATA <= x"A5";
when x"63B" => DATA <= x"59";
when x"63C" => DATA <= x"10";
when x"63D" => DATA <= x"E8";
when x"63E" => DATA <= x"20";
when x"63F" => DATA <= x"55";
when x"640" => DATA <= x"F6";
when x"641" => DATA <= x"4C";
when x"642" => DATA <= x"26";
when x"643" => DATA <= x"F6";
when x"644" => DATA <= x"38";
when x"645" => DATA <= x"A5";
when x"646" => DATA <= x"57";
when x"647" => DATA <= x"E5";
when x"648" => DATA <= x"54";
when x"649" => DATA <= x"85";
when x"64A" => DATA <= x"57";
when x"64B" => DATA <= x"A5";
when x"64C" => DATA <= x"59";
when x"64D" => DATA <= x"E5";
when x"64E" => DATA <= x"55";
when x"64F" => DATA <= x"85";
when x"650" => DATA <= x"59";
when x"651" => DATA <= x"A2";
when x"652" => DATA <= x"00";
when x"653" => DATA <= x"F0";
when x"654" => DATA <= x"0F";
when x"655" => DATA <= x"18";
when x"656" => DATA <= x"A5";
when x"657" => DATA <= x"57";
when x"658" => DATA <= x"65";
when x"659" => DATA <= x"52";
when x"65A" => DATA <= x"85";
when x"65B" => DATA <= x"57";
when x"65C" => DATA <= x"A5";
when x"65D" => DATA <= x"59";
when x"65E" => DATA <= x"65";
when x"65F" => DATA <= x"53";
when x"660" => DATA <= x"85";
when x"661" => DATA <= x"59";
when x"662" => DATA <= x"A2";
when x"663" => DATA <= x"02";
when x"664" => DATA <= x"B5";
when x"665" => DATA <= x"56";
when x"666" => DATA <= x"10";
when x"667" => DATA <= x"09";
when x"668" => DATA <= x"B5";
when x"669" => DATA <= x"5A";
when x"66A" => DATA <= x"D0";
when x"66B" => DATA <= x"02";
when x"66C" => DATA <= x"D6";
when x"66D" => DATA <= x"5B";
when x"66E" => DATA <= x"D6";
when x"66F" => DATA <= x"5A";
when x"670" => DATA <= x"60";
when x"671" => DATA <= x"F6";
when x"672" => DATA <= x"5A";
when x"673" => DATA <= x"D0";
when x"674" => DATA <= x"FB";
when x"675" => DATA <= x"F6";
when x"676" => DATA <= x"5B";
when x"677" => DATA <= x"60";
when x"678" => DATA <= x"6C";
when x"679" => DATA <= x"FE";
when x"67A" => DATA <= x"03";
when x"67B" => DATA <= x"20";
when x"67C" => DATA <= x"C8";
when x"67D" => DATA <= x"C3";
when x"67E" => DATA <= x"A0";
when x"67F" => DATA <= x"00";
when x"680" => DATA <= x"A5";
when x"681" => DATA <= x"52";
when x"682" => DATA <= x"F0";
when x"683" => DATA <= x"3E";
when x"684" => DATA <= x"C9";
when x"685" => DATA <= x"05";
when x"686" => DATA <= x"90";
when x"687" => DATA <= x"02";
when x"688" => DATA <= x"A9";
when x"689" => DATA <= x"04";
when x"68A" => DATA <= x"A2";
when x"68B" => DATA <= x"80";
when x"68C" => DATA <= x"86";
when x"68D" => DATA <= x"54";
when x"68E" => DATA <= x"84";
when x"68F" => DATA <= x"53";
when x"690" => DATA <= x"85";
when x"691" => DATA <= x"52";
when x"692" => DATA <= x"AA";
when x"693" => DATA <= x"BD";
when x"694" => DATA <= x"CE";
when x"695" => DATA <= x"F6";
when x"696" => DATA <= x"A6";
when x"697" => DATA <= x"12";
when x"698" => DATA <= x"10";
when x"699" => DATA <= x"04";
when x"69A" => DATA <= x"C5";
when x"69B" => DATA <= x"12";
when x"69C" => DATA <= x"B0";
when x"69D" => DATA <= x"E1";
when x"69E" => DATA <= x"AA";
when x"69F" => DATA <= x"98";
when x"6A0" => DATA <= x"91";
when x"6A1" => DATA <= x"53";
when x"6A2" => DATA <= x"88";
when x"6A3" => DATA <= x"D0";
when x"6A4" => DATA <= x"FB";
when x"6A5" => DATA <= x"E6";
when x"6A6" => DATA <= x"54";
when x"6A7" => DATA <= x"E4";
when x"6A8" => DATA <= x"54";
when x"6A9" => DATA <= x"D0";
when x"6AA" => DATA <= x"F5";
when x"6AB" => DATA <= x"A4";
when x"6AC" => DATA <= x"52";
when x"6AD" => DATA <= x"B9";
when x"6AE" => DATA <= x"D8";
when x"6AF" => DATA <= x"F6";
when x"6B0" => DATA <= x"8D";
when x"6B1" => DATA <= x"FF";
when x"6B2" => DATA <= x"03";
when x"6B3" => DATA <= x"B9";
when x"6B4" => DATA <= x"D3";
when x"6B5" => DATA <= x"F6";
when x"6B6" => DATA <= x"8D";
when x"6B7" => DATA <= x"FE";
when x"6B8" => DATA <= x"03";
when x"6B9" => DATA <= x"B9";
when x"6BA" => DATA <= x"DD";
when x"6BB" => DATA <= x"F6";
when x"6BC" => DATA <= x"8D";
when x"6BD" => DATA <= x"00";
when x"6BE" => DATA <= x"B0";
when x"6BF" => DATA <= x"4C";
when x"6C0" => DATA <= x"58";
when x"6C1" => DATA <= x"C5";
when x"6C2" => DATA <= x"A9";
when x"6C3" => DATA <= x"40";
when x"6C4" => DATA <= x"99";
when x"6C5" => DATA <= x"00";
when x"6C6" => DATA <= x"80";
when x"6C7" => DATA <= x"99";
when x"6C8" => DATA <= x"00";
when x"6C9" => DATA <= x"81";
when x"6CA" => DATA <= x"88";
when x"6CB" => DATA <= x"D0";
when x"6CC" => DATA <= x"F7";
when x"6CD" => DATA <= x"F0";
when x"6CE" => DATA <= x"DC";
when x"6CF" => DATA <= x"84";
when x"6D0" => DATA <= x"86";
when x"6D1" => DATA <= x"8C";
when x"6D2" => DATA <= x"98";
when x"6D3" => DATA <= x"E2";
when x"6D4" => DATA <= x"3B";
when x"6D5" => DATA <= x"54";
when x"6D6" => DATA <= x"6D";
when x"6D7" => DATA <= x"AA";
when x"6D8" => DATA <= x"F6";
when x"6D9" => DATA <= x"F7";
when x"6DA" => DATA <= x"F7";
when x"6DB" => DATA <= x"F7";
when x"6DC" => DATA <= x"F7";
when x"6DD" => DATA <= x"00";
when x"6DE" => DATA <= x"30";
when x"6DF" => DATA <= x"70";
when x"6E0" => DATA <= x"B0";
when x"6E1" => DATA <= x"F0";
when x"6E2" => DATA <= x"A5";
when x"6E3" => DATA <= x"5B";
when x"6E4" => DATA <= x"05";
when x"6E5" => DATA <= x"5D";
when x"6E6" => DATA <= x"D0";
when x"6E7" => DATA <= x"52";
when x"6E8" => DATA <= x"A5";
when x"6E9" => DATA <= x"5A";
when x"6EA" => DATA <= x"C9";
when x"6EB" => DATA <= x"40";
when x"6EC" => DATA <= x"B0";
when x"6ED" => DATA <= x"4C";
when x"6EE" => DATA <= x"4A";
when x"6EF" => DATA <= x"85";
when x"6F0" => DATA <= x"5F";
when x"6F1" => DATA <= x"A9";
when x"6F2" => DATA <= x"2F";
when x"6F3" => DATA <= x"38";
when x"6F4" => DATA <= x"E5";
when x"6F5" => DATA <= x"5C";
when x"6F6" => DATA <= x"C9";
when x"6F7" => DATA <= x"30";
when x"6F8" => DATA <= x"B0";
when x"6F9" => DATA <= x"40";
when x"6FA" => DATA <= x"A2";
when x"6FB" => DATA <= x"FF";
when x"6FC" => DATA <= x"38";
when x"6FD" => DATA <= x"E8";
when x"6FE" => DATA <= x"E9";
when x"6FF" => DATA <= x"03";
when x"700" => DATA <= x"B0";
when x"701" => DATA <= x"FB";
when x"702" => DATA <= x"69";
when x"703" => DATA <= x"03";
when x"704" => DATA <= x"85";
when x"705" => DATA <= x"61";
when x"706" => DATA <= x"8A";
when x"707" => DATA <= x"0A";
when x"708" => DATA <= x"0A";
when x"709" => DATA <= x"0A";
when x"70A" => DATA <= x"0A";
when x"70B" => DATA <= x"0A";
when x"70C" => DATA <= x"05";
when x"70D" => DATA <= x"5F";
when x"70E" => DATA <= x"85";
when x"70F" => DATA <= x"5F";
when x"710" => DATA <= x"A9";
when x"711" => DATA <= x"80";
when x"712" => DATA <= x"69";
when x"713" => DATA <= x"00";
when x"714" => DATA <= x"85";
when x"715" => DATA <= x"60";
when x"716" => DATA <= x"A5";
when x"717" => DATA <= x"5A";
when x"718" => DATA <= x"4A";
when x"719" => DATA <= x"A5";
when x"71A" => DATA <= x"61";
when x"71B" => DATA <= x"2A";
when x"71C" => DATA <= x"A8";
when x"71D" => DATA <= x"B9";
when x"71E" => DATA <= x"CB";
when x"71F" => DATA <= x"F7";
when x"720" => DATA <= x"A0";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"A6";
when x"723" => DATA <= x"5E";
when x"724" => DATA <= x"CA";
when x"725" => DATA <= x"F0";
when x"726" => DATA <= x"0F";
when x"727" => DATA <= x"CA";
when x"728" => DATA <= x"F0";
when x"729" => DATA <= x"07";
when x"72A" => DATA <= x"49";
when x"72B" => DATA <= x"FF";
when x"72C" => DATA <= x"31";
when x"72D" => DATA <= x"5F";
when x"72E" => DATA <= x"91";
when x"72F" => DATA <= x"5F";
when x"730" => DATA <= x"60";
when x"731" => DATA <= x"51";
when x"732" => DATA <= x"5F";
when x"733" => DATA <= x"91";
when x"734" => DATA <= x"5F";
when x"735" => DATA <= x"60";
when x"736" => DATA <= x"11";
when x"737" => DATA <= x"5F";
when x"738" => DATA <= x"91";
when x"739" => DATA <= x"5F";
when x"73A" => DATA <= x"60";
when x"73B" => DATA <= x"A5";
when x"73C" => DATA <= x"5B";
when x"73D" => DATA <= x"05";
when x"73E" => DATA <= x"5D";
when x"73F" => DATA <= x"D0";
when x"740" => DATA <= x"F9";
when x"741" => DATA <= x"A5";
when x"742" => DATA <= x"5A";
when x"743" => DATA <= x"30";
when x"744" => DATA <= x"F5";
when x"745" => DATA <= x"4A";
when x"746" => DATA <= x"4A";
when x"747" => DATA <= x"4A";
when x"748" => DATA <= x"85";
when x"749" => DATA <= x"5F";
when x"74A" => DATA <= x"A9";
when x"74B" => DATA <= x"3F";
when x"74C" => DATA <= x"38";
when x"74D" => DATA <= x"E5";
when x"74E" => DATA <= x"5C";
when x"74F" => DATA <= x"C9";
when x"750" => DATA <= x"40";
when x"751" => DATA <= x"90";
when x"752" => DATA <= x"32";
when x"753" => DATA <= x"60";
when x"754" => DATA <= x"A5";
when x"755" => DATA <= x"5B";
when x"756" => DATA <= x"05";
when x"757" => DATA <= x"5D";
when x"758" => DATA <= x"D0";
when x"759" => DATA <= x"E0";
when x"75A" => DATA <= x"A5";
when x"75B" => DATA <= x"5A";
when x"75C" => DATA <= x"30";
when x"75D" => DATA <= x"DC";
when x"75E" => DATA <= x"4A";
when x"75F" => DATA <= x"4A";
when x"760" => DATA <= x"4A";
when x"761" => DATA <= x"85";
when x"762" => DATA <= x"5F";
when x"763" => DATA <= x"A9";
when x"764" => DATA <= x"5F";
when x"765" => DATA <= x"38";
when x"766" => DATA <= x"E5";
when x"767" => DATA <= x"5C";
when x"768" => DATA <= x"C9";
when x"769" => DATA <= x"60";
when x"76A" => DATA <= x"90";
when x"76B" => DATA <= x"19";
when x"76C" => DATA <= x"60";
when x"76D" => DATA <= x"A5";
when x"76E" => DATA <= x"5B";
when x"76F" => DATA <= x"05";
when x"770" => DATA <= x"5D";
when x"771" => DATA <= x"D0";
when x"772" => DATA <= x"C7";
when x"773" => DATA <= x"A5";
when x"774" => DATA <= x"5A";
when x"775" => DATA <= x"30";
when x"776" => DATA <= x"C3";
when x"777" => DATA <= x"4A";
when x"778" => DATA <= x"4A";
when x"779" => DATA <= x"4A";
when x"77A" => DATA <= x"85";
when x"77B" => DATA <= x"5F";
when x"77C" => DATA <= x"A9";
when x"77D" => DATA <= x"BF";
when x"77E" => DATA <= x"38";
when x"77F" => DATA <= x"E5";
when x"780" => DATA <= x"5C";
when x"781" => DATA <= x"C9";
when x"782" => DATA <= x"C0";
when x"783" => DATA <= x"B0";
when x"784" => DATA <= x"B5";
when x"785" => DATA <= x"A0";
when x"786" => DATA <= x"00";
when x"787" => DATA <= x"84";
when x"788" => DATA <= x"60";
when x"789" => DATA <= x"0A";
when x"78A" => DATA <= x"26";
when x"78B" => DATA <= x"60";
when x"78C" => DATA <= x"0A";
when x"78D" => DATA <= x"26";
when x"78E" => DATA <= x"60";
when x"78F" => DATA <= x"0A";
when x"790" => DATA <= x"26";
when x"791" => DATA <= x"60";
when x"792" => DATA <= x"0A";
when x"793" => DATA <= x"26";
when x"794" => DATA <= x"60";
when x"795" => DATA <= x"65";
when x"796" => DATA <= x"5F";
when x"797" => DATA <= x"85";
when x"798" => DATA <= x"5F";
when x"799" => DATA <= x"A5";
when x"79A" => DATA <= x"60";
when x"79B" => DATA <= x"69";
when x"79C" => DATA <= x"80";
when x"79D" => DATA <= x"85";
when x"79E" => DATA <= x"60";
when x"79F" => DATA <= x"A5";
when x"7A0" => DATA <= x"5A";
when x"7A1" => DATA <= x"29";
when x"7A2" => DATA <= x"07";
when x"7A3" => DATA <= x"A8";
when x"7A4" => DATA <= x"B9";
when x"7A5" => DATA <= x"C9";
when x"7A6" => DATA <= x"F7";
when x"7A7" => DATA <= x"4C";
when x"7A8" => DATA <= x"20";
when x"7A9" => DATA <= x"F7";
when x"7AA" => DATA <= x"A5";
when x"7AB" => DATA <= x"5B";
when x"7AC" => DATA <= x"05";
when x"7AD" => DATA <= x"5D";
when x"7AE" => DATA <= x"D0";
when x"7AF" => DATA <= x"BC";
when x"7B0" => DATA <= x"A5";
when x"7B1" => DATA <= x"5A";
when x"7B2" => DATA <= x"4A";
when x"7B3" => DATA <= x"4A";
when x"7B4" => DATA <= x"4A";
when x"7B5" => DATA <= x"85";
when x"7B6" => DATA <= x"5F";
when x"7B7" => DATA <= x"A9";
when x"7B8" => DATA <= x"BF";
when x"7B9" => DATA <= x"38";
when x"7BA" => DATA <= x"E5";
when x"7BB" => DATA <= x"5C";
when x"7BC" => DATA <= x"C9";
when x"7BD" => DATA <= x"C0";
when x"7BE" => DATA <= x"B0";
when x"7BF" => DATA <= x"AC";
when x"7C0" => DATA <= x"A0";
when x"7C1" => DATA <= x"00";
when x"7C2" => DATA <= x"84";
when x"7C3" => DATA <= x"60";
when x"7C4" => DATA <= x"0A";
when x"7C5" => DATA <= x"26";
when x"7C6" => DATA <= x"60";
when x"7C7" => DATA <= x"10";
when x"7C8" => DATA <= x"C0";
when x"7C9" => DATA <= x"80";
when x"7CA" => DATA <= x"40";
when x"7CB" => DATA <= x"20";
when x"7CC" => DATA <= x"10";
when x"7CD" => DATA <= x"08";
when x"7CE" => DATA <= x"04";
when x"7CF" => DATA <= x"02";
when x"7D0" => DATA <= x"01";
when x"7D1" => DATA <= x"68";
when x"7D2" => DATA <= x"85";
when x"7D3" => DATA <= x"E8";
when x"7D4" => DATA <= x"68";
when x"7D5" => DATA <= x"85";
when x"7D6" => DATA <= x"E9";
when x"7D7" => DATA <= x"A0";
when x"7D8" => DATA <= x"00";
when x"7D9" => DATA <= x"E6";
when x"7DA" => DATA <= x"E8";
when x"7DB" => DATA <= x"D0";
when x"7DC" => DATA <= x"02";
when x"7DD" => DATA <= x"E6";
when x"7DE" => DATA <= x"E9";
when x"7DF" => DATA <= x"B1";
when x"7E0" => DATA <= x"E8";
when x"7E1" => DATA <= x"30";
when x"7E2" => DATA <= x"06";
when x"7E3" => DATA <= x"20";
when x"7E4" => DATA <= x"F4";
when x"7E5" => DATA <= x"FF";
when x"7E6" => DATA <= x"4C";
when x"7E7" => DATA <= x"D7";
when x"7E8" => DATA <= x"F7";
when x"7E9" => DATA <= x"6C";
when x"7EA" => DATA <= x"E8";
when x"7EB" => DATA <= x"00";
when x"7EC" => DATA <= x"A2";
when x"7ED" => DATA <= x"D4";
when x"7EE" => DATA <= x"20";
when x"7EF" => DATA <= x"F1";
when x"7F0" => DATA <= x"F7";
when x"7F1" => DATA <= x"B5";
when x"7F2" => DATA <= x"01";
when x"7F3" => DATA <= x"20";
when x"7F4" => DATA <= x"02";
when x"7F5" => DATA <= x"F8";
when x"7F6" => DATA <= x"E8";
when x"7F7" => DATA <= x"E8";
when x"7F8" => DATA <= x"B5";
when x"7F9" => DATA <= x"FE";
when x"7FA" => DATA <= x"20";
when x"7FB" => DATA <= x"02";
when x"7FC" => DATA <= x"F8";
when x"7FD" => DATA <= x"A9";
when x"7FE" => DATA <= x"20";
when x"7FF" => DATA <= x"4C";
when x"800" => DATA <= x"F4";
when x"801" => DATA <= x"FF";
when x"802" => DATA <= x"48";
when x"803" => DATA <= x"4A";
when x"804" => DATA <= x"4A";
when x"805" => DATA <= x"4A";
when x"806" => DATA <= x"4A";
when x"807" => DATA <= x"20";
when x"808" => DATA <= x"0B";
when x"809" => DATA <= x"F8";
when x"80A" => DATA <= x"68";
when x"80B" => DATA <= x"29";
when x"80C" => DATA <= x"0F";
when x"80D" => DATA <= x"C9";
when x"80E" => DATA <= x"0A";
when x"80F" => DATA <= x"90";
when x"810" => DATA <= x"02";
when x"811" => DATA <= x"69";
when x"812" => DATA <= x"06";
when x"813" => DATA <= x"69";
when x"814" => DATA <= x"30";
when x"815" => DATA <= x"4C";
when x"816" => DATA <= x"F4";
when x"817" => DATA <= x"FF";
when x"818" => DATA <= x"20";
when x"819" => DATA <= x"76";
when x"81A" => DATA <= x"F8";
when x"81B" => DATA <= x"A2";
when x"81C" => DATA <= x"00";
when x"81D" => DATA <= x"C9";
when x"81E" => DATA <= x"22";
when x"81F" => DATA <= x"F0";
when x"820" => DATA <= x"06";
when x"821" => DATA <= x"E8";
when x"822" => DATA <= x"D0";
when x"823" => DATA <= x"1B";
when x"824" => DATA <= x"4C";
when x"825" => DATA <= x"7D";
when x"826" => DATA <= x"FA";
when x"827" => DATA <= x"C8";
when x"828" => DATA <= x"B9";
when x"829" => DATA <= x"00";
when x"82A" => DATA <= x"01";
when x"82B" => DATA <= x"C9";
when x"82C" => DATA <= x"0D";
when x"82D" => DATA <= x"F0";
when x"82E" => DATA <= x"F5";
when x"82F" => DATA <= x"9D";
when x"830" => DATA <= x"40";
when x"831" => DATA <= x"01";
when x"832" => DATA <= x"E8";
when x"833" => DATA <= x"C9";
when x"834" => DATA <= x"22";
when x"835" => DATA <= x"D0";
when x"836" => DATA <= x"F0";
when x"837" => DATA <= x"C8";
when x"838" => DATA <= x"B9";
when x"839" => DATA <= x"00";
when x"83A" => DATA <= x"01";
when x"83B" => DATA <= x"C9";
when x"83C" => DATA <= x"22";
when x"83D" => DATA <= x"F0";
when x"83E" => DATA <= x"E8";
when x"83F" => DATA <= x"A9";
when x"840" => DATA <= x"0D";
when x"841" => DATA <= x"9D";
when x"842" => DATA <= x"3F";
when x"843" => DATA <= x"01";
when x"844" => DATA <= x"A9";
when x"845" => DATA <= x"40";
when x"846" => DATA <= x"85";
when x"847" => DATA <= x"C9";
when x"848" => DATA <= x"A9";
when x"849" => DATA <= x"01";
when x"84A" => DATA <= x"85";
when x"84B" => DATA <= x"CA";
when x"84C" => DATA <= x"A2";
when x"84D" => DATA <= x"C9";
when x"84E" => DATA <= x"60";
when x"84F" => DATA <= x"A0";
when x"850" => DATA <= x"00";
when x"851" => DATA <= x"B5";
when x"852" => DATA <= x"00";
when x"853" => DATA <= x"99";
when x"854" => DATA <= x"C9";
when x"855" => DATA <= x"00";
when x"856" => DATA <= x"E8";
when x"857" => DATA <= x"C8";
when x"858" => DATA <= x"C0";
when x"859" => DATA <= x"0A";
when x"85A" => DATA <= x"90";
when x"85B" => DATA <= x"F5";
when x"85C" => DATA <= x"A0";
when x"85D" => DATA <= x"FF";
when x"85E" => DATA <= x"A9";
when x"85F" => DATA <= x"0D";
when x"860" => DATA <= x"C8";
when x"861" => DATA <= x"C0";
when x"862" => DATA <= x"0E";
when x"863" => DATA <= x"B0";
when x"864" => DATA <= x"07";
when x"865" => DATA <= x"D1";
when x"866" => DATA <= x"C9";
when x"867" => DATA <= x"D0";
when x"868" => DATA <= x"F7";
when x"869" => DATA <= x"C0";
when x"86A" => DATA <= x"00";
when x"86B" => DATA <= x"60";
when x"86C" => DATA <= x"20";
when x"86D" => DATA <= x"D1";
when x"86E" => DATA <= x"F7";
when x"86F" => DATA <= x"4E";
when x"870" => DATA <= x"41";
when x"871" => DATA <= x"4D";
when x"872" => DATA <= x"45";
when x"873" => DATA <= x"EA";
when x"874" => DATA <= x"00";
when x"875" => DATA <= x"C8";
when x"876" => DATA <= x"B9";
when x"877" => DATA <= x"00";
when x"878" => DATA <= x"01";
when x"879" => DATA <= x"C9";
when x"87A" => DATA <= x"20";
when x"87B" => DATA <= x"F0";
when x"87C" => DATA <= x"F8";
when x"87D" => DATA <= x"60";
when x"87E" => DATA <= x"C9";
when x"87F" => DATA <= x"30";
when x"880" => DATA <= x"90";
when x"881" => DATA <= x"0F";
when x"882" => DATA <= x"C9";
when x"883" => DATA <= x"3A";
when x"884" => DATA <= x"90";
when x"885" => DATA <= x"08";
when x"886" => DATA <= x"E9";
when x"887" => DATA <= x"07";
when x"888" => DATA <= x"90";
when x"889" => DATA <= x"07";
when x"88A" => DATA <= x"C9";
when x"88B" => DATA <= x"40";
when x"88C" => DATA <= x"B0";
when x"88D" => DATA <= x"02";
when x"88E" => DATA <= x"29";
when x"88F" => DATA <= x"0F";
when x"890" => DATA <= x"60";
when x"891" => DATA <= x"38";
when x"892" => DATA <= x"60";
when x"893" => DATA <= x"A9";
when x"894" => DATA <= x"00";
when x"895" => DATA <= x"95";
when x"896" => DATA <= x"00";
when x"897" => DATA <= x"95";
when x"898" => DATA <= x"01";
when x"899" => DATA <= x"95";
when x"89A" => DATA <= x"02";
when x"89B" => DATA <= x"20";
when x"89C" => DATA <= x"76";
when x"89D" => DATA <= x"F8";
when x"89E" => DATA <= x"B9";
when x"89F" => DATA <= x"00";
when x"8A0" => DATA <= x"01";
when x"8A1" => DATA <= x"20";
when x"8A2" => DATA <= x"7E";
when x"8A3" => DATA <= x"F8";
when x"8A4" => DATA <= x"B0";
when x"8A5" => DATA <= x"15";
when x"8A6" => DATA <= x"0A";
when x"8A7" => DATA <= x"0A";
when x"8A8" => DATA <= x"0A";
when x"8A9" => DATA <= x"0A";
when x"8AA" => DATA <= x"94";
when x"8AB" => DATA <= x"02";
when x"8AC" => DATA <= x"A0";
when x"8AD" => DATA <= x"04";
when x"8AE" => DATA <= x"0A";
when x"8AF" => DATA <= x"36";
when x"8B0" => DATA <= x"00";
when x"8B1" => DATA <= x"36";
when x"8B2" => DATA <= x"01";
when x"8B3" => DATA <= x"88";
when x"8B4" => DATA <= x"D0";
when x"8B5" => DATA <= x"F8";
when x"8B6" => DATA <= x"B4";
when x"8B7" => DATA <= x"02";
when x"8B8" => DATA <= x"C8";
when x"8B9" => DATA <= x"D0";
when x"8BA" => DATA <= x"E3";
when x"8BB" => DATA <= x"B5";
when x"8BC" => DATA <= x"02";
when x"8BD" => DATA <= x"60";
when x"8BE" => DATA <= x"43";
when x"8BF" => DATA <= x"41";
when x"8C0" => DATA <= x"54";
when x"8C1" => DATA <= x"FA";
when x"8C2" => DATA <= x"2A";
when x"8C3" => DATA <= x"4C";
when x"8C4" => DATA <= x"4F";
when x"8C5" => DATA <= x"41";
when x"8C6" => DATA <= x"44";
when x"8C7" => DATA <= x"F9";
when x"8C8" => DATA <= x"58";
when x"8C9" => DATA <= x"53";
when x"8CA" => DATA <= x"41";
when x"8CB" => DATA <= x"56";
when x"8CC" => DATA <= x"45";
when x"8CD" => DATA <= x"FA";
when x"8CE" => DATA <= x"BB";
when x"8CF" => DATA <= x"52";
when x"8D0" => DATA <= x"55";
when x"8D1" => DATA <= x"4E";
when x"8D2" => DATA <= x"FA";
when x"8D3" => DATA <= x"20";
when x"8D4" => DATA <= x"4D";
when x"8D5" => DATA <= x"4F";
when x"8D6" => DATA <= x"4E";
when x"8D7" => DATA <= x"FA";
when x"8D8" => DATA <= x"1A";
when x"8D9" => DATA <= x"4E";
when x"8DA" => DATA <= x"4F";
when x"8DB" => DATA <= x"4D";
when x"8DC" => DATA <= x"4F";
when x"8DD" => DATA <= x"4E";
when x"8DE" => DATA <= x"FA";
when x"8DF" => DATA <= x"19";
when x"8E0" => DATA <= x"46";
when x"8E1" => DATA <= x"4C";
when x"8E2" => DATA <= x"4F";
when x"8E3" => DATA <= x"41";
when x"8E4" => DATA <= x"44";
when x"8E5" => DATA <= x"F9";
when x"8E6" => DATA <= x"55";
when x"8E7" => DATA <= x"44";
when x"8E8" => DATA <= x"4F";
when x"8E9" => DATA <= x"53";
when x"8EA" => DATA <= x"CC";
when x"8EB" => DATA <= x"EF";
when x"8EC" => DATA <= x"00";
when x"8ED" => DATA <= x"F9";
when x"8EE" => DATA <= x"26";
when x"8EF" => DATA <= x"A2";
when x"8F0" => DATA <= x"FF";
when x"8F1" => DATA <= x"D8";
when x"8F2" => DATA <= x"A0";
when x"8F3" => DATA <= x"00";
when x"8F4" => DATA <= x"84";
when x"8F5" => DATA <= x"DD";
when x"8F6" => DATA <= x"20";
when x"8F7" => DATA <= x"76";
when x"8F8" => DATA <= x"F8";
when x"8F9" => DATA <= x"88";
when x"8FA" => DATA <= x"C8";
when x"8FB" => DATA <= x"E8";
when x"8FC" => DATA <= x"BD";
when x"8FD" => DATA <= x"BE";
when x"8FE" => DATA <= x"F8";
when x"8FF" => DATA <= x"30";
when x"900" => DATA <= x"18";
when x"901" => DATA <= x"D9";
when x"902" => DATA <= x"00";
when x"903" => DATA <= x"01";
when x"904" => DATA <= x"F0";
when x"905" => DATA <= x"F4";
when x"906" => DATA <= x"CA";
when x"907" => DATA <= x"E8";
when x"908" => DATA <= x"BD";
when x"909" => DATA <= x"BE";
when x"90A" => DATA <= x"F8";
when x"90B" => DATA <= x"10";
when x"90C" => DATA <= x"FA";
when x"90D" => DATA <= x"E8";
when x"90E" => DATA <= x"B9";
when x"90F" => DATA <= x"00";
when x"910" => DATA <= x"01";
when x"911" => DATA <= x"C9";
when x"912" => DATA <= x"2E";
when x"913" => DATA <= x"D0";
when x"914" => DATA <= x"DD";
when x"915" => DATA <= x"C8";
when x"916" => DATA <= x"CA";
when x"917" => DATA <= x"B0";
when x"918" => DATA <= x"E3";
when x"919" => DATA <= x"85";
when x"91A" => DATA <= x"CA";
when x"91B" => DATA <= x"BD";
when x"91C" => DATA <= x"BF";
when x"91D" => DATA <= x"F8";
when x"91E" => DATA <= x"85";
when x"91F" => DATA <= x"C9";
when x"920" => DATA <= x"18";
when x"921" => DATA <= x"A2";
when x"922" => DATA <= x"00";
when x"923" => DATA <= x"6C";
when x"924" => DATA <= x"C9";
when x"925" => DATA <= x"00";
when x"926" => DATA <= x"20";
when x"927" => DATA <= x"D1";
when x"928" => DATA <= x"F7";
when x"929" => DATA <= x"43";
when x"92A" => DATA <= x"4F";
when x"92B" => DATA <= x"4D";
when x"92C" => DATA <= x"3F";
when x"92D" => DATA <= x"EA";
when x"92E" => DATA <= x"00";
when x"92F" => DATA <= x"20";
when x"930" => DATA <= x"8E";
when x"931" => DATA <= x"FB";
when x"932" => DATA <= x"50";
when x"933" => DATA <= x"FA";
when x"934" => DATA <= x"F0";
when x"935" => DATA <= x"F9";
when x"936" => DATA <= x"20";
when x"937" => DATA <= x"2B";
when x"938" => DATA <= x"FC";
when x"939" => DATA <= x"A0";
when x"93A" => DATA <= x"00";
when x"93B" => DATA <= x"20";
when x"93C" => DATA <= x"D4";
when x"93D" => DATA <= x"FF";
when x"93E" => DATA <= x"91";
when x"93F" => DATA <= x"CB";
when x"940" => DATA <= x"E6";
when x"941" => DATA <= x"CB";
when x"942" => DATA <= x"D0";
when x"943" => DATA <= x"02";
when x"944" => DATA <= x"E6";
when x"945" => DATA <= x"CC";
when x"946" => DATA <= x"A2";
when x"947" => DATA <= x"D4";
when x"948" => DATA <= x"20";
when x"949" => DATA <= x"08";
when x"94A" => DATA <= x"FA";
when x"94B" => DATA <= x"D0";
when x"94C" => DATA <= x"EE";
when x"94D" => DATA <= x"38";
when x"94E" => DATA <= x"66";
when x"94F" => DATA <= x"DD";
when x"950" => DATA <= x"18";
when x"951" => DATA <= x"66";
when x"952" => DATA <= x"DD";
when x"953" => DATA <= x"28";
when x"954" => DATA <= x"60";
when x"955" => DATA <= x"38";
when x"956" => DATA <= x"66";
when x"957" => DATA <= x"DD";
when x"958" => DATA <= x"20";
when x"959" => DATA <= x"18";
when x"95A" => DATA <= x"F8";
when x"95B" => DATA <= x"A2";
when x"95C" => DATA <= x"CB";
when x"95D" => DATA <= x"20";
when x"95E" => DATA <= x"93";
when x"95F" => DATA <= x"F8";
when x"960" => DATA <= x"F0";
when x"961" => DATA <= x"04";
when x"962" => DATA <= x"A9";
when x"963" => DATA <= x"FF";
when x"964" => DATA <= x"85";
when x"965" => DATA <= x"CD";
when x"966" => DATA <= x"20";
when x"967" => DATA <= x"76";
when x"968" => DATA <= x"FA";
when x"969" => DATA <= x"A2";
when x"96A" => DATA <= x"C9";
when x"96B" => DATA <= x"6C";
when x"96C" => DATA <= x"0C";
when x"96D" => DATA <= x"02";
when x"96E" => DATA <= x"08";
when x"96F" => DATA <= x"78";
when x"970" => DATA <= x"20";
when x"971" => DATA <= x"4F";
when x"972" => DATA <= x"F8";
when x"973" => DATA <= x"08";
when x"974" => DATA <= x"20";
when x"975" => DATA <= x"3E";
when x"976" => DATA <= x"FC";
when x"977" => DATA <= x"28";
when x"978" => DATA <= x"F0";
when x"979" => DATA <= x"B5";
when x"97A" => DATA <= x"A9";
when x"97B" => DATA <= x"00";
when x"97C" => DATA <= x"85";
when x"97D" => DATA <= x"D0";
when x"97E" => DATA <= x"85";
when x"97F" => DATA <= x"D1";
when x"980" => DATA <= x"20";
when x"981" => DATA <= x"A2";
when x"982" => DATA <= x"F9";
when x"983" => DATA <= x"90";
when x"984" => DATA <= x"C9";
when x"985" => DATA <= x"E6";
when x"986" => DATA <= x"D0";
when x"987" => DATA <= x"E6";
when x"988" => DATA <= x"CC";
when x"989" => DATA <= x"D0";
when x"98A" => DATA <= x"F5";
when x"98B" => DATA <= x"18";
when x"98C" => DATA <= x"90";
when x"98D" => DATA <= x"C0";
when x"98E" => DATA <= x"20";
when x"98F" => DATA <= x"F4";
when x"990" => DATA <= x"FF";
when x"991" => DATA <= x"C8";
when x"992" => DATA <= x"B9";
when x"993" => DATA <= x"ED";
when x"994" => DATA <= x"00";
when x"995" => DATA <= x"C9";
when x"996" => DATA <= x"0D";
when x"997" => DATA <= x"D0";
when x"998" => DATA <= x"F5";
when x"999" => DATA <= x"C8";
when x"99A" => DATA <= x"20";
when x"99B" => DATA <= x"FD";
when x"99C" => DATA <= x"F7";
when x"99D" => DATA <= x"C0";
when x"99E" => DATA <= x"0E";
when x"99F" => DATA <= x"90";
when x"9A0" => DATA <= x"F8";
when x"9A1" => DATA <= x"60";
when x"9A2" => DATA <= x"A9";
when x"9A3" => DATA <= x"00";
when x"9A4" => DATA <= x"85";
when x"9A5" => DATA <= x"DC";
when x"9A6" => DATA <= x"20";
when x"9A7" => DATA <= x"8E";
when x"9A8" => DATA <= x"FB";
when x"9A9" => DATA <= x"50";
when x"9AA" => DATA <= x"F8";
when x"9AB" => DATA <= x"D0";
when x"9AC" => DATA <= x"F5";
when x"9AD" => DATA <= x"20";
when x"9AE" => DATA <= x"C9";
when x"9AF" => DATA <= x"FB";
when x"9B0" => DATA <= x"08";
when x"9B1" => DATA <= x"20";
when x"9B2" => DATA <= x"E2";
when x"9B3" => DATA <= x"FB";
when x"9B4" => DATA <= x"28";
when x"9B5" => DATA <= x"F0";
when x"9B6" => DATA <= x"10";
when x"9B7" => DATA <= x"A5";
when x"9B8" => DATA <= x"DB";
when x"9B9" => DATA <= x"29";
when x"9BA" => DATA <= x"20";
when x"9BB" => DATA <= x"05";
when x"9BC" => DATA <= x"EA";
when x"9BD" => DATA <= x"D0";
when x"9BE" => DATA <= x"E3";
when x"9BF" => DATA <= x"20";
when x"9C0" => DATA <= x"92";
when x"9C1" => DATA <= x"F9";
when x"9C2" => DATA <= x"20";
when x"9C3" => DATA <= x"ED";
when x"9C4" => DATA <= x"FF";
when x"9C5" => DATA <= x"D0";
when x"9C6" => DATA <= x"DB";
when x"9C7" => DATA <= x"A2";
when x"9C8" => DATA <= x"02";
when x"9C9" => DATA <= x"A5";
when x"9CA" => DATA <= x"DD";
when x"9CB" => DATA <= x"30";
when x"9CC" => DATA <= x"13";
when x"9CD" => DATA <= x"B5";
when x"9CE" => DATA <= x"CF";
when x"9CF" => DATA <= x"D5";
when x"9D0" => DATA <= x"D8";
when x"9D1" => DATA <= x"B0";
when x"9D2" => DATA <= x"08";
when x"9D3" => DATA <= x"A9";
when x"9D4" => DATA <= x"05";
when x"9D5" => DATA <= x"20";
when x"9D6" => DATA <= x"40";
when x"9D7" => DATA <= x"FC";
when x"9D8" => DATA <= x"20";
when x"9D9" => DATA <= x"3E";
when x"9DA" => DATA <= x"FC";
when x"9DB" => DATA <= x"D0";
when x"9DC" => DATA <= x"C5";
when x"9DD" => DATA <= x"CA";
when x"9DE" => DATA <= x"D0";
when x"9DF" => DATA <= x"ED";
when x"9E0" => DATA <= x"20";
when x"9E1" => DATA <= x"2B";
when x"9E2" => DATA <= x"FC";
when x"9E3" => DATA <= x"24";
when x"9E4" => DATA <= x"DB";
when x"9E5" => DATA <= x"50";
when x"9E6" => DATA <= x"0B";
when x"9E7" => DATA <= x"88";
when x"9E8" => DATA <= x"C8";
when x"9E9" => DATA <= x"20";
when x"9EA" => DATA <= x"D4";
when x"9EB" => DATA <= x"FF";
when x"9EC" => DATA <= x"91";
when x"9ED" => DATA <= x"CB";
when x"9EE" => DATA <= x"C4";
when x"9EF" => DATA <= x"D8";
when x"9F0" => DATA <= x"D0";
when x"9F1" => DATA <= x"F6";
when x"9F2" => DATA <= x"A5";
when x"9F3" => DATA <= x"DC";
when x"9F4" => DATA <= x"85";
when x"9F5" => DATA <= x"CE";
when x"9F6" => DATA <= x"20";
when x"9F7" => DATA <= x"D4";
when x"9F8" => DATA <= x"FF";
when x"9F9" => DATA <= x"C5";
when x"9FA" => DATA <= x"CE";
when x"9FB" => DATA <= x"F0";
when x"9FC" => DATA <= x"08";
when x"9FD" => DATA <= x"20";
when x"9FE" => DATA <= x"D1";
when x"9FF" => DATA <= x"F7";
when x"A00" => DATA <= x"53";
when x"A01" => DATA <= x"55";
when x"A02" => DATA <= x"4D";
when x"A03" => DATA <= x"EA";
when x"A04" => DATA <= x"00";
when x"A05" => DATA <= x"26";
when x"A06" => DATA <= x"DB";
when x"A07" => DATA <= x"60";
when x"A08" => DATA <= x"F6";
when x"A09" => DATA <= x"00";
when x"A0A" => DATA <= x"D0";
when x"A0B" => DATA <= x"02";
when x"A0C" => DATA <= x"F6";
when x"A0D" => DATA <= x"01";
when x"A0E" => DATA <= x"B5";
when x"A0F" => DATA <= x"00";
when x"A10" => DATA <= x"D5";
when x"A11" => DATA <= x"02";
when x"A12" => DATA <= x"D0";
when x"A13" => DATA <= x"04";
when x"A14" => DATA <= x"B5";
when x"A15" => DATA <= x"01";
when x"A16" => DATA <= x"D5";
when x"A17" => DATA <= x"03";
when x"A18" => DATA <= x"60";
when x"A19" => DATA <= x"CA";
when x"A1A" => DATA <= x"20";
when x"A1B" => DATA <= x"76";
when x"A1C" => DATA <= x"FA";
when x"A1D" => DATA <= x"86";
when x"A1E" => DATA <= x"EA";
when x"A1F" => DATA <= x"60";
when x"A20" => DATA <= x"20";
when x"A21" => DATA <= x"58";
when x"A22" => DATA <= x"F9";
when x"A23" => DATA <= x"24";
when x"A24" => DATA <= x"DD";
when x"A25" => DATA <= x"70";
when x"A26" => DATA <= x"4C";
when x"A27" => DATA <= x"6C";
when x"A28" => DATA <= x"D6";
when x"A29" => DATA <= x"00";
when x"A2A" => DATA <= x"08";
when x"A2B" => DATA <= x"20";
when x"A2C" => DATA <= x"76";
when x"A2D" => DATA <= x"FA";
when x"A2E" => DATA <= x"20";
when x"A2F" => DATA <= x"3E";
when x"A30" => DATA <= x"FC";
when x"A31" => DATA <= x"20";
when x"A32" => DATA <= x"8E";
when x"A33" => DATA <= x"FB";
when x"A34" => DATA <= x"70";
when x"A35" => DATA <= x"02";
when x"A36" => DATA <= x"28";
when x"A37" => DATA <= x"60";
when x"A38" => DATA <= x"F0";
when x"A39" => DATA <= x"0A";
when x"A3A" => DATA <= x"A0";
when x"A3B" => DATA <= x"00";
when x"A3C" => DATA <= x"20";
when x"A3D" => DATA <= x"99";
when x"A3E" => DATA <= x"F9";
when x"A3F" => DATA <= x"20";
when x"A40" => DATA <= x"EC";
when x"A41" => DATA <= x"F7";
when x"A42" => DATA <= x"D0";
when x"A43" => DATA <= x"19";
when x"A44" => DATA <= x"20";
when x"A45" => DATA <= x"C9";
when x"A46" => DATA <= x"FB";
when x"A47" => DATA <= x"20";
when x"A48" => DATA <= x"E2";
when x"A49" => DATA <= x"FB";
when x"A4A" => DATA <= x"20";
when x"A4B" => DATA <= x"92";
when x"A4C" => DATA <= x"F9";
when x"A4D" => DATA <= x"20";
when x"A4E" => DATA <= x"EC";
when x"A4F" => DATA <= x"F7";
when x"A50" => DATA <= x"26";
when x"A51" => DATA <= x"DB";
when x"A52" => DATA <= x"10";
when x"A53" => DATA <= x"09";
when x"A54" => DATA <= x"E8";
when x"A55" => DATA <= x"20";
when x"A56" => DATA <= x"F1";
when x"A57" => DATA <= x"F7";
when x"A58" => DATA <= x"B5";
when x"A59" => DATA <= x"FD";
when x"A5A" => DATA <= x"20";
when x"A5B" => DATA <= x"02";
when x"A5C" => DATA <= x"F8";
when x"A5D" => DATA <= x"20";
when x"A5E" => DATA <= x"ED";
when x"A5F" => DATA <= x"FF";
when x"A60" => DATA <= x"D0";
when x"A61" => DATA <= x"CF";
when x"A62" => DATA <= x"4C";
when x"A63" => DATA <= x"ED";
when x"A64" => DATA <= x"FF";
when x"A65" => DATA <= x"20";
when x"A66" => DATA <= x"93";
when x"A67" => DATA <= x"F8";
when x"A68" => DATA <= x"F0";
when x"A69" => DATA <= x"13";
when x"A6A" => DATA <= x"60";
when x"A6B" => DATA <= x"A2";
when x"A6C" => DATA <= x"CB";
when x"A6D" => DATA <= x"20";
when x"A6E" => DATA <= x"65";
when x"A6F" => DATA <= x"FA";
when x"A70" => DATA <= x"20";
when x"A71" => DATA <= x"76";
when x"A72" => DATA <= x"FA";
when x"A73" => DATA <= x"6C";
when x"A74" => DATA <= x"CB";
when x"A75" => DATA <= x"00";
when x"A76" => DATA <= x"20";
when x"A77" => DATA <= x"76";
when x"A78" => DATA <= x"F8";
when x"A79" => DATA <= x"C9";
when x"A7A" => DATA <= x"0D";
when x"A7B" => DATA <= x"F0";
when x"A7C" => DATA <= x"A2";
when x"A7D" => DATA <= x"20";
when x"A7E" => DATA <= x"D1";
when x"A7F" => DATA <= x"F7";
when x"A80" => DATA <= x"53";
when x"A81" => DATA <= x"59";
when x"A82" => DATA <= x"4E";
when x"A83" => DATA <= x"3F";
when x"A84" => DATA <= x"EA";
when x"A85" => DATA <= x"00";
when x"A86" => DATA <= x"38";
when x"A87" => DATA <= x"A5";
when x"A88" => DATA <= x"D1";
when x"A89" => DATA <= x"E5";
when x"A8A" => DATA <= x"CF";
when x"A8B" => DATA <= x"48";
when x"A8C" => DATA <= x"A5";
when x"A8D" => DATA <= x"D2";
when x"A8E" => DATA <= x"E5";
when x"A8F" => DATA <= x"D0";
when x"A90" => DATA <= x"A8";
when x"A91" => DATA <= x"68";
when x"A92" => DATA <= x"18";
when x"A93" => DATA <= x"65";
when x"A94" => DATA <= x"CB";
when x"A95" => DATA <= x"85";
when x"A96" => DATA <= x"CD";
when x"A97" => DATA <= x"98";
when x"A98" => DATA <= x"65";
when x"A99" => DATA <= x"CC";
when x"A9A" => DATA <= x"85";
when x"A9B" => DATA <= x"CE";
when x"A9C" => DATA <= x"A0";
when x"A9D" => DATA <= x"04";
when x"A9E" => DATA <= x"B9";
when x"A9F" => DATA <= x"CA";
when x"AA0" => DATA <= x"00";
when x"AA1" => DATA <= x"20";
when x"AA2" => DATA <= x"D1";
when x"AA3" => DATA <= x"FF";
when x"AA4" => DATA <= x"88";
when x"AA5" => DATA <= x"D0";
when x"AA6" => DATA <= x"F7";
when x"AA7" => DATA <= x"B1";
when x"AA8" => DATA <= x"CF";
when x"AA9" => DATA <= x"20";
when x"AAA" => DATA <= x"D1";
when x"AAB" => DATA <= x"FF";
when x"AAC" => DATA <= x"E6";
when x"AAD" => DATA <= x"CF";
when x"AAE" => DATA <= x"D0";
when x"AAF" => DATA <= x"02";
when x"AB0" => DATA <= x"E6";
when x"AB1" => DATA <= x"D0";
when x"AB2" => DATA <= x"A2";
when x"AB3" => DATA <= x"CB";
when x"AB4" => DATA <= x"20";
when x"AB5" => DATA <= x"08";
when x"AB6" => DATA <= x"FA";
when x"AB7" => DATA <= x"D0";
when x"AB8" => DATA <= x"EE";
when x"AB9" => DATA <= x"28";
when x"ABA" => DATA <= x"60";
when x"ABB" => DATA <= x"20";
when x"ABC" => DATA <= x"18";
when x"ABD" => DATA <= x"F8";
when x"ABE" => DATA <= x"A2";
when x"ABF" => DATA <= x"CB";
when x"AC0" => DATA <= x"20";
when x"AC1" => DATA <= x"65";
when x"AC2" => DATA <= x"FA";
when x"AC3" => DATA <= x"A2";
when x"AC4" => DATA <= x"D1";
when x"AC5" => DATA <= x"20";
when x"AC6" => DATA <= x"65";
when x"AC7" => DATA <= x"FA";
when x"AC8" => DATA <= x"A2";
when x"AC9" => DATA <= x"CD";
when x"ACA" => DATA <= x"20";
when x"ACB" => DATA <= x"93";
when x"ACC" => DATA <= x"F8";
when x"ACD" => DATA <= x"08";
when x"ACE" => DATA <= x"A5";
when x"ACF" => DATA <= x"CB";
when x"AD0" => DATA <= x"A6";
when x"AD1" => DATA <= x"CC";
when x"AD2" => DATA <= x"28";
when x"AD3" => DATA <= x"D0";
when x"AD4" => DATA <= x"04";
when x"AD5" => DATA <= x"85";
when x"AD6" => DATA <= x"CD";
when x"AD7" => DATA <= x"86";
when x"AD8" => DATA <= x"CE";
when x"AD9" => DATA <= x"85";
when x"ADA" => DATA <= x"CF";
when x"ADB" => DATA <= x"86";
when x"ADC" => DATA <= x"D0";
when x"ADD" => DATA <= x"20";
when x"ADE" => DATA <= x"76";
when x"ADF" => DATA <= x"FA";
when x"AE0" => DATA <= x"A2";
when x"AE1" => DATA <= x"C9";
when x"AE2" => DATA <= x"6C";
when x"AE3" => DATA <= x"0E";
when x"AE4" => DATA <= x"02";
when x"AE5" => DATA <= x"08";
when x"AE6" => DATA <= x"78";
when x"AE7" => DATA <= x"20";
when x"AE8" => DATA <= x"4F";
when x"AE9" => DATA <= x"F8";
when x"AEA" => DATA <= x"08";
when x"AEB" => DATA <= x"A9";
when x"AEC" => DATA <= x"06";
when x"AED" => DATA <= x"20";
when x"AEE" => DATA <= x"40";
when x"AEF" => DATA <= x"FC";
when x"AF0" => DATA <= x"A2";
when x"AF1" => DATA <= x"07";
when x"AF2" => DATA <= x"20";
when x"AF3" => DATA <= x"7A";
when x"AF4" => DATA <= x"FB";
when x"AF5" => DATA <= x"28";
when x"AF6" => DATA <= x"F0";
when x"AF7" => DATA <= x"8E";
when x"AF8" => DATA <= x"A2";
when x"AF9" => DATA <= x"04";
when x"AFA" => DATA <= x"B5";
when x"AFB" => DATA <= x"CE";
when x"AFC" => DATA <= x"95";
when x"AFD" => DATA <= x"D2";
when x"AFE" => DATA <= x"CA";
when x"AFF" => DATA <= x"D0";
when x"B00" => DATA <= x"F9";
when x"B01" => DATA <= x"86";
when x"B02" => DATA <= x"D0";
when x"B03" => DATA <= x"86";
when x"B04" => DATA <= x"D1";
when x"B05" => DATA <= x"A5";
when x"B06" => DATA <= x"D5";
when x"B07" => DATA <= x"D0";
when x"B08" => DATA <= x"02";
when x"B09" => DATA <= x"C6";
when x"B0A" => DATA <= x"D6";
when x"B0B" => DATA <= x"C6";
when x"B0C" => DATA <= x"D5";
when x"B0D" => DATA <= x"18";
when x"B0E" => DATA <= x"66";
when x"B0F" => DATA <= x"D2";
when x"B10" => DATA <= x"38";
when x"B11" => DATA <= x"A2";
when x"B12" => DATA <= x"FF";
when x"B13" => DATA <= x"A5";
when x"B14" => DATA <= x"D5";
when x"B15" => DATA <= x"E5";
when x"B16" => DATA <= x"D3";
when x"B17" => DATA <= x"85";
when x"B18" => DATA <= x"CF";
when x"B19" => DATA <= x"A5";
when x"B1A" => DATA <= x"D6";
when x"B1B" => DATA <= x"E5";
when x"B1C" => DATA <= x"D4";
when x"B1D" => DATA <= x"08";
when x"B1E" => DATA <= x"66";
when x"B1F" => DATA <= x"D2";
when x"B20" => DATA <= x"28";
when x"B21" => DATA <= x"90";
when x"B22" => DATA <= x"06";
when x"B23" => DATA <= x"18";
when x"B24" => DATA <= x"F0";
when x"B25" => DATA <= x"03";
when x"B26" => DATA <= x"86";
when x"B27" => DATA <= x"CF";
when x"B28" => DATA <= x"38";
when x"B29" => DATA <= x"66";
when x"B2A" => DATA <= x"D2";
when x"B2B" => DATA <= x"E8";
when x"B2C" => DATA <= x"20";
when x"B2D" => DATA <= x"3B";
when x"B2E" => DATA <= x"FB";
when x"B2F" => DATA <= x"E6";
when x"B30" => DATA <= x"D0";
when x"B31" => DATA <= x"E6";
when x"B32" => DATA <= x"D4";
when x"B33" => DATA <= x"E6";
when x"B34" => DATA <= x"CC";
when x"B35" => DATA <= x"26";
when x"B36" => DATA <= x"D2";
when x"B37" => DATA <= x"B0";
when x"B38" => DATA <= x"D5";
when x"B39" => DATA <= x"28";
when x"B3A" => DATA <= x"60";
when x"B3B" => DATA <= x"A2";
when x"B3C" => DATA <= x"07";
when x"B3D" => DATA <= x"20";
when x"B3E" => DATA <= x"7A";
when x"B3F" => DATA <= x"FB";
when x"B40" => DATA <= x"86";
when x"B41" => DATA <= x"DC";
when x"B42" => DATA <= x"A0";
when x"B43" => DATA <= x"04";
when x"B44" => DATA <= x"A9";
when x"B45" => DATA <= x"2A";
when x"B46" => DATA <= x"20";
when x"B47" => DATA <= x"D1";
when x"B48" => DATA <= x"FF";
when x"B49" => DATA <= x"88";
when x"B4A" => DATA <= x"D0";
when x"B4B" => DATA <= x"F8";
when x"B4C" => DATA <= x"B1";
when x"B4D" => DATA <= x"C9";
when x"B4E" => DATA <= x"20";
when x"B4F" => DATA <= x"D1";
when x"B50" => DATA <= x"FF";
when x"B51" => DATA <= x"C8";
when x"B52" => DATA <= x"C9";
when x"B53" => DATA <= x"0D";
when x"B54" => DATA <= x"D0";
when x"B55" => DATA <= x"F6";
when x"B56" => DATA <= x"A0";
when x"B57" => DATA <= x"08";
when x"B58" => DATA <= x"B9";
when x"B59" => DATA <= x"CA";
when x"B5A" => DATA <= x"00";
when x"B5B" => DATA <= x"20";
when x"B5C" => DATA <= x"D1";
when x"B5D" => DATA <= x"FF";
when x"B5E" => DATA <= x"88";
when x"B5F" => DATA <= x"D0";
when x"B60" => DATA <= x"F7";
when x"B61" => DATA <= x"20";
when x"B62" => DATA <= x"81";
when x"B63" => DATA <= x"FB";
when x"B64" => DATA <= x"24";
when x"B65" => DATA <= x"D2";
when x"B66" => DATA <= x"50";
when x"B67" => DATA <= x"0B";
when x"B68" => DATA <= x"88";
when x"B69" => DATA <= x"C8";
when x"B6A" => DATA <= x"B1";
when x"B6B" => DATA <= x"D3";
when x"B6C" => DATA <= x"20";
when x"B6D" => DATA <= x"D1";
when x"B6E" => DATA <= x"FF";
when x"B6F" => DATA <= x"C4";
when x"B70" => DATA <= x"CF";
when x"B71" => DATA <= x"D0";
when x"B72" => DATA <= x"F6";
when x"B73" => DATA <= x"A5";
when x"B74" => DATA <= x"DC";
when x"B75" => DATA <= x"20";
when x"B76" => DATA <= x"D1";
when x"B77" => DATA <= x"FF";
when x"B78" => DATA <= x"A2";
when x"B79" => DATA <= x"04";
when x"B7A" => DATA <= x"8E";
when x"B7B" => DATA <= x"02";
when x"B7C" => DATA <= x"B0";
when x"B7D" => DATA <= x"A2";
when x"B7E" => DATA <= x"78";
when x"B7F" => DATA <= x"D0";
when x"B80" => DATA <= x"02";
when x"B81" => DATA <= x"A2";
when x"B82" => DATA <= x"1E";
when x"B83" => DATA <= x"20";
when x"B84" => DATA <= x"66";
when x"B85" => DATA <= x"FE";
when x"B86" => DATA <= x"CA";
when x"B87" => DATA <= x"D0";
when x"B88" => DATA <= x"FA";
when x"B89" => DATA <= x"60";
when x"B8A" => DATA <= x"A2";
when x"B8B" => DATA <= x"06";
when x"B8C" => DATA <= x"D0";
when x"B8D" => DATA <= x"F5";
when x"B8E" => DATA <= x"2C";
when x"B8F" => DATA <= x"01";
when x"B90" => DATA <= x"B0";
when x"B91" => DATA <= x"10";
when x"B92" => DATA <= x"FB";
when x"B93" => DATA <= x"50";
when x"B94" => DATA <= x"F9";
when x"B95" => DATA <= x"A0";
when x"B96" => DATA <= x"00";
when x"B97" => DATA <= x"85";
when x"B98" => DATA <= x"C3";
when x"B99" => DATA <= x"A9";
when x"B9A" => DATA <= x"10";
when x"B9B" => DATA <= x"85";
when x"B9C" => DATA <= x"C2";
when x"B9D" => DATA <= x"2C";
when x"B9E" => DATA <= x"01";
when x"B9F" => DATA <= x"B0";
when x"BA0" => DATA <= x"10";
when x"BA1" => DATA <= x"0F";
when x"BA2" => DATA <= x"50";
when x"BA3" => DATA <= x"0D";
when x"BA4" => DATA <= x"20";
when x"BA5" => DATA <= x"BD";
when x"BA6" => DATA <= x"FC";
when x"BA7" => DATA <= x"B0";
when x"BA8" => DATA <= x"EC";
when x"BA9" => DATA <= x"C6";
when x"BAA" => DATA <= x"C3";
when x"BAB" => DATA <= x"D0";
when x"BAC" => DATA <= x"F0";
when x"BAD" => DATA <= x"C6";
when x"BAE" => DATA <= x"C2";
when x"BAF" => DATA <= x"D0";
when x"BB0" => DATA <= x"EC";
when x"BB1" => DATA <= x"70";
when x"BB2" => DATA <= x"01";
when x"BB3" => DATA <= x"60";
when x"BB4" => DATA <= x"A0";
when x"BB5" => DATA <= x"04";
when x"BB6" => DATA <= x"08";
when x"BB7" => DATA <= x"20";
when x"BB8" => DATA <= x"E4";
when x"BB9" => DATA <= x"FB";
when x"BBA" => DATA <= x"28";
when x"BBB" => DATA <= x"A0";
when x"BBC" => DATA <= x"04";
when x"BBD" => DATA <= x"A9";
when x"BBE" => DATA <= x"2A";
when x"BBF" => DATA <= x"D9";
when x"BC0" => DATA <= x"D3";
when x"BC1" => DATA <= x"00";
when x"BC2" => DATA <= x"D0";
when x"BC3" => DATA <= x"03";
when x"BC4" => DATA <= x"88";
when x"BC5" => DATA <= x"D0";
when x"BC6" => DATA <= x"F8";
when x"BC7" => DATA <= x"60";
when x"BC8" => DATA <= x"C8";
when x"BC9" => DATA <= x"20";
when x"BCA" => DATA <= x"D4";
when x"BCB" => DATA <= x"FF";
when x"BCC" => DATA <= x"99";
when x"BCD" => DATA <= x"ED";
when x"BCE" => DATA <= x"00";
when x"BCF" => DATA <= x"C9";
when x"BD0" => DATA <= x"0D";
when x"BD1" => DATA <= x"D0";
when x"BD2" => DATA <= x"F5";
when x"BD3" => DATA <= x"A0";
when x"BD4" => DATA <= x"FF";
when x"BD5" => DATA <= x"C8";
when x"BD6" => DATA <= x"B1";
when x"BD7" => DATA <= x"C9";
when x"BD8" => DATA <= x"D9";
when x"BD9" => DATA <= x"ED";
when x"BDA" => DATA <= x"00";
when x"BDB" => DATA <= x"D0";
when x"BDC" => DATA <= x"EA";
when x"BDD" => DATA <= x"C9";
when x"BDE" => DATA <= x"0D";
when x"BDF" => DATA <= x"D0";
when x"BE0" => DATA <= x"F4";
when x"BE1" => DATA <= x"60";
when x"BE2" => DATA <= x"A0";
when x"BE3" => DATA <= x"08";
when x"BE4" => DATA <= x"20";
when x"BE5" => DATA <= x"D4";
when x"BE6" => DATA <= x"FF";
when x"BE7" => DATA <= x"99";
when x"BE8" => DATA <= x"D3";
when x"BE9" => DATA <= x"00";
when x"BEA" => DATA <= x"88";
when x"BEB" => DATA <= x"D0";
when x"BEC" => DATA <= x"F7";
when x"BED" => DATA <= x"60";
when x"BEE" => DATA <= x"86";
when x"BEF" => DATA <= x"EC";
when x"BF0" => DATA <= x"84";
when x"BF1" => DATA <= x"C3";
when x"BF2" => DATA <= x"08";
when x"BF3" => DATA <= x"78";
when x"BF4" => DATA <= x"A9";
when x"BF5" => DATA <= x"78";
when x"BF6" => DATA <= x"85";
when x"BF7" => DATA <= x"C0";
when x"BF8" => DATA <= x"20";
when x"BF9" => DATA <= x"BD";
when x"BFA" => DATA <= x"FC";
when x"BFB" => DATA <= x"90";
when x"BFC" => DATA <= x"F7";
when x"BFD" => DATA <= x"E6";
when x"BFE" => DATA <= x"C0";
when x"BFF" => DATA <= x"10";
when x"C00" => DATA <= x"F7";
when x"C01" => DATA <= x"A9";
when x"C02" => DATA <= x"53";
when x"C03" => DATA <= x"85";
when x"C04" => DATA <= x"C4";
when x"C05" => DATA <= x"A2";
when x"C06" => DATA <= x"00";
when x"C07" => DATA <= x"AC";
when x"C08" => DATA <= x"02";
when x"C09" => DATA <= x"B0";
when x"C0A" => DATA <= x"20";
when x"C0B" => DATA <= x"CD";
when x"C0C" => DATA <= x"FC";
when x"C0D" => DATA <= x"F0";
when x"C0E" => DATA <= x"00";
when x"C0F" => DATA <= x"F0";
when x"C10" => DATA <= x"01";
when x"C11" => DATA <= x"E8";
when x"C12" => DATA <= x"C6";
when x"C13" => DATA <= x"C4";
when x"C14" => DATA <= x"D0";
when x"C15" => DATA <= x"F4";
when x"C16" => DATA <= x"E0";
when x"C17" => DATA <= x"0C";
when x"C18" => DATA <= x"66";
when x"C19" => DATA <= x"C0";
when x"C1A" => DATA <= x"90";
when x"C1B" => DATA <= x"E5";
when x"C1C" => DATA <= x"A5";
when x"C1D" => DATA <= x"C0";
when x"C1E" => DATA <= x"28";
when x"C1F" => DATA <= x"A4";
when x"C20" => DATA <= x"C3";
when x"C21" => DATA <= x"A6";
when x"C22" => DATA <= x"EC";
when x"C23" => DATA <= x"48";
when x"C24" => DATA <= x"18";
when x"C25" => DATA <= x"65";
when x"C26" => DATA <= x"DC";
when x"C27" => DATA <= x"85";
when x"C28" => DATA <= x"DC";
when x"C29" => DATA <= x"68";
when x"C2A" => DATA <= x"60";
when x"C2B" => DATA <= x"A5";
when x"C2C" => DATA <= x"CD";
when x"C2D" => DATA <= x"30";
when x"C2E" => DATA <= x"08";
when x"C2F" => DATA <= x"A5";
when x"C30" => DATA <= x"D4";
when x"C31" => DATA <= x"85";
when x"C32" => DATA <= x"CB";
when x"C33" => DATA <= x"A5";
when x"C34" => DATA <= x"D5";
when x"C35" => DATA <= x"85";
when x"C36" => DATA <= x"CC";
when x"C37" => DATA <= x"60";
when x"C38" => DATA <= x"B0";
when x"C39" => DATA <= x"04";
when x"C3A" => DATA <= x"A9";
when x"C3B" => DATA <= x"06";
when x"C3C" => DATA <= x"D0";
when x"C3D" => DATA <= x"02";
when x"C3E" => DATA <= x"A9";
when x"C3F" => DATA <= x"04";
when x"C40" => DATA <= x"A2";
when x"C41" => DATA <= x"07";
when x"C42" => DATA <= x"8E";
when x"C43" => DATA <= x"02";
when x"C44" => DATA <= x"B0";
when x"C45" => DATA <= x"24";
when x"C46" => DATA <= x"EA";
when x"C47" => DATA <= x"D0";
when x"C48" => DATA <= x"2D";
when x"C49" => DATA <= x"C9";
when x"C4A" => DATA <= x"05";
when x"C4B" => DATA <= x"F0";
when x"C4C" => DATA <= x"16";
when x"C4D" => DATA <= x"B0";
when x"C4E" => DATA <= x"09";
when x"C4F" => DATA <= x"20";
when x"C50" => DATA <= x"D1";
when x"C51" => DATA <= x"F7";
when x"C52" => DATA <= x"50";
when x"C53" => DATA <= x"4C";
when x"C54" => DATA <= x"41";
when x"C55" => DATA <= x"59";
when x"C56" => DATA <= x"D0";
when x"C57" => DATA <= x"15";
when x"C58" => DATA <= x"20";
when x"C59" => DATA <= x"D1";
when x"C5A" => DATA <= x"F7";
when x"C5B" => DATA <= x"52";
when x"C5C" => DATA <= x"45";
when x"C5D" => DATA <= x"43";
when x"C5E" => DATA <= x"4F";
when x"C5F" => DATA <= x"52";
when x"C60" => DATA <= x"44";
when x"C61" => DATA <= x"D0";
when x"C62" => DATA <= x"0A";
when x"C63" => DATA <= x"20";
when x"C64" => DATA <= x"D1";
when x"C65" => DATA <= x"F7";
when x"C66" => DATA <= x"52";
when x"C67" => DATA <= x"45";
when x"C68" => DATA <= x"57";
when x"C69" => DATA <= x"49";
when x"C6A" => DATA <= x"4E";
when x"C6B" => DATA <= x"44";
when x"C6C" => DATA <= x"EA";
when x"C6D" => DATA <= x"20";
when x"C6E" => DATA <= x"D1";
when x"C6F" => DATA <= x"F7";
when x"C70" => DATA <= x"20";
when x"C71" => DATA <= x"54";
when x"C72" => DATA <= x"41";
when x"C73" => DATA <= x"50";
when x"C74" => DATA <= x"45";
when x"C75" => DATA <= x"EA";
when x"C76" => DATA <= x"20";
when x"C77" => DATA <= x"E3";
when x"C78" => DATA <= x"FF";
when x"C79" => DATA <= x"4C";
when x"C7A" => DATA <= x"ED";
when x"C7B" => DATA <= x"FF";
when x"C7C" => DATA <= x"86";
when x"C7D" => DATA <= x"EC";
when x"C7E" => DATA <= x"84";
when x"C7F" => DATA <= x"C3";
when x"C80" => DATA <= x"08";
when x"C81" => DATA <= x"78";
when x"C82" => DATA <= x"48";
when x"C83" => DATA <= x"20";
when x"C84" => DATA <= x"23";
when x"C85" => DATA <= x"FC";
when x"C86" => DATA <= x"85";
when x"C87" => DATA <= x"C0";
when x"C88" => DATA <= x"20";
when x"C89" => DATA <= x"D8";
when x"C8A" => DATA <= x"FC";
when x"C8B" => DATA <= x"A9";
when x"C8C" => DATA <= x"0A";
when x"C8D" => DATA <= x"85";
when x"C8E" => DATA <= x"C1";
when x"C8F" => DATA <= x"18";
when x"C90" => DATA <= x"90";
when x"C91" => DATA <= x"0A";
when x"C92" => DATA <= x"A2";
when x"C93" => DATA <= x"07";
when x"C94" => DATA <= x"8E";
when x"C95" => DATA <= x"02";
when x"C96" => DATA <= x"B0";
when x"C97" => DATA <= x"20";
when x"C98" => DATA <= x"DA";
when x"C99" => DATA <= x"FC";
when x"C9A" => DATA <= x"30";
when x"C9B" => DATA <= x"13";
when x"C9C" => DATA <= x"A0";
when x"C9D" => DATA <= x"04";
when x"C9E" => DATA <= x"A9";
when x"C9F" => DATA <= x"04";
when x"CA0" => DATA <= x"8D";
when x"CA1" => DATA <= x"02";
when x"CA2" => DATA <= x"B0";
when x"CA3" => DATA <= x"20";
when x"CA4" => DATA <= x"D8";
when x"CA5" => DATA <= x"FC";
when x"CA6" => DATA <= x"EE";
when x"CA7" => DATA <= x"02";
when x"CA8" => DATA <= x"B0";
when x"CA9" => DATA <= x"20";
when x"CAA" => DATA <= x"D8";
when x"CAB" => DATA <= x"FC";
when x"CAC" => DATA <= x"88";
when x"CAD" => DATA <= x"D0";
when x"CAE" => DATA <= x"EF";
when x"CAF" => DATA <= x"38";
when x"CB0" => DATA <= x"66";
when x"CB1" => DATA <= x"C0";
when x"CB2" => DATA <= x"C6";
when x"CB3" => DATA <= x"C1";
when x"CB4" => DATA <= x"D0";
when x"CB5" => DATA <= x"DA";
when x"CB6" => DATA <= x"A4";
when x"CB7" => DATA <= x"C3";
when x"CB8" => DATA <= x"A6";
when x"CB9" => DATA <= x"EC";
when x"CBA" => DATA <= x"68";
when x"CBB" => DATA <= x"28";
when x"CBC" => DATA <= x"60";
when x"CBD" => DATA <= x"A2";
when x"CBE" => DATA <= x"00";
when x"CBF" => DATA <= x"AC";
when x"CC0" => DATA <= x"02";
when x"CC1" => DATA <= x"B0";
when x"CC2" => DATA <= x"E8";
when x"CC3" => DATA <= x"F0";
when x"CC4" => DATA <= x"07";
when x"CC5" => DATA <= x"20";
when x"CC6" => DATA <= x"CD";
when x"CC7" => DATA <= x"FC";
when x"CC8" => DATA <= x"F0";
when x"CC9" => DATA <= x"F8";
when x"CCA" => DATA <= x"E0";
when x"CCB" => DATA <= x"08";
when x"CCC" => DATA <= x"60";
when x"CCD" => DATA <= x"84";
when x"CCE" => DATA <= x"C5";
when x"CCF" => DATA <= x"AD";
when x"CD0" => DATA <= x"02";
when x"CD1" => DATA <= x"B0";
when x"CD2" => DATA <= x"A8";
when x"CD3" => DATA <= x"45";
when x"CD4" => DATA <= x"C5";
when x"CD5" => DATA <= x"29";
when x"CD6" => DATA <= x"20";
when x"CD7" => DATA <= x"60";
when x"CD8" => DATA <= x"A2";
when x"CD9" => DATA <= x"00";
when x"CDA" => DATA <= x"A9";
when x"CDB" => DATA <= x"10";
when x"CDC" => DATA <= x"2C";
when x"CDD" => DATA <= x"02";
when x"CDE" => DATA <= x"B0";
when x"CDF" => DATA <= x"F0";
when x"CE0" => DATA <= x"FB";
when x"CE1" => DATA <= x"2C";
when x"CE2" => DATA <= x"02";
when x"CE3" => DATA <= x"B0";
when x"CE4" => DATA <= x"D0";
when x"CE5" => DATA <= x"FB";
when x"CE6" => DATA <= x"CA";
when x"CE7" => DATA <= x"10";
when x"CE8" => DATA <= x"F3";
when x"CE9" => DATA <= x"60";
when x"CEA" => DATA <= x"C9";
when x"CEB" => DATA <= x"06";
when x"CEC" => DATA <= x"F0";
when x"CED" => DATA <= x"1D";
when x"CEE" => DATA <= x"C9";
when x"CEF" => DATA <= x"15";
when x"CF0" => DATA <= x"F0";
when x"CF1" => DATA <= x"1F";
when x"CF2" => DATA <= x"A4";
when x"CF3" => DATA <= x"E0";
when x"CF4" => DATA <= x"30";
when x"CF5" => DATA <= x"23";
when x"CF6" => DATA <= x"C9";
when x"CF7" => DATA <= x"1B";
when x"CF8" => DATA <= x"F0";
when x"CF9" => DATA <= x"11";
when x"CFA" => DATA <= x"C9";
when x"CFB" => DATA <= x"07";
when x"CFC" => DATA <= x"F0";
when x"CFD" => DATA <= x"1C";
when x"CFE" => DATA <= x"20";
when x"CFF" => DATA <= x"44";
when x"D00" => DATA <= x"FD";
when x"D01" => DATA <= x"A2";
when x"D02" => DATA <= x"0A";
when x"D03" => DATA <= x"20";
when x"D04" => DATA <= x"C5";
when x"D05" => DATA <= x"FE";
when x"D06" => DATA <= x"D0";
when x"D07" => DATA <= x"21";
when x"D08" => DATA <= x"4C";
when x"D09" => DATA <= x"B7";
when x"D0A" => DATA <= x"FE";
when x"D0B" => DATA <= x"18";
when x"D0C" => DATA <= x"A2";
when x"D0D" => DATA <= x"00";
when x"D0E" => DATA <= x"8E";
when x"D0F" => DATA <= x"00";
when x"D10" => DATA <= x"B0";
when x"D11" => DATA <= x"A2";
when x"D12" => DATA <= x"02";
when x"D13" => DATA <= x"08";
when x"D14" => DATA <= x"16";
when x"D15" => DATA <= x"DE";
when x"D16" => DATA <= x"28";
when x"D17" => DATA <= x"76";
when x"D18" => DATA <= x"DE";
when x"D19" => DATA <= x"60";
when x"D1A" => DATA <= x"A9";
when x"D1B" => DATA <= x"05";
when x"D1C" => DATA <= x"A8";
when x"D1D" => DATA <= x"8D";
when x"D1E" => DATA <= x"03";
when x"D1F" => DATA <= x"B0";
when x"D20" => DATA <= x"CA";
when x"D21" => DATA <= x"D0";
when x"D22" => DATA <= x"FD";
when x"D23" => DATA <= x"49";
when x"D24" => DATA <= x"01";
when x"D25" => DATA <= x"C8";
when x"D26" => DATA <= x"10";
when x"D27" => DATA <= x"F5";
when x"D28" => DATA <= x"60";
when x"D29" => DATA <= x"C9";
when x"D2A" => DATA <= x"20";
when x"D2B" => DATA <= x"90";
when x"D2C" => DATA <= x"17";
when x"D2D" => DATA <= x"69";
when x"D2E" => DATA <= x"1F";
when x"D2F" => DATA <= x"30";
when x"D30" => DATA <= x"02";
when x"D31" => DATA <= x"49";
when x"D32" => DATA <= x"60";
when x"D33" => DATA <= x"20";
when x"D34" => DATA <= x"6B";
when x"D35" => DATA <= x"FE";
when x"D36" => DATA <= x"91";
when x"D37" => DATA <= x"DE";
when x"D38" => DATA <= x"C8";
when x"D39" => DATA <= x"C0";
when x"D3A" => DATA <= x"20";
when x"D3B" => DATA <= x"90";
when x"D3C" => DATA <= x"05";
when x"D3D" => DATA <= x"20";
when x"D3E" => DATA <= x"EC";
when x"D3F" => DATA <= x"FD";
when x"D40" => DATA <= x"A0";
when x"D41" => DATA <= x"00";
when x"D42" => DATA <= x"84";
when x"D43" => DATA <= x"E0";
when x"D44" => DATA <= x"48";
when x"D45" => DATA <= x"20";
when x"D46" => DATA <= x"6B";
when x"D47" => DATA <= x"FE";
when x"D48" => DATA <= x"B1";
when x"D49" => DATA <= x"DE";
when x"D4A" => DATA <= x"45";
when x"D4B" => DATA <= x"E1";
when x"D4C" => DATA <= x"91";
when x"D4D" => DATA <= x"DE";
when x"D4E" => DATA <= x"68";
when x"D4F" => DATA <= x"60";
when x"D50" => DATA <= x"20";
when x"D51" => DATA <= x"35";
when x"D52" => DATA <= x"FE";
when x"D53" => DATA <= x"A9";
when x"D54" => DATA <= x"20";
when x"D55" => DATA <= x"20";
when x"D56" => DATA <= x"6B";
when x"D57" => DATA <= x"FE";
when x"D58" => DATA <= x"91";
when x"D59" => DATA <= x"DE";
when x"D5A" => DATA <= x"10";
when x"D5B" => DATA <= x"E6";
when x"D5C" => DATA <= x"20";
when x"D5D" => DATA <= x"35";
when x"D5E" => DATA <= x"FE";
when x"D5F" => DATA <= x"4C";
when x"D60" => DATA <= x"42";
when x"D61" => DATA <= x"FD";
when x"D62" => DATA <= x"20";
when x"D63" => DATA <= x"EC";
when x"D64" => DATA <= x"FD";
when x"D65" => DATA <= x"A4";
when x"D66" => DATA <= x"E0";
when x"D67" => DATA <= x"10";
when x"D68" => DATA <= x"D9";
when x"D69" => DATA <= x"A0";
when x"D6A" => DATA <= x"80";
when x"D6B" => DATA <= x"84";
when x"D6C" => DATA <= x"E1";
when x"D6D" => DATA <= x"A0";
when x"D6E" => DATA <= x"00";
when x"D6F" => DATA <= x"8C";
when x"D70" => DATA <= x"00";
when x"D71" => DATA <= x"B0";
when x"D72" => DATA <= x"A9";
when x"D73" => DATA <= x"20";
when x"D74" => DATA <= x"99";
when x"D75" => DATA <= x"00";
when x"D76" => DATA <= x"80";
when x"D77" => DATA <= x"99";
when x"D78" => DATA <= x"00";
when x"D79" => DATA <= x"81";
when x"D7A" => DATA <= x"C8";
when x"D7B" => DATA <= x"D0";
when x"D7C" => DATA <= x"F7";
when x"D7D" => DATA <= x"A9";
when x"D7E" => DATA <= x"80";
when x"D7F" => DATA <= x"A0";
when x"D80" => DATA <= x"00";
when x"D81" => DATA <= x"85";
when x"D82" => DATA <= x"DF";
when x"D83" => DATA <= x"84";
when x"D84" => DATA <= x"DE";
when x"D85" => DATA <= x"F0";
when x"D86" => DATA <= x"BB";
when x"D87" => DATA <= x"20";
when x"D88" => DATA <= x"3A";
when x"D89" => DATA <= x"FE";
when x"D8A" => DATA <= x"4C";
when x"D8B" => DATA <= x"42";
when x"D8C" => DATA <= x"FD";
when x"D8D" => DATA <= x"18";
when x"D8E" => DATA <= x"A9";
when x"D8F" => DATA <= x"10";
when x"D90" => DATA <= x"85";
when x"D91" => DATA <= x"E6";
when x"D92" => DATA <= x"A2";
when x"D93" => DATA <= x"08";
when x"D94" => DATA <= x"20";
when x"D95" => DATA <= x"13";
when x"D96" => DATA <= x"FD";
when x"D97" => DATA <= x"4C";
when x"D98" => DATA <= x"44";
when x"D99" => DATA <= x"FD";
when x"D9A" => DATA <= x"A5";
when x"D9B" => DATA <= x"E7";
when x"D9C" => DATA <= x"49";
when x"D9D" => DATA <= x"60";
when x"D9E" => DATA <= x"85";
when x"D9F" => DATA <= x"E7";
when x"DA0" => DATA <= x"B0";
when x"DA1" => DATA <= x"09";
when x"DA2" => DATA <= x"29";
when x"DA3" => DATA <= x"05";
when x"DA4" => DATA <= x"2E";
when x"DA5" => DATA <= x"01";
when x"DA6" => DATA <= x"B0";
when x"DA7" => DATA <= x"2A";
when x"DA8" => DATA <= x"20";
when x"DA9" => DATA <= x"EA";
when x"DAA" => DATA <= x"FC";
when x"DAB" => DATA <= x"4C";
when x"DAC" => DATA <= x"9A";
when x"DAD" => DATA <= x"FE";
when x"DAE" => DATA <= x"A4";
when x"DAF" => DATA <= x"E0";
when x"DB0" => DATA <= x"20";
when x"DB1" => DATA <= x"6B";
when x"DB2" => DATA <= x"FE";
when x"DB3" => DATA <= x"B1";
when x"DB4" => DATA <= x"DE";
when x"DB5" => DATA <= x"45";
when x"DB6" => DATA <= x"E1";
when x"DB7" => DATA <= x"30";
when x"DB8" => DATA <= x"02";
when x"DB9" => DATA <= x"49";
when x"DBA" => DATA <= x"60";
when x"DBB" => DATA <= x"E9";
when x"DBC" => DATA <= x"20";
when x"DBD" => DATA <= x"4C";
when x"DBE" => DATA <= x"E9";
when x"DBF" => DATA <= x"FD";
when x"DC0" => DATA <= x"A9";
when x"DC1" => DATA <= x"5F";
when x"DC2" => DATA <= x"49";
when x"DC3" => DATA <= x"20";
when x"DC4" => DATA <= x"D0";
when x"DC5" => DATA <= x"23";
when x"DC6" => DATA <= x"45";
when x"DC7" => DATA <= x"E7";
when x"DC8" => DATA <= x"2C";
when x"DC9" => DATA <= x"01";
when x"DCA" => DATA <= x"B0";
when x"DCB" => DATA <= x"30";
when x"DCC" => DATA <= x"02";
when x"DCD" => DATA <= x"49";
when x"DCE" => DATA <= x"60";
when x"DCF" => DATA <= x"4C";
when x"DD0" => DATA <= x"DF";
when x"DD1" => DATA <= x"FD";
when x"DD2" => DATA <= x"69";
when x"DD3" => DATA <= x"39";
when x"DD4" => DATA <= x"90";
when x"DD5" => DATA <= x"F2";
when x"DD6" => DATA <= x"49";
when x"DD7" => DATA <= x"10";
when x"DD8" => DATA <= x"2C";
when x"DD9" => DATA <= x"01";
when x"DDA" => DATA <= x"B0";
when x"DDB" => DATA <= x"30";
when x"DDC" => DATA <= x"02";
when x"DDD" => DATA <= x"49";
when x"DDE" => DATA <= x"10";
when x"DDF" => DATA <= x"18";
when x"DE0" => DATA <= x"69";
when x"DE1" => DATA <= x"20";
when x"DE2" => DATA <= x"2C";
when x"DE3" => DATA <= x"01";
when x"DE4" => DATA <= x"B0";
when x"DE5" => DATA <= x"70";
when x"DE6" => DATA <= x"02";
when x"DE7" => DATA <= x"29";
when x"DE8" => DATA <= x"1F";
when x"DE9" => DATA <= x"4C";
when x"DEA" => DATA <= x"60";
when x"DEB" => DATA <= x"FE";
when x"DEC" => DATA <= x"A5";
when x"DED" => DATA <= x"DE";
when x"DEE" => DATA <= x"A4";
when x"DEF" => DATA <= x"DF";
when x"DF0" => DATA <= x"C0";
when x"DF1" => DATA <= x"81";
when x"DF2" => DATA <= x"90";
when x"DF3" => DATA <= x"38";
when x"DF4" => DATA <= x"C9";
when x"DF5" => DATA <= x"E0";
when x"DF6" => DATA <= x"90";
when x"DF7" => DATA <= x"34";
when x"DF8" => DATA <= x"A4";
when x"DF9" => DATA <= x"E6";
when x"DFA" => DATA <= x"30";
when x"DFB" => DATA <= x"0C";
when x"DFC" => DATA <= x"88";
when x"DFD" => DATA <= x"D0";
when x"DFE" => DATA <= x"07";
when x"DFF" => DATA <= x"20";
when x"E00" => DATA <= x"71";
when x"E01" => DATA <= x"FE";
when x"E02" => DATA <= x"B0";
when x"E03" => DATA <= x"FB";
when x"E04" => DATA <= x"A0";
when x"E05" => DATA <= x"10";
when x"E06" => DATA <= x"84";
when x"E07" => DATA <= x"E6";
when x"E08" => DATA <= x"A0";
when x"E09" => DATA <= x"20";
when x"E0A" => DATA <= x"20";
when x"E0B" => DATA <= x"66";
when x"E0C" => DATA <= x"FE";
when x"E0D" => DATA <= x"B9";
when x"E0E" => DATA <= x"00";
when x"E0F" => DATA <= x"80";
when x"E10" => DATA <= x"99";
when x"E11" => DATA <= x"E0";
when x"E12" => DATA <= x"7F";
when x"E13" => DATA <= x"C8";
when x"E14" => DATA <= x"D0";
when x"E15" => DATA <= x"F7";
when x"E16" => DATA <= x"20";
when x"E17" => DATA <= x"6B";
when x"E18" => DATA <= x"FE";
when x"E19" => DATA <= x"B9";
when x"E1A" => DATA <= x"00";
when x"E1B" => DATA <= x"81";
when x"E1C" => DATA <= x"99";
when x"E1D" => DATA <= x"E0";
when x"E1E" => DATA <= x"80";
when x"E1F" => DATA <= x"C8";
when x"E20" => DATA <= x"D0";
when x"E21" => DATA <= x"F7";
when x"E22" => DATA <= x"A0";
when x"E23" => DATA <= x"1F";
when x"E24" => DATA <= x"A9";
when x"E25" => DATA <= x"20";
when x"E26" => DATA <= x"91";
when x"E27" => DATA <= x"DE";
when x"E28" => DATA <= x"88";
when x"E29" => DATA <= x"10";
when x"E2A" => DATA <= x"FB";
when x"E2B" => DATA <= x"60";
when x"E2C" => DATA <= x"69";
when x"E2D" => DATA <= x"20";
when x"E2E" => DATA <= x"85";
when x"E2F" => DATA <= x"DE";
when x"E30" => DATA <= x"D0";
when x"E31" => DATA <= x"02";
when x"E32" => DATA <= x"E6";
when x"E33" => DATA <= x"DF";
when x"E34" => DATA <= x"60";
when x"E35" => DATA <= x"88";
when x"E36" => DATA <= x"10";
when x"E37" => DATA <= x"19";
when x"E38" => DATA <= x"A0";
when x"E39" => DATA <= x"1F";
when x"E3A" => DATA <= x"A5";
when x"E3B" => DATA <= x"DE";
when x"E3C" => DATA <= x"D0";
when x"E3D" => DATA <= x"0B";
when x"E3E" => DATA <= x"A6";
when x"E3F" => DATA <= x"DF";
when x"E40" => DATA <= x"E0";
when x"E41" => DATA <= x"80";
when x"E42" => DATA <= x"D0";
when x"E43" => DATA <= x"05";
when x"E44" => DATA <= x"68";
when x"E45" => DATA <= x"68";
when x"E46" => DATA <= x"4C";
when x"E47" => DATA <= x"65";
when x"E48" => DATA <= x"FD";
when x"E49" => DATA <= x"E9";
when x"E4A" => DATA <= x"20";
when x"E4B" => DATA <= x"85";
when x"E4C" => DATA <= x"DE";
when x"E4D" => DATA <= x"B0";
when x"E4E" => DATA <= x"02";
when x"E4F" => DATA <= x"C6";
when x"E50" => DATA <= x"DF";
when x"E51" => DATA <= x"60";
when x"E52" => DATA <= x"20";
when x"E53" => DATA <= x"FB";
when x"E54" => DATA <= x"FE";
when x"E55" => DATA <= x"08";
when x"E56" => DATA <= x"48";
when x"E57" => DATA <= x"D8";
when x"E58" => DATA <= x"84";
when x"E59" => DATA <= x"E5";
when x"E5A" => DATA <= x"86";
when x"E5B" => DATA <= x"E4";
when x"E5C" => DATA <= x"20";
when x"E5D" => DATA <= x"EA";
when x"E5E" => DATA <= x"FC";
when x"E5F" => DATA <= x"68";
when x"E60" => DATA <= x"A6";
when x"E61" => DATA <= x"E4";
when x"E62" => DATA <= x"A4";
when x"E63" => DATA <= x"E5";
when x"E64" => DATA <= x"28";
when x"E65" => DATA <= x"60";
when x"E66" => DATA <= x"2C";
when x"E67" => DATA <= x"02";
when x"E68" => DATA <= x"B0";
when x"E69" => DATA <= x"10";
when x"E6A" => DATA <= x"FB";
when x"E6B" => DATA <= x"2C";
when x"E6C" => DATA <= x"02";
when x"E6D" => DATA <= x"B0";
when x"E6E" => DATA <= x"30";
when x"E6F" => DATA <= x"FB";
when x"E70" => DATA <= x"60";
when x"E71" => DATA <= x"A0";
when x"E72" => DATA <= x"3B";
when x"E73" => DATA <= x"18";
when x"E74" => DATA <= x"A9";
when x"E75" => DATA <= x"20";
when x"E76" => DATA <= x"A2";
when x"E77" => DATA <= x"0A";
when x"E78" => DATA <= x"2C";
when x"E79" => DATA <= x"01";
when x"E7A" => DATA <= x"B0";
when x"E7B" => DATA <= x"F0";
when x"E7C" => DATA <= x"08";
when x"E7D" => DATA <= x"EE";
when x"E7E" => DATA <= x"00";
when x"E7F" => DATA <= x"B0";
when x"E80" => DATA <= x"88";
when x"E81" => DATA <= x"CA";
when x"E82" => DATA <= x"D0";
when x"E83" => DATA <= x"F4";
when x"E84" => DATA <= x"4A";
when x"E85" => DATA <= x"08";
when x"E86" => DATA <= x"48";
when x"E87" => DATA <= x"AD";
when x"E88" => DATA <= x"00";
when x"E89" => DATA <= x"B0";
when x"E8A" => DATA <= x"29";
when x"E8B" => DATA <= x"F0";
when x"E8C" => DATA <= x"8D";
when x"E8D" => DATA <= x"00";
when x"E8E" => DATA <= x"B0";
when x"E8F" => DATA <= x"68";
when x"E90" => DATA <= x"28";
when x"E91" => DATA <= x"D0";
when x"E92" => DATA <= x"E3";
when x"E93" => DATA <= x"60";
when x"E94" => DATA <= x"08";
when x"E95" => DATA <= x"D8";
when x"E96" => DATA <= x"86";
when x"E97" => DATA <= x"E4";
when x"E98" => DATA <= x"84";
when x"E99" => DATA <= x"E5";
when x"E9A" => DATA <= x"2C";
when x"E9B" => DATA <= x"02";
when x"E9C" => DATA <= x"B0";
when x"E9D" => DATA <= x"50";
when x"E9E" => DATA <= x"05";
when x"E9F" => DATA <= x"20";
when x"EA0" => DATA <= x"71";
when x"EA1" => DATA <= x"FE";
when x"EA2" => DATA <= x"90";
when x"EA3" => DATA <= x"F6";
when x"EA4" => DATA <= x"20";
when x"EA5" => DATA <= x"8A";
when x"EA6" => DATA <= x"FB";
when x"EA7" => DATA <= x"20";
when x"EA8" => DATA <= x"71";
when x"EA9" => DATA <= x"FE";
when x"EAA" => DATA <= x"B0";
when x"EAB" => DATA <= x"FB";
when x"EAC" => DATA <= x"20";
when x"EAD" => DATA <= x"71";
when x"EAE" => DATA <= x"FE";
when x"EAF" => DATA <= x"B0";
when x"EB0" => DATA <= x"F6";
when x"EB1" => DATA <= x"98";
when x"EB2" => DATA <= x"A2";
when x"EB3" => DATA <= x"17";
when x"EB4" => DATA <= x"20";
when x"EB5" => DATA <= x"C5";
when x"EB6" => DATA <= x"FE";
when x"EB7" => DATA <= x"BD";
when x"EB8" => DATA <= x"E3";
when x"EB9" => DATA <= x"FE";
when x"EBA" => DATA <= x"85";
when x"EBB" => DATA <= x"E2";
when x"EBC" => DATA <= x"A9";
when x"EBD" => DATA <= x"FD";
when x"EBE" => DATA <= x"85";
when x"EBF" => DATA <= x"E3";
when x"EC0" => DATA <= x"98";
when x"EC1" => DATA <= x"6C";
when x"EC2" => DATA <= x"E2";
when x"EC3" => DATA <= x"00";
when x"EC4" => DATA <= x"CA";
when x"EC5" => DATA <= x"DD";
when x"EC6" => DATA <= x"CB";
when x"EC7" => DATA <= x"FE";
when x"EC8" => DATA <= x"90";
when x"EC9" => DATA <= x"FA";
when x"ECA" => DATA <= x"60";
when x"ECB" => DATA <= x"00";
when x"ECC" => DATA <= x"08";
when x"ECD" => DATA <= x"09";
when x"ECE" => DATA <= x"0A";
when x"ECF" => DATA <= x"0B";
when x"ED0" => DATA <= x"0C";
when x"ED1" => DATA <= x"0D";
when x"ED2" => DATA <= x"0E";
when x"ED3" => DATA <= x"0F";
when x"ED4" => DATA <= x"1E";
when x"ED5" => DATA <= x"7F";
when x"ED6" => DATA <= x"00";
when x"ED7" => DATA <= x"01";
when x"ED8" => DATA <= x"05";
when x"ED9" => DATA <= x"06";
when x"EDA" => DATA <= x"08";
when x"EDB" => DATA <= x"0E";
when x"EDC" => DATA <= x"0F";
when x"EDD" => DATA <= x"10";
when x"EDE" => DATA <= x"11";
when x"EDF" => DATA <= x"1C";
when x"EE0" => DATA <= x"20";
when x"EE1" => DATA <= x"21";
when x"EE2" => DATA <= x"3B";
when x"EE3" => DATA <= x"44";
when x"EE4" => DATA <= x"5C";
when x"EE5" => DATA <= x"38";
when x"EE6" => DATA <= x"62";
when x"EE7" => DATA <= x"87";
when x"EE8" => DATA <= x"69";
when x"EE9" => DATA <= x"40";
when x"EEA" => DATA <= x"8D";
when x"EEB" => DATA <= x"92";
when x"EEC" => DATA <= x"7D";
when x"EED" => DATA <= x"50";
when x"EEE" => DATA <= x"DF";
when x"EEF" => DATA <= x"D2";
when x"EF0" => DATA <= x"9A";
when x"EF1" => DATA <= x"A2";
when x"EF2" => DATA <= x"E2";
when x"EF3" => DATA <= x"AE";
when x"EF4" => DATA <= x"C0";
when x"EF5" => DATA <= x"DF";
when x"EF6" => DATA <= x"D8";
when x"EF7" => DATA <= x"D6";
when x"EF8" => DATA <= x"C8";
when x"EF9" => DATA <= x"C6";
when x"EFA" => DATA <= x"C2";
when x"EFB" => DATA <= x"48";
when x"EFC" => DATA <= x"C9";
when x"EFD" => DATA <= x"02";
when x"EFE" => DATA <= x"F0";
when x"EFF" => DATA <= x"27";
when x"F00" => DATA <= x"C9";
when x"F01" => DATA <= x"03";
when x"F02" => DATA <= x"F0";
when x"F03" => DATA <= x"34";
when x"F04" => DATA <= x"C5";
when x"F05" => DATA <= x"FE";
when x"F06" => DATA <= x"F0";
when x"F07" => DATA <= x"2E";
when x"F08" => DATA <= x"AD";
when x"F09" => DATA <= x"0C";
when x"F0A" => DATA <= x"B8";
when x"F0B" => DATA <= x"29";
when x"F0C" => DATA <= x"0E";
when x"F0D" => DATA <= x"F0";
when x"F0E" => DATA <= x"27";
when x"F0F" => DATA <= x"68";
when x"F10" => DATA <= x"2C";
when x"F11" => DATA <= x"01";
when x"F12" => DATA <= x"B8";
when x"F13" => DATA <= x"30";
when x"F14" => DATA <= x"FB";
when x"F15" => DATA <= x"8D";
when x"F16" => DATA <= x"01";
when x"F17" => DATA <= x"B8";
when x"F18" => DATA <= x"48";
when x"F19" => DATA <= x"AD";
when x"F1A" => DATA <= x"0C";
when x"F1B" => DATA <= x"B8";
when x"F1C" => DATA <= x"29";
when x"F1D" => DATA <= x"F0";
when x"F1E" => DATA <= x"09";
when x"F1F" => DATA <= x"0C";
when x"F20" => DATA <= x"8D";
when x"F21" => DATA <= x"0C";
when x"F22" => DATA <= x"B8";
when x"F23" => DATA <= x"09";
when x"F24" => DATA <= x"02";
when x"F25" => DATA <= x"D0";
when x"F26" => DATA <= x"0C";
when x"F27" => DATA <= x"A9";
when x"F28" => DATA <= x"7F";
when x"F29" => DATA <= x"8D";
when x"F2A" => DATA <= x"03";
when x"F2B" => DATA <= x"B8";
when x"F2C" => DATA <= x"AD";
when x"F2D" => DATA <= x"0C";
when x"F2E" => DATA <= x"B8";
when x"F2F" => DATA <= x"29";
when x"F30" => DATA <= x"F0";
when x"F31" => DATA <= x"09";
when x"F32" => DATA <= x"0E";
when x"F33" => DATA <= x"8D";
when x"F34" => DATA <= x"0C";
when x"F35" => DATA <= x"B8";
when x"F36" => DATA <= x"68";
when x"F37" => DATA <= x"60";
when x"F38" => DATA <= x"AD";
when x"F39" => DATA <= x"0C";
when x"F3A" => DATA <= x"B8";
when x"F3B" => DATA <= x"29";
when x"F3C" => DATA <= x"F0";
when x"F3D" => DATA <= x"B0";
when x"F3E" => DATA <= x"F4";
when x"F3F" => DATA <= x"A2";
when x"F40" => DATA <= x"17";
when x"F41" => DATA <= x"BD";
when x"F42" => DATA <= x"9A";
when x"F43" => DATA <= x"FF";
when x"F44" => DATA <= x"9D";
when x"F45" => DATA <= x"04";
when x"F46" => DATA <= x"02";
when x"F47" => DATA <= x"CA";
when x"F48" => DATA <= x"10";
when x"F49" => DATA <= x"F7";
when x"F4A" => DATA <= x"9A";
when x"F4B" => DATA <= x"8A";
when x"F4C" => DATA <= x"E8";
when x"F4D" => DATA <= x"86";
when x"F4E" => DATA <= x"EA";
when x"F4F" => DATA <= x"86";
when x"F50" => DATA <= x"E1";
when x"F51" => DATA <= x"86";
when x"F52" => DATA <= x"E7";
when x"F53" => DATA <= x"A2";
when x"F54" => DATA <= x"33";
when x"F55" => DATA <= x"9D";
when x"F56" => DATA <= x"EB";
when x"F57" => DATA <= x"02";
when x"F58" => DATA <= x"CA";
when x"F59" => DATA <= x"10";
when x"F5A" => DATA <= x"FA";
when x"F5B" => DATA <= x"A9";
when x"F5C" => DATA <= x"0A";
when x"F5D" => DATA <= x"85";
when x"F5E" => DATA <= x"FE";
when x"F5F" => DATA <= x"A9";
when x"F60" => DATA <= x"8A";
when x"F61" => DATA <= x"8D";
when x"F62" => DATA <= x"03";
when x"F63" => DATA <= x"B0";
when x"F64" => DATA <= x"A9";
when x"F65" => DATA <= x"07";
when x"F66" => DATA <= x"8D";
when x"F67" => DATA <= x"02";
when x"F68" => DATA <= x"B0";
when x"F69" => DATA <= x"2C";
when x"F6A" => DATA <= x"01";
when x"F6B" => DATA <= x"B0";
when x"F6C" => DATA <= x"50";
when x"F6D" => DATA <= x"11";
when x"F6E" => DATA <= x"AD";
when x"F6F" => DATA <= x"FE";
when x"F70" => DATA <= x"BF";
when x"F71" => DATA <= x"29";
when x"F72" => DATA <= x"10";
when x"F73" => DATA <= x"F0";
when x"F74" => DATA <= x"0A";
when x"F75" => DATA <= x"A9";
when x"F76" => DATA <= x"83";
when x"F77" => DATA <= x"8D";
when x"F78" => DATA <= x"FE";
when x"F79" => DATA <= x"BF";
when x"F7A" => DATA <= x"6C";
when x"F7B" => DATA <= x"FE";
when x"F7C" => DATA <= x"7F";
when x"F7D" => DATA <= x"EA";
when x"F7E" => DATA <= x"EA";
when x"F7F" => DATA <= x"20";
when x"F80" => DATA <= x"D1";
when x"F81" => DATA <= x"F7";
when x"F82" => DATA <= x"06";
when x"F83" => DATA <= x"0C";
when x"F84" => DATA <= x"0F";
when x"F85" => DATA <= x"41";
when x"F86" => DATA <= x"43";
when x"F87" => DATA <= x"4F";
when x"F88" => DATA <= x"52";
when x"F89" => DATA <= x"4E";
when x"F8A" => DATA <= x"20";
when x"F8B" => DATA <= x"41";
when x"F8C" => DATA <= x"54";
when x"F8D" => DATA <= x"4F";
when x"F8E" => DATA <= x"4D";
when x"F8F" => DATA <= x"0A";
when x"F90" => DATA <= x"0A";
when x"F91" => DATA <= x"0D";
when x"F92" => DATA <= x"EA";
when x"F93" => DATA <= x"58";
when x"F94" => DATA <= x"4C";
when x"F95" => DATA <= x"00";
when x"F96" => DATA <= x"E0";
when x"F97" => DATA <= x"EA";
when x"F98" => DATA <= x"EA";
when x"F99" => DATA <= x"EA";
when x"F9A" => DATA <= x"00";
when x"F9B" => DATA <= x"A0";
when x"F9C" => DATA <= x"EF";
when x"F9D" => DATA <= x"F8";
when x"F9E" => DATA <= x"52";
when x"F9F" => DATA <= x"FE";
when x"FA0" => DATA <= x"94";
when x"FA1" => DATA <= x"FE";
when x"FA2" => DATA <= x"6E";
when x"FA3" => DATA <= x"F9";
when x"FA4" => DATA <= x"E5";
when x"FA5" => DATA <= x"FA";
when x"FA6" => DATA <= x"AC";
when x"FA7" => DATA <= x"C2";
when x"FA8" => DATA <= x"AC";
when x"FA9" => DATA <= x"C2";
when x"FAA" => DATA <= x"EE";
when x"FAB" => DATA <= x"FB";
when x"FAC" => DATA <= x"7C";
when x"FAD" => DATA <= x"FC";
when x"FAE" => DATA <= x"38";
when x"FAF" => DATA <= x"FC";
when x"FB0" => DATA <= x"78";
when x"FB1" => DATA <= x"C2";
when x"FB2" => DATA <= x"85";
when x"FB3" => DATA <= x"FF";
when x"FB4" => DATA <= x"68";
when x"FB5" => DATA <= x"48";
when x"FB6" => DATA <= x"29";
when x"FB7" => DATA <= x"10";
when x"FB8" => DATA <= x"D0";
when x"FB9" => DATA <= x"06";
when x"FBA" => DATA <= x"A5";
when x"FBB" => DATA <= x"FF";
when x"FBC" => DATA <= x"48";
when x"FBD" => DATA <= x"6C";
when x"FBE" => DATA <= x"04";
when x"FBF" => DATA <= x"02";
when x"FC0" => DATA <= x"A5";
when x"FC1" => DATA <= x"FF";
when x"FC2" => DATA <= x"28";
when x"FC3" => DATA <= x"08";
when x"FC4" => DATA <= x"6C";
when x"FC5" => DATA <= x"02";
when x"FC6" => DATA <= x"02";
when x"FC7" => DATA <= x"48";
when x"FC8" => DATA <= x"6C";
when x"FC9" => DATA <= x"00";
when x"FCA" => DATA <= x"02";
when x"FCB" => DATA <= x"6C";
when x"FCC" => DATA <= x"1A";
when x"FCD" => DATA <= x"02";
when x"FCE" => DATA <= x"6C";
when x"FCF" => DATA <= x"18";
when x"FD0" => DATA <= x"02";
when x"FD1" => DATA <= x"6C";
when x"FD2" => DATA <= x"16";
when x"FD3" => DATA <= x"02";
when x"FD4" => DATA <= x"6C";
when x"FD5" => DATA <= x"14";
when x"FD6" => DATA <= x"02";
when x"FD7" => DATA <= x"6C";
when x"FD8" => DATA <= x"12";
when x"FD9" => DATA <= x"02";
when x"FDA" => DATA <= x"6C";
when x"FDB" => DATA <= x"10";
when x"FDC" => DATA <= x"02";
when x"FDD" => DATA <= x"6C";
when x"FDE" => DATA <= x"0E";
when x"FDF" => DATA <= x"02";
when x"FE0" => DATA <= x"6C";
when x"FE1" => DATA <= x"0C";
when x"FE2" => DATA <= x"02";
when x"FE3" => DATA <= x"6C";
when x"FE4" => DATA <= x"0A";
when x"FE5" => DATA <= x"02";
when x"FE6" => DATA <= x"20";
when x"FE7" => DATA <= x"E3";
when x"FE8" => DATA <= x"FF";
when x"FE9" => DATA <= x"C9";
when x"FEA" => DATA <= x"0D";
when x"FEB" => DATA <= x"D0";
when x"FEC" => DATA <= x"07";
when x"FED" => DATA <= x"A9";
when x"FEE" => DATA <= x"0A";
when x"FEF" => DATA <= x"20";
when x"FF0" => DATA <= x"F4";
when x"FF1" => DATA <= x"FF";
when x"FF2" => DATA <= x"A9";
when x"FF3" => DATA <= x"0D";
when x"FF4" => DATA <= x"6C";
when x"FF5" => DATA <= x"08";
when x"FF6" => DATA <= x"02";
when x"FF7" => DATA <= x"6C";
when x"FF8" => DATA <= x"06";
when x"FF9" => DATA <= x"02";
when x"FFA" => DATA <= x"C7";
when x"FFB" => DATA <= x"FF";
when x"FFC" => DATA <= x"3F";
when x"FFD" => DATA <= x"FF";
when x"FFE" => DATA <= x"B2";
when x"FFF" => DATA <= x"FF";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/T6502/T65_ALU.vhd
|
1
|
9755
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_ALU.vhd 2653 2018-06-05 18:14:10Z gary.mups $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in T_ALU_OP;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
signal SBX_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
variable CT : std_logic;
begin
CT:='0';
if( Op=ALU_OP_AND or --"0001" These OpCodes used to have LSB set
Op=ALU_OP_ADC or --"0011"
Op=ALU_OP_EQ2 or --"0101"
Op=ALU_OP_SBC or --"0111"
Op=ALU_OP_ROL or --"1001"
Op=ALU_OP_ROR or --"1011"
-- Op=ALU_OP_EQ3 or --"1101"
Op=ALU_OP_INC --"1111"
) then
CT:='1';
end if;
C := P_In(Flag_C) or not CT;--was: or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
variable Q2_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
Q2_t := BusA;
case Op is
when ALU_OP_OR=>
Q_t := BusA or BusB;
when ALU_OP_AND=>
Q_t := BusA and BusB;
when ALU_OP_EOR=>
Q_t := BusA xor BusB;
when ALU_OP_ADC=>
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when ALU_OP_CMP=>
P_Out(Flag_C) <= SBC_C;
when ALU_OP_SAX=>
P_Out(Flag_C) <= SBC_C;
Q_t := SBX_Q; -- undoc: subtract (A & X) - (immediate)
when ALU_OP_SBC=>
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q; -- undoc: subtract (A & X) - (immediate), then decimal correction
when ALU_OP_ASL=>
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when ALU_OP_ROL=>
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when ALU_OP_LSR=>
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_ROR=>
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when ALU_OP_ARR=>
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
Q2_t := Q_t;
if P_In(Flag_D)='1' then
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
end if;
if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then
Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6");
P_Out(Flag_C) <= '1';
else
P_Out(Flag_C) <= '0';
end if;
else
P_Out(Flag_C) <= Q_t(6);
end if;
when ALU_OP_BIT=>
P_Out(Flag_V) <= BusB(6);
when ALU_OP_DEC=>
Q_t := std_logic_vector(unsigned(BusA) - 1);
when ALU_OP_INC=>
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
null;
--EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out
end case;
case Op is
when ALU_OP_ADC=>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when ALU_OP_EQ1=>--dont touch P
when ALU_OP_BIT=>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when ALU_OP_ANC=>
P_Out(Flag_N) <= Q_t(7);
P_Out(Flag_C) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
if Op=ALU_OP_ARR then
-- handled above in ARR code
Q <= Q2_t;
else
Q <= Q_t;
end if;
end process;
end;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/ROM/InternalROM.vhd
|
1
|
2892
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity InternalROM is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(16 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture BEHAVIORAL of InternalROM is
component e000 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
component atombasic
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
component atomfloat
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
component atomkernal
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
signal basic_rom_enable : std_logic;
signal kernal_rom_enable : std_logic;
signal float_rom_enable : std_logic;
signal sddos_rom_enable : std_logic;
signal kernal_data : std_logic_vector(7 downto 0);
signal basic_data : std_logic_vector(7 downto 0);
signal float_data : std_logic_vector(7 downto 0);
signal sddos_data : std_logic_vector(7 downto 0);
begin
romc000 : atombasic port map(
CLK => CLK,
ADDR => ADDR(11 downto 0),
DATA => basic_data);
romd000 : atomfloat port map(
CLK => CLK,
ADDR => ADDR(11 downto 0),
DATA => float_data);
rome000 : e000 port map(
CLK => CLK,
ADDR => ADDR(11 downto 0),
DATA => sddos_data);
romf000 : atomkernal port map(
CLK => CLK,
ADDR => ADDR(11 downto 0),
DATA => kernal_data);
process(ADDR)
begin
-- All regions normally de-selected
sddos_rom_enable <= '0';
basic_rom_enable <= '0';
kernal_rom_enable <= '0';
float_rom_enable <= '0';
case ADDR(15 downto 12) is
when x"C" => basic_rom_enable <= '1';
when x"D" => float_rom_enable <= '1';
when x"E" => sddos_rom_enable <= '1';
when x"F" => kernal_rom_enable <= '1';
when others => null;
end case;
end process;
DATA <=
basic_data when basic_rom_enable = '1' else
float_data when float_rom_enable = '1' else
sddos_data when sddos_rom_enable = '1' else
kernal_data when kernal_rom_enable = '1' else
x"f1"; -- un-decoded locations
end BEHAVIORAL;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/AVR8/resync/rsnc_vect.vhd
|
4
|
2053
|
--**********************************************************************************************
-- Resynchronizer (for n-bit vector)
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_vect is generic(
width : integer := 8;
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end rsnc_vect;
architecture rtl of rsnc_vect is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0);
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
inverted_first_stg:if (inv_f_stgs/=0) generate
seq_f_fe_prc:process(clk)
begin
if(clk='0' and clk'event) then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
norm_first_stg:if (inv_f_stgs=0) generate
seq_f_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;
|
apache-2.0
|
msiddalingaiah/TTA
|
VHDL/ControlUnit.vhd
|
1
|
7311
|
--------------------------------------------------------------------------------
-- Copyright 2014 Madhu Siddalingaiah
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Entity: ControlUnit
-- Date: 2014-10-31
-- Author: Madhu
--
-- Description:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Avoid using ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ControlUnit is
generic (
DATA_WIDTH : integer := 16;
PM_DEPTH : natural := 16
);
port (
reset : in std_logic;
clock : in std_logic;
load_enable : in std_logic;
run_enable : in std_logic;
pm_data_in : in std_logic_vector ( 16 - 1 downto 0 );
halt_flag : out std_logic
);
end ControlUnit;
-- f ddddddd ssssssss
-- 1 module module
-- 0 module immediate
-- module 0 - prefix
architecture arch of ControlUnit is
component ProgramMemory
generic (
DATA_WIDTH : integer;
ADDRESS_WIDTH : integer;
DEPTH : natural
);
port (
reset : in std_logic;
clock : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
pc_in : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
pc_out : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
memory_write : in std_logic;
pc_write : in std_logic
);
end component;
component ArithmeticUnit
generic (
DATA_WIDTH : integer;
ADDRESS_WIDTH : integer;
DEPTH : natural
);
port (
reset : in std_logic;
clock : in std_logic;
address : in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 );
data_in : in std_logic_vector ( DATA_WIDTH - 1 downto 0 );
data_out : out std_logic_vector ( DATA_WIDTH - 1 downto 0 );
read_enable : in std_logic;
write_enable : in std_logic;
busy : out std_logic
);
end component;
constant SUBSYSTEM_WIDTH : integer := 3;
constant DEST_BASE : integer := 8;
constant UNIT_WIDTH : integer := 4;
constant IMM_BIT : integer := DEST_BASE+3;
constant SHORT_IMM_BIT : integer := DEST_BASE-1;
constant SHORT_IMM_WIDTH : integer := SHORT_IMM_BIT-1;
constant UNIT_PM : integer := 1;
constant UNIT_ARITH : integer := 2;
constant NUM_UNITS : integer := 16;
type DataBusArray is array (NUM_UNITS-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
type AddrBusArray is array (NUM_UNITS-1 downto 0) of std_logic_vector(SUBSYSTEM_WIDTH-1 downto 0);
signal data_in, data_out : DataBusArray;
signal address : AddrBusArray;
signal read_enable, write_enable, busy : std_logic_vector(0 to NUM_UNITS-1);
signal instruction, code_data_out : std_logic_vector(DATA_WIDTH-1 downto 0);
signal l_reset, l_clock, code_read_enable : std_logic;
begin
au : ArithmeticUnit
generic map(
DATA_WIDTH => DATA_WIDTH,
ADDRESS_WIDTH => SUBSYSTEM_WIDTH,
DEPTH => 32
)
port map(
reset => l_reset,
clock => l_clock,
address => address(UNIT_ARITH),
data_in => data_in(UNIT_ARITH),
data_out => data_out(UNIT_ARITH),
read_enable => read_enable(UNIT_ARITH),
write_enable => write_enable(UNIT_ARITH),
busy => busy(UNIT_ARITH)
);
statemachine: block
type state_type is (LOAD, PREFETCH, EXEC, HALT);
signal state : state_type := LOAD;
signal dest_sub_system, src_sub_system : std_logic_vector( SUBSYSTEM_WIDTH - 1 downto 0 );
signal short_immediate : std_logic_vector( SHORT_IMM_WIDTH - 1 downto 0 );
signal imm_flag, long_imm_flag : std_logic;
begin
l_reset <= reset;
l_clock <= clock;
imm_flag <= instruction(IMM_BIT);
long_imm_flag <= instruction(SHORT_IMM_BIT);
short_immediate <= instruction(SHORT_IMM_WIDTH - 1 downto 0);
dest_sub_system <= instruction(IMM_BIT - 1 downto DEST_BASE);
src_sub_system <= instruction(SUBSYSTEM_WIDTH - 1 downto 0);
process(clock, reset)
variable dest_unit, src_unit : integer;
begin
if reset = '1' then
state <= LOAD;
halt_flag <= '0';
code_read_enable <= '0';
read_enable <= (others => '0');
write_enable <= (others => '0');
elsif rising_edge(clock) then
read_enable <= (others => '0');
write_enable <= (others => '0');
case state is
when LOAD =>
if load_enable = '0' and run_enable = '1' then
state <= PREFETCH;
elsif load_enable = '1' then
address(UNIT_PM) <= std_logic_vector(to_unsigned(1, address(UNIT_PM)'length));
data_in(UNIT_PM) <= pm_data_in;
write_enable(UNIT_PM) <= '1';
end if;
when PREFETCH =>
state <= EXEC;
code_read_enable <= '1';
when EXEC =>
if to_integer(unsigned(instruction(DATA_WIDTH - 1 downto 0))) = 1 then
state <= HALT;
else
state <= EXEC;
src_unit := to_integer(unsigned(instruction(DEST_BASE - 1 downto UNIT_WIDTH)));
dest_unit := to_integer(unsigned(instruction(DATA_WIDTH - 1 downto IMM_BIT+1)));
address(dest_unit) <= dest_sub_system;
if imm_flag = '1' then
if long_imm_flag = '0' then
data_in(dest_unit) <= std_logic_vector(resize(signed(short_immediate), data_in(dest_unit)'length));
else
address(UNIT_PM) <= std_logic_vector(to_unsigned(1, address(UNIT_PM)'length));
read_enable(UNIT_PM) <= '1';
data_in(dest_unit) <= data_out(UNIT_PM);
end if;
else
address(src_unit) <= src_sub_system;
read_enable(src_unit) <= '1';
data_in(dest_unit) <= data_out(src_unit);
end if;
write_enable(dest_unit) <= '1';
end if;
when HALT =>
halt_flag <= '1';
when others =>
state <= HALT;
end case;
end if;
end process;
end block;
end arch;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/AVR8/Peripheral/portx.vhd
|
4
|
4513
|
--**********************************************************************************************
-- Parallel Port Peripheral for the AVR Core
-- Version 0.7
-- Modified 10.08.2003
-- Designed by Ruslan Lepetenok.
--
-- The possibility of implementing level sensitive LATCH instead of edge sensitive DFF
-- (for the first stage of the synchronizer) is added.
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.SynchronizerCompPack.all; -- Component declarations for the synchronizers
entity pport is generic(PPortNum : natural);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- --Info
-- miso_LOC : in integer;
-- spi_spe : in std_logic;
-- External connection
-- spi_misoi : out std_logic;
portx : out std_logic_vector(7 downto 0);
ddrx : out std_logic_vector(7 downto 0);
pinx : in std_logic_vector(7 downto 0);
irqlines : out std_logic_vector(7 downto 0));
end pport;
architecture RTL of pport is
signal PORTx_Int : std_logic_vector(portx'range);
signal DDRx_Int : std_logic_vector(ddrx'range);
signal PINx_Tmp : std_logic_vector(pinx'range);
signal PINx_Resync : std_logic_vector(pinx'range);
signal PORTx_Sel : std_logic;
signal DDRx_Sel : std_logic;
signal PINx_Sel : std_logic;
begin
PORTx_Sel <= '1' when adr=PPortAdrArray(PPortNum).Port_Adr else '0';
DDRx_Sel <= '1' when adr=PPortAdrArray(PPortNum).DDR_Adr else '0';
PINx_Sel <= '1' when adr=PPortAdrArray(PPortNum).Pin_Adr else '0';
--spi_misoi_Sel <= '1' when adr=PPortAdrArray(PPortNum).Pin_Adr else '0';
out_en <= (PORTx_Sel or DDRx_Sel or PINx_Sel) and iore;
PORTx_DFF:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PORTx_Int <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if PORTx_Sel='1' and iowe='1' then -- Clock enable
PORTx_Int <= dbus_in;
end if;
end if;
end process;
DDRx_DFF:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
DDRx_Int <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if DDRx_Sel='1' and iowe='1' then -- Clock enable
DDRx_Int <= dbus_in;
end if;
end if;
end process;
-- The first stage of the resynchronizer : DFF or Latch
SynchDFF:if not CSynchLatchUsed generate
PINxDFFSynchronizer:for i in pinx'range generate
PINxDFFSynchronizer_Inst:component SynchronizerDFF port map(
NRST => ireset,
CLK => cp2,
D => pinx(i),
Q => PINx_Tmp(i));
end generate;
end generate;
SynchLatch:if CSynchLatchUsed generate
PINxLatchSynchronizer:for i in pinx'range generate
PINxLatchSynchronizer_Inst:component SynchronizerLatch port map(
D => pinx(i),
G => cp2,
Q => PINx_Tmp(i),
QN => open);
end generate;
end generate;
-- End of the first stage of the resynchronizer
PINXInputReg:process(cp2,ireset)
begin
if (ireset='0') then -- Reset
PINx_Resync <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
PINx_Resync <= PINx_Tmp;
end if;
end process;
DBusOutMux:for i in pinx'range generate
dbus_out(i) <= (PORTx_Int(i) and PORTx_Sel)or(DDRx_Int(i) and DDRx_Sel)or(PINx_Resync(i) and PINx_Sel);
irqlines(i) <= PINx_Resync(i);
--spi_misoi <= pinx(i) when miso_Loc = i and spi_spe = '1';
end generate;
-- Outputs
portx <= PORTx_Int;
ddrx <= DDRx_Int;
end RTL;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/AVR8/resync/rsnc_comp_pack.vhd
|
4
|
2088
|
--**********************************************************************************************
-- Resynchronizers
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package rsnc_comp_pack is
component rsnc_vect is generic(
width : integer := 8;
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end component;
component rsnc_bit is generic(
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end component;
component rsnc_l_vect is generic(
tech : integer := 0;
width : integer := 8;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end component;
component rsnc_l_bit is generic(
tech : integer := 0;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic;
do : out std_logic
);
end component;
end rsnc_comp_pack;
|
apache-2.0
|
astoria-d/super-duper-nes
|
duper_cartridge/simulation/testbench_duper_cartridge.vhd
|
1
|
17238
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.conv_std_logic_vector;
entity testbench_i2c_test is
end testbench_i2c_test;
architecture stimulus of testbench_i2c_test is
constant powerup_time : time := 200 ns;
constant reset_time : time := 800 ns;
constant start_time : time := 12 us;
--DE1 base clock = 50 MHz
constant base_clock_time : time := 20 ns;
--i2c normal clock speed 100 KHz
constant i2c_clock_time : time := 10 us;
---https://wiki.nesdev.com/w/index.php/Clock_rate
--nes cpu clock = 1.789773 MHz
constant nes_clock_time : time := 558 ns;
constant bus_cycle : integer := 3;
---fifo status register
---bit
---7 always 0
---6 always 0
---5 read fifo full
---4 read fifo empty
---3 always 0
---2 always 0
---1 write fifo full
---0 write fifo empty
constant wfifo_empty_bit : integer := 0;
constant wfifo_full_bit : integer := 1;
constant rfifo_empty_bit : integer := 4;
constant rfifo_full_bit : integer := 5;
constant i2c_read : std_logic := '1';
constant i2c_write : std_logic := '0';
component duper_cartridge
port (
pi_reset_n : in std_logic;
pi_base_clk : in std_logic;
--nes side
pi_phi2 : in std_logic;
pi_prg_ce_n : in std_logic;
pi_prg_r_nw : in std_logic;
pi_prg_addr : in std_logic_vector(14 downto 0);
pio_prg_data : inout std_logic_vector(7 downto 0);
pi_chr_ce_n : in std_logic;
pi_chr_oe_n : in std_logic;
pi_chr_we_n : in std_logic;
pi_chr_addr : in std_logic_vector(12 downto 0);
po_chr_data : out std_logic_vector(7 downto 0);
--i2c side
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
--bbb gpio
po_nes_f_full : out std_logic;
po_bbb_f_empty : out std_logic;
po_dbg_cnt : out std_logic_vector (63 downto 0)
);
end component ;
signal reset_input : std_logic;
signal base_clk : std_logic;
signal phi2 : std_logic;
signal prg_ce_n : std_logic;
signal prg_r_nw : std_logic;
signal prg_addr : std_logic_vector(14 downto 0);
signal prg_data : std_logic_vector(7 downto 0);
signal chr_ce_n : std_logic;
signal chr_oe_n : std_logic;
signal chr_we_n : std_logic;
signal chr_addr : std_logic_vector(12 downto 0);
signal chr_data : std_logic_vector(7 downto 0);
signal i2c_scl : std_logic;
signal i2c_sda : std_logic;
signal nes_f_full : std_logic;
signal bbb_f_empty : std_logic;
signal dbg_cnt : std_logic_vector (63 downto 0);
signal reg_rom_data : std_logic_vector(7 downto 0);
signal reg_bbb_data : std_logic_vector (7 downto 0);
signal start_scl : std_logic;
signal step_cnt : integer range 0 to 65535 := 0;
signal stage_cnt : integer range 0 to 65535 := 0;
signal i2c_step_cnt : integer range 0 to 65535 := 0;
begin
---chrrom side disabled..
chr_ce_n <= 'Z';
chr_oe_n <= 'Z';
chr_we_n <= 'Z';
chr_addr <= (others => 'Z');
chr_data <= (others => 'Z');
sim_board : duper_cartridge port map (
reset_input,
base_clk,
phi2,
prg_ce_n,
prg_r_nw,
prg_addr,
prg_data,
chr_ce_n,
chr_oe_n,
chr_we_n,
chr_addr,
chr_data,
i2c_scl,
i2c_sda,
nes_f_full,
bbb_f_empty,
dbg_cnt);
--- input reset.
reset_p: process
begin
reset_input <= '1';
wait for powerup_time;
reset_input <= '0';
wait for reset_time;
reset_input <= '1';
wait;
end process;
--- generate base clock.
clock_p1 : process
begin
base_clk <= '1';
wait for base_clock_time / 2;
base_clk <= '0';
wait for base_clock_time / 2;
end process;
--- nes clock.
clock_p2 : process
begin
phi2 <= '1';
wait for nes_clock_time / 2;
phi2 <= '0';
wait for nes_clock_time / 2;
end process;
--rom save register...
romreg_p : process (phi2)
begin
if (rising_edge(phi2)) then
--bus cycle is 1 cycle delayed.
if (step_cnt mod bus_cycle = 1) then
reg_rom_data <= prg_data;
end if;
end if;
end process;
--- cpu bus emulation...
emu_cpu : process
procedure mem_write
(
addr : in std_logic_vector (14 downto 0);
data : in std_logic_vector (7 downto 0)
) is
begin
prg_ce_n <= '0';
prg_r_nw <= '0';
prg_addr <= addr;
prg_data <= data;
end;
procedure mem_read
(
addr : in std_logic_vector (14 downto 0)
) is
begin
prg_ce_n <= '0';
prg_r_nw <= '1';
prg_addr <= addr;
prg_data <= (others => 'Z');
end;
procedure bus_wait is
begin
prg_ce_n <= '1';
prg_r_nw <= 'Z';
prg_addr <= (others => 'Z');
prg_data <= (others => 'Z');
end;
begin
if (stage_cnt = 0) then
wait for powerup_time + reset_time;
stage_cnt <= stage_cnt + 1;
step_cnt <= 0;
elsif (stage_cnt = 1) then
--pseudo rom read.
if (step_cnt < bus_cycle * 1) then
if (step_cnt mod bus_cycle = 0) then
mem_read (conv_std_logic_vector(16#fffa#, 15));
else
bus_wait;
end if;
step_cnt <= step_cnt + 1;
elsif (step_cnt < bus_cycle * 2) then
if (step_cnt mod bus_cycle = 0) then
mem_read (conv_std_logic_vector(16#fff8#, 15));
else
bus_wait;
end if;
step_cnt <= step_cnt + 1;
else
bus_wait;
step_cnt <= 0;
stage_cnt <= stage_cnt + 1;
end if;
elsif (stage_cnt = 2) then
--polling fifo status.
if (reg_rom_data (rfifo_empty_bit) = '1') then
if (step_cnt mod bus_cycle = 0) then
mem_read (conv_std_logic_vector(16#fff8#, 15));
else
bus_wait;
end if;
step_cnt <= step_cnt + 1;
else
bus_wait;
step_cnt <= 0;
stage_cnt <= stage_cnt + 1;
end if;
elsif (stage_cnt = 3) then
--read fifo..
--wait for test pattern.
if (reg_rom_data /= conv_std_logic_vector(16#5a#, 8)) then
if (step_cnt mod bus_cycle = 0) then
--0xfff9 is fifo read.
mem_read (conv_std_logic_vector(16#fff9#, 15));
else
bus_wait;
end if;
step_cnt <= step_cnt + 1;
else
bus_wait;
step_cnt <= 0;
stage_cnt <= stage_cnt + 1;
end if;
elsif (stage_cnt = 4) then
--push fifo to bbb..
if (step_cnt mod bus_cycle = 0 and step_cnt < 30) then
--0xfff9 is fifo write.
mem_write (conv_std_logic_vector(16#fff9#, 15),conv_std_logic_vector(16#77# + step_cnt, 8));
step_cnt <= step_cnt + 1;
elsif (step_cnt mod bus_cycle = 0 and step_cnt = 30) then
bus_wait;
step_cnt <= 0;
stage_cnt <= stage_cnt + 1;
else
bus_wait;
step_cnt <= step_cnt + 1;
end if;
elsif (stage_cnt = 5) then
--polling fifo status.
if (step_cnt = 0) then
mem_read (conv_std_logic_vector(16#fff8#, 15));
step_cnt <= step_cnt + 1;
else
if (reg_rom_data (wfifo_empty_bit) = '0') then
if (step_cnt mod bus_cycle = 0) then
mem_read (conv_std_logic_vector(16#fff8#, 15));
else
bus_wait;
end if;
step_cnt <= step_cnt + 1;
else
bus_wait;
step_cnt <= 0;
stage_cnt <= stage_cnt + 1;
end if;
end if;
else
bus_wait;
stage_cnt <= stage_cnt + 1;
end if;
wait for nes_clock_time;
end process;
--- i2c_scl process..
scl_p : process
begin
if(start_scl = '1') then
i2c_scl <= '1';
wait for i2c_clock_time / 2;
i2c_scl <= '0';
wait for i2c_clock_time / 2;
else
i2c_scl <= '1';
wait for i2c_clock_time;
end if;
end process;
i2c_cnt_p : process
begin
if (stage_cnt = 2) then
i2c_step_cnt <= i2c_step_cnt + 1;
elsif (stage_cnt = 3) then
if (i2c_step_cnt = 22) then
i2c_step_cnt <= 0;
else
i2c_step_cnt <= i2c_step_cnt + 1;
end if;
elsif (stage_cnt = 5) then
i2c_step_cnt <= i2c_step_cnt + 1;
else
i2c_step_cnt <= 0;
end if;
wait for i2c_clock_time;
end process;
--- i2c_scl process..
i2c_scl_handl_p : process
begin
if (stage_cnt = 0) then
start_scl <= '0';
elsif (stage_cnt = 2) then
start_scl <= '1';
elsif (stage_cnt = 3) then
if (step_cnt < 50) then
start_scl <= '0';
else
start_scl <= '1';
end if;
elsif (stage_cnt = 5) then
if (step_cnt < 50) then
start_scl <= '0';
else
start_scl <= '1';
end if;
else
start_scl <= '0';
end if;
wait for nes_clock_time;
end process;
--- i2c_sda process..
i2c_p : process
variable remaining_time : time;
variable start_index : integer;
procedure wait_clock
(
wait_time : in time
) is
begin
wait for wait_time;
remaining_time := remaining_time - wait_time;
end;
procedure wait_remaining is
begin
wait for remaining_time;
end;
procedure output_addr
(
i : in integer;
addr : in std_logic_vector (6 downto 0)
) is
begin
i2c_sda <= addr(i);
end;
procedure ack_wait is
begin
i2c_sda <= 'Z';
end;
procedure output_data
(
i : in integer;
data : in std_logic_vector (7 downto 0)
) is
begin
i2c_sda <= data(i);
end;
procedure input_data
(
i : in integer
) is
begin
reg_bbb_data(i) <= i2c_sda;
end;
begin
remaining_time := i2c_clock_time;
if (stage_cnt = 2) then
--from bbb to nes i2c write.
if (i2c_step_cnt = 0) then
start_index := 0;
elsif (i2c_step_cnt = 1) then
--start up seq...
wait_clock (i2c_clock_time / 4);
i2c_sda <= '0';
--set i2c addr...
--addr output with write.....
--0x44 = 100 0101.
start_index := i2c_step_cnt;
wait_clock (i2c_clock_time / 2);
output_addr(6 - i2c_step_cnt + start_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt <= 7) then
wait_clock (i2c_clock_time * 3 / 4);
output_addr(6 - i2c_step_cnt + start_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt = 8) then
wait_clock (i2c_clock_time * 3 / 4);
i2c_sda <= i2c_write;
elsif (i2c_step_cnt = 9) then
--wait ack...
wait_clock (i2c_clock_time * 3 / 4);
ack_wait;
--output data
elsif (i2c_step_cnt = 10) then
start_index := i2c_step_cnt;
wait_clock (i2c_clock_time * 3 / 4);
output_data(8 - i2c_step_cnt + start_index, conv_std_logic_vector(16#55#, 8));
elsif (i2c_step_cnt <= 17) then
wait_clock (i2c_clock_time * 3 / 4);
output_data(8 - i2c_step_cnt + start_index, conv_std_logic_vector(16#55#, 8));
elsif (i2c_step_cnt = 18) then
--wait ack...
wait_clock (i2c_clock_time * 3 / 4);
ack_wait;
elsif (i2c_step_cnt = 20) then
--stop seq...
i2c_sda <= '0';
wait_clock (i2c_clock_time / 4);
i2c_sda <= '1';
end if;
elsif (stage_cnt = 3) then
--from bbb to nes i2c write.
if (i2c_step_cnt = 0) then
start_index := 0;
elsif (i2c_step_cnt = 1) then
--start up seq...
wait_clock (i2c_clock_time / 4);
i2c_sda <= '0';
--set i2c addr...
--addr output with write.....
--0x44 = 100 0101.
start_index := i2c_step_cnt;
wait_clock (i2c_clock_time / 2);
output_addr(6 - i2c_step_cnt + start_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt <= 7) then
wait_clock (i2c_clock_time * 3 / 4);
output_addr(6 - i2c_step_cnt + start_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt = 8) then
wait_clock (i2c_clock_time * 3 / 4);
i2c_sda <= i2c_write;
elsif (i2c_step_cnt = 9) then
--wait ack...
wait_clock (i2c_clock_time * 3 / 4);
ack_wait;
--output data
elsif (i2c_step_cnt = 10) then
start_index := i2c_step_cnt;
wait_clock (i2c_clock_time * 3 / 4);
output_data(8 - i2c_step_cnt + start_index, conv_std_logic_vector(16#5a#, 8));
elsif (i2c_step_cnt <= 17) then
wait_clock (i2c_clock_time * 3 / 4);
output_data(8 - i2c_step_cnt + start_index, conv_std_logic_vector(16#5a#, 8));
elsif (i2c_step_cnt = 18) then
--wait ack...
wait_clock (i2c_clock_time * 3 / 4);
ack_wait;
elsif (i2c_step_cnt = 20) then
--stop seq...
i2c_sda <= '0';
wait_clock (i2c_clock_time / 4);
i2c_sda <= '1';
end if;
elsif (stage_cnt = 5) then
--from bbb to nes i2c read.
if (i2c_step_cnt <= 3) then
start_index := i2c_step_cnt;
elsif (i2c_step_cnt = 4) then
--start up seq...
wait_clock (i2c_clock_time / 4);
i2c_sda <= '0';
--set i2c addr...
--addr output with write.....
--0x44 = 100 0101.
start_index := i2c_step_cnt;
wait_clock (i2c_clock_time / 2);
output_addr(6 - i2c_step_cnt + start_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt <= 10) then
wait_clock (i2c_clock_time * 3 / 4);
output_addr(6 - i2c_step_cnt + start_index, conv_std_logic_vector(16#44#, 7));
elsif (i2c_step_cnt = 11) then
wait_clock (i2c_clock_time * 3 / 4);
i2c_sda <= i2c_read;
elsif (i2c_step_cnt = 12) then
--wait ack...
wait_clock (i2c_clock_time * 3 / 4);
start_index := i2c_step_cnt + 1;
ack_wait;
--read data
elsif (i2c_step_cnt >= 14 and i2c_step_cnt <= 21) then
input_data(7 - i2c_step_cnt + start_index);
elsif (i2c_step_cnt = 22) then
--return ack...
wait_clock (i2c_clock_time * 3 / 4);
i2c_sda <= '0';
elsif (i2c_step_cnt = 23) then
--stop seq...
i2c_sda <= '0';
wait_clock (i2c_clock_time / 4);
i2c_sda <= '1';
end if;
else
--pull up.
i2c_sda <= '1';
end if;
wait_remaining;
end process;
end stimulus;
|
apache-2.0
|
astoria-d/super-duper-nes
|
test/voltage_test01/voltage_test01.vhd
|
1
|
1838
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
--
-- MOTO NES FPGA On DE0-CV Environment Virtual Cuicuit Board
-- All of the components are assembled and instanciated on this board.
--
entity voltage_test01 is
port (
pi_base_clk : in std_logic;
pi_sw : in std_logic_vector(9 downto 0);
pi_btn_n : in std_logic_vector(3 downto 0);
po_led_r : out std_logic_vector(9 downto 0);
po_led_g : out std_logic_vector(7 downto 0);
po_gpio0 : out std_logic_vector(3 downto 0);
po_gpio1 : out std_logic_vector(9 downto 0)
);
end voltage_test01;
architecture rtl of voltage_test01 is
--slow down button update timing.
constant FREQ_DEVIDE : integer := 1000000;
signal reg_btn_flg : integer range 0 to FREQ_DEVIDE;
signal reg_key3_cnt : std_logic_vector(7 downto 0);
signal wr_rst_n : std_logic;
begin
wr_rst_n <= pi_btn_n(0);
po_led_g <= reg_key3_cnt;
po_led_r <= pi_sw;
po_gpio0 <= pi_btn_n;
po_gpio1 <= pi_sw;
--key3 button proc.
key3_cnt_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
reg_key3_cnt <= (others => '0');
elsif (rising_edge(pi_base_clk)) then
if (pi_btn_n(3) = '0' and reg_btn_flg = 0) then
reg_key3_cnt <= reg_key3_cnt + 1;
end if;
end if;
end process;
--
led_flg_p : process (wr_rst_n, pi_base_clk)
begin
if (wr_rst_n = '0') then
reg_btn_flg <= 0;
elsif (rising_edge(pi_base_clk)) then
reg_btn_flg <= reg_btn_flg + 1;
end if;
end process;
end rtl;
|
apache-2.0
|
five-elephants/hw-neural-sampling
|
input_sum.vhdl
|
1
|
954
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling.all;
entity input_sum is
generic (
num_samplers : integer := 1
);
port (
clk, reset : in std_ulogic;
phase : in phase_t;
state : in state_array_t(1 to num_samplers);
weights : in weight_array_t(1 to num_samplers);
sum : out signed(sum_in_size(num_samplers)-1 downto 0)
);
end input_sum;
architecture rtl of input_sum is
subtype sum_in_t is
signed(sum_in_size(num_samplers)-1 downto 0);
begin
------------------------------------------------------------
summation: process ( state, weights )
variable acc : sum_in_t;
begin
acc := to_signed(0, acc'length);
for i in 1 to num_samplers loop
if state(i) = '1' then
acc := acc + resize(weights(i), acc'length);
end if;
end loop;
sum <= acc;
end process;
------------------------------------------------------------
end rtl;
|
apache-2.0
|
five-elephants/hw-neural-sampling
|
test_activation.vhdl
|
1
|
4229
|
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
entity test_activation is
end test_activation;
architecture behave of test_activation is
constant clk_period : time := 10 ns;
constant num_samplers : integer := 1;
constant num_rngs_per_sampler : integer := 4;
constant tau : integer := 20;
constant threshold : membrane_t := make_fixed(3.0,
membrane_width-1-membrane_fraction,
membrane_fraction);
constant weights : weight_array2_t(1 to num_samplers, 1 to num_samplers) := (
others => (others => make_fixed(0.0, 2, 1))
);
signal clk, reset : std_ulogic;
signal clock_tick : std_ulogic;
signal systime : systime_t;
signal state_clamp_mask,
state_clamp,
state : state_array_t(1 to num_samplers);
signal membranes : membrane_array_t(1 to num_samplers);
signal fires : std_ulogic_vector(1 to num_samplers);
signal seeds : lfsr_state_array_t(1 to num_samplers*num_rngs_per_sampler);
signal biases : weight_array_t(1 to num_samplers);
begin
clock_generation: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
------------------------------------------------------------
-- unit under test
------------------------------------------------------------
uut: entity work.sampling_network
generic map (
num_samplers => num_samplers,
tau => tau
)
port map (
clk => clk,
reset => reset,
clock_tick => clock_tick,
systime => systime,
state => state,
membranes => membranes,
fires => fires,
seeds => seeds,
biases => biases,
weights => weights
);
------------------------------------------------------------
-- stimulus generation
------------------------------------------------------------
stimulus: process
variable l : line;
variable seed1, seed2 : positive;
variable rand : real;
variable int_rand : integer;
variable test_input : real;
begin
biases <= (others => make_fixed(0.0, 2, 1));
for i in seeds'range loop
uniform(seed1, seed2, rand);
int_rand := integer(rand*(2.0**lfsr_width-1.0));
seeds(i) <= std_logic_vector(to_unsigned(int_rand, seeds(i)'length));
end loop;
write(l, string'("biases:"));
writeline(output, l);
for i in biases'range loop
hwrite(l, std_logic_vector(biases(i)));
writeline(output, l);
end loop;
write(l, string'("weights:"));
writeline(output, l);
for i in 1 to num_samplers loop
for j in 1 to num_samplers loop
hwrite(l, std_logic_vector(weights(i,j)));
write(l, string'(" "));
end loop;
writeline(output, l);
end loop;
write(l, string'("threshold: "));
hwrite(l, std_logic_vector(threshold));
writeline(output, l);
reset <= '1';
wait for 100 ns;
reset <= '0';
wait until rising_edge(clk);
test_input := -4.0;
while test_input <= 3.5 loop
write(l, string'("test_input: "));
write(l, test_input);
biases <= (others => make_fixed(test_input, 2, 1));
write(l, string'(" ("));
hwrite(l, std_logic_vector(make_fixed(test_input, 2, 1)));
write(l, string'(")"));
writeline(output, l);
wait for 100000*clk_period;
test_input := test_input + 0.5;
end loop;
assert(false)
report "no error; simulation end"
severity failure;
end process;
------------------------------------------------------------
recorder: process
file f : text open write_mode is "activation_trace";
variable ln : line;
begin
loop
wait until rising_edge(clock_tick);
for i in state'range loop
write(ln, state(i));
write(ln, string'(" "));
write(ln, fires(i));
write(ln, string'(" "));
hwrite(ln, std_logic_vector(membranes(i)));
write(ln, string'(" "));
--hwrite(ln, std_logic_vector(biases(i)));
--write(ln, string'(" "));
end loop;
writeline(f, ln);
end loop;
end process;
------------------------------------------------------------
end behave;
|
apache-2.0
|
five-elephants/hw-neural-sampling
|
sampling_shell.vhdl
|
1
|
2797
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
use work.net_config.all;
entity sampling_shell is
generic (
num_samplers : integer := 4;
tau : positive := 20;
num_observers : natural := 16
);
port (
clk, reset : in std_ulogic;
observed_joints : in state_array2_t(1 to num_observers, 1 to num_samplers);
joint_counters : out joint_counter_array_t(1 to num_observers);
systime : out systime_t
);
end sampling_shell;
architecture rtl of sampling_shell is
------------------------------------------------------------
--function init_seeds
--return lfsr_state_array_t is
--variable seed1, seed2 : positive;
--variable rand : real;
--variable int_rand : integer;
--variable rv : lfsr_state_array_t(1 to num_samplers);
--begin
--for i in rv'range loop
--uniform(seed1, seed2, rand);
--int_rand := integer(rand*(2.0**lfsr_width-1.0));
--rv(i) := std_logic_vector(to_unsigned(int_rand, rv(i)'length));
--end loop;
--return rv;
--end function init_seeds;
------------------------------------------------------------
-- TODO initialise constants
--constant seeds : lfsr_state_array_t(1 to num_samplers) := init_seeds;
signal state : state_array_t(1 to num_samplers);
begin
------------------------------------------------------------
net: entity work.sampling_network(rtl)
generic map (
num_samplers => num_samplers,
tau => tau
)
port map (
clk => clk,
reset => reset,
clock_tick => open,
systime => systime,
state => state,
membranes => open,
fires => open,
seeds => seeds,
biases => biases,
weights => weights
);
------------------------------------------------------------
------------------------------------------------------------
gen_observers: for observer_i in 1 to num_observers generate
signal observe_state : state_array_t(1 to num_samplers);
begin
------------------------------------------------------------
process ( observed_joints )
begin
for i in 1 to num_samplers loop
observe_state(i) <= observed_joints(observer_i, i);
end loop;
end process;
------------------------------------------------------------
obs: entity work.observer(rtl)
generic map (
num_samplers => num_samplers,
counter_width => joint_counter_width
)
port map (
clk => clk,
reset => reset,
state => state,
observe_state => observe_state,
count => joint_counters(observer_i),
saturated => open
);
end generate gen_observers;
------------------------------------------------------------
end rtl;
-- vim: set et fenc= ff=unix sts=0 sw=2 ts=2 :
|
apache-2.0
|
chipsalliance/Surelog
|
third_party/tests/YosysTests/frontends/read/top.vhd
|
2
|
302
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
clk : in STD_LOGIC;
A : out STD_LOGIC;
cout : out STD_LOGIC
);
end entity;
architecture beh of top is
begin
A <= y + cin;
cout <= y + A;
end architecture;
|
apache-2.0
|
chipsalliance/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/slib_counter.vhd
|
5
|
2883
|
--
-- Counter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.2
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Counter
entity slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end slib_counter;
architecture rtl of slib_counter is
signal iCounter : unsigned(WIDTH downto 0); -- Counter register
begin
-- Counter process
COUNT_SHIFT: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0'); -- Reset counter register
elsif (CLK'event and CLK='1') then
if (CLEAR = '1') then
iCounter <= (others => '0'); -- Clear counter register
elsif (LOAD = '1') then -- Load counter register
iCounter <= unsigned('0' & D);
elsif (ENABLE = '1') then -- Enable counter
if (DOWN = '0') then -- Count up
iCounter <= iCounter + 1;
else -- Count down
iCounter <= iCounter - 1;
end if;
end if;
if (iCounter(WIDTH) = '1') then -- Clear overflow
iCounter(WIDTH) <= '0';
end if;
end if;
end process;
-- Output ports
Q <= std_logic_vector(iCounter(WIDTH-1 downto 0));
OVERFLOW <= iCounter(WIDTH);
end rtl;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/add_inferred.vhdl
|
1
|
1626
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity add_inferred is
generic (
src_bits : natural := 32
);
port (
carryin : in std_ulogic;
src1 : in std_ulogic_vector(src_bits-1 downto 0);
src2 : in std_ulogic_vector(src_bits-1 downto 0);
result : out std_ulogic_vector(src_bits-1 downto 0);
carryout : out std_ulogic;
overflow : out std_ulogic
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/mmu/data/pass/cpu_mmu_data_pass_pkg.vhdl
|
1
|
1808
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_mmu_data_types_pkg.all;
use work.cpu_types_pkg.all;
package cpu_mmu_data_pass_pkg is
type cpu_mmu_data_pass_ctrl_in_type is record
request : std_ulogic;
mmuen : std_ulogic;
end record;
type cpu_mmu_data_pass_ctrl_out_type is record
ready : std_ulogic;
result : cpu_mmu_data_result_code_type;
end record;
type cpu_mmu_data_pass_dp_in_type is record
vpn : cpu_vpn_type;
end record;
type cpu_mmu_data_pass_dp_out_type is record
ppn : cpu_ppn_type;
end record;
end package;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/mmu/inst/cpu_mmu_inst.vhdl
|
1
|
1715
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_inst_pkg.all;
entity cpu_mmu_inst is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_inst_ctrl_in : in cpu_mmu_inst_ctrl_in_type;
cpu_mmu_inst_dp_in : in cpu_mmu_inst_dp_in_type;
cpu_mmu_inst_ctrl_out : out cpu_mmu_inst_ctrl_out_type;
cpu_mmu_inst_dp_out : out cpu_mmu_inst_dp_out_type
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/madd-rtl.vhdl
|
1
|
1583
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of madd is
begin
madd : entity work.madd_inferred(rtl)
generic map (
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
unsgnd => unsgnd,
sub => sub,
acc => acc,
src1 => src1,
src2 => src2,
result => result,
overflow => overflow
);
end;
|
apache-2.0
|
smithe0/GestureControlInterface
|
DE2Component_FLASH/niosII_system/synthesis/niosii_system_nios2_qsys_0_instruction_master_translator.vhd
|
1
|
14346
|
-- niosii_system_nios2_qsys_0_instruction_master_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_nios2_qsys_0_instruction_master_translator is
generic (
AV_ADDRESS_W : integer := 25;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
USE_READ : integer := 1;
USE_WRITE : integer := 0;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 1;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 1;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : out std_logic_vector(24 downto 0); -- avalon_universal_master_0.address
uav_burstcount : out std_logic_vector(2 downto 0); -- .burstcount
uav_read : out std_logic; -- .read
uav_write : out std_logic; -- .write
uav_waitrequest : in std_logic := '0'; -- .waitrequest
uav_readdatavalid : in std_logic := '0'; -- .readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
uav_writedata : out std_logic_vector(31 downto 0); -- .writedata
uav_lock : out std_logic; -- .lock
uav_debugaccess : out std_logic; -- .debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_anti_master_0.address
av_waitrequest : out std_logic; -- .waitrequest
av_read : in std_logic := '0'; -- .read
av_readdata : out std_logic_vector(31 downto 0); -- .readdata
av_beginbursttransfer : in std_logic := '0';
av_begintransfer : in std_logic := '0';
av_burstcount : in std_logic_vector(0 downto 0) := (others => '0');
av_byteenable : in std_logic_vector(3 downto 0) := (others => '0');
av_chipselect : in std_logic := '0';
av_clken : in std_logic := '0';
av_debugaccess : in std_logic := '0';
av_lock : in std_logic := '0';
av_readdatavalid : out std_logic;
av_response : out std_logic_vector(1 downto 0);
av_write : in std_logic := '0';
av_writedata : in std_logic_vector(31 downto 0) := (others => '0');
av_writeresponserequest : in std_logic := '0';
av_writeresponsevalid : out std_logic;
uav_clken : out std_logic;
uav_response : in std_logic_vector(1 downto 0) := (others => '0');
uav_writeresponserequest : out std_logic;
uav_writeresponsevalid : in std_logic := '0'
);
end entity niosii_system_nios2_qsys_0_instruction_master_translator;
architecture rtl of niosii_system_nios2_qsys_0_instruction_master_translator is
component altera_merlin_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_lock : in std_logic := 'X'; -- lock
av_debugaccess : in std_logic := 'X'; -- debugaccess
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_translator;
begin
nios2_qsys_0_instruction_master_translator : component altera_merlin_master_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
USE_READ => USE_READ,
USE_WRITE => USE_WRITE,
USE_BEGINBURSTTRANSFER => USE_BEGINBURSTTRANSFER,
USE_BEGINTRANSFER => USE_BEGINTRANSFER,
USE_CHIPSELECT => USE_CHIPSELECT,
USE_BURSTCOUNT => USE_BURSTCOUNT,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_LINEWRAPBURSTS => AV_LINEWRAPBURSTS,
AV_REGISTERINCOMINGSIGNALS => AV_REGISTERINCOMINGSIGNALS
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_master_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_master_0.address
av_waitrequest => av_waitrequest, -- .waitrequest
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_burstcount => "1", -- (terminated)
av_byteenable => "1111", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_write => '0', -- (terminated)
av_writedata => "00000000000000000000000000000000", -- (terminated)
av_lock => '0', -- (terminated)
av_debugaccess => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
end architecture rtl; -- of niosii_system_nios2_qsys_0_instruction_master_translator
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/encoder.vhdl
|
1
|
1521
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.numeric_pkg.all;
entity encoder is
generic (
input_bits : natural := 2
);
port (
datain : in std_ulogic_vector(input_bits-1 downto 0);
dataout : out std_ulogic_vector(bitsize(input_bits-1)-1 downto 0)
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/inst/pass/cpu_l1mem_inst_pass_pkg.vhdl
|
1
|
2078
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
use work.cpu_types_pkg.all;
use work.cpu_l1mem_inst_types_pkg.all;
package cpu_l1mem_inst_pass_pkg is
type cpu_l1mem_inst_pass_ctrl_in_type is record
request : cpu_l1mem_inst_request_code_type;
cacheen : std_ulogic;
mmuen : std_ulogic;
alloc : std_ulogic;
priv : std_ulogic;
direction : cpu_l1mem_inst_fetch_direction_type;
end record;
type cpu_l1mem_inst_pass_dp_in_type is record
vaddr : cpu_ivaddr_type;
end record;
type cpu_l1mem_inst_pass_ctrl_out_type is record
ready : std_ulogic;
result : cpu_l1mem_inst_result_code_type;
end record;
type cpu_l1mem_inst_pass_dp_out_type is record
paddr : cpu_ipaddr_type;
data : cpu_inst_type;
end record;
end package;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/madd_pipe_inferred-rtl.vhdl
|
1
|
3565
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of madd_pipe_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
prod_tmp1 : std_ulogic_vector(src1_bits+src2_bits+1 downto 0);
prod_tmp2 : std_ulogic_vector(src1_bits+src2_bits downto 0);
acc_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_msb_carryin : std_ulogic;
result_msb : std_ulogic;
carryout : std_ulogic;
end record;
type stage_type is record
overflow : std_ulogic;
result : std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
end record;
type reg_type is array(0 to stages-1) of stage_type;
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src2(src2_bits-1) and not unsgnd) & src2;
c.prod_tmp1 <= std_ulogic_vector(signed(c.src1_tmp) * signed(c.src2_tmp));
c.prod_tmp2 <= (('0' & c.prod_tmp1(src1_bits+src2_bits-2 downto 0) & '0') xor
(src1_bits+src2_bits downto 0 => sub));
c.acc_tmp <= '0' & acc(src1_bits+src2_bits-2 downto 0) & '1';
c.result_tmp <= std_ulogic_vector(signed(c.acc_tmp) +
signed(c.prod_tmp2));
c.result_msb_carryin <= c.result_tmp(src1_bits+src2_bits);
c.result_msb <= (acc(src1_bits+src2_bits-1) xor
c.prod_tmp1(src1_bits+src2_bits-1) xor
c.result_msb_carryin
);
c.carryout <= (((sub xor acc(src1_bits+src2_bits-1)) and (c.prod_tmp1(src1_bits+src2_bits-1) or c.result_msb_carryin)) or
(c.prod_tmp1(src1_bits+src2_bits-1) and c.result_msb_carryin));
r_next(0).overflow <= c.carryout xor (not unsgnd and c.result_msb_carryin);
r_next(0).result <= c.result_msb & c.result_tmp(src1_bits+src2_bits-1 downto 1);
stages_gt_1 : if stages > 1 generate
pipeline_loop : for n in 1 to stages-1 generate
r_next(n) <= r(n-1);
end generate;
end generate;
overflow <= r(stages-1).overflow;
result <= r(stages-1).result;
seq : process(clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/syncram_1r1w-rtl.vhdl
|
1
|
1672
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of syncram_1r1w is
begin
syncram : entity work.syncram_1r1w_inferred(rtl)
generic map (
addr_bits => addr_bits,
data_bits => data_bits,
write_first => write_first
)
port map (
clk => clk,
we => we,
waddr => waddr,
wdata => wdata,
re => re,
raddr => raddr,
rdata => rdata
);
end;
|
apache-2.0
|
smithe0/GestureControlInterface
|
DE2Component_FLASH/niosII_system/synthesis/niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo.vhd
|
1
|
8495
|
-- niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 101;
FIFO_DEPTH : integer := 2;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 1;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 1;
USE_MEMORY_BLOCKS : integer := 0;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(100 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
out_data : out std_logic_vector(100 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
out_endofpacket : out std_logic; -- .endofpacket
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_error : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_error : out std_logic
);
end entity niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo;
architecture rtl of niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(100 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
out_endofpacket => out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/madd_inferred-rtl.vhdl
|
1
|
2975
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of madd_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
prod_tmp1 : std_ulogic_vector(src1_bits+src2_bits+1 downto 0);
prod_tmp2 : std_ulogic_vector(src1_bits+src2_bits downto 0);
acc_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_msb_carryin : std_ulogic;
result_msb : std_ulogic;
carryout : std_ulogic;
end record;
signal c : comb_type;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src2(src2_bits-1) and not unsgnd) & src2;
c.prod_tmp1 <= std_ulogic_vector(signed(c.src1_tmp) * signed(c.src2_tmp));
c.prod_tmp2 <= (('0' & c.prod_tmp1(src1_bits+src2_bits-2 downto 0) & '0') xor
(src1_bits+src2_bits downto 0 => sub));
c.acc_tmp <= '0' & acc(src1_bits+src2_bits-2 downto 0) & '1';
c.result_tmp <= std_ulogic_vector(signed(c.acc_tmp) +
signed(c.prod_tmp2));
c.result_msb_carryin <= c.result_tmp(src1_bits+src2_bits);
c.result_msb <= (acc(src1_bits+src2_bits-1) xor
c.prod_tmp1(src1_bits+src2_bits-1) xor
c.result_msb_carryin
);
c.carryout <= (((sub xor acc(src1_bits+src2_bits-1)) and (c.prod_tmp1(src1_bits+src2_bits-1) or c.result_msb_carryin)) or
(c.prod_tmp1(src1_bits+src2_bits-1) and c.result_msb_carryin));
overflow <= c.carryout xor (not unsgnd and c.result_msb_carryin);
result <= c.result_msb & c.result_tmp(src1_bits+src2_bits-1 downto 1);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/data/pass/cpu_l1mem_data_pass-rtl.vhdl
|
1
|
14275
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library sys;
use sys.sys_pkg.all;
use sys.sys_config_pkg.all;
use work.cpu_types_pkg.all;
use work.cpu_l1mem_data_types_pkg.all;
use work.cpu_mmu_data_types_pkg.all;
architecture rtl of cpu_l1mem_data_pass is
type state_index_type is (
state_index_idle,
state_index_mmu_access,
state_index_bus_access
);
type state_type is array (state_index_type range state_index_type'high downto state_index_type'low) of std_ulogic;
constant state_idle : state_type := "001";
constant state_mmu_access : state_type := "010";
constant state_bus_access : state_type := "100";
type paddr_sel_index_type is (
paddr_sel_index_reg,
paddr_sel_index_incoming,
paddr_sel_index_mmu
);
type paddr_sel_type is array (paddr_sel_index_type range paddr_sel_index_type'high downto paddr_sel_index_type'low) of std_ulogic;
constant paddr_sel_reg : paddr_sel_type := "001";
constant paddr_sel_incoming : paddr_sel_type := "010";
constant paddr_sel_mmu : paddr_sel_type := "100";
type comb_type is record
state_next : state_type;
mmu_request : std_ulogic;
bus_request : std_ulogic;
bus_requested_next : std_ulogic;
incoming_request : std_ulogic;
use_incoming_request : std_ulogic;
write : std_ulogic;
incoming_size : sys_transfer_size_type;
be : std_ulogic;
size : sys_transfer_size_type;
mmuen : std_ulogic;
cacheen : std_ulogic;
priv : std_ulogic;
store_data : cpu_word_type;
incoming_paddr : cpu_paddr_type;
mmu_paddr : cpu_paddr_type;
bus_paddr_sel : paddr_sel_type;
bus_paddr : cpu_paddr_type;
paddr_next : cpu_paddr_type;
end record;
type reg_type is record
state : state_type;
bus_requested : std_ulogic;
write : std_ulogic;
be : std_ulogic;
size : sys_transfer_size_type;
mmuen : std_ulogic;
cacheen : std_ulogic;
priv : std_ulogic;
store_data : cpu_word_type;
paddr : cpu_paddr_type;
end record;
constant reg_x : reg_type := (
state => (others => 'X'),
bus_requested => 'X',
write => 'X',
be => 'X',
size => (others => 'X'),
mmuen => 'X',
cacheen => 'X',
priv => 'X',
store_data => (others => 'X'),
paddr => (others => 'X')
);
constant reg_init : reg_type := (
state => state_idle,
bus_requested => 'X',
write => 'X',
be => 'X',
size => (others => 'X'),
mmuen => 'X',
cacheen => 'X',
priv => 'X',
store_data => (others => 'X'),
paddr => (others => 'X')
);
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.incoming_request <= (cpu_l1mem_data_pass_ctrl_in.request(cpu_l1mem_data_request_code_index_load) or
cpu_l1mem_data_pass_ctrl_in.request(cpu_l1mem_data_request_code_index_store));
with r.state select
c.state_next <= (state_index_idle => not c.incoming_request,
state_index_mmu_access => c.incoming_request and cpu_l1mem_data_pass_ctrl_in.mmuen,
state_index_bus_access => c.incoming_request and not cpu_l1mem_data_pass_ctrl_in.mmuen
) when state_idle,
(state_index_idle => (cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid) and
not c.incoming_request
),
state_index_mmu_access => (not cpu_mmu_data_ctrl_out.ready or
(not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid) and
c.incoming_request)
),
state_index_bus_access => (cpu_mmu_data_ctrl_out.ready and
cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)
)
) when state_mmu_access,
(state_index_idle => (r.bus_requested and
sys_slave_ctrl_out.ready and
not c.incoming_request
),
state_index_mmu_access => (r.bus_requested and
sys_slave_ctrl_out.ready and
c.incoming_request and
cpu_l1mem_data_pass_ctrl_in.mmuen
),
state_index_bus_access => ((sys_slave_ctrl_out.ready and
c.incoming_request and
not cpu_l1mem_data_pass_ctrl_in.mmuen
) or
not r.bus_requested or
not sys_slave_ctrl_out.ready
)
) when state_bus_access,
(others => 'X') when others;
c.mmu_request <= r.state(state_index_idle) and c.incoming_request;
with r.state select
c.bus_request <= (c.incoming_request and
not cpu_l1mem_data_pass_ctrl_in.mmuen) when state_idle,
cpu_mmu_data_ctrl_out.ready when state_mmu_access,
(not r.bus_requested or
(c.incoming_request and
not cpu_l1mem_data_pass_ctrl_in.mmuen)) when state_bus_access,
'X' when others;
c.use_incoming_request <= (r.state(state_index_idle) or
(r.state(state_index_mmu_access) and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)) or
(r.state(state_index_bus_access) and sys_slave_ctrl_out.ready)
);
with r.state select
c.bus_requested_next <= not cpu_l1mem_data_pass_ctrl_in.mmuen and sys_slave_ctrl_out.ready when state_idle,
cpu_mmu_data_ctrl_out.ready and sys_slave_ctrl_out.ready when state_mmu_access,
r.bus_requested or sys_slave_ctrl_out.ready when state_bus_access,
'X' when others;
with c.use_incoming_request select
c.write <= cpu_l1mem_data_pass_ctrl_in.request(cpu_l1mem_data_request_code_index_store) when '1',
r.write when '0',
'X' when others;
c.incoming_size(cpu_data_size_bits-1 downto 0) <= cpu_l1mem_data_pass_dp_in.size;
incoming_size_high_bits : if sys_transfer_size_bits > cpu_data_size_bits generate
c.incoming_size(sys_transfer_size_bits downto cpu_data_size_bits) <= (others => '0');
end generate;
with c.use_incoming_request select
c.size <= c.incoming_size when '1',
r.size when '0',
(others => 'X') when others;
with c.use_incoming_request select
c.mmuen <= cpu_l1mem_data_pass_ctrl_in.mmuen when '1',
r.mmuen when '0',
'X' when others;
with c.use_incoming_request select
c.cacheen <= cpu_l1mem_data_pass_ctrl_in.cacheen when '1',
r.cacheen when '0',
'X' when others;
with c.use_incoming_request select
c.priv <= cpu_l1mem_data_pass_ctrl_in.priv when '1',
r.priv when '0',
'X' when others;
with c.use_incoming_request select
c.be <= cpu_l1mem_data_pass_ctrl_in.be when '1',
r.be when '0',
'X' when others;
with c.use_incoming_request select
c.store_data <= cpu_l1mem_data_pass_dp_in.data when '1',
r.store_data when '0',
(others => 'X') when others;
incoming_paddr_vaddr_bigger : if cpu_vaddr_bits >= cpu_paddr_bits generate
c.incoming_paddr <= cpu_l1mem_data_pass_dp_in.vaddr(cpu_paddr_bits-1 downto 0);
end generate;
incoming_paddr_vaddr_smaller : if cpu_vaddr_bits < cpu_paddr_bits generate
c.incoming_paddr(cpu_paddr_bits-1 downto cpu_vaddr_bits) <= (others => '0');
c.incoming_paddr(cpu_vaddr_bits-1 downto 0) <= cpu_l1mem_data_pass_dp_in.vaddr;
end generate;
mmu_paddr_gen_0 : if cpu_ppn_bits = 0 generate
c.mmu_paddr <= r.paddr;
end generate;
mmu_paddr_gen_n : if cpu_ppn_bits > 0 generate
c.mmu_paddr <= cpu_mmu_data_dp_out.ppn & r.paddr(cpu_poffset_bits-1 downto 0);
end generate;
with r.state select
c.bus_paddr_sel <= paddr_sel_incoming when state_idle,
paddr_sel_mmu when state_mmu_access,
(paddr_sel_index_reg => not r.bus_requested or not sys_slave_ctrl_out.ready,
paddr_sel_index_incoming => r.bus_requested and sys_slave_ctrl_out.ready,
paddr_sel_index_mmu => '0'
) when state_bus_access,
(others => 'X') when others;
with c.bus_paddr_sel select
c.bus_paddr <= r.paddr when paddr_sel_reg,
c.incoming_paddr when paddr_sel_incoming,
c.mmu_paddr when paddr_sel_mmu,
(others => 'X') when others;
c.paddr_next <= c.bus_paddr;
cpu_l1mem_data_pass_ctrl_out <= (
ready => (sys_slave_ctrl_out.ready and
not r.state(state_index_mmu_access)
),
result => (
cpu_l1mem_data_result_code_index_valid => (
not ((r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)) or
(r.state(state_index_bus_access) and
sys_slave_ctrl_out.ready and
sys_slave_ctrl_out.error)
)
),
cpu_l1mem_data_result_code_index_error => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_error)) or
(r.state(state_index_bus_access) and
sys_slave_ctrl_out.ready and
sys_slave_ctrl_out.error)
),
cpu_l1mem_data_result_code_index_tlbmiss => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_tlbmiss))
),
cpu_l1mem_data_result_code_index_pf => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_pf))
)
)
);
cpu_l1mem_data_pass_dp_out <= (
paddr => r.paddr,
data => sys_slave_dp_out.data(cpu_word_bits-1 downto 0)
);
cpu_mmu_data_ctrl_in <= (
request => c.mmu_request,
mmuen => c.mmuen
);
sys_master_ctrl_out <= (
request => c.bus_request,
be => c.be,
write => c.write,
cacheable => c.cacheen,
priv => c.priv,
inst => '0',
burst => '0',
bwrap => 'X',
bcycles => (others => 'X')
);
sys_master_dp_out <= (
size => c.size,
paddr => (sys_paddr_bits-1 downto cpu_paddr_bits => '0') & c.bus_paddr,
data => c.store_data
);
r_next <= (
state => c.state_next,
bus_requested => c.bus_requested_next,
write => c.write,
size => c.size,
mmuen => c.mmuen,
cacheen => c.cacheen,
be => c.be,
priv => c.priv,
paddr => c.paddr_next,
store_data => c.store_data
);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r <= reg_init;
when others =>
r <= reg_x;
end case;
end if;
end process;
end;
|
apache-2.0
|
smithe0/GestureControlInterface
|
DE2Component_FLASH/niosII_system/synthesis/niosii_system_sram_0_avalon_sram_slave_translator.vhd
|
1
|
14693
|
-- niosii_system_sram_0_avalon_sram_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_sram_0_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 18;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 16;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 2;
UAV_BYTEENABLE_W : integer := 2;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 2;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 2;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- .readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(17 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_byteenable : out std_logic_vector(1 downto 0); -- .byteenable
av_readdatavalid : in std_logic := '0'; -- .readdatavalid
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(1 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_sram_0_avalon_sram_slave_translator;
architecture rtl of niosii_system_sram_0_avalon_sram_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
sram_0_avalon_sram_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_readdatavalid => av_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_sram_0_avalon_sram_slave_translator
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/data/cache/cpu_l1mem_data_cache_pkg.vhdl
|
1
|
14834
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
use work.cpu_l1mem_data_cache_config_pkg.all;
use work.cpu_l1mem_data_types_pkg.all;
use work.cpu_types_pkg.all;
package cpu_l1mem_data_cache_pkg is
constant cpu_l1mem_data_cache_assoc : natural := 2**cpu_l1mem_data_cache_log2_assoc;
type cpu_l1mem_data_cache_ctrl_in_type is record
-- when '1' indicates a new request, must be '0' while
-- waiting for a miss return, otherwise '1' will cancel
-- a pending request
request : cpu_l1mem_data_request_code_type;
cacheen : std_ulogic;
mmuen : std_ulogic;
alloc : std_ulogic;
writethrough : std_ulogic;
priv : std_ulogic;
be : std_ulogic;
end record;
type cpu_l1mem_data_cache_dp_in_type is record
size : cpu_data_size_type;
vaddr : cpu_vaddr_type;
data : cpu_word_type;
end record;
type cpu_l1mem_data_cache_ctrl_out_type is record
ready : std_ulogic;
result : cpu_l1mem_data_result_code_type;
end record;
type cpu_l1mem_data_cache_dp_out_type is record
paddr : cpu_paddr_type;
data : cpu_word_type;
end record;
constant cpu_l1mem_data_cache_block_bytes : natural := 2**cpu_l1mem_data_cache_offset_bits;
constant cpu_l1mem_data_cache_log2_block_words : natural := cpu_l1mem_data_cache_offset_bits - cpu_log2_word_bytes;
constant cpu_l1mem_data_cache_block_words : natural := 2**cpu_l1mem_data_cache_log2_block_words;
constant cpu_l1mem_data_cache_tag_bits : natural := cpu_paddr_bits - cpu_l1mem_data_cache_index_bits - cpu_l1mem_data_cache_offset_bits;
type cpu_l1mem_data_cache_owner_index_type is (
cpu_l1mem_data_cache_owner_index_none,
cpu_l1mem_data_cache_owner_index_request,
cpu_l1mem_data_cache_owner_index_stb,
cpu_l1mem_data_cache_owner_index_bus_op
);
type cpu_l1mem_data_cache_owner_type is
array (cpu_l1mem_data_cache_owner_index_type range
cpu_l1mem_data_cache_owner_index_type'high downto
cpu_l1mem_data_cache_owner_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_owner_none : cpu_l1mem_data_cache_owner_type := "0001";
constant cpu_l1mem_data_cache_owner_request : cpu_l1mem_data_cache_owner_type := "0010";
constant cpu_l1mem_data_cache_owner_stb : cpu_l1mem_data_cache_owner_type := "0100";
constant cpu_l1mem_data_cache_owner_bus_op : cpu_l1mem_data_cache_owner_type := "1000";
type cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_type is (
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_old,
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_request,
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_stb,
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_replace
);
type cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type is
array (cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_type range
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_type'high downto
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_old : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type := "0001";
constant cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type := "0010";
constant cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type := "0100";
constant cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_replace : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type := "1000";
type cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_type is (
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_old,
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_request,
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_stb
);
type cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type is
array (cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_type range
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_type'high downto
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_old : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type := "001";
constant cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type := "010";
constant cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type := "100";
type cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_type is (
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_old,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_next_word,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_request,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_request_word,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_stb,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_stb_word
);
type cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type is
array (cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_type range
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_type'high downto
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_old : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "000001";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_next_word : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "000010";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "000100";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request_word : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "001000";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "010000";
constant cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb_word : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type := "100000";
type cpu_l1mem_data_cache_a_bus_op_size_sel_index_type is (
cpu_l1mem_data_cache_a_bus_op_size_sel_index_old,
cpu_l1mem_data_cache_a_bus_op_size_sel_index_word,
cpu_l1mem_data_cache_a_bus_op_size_sel_index_request,
cpu_l1mem_data_cache_a_bus_op_size_sel_index_stb
);
type cpu_l1mem_data_cache_a_bus_op_size_sel_type is
array (cpu_l1mem_data_cache_a_bus_op_size_sel_index_type range
cpu_l1mem_data_cache_a_bus_op_size_sel_index_type'high downto
cpu_l1mem_data_cache_a_bus_op_size_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_a_bus_op_size_sel_old : cpu_l1mem_data_cache_a_bus_op_size_sel_type := "0001";
constant cpu_l1mem_data_cache_a_bus_op_size_sel_word : cpu_l1mem_data_cache_a_bus_op_size_sel_type := "0010";
constant cpu_l1mem_data_cache_a_bus_op_size_sel_request : cpu_l1mem_data_cache_a_bus_op_size_sel_type := "0100";
constant cpu_l1mem_data_cache_a_bus_op_size_sel_stb : cpu_l1mem_data_cache_a_bus_op_size_sel_type := "1000";
type cpu_l1mem_data_cache_b_result_data_sel_index_type is (
cpu_l1mem_data_cache_b_result_data_sel_index_cache,
cpu_l1mem_data_cache_b_result_data_sel_index_bus,
cpu_l1mem_data_cache_b_result_data_sel_index_bus_shifted,
cpu_l1mem_data_cache_b_result_data_sel_index_stb
);
type cpu_l1mem_data_cache_b_result_data_sel_type is
array (cpu_l1mem_data_cache_b_result_data_sel_index_type range
cpu_l1mem_data_cache_b_result_data_sel_index_type'high downto
cpu_l1mem_data_cache_b_result_data_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_data_cache_b_result_data_sel_cache : cpu_l1mem_data_cache_b_result_data_sel_type := "0001";
constant cpu_l1mem_data_cache_b_result_data_sel_bus : cpu_l1mem_data_cache_b_result_data_sel_type := "0010";
constant cpu_l1mem_data_cache_b_result_data_sel_bus_shifted : cpu_l1mem_data_cache_b_result_data_sel_type := "0100";
constant cpu_l1mem_data_cache_b_result_data_sel_stb : cpu_l1mem_data_cache_b_result_data_sel_type := "1000";
type cpu_l1mem_data_cache_dp_in_ctrl_type is record
a_stb_head_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_head_be : std_ulogic;
a_stb_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_bus_op_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_bus_op_paddr_tag_sel : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type;
a_bus_op_paddr_index_sel : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type;
a_bus_op_paddr_offset_sel : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type;
a_bus_op_size_sel : cpu_l1mem_data_cache_a_bus_op_size_sel_type;
a_bus_op_cache_paddr_sel_old : std_ulogic;
a_bus_op_sys_paddr_sel_old : std_ulogic;
a_bus_op_sys_data_sel_cache : std_ulogic;
a_vtram_owner : cpu_l1mem_data_cache_owner_type;
a_rmdram_owner : cpu_l1mem_data_cache_owner_type;
a_bus_op_owner : cpu_l1mem_data_cache_owner_type;
a_dram_wdata_be : std_ulogic;
b_vtram_owner : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner : cpu_l1mem_data_cache_owner_type;
b_replace_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_cache_read_data_be : std_ulogic;
b_cache_read_data_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_be : std_ulogic;
b_request_stb_array_hit : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_complete : std_ulogic;
b_stb_head_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_push_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_combine_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_result_data_sel : cpu_l1mem_data_cache_b_result_data_sel_type;
end record;
type cpu_l1mem_data_cache_dp_out_ctrl_type is record
b_request_cache_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_stb_array_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_size_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_index_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_block_word_offset_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_word_byte_offset_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_block_change_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_block_change_index_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_in_vram_type is record
rdata : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_out_vram_type is record
re : std_ulogic;
we : std_ulogic;
wdata : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_out_vram_type is record
raddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
waddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_in_mram_type is record
rdata : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_out_mram_type is record
re : std_ulogic;
we : std_ulogic;
wdata : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_out_mram_type is record
raddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
waddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_out_tram_type is record
en : std_ulogic;
we : std_ulogic;
banken : std_ulogic_vector(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_in_tram_type is record
rdata : std_ulogic_vector2(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_out_tram_type is record
addr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
wdata : std_ulogic_vector2(2**cpu_l1mem_data_cache_log2_assoc-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_ctrl_out_dram_type is record
en : std_ulogic;
we : std_ulogic;
end record;
type cpu_l1mem_data_cache_dp_in_dram_type is record
rdata : std_ulogic_vector2(2**(cpu_l1mem_data_cache_log2_assoc+cpu_log2_word_bytes)-1 downto 0,
byte_bits-1 downto 0);
end record;
type cpu_l1mem_data_cache_dp_out_dram_type is record
banken : std_ulogic_vector(2**(cpu_l1mem_data_cache_log2_assoc+cpu_log2_word_bytes)-1 downto 0);
addr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
wdata : std_ulogic_vector2(2**(cpu_l1mem_data_cache_log2_assoc+cpu_log2_word_bytes)-1 downto 0,
byte_bits-1 downto 0);
end record;
end package;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/lfsr_inferred-rtl.vhdl
|
1
|
2497
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.logic_pkg.all;
architecture rtl of lfsr_inferred is
subtype state_type is std_ulogic_vector(state_bits-1 downto 0);
constant taps : state_type := lfsr_taps(state_bits);
type comb_type is record
state_next : state_type;
end record;
signal c : comb_type;
type reg_type is record
state : state_type;
end record;
signal r, r_next : reg_type;
begin
-- Galois style
state_next_gen : for n in state_bits-2 downto 0 generate
tap : if taps(n) = '1' generate
c.state_next(n) <= r.state(n+1) xor r.state(0);
end generate;
no_tap : if taps(n) = '0' generate
c.state_next(n) <= r.state(n+1);
end generate;
end generate;
c.state_next(state_bits-1) <= r.state(0);
with en select
r_next.state <= c.state_next when '1',
r.state when '0',
(others => 'X') when others;
output <= r.state(0);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r.state(0) <= '1';
r.state(state_bits-1 downto 1) <= (others => '0');
when others =>
r <= (state => (others => 'X'));
end case;
end if;
end process;
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/div_pipe-rtl.vhdl
|
1
|
1612
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of div_pipe is
begin
div : entity work.div_pipe_inferred(rtl)
generic map (
stages => stages,
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
clk => clk,
rstn => rstn,
unsgnd => unsgnd,
src1 => src1,
src2 => src2,
dbz => dbz,
overflow => overflow,
result => result
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/util/names_pkg-vcs.vhdl
|
1
|
1634
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
package names_pkg is
pure function entity_path_name(name : string) return string;
end package;
package body names_pkg is
-- VCS sometimes leaves the trailing colon off 'path_name and 'instance_name
pure function entity_path_name(name : string) return string is
begin
if name(name'right) /= ':' then
return name & ":";
else
return name;
end if;
end function;
end package body;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/mul_pipe_inferred.vhdl
|
1
|
1693
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mul_pipe_inferred is
generic (
stages : positive := 3;
src1_bits : natural := 32;
src2_bits : natural := 32
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src2_bits-1 downto 0);
result : out std_ulogic_vector(src1_bits+src2_bits-1 downto 0)
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/btb/cache/cpu_btb_cache_pkg.vhdl
|
1
|
2443
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_btb_cache_config_pkg.all;
use work.cpu_btb_cache_replace_pkg.all;
use work.cpu_types_pkg.all;
package cpu_btb_cache_pkg is
constant cpu_btb_cache_assoc : natural := 2**cpu_btb_cache_log2_assoc;
constant cpu_btb_cache_state_bits : natural := (cpu_btb_cache_assoc + -- way
cpu_btb_cache_assoc + -- replace_way
cpu_btb_cache_replace_state_bits -- replace_state
);
subtype cpu_btb_cache_state_type is std_ulogic_vector(cpu_btb_cache_state_bits-1 downto 0);
type cpu_btb_cache_ctrl_in_type is record
ren : std_ulogic;
wen : std_ulogic;
end record;
type cpu_btb_cache_dp_in_type is record
raddr : cpu_ivaddr_type;
waddr : cpu_ivaddr_type;
wstate : cpu_btb_cache_state_type;
wtarget : cpu_ivaddr_type;
end record;
type cpu_btb_cache_ctrl_out_type is record
rvalid : std_ulogic;
end record;
type cpu_btb_cache_dp_out_type is record
rstate : cpu_btb_cache_state_type;
rtarget : cpu_ivaddr_type;
end record;
end package;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/prioritizer_inferred-rtl.vhdl
|
1
|
19302
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture rtl of prioritizer_inferred is
begin
input_bits_1 : if input_bits = 1 generate
dataout <= datain;
end generate;
input_bits_2 : if input_bits = 2 generate
dataout <= (others => 'X') when is_x(datain(1)) else
"10" when datain(1) = '1' else
"0X" when is_x(datain(0)) else
"01" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_3 : if input_bits = 3 generate
dataout <= (others => 'X') when is_x(datain(2)) else
"100" when datain(2) = '1' else
"0XX" when is_x(datain(1)) else
"010" when datain(1) = '1' else
"00X" when is_x(datain(0)) else
"001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_4 : if input_bits = 4 generate
dataout <= (others => 'X') when is_x(datain(3)) else
"1000" when datain(3) = '1' else
"0XXX" when is_x(datain(2)) else
"0100" when datain(2) = '1' else
"00XX" when is_x(datain(1)) else
"0010" when datain(1) = '1' else
"000X" when is_x(datain(0)) else
"0001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_5 : if input_bits = 5 generate
dataout <= (others => 'X') when is_x(datain(4)) else
"10000" when datain(4) = '1' else
"0XXXX" when is_x(datain(3)) else
"01000" when datain(3) = '1' else
"00XXX" when is_x(datain(2)) else
"00100" when datain(2) = '1' else
"000XX" when is_x(datain(1)) else
"00010" when datain(1) = '1' else
"0000X" when is_x(datain(0)) else
"00001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_6 : if input_bits = 6 generate
dataout <= (others => 'X') when is_x(datain(5)) else
"100000" when datain(5) = '1' else
"0XXXXX" when is_x(datain(4)) else
"010000" when datain(4) = '1' else
"00XXXX" when is_x(datain(3)) else
"001000" when datain(3) = '1' else
"000XXX" when is_x(datain(2)) else
"000100" when datain(2) = '1' else
"0000XX" when is_x(datain(1)) else
"000010" when datain(1) = '1' else
"00000X" when is_x(datain(0)) else
"000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_7 : if input_bits = 7 generate
dataout <= (others => 'X') when is_x(datain(6)) else
"1000000" when datain(6) = '1' else
"0XXXXXX" when is_x(datain(5)) else
"0100000" when datain(5) = '1' else
"00XXXXX" when is_x(datain(4)) else
"0010000" when datain(4) = '1' else
"000XXXX" when is_x(datain(3)) else
"0001000" when datain(3) = '1' else
"0000XXX" when is_x(datain(2)) else
"0000100" when datain(2) = '1' else
"00000XX" when is_x(datain(1)) else
"0000010" when datain(1) = '1' else
"000000X" when is_x(datain(0)) else
"0000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_8 : if input_bits = 8 generate
dataout <= (others => 'X') when is_x(datain(7)) else
"10000000" when datain(7) = '1' else
"0XXXXXXX" when is_x(datain(6)) else
"01000000" when datain(6) = '1' else
"00XXXXXX" when is_x(datain(5)) else
"00100000" when datain(5) = '1' else
"000XXXXX" when is_x(datain(4)) else
"00010000" when datain(4) = '1' else
"0000XXXX" when is_x(datain(3)) else
"00001000" when datain(3) = '1' else
"00000XXX" when is_x(datain(2)) else
"00000100" when datain(2) = '1' else
"000000XX" when is_x(datain(1)) else
"00000010" when datain(1) = '1' else
"0000000X" when is_x(datain(0)) else
"00000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_9 : if input_bits = 9 generate
dataout <= (others => 'X') when is_x(datain(8)) else
"100000000" when datain(8) = '1' else
"0XXXXXXXX" when is_x(datain(7)) else
"010000000" when datain(7) = '1' else
"00XXXXXXX" when is_x(datain(6)) else
"001000000" when datain(6) = '1' else
"000XXXXXX" when is_x(datain(5)) else
"000100000" when datain(5) = '1' else
"0000XXXXX" when is_x(datain(4)) else
"000010000" when datain(4) = '1' else
"00000XXXX" when is_x(datain(3)) else
"000001000" when datain(3) = '1' else
"000000XXX" when is_x(datain(2)) else
"000000100" when datain(2) = '1' else
"0000000XX" when is_x(datain(1)) else
"000000010" when datain(1) = '1' else
"00000000X" when is_x(datain(0)) else
"000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_10 : if input_bits = 10 generate
dataout <= (others => 'X') when is_x(datain(9)) else
"1000000000" when datain(9) = '1' else
"0XXXXXXXXX" when is_x(datain(8)) else
"0100000000" when datain(8) = '1' else
"00XXXXXXXX" when is_x(datain(7)) else
"0010000000" when datain(7) = '1' else
"000XXXXXXX" when is_x(datain(6)) else
"0001000000" when datain(6) = '1' else
"0000XXXXXX" when is_x(datain(5)) else
"0000100000" when datain(5) = '1' else
"00000XXXXX" when is_x(datain(4)) else
"0000010000" when datain(4) = '1' else
"000000XXXX" when is_x(datain(3)) else
"0000001000" when datain(3) = '1' else
"0000000XXX" when is_x(datain(2)) else
"0000000100" when datain(2) = '1' else
"00000000XX" when is_x(datain(1)) else
"0000000010" when datain(1) = '1' else
"000000000X" when is_x(datain(0)) else
"0000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_11 : if input_bits = 11 generate
dataout <= (others => 'X') when is_x(datain(10)) else
"10000000000" when datain(10) = '1' else
"0XXXXXXXXXX" when is_x(datain(9)) else
"01000000000" when datain(9) = '1' else
"00XXXXXXXXX" when is_x(datain(8)) else
"00100000000" when datain(8) = '1' else
"000XXXXXXXX" when is_x(datain(7)) else
"00010000000" when datain(7) = '1' else
"0000XXXXXXX" when is_x(datain(6)) else
"00001000000" when datain(6) = '1' else
"00000XXXXXX" when is_x(datain(5)) else
"00000100000" when datain(5) = '1' else
"000000XXXXX" when is_x(datain(4)) else
"00000010000" when datain(4) = '1' else
"0000000XXXX" when is_x(datain(3)) else
"00000001000" when datain(3) = '1' else
"00000000XXX" when is_x(datain(2)) else
"00000000100" when datain(2) = '1' else
"000000000XX" when is_x(datain(1)) else
"00000000010" when datain(1) = '1' else
"0000000000X" when is_x(datain(0)) else
"00000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_12 : if input_bits = 12 generate
dataout <= (others => 'X') when is_x(datain(11)) else
"100000000000" when datain(11) = '1' else
"0XXXXXXXXXXX" when is_x(datain(10)) else
"010000000000" when datain(10) = '1' else
"00XXXXXXXXXX" when is_x(datain(9)) else
"001000000000" when datain(9) = '1' else
"000XXXXXXXXX" when is_x(datain(8)) else
"000100000000" when datain(8) = '1' else
"0000XXXXXXXX" when is_x(datain(7)) else
"000010000000" when datain(7) = '1' else
"00000XXXXXXX" when is_x(datain(6)) else
"000001000000" when datain(6) = '1' else
"000000XXXXXX" when is_x(datain(5)) else
"000000100000" when datain(5) = '1' else
"0000000XXXXX" when is_x(datain(4)) else
"000000010000" when datain(4) = '1' else
"00000000XXXX" when is_x(datain(3)) else
"000000001000" when datain(3) = '1' else
"000000000XXX" when is_x(datain(2)) else
"000000000100" when datain(2) = '1' else
"0000000000XX" when is_x(datain(1)) else
"000000000010" when datain(1) = '1' else
"00000000000X" when is_x(datain(0)) else
"000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_13 : if input_bits = 13 generate
dataout <= (others => 'X') when is_x(datain(12)) else
"1000000000000" when datain(12) = '1' else
"0XXXXXXXXXXXX" when is_x(datain(11)) else
"0100000000000" when datain(11) = '1' else
"00XXXXXXXXXXX" when is_x(datain(10)) else
"0010000000000" when datain(10) = '1' else
"000XXXXXXXXXX" when is_x(datain(9)) else
"0001000000000" when datain(9) = '1' else
"0000XXXXXXXXX" when is_x(datain(8)) else
"0000100000000" when datain(8) = '1' else
"00000XXXXXXXX" when is_x(datain(7)) else
"0000010000000" when datain(7) = '1' else
"000000XXXXXXX" when is_x(datain(6)) else
"0000001000000" when datain(6) = '1' else
"0000000XXXXXX" when is_x(datain(5)) else
"0000000100000" when datain(5) = '1' else
"00000000XXXXX" when is_x(datain(4)) else
"0000000010000" when datain(4) = '1' else
"000000000XXXX" when is_x(datain(3)) else
"0000000001000" when datain(3) = '1' else
"0000000000XXX" when is_x(datain(2)) else
"0000000000100" when datain(2) = '1' else
"00000000000XX" when is_x(datain(1)) else
"0000000000010" when datain(1) = '1' else
"000000000000X" when is_x(datain(0)) else
"0000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_14 : if input_bits = 14 generate
dataout <= (others => 'X') when is_x(datain(13)) else
"10000000000000" when datain(13) = '1' else
"0XXXXXXXXXXXXX" when is_x(datain(12)) else
"01000000000000" when datain(12) = '1' else
"00XXXXXXXXXXXX" when is_x(datain(11)) else
"00100000000000" when datain(11) = '1' else
"000XXXXXXXXXXX" when is_x(datain(10)) else
"00010000000000" when datain(10) = '1' else
"0000XXXXXXXXXX" when is_x(datain(9)) else
"00001000000000" when datain(9) = '1' else
"00000XXXXXXXXX" when is_x(datain(8)) else
"00000100000000" when datain(8) = '1' else
"000000XXXXXXXX" when is_x(datain(7)) else
"00000010000000" when datain(7) = '1' else
"0000000XXXXXXX" when is_x(datain(6)) else
"00000001000000" when datain(6) = '1' else
"00000000XXXXXX" when is_x(datain(5)) else
"00000000100000" when datain(5) = '1' else
"000000000XXXXX" when is_x(datain(4)) else
"00000000010000" when datain(4) = '1' else
"0000000000XXXX" when is_x(datain(3)) else
"00000000001000" when datain(3) = '1' else
"00000000000XXX" when is_x(datain(2)) else
"00000000000100" when datain(2) = '1' else
"000000000000XX" when is_x(datain(1)) else
"00000000000010" when datain(1) = '1' else
"0000000000000X" when is_x(datain(0)) else
"00000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_15 : if input_bits = 15 generate
dataout <= (others => 'X') when is_x(datain(14)) else
"100000000000000" when datain(14) = '1' else
"0XXXXXXXXXXXXXX" when is_x(datain(13)) else
"010000000000000" when datain(13) = '1' else
"00XXXXXXXXXXXXX" when is_x(datain(12)) else
"001000000000000" when datain(12) = '1' else
"000XXXXXXXXXXXX" when is_x(datain(11)) else
"000100000000000" when datain(11) = '1' else
"0000XXXXXXXXXXX" when is_x(datain(10)) else
"000010000000000" when datain(10) = '1' else
"00000XXXXXXXXXX" when is_x(datain(9)) else
"000001000000000" when datain(9) = '1' else
"000000XXXXXXXXX" when is_x(datain(8)) else
"000000100000000" when datain(8) = '1' else
"0000000XXXXXXXX" when is_x(datain(7)) else
"000000010000000" when datain(7) = '1' else
"00000000XXXXXXX" when is_x(datain(6)) else
"000000001000000" when datain(6) = '1' else
"000000000XXXXXX" when is_x(datain(5)) else
"000000000100000" when datain(5) = '1' else
"0000000000XXXXX" when is_x(datain(4)) else
"000000000010000" when datain(4) = '1' else
"00000000000XXXX" when is_x(datain(3)) else
"000000000001000" when datain(3) = '1' else
"000000000000XXX" when is_x(datain(2)) else
"000000000000100" when datain(2) = '1' else
"0000000000000XX" when is_x(datain(1)) else
"000000000000010" when datain(1) = '1' else
"00000000000000X" when is_x(datain(0)) else
"000000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_16 : if input_bits = 16 generate
dataout <= (others => 'X') when is_x(datain(15)) else
"1000000000000000" when datain(15) = '1' else
"0XXXXXXXXXXXXXXX" when is_x(datain(14)) else
"0100000000000000" when datain(14) = '1' else
"00XXXXXXXXXXXXXX" when is_x(datain(13)) else
"0010000000000000" when datain(13) = '1' else
"000XXXXXXXXXXXXX" when is_x(datain(12)) else
"0001000000000000" when datain(12) = '1' else
"0000XXXXXXXXXXXX" when is_x(datain(11)) else
"0000100000000000" when datain(11) = '1' else
"00000XXXXXXXXXXX" when is_x(datain(10)) else
"0000010000000000" when datain(10) = '1' else
"000000XXXXXXXXXX" when is_x(datain(9)) else
"0000001000000000" when datain(9) = '1' else
"0000000XXXXXXXXX" when is_x(datain(8)) else
"0000000100000000" when datain(8) = '1' else
"00000000XXXXXXXX" when is_x(datain(7)) else
"0000000010000000" when datain(7) = '1' else
"000000000XXXXXXX" when is_x(datain(6)) else
"0000000001000000" when datain(6) = '1' else
"0000000000XXXXXX" when is_x(datain(5)) else
"0000000000100000" when datain(5) = '1' else
"00000000000XXXXX" when is_x(datain(4)) else
"0000000000010000" when datain(4) = '1' else
"000000000000XXXX" when is_x(datain(3)) else
"0000000000001000" when datain(3) = '1' else
"0000000000000XXX" when is_x(datain(2)) else
"0000000000000100" when datain(2) = '1' else
"00000000000000XX" when is_x(datain(1)) else
"0000000000000010" when datain(1) = '1' else
"000000000000000X" when is_x(datain(0)) else
"0000000000000001" when datain(0) = '1' else
(others => 'X');
end generate;
input_bits_out_of_range : if input_bits > 16 generate
input_bits_out_of_rance_proc : process is
begin
assert input_bits > 16 report "input_bits is out of range" severity failure;
wait;
end process;
end generate;
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/inst/cache/replace/none/cpu_l1mem_inst_cache_replace_none.vhdl
|
1
|
1861
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Dummy Cache Replacement Algorithm for Direct-Mapped Caches
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_l1mem_inst_cache_replace_none_pkg.all;
entity cpu_l1mem_inst_cache_replace_none is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_l1mem_inst_cache_replace_none_ctrl_in : in cpu_l1mem_inst_cache_replace_none_ctrl_in_type;
cpu_l1mem_inst_cache_replace_none_dp_in : in cpu_l1mem_inst_cache_replace_none_dp_in_type;
cpu_l1mem_inst_cache_replace_none_dp_out : out cpu_l1mem_inst_cache_replace_none_dp_out_type
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/decoder-rtl.vhdl
|
1
|
1440
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of decoder is
begin
decoder : entity work.decoder_inferred(rtl)
generic map (
output_bits => output_bits
)
port map (
datain => datain,
dataout => dataout
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/inst/cache/cpu_l1mem_inst_cache_dp-rtl.vhdl
|
1
|
16870
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library tech;
library sys;
use sys.sys_config_pkg.all;
use sys.sys_pkg.all;
use work.cpu_l1mem_inst_cache_pkg.all;
use work.cpu_l1mem_inst_cache_config_pkg.all;
use work.cpu_types_pkg.all;
architecture rtl of cpu_l1mem_inst_cache_dp is
type reg_type is record
b_request_vpn : cpu_vpn_type;
b_request_poffset : cpu_ipoffset_type;
b_bus_op_paddr : cpu_ipaddr_type;
end record;
type comb_type is record
b_replace_rstate : cpu_l1mem_inst_cache_replace_state_type;
b_tram_rdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_dram_rdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
b_bus_op_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_bus_op_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_bus_op_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_ppn : cpu_ppn_type;
b_request_paddr : cpu_ipaddr_type;
b_request_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_request_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_request_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_cache_tag_match : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_request_last_in_block : std_ulogic;
b_cache_way_read_data : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
b_cache_read_data : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_inst_bus : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_inst_cache : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_paddr : cpu_ipaddr_type;
b_result_inst : cpu_inst_type;
b_replace_windex : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_replace_wstate : cpu_l1mem_inst_cache_replace_state_type;
b_vram_waddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_mram_waddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_new_request_poffset : cpu_ipoffset_type;
a_new_request_vpn : cpu_vpn_type;
a_request_poffset : cpu_ipoffset_type;
a_request_vpn : cpu_vpn_type;
a_request_ppn : cpu_ppn_type;
a_request_bus_op_data : cpu_inst_type;
a_request_vaddr : cpu_vaddr_type;
a_request_paddr : cpu_ipaddr_type;
a_request_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_request_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_request_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_paddr_block_inst_offset_next : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_paddr : cpu_ipaddr_type;
a_bus_op_size : cpu_data_size_type;
a_bus_op_data : cpu_inst_type;
a_bus_op_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_bus_op_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_cache_wtag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_bus_op_cache_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_bus_op_cache_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_tram_wdata_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_bus_op_sys_paddr : cpu_ipaddr_type;
a_bus_op_sys_data : cpu_inst_type;
a_bus_op_dram_wdata : std_ulogic_vector(cpu_inst_bits-1 downto 0);
a_sys_size : sys_transfer_size_type;
a_sys_paddr : sys_paddr_type;
a_sys_data : sys_bus_type;
a_cache_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_cache_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_vram_raddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_tram_addr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_tram_wtag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_tram_wdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_dram_addr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_dram_wdata_inst : std_ulogic_vector(cpu_inst_bits-1 downto 0);
a_dram_wdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
a_replace_rindex : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
end record;
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.b_replace_rstate <= cpu_l1mem_inst_cache_replace_dp_out.rstate;
c.b_tram_rdata <= cpu_l1mem_inst_cache_dp_in_tram.rdata;
c.b_dram_rdata <= cpu_l1mem_inst_cache_dp_in_dram.rdata;
----------------------------------
c.b_request_ppn <= cpu_mmu_inst_dp_out.ppn;
c.b_request_paddr <= c.b_request_ppn & r.b_request_poffset;
c.b_request_tag <= c.b_request_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.b_request_index <= c.b_request_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1
downto cpu_l1mem_inst_cache_offset_bits);
c.b_request_offset <= c.b_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_tag_match_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
c.b_request_cache_tag_match(n) <=
logic_eq(c.b_request_tag,
std_ulogic_vector2_slice2(c.b_tram_rdata, n));
end generate;
c.b_request_last_in_block <= all_ones(c.b_request_offset);
----------------------------------
b_cache_read_data_way_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_loop : for b in cpu_inst_bits-1 downto 0 generate
c.b_cache_way_read_data(n, b) <= c.b_dram_rdata(n, b);
end generate;
end generate;
b_cache_read_data_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_inst_bits,
sel_bits => cpu_l1mem_inst_cache_assoc
)
port map (
din => c.b_cache_way_read_data,
sel => cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_read_data_way,
dout => c.b_cache_read_data
);
----------------------------------
c.b_bus_op_tag <= r.b_bus_op_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.b_bus_op_index <= r.b_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.b_bus_op_offset <= r.b_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
----------------------------------
c.b_result_inst_bus <= sys_slave_dp_out.data(cpu_inst_bits-1 downto 0);
c.b_result_inst_cache <= c.b_cache_read_data;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_result_inst_sel select
c.b_result_inst <= c.b_result_inst_cache when cpu_l1mem_inst_cache_b_result_inst_sel_b_cache,
c.b_result_inst_bus when cpu_l1mem_inst_cache_b_result_inst_sel_b_bus,
(others => 'X') when others;
----------------------------------
with cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_owner select
c.b_replace_windex <= c.b_request_index when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
c.b_replace_wstate <= c.b_replace_rstate;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_owner select
c.b_vram_waddr <= c.b_request_index when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
--------------------------
c.a_new_request_poffset <= cpu_l1mem_inst_cache_dp_in.vaddr(cpu_ipoffset_bits-1 downto 0);
c.a_new_request_vpn <= cpu_l1mem_inst_cache_dp_in.vaddr(cpu_ivaddr_bits-1 downto cpu_ipoffset_bits);
with cpu_l1mem_inst_cache_dp_in_ctrl.b_request_complete select
c.a_request_poffset <= c.a_new_request_poffset when '1',
r.b_request_poffset when '0',
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_request_complete select
c.a_request_vpn <= c.a_new_request_vpn when '1',
r.b_request_vpn when '0',
(others => 'X') when others;
c.a_request_ppn <= c.b_request_ppn;
c.a_request_paddr <= c.a_request_ppn & c.a_request_poffset;
c.a_request_tag <= c.a_request_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.a_request_index <= c.a_request_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.a_request_offset <= c.a_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
--------------------------------
c.a_bus_op_dram_wdata <= sys_slave_dp_out.data;
a_bus_op_paddr_block_inst_offset_next_gen : if cpu_l1mem_inst_cache_offset_bits > 0 generate
c.a_bus_op_paddr_block_inst_offset_next <=
std_ulogic_vector(unsigned(r.b_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0)) +
to_unsigned(1, cpu_l1mem_inst_cache_offset_bits));
end generate;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_tag_sel select
c.a_bus_op_paddr(cpu_ipaddr_bits-1 downto cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits) <=
c.a_request_tag when cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_request,
c.b_bus_op_tag when cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_old,
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_index_sel select
c.a_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto cpu_l1mem_inst_cache_offset_bits) <=
c.a_request_index when cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_old,
(others => 'X') when others;
a_bus_op_paddr_block_inst_offset_gen : if cpu_l1mem_inst_cache_offset_bits > 0 generate
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_offset_sel select
c.a_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0) <=
c.b_bus_op_offset(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_old,
c.a_bus_op_paddr_block_inst_offset_next when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_next,
c.a_request_offset(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_request,
(others => 'X') when others;
end generate;
c.a_bus_op_index <= c.a_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.a_bus_op_offset <= c.a_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
c.a_bus_op_cache_wtag <= r.b_bus_op_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_index <=
c.a_bus_op_index when '0',
c.b_bus_op_index when '1',
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_offset <=
c.a_bus_op_offset when '0',
c.b_bus_op_offset when '1',
(others => 'X') when others;
c.a_bus_op_sys_paddr <= c.a_bus_op_paddr;
--------------------------------
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_cache_index <= c.a_request_index when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_cache_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_cache_offset <= c.a_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_cache_offset
when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
c.a_vram_raddr <= c.a_cache_index;
c.a_tram_addr <= c.a_cache_index;
c.a_tram_wtag <= c.a_bus_op_cache_wtag;
a_tram_wdata_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_gen : for b in cpu_l1mem_inst_cache_tag_bits-1 downto 0 generate
c.a_tram_wdata(n, b) <= c.a_tram_wtag(b);
end generate;
end generate;
c.a_replace_rindex <= c.a_cache_index;
c.a_dram_addr <= c.a_cache_index & c.a_cache_offset;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_dram_wdata_inst <= c.a_bus_op_dram_wdata when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
a_dram_wdata_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_loop : for b in cpu_inst_bits-1 downto 0 generate
c.a_dram_wdata(n, b) <= c.a_dram_wdata_inst(b);
end generate;
end generate;
c.a_sys_size <= std_ulogic_vector(to_unsigned(cpu_log2_inst_bytes, sys_transfer_size_bits));
c.a_sys_paddr <= (sys_paddr_bits-1 downto cpu_paddr_bits => '0') & c.a_bus_op_sys_paddr & (cpu_log2_inst_bytes-1 downto 0 => '0');
c.b_result_paddr <= r.b_bus_op_paddr;
r_next <= (
b_request_poffset => c.a_request_poffset,
b_request_vpn => c.a_request_vpn,
b_bus_op_paddr => c.a_bus_op_paddr
);
cpu_l1mem_inst_cache_dp_out_ctrl <= (
b_request_last_in_block => c.b_request_last_in_block,
b_request_cache_tag_match => c.b_request_cache_tag_match
);
cpu_l1mem_inst_cache_dp_out_vram <= (
raddr => c.a_vram_raddr,
waddr => c.b_vram_waddr
);
cpu_l1mem_inst_cache_dp_out_tram <= (
addr => c.a_tram_addr,
wdata => c.a_tram_wdata
);
cpu_l1mem_inst_cache_dp_out_dram <= (
addr => c.a_dram_addr,
wdata => c.a_dram_wdata
);
cpu_l1mem_inst_cache_replace_dp_in <= (
rindex => c.a_replace_rindex,
windex => c.b_replace_windex,
wstate => c.b_replace_wstate
);
cpu_l1mem_inst_cache_dp_out <= (
paddr => c.b_result_paddr,
data => c.b_result_inst
);
cpu_mmu_inst_dp_in <= (
vpn => c.a_request_vpn
);
sys_master_dp_out <= (
size => c.a_sys_size,
paddr => c.a_sys_paddr,
data => (others => 'X')
);
process (clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/inst/cache/replace/lru/cpu_l1mem_inst_cache_replace_lru-rtl.vhdl
|
1
|
2122
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library mem;
use work.cpu_l1mem_inst_cache_config_pkg.all;
use work.cpu_l1mem_inst_cache_replace_lru_pkg.all;
architecture rtl of cpu_l1mem_inst_cache_replace_lru is
begin
lru : entity mem.cache_replace_lru(rtl)
generic map (
log2_assoc => cpu_l1mem_inst_cache_log2_assoc,
index_bits => cpu_l1mem_inst_cache_index_bits
)
port map (
clk => clk,
rstn => rstn,
re => cpu_l1mem_inst_cache_replace_lru_ctrl_in.re,
rindex => cpu_l1mem_inst_cache_replace_lru_dp_in.rindex,
rway => cpu_l1mem_inst_cache_replace_lru_ctrl_out.rway,
rstate => cpu_l1mem_inst_cache_replace_lru_dp_out.rstate,
we => cpu_l1mem_inst_cache_replace_lru_ctrl_in.we,
windex => cpu_l1mem_inst_cache_replace_lru_dp_in.windex,
wway => cpu_l1mem_inst_cache_replace_lru_ctrl_in.wway,
wstate => cpu_l1mem_inst_cache_replace_lru_dp_in.wstate
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/inst/cache/cpu_l1mem_inst_cache.vhdl
|
1
|
2352
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_inst_pkg.all;
use work.cpu_l1mem_inst_cache_pkg.all;
entity cpu_l1mem_inst_cache is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_inst_ctrl_in : out cpu_mmu_inst_ctrl_in_type;
cpu_mmu_inst_dp_in : out cpu_mmu_inst_dp_in_type;
cpu_mmu_inst_ctrl_out : in cpu_mmu_inst_ctrl_out_type;
cpu_mmu_inst_dp_out : in cpu_mmu_inst_dp_out_type;
cpu_l1mem_inst_cache_ctrl_in : in cpu_l1mem_inst_cache_ctrl_in_type;
cpu_l1mem_inst_cache_dp_in : in cpu_l1mem_inst_cache_dp_in_type;
cpu_l1mem_inst_cache_ctrl_out : out cpu_l1mem_inst_cache_ctrl_out_type;
cpu_l1mem_inst_cache_dp_out : out cpu_l1mem_inst_cache_dp_out_type;
sys_master_ctrl_out : out sys_master_ctrl_out_type;
sys_master_dp_out : out sys_master_dp_out_type;
sys_slave_ctrl_out : in sys_slave_ctrl_out_type;
sys_slave_dp_out : in sys_slave_dp_out_type
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/mul_seq_inferred.vhdl
|
1
|
1749
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mul_seq_inferred is
generic (
latency : positive := 1;
src1_bits : natural := 32;
src2_bits : natural := 32
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
en : in std_ulogic;
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src2_bits-1 downto 0);
valid : out std_ulogic;
result : out std_ulogic_vector(src1_bits+src2_bits-1 downto 0)
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/syncram_2r1w_inferred.vhdl
|
1
|
1906
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity syncram_2r1w_inferred is
generic (
addr_bits : natural := 6;
data_bits : natural := 32;
write_first : boolean := true
);
port (
clk : in std_ulogic;
we : in std_ulogic;
waddr : in std_ulogic_vector((addr_bits-1) downto 0);
wdata : in std_ulogic_vector((data_bits-1) downto 0);
re1 : in std_ulogic;
raddr1 : in std_ulogic_vector((addr_bits-1) downto 0);
rdata1 : out std_ulogic_vector((data_bits-1) downto 0);
re2 : in std_ulogic;
raddr2 : in std_ulogic_vector((addr_bits-1) downto 0);
rdata2 : out std_ulogic_vector((data_bits-1) downto 0)
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/or1knd/i5/mmu/data/cpu_or1knd_i5_mmu_data_types_pkg.vhdl
|
2
|
2103
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package cpu_mmu_data_types_pkg is
type cpu_mmu_data_result_code_index_type is (
cpu_mmu_data_result_code_index_valid,
cpu_mmu_data_result_code_index_error,
cpu_mmu_data_result_code_index_tlbmiss,
cpu_mmu_data_result_code_index_pf
);
type cpu_mmu_data_result_code_type is
array (cpu_mmu_data_result_code_index_type range
cpu_mmu_data_result_code_index_type'high downto
cpu_mmu_data_result_code_index_type'low) of std_ulogic;
constant cpu_mmu_data_result_code_valid : cpu_mmu_data_result_code_type := "0001";
constant cpu_mmu_data_result_code_error : cpu_mmu_data_result_code_type := "0010";
constant cpu_mmu_data_result_code_tlbmiss : cpu_mmu_data_result_code_type := "0100";
constant cpu_mmu_data_result_code_pf : cpu_mmu_data_result_code_type := "1000";
end package;
|
apache-2.0
|
smithe0/GestureControlInterface
|
DE2Component_FLASH/niosII_system/synthesis/niosII_system.vhd
|
1
|
877260
|
-- niosII_system.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosII_system is
port (
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
green_leds_external_connection_export : out std_logic_vector(7 downto 0); -- green_leds_external_connection.export
switches_external_connection_export : in std_logic_vector(7 downto 0) := (others => '0'); -- switches_external_connection.export
sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- sdram_0_wire.addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_0_wire_cas_n : out std_logic; -- .cas_n
sdram_0_wire_cke : out std_logic; -- .cke
sdram_0_wire_cs_n : out std_logic; -- .cs_n
sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_0_wire_ras_n : out std_logic; -- .ras_n
sdram_0_wire_we_n : out std_logic; -- .we_n
sram_0_external_interface_DQ : inout std_logic_vector(15 downto 0) := (others => '0'); -- sram_0_external_interface.DQ
sram_0_external_interface_ADDR : out std_logic_vector(17 downto 0); -- .ADDR
sram_0_external_interface_LB_N : out std_logic; -- .LB_N
sram_0_external_interface_UB_N : out std_logic; -- .UB_N
sram_0_external_interface_CE_N : out std_logic; -- .CE_N
sram_0_external_interface_OE_N : out std_logic; -- .OE_N
sram_0_external_interface_WE_N : out std_logic; -- .WE_N
altpll_0_c0_clk : out std_logic; -- altpll_0_c0.clk
usb_0_external_interface_INT1 : in std_logic := '0'; -- usb_0_external_interface.INT1
usb_0_external_interface_DATA : inout std_logic_vector(15 downto 0) := (others => '0'); -- .DATA
usb_0_external_interface_RST_N : out std_logic; -- .RST_N
usb_0_external_interface_ADDR : out std_logic_vector(1 downto 0); -- .ADDR
usb_0_external_interface_CS_N : out std_logic; -- .CS_N
usb_0_external_interface_RD_N : out std_logic; -- .RD_N
usb_0_external_interface_WR_N : out std_logic; -- .WR_N
usb_0_external_interface_INT0 : in std_logic := '0'; -- .INT0
rs232_0_external_interface_RXD : in std_logic := '0'; -- rs232_0_external_interface.RXD
rs232_0_external_interface_TXD : out std_logic; -- .TXD
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- tristate_conduit_bridge_0_out.generic_tristate_controller_0_tcm_read_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => '0'); -- .generic_tristate_controller_0_tcm_data_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_chipselect_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_write_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_byteenable_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_begintransfer_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- .generic_tristate_controller_0_tcm_address_out
);
end entity niosII_system;
architecture rtl of niosII_system is
component niosII_system_nios2_qsys_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(24 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_debug_module_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(24 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
d_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
jtag_debug_module_resetrequest : out std_logic; -- reset
jtag_debug_module_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
jtag_debug_module_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
jtag_debug_module_debugaccess : in std_logic := 'X'; -- debugaccess
jtag_debug_module_read : in std_logic := 'X'; -- read
jtag_debug_module_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_debug_module_waitrequest : out std_logic; -- waitrequest
jtag_debug_module_write : in std_logic := 'X'; -- write
jtag_debug_module_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
no_ci_readra : out std_logic -- readra
);
end component niosII_system_nios2_qsys_0;
component niosII_system_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosII_system_onchip_memory2_0;
component niosII_system_sysid_qsys_0 is
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X' -- address
);
end component niosII_system_sysid_qsys_0;
component niosII_system_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosII_system_jtag_uart_0;
component niosII_system_green_leds is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosII_system_green_leds;
component niosII_system_switches is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component niosII_system_switches;
component niosII_system_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component niosII_system_altpll_0;
component niosII_system_sdram_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(21 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(11 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component niosII_system_sdram_0;
component niosII_system_sram_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
SRAM_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
SRAM_ADDR : out std_logic_vector(17 downto 0); -- export
SRAM_LB_N : out std_logic; -- export
SRAM_UB_N : out std_logic; -- export
SRAM_CE_N : out std_logic; -- export
SRAM_OE_N : out std_logic; -- export
SRAM_WE_N : out std_logic; -- export
address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
readdatavalid : out std_logic -- readdatavalid
);
end component niosII_system_sram_0;
component niosII_system_timer_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosII_system_timer_0;
component niosII_system_usb_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
irq : out std_logic; -- irq
OTG_INT1 : in std_logic := 'X'; -- export
OTG_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
OTG_RST_N : out std_logic; -- export
OTG_ADDR : out std_logic_vector(1 downto 0); -- export
OTG_CS_N : out std_logic; -- export
OTG_RD_N : out std_logic; -- export
OTG_WR_N : out std_logic; -- export
OTG_INT0 : in std_logic := 'X' -- export
);
end component niosII_system_usb_0;
component niosII_system_rs232_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic := 'X'; -- address
chipselect : in std_logic := 'X'; -- chipselect
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(31 downto 0); -- readdata
irq : out std_logic; -- irq
UART_RXD : in std_logic := 'X'; -- export
UART_TXD : out std_logic -- export
);
end component niosII_system_rs232_0;
component niosII_system_generic_tristate_controller_0 is
generic (
TCM_ADDRESS_W : integer := 30;
TCM_DATA_W : integer := 32;
TCM_BYTEENABLE_W : integer := 4;
TCM_READ_WAIT : integer := 1;
TCM_WRITE_WAIT : integer := 0;
TCM_SETUP_WAIT : integer := 0;
TCM_DATA_HOLD : integer := 0;
TCM_TURNAROUND_TIME : integer := 2;
TCM_TIMING_UNITS : integer := 1;
TCM_READLATENCY : integer := 2;
TCM_SYMBOLS_PER_WORD : integer := 4;
USE_READDATA : integer := 1;
USE_WRITEDATA : integer := 1;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BYTEENABLE : integer := 1;
USE_CHIPSELECT : integer := 0;
USE_LOCK : integer := 0;
USE_ADDRESS : integer := 1;
USE_WAITREQUEST : integer := 0;
USE_WRITEBYTEENABLE : integer := 0;
USE_OUTPUTENABLE : integer := 0;
USE_RESETREQUEST : integer := 0;
USE_IRQ : integer := 0;
USE_RESET_OUTPUT : integer := 0;
ACTIVE_LOW_READ : integer := 0;
ACTIVE_LOW_LOCK : integer := 0;
ACTIVE_LOW_WRITE : integer := 0;
ACTIVE_LOW_CHIPSELECT : integer := 0;
ACTIVE_LOW_BYTEENABLE : integer := 0;
ACTIVE_LOW_OUTPUTENABLE : integer := 0;
ACTIVE_LOW_WRITEBYTEENABLE : integer := 0;
ACTIVE_LOW_WAITREQUEST : integer := 0;
ACTIVE_LOW_BEGINTRANSFER : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0
);
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset : in std_logic := 'X'; -- reset
uas_address : in std_logic_vector(21 downto 0) := (others => 'X'); -- address
uas_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
uas_read : in std_logic := 'X'; -- read
uas_write : in std_logic := 'X'; -- write
uas_waitrequest : out std_logic; -- waitrequest
uas_readdatavalid : out std_logic; -- readdatavalid
uas_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
uas_readdata : out std_logic_vector(7 downto 0); -- readdata
uas_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
uas_lock : in std_logic := 'X'; -- lock
uas_debugaccess : in std_logic := 'X'; -- debugaccess
tcm_write_n_out : out std_logic; -- write_n_out
tcm_read_n_out : out std_logic; -- read_n_out
tcm_begintransfer_out : out std_logic; -- begintransfer_out
tcm_chipselect_n_out : out std_logic; -- chipselect_n_out
tcm_request : out std_logic; -- request
tcm_grant : in std_logic := 'X'; -- grant
tcm_address_out : out std_logic_vector(21 downto 0); -- address_out
tcm_byteenable_out : out std_logic; -- byteenable_out
tcm_data_out : out std_logic_vector(7 downto 0); -- data_out
tcm_data_outen : out std_logic; -- data_outen
tcm_data_in : in std_logic_vector(7 downto 0) := (others => 'X') -- data_in
);
end component niosII_system_generic_tristate_controller_0;
component niosII_system_tristate_conduit_bridge_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
request : in std_logic := 'X'; -- request
grant : out std_logic; -- grant
tcs_generic_tristate_controller_0_tcm_read_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_read_n_out_out
tcs_generic_tristate_controller_0_tcm_data_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out_out
tcs_generic_tristate_controller_0_tcm_data_outen : in std_logic := 'X'; -- generic_tristate_controller_0_tcm_data_out_outen
tcs_generic_tristate_controller_0_tcm_data_in : out std_logic_vector(7 downto 0); -- generic_tristate_controller_0_tcm_data_out_in
tcs_generic_tristate_controller_0_tcm_chipselect_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_chipselect_n_out_out
tcs_generic_tristate_controller_0_tcm_write_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_write_n_out_out
tcs_generic_tristate_controller_0_tcm_byteenable_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_byteenable_out_out
tcs_generic_tristate_controller_0_tcm_begintransfer_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_begintransfer_out_out
tcs_generic_tristate_controller_0_tcm_address_out : in std_logic_vector(21 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_address_out_out
generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out
generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out
generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out
generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out
generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_byteenable_out
generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_begintransfer_out
generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- generic_tristate_controller_0_tcm_address_out
);
end component niosII_system_tristate_conduit_bridge_0;
component niosII_system_tristate_conduit_pin_sharer_0 is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset : in std_logic := 'X'; -- reset
request : out std_logic; -- request
grant : in std_logic := 'X'; -- grant
generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_byteenable_out_out
generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0); -- generic_tristate_controller_0_tcm_address_out_out
generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out_out
generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out_out
generic_tristate_controller_0_tcm_data_out : out std_logic_vector(7 downto 0); -- generic_tristate_controller_0_tcm_data_out_out
generic_tristate_controller_0_tcm_data_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out_in
generic_tristate_controller_0_tcm_data_outen : out std_logic; -- generic_tristate_controller_0_tcm_data_out_outen
generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out_out
generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_begintransfer_out_out
tcs0_request : in std_logic := 'X'; -- request
tcs0_grant : out std_logic; -- grant
tcs0_byteenable_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable_out
tcs0_address_out : in std_logic_vector(21 downto 0) := (others => 'X'); -- address_out
tcs0_read_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- read_n_out
tcs0_write_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- write_n_out
tcs0_data_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- data_out
tcs0_data_in : out std_logic_vector(7 downto 0); -- data_in
tcs0_data_outen : in std_logic := 'X'; -- data_outen
tcs0_chipselect_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- chipselect_n_out
tcs0_begintransfer_out : in std_logic_vector(0 downto 0) := (others => 'X') -- begintransfer_out
);
end component niosII_system_tristate_conduit_pin_sharer_0;
component altera_merlin_master_agent is
generic (
PKT_PROTECTION_H : integer := 80;
PKT_PROTECTION_L : integer := 80;
PKT_BEGIN_BURST : integer := 81;
PKT_BURSTWRAP_H : integer := 79;
PKT_BURSTWRAP_L : integer := 77;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 94;
PKT_BURST_TYPE_L : integer := 93;
PKT_BYTE_CNT_H : integer := 76;
PKT_BYTE_CNT_L : integer := 74;
PKT_ADDR_H : integer := 73;
PKT_ADDR_L : integer := 42;
PKT_TRANS_COMPRESSED_READ : integer := 41;
PKT_TRANS_POSTED : integer := 40;
PKT_TRANS_WRITE : integer := 39;
PKT_TRANS_READ : integer := 38;
PKT_TRANS_LOCK : integer := 82;
PKT_TRANS_EXCLUSIVE : integer := 83;
PKT_DATA_H : integer := 37;
PKT_DATA_L : integer := 6;
PKT_BYTEEN_H : integer := 5;
PKT_BYTEEN_L : integer := 2;
PKT_SRC_ID_H : integer := 1;
PKT_SRC_ID_L : integer := 1;
PKT_DEST_ID_H : integer := 0;
PKT_DEST_ID_L : integer := 0;
PKT_THREAD_ID_H : integer := 88;
PKT_THREAD_ID_L : integer := 87;
PKT_CACHE_H : integer := 92;
PKT_CACHE_L : integer := 89;
PKT_DATA_SIDEBAND_H : integer := 105;
PKT_DATA_SIDEBAND_L : integer := 98;
PKT_QOS_H : integer := 109;
PKT_QOS_L : integer := 106;
PKT_ADDR_SIDEBAND_H : integer := 97;
PKT_ADDR_SIDEBAND_L : integer := 93;
PKT_RESPONSE_STATUS_H : integer := 111;
PKT_RESPONSE_STATUS_L : integer := 110;
ST_DATA_W : integer := 112;
ST_CHANNEL_W : integer := 1;
AV_BURSTCOUNT_W : integer := 3;
SUPPRESS_0_BYTEEN_RSP : integer := 1;
ID : integer := 1;
BURSTWRAP_VALUE : integer := 4;
CACHE_VALUE : integer := 0;
SECURE_ACCESS_BIT : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(99 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic; -- ready
av_response : out std_logic_vector(1 downto 0); -- response
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_agent;
component niosII_system_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_addr_router;
component niosII_system_addr_router_001 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_addr_router_001;
component niosII_system_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_id_router;
component niosII_system_id_router_001 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(81 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_id_router_001;
component niosII_system_id_router_004 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(72 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_id_router_004;
component niosII_system_id_router_005 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_id_router_005;
component niosII_system_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(99 downto 0); -- data
src2_channel : out std_logic_vector(12 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(99 downto 0); -- data
src3_channel : out std_logic_vector(12 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(99 downto 0); -- data
src4_channel : out std_logic_vector(12 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_cmd_xbar_demux;
component niosII_system_cmd_xbar_demux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(99 downto 0); -- data
src2_channel : out std_logic_vector(12 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(99 downto 0); -- data
src3_channel : out std_logic_vector(12 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(99 downto 0); -- data
src4_channel : out std_logic_vector(12 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(99 downto 0); -- data
src5_channel : out std_logic_vector(12 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic; -- endofpacket
src6_ready : in std_logic := 'X'; -- ready
src6_valid : out std_logic; -- valid
src6_data : out std_logic_vector(99 downto 0); -- data
src6_channel : out std_logic_vector(12 downto 0); -- channel
src6_startofpacket : out std_logic; -- startofpacket
src6_endofpacket : out std_logic; -- endofpacket
src7_ready : in std_logic := 'X'; -- ready
src7_valid : out std_logic; -- valid
src7_data : out std_logic_vector(99 downto 0); -- data
src7_channel : out std_logic_vector(12 downto 0); -- channel
src7_startofpacket : out std_logic; -- startofpacket
src7_endofpacket : out std_logic; -- endofpacket
src8_ready : in std_logic := 'X'; -- ready
src8_valid : out std_logic; -- valid
src8_data : out std_logic_vector(99 downto 0); -- data
src8_channel : out std_logic_vector(12 downto 0); -- channel
src8_startofpacket : out std_logic; -- startofpacket
src8_endofpacket : out std_logic; -- endofpacket
src9_ready : in std_logic := 'X'; -- ready
src9_valid : out std_logic; -- valid
src9_data : out std_logic_vector(99 downto 0); -- data
src9_channel : out std_logic_vector(12 downto 0); -- channel
src9_startofpacket : out std_logic; -- startofpacket
src9_endofpacket : out std_logic; -- endofpacket
src10_ready : in std_logic := 'X'; -- ready
src10_valid : out std_logic; -- valid
src10_data : out std_logic_vector(99 downto 0); -- data
src10_channel : out std_logic_vector(12 downto 0); -- channel
src10_startofpacket : out std_logic; -- startofpacket
src10_endofpacket : out std_logic; -- endofpacket
src11_ready : in std_logic := 'X'; -- ready
src11_valid : out std_logic; -- valid
src11_data : out std_logic_vector(99 downto 0); -- data
src11_channel : out std_logic_vector(12 downto 0); -- channel
src11_startofpacket : out std_logic; -- startofpacket
src11_endofpacket : out std_logic; -- endofpacket
src12_ready : in std_logic := 'X'; -- ready
src12_valid : out std_logic; -- valid
src12_data : out std_logic_vector(99 downto 0); -- data
src12_channel : out std_logic_vector(12 downto 0); -- channel
src12_startofpacket : out std_logic; -- startofpacket
src12_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_cmd_xbar_demux_001;
component niosII_system_cmd_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X' -- endofpacket
);
end component niosII_system_cmd_xbar_mux;
component niosII_system_rsp_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_rsp_xbar_demux;
component niosII_system_rsp_xbar_demux_005 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component niosII_system_rsp_xbar_demux_005;
component niosII_system_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X' -- endofpacket
);
end component niosII_system_rsp_xbar_mux;
component niosII_system_rsp_xbar_mux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X'; -- endofpacket
sink6_ready : out std_logic; -- ready
sink6_valid : in std_logic := 'X'; -- valid
sink6_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink6_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink6_startofpacket : in std_logic := 'X'; -- startofpacket
sink6_endofpacket : in std_logic := 'X'; -- endofpacket
sink7_ready : out std_logic; -- ready
sink7_valid : in std_logic := 'X'; -- valid
sink7_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink7_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink7_startofpacket : in std_logic := 'X'; -- startofpacket
sink7_endofpacket : in std_logic := 'X'; -- endofpacket
sink8_ready : out std_logic; -- ready
sink8_valid : in std_logic := 'X'; -- valid
sink8_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink8_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink8_startofpacket : in std_logic := 'X'; -- startofpacket
sink8_endofpacket : in std_logic := 'X'; -- endofpacket
sink9_ready : out std_logic; -- ready
sink9_valid : in std_logic := 'X'; -- valid
sink9_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink9_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink9_startofpacket : in std_logic := 'X'; -- startofpacket
sink9_endofpacket : in std_logic := 'X'; -- endofpacket
sink10_ready : out std_logic; -- ready
sink10_valid : in std_logic := 'X'; -- valid
sink10_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink10_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink10_startofpacket : in std_logic := 'X'; -- startofpacket
sink10_endofpacket : in std_logic := 'X'; -- endofpacket
sink11_ready : out std_logic; -- ready
sink11_valid : in std_logic := 'X'; -- valid
sink11_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink11_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink11_startofpacket : in std_logic := 'X'; -- startofpacket
sink11_endofpacket : in std_logic := 'X'; -- endofpacket
sink12_ready : out std_logic; -- ready
sink12_valid : in std_logic := 'X'; -- valid
sink12_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink12_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink12_startofpacket : in std_logic := 'X'; -- startofpacket
sink12_endofpacket : in std_logic := 'X' -- endofpacket
);
end component niosII_system_rsp_xbar_mux_001;
component altera_avalon_st_handshake_clock_crosser is
generic (
DATA_WIDTH : integer := 8;
BITS_PER_SYMBOL : integer := 8;
USE_PACKETS : integer := 0;
USE_CHANNEL : integer := 0;
CHANNEL_WIDTH : integer := 1;
USE_ERROR : integer := 0;
ERROR_WIDTH : integer := 1;
VALID_SYNC_DEPTH : integer := 2;
READY_SYNC_DEPTH : integer := 2;
USE_OUTPUT_PIPELINE : integer := 1
);
port (
in_clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_clk : in std_logic := 'X'; -- clk
out_reset : in std_logic := 'X'; -- reset
in_ready : out std_logic; -- ready
in_valid : in std_logic := 'X'; -- valid
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_ready : in std_logic := 'X'; -- ready
out_valid : out std_logic; -- valid
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
out_channel : out std_logic_vector(12 downto 0); -- channel
out_data : out std_logic_vector(99 downto 0); -- data
in_empty : in std_logic := 'X'; -- empty
in_error : in std_logic := 'X'; -- error
out_empty : out std_logic; -- empty
out_error : out std_logic -- error
);
end component altera_avalon_st_handshake_clock_crosser;
component niosII_system_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosII_system_irq_mapper;
component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(100 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo;
component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(82 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo;
component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(17 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(17 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo;
component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(73 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo;
component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(9 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(9 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo;
component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(33 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo;
component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(33 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent;
component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(15 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(81 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(82 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(17 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(17 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent;
component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(0 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(0 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(7 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(72 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(73 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(9 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(9 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent;
component niosii_system_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(81 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component niosii_system_width_adapter;
component niosii_system_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component niosii_system_width_adapter_001;
component niosii_system_width_adapter_004 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(72 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component niosii_system_width_adapter_004;
component niosii_system_width_adapter_005 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component niosii_system_width_adapter_005;
component niosii_system_nios2_qsys_0_instruction_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_lock : in std_logic := 'X'; -- lock
av_debugaccess : in std_logic := 'X'; -- debugaccess
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component niosii_system_nios2_qsys_0_instruction_master_translator;
component niosii_system_nios2_qsys_0_data_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_lock : in std_logic := 'X'; -- lock
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component niosii_system_nios2_qsys_0_data_master_translator;
component niosii_system_burst_adapter is
generic (
PKT_ADDR_H : integer := 79;
PKT_ADDR_L : integer := 48;
PKT_BEGIN_BURST : integer := 81;
PKT_BYTE_CNT_H : integer := 5;
PKT_BYTE_CNT_L : integer := 0;
PKT_BYTEEN_H : integer := 83;
PKT_BYTEEN_L : integer := 80;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 88;
PKT_BURST_TYPE_L : integer := 87;
PKT_BURSTWRAP_H : integer := 11;
PKT_BURSTWRAP_L : integer := 6;
PKT_TRANS_COMPRESSED_READ : integer := 14;
PKT_TRANS_WRITE : integer := 13;
PKT_TRANS_READ : integer := 12;
OUT_NARROW_SIZE : integer := 0;
IN_NARROW_SIZE : integer := 0;
OUT_FIXED : integer := 0;
OUT_COMPLETE_WRAP : integer := 0;
ST_DATA_W : integer := 89;
ST_CHANNEL_W : integer := 8;
OUT_BYTE_CNT_H : integer := 5;
OUT_BURSTWRAP_H : integer := 11;
COMPRESSED_READ_SUPPORT : integer := 1;
BYTEENABLE_SYNTHESIS : integer := 0;
PIPE_INPUTS : integer := 0;
NO_WRAP_SUPPORT : integer := 0;
BURSTWRAP_CONST_MASK : integer := 0;
BURSTWRAP_CONST_VALUE : integer := -1
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(81 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component niosii_system_burst_adapter;
component niosii_system_burst_adapter_002 is
generic (
PKT_ADDR_H : integer := 79;
PKT_ADDR_L : integer := 48;
PKT_BEGIN_BURST : integer := 81;
PKT_BYTE_CNT_H : integer := 5;
PKT_BYTE_CNT_L : integer := 0;
PKT_BYTEEN_H : integer := 83;
PKT_BYTEEN_L : integer := 80;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 88;
PKT_BURST_TYPE_L : integer := 87;
PKT_BURSTWRAP_H : integer := 11;
PKT_BURSTWRAP_L : integer := 6;
PKT_TRANS_COMPRESSED_READ : integer := 14;
PKT_TRANS_WRITE : integer := 13;
PKT_TRANS_READ : integer := 12;
OUT_NARROW_SIZE : integer := 0;
IN_NARROW_SIZE : integer := 0;
OUT_FIXED : integer := 0;
OUT_COMPLETE_WRAP : integer := 0;
ST_DATA_W : integer := 89;
ST_CHANNEL_W : integer := 8;
OUT_BYTE_CNT_H : integer := 5;
OUT_BURSTWRAP_H : integer := 11;
COMPRESSED_READ_SUPPORT : integer := 1;
BYTEENABLE_SYNTHESIS : integer := 0;
PIPE_INPUTS : integer := 0;
NO_WRAP_SUPPORT : integer := 0;
BURSTWRAP_CONST_MASK : integer := 0;
BURSTWRAP_CONST_VALUE : integer := -1
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(72 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component niosii_system_burst_adapter_002;
component niosii_system_nios2_qsys_0_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_debugaccess : out std_logic; -- debugaccess
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_nios2_qsys_0_jtag_debug_module_translator;
component niosii_system_sdram_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_sdram_0_s1_translator;
component niosii_system_onchip_memory2_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_onchip_memory2_0_s1_translator;
component niosii_system_sram_0_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_sram_0_avalon_sram_slave_translator;
component niosii_system_generic_tristate_controller_0_uas_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(7 downto 0); -- readdata
uav_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(7 downto 0); -- writedata
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_lock : out std_logic; -- lock
av_debugaccess : out std_logic; -- debugaccess
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_generic_tristate_controller_0_uas_translator;
component niosii_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_jtag_uart_0_avalon_jtag_slave_translator;
component niosii_system_sysid_qsys_0_control_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_sysid_qsys_0_control_slave_translator;
component niosii_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_green_leds_s1_translator;
component niosii_system_switches_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_switches_s1_translator;
component niosii_system_altpll_0_pll_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_altpll_0_pll_slave_translator;
component niosii_system_timer_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(2 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_timer_0_s1_translator;
component niosii_system_usb_0_avalon_usb_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_usb_0_avalon_usb_slave_translator;
component niosii_system_rs232_0_avalon_rs232_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component niosii_system_rs232_0_avalon_rs232_slave_translator;
component niosii_system_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component niosii_system_rst_controller;
component niosii_system_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component niosii_system_rst_controller_001;
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [addr_router:clk, addr_router_001:clk, burst_adapter:clk, burst_adapter_001:clk, burst_adapter_002:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, cmd_xbar_mux_004:clk, crosser:in_clk, crosser_001:out_clk, generic_tristate_controller_0:clk_clk, generic_tristate_controller_0_uas_translator:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, green_leds:clk, green_leds_s1_translator:clk, green_leds_s1_translator_avalon_universal_slave_0_agent:clk, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, id_router_008:clk, id_router_010:clk, id_router_011:clk, id_router_012:clk, irq_mapper:clk, jtag_uart_0:clk, jtag_uart_0_avalon_jtag_slave_translator:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, nios2_qsys_0:clk, nios2_qsys_0_data_master_translator:clk, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_instruction_master_translator:clk, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, onchip_memory2_0:clk, onchip_memory2_0_s1_translator:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rs232_0:clk, rs232_0_avalon_rs232_slave_translator:clk, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:clk, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_demux_008:clk, rsp_xbar_demux_010:clk, rsp_xbar_demux_011:clk, rsp_xbar_demux_012:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sram_0:clk, sram_0_avalon_sram_slave_translator:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switches:clk, switches_s1_translator:clk, switches_s1_translator_avalon_universal_slave_0_agent:clk, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid_qsys_0:clock, sysid_qsys_0_control_slave_translator:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, timer_0:clk, timer_0_s1_translator:clk, timer_0_s1_translator_avalon_universal_slave_0_agent:clk, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, tristate_conduit_bridge_0:clk, tristate_conduit_pin_sharer_0:clk_clk, usb_0:clk, usb_0_avalon_usb_slave_translator:clk, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:clk, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk]
signal generic_tristate_controller_0_tcm_chipselect_n_out : std_logic; -- generic_tristate_controller_0:tcm_chipselect_n_out -> tristate_conduit_pin_sharer_0:tcs0_chipselect_n_out
signal generic_tristate_controller_0_tcm_grant : std_logic; -- tristate_conduit_pin_sharer_0:tcs0_grant -> generic_tristate_controller_0:tcm_grant
signal generic_tristate_controller_0_tcm_data_outen : std_logic; -- generic_tristate_controller_0:tcm_data_outen -> tristate_conduit_pin_sharer_0:tcs0_data_outen
signal generic_tristate_controller_0_tcm_byteenable_out : std_logic; -- generic_tristate_controller_0:tcm_byteenable_out -> tristate_conduit_pin_sharer_0:tcs0_byteenable_out
signal generic_tristate_controller_0_tcm_request : std_logic; -- generic_tristate_controller_0:tcm_request -> tristate_conduit_pin_sharer_0:tcs0_request
signal generic_tristate_controller_0_tcm_begintransfer_out : std_logic; -- generic_tristate_controller_0:tcm_begintransfer_out -> tristate_conduit_pin_sharer_0:tcs0_begintransfer_out
signal generic_tristate_controller_0_tcm_data_out : std_logic_vector(7 downto 0); -- generic_tristate_controller_0:tcm_data_out -> tristate_conduit_pin_sharer_0:tcs0_data_out
signal generic_tristate_controller_0_tcm_write_n_out : std_logic; -- generic_tristate_controller_0:tcm_write_n_out -> tristate_conduit_pin_sharer_0:tcs0_write_n_out
signal generic_tristate_controller_0_tcm_address_out : std_logic_vector(21 downto 0); -- generic_tristate_controller_0:tcm_address_out -> tristate_conduit_pin_sharer_0:tcs0_address_out
signal generic_tristate_controller_0_tcm_data_in : std_logic_vector(7 downto 0); -- tristate_conduit_pin_sharer_0:tcs0_data_in -> generic_tristate_controller_0:tcm_data_in
signal generic_tristate_controller_0_tcm_read_n_out : std_logic; -- generic_tristate_controller_0:tcm_read_n_out -> tristate_conduit_pin_sharer_0:tcs0_read_n_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_read_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_read_n_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_byteenable_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_byteenable_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_begintransfer_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_begintransfer_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_write_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_write_n_out
signal tristate_conduit_pin_sharer_0_tcm_grant : std_logic; -- tristate_conduit_bridge_0:grant -> tristate_conduit_pin_sharer_0:grant
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in : std_logic_vector(7 downto 0); -- tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_in -> tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_in
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out : std_logic_vector(7 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_out
signal tristate_conduit_pin_sharer_0_tcm_request : std_logic; -- tristate_conduit_pin_sharer_0:request -> tristate_conduit_bridge_0:request
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_chipselect_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_chipselect_n_out
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen : std_logic; -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_outen -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_outen
signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out : std_logic_vector(21 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_address_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_address_out
signal nios2_qsys_0_instruction_master_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator:av_waitrequest -> nios2_qsys_0:i_waitrequest
signal nios2_qsys_0_instruction_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:i_address -> nios2_qsys_0_instruction_master_translator:av_address
signal nios2_qsys_0_instruction_master_read : std_logic; -- nios2_qsys_0:i_read -> nios2_qsys_0_instruction_master_translator:av_read
signal nios2_qsys_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:av_readdata -> nios2_qsys_0:i_readdata
signal nios2_qsys_0_data_master_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator:av_waitrequest -> nios2_qsys_0:d_waitrequest
signal nios2_qsys_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0:d_writedata -> nios2_qsys_0_data_master_translator:av_writedata
signal nios2_qsys_0_data_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:d_address -> nios2_qsys_0_data_master_translator:av_address
signal nios2_qsys_0_data_master_write : std_logic; -- nios2_qsys_0:d_write -> nios2_qsys_0_data_master_translator:av_write
signal nios2_qsys_0_data_master_read : std_logic; -- nios2_qsys_0:d_read -> nios2_qsys_0_data_master_translator:av_read
signal nios2_qsys_0_data_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:av_readdata -> nios2_qsys_0:d_readdata
signal nios2_qsys_0_data_master_debugaccess : std_logic; -- nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_0_data_master_translator:av_debugaccess
signal nios2_qsys_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0:d_byteenable -> nios2_qsys_0_data_master_translator:av_byteenable
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest : std_logic; -- nios2_qsys_0:jtag_debug_module_waitrequest -> nios2_qsys_0_jtag_debug_module_translator:av_waitrequest
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_writedata -> nios2_qsys_0:jtag_debug_module_writedata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address : std_logic_vector(8 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_address -> nios2_qsys_0:jtag_debug_module_address
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_write -> nios2_qsys_0:jtag_debug_module_write
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_read -> nios2_qsys_0:jtag_debug_module_read
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0:jtag_debug_module_readdata -> nios2_qsys_0_jtag_debug_module_translator:av_readdata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
signal sdram_0_s1_translator_avalon_anti_slave_0_waitrequest : std_logic; -- sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
signal sdram_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:av_writedata -> sdram_0:az_data
signal sdram_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(21 downto 0); -- sdram_0_s1_translator:av_address -> sdram_0:az_addr
signal sdram_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
signal sdram_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- sdram_0_s1_translator:av_write -> sdram_0_s1_translator_avalon_anti_slave_0_write:in
signal sdram_0_s1_translator_avalon_anti_slave_0_read : std_logic; -- sdram_0_s1_translator:av_read -> sdram_0_s1_translator_avalon_anti_slave_0_read:in
signal sdram_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sdram_0:za_data -> sdram_0_s1_translator:av_readdata
signal sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator:av_byteenable -> sdram_0_s1_translator_avalon_anti_slave_0_byteenable:in
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(11 downto 0); -- onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken : std_logic; -- onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:av_writedata -> sram_0:writedata
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator:av_address -> sram_0:address
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write : std_logic; -- sram_0_avalon_sram_slave_translator:av_write -> sram_0:write
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read : std_logic; -- sram_0_avalon_sram_slave_translator:av_read -> sram_0:read
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sram_0:readdata -> sram_0_avalon_sram_slave_translator:av_readdata
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sram_0:readdatavalid -> sram_0_avalon_sram_slave_translator:av_readdatavalid
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator:av_byteenable -> sram_0:byteenable
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest : std_logic; -- generic_tristate_controller_0:uas_waitrequest -> generic_tristate_controller_0_uas_translator:av_waitrequest
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator:av_burstcount -> generic_tristate_controller_0:uas_burstcount
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator:av_writedata -> generic_tristate_controller_0:uas_writedata
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address : std_logic_vector(21 downto 0); -- generic_tristate_controller_0_uas_translator:av_address -> generic_tristate_controller_0:uas_address
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock : std_logic; -- generic_tristate_controller_0_uas_translator:av_lock -> generic_tristate_controller_0:uas_lock
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write : std_logic; -- generic_tristate_controller_0_uas_translator:av_write -> generic_tristate_controller_0:uas_write
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read : std_logic; -- generic_tristate_controller_0_uas_translator:av_read -> generic_tristate_controller_0:uas_read
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0:uas_readdata -> generic_tristate_controller_0_uas_translator:av_readdata
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess : std_logic; -- generic_tristate_controller_0_uas_translator:av_debugaccess -> generic_tristate_controller_0:uas_debugaccess
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- generic_tristate_controller_0:uas_readdatavalid -> generic_tristate_controller_0_uas_translator:av_readdatavalid
signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator:av_byteenable -> generic_tristate_controller_0:uas_byteenable
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:in
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:in
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
signal green_leds_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:av_writedata -> green_leds:writedata
signal green_leds_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- green_leds_s1_translator:av_address -> green_leds:address
signal green_leds_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- green_leds_s1_translator:av_chipselect -> green_leds:chipselect
signal green_leds_s1_translator_avalon_anti_slave_0_write : std_logic; -- green_leds_s1_translator:av_write -> green_leds_s1_translator_avalon_anti_slave_0_write:in
signal green_leds_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- green_leds:readdata -> green_leds_s1_translator:av_readdata
signal switches_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- switches_s1_translator:av_address -> switches:address
signal switches_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- switches:readdata -> switches_s1_translator:av_readdata
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:av_writedata -> altpll_0:writedata
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- altpll_0_pll_slave_translator:av_address -> altpll_0:address
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_write : std_logic; -- altpll_0_pll_slave_translator:av_write -> altpll_0:write
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_read : std_logic; -- altpll_0_pll_slave_translator:av_read -> altpll_0:read
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> altpll_0_pll_slave_translator:av_readdata
signal timer_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- timer_0_s1_translator:av_writedata -> timer_0:writedata
signal timer_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(2 downto 0); -- timer_0_s1_translator:av_address -> timer_0:address
signal timer_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- timer_0_s1_translator:av_chipselect -> timer_0:chipselect
signal timer_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- timer_0_s1_translator:av_write -> timer_0_s1_translator_avalon_anti_slave_0_write:in
signal timer_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- timer_0:readdata -> timer_0_s1_translator:av_readdata
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- usb_0_avalon_usb_slave_translator:av_writedata -> usb_0:writedata
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- usb_0_avalon_usb_slave_translator:av_address -> usb_0:address
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- usb_0_avalon_usb_slave_translator:av_chipselect -> usb_0:chipselect
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write : std_logic; -- usb_0_avalon_usb_slave_translator:av_write -> usb_0:write
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read : std_logic; -- usb_0_avalon_usb_slave_translator:av_read -> usb_0:read
signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- usb_0:readdata -> usb_0_avalon_usb_slave_translator:av_readdata
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_writedata -> rs232_0:writedata
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_address -> rs232_0:address
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_chipselect -> rs232_0:chipselect
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_write -> rs232_0:write
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_read -> rs232_0:read
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rs232_0:readdata -> rs232_0_avalon_rs232_slave_translator:av_readdata
signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_byteenable -> rs232_0:byteenable
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_address
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_lock
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_write
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_read
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_burstcount
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_writedata
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_address
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_lock
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_write
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_read
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_byteenable
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(17 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(17 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sram_0_avalon_sram_slave_translator:uav_waitrequest -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sram_0_avalon_sram_slave_translator:uav_burstcount
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sram_0_avalon_sram_slave_translator:uav_writedata
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> sram_0_avalon_sram_slave_translator:uav_address
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> sram_0_avalon_sram_slave_translator:uav_write
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sram_0_avalon_sram_slave_translator:uav_lock
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> sram_0_avalon_sram_slave_translator:uav_read
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:uav_readdata -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sram_0_avalon_sram_slave_translator:uav_readdatavalid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sram_0_avalon_sram_slave_translator:uav_debugaccess
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sram_0_avalon_sram_slave_translator:uav_byteenable
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- generic_tristate_controller_0_uas_translator:uav_waitrequest -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_burstcount -> generic_tristate_controller_0_uas_translator:uav_burstcount
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_writedata -> generic_tristate_controller_0_uas_translator:uav_writedata
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_address -> generic_tristate_controller_0_uas_translator:uav_address
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_write -> generic_tristate_controller_0_uas_translator:uav_write
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_lock -> generic_tristate_controller_0_uas_translator:uav_lock
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_read -> generic_tristate_controller_0_uas_translator:uav_read
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator:uav_readdata -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_readdata
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- generic_tristate_controller_0_uas_translator:uav_readdatavalid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_debugaccess -> generic_tristate_controller_0_uas_translator:uav_debugaccess
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_byteenable -> generic_tristate_controller_0_uas_translator:uav_byteenable
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(73 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(73 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(9 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(9 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- green_leds_s1_translator:uav_waitrequest -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> green_leds_s1_translator:uav_burstcount
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> green_leds_s1_translator:uav_writedata
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_address -> green_leds_s1_translator:uav_address
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_write -> green_leds_s1_translator:uav_write
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_lock -> green_leds_s1_translator:uav_lock
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_read -> green_leds_s1_translator:uav_read
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:uav_readdata -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- green_leds_s1_translator:uav_readdatavalid -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> green_leds_s1_translator:uav_debugaccess
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> green_leds_s1_translator:uav_byteenable
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
signal switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_address -> altpll_0_pll_slave_translator:uav_address
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_write -> altpll_0_pll_slave_translator:uav_write
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_read -> altpll_0_pll_slave_translator:uav_read
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(33 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- usb_0_avalon_usb_slave_translator:uav_waitrequest -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> usb_0_avalon_usb_slave_translator:uav_burstcount
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> usb_0_avalon_usb_slave_translator:uav_writedata
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_address -> usb_0_avalon_usb_slave_translator:uav_address
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_write -> usb_0_avalon_usb_slave_translator:uav_write
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_lock -> usb_0_avalon_usb_slave_translator:uav_lock
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_read -> usb_0_avalon_usb_slave_translator:uav_read
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- usb_0_avalon_usb_slave_translator:uav_readdata -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- usb_0_avalon_usb_slave_translator:uav_readdatavalid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> usb_0_avalon_usb_slave_translator:uav_debugaccess
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> usb_0_avalon_usb_slave_translator:uav_byteenable
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rs232_0_avalon_rs232_slave_translator:uav_waitrequest -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> rs232_0_avalon_rs232_slave_translator:uav_burstcount
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> rs232_0_avalon_rs232_slave_translator:uav_writedata
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_address -> rs232_0_avalon_rs232_slave_translator:uav_address
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_write -> rs232_0_avalon_rs232_slave_translator:uav_write
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_lock -> rs232_0_avalon_rs232_slave_translator:uav_lock
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_read -> rs232_0_avalon_rs232_slave_translator:uav_read
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator:uav_readdata -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rs232_0_avalon_rs232_slave_translator:uav_readdatavalid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rs232_0_avalon_rs232_slave_translator:uav_debugaccess
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> rs232_0_avalon_rs232_slave_translator:uav_byteenable
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_001:sink_ready -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(72 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_006:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_007:sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
signal switches_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_008:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_009:sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_010:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data
signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_011:sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data
signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_012:sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal burst_adapter_source0_endofpacket : std_logic; -- burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_source0_valid : std_logic; -- burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_source0_startofpacket : std_logic; -- burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_source0_data : std_logic_vector(81 downto 0); -- burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_source0_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
signal burst_adapter_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_001_source0_endofpacket : std_logic; -- burst_adapter_001:source0_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_001_source0_valid : std_logic; -- burst_adapter_001:source0_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_001_source0_startofpacket : std_logic; -- burst_adapter_001:source0_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_001_source0_data : std_logic_vector(81 downto 0); -- burst_adapter_001:source0_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_001_source0_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
signal burst_adapter_001_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_001:source0_channel -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_002_source0_endofpacket : std_logic; -- burst_adapter_002:source0_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_002_source0_valid : std_logic; -- burst_adapter_002:source0_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_002_source0_startofpacket : std_logic; -- burst_adapter_002:source0_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_002_source0_data : std_logic_vector(72 downto 0); -- burst_adapter_002:source0_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_002_source0_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_002:source0_ready
signal burst_adapter_002_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_002:source0_channel -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_channel
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, burst_adapter:reset, burst_adapter_001:reset, burst_adapter_002:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_003:reset, cmd_xbar_mux_004:reset, crosser:in_reset, crosser_001:out_reset, generic_tristate_controller_0:reset_reset, generic_tristate_controller_0_uas_translator:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, green_leds_s1_translator:reset, green_leds_s1_translator_avalon_universal_slave_0_agent:reset, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, irq_mapper:reset, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_qsys_0_data_master_translator:reset, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_instruction_master_translator:reset, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0:reset, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rs232_0:reset, rs232_0_avalon_rs232_slave_translator:reset, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:reset, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, rst_controller_reset_out_reset:in, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sram_0:reset, sram_0_avalon_sram_slave_translator:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tristate_conduit_bridge_0:reset, tristate_conduit_pin_sharer_0:reset_reset, usb_0:reset, usb_0_avalon_usb_slave_translator:reset, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:reset, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> onchip_memory2_0:reset_req
signal nios2_qsys_0_jtag_debug_module_reset_reset : std_logic; -- nios2_qsys_0:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [altpll_0:reset, altpll_0_pll_slave_translator:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, crosser:out_reset, crosser_001:in_reset, id_router_009:reset, rsp_xbar_demux_009:reset]
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
signal cmd_xbar_demux_src0_ready : std_logic; -- cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
signal cmd_xbar_demux_src2_endofpacket : std_logic; -- cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
signal cmd_xbar_demux_src2_valid : std_logic; -- cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid
signal cmd_xbar_demux_src2_startofpacket : std_logic; -- cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
signal cmd_xbar_demux_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data
signal cmd_xbar_demux_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel
signal cmd_xbar_demux_src2_ready : std_logic; -- cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready
signal cmd_xbar_demux_src3_endofpacket : std_logic; -- cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
signal cmd_xbar_demux_src3_valid : std_logic; -- cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
signal cmd_xbar_demux_src3_startofpacket : std_logic; -- cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
signal cmd_xbar_demux_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
signal cmd_xbar_demux_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
signal cmd_xbar_demux_src3_ready : std_logic; -- cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
signal cmd_xbar_demux_src4_endofpacket : std_logic; -- cmd_xbar_demux:src4_endofpacket -> cmd_xbar_mux_004:sink0_endofpacket
signal cmd_xbar_demux_src4_valid : std_logic; -- cmd_xbar_demux:src4_valid -> cmd_xbar_mux_004:sink0_valid
signal cmd_xbar_demux_src4_startofpacket : std_logic; -- cmd_xbar_demux:src4_startofpacket -> cmd_xbar_mux_004:sink0_startofpacket
signal cmd_xbar_demux_src4_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src4_data -> cmd_xbar_mux_004:sink0_data
signal cmd_xbar_demux_src4_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src4_channel -> cmd_xbar_mux_004:sink0_channel
signal cmd_xbar_demux_src4_ready : std_logic; -- cmd_xbar_mux_004:sink0_ready -> cmd_xbar_demux:src4_ready
signal cmd_xbar_demux_001_src0_endofpacket : std_logic; -- cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
signal cmd_xbar_demux_001_src0_valid : std_logic; -- cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
signal cmd_xbar_demux_001_src0_startofpacket : std_logic; -- cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
signal cmd_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
signal cmd_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
signal cmd_xbar_demux_001_src0_ready : std_logic; -- cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
signal cmd_xbar_demux_001_src1_endofpacket : std_logic; -- cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
signal cmd_xbar_demux_001_src1_valid : std_logic; -- cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
signal cmd_xbar_demux_001_src1_startofpacket : std_logic; -- cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
signal cmd_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
signal cmd_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
signal cmd_xbar_demux_001_src1_ready : std_logic; -- cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
signal cmd_xbar_demux_001_src2_endofpacket : std_logic; -- cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
signal cmd_xbar_demux_001_src2_valid : std_logic; -- cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_002:sink1_valid
signal cmd_xbar_demux_001_src2_startofpacket : std_logic; -- cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
signal cmd_xbar_demux_001_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_002:sink1_data
signal cmd_xbar_demux_001_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_002:sink1_channel
signal cmd_xbar_demux_001_src2_ready : std_logic; -- cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_001:src2_ready
signal cmd_xbar_demux_001_src3_endofpacket : std_logic; -- cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
signal cmd_xbar_demux_001_src3_valid : std_logic; -- cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_003:sink1_valid
signal cmd_xbar_demux_001_src3_startofpacket : std_logic; -- cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
signal cmd_xbar_demux_001_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_003:sink1_data
signal cmd_xbar_demux_001_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_003:sink1_channel
signal cmd_xbar_demux_001_src3_ready : std_logic; -- cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src3_ready
signal cmd_xbar_demux_001_src4_endofpacket : std_logic; -- cmd_xbar_demux_001:src4_endofpacket -> cmd_xbar_mux_004:sink1_endofpacket
signal cmd_xbar_demux_001_src4_valid : std_logic; -- cmd_xbar_demux_001:src4_valid -> cmd_xbar_mux_004:sink1_valid
signal cmd_xbar_demux_001_src4_startofpacket : std_logic; -- cmd_xbar_demux_001:src4_startofpacket -> cmd_xbar_mux_004:sink1_startofpacket
signal cmd_xbar_demux_001_src4_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src4_data -> cmd_xbar_mux_004:sink1_data
signal cmd_xbar_demux_001_src4_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src4_channel -> cmd_xbar_mux_004:sink1_channel
signal cmd_xbar_demux_001_src4_ready : std_logic; -- cmd_xbar_mux_004:sink1_ready -> cmd_xbar_demux_001:src4_ready
signal cmd_xbar_demux_001_src5_endofpacket : std_logic; -- cmd_xbar_demux_001:src5_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src5_valid : std_logic; -- cmd_xbar_demux_001:src5_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src5_startofpacket : std_logic; -- cmd_xbar_demux_001:src5_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src5_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src5_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src5_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src5_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src6_endofpacket : std_logic; -- cmd_xbar_demux_001:src6_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src6_valid : std_logic; -- cmd_xbar_demux_001:src6_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src6_startofpacket : std_logic; -- cmd_xbar_demux_001:src6_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src6_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src6_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src6_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src6_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src7_endofpacket : std_logic; -- cmd_xbar_demux_001:src7_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src7_valid : std_logic; -- cmd_xbar_demux_001:src7_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src7_startofpacket : std_logic; -- cmd_xbar_demux_001:src7_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src7_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src7_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src7_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src7_channel -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src8_endofpacket : std_logic; -- cmd_xbar_demux_001:src8_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src8_valid : std_logic; -- cmd_xbar_demux_001:src8_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src8_startofpacket : std_logic; -- cmd_xbar_demux_001:src8_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src8_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src8_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src8_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src8_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src10_endofpacket : std_logic; -- cmd_xbar_demux_001:src10_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src10_valid : std_logic; -- cmd_xbar_demux_001:src10_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src10_startofpacket : std_logic; -- cmd_xbar_demux_001:src10_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src10_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src10_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src10_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src10_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src11_endofpacket : std_logic; -- cmd_xbar_demux_001:src11_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src11_valid : std_logic; -- cmd_xbar_demux_001:src11_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src11_startofpacket : std_logic; -- cmd_xbar_demux_001:src11_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src11_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src11_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src11_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src11_channel -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src12_endofpacket : std_logic; -- cmd_xbar_demux_001:src12_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src12_valid : std_logic; -- cmd_xbar_demux_001:src12_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src12_startofpacket : std_logic; -- cmd_xbar_demux_001:src12_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src12_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src12_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src12_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src12_channel -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_src1_endofpacket : std_logic; -- rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
signal rsp_xbar_demux_src1_valid : std_logic; -- rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
signal rsp_xbar_demux_src1_startofpacket : std_logic; -- rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
signal rsp_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
signal rsp_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
signal rsp_xbar_demux_src1_ready : std_logic; -- rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_001_src1_endofpacket : std_logic; -- rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
signal rsp_xbar_demux_001_src1_valid : std_logic; -- rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
signal rsp_xbar_demux_001_src1_startofpacket : std_logic; -- rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
signal rsp_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
signal rsp_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
signal rsp_xbar_demux_001_src1_ready : std_logic; -- rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
signal rsp_xbar_demux_002_src1_endofpacket : std_logic; -- rsp_xbar_demux_002:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
signal rsp_xbar_demux_002_src1_valid : std_logic; -- rsp_xbar_demux_002:src1_valid -> rsp_xbar_mux_001:sink2_valid
signal rsp_xbar_demux_002_src1_startofpacket : std_logic; -- rsp_xbar_demux_002:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
signal rsp_xbar_demux_002_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src1_data -> rsp_xbar_mux_001:sink2_data
signal rsp_xbar_demux_002_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src1_channel -> rsp_xbar_mux_001:sink2_channel
signal rsp_xbar_demux_002_src1_ready : std_logic; -- rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src1_ready
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_003_src1_endofpacket : std_logic; -- rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
signal rsp_xbar_demux_003_src1_valid : std_logic; -- rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink3_valid
signal rsp_xbar_demux_003_src1_startofpacket : std_logic; -- rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
signal rsp_xbar_demux_003_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink3_data
signal rsp_xbar_demux_003_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink3_channel
signal rsp_xbar_demux_003_src1_ready : std_logic; -- rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src1_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
signal rsp_xbar_demux_004_src1_endofpacket : std_logic; -- rsp_xbar_demux_004:src1_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
signal rsp_xbar_demux_004_src1_valid : std_logic; -- rsp_xbar_demux_004:src1_valid -> rsp_xbar_mux_001:sink4_valid
signal rsp_xbar_demux_004_src1_startofpacket : std_logic; -- rsp_xbar_demux_004:src1_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
signal rsp_xbar_demux_004_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_004:src1_data -> rsp_xbar_mux_001:sink4_data
signal rsp_xbar_demux_004_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_004:src1_channel -> rsp_xbar_mux_001:sink4_channel
signal rsp_xbar_demux_004_src1_ready : std_logic; -- rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src1_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal rsp_xbar_demux_006_src0_endofpacket : std_logic; -- rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
signal rsp_xbar_demux_006_src0_valid : std_logic; -- rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
signal rsp_xbar_demux_006_src0_startofpacket : std_logic; -- rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
signal rsp_xbar_demux_006_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
signal rsp_xbar_demux_006_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
signal rsp_xbar_demux_006_src0_ready : std_logic; -- rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
signal rsp_xbar_demux_007_src0_endofpacket : std_logic; -- rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
signal rsp_xbar_demux_007_src0_valid : std_logic; -- rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
signal rsp_xbar_demux_007_src0_startofpacket : std_logic; -- rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
signal rsp_xbar_demux_007_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
signal rsp_xbar_demux_007_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
signal rsp_xbar_demux_007_src0_ready : std_logic; -- rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
signal rsp_xbar_demux_008_src0_endofpacket : std_logic; -- rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket
signal rsp_xbar_demux_008_src0_valid : std_logic; -- rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid
signal rsp_xbar_demux_008_src0_startofpacket : std_logic; -- rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket
signal rsp_xbar_demux_008_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data
signal rsp_xbar_demux_008_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel
signal rsp_xbar_demux_008_src0_ready : std_logic; -- rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready
signal rsp_xbar_demux_010_src0_endofpacket : std_logic; -- rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket
signal rsp_xbar_demux_010_src0_valid : std_logic; -- rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid
signal rsp_xbar_demux_010_src0_startofpacket : std_logic; -- rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket
signal rsp_xbar_demux_010_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data
signal rsp_xbar_demux_010_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel
signal rsp_xbar_demux_010_src0_ready : std_logic; -- rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready
signal rsp_xbar_demux_011_src0_endofpacket : std_logic; -- rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket
signal rsp_xbar_demux_011_src0_valid : std_logic; -- rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid
signal rsp_xbar_demux_011_src0_startofpacket : std_logic; -- rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket
signal rsp_xbar_demux_011_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data
signal rsp_xbar_demux_011_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel
signal rsp_xbar_demux_011_src0_ready : std_logic; -- rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready
signal rsp_xbar_demux_012_src0_endofpacket : std_logic; -- rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket
signal rsp_xbar_demux_012_src0_valid : std_logic; -- rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid
signal rsp_xbar_demux_012_src0_startofpacket : std_logic; -- rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket
signal rsp_xbar_demux_012_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data
signal rsp_xbar_demux_012_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel
signal rsp_xbar_demux_012_src0_ready : std_logic; -- rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> cmd_xbar_demux:sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal addr_router_src_data : std_logic_vector(99 downto 0); -- addr_router:src_data -> cmd_xbar_demux:sink_data
signal addr_router_src_channel : std_logic_vector(12 downto 0); -- addr_router:src_channel -> cmd_xbar_demux:sink_channel
signal addr_router_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> addr_router:src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux:src_data -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux:src_channel -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_src_ready : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
signal addr_router_001_src_endofpacket : std_logic; -- addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
signal addr_router_001_src_valid : std_logic; -- addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
signal addr_router_001_src_startofpacket : std_logic; -- addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
signal addr_router_001_src_data : std_logic_vector(99 downto 0); -- addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
signal addr_router_001_src_channel : std_logic_vector(12 downto 0); -- addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
signal addr_router_001_src_ready : std_logic; -- cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
signal rsp_xbar_mux_001_src_endofpacket : std_logic; -- rsp_xbar_mux_001:src_endofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_001_src_valid : std_logic; -- rsp_xbar_mux_001:src_valid -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_001_src_startofpacket : std_logic; -- rsp_xbar_mux_001:src_startofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux_001:src_data -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux_001:src_channel -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_001_src_ready : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready
signal cmd_xbar_mux_src_endofpacket : std_logic; -- cmd_xbar_mux:src_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_src_valid : std_logic; -- cmd_xbar_mux:src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_src_startofpacket : std_logic; -- cmd_xbar_mux:src_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux:src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux:src_channel -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> rsp_xbar_demux:sink_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal id_router_src_data : std_logic_vector(99 downto 0); -- id_router:src_data -> rsp_xbar_demux:sink_data
signal id_router_src_channel : std_logic_vector(12 downto 0); -- id_router:src_channel -> rsp_xbar_demux:sink_channel
signal id_router_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> id_router:src_ready
signal cmd_xbar_mux_002_src_endofpacket : std_logic; -- cmd_xbar_mux_002:src_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_002_src_valid : std_logic; -- cmd_xbar_mux_002:src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_002_src_startofpacket : std_logic; -- cmd_xbar_mux_002:src_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_002_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_002:src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_002_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_002:src_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_002_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_002:src_ready
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal id_router_002_src_data : std_logic_vector(99 downto 0); -- id_router_002:src_data -> rsp_xbar_demux_002:sink_data
signal id_router_002_src_channel : std_logic_vector(12 downto 0); -- id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
signal id_router_002_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
signal cmd_xbar_demux_001_src5_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal id_router_005_src_data : std_logic_vector(99 downto 0); -- id_router_005:src_data -> rsp_xbar_demux_005:sink_data
signal id_router_005_src_channel : std_logic_vector(12 downto 0); -- id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
signal id_router_005_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
signal cmd_xbar_demux_001_src6_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
signal id_router_006_src_endofpacket : std_logic; -- id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
signal id_router_006_src_valid : std_logic; -- id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
signal id_router_006_src_startofpacket : std_logic; -- id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
signal id_router_006_src_data : std_logic_vector(99 downto 0); -- id_router_006:src_data -> rsp_xbar_demux_006:sink_data
signal id_router_006_src_channel : std_logic_vector(12 downto 0); -- id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
signal id_router_006_src_ready : std_logic; -- rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
signal cmd_xbar_demux_001_src7_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
signal id_router_007_src_endofpacket : std_logic; -- id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
signal id_router_007_src_valid : std_logic; -- id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
signal id_router_007_src_startofpacket : std_logic; -- id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
signal id_router_007_src_data : std_logic_vector(99 downto 0); -- id_router_007:src_data -> rsp_xbar_demux_007:sink_data
signal id_router_007_src_channel : std_logic_vector(12 downto 0); -- id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
signal id_router_007_src_ready : std_logic; -- rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
signal cmd_xbar_demux_001_src8_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready
signal id_router_008_src_endofpacket : std_logic; -- id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
signal id_router_008_src_valid : std_logic; -- id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
signal id_router_008_src_startofpacket : std_logic; -- id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
signal id_router_008_src_data : std_logic_vector(99 downto 0); -- id_router_008:src_data -> rsp_xbar_demux_008:sink_data
signal id_router_008_src_channel : std_logic_vector(12 downto 0); -- id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
signal id_router_008_src_ready : std_logic; -- rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
signal crosser_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready
signal id_router_009_src_endofpacket : std_logic; -- id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
signal id_router_009_src_valid : std_logic; -- id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
signal id_router_009_src_startofpacket : std_logic; -- id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
signal id_router_009_src_data : std_logic_vector(99 downto 0); -- id_router_009:src_data -> rsp_xbar_demux_009:sink_data
signal id_router_009_src_channel : std_logic_vector(12 downto 0); -- id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
signal id_router_009_src_ready : std_logic; -- rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
signal cmd_xbar_demux_001_src10_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready
signal id_router_010_src_endofpacket : std_logic; -- id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
signal id_router_010_src_valid : std_logic; -- id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
signal id_router_010_src_startofpacket : std_logic; -- id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
signal id_router_010_src_data : std_logic_vector(99 downto 0); -- id_router_010:src_data -> rsp_xbar_demux_010:sink_data
signal id_router_010_src_channel : std_logic_vector(12 downto 0); -- id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
signal id_router_010_src_ready : std_logic; -- rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
signal cmd_xbar_demux_001_src11_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready
signal id_router_011_src_endofpacket : std_logic; -- id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket
signal id_router_011_src_valid : std_logic; -- id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid
signal id_router_011_src_startofpacket : std_logic; -- id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket
signal id_router_011_src_data : std_logic_vector(99 downto 0); -- id_router_011:src_data -> rsp_xbar_demux_011:sink_data
signal id_router_011_src_channel : std_logic_vector(12 downto 0); -- id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel
signal id_router_011_src_ready : std_logic; -- rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready
signal cmd_xbar_demux_001_src12_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready
signal id_router_012_src_endofpacket : std_logic; -- id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket
signal id_router_012_src_valid : std_logic; -- id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid
signal id_router_012_src_startofpacket : std_logic; -- id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket
signal id_router_012_src_data : std_logic_vector(99 downto 0); -- id_router_012:src_data -> rsp_xbar_demux_012:sink_data
signal id_router_012_src_channel : std_logic_vector(12 downto 0); -- id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel
signal id_router_012_src_ready : std_logic; -- rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready
signal cmd_xbar_mux_001_src_endofpacket : std_logic; -- cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_mux_001_src_valid : std_logic; -- cmd_xbar_mux_001:src_valid -> width_adapter:in_valid
signal cmd_xbar_mux_001_src_startofpacket : std_logic; -- cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_001:src_data -> width_adapter:in_data
signal cmd_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_001:src_channel -> width_adapter:in_channel
signal cmd_xbar_mux_001_src_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_mux_001:src_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> burst_adapter:sink0_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
signal width_adapter_src_data : std_logic_vector(81 downto 0); -- width_adapter:out_data -> burst_adapter:sink0_data
signal width_adapter_src_ready : std_logic; -- burst_adapter:sink0_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(12 downto 0); -- width_adapter:out_channel -> burst_adapter:sink0_channel
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> width_adapter_001:in_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket
signal id_router_001_src_data : std_logic_vector(81 downto 0); -- id_router_001:src_data -> width_adapter_001:in_data
signal id_router_001_src_channel : std_logic_vector(12 downto 0); -- id_router_001:src_channel -> width_adapter_001:in_channel
signal id_router_001_src_ready : std_logic; -- width_adapter_001:in_ready -> id_router_001:src_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal width_adapter_001_src_data : std_logic_vector(99 downto 0); -- width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(12 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel
signal cmd_xbar_mux_003_src_endofpacket : std_logic; -- cmd_xbar_mux_003:src_endofpacket -> width_adapter_002:in_endofpacket
signal cmd_xbar_mux_003_src_valid : std_logic; -- cmd_xbar_mux_003:src_valid -> width_adapter_002:in_valid
signal cmd_xbar_mux_003_src_startofpacket : std_logic; -- cmd_xbar_mux_003:src_startofpacket -> width_adapter_002:in_startofpacket
signal cmd_xbar_mux_003_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_003:src_data -> width_adapter_002:in_data
signal cmd_xbar_mux_003_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_003:src_channel -> width_adapter_002:in_channel
signal cmd_xbar_mux_003_src_ready : std_logic; -- width_adapter_002:in_ready -> cmd_xbar_mux_003:src_ready
signal width_adapter_002_src_endofpacket : std_logic; -- width_adapter_002:out_endofpacket -> burst_adapter_001:sink0_endofpacket
signal width_adapter_002_src_valid : std_logic; -- width_adapter_002:out_valid -> burst_adapter_001:sink0_valid
signal width_adapter_002_src_startofpacket : std_logic; -- width_adapter_002:out_startofpacket -> burst_adapter_001:sink0_startofpacket
signal width_adapter_002_src_data : std_logic_vector(81 downto 0); -- width_adapter_002:out_data -> burst_adapter_001:sink0_data
signal width_adapter_002_src_ready : std_logic; -- burst_adapter_001:sink0_ready -> width_adapter_002:out_ready
signal width_adapter_002_src_channel : std_logic_vector(12 downto 0); -- width_adapter_002:out_channel -> burst_adapter_001:sink0_channel
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> width_adapter_003:in_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> width_adapter_003:in_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> width_adapter_003:in_startofpacket
signal id_router_003_src_data : std_logic_vector(81 downto 0); -- id_router_003:src_data -> width_adapter_003:in_data
signal id_router_003_src_channel : std_logic_vector(12 downto 0); -- id_router_003:src_channel -> width_adapter_003:in_channel
signal id_router_003_src_ready : std_logic; -- width_adapter_003:in_ready -> id_router_003:src_ready
signal width_adapter_003_src_endofpacket : std_logic; -- width_adapter_003:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal width_adapter_003_src_valid : std_logic; -- width_adapter_003:out_valid -> rsp_xbar_demux_003:sink_valid
signal width_adapter_003_src_startofpacket : std_logic; -- width_adapter_003:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal width_adapter_003_src_data : std_logic_vector(99 downto 0); -- width_adapter_003:out_data -> rsp_xbar_demux_003:sink_data
signal width_adapter_003_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> width_adapter_003:out_ready
signal width_adapter_003_src_channel : std_logic_vector(12 downto 0); -- width_adapter_003:out_channel -> rsp_xbar_demux_003:sink_channel
signal cmd_xbar_mux_004_src_endofpacket : std_logic; -- cmd_xbar_mux_004:src_endofpacket -> width_adapter_004:in_endofpacket
signal cmd_xbar_mux_004_src_valid : std_logic; -- cmd_xbar_mux_004:src_valid -> width_adapter_004:in_valid
signal cmd_xbar_mux_004_src_startofpacket : std_logic; -- cmd_xbar_mux_004:src_startofpacket -> width_adapter_004:in_startofpacket
signal cmd_xbar_mux_004_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_004:src_data -> width_adapter_004:in_data
signal cmd_xbar_mux_004_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_004:src_channel -> width_adapter_004:in_channel
signal cmd_xbar_mux_004_src_ready : std_logic; -- width_adapter_004:in_ready -> cmd_xbar_mux_004:src_ready
signal width_adapter_004_src_endofpacket : std_logic; -- width_adapter_004:out_endofpacket -> burst_adapter_002:sink0_endofpacket
signal width_adapter_004_src_valid : std_logic; -- width_adapter_004:out_valid -> burst_adapter_002:sink0_valid
signal width_adapter_004_src_startofpacket : std_logic; -- width_adapter_004:out_startofpacket -> burst_adapter_002:sink0_startofpacket
signal width_adapter_004_src_data : std_logic_vector(72 downto 0); -- width_adapter_004:out_data -> burst_adapter_002:sink0_data
signal width_adapter_004_src_ready : std_logic; -- burst_adapter_002:sink0_ready -> width_adapter_004:out_ready
signal width_adapter_004_src_channel : std_logic_vector(12 downto 0); -- width_adapter_004:out_channel -> burst_adapter_002:sink0_channel
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> width_adapter_005:in_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> width_adapter_005:in_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> width_adapter_005:in_startofpacket
signal id_router_004_src_data : std_logic_vector(72 downto 0); -- id_router_004:src_data -> width_adapter_005:in_data
signal id_router_004_src_channel : std_logic_vector(12 downto 0); -- id_router_004:src_channel -> width_adapter_005:in_channel
signal id_router_004_src_ready : std_logic; -- width_adapter_005:in_ready -> id_router_004:src_ready
signal width_adapter_005_src_endofpacket : std_logic; -- width_adapter_005:out_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal width_adapter_005_src_valid : std_logic; -- width_adapter_005:out_valid -> rsp_xbar_demux_004:sink_valid
signal width_adapter_005_src_startofpacket : std_logic; -- width_adapter_005:out_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal width_adapter_005_src_data : std_logic_vector(99 downto 0); -- width_adapter_005:out_data -> rsp_xbar_demux_004:sink_data
signal width_adapter_005_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> width_adapter_005:out_ready
signal width_adapter_005_src_channel : std_logic_vector(12 downto 0); -- width_adapter_005:out_channel -> rsp_xbar_demux_004:sink_channel
signal crosser_out_endofpacket : std_logic; -- crosser:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal crosser_out_valid : std_logic; -- crosser:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal crosser_out_startofpacket : std_logic; -- crosser:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal crosser_out_data : std_logic_vector(99 downto 0); -- crosser:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_data
signal crosser_out_channel : std_logic_vector(12 downto 0); -- crosser:out_channel -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src9_endofpacket : std_logic; -- cmd_xbar_demux_001:src9_endofpacket -> crosser:in_endofpacket
signal cmd_xbar_demux_001_src9_valid : std_logic; -- cmd_xbar_demux_001:src9_valid -> crosser:in_valid
signal cmd_xbar_demux_001_src9_startofpacket : std_logic; -- cmd_xbar_demux_001:src9_startofpacket -> crosser:in_startofpacket
signal cmd_xbar_demux_001_src9_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src9_data -> crosser:in_data
signal cmd_xbar_demux_001_src9_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src9_channel -> crosser:in_channel
signal cmd_xbar_demux_001_src9_ready : std_logic; -- crosser:in_ready -> cmd_xbar_demux_001:src9_ready
signal crosser_001_out_endofpacket : std_logic; -- crosser_001:out_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket
signal crosser_001_out_valid : std_logic; -- crosser_001:out_valid -> rsp_xbar_mux_001:sink9_valid
signal crosser_001_out_startofpacket : std_logic; -- crosser_001:out_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket
signal crosser_001_out_data : std_logic_vector(99 downto 0); -- crosser_001:out_data -> rsp_xbar_mux_001:sink9_data
signal crosser_001_out_channel : std_logic_vector(12 downto 0); -- crosser_001:out_channel -> rsp_xbar_mux_001:sink9_channel
signal crosser_001_out_ready : std_logic; -- rsp_xbar_mux_001:sink9_ready -> crosser_001:out_ready
signal rsp_xbar_demux_009_src0_endofpacket : std_logic; -- rsp_xbar_demux_009:src0_endofpacket -> crosser_001:in_endofpacket
signal rsp_xbar_demux_009_src0_valid : std_logic; -- rsp_xbar_demux_009:src0_valid -> crosser_001:in_valid
signal rsp_xbar_demux_009_src0_startofpacket : std_logic; -- rsp_xbar_demux_009:src0_startofpacket -> crosser_001:in_startofpacket
signal rsp_xbar_demux_009_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_009:src0_data -> crosser_001:in_data
signal rsp_xbar_demux_009_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_009:src0_channel -> crosser_001:in_channel
signal rsp_xbar_demux_009_src0_ready : std_logic; -- crosser_001:in_ready -> rsp_xbar_demux_009:src0_ready
signal irq_mapper_receiver0_irq : std_logic; -- timer_0:irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver1_irq
signal irq_mapper_receiver2_irq : std_logic; -- usb_0:irq -> irq_mapper:receiver2_irq
signal irq_mapper_receiver3_irq : std_logic; -- rs232_0:irq -> irq_mapper:receiver3_irq
signal nios2_qsys_0_d_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_qsys_0:d_irq
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_write:inv -> sdram_0:az_wr_n
signal sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_read:inv -> sdram_0:az_rd_n
signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_anti_slave_0_byteenable:inv -> sdram_0:az_be_n
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:inv -> jtag_uart_0:av_write_n
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:inv -> jtag_uart_0:av_read_n
signal green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- green_leds_s1_translator_avalon_anti_slave_0_write:inv -> green_leds:write_n
signal timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- timer_0_s1_translator_avalon_anti_slave_0_write:inv -> timer_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [green_leds:reset_n, jtag_uart_0:rst_n, nios2_qsys_0:reset_n, sdram_0:reset_n, switches:reset_n, sysid_qsys_0:reset_n, timer_0:reset_n]
begin
nios2_qsys_0 : component niosII_system_nios2_qsys_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
d_address => nios2_qsys_0_data_master_address, -- data_master.address
d_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
d_read => nios2_qsys_0_data_master_read, -- .read
d_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_qsys_0_data_master_write, -- .write
d_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
jtag_debug_module_debugaccess_to_roms => nios2_qsys_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_qsys_0_instruction_master_address, -- instruction_master.address
i_read => nios2_qsys_0_instruction_master_read, -- .read
i_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
d_irq => nios2_qsys_0_d_irq_irq, -- d_irq.irq
jtag_debug_module_resetrequest => nios2_qsys_0_jtag_debug_module_reset_reset, -- jtag_debug_module_reset.reset
jtag_debug_module_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- jtag_debug_module.address
jtag_debug_module_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
jtag_debug_module_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
jtag_debug_module_read => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read, -- .read
jtag_debug_module_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
jtag_debug_module_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
jtag_debug_module_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
jtag_debug_module_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
no_ci_readra => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosII_system_onchip_memory2_0
port map (
clk => altpll_0_c1_clk, -- clk1.clk
address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken
chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write
readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
sysid_qsys_0 : component niosII_system_sysid_qsys_0
port map (
clock => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- control_slave.readdata
address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address(0) -- .address
);
jtag_uart_0 : component niosII_system_jtag_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- avalon_jtag_slave.chipselect
av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address(0), -- .address
av_read_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n
av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver1_irq -- irq.irq
);
green_leds : component niosII_system_green_leds
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => green_leds_s1_translator_avalon_anti_slave_0_address, -- s1.address
write_n => green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
out_port => green_leds_external_connection_export -- external_connection.export
);
switches : component niosII_system_switches
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => switches_s1_translator_avalon_anti_slave_0_address, -- s1.address
readdata => switches_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
in_port => switches_external_connection_export -- external_connection.export
);
altpll_0 : component niosII_system_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_001_reset_out_reset, -- inclk_interface_reset.reset
read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- pll_slave.read
write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write
address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- .address
readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
sdram_0 : component niosII_system_sdram_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => sdram_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
az_be_n => sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv, -- .byteenable_n
az_cs => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
az_data => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
az_rd_n => sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n
az_wr_n => sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
za_data => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
za_valid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
za_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
zs_addr => sdram_0_wire_addr, -- wire.export
zs_ba => sdram_0_wire_ba, -- .export
zs_cas_n => sdram_0_wire_cas_n, -- .export
zs_cke => sdram_0_wire_cke, -- .export
zs_cs_n => sdram_0_wire_cs_n, -- .export
zs_dq => sdram_0_wire_dq, -- .export
zs_dqm => sdram_0_wire_dqm, -- .export
zs_ras_n => sdram_0_wire_ras_n, -- .export
zs_we_n => sdram_0_wire_we_n -- .export
);
sram_0 : component niosII_system_sram_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
SRAM_DQ => sram_0_external_interface_DQ, -- external_interface.export
SRAM_ADDR => sram_0_external_interface_ADDR, -- .export
SRAM_LB_N => sram_0_external_interface_LB_N, -- .export
SRAM_UB_N => sram_0_external_interface_UB_N, -- .export
SRAM_CE_N => sram_0_external_interface_CE_N, -- .export
SRAM_OE_N => sram_0_external_interface_OE_N, -- .export
SRAM_WE_N => sram_0_external_interface_WE_N, -- .export
address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_sram_slave.address
byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid -- .readdatavalid
);
timer_0 : component niosII_system_timer_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => timer_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
write_n => timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
irq => irq_mapper_receiver0_irq -- irq.irq
);
usb_0 : component niosII_system_usb_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
address => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address, -- avalon_usb_slave.address
chipselect => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
read => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read, -- .read
write => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
irq => irq_mapper_receiver2_irq, -- interrupt.irq
OTG_INT1 => usb_0_external_interface_INT1, -- external_interface.export
OTG_DATA => usb_0_external_interface_DATA, -- .export
OTG_RST_N => usb_0_external_interface_RST_N, -- .export
OTG_ADDR => usb_0_external_interface_ADDR, -- .export
OTG_CS_N => usb_0_external_interface_CS_N, -- .export
OTG_RD_N => usb_0_external_interface_RD_N, -- .export
OTG_WR_N => usb_0_external_interface_WR_N, -- .export
OTG_INT0 => usb_0_external_interface_INT0 -- .export
);
rs232_0 : component niosII_system_rs232_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
address => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address(0), -- avalon_rs232_slave.address
chipselect => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
byteenable => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read, -- .read
write => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
irq => irq_mapper_receiver3_irq, -- interrupt.irq
UART_RXD => rs232_0_external_interface_RXD, -- external_interface.export
UART_TXD => rs232_0_external_interface_TXD -- .export
);
generic_tristate_controller_0 : component niosII_system_generic_tristate_controller_0
generic map (
TCM_ADDRESS_W => 22,
TCM_DATA_W => 8,
TCM_BYTEENABLE_W => 1,
TCM_READ_WAIT => 160,
TCM_WRITE_WAIT => 160,
TCM_SETUP_WAIT => 40,
TCM_DATA_HOLD => 40,
TCM_TURNAROUND_TIME => 2,
TCM_TIMING_UNITS => 0,
TCM_READLATENCY => 2,
TCM_SYMBOLS_PER_WORD => 1,
USE_READDATA => 1,
USE_WRITEDATA => 1,
USE_READ => 1,
USE_WRITE => 1,
USE_BYTEENABLE => 1,
USE_CHIPSELECT => 1,
USE_LOCK => 0,
USE_ADDRESS => 1,
USE_WAITREQUEST => 0,
USE_WRITEBYTEENABLE => 0,
USE_OUTPUTENABLE => 0,
USE_RESETREQUEST => 0,
USE_IRQ => 0,
USE_RESET_OUTPUT => 0,
ACTIVE_LOW_READ => 1,
ACTIVE_LOW_LOCK => 0,
ACTIVE_LOW_WRITE => 1,
ACTIVE_LOW_CHIPSELECT => 1,
ACTIVE_LOW_BYTEENABLE => 0,
ACTIVE_LOW_OUTPUTENABLE => 0,
ACTIVE_LOW_WRITEBYTEENABLE => 0,
ACTIVE_LOW_WAITREQUEST => 0,
ACTIVE_LOW_BEGINTRANSFER => 0,
CHIPSELECT_THROUGH_READLATENCY => 0
)
port map (
clk_clk => altpll_0_c1_clk, -- clk.clk
reset_reset => rst_controller_reset_out_reset, -- reset.reset
uas_address => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address, -- uas.address
uas_burstcount => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount, -- .burstcount
uas_read => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read, -- .read
uas_write => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write, -- .write
uas_waitrequest => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
uas_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
uas_byteenable => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable, -- .byteenable
uas_readdata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata, -- .readdata
uas_writedata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata, -- .writedata
uas_lock => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock, -- .lock
uas_debugaccess => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
tcm_write_n_out => generic_tristate_controller_0_tcm_write_n_out, -- tcm.write_n_out
tcm_read_n_out => generic_tristate_controller_0_tcm_read_n_out, -- .read_n_out
tcm_begintransfer_out => generic_tristate_controller_0_tcm_begintransfer_out, -- .begintransfer_out
tcm_chipselect_n_out => generic_tristate_controller_0_tcm_chipselect_n_out, -- .chipselect_n_out
tcm_request => generic_tristate_controller_0_tcm_request, -- .request
tcm_grant => generic_tristate_controller_0_tcm_grant, -- .grant
tcm_address_out => generic_tristate_controller_0_tcm_address_out, -- .address_out
tcm_byteenable_out => generic_tristate_controller_0_tcm_byteenable_out, -- .byteenable_out
tcm_data_out => generic_tristate_controller_0_tcm_data_out, -- .data_out
tcm_data_outen => generic_tristate_controller_0_tcm_data_outen, -- .data_outen
tcm_data_in => generic_tristate_controller_0_tcm_data_in -- .data_in
);
tristate_conduit_bridge_0 : component niosII_system_tristate_conduit_bridge_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
request => tristate_conduit_pin_sharer_0_tcm_request, -- tcs.request
grant => tristate_conduit_pin_sharer_0_tcm_grant, -- .grant
tcs_generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out, -- .generic_tristate_controller_0_tcm_read_n_out_out
tcs_generic_tristate_controller_0_tcm_data_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out, -- .generic_tristate_controller_0_tcm_data_out_out
tcs_generic_tristate_controller_0_tcm_data_outen => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen, -- .generic_tristate_controller_0_tcm_data_out_outen
tcs_generic_tristate_controller_0_tcm_data_in => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in, -- .generic_tristate_controller_0_tcm_data_out_in
tcs_generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out_out
tcs_generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out, -- .generic_tristate_controller_0_tcm_write_n_out_out
tcs_generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out, -- .generic_tristate_controller_0_tcm_byteenable_out_out
tcs_generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out, -- .generic_tristate_controller_0_tcm_begintransfer_out_out
tcs_generic_tristate_controller_0_tcm_address_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out, -- .generic_tristate_controller_0_tcm_address_out_out
generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out, -- out.generic_tristate_controller_0_tcm_read_n_out
generic_tristate_controller_0_tcm_data_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out, -- .generic_tristate_controller_0_tcm_data_out
generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out
generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out, -- .generic_tristate_controller_0_tcm_write_n_out
generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_byteenable_out, -- .generic_tristate_controller_0_tcm_byteenable_out
generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_begintransfer_out, -- .generic_tristate_controller_0_tcm_begintransfer_out
generic_tristate_controller_0_tcm_address_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out -- .generic_tristate_controller_0_tcm_address_out
);
tristate_conduit_pin_sharer_0 : component niosII_system_tristate_conduit_pin_sharer_0
port map (
clk_clk => altpll_0_c1_clk, -- clk.clk
reset_reset => rst_controller_reset_out_reset, -- reset.reset
request => tristate_conduit_pin_sharer_0_tcm_request, -- tcm.request
grant => tristate_conduit_pin_sharer_0_tcm_grant, -- .grant
generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out, -- .generic_tristate_controller_0_tcm_byteenable_out_out
generic_tristate_controller_0_tcm_address_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out, -- .generic_tristate_controller_0_tcm_address_out_out
generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out, -- .generic_tristate_controller_0_tcm_read_n_out_out
generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out, -- .generic_tristate_controller_0_tcm_write_n_out_out
generic_tristate_controller_0_tcm_data_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out, -- .generic_tristate_controller_0_tcm_data_out_out
generic_tristate_controller_0_tcm_data_in => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in, -- .generic_tristate_controller_0_tcm_data_out_in
generic_tristate_controller_0_tcm_data_outen => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen, -- .generic_tristate_controller_0_tcm_data_out_outen
generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out_out
generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out, -- .generic_tristate_controller_0_tcm_begintransfer_out_out
tcs0_request => generic_tristate_controller_0_tcm_request, -- tcs0.request
tcs0_grant => generic_tristate_controller_0_tcm_grant, -- .grant
tcs0_byteenable_out(0) => generic_tristate_controller_0_tcm_byteenable_out, -- .byteenable_out
tcs0_address_out => generic_tristate_controller_0_tcm_address_out, -- .address_out
tcs0_read_n_out(0) => generic_tristate_controller_0_tcm_read_n_out, -- .read_n_out
tcs0_write_n_out(0) => generic_tristate_controller_0_tcm_write_n_out, -- .write_n_out
tcs0_data_out => generic_tristate_controller_0_tcm_data_out, -- .data_out
tcs0_data_in => generic_tristate_controller_0_tcm_data_in, -- .data_in
tcs0_data_outen => generic_tristate_controller_0_tcm_data_outen, -- .data_outen
tcs0_chipselect_n_out(0) => generic_tristate_controller_0_tcm_chipselect_n_out, -- .chipselect_n_out
tcs0_begintransfer_out(0) => generic_tristate_controller_0_tcm_begintransfer_out -- .begintransfer_out
);
nios2_qsys_0_instruction_master_translator : component niosii_system_nios2_qsys_0_instruction_master_translator
generic map (
AV_ADDRESS_W => 25,
AV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
USE_READ => 1,
USE_WRITE => 0,
USE_BEGINBURSTTRANSFER => 0,
USE_BEGINTRANSFER => 0,
USE_CHIPSELECT => 0,
USE_BURSTCOUNT => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 1,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_LINEWRAPBURSTS => 1,
AV_REGISTERINCOMINGSIGNALS => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read
uav_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_instruction_master_address, -- avalon_anti_master_0.address
av_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
av_read => nios2_qsys_0_instruction_master_read, -- .read
av_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
av_burstcount => "1", -- (terminated)
av_byteenable => "1111", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_write => '0', -- (terminated)
av_writedata => "00000000000000000000000000000000", -- (terminated)
av_lock => '0', -- (terminated)
av_debugaccess => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
nios2_qsys_0_data_master_translator : component niosii_system_nios2_qsys_0_data_master_translator
generic map (
AV_ADDRESS_W => 25,
AV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
USE_READ => 1,
USE_WRITE => 1,
USE_BEGINBURSTTRANSFER => 0,
USE_BEGINTRANSFER => 0,
USE_CHIPSELECT => 0,
USE_BURSTCOUNT => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 1,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_LINEWRAPBURSTS => 0,
AV_REGISTERINCOMINGSIGNALS => 1
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read
uav_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_data_master_address, -- avalon_anti_master_0.address
av_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
av_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
av_read => nios2_qsys_0_data_master_read, -- .read
av_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
av_write => nios2_qsys_0_data_master_write, -- .write
av_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
av_debugaccess => nios2_qsys_0_data_master_debugaccess, -- .debugaccess
av_burstcount => "1", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_lock => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
nios2_qsys_0_jtag_debug_module_translator : component niosii_system_nios2_qsys_0_jtag_debug_module_translator
generic map (
AV_ADDRESS_W => 9,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
av_read => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read, -- .read
av_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
sdram_0_s1_translator : component niosii_system_sdram_0_s1_translator
generic map (
AV_ADDRESS_W => 22,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sdram_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => sdram_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_read => sdram_0_s1_translator_avalon_anti_slave_0_read, -- .read
av_readdata => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => sdram_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
onchip_memory2_0_s1_translator : component niosii_system_onchip_memory2_0_s1_translator
generic map (
AV_ADDRESS_W => 12,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
sram_0_avalon_sram_slave_translator : component niosii_system_sram_0_avalon_sram_slave_translator
generic map (
AV_ADDRESS_W => 18,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
generic_tristate_controller_0_uas_translator : component niosii_system_generic_tristate_controller_0_uas_translator
generic map (
AV_ADDRESS_W => 22,
AV_DATA_W => 8,
UAV_DATA_W => 8,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 1,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 1,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 1,
AV_ADDRESS_SYMBOLS => 1,
AV_BURSTCOUNT_SYMBOLS => 1,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write, -- .write
av_read => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read, -- .read
av_readdata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata, -- .writedata
av_burstcount => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount, -- .burstcount
av_byteenable => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_waitrequest => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_lock => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock, -- .lock
av_debugaccess => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
jtag_uart_0_avalon_jtag_slave_translator : component niosii_system_jtag_uart_0_avalon_jtag_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
sysid_qsys_0_control_slave_translator : component niosii_system_sysid_qsys_0_control_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
green_leds_s1_translator : component niosii_system_green_leds_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => green_leds_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => green_leds_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
switches_s1_translator : component niosii_system_switches_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => switches_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => switches_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => switches_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => switches_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => switches_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => switches_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
altpll_0_pll_slave_translator : component niosii_system_altpll_0_pll_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
timer_0_s1_translator : component niosii_system_timer_0_s1_translator
generic map (
AV_ADDRESS_W => 3,
AV_DATA_W => 16,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => timer_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => timer_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
usb_0_avalon_usb_slave_translator : component niosii_system_usb_0_avalon_usb_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 16,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 5,
AV_WRITE_WAIT_CYCLES => 5,
AV_SETUP_WAIT_CYCLES => 5,
AV_DATA_HOLD_CYCLES => 5
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
rs232_0_avalon_rs232_slave_translator : component niosii_system_rs232_0_avalon_rs232_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent
generic map (
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_BEGIN_BURST => 80,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
PKT_BURST_TYPE_H => 77,
PKT_BURST_TYPE_L => 76,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_TRANS_EXCLUSIVE => 66,
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_THREAD_ID_H => 90,
PKT_THREAD_ID_L => 90,
PKT_CACHE_H => 97,
PKT_CACHE_L => 94,
PKT_DATA_SIDEBAND_H => 79,
PKT_DATA_SIDEBAND_L => 79,
PKT_QOS_H => 81,
PKT_QOS_L => 81,
PKT_ADDR_SIDEBAND_H => 78,
PKT_ADDR_SIDEBAND_L => 78,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
ST_DATA_W => 100,
ST_CHANNEL_W => 13,
AV_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_RSP => 0,
ID => 1,
BURSTWRAP_VALUE => 3,
CACHE_VALUE => 0,
SECURE_ACCESS_BIT => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- av.address
av_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write
av_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_src_data, -- .data
rp_channel => rsp_xbar_mux_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_src_ready, -- .ready
av_response => open, -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent
generic map (
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_BEGIN_BURST => 80,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
PKT_BURST_TYPE_H => 77,
PKT_BURST_TYPE_L => 76,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_TRANS_EXCLUSIVE => 66,
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_THREAD_ID_H => 90,
PKT_THREAD_ID_L => 90,
PKT_CACHE_H => 97,
PKT_CACHE_L => 94,
PKT_DATA_SIDEBAND_H => 79,
PKT_DATA_SIDEBAND_L => 79,
PKT_QOS_H => 81,
PKT_QOS_L => 81,
PKT_ADDR_SIDEBAND_H => 78,
PKT_ADDR_SIDEBAND_L => 78,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
ST_DATA_W => 100,
ST_CHANNEL_W => 13,
AV_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_RSP => 0,
ID => 0,
BURSTWRAP_VALUE => 7,
CACHE_VALUE => 0,
SECURE_ACCESS_BIT => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- av.address
av_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write
av_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_001_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_001_src_data, -- .data
rp_channel => rsp_xbar_mux_001_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_001_src_ready, -- .ready
av_response => open, -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_src_valid, -- .valid
cp_data => cmd_xbar_mux_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_src_channel, -- .channel
rf_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sdram_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 15,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 62,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_ADDR_H => 42,
PKT_ADDR_L => 18,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_POSTED => 44,
PKT_TRANS_WRITE => 45,
PKT_TRANS_READ => 46,
PKT_TRANS_LOCK => 47,
PKT_SRC_ID_H => 67,
PKT_SRC_ID_L => 64,
PKT_DEST_ID_H => 71,
PKT_DEST_ID_L => 68,
PKT_BURSTWRAP_H => 54,
PKT_BURSTWRAP_L => 52,
PKT_BYTE_CNT_H => 51,
PKT_BYTE_CNT_L => 49,
PKT_PROTECTION_H => 75,
PKT_PROTECTION_L => 73,
PKT_RESPONSE_STATUS_H => 81,
PKT_RESPONSE_STATUS_L => 80,
PKT_BURST_SIZE_H => 57,
PKT_BURST_SIZE_L => 55,
ST_CHANNEL_W => 13,
ST_DATA_W => 82,
AVS_BURSTCOUNT_W => 2,
SUPPRESS_0_BYTEEN_CMD => 1,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_source0_ready, -- cp.ready
cp_valid => burst_adapter_source0_valid, -- .valid
cp_data => burst_adapter_source0_data, -- .data
cp_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_source0_channel, -- .channel
rf_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 83,
FIFO_DEPTH => 8,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 18,
FIFO_DEPTH => 8,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 0,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 3,
USE_MEMORY_BLOCKS => 1,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_002_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_002_src_valid, -- .valid
cp_data => cmd_xbar_mux_002_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_002_src_channel, -- .channel
rf_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 15,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 62,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_ADDR_H => 42,
PKT_ADDR_L => 18,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_POSTED => 44,
PKT_TRANS_WRITE => 45,
PKT_TRANS_READ => 46,
PKT_TRANS_LOCK => 47,
PKT_SRC_ID_H => 67,
PKT_SRC_ID_L => 64,
PKT_DEST_ID_H => 71,
PKT_DEST_ID_L => 68,
PKT_BURSTWRAP_H => 54,
PKT_BURSTWRAP_L => 52,
PKT_BYTE_CNT_H => 51,
PKT_BYTE_CNT_L => 49,
PKT_PROTECTION_H => 75,
PKT_PROTECTION_L => 73,
PKT_RESPONSE_STATUS_H => 81,
PKT_RESPONSE_STATUS_L => 80,
PKT_BURST_SIZE_H => 57,
PKT_BURST_SIZE_L => 55,
ST_CHANNEL_W => 13,
ST_DATA_W => 82,
AVS_BURSTCOUNT_W => 2,
SUPPRESS_0_BYTEEN_CMD => 1,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_001_source0_ready, -- cp.ready
cp_valid => burst_adapter_001_source0_valid, -- .valid
cp_data => burst_adapter_001_source0_data, -- .data
cp_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_001_source0_channel, -- .channel
rf_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 83,
FIFO_DEPTH => 3,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 18,
FIFO_DEPTH => 3,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 0,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 0,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 7,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 53,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 8,
PKT_BYTEEN_L => 8,
PKT_ADDR_H => 33,
PKT_ADDR_L => 9,
PKT_TRANS_COMPRESSED_READ => 34,
PKT_TRANS_POSTED => 35,
PKT_TRANS_WRITE => 36,
PKT_TRANS_READ => 37,
PKT_TRANS_LOCK => 38,
PKT_SRC_ID_H => 58,
PKT_SRC_ID_L => 55,
PKT_DEST_ID_H => 62,
PKT_DEST_ID_L => 59,
PKT_BURSTWRAP_H => 45,
PKT_BURSTWRAP_L => 43,
PKT_BYTE_CNT_H => 42,
PKT_BYTE_CNT_L => 40,
PKT_PROTECTION_H => 66,
PKT_PROTECTION_L => 64,
PKT_RESPONSE_STATUS_H => 72,
PKT_RESPONSE_STATUS_L => 71,
PKT_BURST_SIZE_H => 48,
PKT_BURST_SIZE_L => 46,
ST_CHANNEL_W => 13,
ST_DATA_W => 73,
AVS_BURSTCOUNT_W => 1,
SUPPRESS_0_BYTEEN_CMD => 1,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_002_source0_ready, -- cp.ready
cp_valid => burst_adapter_002_source0_valid, -- .valid
cp_data => burst_adapter_002_source0_data, -- .data
cp_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_002_source0_channel, -- .channel
rf_sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 74,
FIFO_DEPTH => 4,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 10,
FIFO_DEPTH => 4,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 0,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 0,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src5_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src5_valid, -- .valid
cp_data => cmd_xbar_demux_001_src5_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src5_channel, -- .channel
rf_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src6_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src6_valid, -- .valid
cp_data => cmd_xbar_demux_001_src6_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src6_channel, -- .channel
rf_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
green_leds_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src7_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src7_valid, -- .valid
cp_data => cmd_xbar_demux_001_src7_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src7_channel, -- .channel
rf_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
switches_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => switches_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => switches_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => switches_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => switches_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => switches_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => switches_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => switches_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src8_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src8_valid, -- .valid
cp_data => cmd_xbar_demux_001_src8_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src8_channel, -- .channel
rf_sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => crosser_out_ready, -- cp.ready
cp_valid => crosser_out_valid, -- .valid
cp_data => crosser_out_data, -- .data
cp_startofpacket => crosser_out_startofpacket, -- .startofpacket
cp_endofpacket => crosser_out_endofpacket, -- .endofpacket
cp_channel => crosser_out_channel, -- .channel
rf_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 34,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 0,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 0,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
timer_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src10_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src10_valid, -- .valid
cp_data => cmd_xbar_demux_001_src10_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src10_channel, -- .channel
rf_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src11_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src11_valid, -- .valid
cp_data => cmd_xbar_demux_001_src11_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src11_channel, -- .channel
rf_sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 80,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 60,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 61,
PKT_TRANS_POSTED => 62,
PKT_TRANS_WRITE => 63,
PKT_TRANS_READ => 64,
PKT_TRANS_LOCK => 65,
PKT_SRC_ID_H => 85,
PKT_SRC_ID_L => 82,
PKT_DEST_ID_H => 89,
PKT_DEST_ID_L => 86,
PKT_BURSTWRAP_H => 72,
PKT_BURSTWRAP_L => 70,
PKT_BYTE_CNT_H => 69,
PKT_BYTE_CNT_L => 67,
PKT_PROTECTION_H => 93,
PKT_PROTECTION_L => 91,
PKT_RESPONSE_STATUS_H => 99,
PKT_RESPONSE_STATUS_L => 98,
PKT_BURST_SIZE_H => 75,
PKT_BURST_SIZE_L => 73,
ST_CHANNEL_W => 13,
ST_DATA_W => 100,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src12_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src12_valid, -- .valid
cp_data => cmd_xbar_demux_001_src12_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src12_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src12_channel, -- .channel
rf_sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 101,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
addr_router : component niosII_system_addr_router
port map (
sink_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
addr_router_001 : component niosII_system_addr_router_001
port map (
sink_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_001_src_ready, -- src.ready
src_valid => addr_router_001_src_valid, -- .valid
src_data => addr_router_001_src_data, -- .data
src_channel => addr_router_001_src_channel, -- .channel
src_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_001_src_endofpacket -- .endofpacket
);
id_router : component niosII_system_id_router
port map (
sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component niosII_system_id_router_001
port map (
sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component niosII_system_id_router
port map (
sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component niosII_system_id_router_001
port map (
sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component niosII_system_id_router_004
port map (
sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component niosII_system_id_router_005
port map (
sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
id_router_006 : component niosII_system_id_router_005
port map (
sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_006_src_ready, -- src.ready
src_valid => id_router_006_src_valid, -- .valid
src_data => id_router_006_src_data, -- .data
src_channel => id_router_006_src_channel, -- .channel
src_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_006_src_endofpacket -- .endofpacket
);
id_router_007 : component niosII_system_id_router_005
port map (
sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_007_src_ready, -- src.ready
src_valid => id_router_007_src_valid, -- .valid
src_data => id_router_007_src_data, -- .data
src_channel => id_router_007_src_channel, -- .channel
src_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_007_src_endofpacket -- .endofpacket
);
id_router_008 : component niosII_system_id_router_005
port map (
sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_008_src_ready, -- src.ready
src_valid => id_router_008_src_valid, -- .valid
src_data => id_router_008_src_data, -- .data
src_channel => id_router_008_src_channel, -- .channel
src_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_008_src_endofpacket -- .endofpacket
);
id_router_009 : component niosII_system_id_router_005
port map (
sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_009_src_ready, -- src.ready
src_valid => id_router_009_src_valid, -- .valid
src_data => id_router_009_src_data, -- .data
src_channel => id_router_009_src_channel, -- .channel
src_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_009_src_endofpacket -- .endofpacket
);
id_router_010 : component niosII_system_id_router_005
port map (
sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_010_src_ready, -- src.ready
src_valid => id_router_010_src_valid, -- .valid
src_data => id_router_010_src_data, -- .data
src_channel => id_router_010_src_channel, -- .channel
src_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_010_src_endofpacket -- .endofpacket
);
id_router_011 : component niosII_system_id_router_005
port map (
sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_011_src_ready, -- src.ready
src_valid => id_router_011_src_valid, -- .valid
src_data => id_router_011_src_data, -- .data
src_channel => id_router_011_src_channel, -- .channel
src_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_011_src_endofpacket -- .endofpacket
);
id_router_012 : component niosII_system_id_router_005
port map (
sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_012_src_ready, -- src.ready
src_valid => id_router_012_src_valid, -- .valid
src_data => id_router_012_src_data, -- .data
src_channel => id_router_012_src_channel, -- .channel
src_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_012_src_endofpacket -- .endofpacket
);
burst_adapter : component niosii_system_burst_adapter
generic map (
PKT_ADDR_H => 42,
PKT_ADDR_L => 18,
PKT_BEGIN_BURST => 62,
PKT_BYTE_CNT_H => 51,
PKT_BYTE_CNT_L => 49,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_BURST_SIZE_H => 57,
PKT_BURST_SIZE_L => 55,
PKT_BURST_TYPE_H => 59,
PKT_BURST_TYPE_L => 58,
PKT_BURSTWRAP_H => 54,
PKT_BURSTWRAP_L => 52,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_WRITE => 45,
PKT_TRANS_READ => 46,
OUT_NARROW_SIZE => 0,
IN_NARROW_SIZE => 0,
OUT_FIXED => 0,
OUT_COMPLETE_WRAP => 0,
ST_DATA_W => 82,
ST_CHANNEL_W => 13,
OUT_BYTE_CNT_H => 50,
OUT_BURSTWRAP_H => 54,
COMPRESSED_READ_SUPPORT => 0,
BYTEENABLE_SYNTHESIS => 1,
PIPE_INPUTS => 0,
NO_WRAP_SUPPORT => 0,
BURSTWRAP_CONST_MASK => 3,
BURSTWRAP_CONST_VALUE => 3
)
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_src_valid, -- sink0.valid
sink0_data => width_adapter_src_data, -- .data
sink0_channel => width_adapter_src_channel, -- .channel
sink0_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_src_ready, -- .ready
source0_valid => burst_adapter_source0_valid, -- source0.valid
source0_data => burst_adapter_source0_data, -- .data
source0_channel => burst_adapter_source0_channel, -- .channel
source0_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_source0_ready -- .ready
);
burst_adapter_001 : component niosii_system_burst_adapter
generic map (
PKT_ADDR_H => 42,
PKT_ADDR_L => 18,
PKT_BEGIN_BURST => 62,
PKT_BYTE_CNT_H => 51,
PKT_BYTE_CNT_L => 49,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_BURST_SIZE_H => 57,
PKT_BURST_SIZE_L => 55,
PKT_BURST_TYPE_H => 59,
PKT_BURST_TYPE_L => 58,
PKT_BURSTWRAP_H => 54,
PKT_BURSTWRAP_L => 52,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_WRITE => 45,
PKT_TRANS_READ => 46,
OUT_NARROW_SIZE => 0,
IN_NARROW_SIZE => 0,
OUT_FIXED => 0,
OUT_COMPLETE_WRAP => 0,
ST_DATA_W => 82,
ST_CHANNEL_W => 13,
OUT_BYTE_CNT_H => 50,
OUT_BURSTWRAP_H => 54,
COMPRESSED_READ_SUPPORT => 0,
BYTEENABLE_SYNTHESIS => 1,
PIPE_INPUTS => 0,
NO_WRAP_SUPPORT => 0,
BURSTWRAP_CONST_MASK => 3,
BURSTWRAP_CONST_VALUE => 3
)
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_002_src_valid, -- sink0.valid
sink0_data => width_adapter_002_src_data, -- .data
sink0_channel => width_adapter_002_src_channel, -- .channel
sink0_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_002_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_002_src_ready, -- .ready
source0_valid => burst_adapter_001_source0_valid, -- source0.valid
source0_data => burst_adapter_001_source0_data, -- .data
source0_channel => burst_adapter_001_source0_channel, -- .channel
source0_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_001_source0_ready -- .ready
);
burst_adapter_002 : component niosii_system_burst_adapter_002
generic map (
PKT_ADDR_H => 33,
PKT_ADDR_L => 9,
PKT_BEGIN_BURST => 53,
PKT_BYTE_CNT_H => 42,
PKT_BYTE_CNT_L => 40,
PKT_BYTEEN_H => 8,
PKT_BYTEEN_L => 8,
PKT_BURST_SIZE_H => 48,
PKT_BURST_SIZE_L => 46,
PKT_BURST_TYPE_H => 50,
PKT_BURST_TYPE_L => 49,
PKT_BURSTWRAP_H => 45,
PKT_BURSTWRAP_L => 43,
PKT_TRANS_COMPRESSED_READ => 34,
PKT_TRANS_WRITE => 36,
PKT_TRANS_READ => 37,
OUT_NARROW_SIZE => 0,
IN_NARROW_SIZE => 0,
OUT_FIXED => 0,
OUT_COMPLETE_WRAP => 0,
ST_DATA_W => 73,
ST_CHANNEL_W => 13,
OUT_BYTE_CNT_H => 40,
OUT_BURSTWRAP_H => 45,
COMPRESSED_READ_SUPPORT => 0,
BYTEENABLE_SYNTHESIS => 1,
PIPE_INPUTS => 0,
NO_WRAP_SUPPORT => 0,
BURSTWRAP_CONST_MASK => 3,
BURSTWRAP_CONST_VALUE => 3
)
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_004_src_valid, -- sink0.valid
sink0_data => width_adapter_004_src_data, -- .data
sink0_channel => width_adapter_004_src_channel, -- .channel
sink0_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_004_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_004_src_ready, -- .ready
source0_valid => burst_adapter_002_source0_valid, -- source0.valid
source0_data => burst_adapter_002_source0_data, -- .data
source0_channel => burst_adapter_002_source0_channel, -- .channel
source0_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_002_source0_ready -- .ready
);
rst_controller : component niosii_system_rst_controller
generic map (
NUM_RESET_INPUTS => 2,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_system_rst_controller_001
generic map (
NUM_RESET_INPUTS => 2,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
cmd_xbar_demux : component niosII_system_cmd_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_src_ready, -- sink.ready
sink_channel => addr_router_src_channel, -- .channel
sink_data => addr_router_src_data, -- .data
sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_src_valid, -- .valid
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_src2_valid, -- .valid
src2_data => cmd_xbar_demux_src2_data, -- .data
src2_channel => cmd_xbar_demux_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_src3_valid, -- .valid
src3_data => cmd_xbar_demux_src3_data, -- .data
src3_channel => cmd_xbar_demux_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_src4_valid, -- .valid
src4_data => cmd_xbar_demux_src4_data, -- .data
src4_channel => cmd_xbar_demux_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_src4_endofpacket -- .endofpacket
);
cmd_xbar_demux_001 : component niosII_system_cmd_xbar_demux_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_001_src_ready, -- sink.ready
sink_channel => addr_router_001_src_channel, -- .channel
sink_data => addr_router_001_src_data, -- .data
sink_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_001_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_001_src_valid, -- .valid
src0_ready => cmd_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_001_src0_valid, -- .valid
src0_data => cmd_xbar_demux_001_src0_data, -- .data
src0_channel => cmd_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
src1_data => cmd_xbar_demux_001_src1_data, -- .data
src1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_001_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_001_src2_valid, -- .valid
src2_data => cmd_xbar_demux_001_src2_data, -- .data
src2_channel => cmd_xbar_demux_001_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_001_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_001_src3_valid, -- .valid
src3_data => cmd_xbar_demux_001_src3_data, -- .data
src3_channel => cmd_xbar_demux_001_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_001_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_001_src4_valid, -- .valid
src4_data => cmd_xbar_demux_001_src4_data, -- .data
src4_channel => cmd_xbar_demux_001_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_001_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_001_src5_valid, -- .valid
src5_data => cmd_xbar_demux_001_src5_data, -- .data
src5_channel => cmd_xbar_demux_001_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
src6_ready => cmd_xbar_demux_001_src6_ready, -- src6.ready
src6_valid => cmd_xbar_demux_001_src6_valid, -- .valid
src6_data => cmd_xbar_demux_001_src6_data, -- .data
src6_channel => cmd_xbar_demux_001_src6_channel, -- .channel
src6_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
src6_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
src7_ready => cmd_xbar_demux_001_src7_ready, -- src7.ready
src7_valid => cmd_xbar_demux_001_src7_valid, -- .valid
src7_data => cmd_xbar_demux_001_src7_data, -- .data
src7_channel => cmd_xbar_demux_001_src7_channel, -- .channel
src7_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
src7_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
src8_ready => cmd_xbar_demux_001_src8_ready, -- src8.ready
src8_valid => cmd_xbar_demux_001_src8_valid, -- .valid
src8_data => cmd_xbar_demux_001_src8_data, -- .data
src8_channel => cmd_xbar_demux_001_src8_channel, -- .channel
src8_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket
src8_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket
src9_ready => cmd_xbar_demux_001_src9_ready, -- src9.ready
src9_valid => cmd_xbar_demux_001_src9_valid, -- .valid
src9_data => cmd_xbar_demux_001_src9_data, -- .data
src9_channel => cmd_xbar_demux_001_src9_channel, -- .channel
src9_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket
src9_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket
src10_ready => cmd_xbar_demux_001_src10_ready, -- src10.ready
src10_valid => cmd_xbar_demux_001_src10_valid, -- .valid
src10_data => cmd_xbar_demux_001_src10_data, -- .data
src10_channel => cmd_xbar_demux_001_src10_channel, -- .channel
src10_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket
src10_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket
src11_ready => cmd_xbar_demux_001_src11_ready, -- src11.ready
src11_valid => cmd_xbar_demux_001_src11_valid, -- .valid
src11_data => cmd_xbar_demux_001_src11_data, -- .data
src11_channel => cmd_xbar_demux_001_src11_channel, -- .channel
src11_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket
src11_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket
src12_ready => cmd_xbar_demux_001_src12_ready, -- src12.ready
src12_valid => cmd_xbar_demux_001_src12_valid, -- .valid
src12_data => cmd_xbar_demux_001_src12_data, -- .data
src12_channel => cmd_xbar_demux_001_src12_channel, -- .channel
src12_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket
src12_endofpacket => cmd_xbar_demux_001_src12_endofpacket -- .endofpacket
);
cmd_xbar_mux : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_src_ready, -- src.ready
src_valid => cmd_xbar_mux_src_valid, -- .valid
src_data => cmd_xbar_mux_src_data, -- .data
src_channel => cmd_xbar_mux_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src0_valid, -- .valid
sink0_channel => cmd_xbar_demux_src0_channel, -- .channel
sink0_data => cmd_xbar_demux_src0_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src0_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src0_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src0_endofpacket -- .endofpacket
);
cmd_xbar_mux_001 : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_001_src_ready, -- src.ready
src_valid => cmd_xbar_mux_001_src_valid, -- .valid
src_data => cmd_xbar_mux_001_src_data, -- .data
src_channel => cmd_xbar_mux_001_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src1_valid, -- .valid
sink0_channel => cmd_xbar_demux_src1_channel, -- .channel
sink0_data => cmd_xbar_demux_src1_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src1_endofpacket -- .endofpacket
);
cmd_xbar_mux_002 : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_002_src_ready, -- src.ready
src_valid => cmd_xbar_mux_002_src_valid, -- .valid
src_data => cmd_xbar_mux_002_src_data, -- .data
src_channel => cmd_xbar_mux_002_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src2_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src2_valid, -- .valid
sink0_channel => cmd_xbar_demux_src2_channel, -- .channel
sink0_data => cmd_xbar_demux_src2_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src2_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src2_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src2_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src2_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src2_endofpacket -- .endofpacket
);
cmd_xbar_mux_003 : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_003_src_ready, -- src.ready
src_valid => cmd_xbar_mux_003_src_valid, -- .valid
src_data => cmd_xbar_mux_003_src_data, -- .data
src_channel => cmd_xbar_mux_003_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src3_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src3_valid, -- .valid
sink0_channel => cmd_xbar_demux_src3_channel, -- .channel
sink0_data => cmd_xbar_demux_src3_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src3_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src3_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src3_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src3_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src3_endofpacket -- .endofpacket
);
cmd_xbar_mux_004 : component niosII_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_004_src_ready, -- src.ready
src_valid => cmd_xbar_mux_004_src_valid, -- .valid
src_data => cmd_xbar_mux_004_src_data, -- .data
src_channel => cmd_xbar_mux_004_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_004_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_004_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src4_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src4_valid, -- .valid
sink0_channel => cmd_xbar_demux_src4_channel, -- .channel
sink0_data => cmd_xbar_demux_src4_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src4_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src4_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src4_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src4_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src4_endofpacket -- .endofpacket
);
rsp_xbar_demux : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_src_ready, -- sink.ready
sink_channel => id_router_src_channel, -- .channel
sink_data => id_router_src_data, -- .data
sink_startofpacket => id_router_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_src1_valid, -- .valid
src1_data => rsp_xbar_demux_src1_data, -- .data
src1_channel => rsp_xbar_demux_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_001_src_ready, -- sink.ready
sink_channel => width_adapter_001_src_channel, -- .channel
sink_data => width_adapter_001_src_data, -- .data
sink_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
src1_data => rsp_xbar_demux_001_src1_data, -- .data
src1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_001_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_002_src_ready, -- sink.ready
sink_channel => id_router_002_src_channel, -- .channel
sink_data => id_router_002_src_data, -- .data
sink_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_002_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_002_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_002_src1_valid, -- .valid
src1_data => rsp_xbar_demux_002_src1_data, -- .data
src1_channel => rsp_xbar_demux_002_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_002_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_003_src_ready, -- sink.ready
sink_channel => width_adapter_003_src_channel, -- .channel
sink_data => width_adapter_003_src_data, -- .data
sink_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_003_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_003_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_003_src1_valid, -- .valid
src1_data => rsp_xbar_demux_003_src1_data, -- .data
src1_channel => rsp_xbar_demux_003_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_003_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component niosII_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_005_src_ready, -- sink.ready
sink_channel => width_adapter_005_src_channel, -- .channel
sink_data => width_adapter_005_src_data, -- .data
sink_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_005_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_004_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_004_src1_valid, -- .valid
src1_data => rsp_xbar_demux_004_src1_data, -- .data
src1_channel => rsp_xbar_demux_004_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_004_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_004_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_005_src_ready, -- sink.ready
sink_channel => id_router_005_src_channel, -- .channel
sink_data => id_router_005_src_data, -- .data
sink_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_006 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_006_src_ready, -- sink.ready
sink_channel => id_router_006_src_channel, -- .channel
sink_data => id_router_006_src_data, -- .data
sink_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_006_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_006_src_valid, -- .valid
src0_ready => rsp_xbar_demux_006_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_006_src0_valid, -- .valid
src0_data => rsp_xbar_demux_006_src0_data, -- .data
src0_channel => rsp_xbar_demux_006_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_007 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_007_src_ready, -- sink.ready
sink_channel => id_router_007_src_channel, -- .channel
sink_data => id_router_007_src_data, -- .data
sink_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_007_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_007_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_007_src0_valid, -- .valid
src0_data => rsp_xbar_demux_007_src0_data, -- .data
src0_channel => rsp_xbar_demux_007_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_007_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_008 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_008_src_ready, -- sink.ready
sink_channel => id_router_008_src_channel, -- .channel
sink_data => id_router_008_src_data, -- .data
sink_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_008_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_008_src_valid, -- .valid
src0_ready => rsp_xbar_demux_008_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_008_src0_valid, -- .valid
src0_data => rsp_xbar_demux_008_src0_data, -- .data
src0_channel => rsp_xbar_demux_008_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_008_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_009 : component niosII_system_rsp_xbar_demux_005
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_009_src_ready, -- sink.ready
sink_channel => id_router_009_src_channel, -- .channel
sink_data => id_router_009_src_data, -- .data
sink_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_009_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_009_src_valid, -- .valid
src0_ready => rsp_xbar_demux_009_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_009_src0_valid, -- .valid
src0_data => rsp_xbar_demux_009_src0_data, -- .data
src0_channel => rsp_xbar_demux_009_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_009_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_010 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_010_src_ready, -- sink.ready
sink_channel => id_router_010_src_channel, -- .channel
sink_data => id_router_010_src_data, -- .data
sink_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_010_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_010_src_valid, -- .valid
src0_ready => rsp_xbar_demux_010_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_010_src0_valid, -- .valid
src0_data => rsp_xbar_demux_010_src0_data, -- .data
src0_channel => rsp_xbar_demux_010_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_010_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_011 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_011_src_ready, -- sink.ready
sink_channel => id_router_011_src_channel, -- .channel
sink_data => id_router_011_src_data, -- .data
sink_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_011_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_011_src_valid, -- .valid
src0_ready => rsp_xbar_demux_011_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_011_src0_valid, -- .valid
src0_data => rsp_xbar_demux_011_src0_data, -- .data
src0_channel => rsp_xbar_demux_011_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_011_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_012 : component niosII_system_rsp_xbar_demux_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_012_src_ready, -- sink.ready
sink_channel => id_router_012_src_channel, -- .channel
sink_data => id_router_012_src_data, -- .data
sink_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_012_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_012_src_valid, -- .valid
src0_ready => rsp_xbar_demux_012_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_012_src0_valid, -- .valid
src0_data => rsp_xbar_demux_012_src0_data, -- .data
src0_channel => rsp_xbar_demux_012_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component niosII_system_rsp_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src0_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src0_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src0_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src0_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src0_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src0_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src0_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src0_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux_001 : component niosII_system_rsp_xbar_mux_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_001_src_ready, -- src.ready
src_valid => rsp_xbar_mux_001_src_valid, -- .valid
src_data => rsp_xbar_mux_001_src_data, -- .data
src_channel => rsp_xbar_mux_001_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src1_valid, -- .valid
sink0_channel => rsp_xbar_demux_src1_channel, -- .channel
sink0_data => rsp_xbar_demux_src1_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src1_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src1_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src1_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src1_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src1_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src1_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src1_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src1_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src1_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src1_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src1_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src1_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src1_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src1_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src1_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src1_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket, -- .endofpacket
sink6_ready => rsp_xbar_demux_006_src0_ready, -- sink6.ready
sink6_valid => rsp_xbar_demux_006_src0_valid, -- .valid
sink6_channel => rsp_xbar_demux_006_src0_channel, -- .channel
sink6_data => rsp_xbar_demux_006_src0_data, -- .data
sink6_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
sink6_endofpacket => rsp_xbar_demux_006_src0_endofpacket, -- .endofpacket
sink7_ready => rsp_xbar_demux_007_src0_ready, -- sink7.ready
sink7_valid => rsp_xbar_demux_007_src0_valid, -- .valid
sink7_channel => rsp_xbar_demux_007_src0_channel, -- .channel
sink7_data => rsp_xbar_demux_007_src0_data, -- .data
sink7_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
sink7_endofpacket => rsp_xbar_demux_007_src0_endofpacket, -- .endofpacket
sink8_ready => rsp_xbar_demux_008_src0_ready, -- sink8.ready
sink8_valid => rsp_xbar_demux_008_src0_valid, -- .valid
sink8_channel => rsp_xbar_demux_008_src0_channel, -- .channel
sink8_data => rsp_xbar_demux_008_src0_data, -- .data
sink8_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
sink8_endofpacket => rsp_xbar_demux_008_src0_endofpacket, -- .endofpacket
sink9_ready => crosser_001_out_ready, -- sink9.ready
sink9_valid => crosser_001_out_valid, -- .valid
sink9_channel => crosser_001_out_channel, -- .channel
sink9_data => crosser_001_out_data, -- .data
sink9_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
sink9_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
sink10_ready => rsp_xbar_demux_010_src0_ready, -- sink10.ready
sink10_valid => rsp_xbar_demux_010_src0_valid, -- .valid
sink10_channel => rsp_xbar_demux_010_src0_channel, -- .channel
sink10_data => rsp_xbar_demux_010_src0_data, -- .data
sink10_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
sink10_endofpacket => rsp_xbar_demux_010_src0_endofpacket, -- .endofpacket
sink11_ready => rsp_xbar_demux_011_src0_ready, -- sink11.ready
sink11_valid => rsp_xbar_demux_011_src0_valid, -- .valid
sink11_channel => rsp_xbar_demux_011_src0_channel, -- .channel
sink11_data => rsp_xbar_demux_011_src0_data, -- .data
sink11_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
sink11_endofpacket => rsp_xbar_demux_011_src0_endofpacket, -- .endofpacket
sink12_ready => rsp_xbar_demux_012_src0_ready, -- sink12.ready
sink12_valid => rsp_xbar_demux_012_src0_valid, -- .valid
sink12_channel => rsp_xbar_demux_012_src0_channel, -- .channel
sink12_data => rsp_xbar_demux_012_src0_data, -- .data
sink12_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
sink12_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
);
width_adapter : component niosii_system_width_adapter
generic map (
IN_PKT_ADDR_H => 60,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 69,
IN_PKT_BYTE_CNT_L => 67,
IN_PKT_TRANS_COMPRESSED_READ => 61,
IN_PKT_BURSTWRAP_H => 72,
IN_PKT_BURSTWRAP_L => 70,
IN_PKT_BURST_SIZE_H => 75,
IN_PKT_BURST_SIZE_L => 73,
IN_PKT_RESPONSE_STATUS_H => 99,
IN_PKT_RESPONSE_STATUS_L => 98,
IN_PKT_TRANS_EXCLUSIVE => 66,
IN_PKT_BURST_TYPE_H => 77,
IN_PKT_BURST_TYPE_L => 76,
IN_ST_DATA_W => 100,
OUT_PKT_ADDR_H => 42,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 51,
OUT_PKT_BYTE_CNT_L => 49,
OUT_PKT_TRANS_COMPRESSED_READ => 43,
OUT_PKT_BURST_SIZE_H => 57,
OUT_PKT_BURST_SIZE_L => 55,
OUT_PKT_RESPONSE_STATUS_H => 81,
OUT_PKT_RESPONSE_STATUS_L => 80,
OUT_PKT_TRANS_EXCLUSIVE => 48,
OUT_PKT_BURST_TYPE_H => 59,
OUT_PKT_BURST_TYPE_L => 58,
OUT_ST_DATA_W => 82,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_001_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_001_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_001_src_ready, -- .ready
in_data => cmd_xbar_mux_001_src_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_001 : component niosii_system_width_adapter_001
generic map (
IN_PKT_ADDR_H => 42,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 51,
IN_PKT_BYTE_CNT_L => 49,
IN_PKT_TRANS_COMPRESSED_READ => 43,
IN_PKT_BURSTWRAP_H => 54,
IN_PKT_BURSTWRAP_L => 52,
IN_PKT_BURST_SIZE_H => 57,
IN_PKT_BURST_SIZE_L => 55,
IN_PKT_RESPONSE_STATUS_H => 81,
IN_PKT_RESPONSE_STATUS_L => 80,
IN_PKT_TRANS_EXCLUSIVE => 48,
IN_PKT_BURST_TYPE_H => 59,
IN_PKT_BURST_TYPE_L => 58,
IN_ST_DATA_W => 82,
OUT_PKT_ADDR_H => 60,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 69,
OUT_PKT_BYTE_CNT_L => 67,
OUT_PKT_TRANS_COMPRESSED_READ => 61,
OUT_PKT_BURST_SIZE_H => 75,
OUT_PKT_BURST_SIZE_L => 73,
OUT_PKT_RESPONSE_STATUS_H => 99,
OUT_PKT_RESPONSE_STATUS_L => 98,
OUT_PKT_TRANS_EXCLUSIVE => 66,
OUT_PKT_BURST_TYPE_H => 77,
OUT_PKT_BURST_TYPE_L => 76,
OUT_ST_DATA_W => 100,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_001_src_valid, -- sink.valid
in_channel => id_router_001_src_channel, -- .channel
in_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
in_ready => id_router_001_src_ready, -- .ready
in_data => id_router_001_src_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_002 : component niosii_system_width_adapter
generic map (
IN_PKT_ADDR_H => 60,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 69,
IN_PKT_BYTE_CNT_L => 67,
IN_PKT_TRANS_COMPRESSED_READ => 61,
IN_PKT_BURSTWRAP_H => 72,
IN_PKT_BURSTWRAP_L => 70,
IN_PKT_BURST_SIZE_H => 75,
IN_PKT_BURST_SIZE_L => 73,
IN_PKT_RESPONSE_STATUS_H => 99,
IN_PKT_RESPONSE_STATUS_L => 98,
IN_PKT_TRANS_EXCLUSIVE => 66,
IN_PKT_BURST_TYPE_H => 77,
IN_PKT_BURST_TYPE_L => 76,
IN_ST_DATA_W => 100,
OUT_PKT_ADDR_H => 42,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 51,
OUT_PKT_BYTE_CNT_L => 49,
OUT_PKT_TRANS_COMPRESSED_READ => 43,
OUT_PKT_BURST_SIZE_H => 57,
OUT_PKT_BURST_SIZE_L => 55,
OUT_PKT_RESPONSE_STATUS_H => 81,
OUT_PKT_RESPONSE_STATUS_L => 80,
OUT_PKT_TRANS_EXCLUSIVE => 48,
OUT_PKT_BURST_TYPE_H => 59,
OUT_PKT_BURST_TYPE_L => 58,
OUT_ST_DATA_W => 82,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_003_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_003_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_003_src_ready, -- .ready
in_data => cmd_xbar_mux_003_src_data, -- .data
out_endofpacket => width_adapter_002_src_endofpacket, -- src.endofpacket
out_data => width_adapter_002_src_data, -- .data
out_channel => width_adapter_002_src_channel, -- .channel
out_valid => width_adapter_002_src_valid, -- .valid
out_ready => width_adapter_002_src_ready, -- .ready
out_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_003 : component niosii_system_width_adapter_001
generic map (
IN_PKT_ADDR_H => 42,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 51,
IN_PKT_BYTE_CNT_L => 49,
IN_PKT_TRANS_COMPRESSED_READ => 43,
IN_PKT_BURSTWRAP_H => 54,
IN_PKT_BURSTWRAP_L => 52,
IN_PKT_BURST_SIZE_H => 57,
IN_PKT_BURST_SIZE_L => 55,
IN_PKT_RESPONSE_STATUS_H => 81,
IN_PKT_RESPONSE_STATUS_L => 80,
IN_PKT_TRANS_EXCLUSIVE => 48,
IN_PKT_BURST_TYPE_H => 59,
IN_PKT_BURST_TYPE_L => 58,
IN_ST_DATA_W => 82,
OUT_PKT_ADDR_H => 60,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 69,
OUT_PKT_BYTE_CNT_L => 67,
OUT_PKT_TRANS_COMPRESSED_READ => 61,
OUT_PKT_BURST_SIZE_H => 75,
OUT_PKT_BURST_SIZE_L => 73,
OUT_PKT_RESPONSE_STATUS_H => 99,
OUT_PKT_RESPONSE_STATUS_L => 98,
OUT_PKT_TRANS_EXCLUSIVE => 66,
OUT_PKT_BURST_TYPE_H => 77,
OUT_PKT_BURST_TYPE_L => 76,
OUT_ST_DATA_W => 100,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_003_src_valid, -- sink.valid
in_channel => id_router_003_src_channel, -- .channel
in_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
in_ready => id_router_003_src_ready, -- .ready
in_data => id_router_003_src_data, -- .data
out_endofpacket => width_adapter_003_src_endofpacket, -- src.endofpacket
out_data => width_adapter_003_src_data, -- .data
out_channel => width_adapter_003_src_channel, -- .channel
out_valid => width_adapter_003_src_valid, -- .valid
out_ready => width_adapter_003_src_ready, -- .ready
out_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_004 : component niosii_system_width_adapter_004
generic map (
IN_PKT_ADDR_H => 60,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 69,
IN_PKT_BYTE_CNT_L => 67,
IN_PKT_TRANS_COMPRESSED_READ => 61,
IN_PKT_BURSTWRAP_H => 72,
IN_PKT_BURSTWRAP_L => 70,
IN_PKT_BURST_SIZE_H => 75,
IN_PKT_BURST_SIZE_L => 73,
IN_PKT_RESPONSE_STATUS_H => 99,
IN_PKT_RESPONSE_STATUS_L => 98,
IN_PKT_TRANS_EXCLUSIVE => 66,
IN_PKT_BURST_TYPE_H => 77,
IN_PKT_BURST_TYPE_L => 76,
IN_ST_DATA_W => 100,
OUT_PKT_ADDR_H => 33,
OUT_PKT_ADDR_L => 9,
OUT_PKT_DATA_H => 7,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 8,
OUT_PKT_BYTEEN_L => 8,
OUT_PKT_BYTE_CNT_H => 42,
OUT_PKT_BYTE_CNT_L => 40,
OUT_PKT_TRANS_COMPRESSED_READ => 34,
OUT_PKT_BURST_SIZE_H => 48,
OUT_PKT_BURST_SIZE_L => 46,
OUT_PKT_RESPONSE_STATUS_H => 72,
OUT_PKT_RESPONSE_STATUS_L => 71,
OUT_PKT_TRANS_EXCLUSIVE => 39,
OUT_PKT_BURST_TYPE_H => 50,
OUT_PKT_BURST_TYPE_L => 49,
OUT_ST_DATA_W => 73,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_004_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_004_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_004_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_004_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_004_src_ready, -- .ready
in_data => cmd_xbar_mux_004_src_data, -- .data
out_endofpacket => width_adapter_004_src_endofpacket, -- src.endofpacket
out_data => width_adapter_004_src_data, -- .data
out_channel => width_adapter_004_src_channel, -- .channel
out_valid => width_adapter_004_src_valid, -- .valid
out_ready => width_adapter_004_src_ready, -- .ready
out_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_005 : component niosii_system_width_adapter_005
generic map (
IN_PKT_ADDR_H => 33,
IN_PKT_ADDR_L => 9,
IN_PKT_DATA_H => 7,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 8,
IN_PKT_BYTEEN_L => 8,
IN_PKT_BYTE_CNT_H => 42,
IN_PKT_BYTE_CNT_L => 40,
IN_PKT_TRANS_COMPRESSED_READ => 34,
IN_PKT_BURSTWRAP_H => 45,
IN_PKT_BURSTWRAP_L => 43,
IN_PKT_BURST_SIZE_H => 48,
IN_PKT_BURST_SIZE_L => 46,
IN_PKT_RESPONSE_STATUS_H => 72,
IN_PKT_RESPONSE_STATUS_L => 71,
IN_PKT_TRANS_EXCLUSIVE => 39,
IN_PKT_BURST_TYPE_H => 50,
IN_PKT_BURST_TYPE_L => 49,
IN_ST_DATA_W => 73,
OUT_PKT_ADDR_H => 60,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 69,
OUT_PKT_BYTE_CNT_L => 67,
OUT_PKT_TRANS_COMPRESSED_READ => 61,
OUT_PKT_BURST_SIZE_H => 75,
OUT_PKT_BURST_SIZE_L => 73,
OUT_PKT_RESPONSE_STATUS_H => 99,
OUT_PKT_RESPONSE_STATUS_L => 98,
OUT_PKT_TRANS_EXCLUSIVE => 66,
OUT_PKT_BURST_TYPE_H => 77,
OUT_PKT_BURST_TYPE_L => 76,
OUT_ST_DATA_W => 100,
ST_CHANNEL_W => 13,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_004_src_valid, -- sink.valid
in_channel => id_router_004_src_channel, -- .channel
in_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
in_ready => id_router_004_src_ready, -- .ready
in_data => id_router_004_src_data, -- .data
out_endofpacket => width_adapter_005_src_endofpacket, -- src.endofpacket
out_data => width_adapter_005_src_data, -- .data
out_channel => width_adapter_005_src_channel, -- .channel
out_valid => width_adapter_005_src_valid, -- .valid
out_ready => width_adapter_005_src_ready, -- .ready
out_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
crosser : component altera_avalon_st_handshake_clock_crosser
generic map (
DATA_WIDTH => 100,
BITS_PER_SYMBOL => 100,
USE_PACKETS => 1,
USE_CHANNEL => 1,
CHANNEL_WIDTH => 13,
USE_ERROR => 0,
ERROR_WIDTH => 1,
VALID_SYNC_DEPTH => 2,
READY_SYNC_DEPTH => 2,
USE_OUTPUT_PIPELINE => 0
)
port map (
in_clk => altpll_0_c1_clk, -- in_clk.clk
in_reset => rst_controller_reset_out_reset, -- in_clk_reset.reset
out_clk => clk_clk, -- out_clk.clk
out_reset => rst_controller_001_reset_out_reset, -- out_clk_reset.reset
in_ready => cmd_xbar_demux_001_src9_ready, -- in.ready
in_valid => cmd_xbar_demux_001_src9_valid, -- .valid
in_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket
in_channel => cmd_xbar_demux_001_src9_channel, -- .channel
in_data => cmd_xbar_demux_001_src9_data, -- .data
out_ready => crosser_out_ready, -- out.ready
out_valid => crosser_out_valid, -- .valid
out_startofpacket => crosser_out_startofpacket, -- .startofpacket
out_endofpacket => crosser_out_endofpacket, -- .endofpacket
out_channel => crosser_out_channel, -- .channel
out_data => crosser_out_data, -- .data
in_empty => '0', -- (terminated)
in_error => '0', -- (terminated)
out_empty => open, -- (terminated)
out_error => open -- (terminated)
);
crosser_001 : component altera_avalon_st_handshake_clock_crosser
generic map (
DATA_WIDTH => 100,
BITS_PER_SYMBOL => 100,
USE_PACKETS => 1,
USE_CHANNEL => 1,
CHANNEL_WIDTH => 13,
USE_ERROR => 0,
ERROR_WIDTH => 1,
VALID_SYNC_DEPTH => 2,
READY_SYNC_DEPTH => 2,
USE_OUTPUT_PIPELINE => 0
)
port map (
in_clk => clk_clk, -- in_clk.clk
in_reset => rst_controller_001_reset_out_reset, -- in_clk_reset.reset
out_clk => altpll_0_c1_clk, -- out_clk.clk
out_reset => rst_controller_reset_out_reset, -- out_clk_reset.reset
in_ready => rsp_xbar_demux_009_src0_ready, -- in.ready
in_valid => rsp_xbar_demux_009_src0_valid, -- .valid
in_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
in_endofpacket => rsp_xbar_demux_009_src0_endofpacket, -- .endofpacket
in_channel => rsp_xbar_demux_009_src0_channel, -- .channel
in_data => rsp_xbar_demux_009_src0_data, -- .data
out_ready => crosser_001_out_ready, -- out.ready
out_valid => crosser_001_out_valid, -- .valid
out_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
out_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
out_channel => crosser_001_out_channel, -- .channel
out_data => crosser_001_out_data, -- .data
in_empty => '0', -- (terminated)
in_error => '0', -- (terminated)
out_empty => open, -- (terminated)
out_error => open -- (terminated)
);
irq_mapper : component niosII_system_irq_mapper
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
sender_irq => nios2_qsys_0_d_irq_irq -- sender.irq
);
reset_reset_n_ports_inv <= not reset_reset_n;
sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_write;
sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_read;
sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_byteenable;
jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write;
jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read;
green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv <= not green_leds_s1_translator_avalon_anti_slave_0_write;
timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not timer_0_s1_translator_avalon_anti_slave_0_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of niosII_system
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/syncram_1rw_inferred.vhdl
|
1
|
1664
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity syncram_1rw_inferred is
generic (
addr_bits : natural := 10;
data_bits : natural := 8
);
port (
clk : in std_ulogic;
en : in std_ulogic;
we : in std_ulogic;
addr : in std_ulogic_vector((addr_bits-1) downto 0);
wdata : in std_ulogic_vector((data_bits-1) downto 0);
rdata : out std_ulogic_vector((data_bits-1) downto 0)
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/data/cache/cpu_l1mem_data_cache_dp-rtl.vhdl
|
1
|
45685
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the Licensee for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library sys;
use sys.sys_config_pkg.all;
use sys.sys_pkg.all;
library tech;
use work.cpu_l1mem_data_cache_pkg.all;
use work.cpu_l1mem_data_cache_config_pkg.all;
use work.cpu_types_pkg.all;
architecture rtl of cpu_l1mem_data_cache_dp is
type reg_type is record
b_request_size : cpu_data_size_type;
b_request_poffset : cpu_poffset_type;
b_request_vpn : cpu_vpn_type;
b_request_data : cpu_word_type;
b_bus_op_size : cpu_data_size_type;
b_bus_op_paddr : cpu_paddr_type;
b_stb_array_size : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_data_size_bits-1 downto 0);
b_stb_array_paddr : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_paddr_bits-1 downto 0);
b_stb_array_data : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_word_bits-1 downto 0);
end record;
type comb_type is record
b_replace_rstate : cpu_l1mem_data_cache_replace_state_type;
b_replace_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_tram_rdata : std_ulogic_vector2(cpu_l1mem_data_cache_assoc-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_dram_rdata : std_ulogic_vector2((cpu_l1mem_data_cache_assoc*cpu_word_bytes)-1 downto 0,
byte_bits-1 downto 0);
b_bus_op_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_bus_op_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_bus_op_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
b_request_ppn : cpu_ppn_type;
b_request_paddr : cpu_paddr_type;
b_request_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_request_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_request_block_word_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
b_request_word_byte_offset : std_ulogic_vector(cpu_log2_word_bytes-1 downto 0);
b_request_size_mask : std_ulogic_vector(cpu_log2_word_bytes-1 downto 0);
b_request_cache_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_cache_way_read_data_le : std_ulogic_vector2(cpu_l1mem_data_cache_assoc-1 downto 0,
cpu_word_bits-1 downto 0);
b_cache_read_data_le : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_cache_read_data_be : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_cache_read_data : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_result_data_bus : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_result_data_cache_or_bus_unshifted : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_result_data_cache_or_bus_shifter : std_ulogic_vector2(cpu_log2_word_bytes downto 0,
cpu_word_bits-1 downto 0);
b_result_data_cache_or_bus_shifted : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_result_data_stb : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_stb_update_data_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_tag : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_stb_array_index : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_index_bits-1 downto 0);
b_stb_array_block_word_offset : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
b_stb_array_word_byte_offset : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_log2_word_bytes-1 downto 0);
b_stb_array_size_mask : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_log2_word_bytes-1 downto 0);
b_stb_array_size_next : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_data_size_bits-1 downto 0);
b_stb_array_paddr_next : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_paddr_bits-1 downto 0);
b_stb_array_data_next : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_word_bits-1 downto 0);
b_stb_head_paddr : cpu_paddr_type;
b_stb_head_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_request_stb_array_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_index_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_block_word_offset_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_word_byte_offset_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_size_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_block_change_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_block_change_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_stb_array_block_change_index_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_block_change_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_result_paddr : cpu_paddr_type;
b_result_data : cpu_word_type;
b_replace_windex : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_replace_wstate : cpu_l1mem_data_cache_replace_state_type;
b_vram_waddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_mram_waddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_new_request_size : cpu_data_size_type;
a_new_request_poffset : cpu_poffset_type;
a_new_request_vpn : cpu_vpn_type;
a_new_request_data : cpu_word_type;
a_request_poffset : cpu_poffset_type;
a_request_vpn : cpu_vpn_type;
a_request_ppn : cpu_ppn_type;
a_request_data : cpu_word_type;
a_request_bus_op_data : cpu_word_type;
a_request_size : cpu_data_size_type;
a_request_size_dec : std_ulogic_vector(cpu_log2_word_bytes downto 0);
a_request_word_byte_mask_by_size : std_ulogic_vector2(cpu_log2_word_bytes downto 0,
cpu_word_bytes-1 downto 0);
a_request_word_byte_mask : std_ulogic_vector(cpu_word_bytes-1 downto 0);
a_request_dram_banken : std_ulogic_vector(cpu_l1mem_data_cache_assoc*cpu_word_bytes-1 downto 0);
a_request_vaddr : cpu_vaddr_type;
a_request_paddr : cpu_paddr_type;
a_request_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_request_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_request_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_stb_array_paddr : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_paddr_bits-1 downto 0);
a_stb_array_data : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_word_bits-1 downto 0);
a_stb_array_size : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_data_size_bits-1 downto 0);
a_stb_array_size_mask : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_log2_word_bytes-1 downto 0);
a_stb_head_size : cpu_data_size_type;
a_stb_head_paddr : cpu_paddr_type;
a_stb_head_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_stb_head_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_stb_head_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_stb_head_data : cpu_word_type;
a_stb_head_size_dec : std_ulogic_vector(cpu_log2_word_bytes downto 0);
a_stb_word_byte_mask_by_size : std_ulogic_vector2(cpu_log2_word_bytes downto 0,
cpu_word_bytes-1 downto 0);
a_stb_word_byte_mask : std_ulogic_vector(cpu_word_bytes-1 downto 0);
a_stb_dram_banken : std_ulogic_vector((cpu_l1mem_data_cache_assoc*cpu_word_bytes)-1 downto 0);
a_stb_dram_wdata_sel : std_ulogic_vector(cpu_log2_word_bytes-1 downto 0);
a_stb_dram_wdata_word : std_ulogic_vector(cpu_word_bits-1 downto 0);
a_bus_op_paddr_block_word_offset_next : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
a_bus_op_paddr : cpu_paddr_type;
a_bus_op_size : cpu_data_size_type;
a_bus_op_data : cpu_word_type;
a_bus_op_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_bus_op_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_bus_op_cache_wtag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_bus_op_cache_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_bus_op_cache_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_bus_op_tram_wdata_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_bus_op_sys_paddr : cpu_paddr_type;
a_bus_op_sys_data : cpu_word_type;
a_bus_op_dram_banken : std_ulogic_vector((cpu_l1mem_data_cache_assoc*cpu_word_bytes)-1 downto 0);
a_bus_op_dram_wdata_word : std_ulogic_vector(cpu_word_bits-1 downto 0);
a_sys_size : sys_transfer_size_type;
a_sys_paddr : sys_paddr_type;
a_sys_data : sys_bus_type;
a_vtram_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_rmdram_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_rmdram_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_vram_raddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_mram_raddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_tram_addr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_tram_wtag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_tram_wdata : std_ulogic_vector2(cpu_l1mem_data_cache_assoc-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_dram_banken : std_ulogic_vector(cpu_l1mem_data_cache_assoc*cpu_word_bytes-1 downto 0);
a_dram_addr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
a_dram_wdata_word : std_ulogic_vector(cpu_word_bits-1 downto 0);
a_dram_wdata_bytes_le : std_ulogic_vector2(cpu_word_bytes-1 downto 0, byte_bits-1 downto 0);
a_dram_wdata_bytes_be : std_ulogic_vector2(cpu_word_bytes-1 downto 0, byte_bits-1 downto 0);
a_dram_wdata_bytes : std_ulogic_vector2(cpu_word_bytes-1 downto 0, byte_bits-1 downto 0);
a_dram_wdata : std_ulogic_vector2(cpu_l1mem_data_cache_assoc*cpu_word_bytes-1 downto 0,
byte_bits-1 downto 0);
a_replace_rindex : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
end record;
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.b_replace_rstate <= cpu_l1mem_data_cache_replace_dp_out.rstate;
c.b_tram_rdata <= cpu_l1mem_data_cache_dp_in_tram.rdata;
c.b_dram_rdata <= cpu_l1mem_data_cache_dp_in_dram.rdata;
b_replace_tag_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_l1mem_data_cache_tag_bits,
sel_bits => cpu_l1mem_data_cache_assoc
)
port map (
din => c.b_tram_rdata,
sel => cpu_l1mem_data_cache_dp_in_ctrl.b_replace_way,
dout => c.b_replace_tag
);
----------------------------------
c.b_request_ppn <= cpu_mmu_data_dp_out.ppn;
c.b_request_paddr <= cpu_mmu_data_dp_out.ppn & r.b_request_poffset;
c.b_request_tag <= c.b_request_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
c.b_request_index <= c.b_request_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1
downto cpu_l1mem_data_cache_offset_bits);
c.b_request_block_word_offset <= c.b_request_paddr(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes);
c.b_request_word_byte_offset <= c.b_request_paddr(cpu_log2_word_bytes-1 downto 0);
c.b_request_size_mask(0) <= all_zeros(r.b_request_size);
b_request_size_mask_gen : for n in 1 to cpu_log2_word_bytes-1 generate
c.b_request_size_mask(n) <= (c.b_request_size_mask(n-1) or
logic_eq(r.b_request_size,
std_ulogic_vector(to_unsigned(n, cpu_data_size_bits))));
end generate;
b_request_tag_match_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
c.b_request_cache_tag_match(n) <=
logic_eq(c.b_request_tag,
std_ulogic_vector2_slice2(c.b_tram_rdata, n));
end generate;
----------------------------------
b_cache_read_data_way_words_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
byte_loop : for m in cpu_word_bytes-1 downto 0 generate
bit_loop : for b in byte_bits-1 downto 0 generate
c.b_cache_way_read_data_le(n, m*byte_bits+b) <= c.b_dram_rdata(n*cpu_word_bytes+m, b);
end generate;
end generate;
end generate;
b_cache_read_data_word_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bits,
sel_bits => cpu_l1mem_data_cache_assoc
)
port map (
din => c.b_cache_way_read_data_le,
sel => cpu_l1mem_data_cache_dp_in_ctrl.b_cache_read_data_way,
dout => c.b_cache_read_data_le
);
b_cache_read_data_gen : for m in cpu_word_bytes-1 downto 0 generate
bit_loop : for b in byte_bits-1 downto 0 generate
c.b_cache_read_data_be((cpu_word_bytes-m-1)*byte_bits+b) <= c.b_cache_read_data_le(m*byte_bits+b);
end generate;
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.b_cache_read_data_be select
c.b_cache_read_data <= c.b_cache_read_data_le when '0',
c.b_cache_read_data_be when '1',
(others => 'X') when others;
----------------------------------
c.b_bus_op_tag <= r.b_bus_op_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
c.b_bus_op_index <= r.b_bus_op_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.b_bus_op_offset <= r.b_bus_op_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0);
----------------------------------
c.b_result_data_bus <= sys_slave_dp_out.data(cpu_word_bits-1 downto 0);
with cpu_l1mem_data_cache_dp_in_ctrl.b_result_data_sel select
c.b_result_data_cache_or_bus_unshifted <= c.b_cache_read_data when cpu_l1mem_data_cache_b_result_data_sel_cache,
c.b_result_data_bus when cpu_l1mem_data_cache_b_result_data_sel_bus_shifted,
(others => 'X') when others;
b_result_data_cache_or_bus_tmp_0_gen : for n in cpu_word_bits-1 downto 0 generate
c.b_result_data_cache_or_bus_shifter(cpu_log2_word_bytes, n) <= c.b_result_data_cache_or_bus_unshifted(n);
end generate;
b_result_data_cache_or_bus_shifter_gen : for n in cpu_log2_word_bytes-1 downto 0 generate
blk : block
signal sel : std_ulogic;
signal word : cpu_word_type;
signal part : std_ulogic_vector((2**n)*byte_bits-1 downto 0);
begin
-- align the result from the cache according to the least significant bits of the address
sel <= ((r.b_request_poffset(n) xor cpu_l1mem_data_cache_dp_in_ctrl.b_request_be) and c.b_request_size_mask(n));
word_loop : for b in cpu_word_bits-1 downto 0 generate
word(b) <= c.b_result_data_cache_or_bus_shifter(n+1, b);
end generate;
with sel select
part <= word(2*(2**n)*byte_bits-1 downto (2**n)*byte_bits) when '1',
word((2**n)*byte_bits-1 downto 0) when '0',
(others => 'X') when others;
out_hi_loop : for b in cpu_word_bits-1 downto (2**n)*byte_bits generate
c.b_result_data_cache_or_bus_shifter(n, b) <= word(b);
end generate;
out_lo_loop : for b in (2**n)*byte_bits-1 downto 0 generate
c.b_result_data_cache_or_bus_shifter(n, b) <= part(b);
end generate;
end block;
end generate;
b_result_data_cache_or_bus_gen : for n in cpu_word_bits-1 downto 0 generate
c.b_result_data_cache_or_bus_shifted(n) <= c.b_result_data_cache_or_bus_shifter(0, n);
end generate;
b_result_data_stb_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => r.b_stb_array_data,
sel => cpu_l1mem_data_cache_dp_in_ctrl.b_request_stb_array_hit,
dout => c.b_result_data_stb
);
with cpu_l1mem_data_cache_dp_in_ctrl.b_result_data_sel select
c.b_result_data <= c.b_result_data_cache_or_bus_shifted when cpu_l1mem_data_cache_b_result_data_sel_cache |
cpu_l1mem_data_cache_b_result_data_sel_bus_shifted,
c.b_result_data_bus when cpu_l1mem_data_cache_b_result_data_sel_bus,
c.b_result_data_stb when cpu_l1mem_data_cache_b_result_data_sel_stb,
(others => 'X') when others;
----------------------------------
c.b_block_change_index <= r.b_bus_op_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.b_block_change_tag <= r.b_bus_op_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
b_stb_array_gen : for n in cpu_l1mem_data_cache_stb_entries-1 downto 0 generate
b_stb_array_word_byte_offset_gen : for m in cpu_log2_word_bytes-1 downto 0 generate
c.b_stb_array_word_byte_offset(n, m) <= r.b_stb_array_paddr(n, m);
end generate;
b_stb_array_block_word_offset_gen : for m in cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0 generate
c.b_stb_array_block_word_offset(n, m) <= r.b_stb_array_paddr(n, m + cpu_log2_word_bytes);
end generate;
b_stb_array_index_gen : for m in cpu_l1mem_data_cache_index_bits-1 downto 0 generate
c.b_stb_array_index(n, m) <= r.b_stb_array_paddr(n, m + cpu_l1mem_data_cache_offset_bits);
end generate;
b_stb_array_tag_gen : for m in cpu_l1mem_data_cache_tag_bits-1 downto 0 generate
c.b_stb_array_tag(n, m) <= r.b_stb_array_paddr(n, m + cpu_l1mem_data_cache_offset_bits + cpu_l1mem_data_cache_index_bits);
end generate;
c.b_stb_array_size_mask(n, 0) <= all_zeros(std_ulogic_vector2_slice2(r.b_stb_array_size, n));
b_request_size_mask_gen : for m in 1 to cpu_log2_word_bytes-1 generate
c.b_stb_array_size_mask(n, m) <= (c.b_stb_array_size_mask(n, m-1) or
logic_eq(r.b_request_size,
std_ulogic_vector(to_unsigned(n, cpu_data_size_bits))));
end generate;
c.b_request_stb_array_tag_match(n) <=
logic_eq(c.b_request_tag,
std_ulogic_vector2_slice2(c.b_stb_array_tag, n));
c.b_request_stb_array_index_match(n) <=
logic_eq(c.b_request_index,
std_ulogic_vector2_slice2(c.b_stb_array_index, n));
c.b_request_stb_array_block_word_offset_match(n) <=
logic_eq(c.b_request_block_word_offset,
std_ulogic_vector2_slice2(c.b_stb_array_block_word_offset, n));
c.b_request_stb_array_word_byte_offset_match(n) <=
logic_eq(c.b_request_word_byte_offset,
std_ulogic_vector2_slice2(c.b_stb_array_word_byte_offset, n)
);
c.b_request_stb_array_size_match(n) <=
logic_eq(r.b_request_size,
std_ulogic_vector2_slice2(r.b_stb_array_size, n));
c.b_stb_array_block_change_index_match(n) <=
logic_eq(c.b_block_change_index,
std_ulogic_vector2_slice2(c.b_stb_array_index, n));
c.b_stb_array_block_change_tag_match(n) <=
logic_eq(c.b_block_change_tag,
std_ulogic_vector2_slice2(c.b_stb_array_tag, n));
end generate;
b_stb_head_paddr_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_paddr_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => r.b_stb_array_paddr,
sel => cpu_l1mem_data_cache_dp_in_ctrl.b_stb_head_ptr,
dout => c.b_stb_head_paddr
);
c.b_stb_head_index <= c.b_stb_head_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.b_stb_update_data_ptr <= (
cpu_l1mem_data_cache_dp_in_ctrl.b_stb_push_ptr or
cpu_l1mem_data_cache_dp_in_ctrl.b_stb_combine_ptr
);
b_stb_array_next_gen : for n in cpu_l1mem_data_cache_stb_entries-1 downto 0 generate
blk : block
signal size : cpu_data_size_type;
signal data : cpu_word_type;
signal paddr : cpu_paddr_type;
begin
with cpu_l1mem_data_cache_dp_in_ctrl.b_stb_push_ptr(n) select
paddr <= std_ulogic_vector2_slice2(r.b_stb_array_paddr, n) when '0',
c.b_request_paddr when '1',
(others => 'X') when others;
paddr_bit_loop : for m in cpu_paddr_bits-1 downto 0 generate
c.b_stb_array_paddr_next(n, m) <= paddr(m);
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.b_stb_push_ptr(n) select
size <= std_ulogic_vector2_slice2(r.b_stb_array_size, n) when '0',
r.b_request_size when '1',
(others => 'X') when others;
size_bit_loop : for m in cpu_data_size_bits-1 downto 0 generate
c.b_stb_array_size_next(n, m) <= size(m);
end generate;
with c.b_stb_update_data_ptr(n) select
data <= std_ulogic_vector2_slice2(r.b_stb_array_data, n) when '0',
r.b_request_data when '1',
(others => 'X') when others;
data_bit_loop : for m in cpu_word_bits-1 downto 0 generate
c.b_stb_array_data_next(n, m) <= data(m);
end generate;
end block;
end generate;
--------------------------
with cpu_l1mem_data_cache_dp_in_ctrl.b_rmdram_owner select
c.b_replace_windex <= c.b_request_index when cpu_l1mem_data_cache_owner_request,
c.b_stb_head_index when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_index when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
c.b_replace_wstate <= c.b_replace_rstate;
with cpu_l1mem_data_cache_dp_in_ctrl.b_vtram_owner select
c.b_vram_waddr <= c.b_request_index when cpu_l1mem_data_cache_owner_request,
c.b_bus_op_index when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.b_rmdram_owner select
c.b_mram_waddr <= c.b_stb_head_index when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_index when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
--------------------------
c.a_stb_array_paddr <= c.b_stb_array_paddr_next;
c.a_stb_array_size <= c.b_stb_array_size_next;
c.a_stb_array_data <= c.b_stb_array_data_next;
a_stb_head_paddr_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_paddr_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => c.a_stb_array_paddr,
sel => cpu_l1mem_data_cache_dp_in_ctrl.a_stb_head_ptr,
dout => c.a_stb_head_paddr
);
c.a_stb_head_tag <= c.a_stb_head_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
c.a_stb_head_index <= c.a_stb_head_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.a_stb_head_offset <= c.a_stb_head_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_stb_head_data_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => c.a_stb_array_data,
sel => cpu_l1mem_data_cache_dp_in_ctrl.a_stb_head_ptr,
dout => c.a_stb_head_data
);
a_stb_head_size_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_data_size_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => c.a_stb_array_size,
sel => cpu_l1mem_data_cache_dp_in_ctrl.a_stb_head_ptr,
dout => c.a_stb_head_size
);
a_stb_head_size_decoder : entity tech.decoder(rtl)
generic map (
output_bits => cpu_log2_word_bytes + 1
)
port map (
datain => c.a_stb_head_size,
dataout => c.a_stb_head_size_dec
);
a_stb_word_byte_mask_gen : for m in cpu_word_bytes-1 downto 0 generate
c.a_stb_word_byte_mask_by_size(cpu_log2_word_bytes, m) <= '1';
size_loop : for n in cpu_log2_word_bytes-1 downto 0 generate
c.a_stb_word_byte_mask_by_size(n, m) <= logic_eq(c.a_stb_head_offset(cpu_log2_word_bytes-1 downto n),
std_ulogic_vector(to_unsigned(m/(2**n), cpu_log2_word_bytes-n)));
end generate;
end generate;
a_stb_word_byte_mask_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bytes,
sel_bits => cpu_log2_word_bytes + 1
)
port map (
din => c.a_stb_word_byte_mask_by_size,
sel => c.a_stb_head_size_dec,
dout => c.a_stb_word_byte_mask
);
a_stb_dram_banken_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
word_byte_loop : for m in cpu_word_bytes-1 downto 0 generate
c.a_stb_dram_banken(n*cpu_word_bytes+m) <= (
cpu_l1mem_data_cache_dp_in_ctrl.a_stb_way(n) and
c.a_stb_word_byte_mask(m)
);
end generate;
end generate;
-- log2_word_bytes size wdata
-- 0 0 0
-- 1 0 00
-- 1 1 10
-- 2 0 0000
-- 2 1 1010
-- 2 2 3210
-- 3 0 00000000
-- 3 1 10101010
-- 3 2 32103210
-- 3 3 76543210
c.a_stb_dram_wdata_sel(0) <= c.a_stb_head_size_dec(0);
a_stb_dram_wdata_word_sel_gen : for n in 1 to cpu_log2_word_bytes-1 generate
c.a_stb_dram_wdata_sel(n) <= c.a_stb_dram_wdata_sel(n-1) or c.a_stb_head_size_dec(n);
end generate;
c.a_stb_dram_wdata_word(byte_bits-1 downto 0) <= c.a_stb_head_data(byte_bits-1 downto 0);
a_stb_dram_wdata_word_gen : for n in cpu_log2_word_bytes-1 downto 0 generate
with c.a_stb_dram_wdata_sel(n) select
c.a_stb_dram_wdata_word((2**(n+1))*byte_bits-1 downto (2**n)*byte_bits) <=
c.a_stb_head_data((2**(n+1))*byte_bits-1 downto (2**n)*byte_bits) when '0',
c.a_stb_dram_wdata_word((2**n)*byte_bits-1 downto 0) when '1',
(others => 'X') when others;
end generate;
--------------------------
c.a_new_request_size <= cpu_l1mem_data_cache_dp_in.size;
c.a_new_request_poffset <= cpu_l1mem_data_cache_dp_in.vaddr(cpu_poffset_bits-1 downto 0);
c.a_new_request_vpn <= cpu_l1mem_data_cache_dp_in.vaddr(cpu_vaddr_bits-1 downto cpu_poffset_bits);
c.a_new_request_data <= cpu_l1mem_data_cache_dp_in.data;
with cpu_l1mem_data_cache_dp_in_ctrl.b_request_complete select
c.a_request_size <= c.a_new_request_size when '1',
r.b_request_size when '0',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.b_request_complete select
c.a_request_poffset <= c.a_new_request_poffset when '1',
r.b_request_poffset when '0',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.b_request_complete select
c.a_request_vpn <= c.a_new_request_vpn when '1',
r.b_request_vpn when '0',
(others => 'X') when others;
c.a_request_ppn <= c.b_request_ppn;
c.a_request_paddr <= c.a_request_ppn & c.a_request_poffset;
c.a_request_tag <= c.a_request_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
c.a_request_index <= c.a_request_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.a_request_offset <= c.a_request_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0);
with cpu_l1mem_data_cache_dp_in_ctrl.b_request_complete select
c.a_request_data <= c.a_new_request_data when '1',
r.b_request_data when '0',
(others => 'X') when others;
c.a_request_bus_op_data <= r.b_request_data;
a_request_size_decoder : entity tech.decoder(rtl)
generic map (
output_bits => cpu_log2_word_bytes + 1
)
port map (
datain => c.a_request_size,
dataout => c.a_request_size_dec
);
a_request_word_byte_mask_gen : for m in cpu_word_bytes-1 downto 0 generate
c.a_request_word_byte_mask_by_size(cpu_log2_word_bytes, m) <= '1';
size_loop : for n in cpu_log2_word_bytes-1 downto 0 generate
c.a_request_word_byte_mask_by_size(n, m) <= logic_eq(c.a_request_poffset(cpu_log2_word_bytes-1 downto n),
std_ulogic_vector(to_unsigned(m/(2**n), cpu_log2_word_bytes-n)));
end generate;
end generate;
a_request_word_byte_mask_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bytes,
sel_bits => cpu_log2_word_bytes + 1
)
port map (
din => c.a_request_word_byte_mask_by_size,
sel => c.a_request_size_dec,
dout => c.a_request_word_byte_mask
);
a_request_dram_banken_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
word_byte_loop : for m in cpu_word_bytes-1 downto 0 generate
c.a_request_dram_banken(n*cpu_word_bytes+m) <= c.a_request_word_byte_mask(m);
end generate;
end generate;
--------------------------------
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_size_sel select
c.a_bus_op_size <= r.b_bus_op_size when cpu_l1mem_data_cache_a_bus_op_size_sel_old,
c.a_request_size when cpu_l1mem_data_cache_a_bus_op_size_sel_request,
c.a_stb_head_size when cpu_l1mem_data_cache_a_bus_op_size_sel_stb,
std_ulogic_vector(to_unsigned(cpu_log2_word_bytes, cpu_data_size_bits)) when cpu_l1mem_data_cache_a_bus_op_size_sel_word,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_owner select
c.a_bus_op_data <= c.a_request_bus_op_data when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_data when cpu_l1mem_data_cache_owner_stb,
(others => 'X') when others;
a_bus_op_dram_banken_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
word_byte_loop : for m in cpu_word_bytes-1 downto 0 generate
c.a_bus_op_dram_banken(n*cpu_word_bytes+m) <= cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_way(n);
end generate;
end generate;
c.a_bus_op_dram_wdata_word <= sys_slave_dp_out.data;
a_bus_op_paddr_block_word_offset_next_gen : if cpu_l1mem_data_cache_offset_bits > cpu_log2_word_bytes generate
c.a_bus_op_paddr_block_word_offset_next <=
std_ulogic_vector(unsigned(r.b_bus_op_paddr(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes)) +
to_unsigned(1, cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes));
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_paddr_tag_sel select
c.a_bus_op_paddr(cpu_paddr_bits-1 downto cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits) <=
c.a_request_tag when cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_request,
c.a_stb_head_tag when cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_stb,
c.b_bus_op_tag when cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_old,
c.b_replace_tag when cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_replace,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_paddr_index_sel select
c.a_bus_op_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto cpu_l1mem_data_cache_offset_bits) <=
c.a_request_index when cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_request,
c.a_stb_head_index when cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_stb,
c.b_bus_op_index when cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_old,
(others => 'X') when others;
a_bus_op_paddr_block_word_offset_gen : if cpu_l1mem_data_cache_offset_bits > cpu_log2_word_bytes generate
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_paddr_offset_sel select
c.a_bus_op_paddr(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes) <=
c.b_bus_op_offset(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes)
when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_old,
c.a_bus_op_paddr_block_word_offset_next when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_next_word,
c.a_request_offset(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes)
when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request |
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request_word,
c.a_stb_head_offset(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes)
when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb |
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb_word,
(others => 'X') when others;
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_paddr_offset_sel select
c.a_bus_op_paddr(cpu_log2_word_bytes-1 downto 0) <=
r.b_bus_op_paddr(cpu_log2_word_bytes-1 downto 0) when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_old,
c.a_request_paddr(cpu_log2_word_bytes-1 downto 0) when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request,
c.a_stb_head_paddr(cpu_log2_word_bytes-1 downto 0) when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb,
(cpu_log2_word_bytes-1 downto 0 => '0') when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_next_word |
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request_word |
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb_word,
(others => 'X') when others;
c.a_bus_op_index <= c.a_bus_op_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.a_bus_op_offset <= c.a_bus_op_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0);
c.a_bus_op_cache_wtag <= r.b_bus_op_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_index <=
c.a_bus_op_index when '0',
c.b_bus_op_index when '1',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_offset <=
c.a_bus_op_offset when '0',
c.b_bus_op_offset when '1',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_sys_paddr_sel_old select
c.a_bus_op_sys_paddr <=
c.a_bus_op_paddr when '0',
r.b_bus_op_paddr when '1',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_sys_data_sel_cache select
c.a_bus_op_sys_data <=
c.a_bus_op_data when '0',
c.b_cache_read_data when '1',
(others => 'X') when others;
--------------------------------
with cpu_l1mem_data_cache_dp_in_ctrl.a_vtram_owner select
c.a_vtram_index <= c.a_request_index when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_index when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_cache_index when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
c.a_vram_raddr <= c.a_vtram_index;
c.a_tram_addr <= c.a_vtram_index;
c.a_tram_wtag <= c.a_bus_op_cache_wtag;
a_tram_wdata_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
bit_gen : for b in cpu_l1mem_data_cache_tag_bits-1 downto 0 generate
c.a_tram_wdata(n, b) <= c.a_tram_wtag(b);
end generate;
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.a_rmdram_owner select
c.a_rmdram_index <= c.a_request_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1
downto cpu_l1mem_data_cache_offset_bits)
when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1
downto cpu_l1mem_data_cache_offset_bits)
when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_cache_index
when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_rmdram_owner select
c.a_rmdram_offset <= c.a_request_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0)
when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0)
when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_cache_offset
when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
c.a_mram_raddr <= c.a_rmdram_index;
c.a_replace_rindex <= c.a_rmdram_index;
c.a_dram_addr <= c.a_rmdram_index & c.a_rmdram_offset(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes);
with cpu_l1mem_data_cache_dp_in_ctrl.a_rmdram_owner select
c.a_dram_banken <= c.a_request_dram_banken when cpu_l1mem_data_cache_owner_request,
c.a_stb_dram_banken when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_dram_banken when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_rmdram_owner select
c.a_dram_wdata_word <= c.a_stb_dram_wdata_word when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_dram_wdata_word when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
a_dram_wdata_bytes_gen : for n in cpu_word_bytes-1 downto 0 generate
bit_loop : for b in byte_bits-1 downto 0 generate
c.a_dram_wdata_bytes_le(n, b) <= c.a_dram_wdata_word(n*byte_bits+b);
c.a_dram_wdata_bytes_be(cpu_word_bytes-n-1, b) <= c.a_dram_wdata_word(n*byte_bits+b);
end generate;
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.a_dram_wdata_be select
c.a_dram_wdata_bytes <= c.a_dram_wdata_bytes_le when '0',
c.a_dram_wdata_bytes_be when '1',
(others => (others => 'X')) when others;
a_dram_wdata_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
byte_loop : for m in cpu_word_bytes-1 downto 0 generate
bit_loop : for b in byte_bits-1 downto 0 generate
c.a_dram_wdata(n*cpu_word_bytes+m, b) <= c.a_dram_wdata_bytes(m, b);
end generate;
end generate;
end generate;
c.a_sys_size <= (sys_transfer_size_bits-1 downto cpu_data_size_bits => '0') & c.a_bus_op_size;
c.a_sys_paddr <= (sys_paddr_bits-1 downto cpu_paddr_bits => '0') & c.a_bus_op_sys_paddr;
c.a_sys_data <= c.a_bus_op_sys_data;
c.b_result_paddr <= r.b_bus_op_paddr;
r_next <= (
b_request_size => c.a_request_size,
b_request_poffset => c.a_request_poffset,
b_request_vpn => c.a_request_vpn,
b_request_data => c.a_request_data,
b_bus_op_size => c.a_bus_op_size,
b_bus_op_paddr => c.a_bus_op_paddr,
b_stb_array_paddr => c.a_stb_array_paddr,
b_stb_array_data => c.a_stb_array_data,
b_stb_array_size => c.a_stb_array_size
);
cpu_l1mem_data_cache_dp_out_ctrl <= (
b_request_cache_tag_match => c.b_request_cache_tag_match,
b_request_stb_array_tag_match => c.b_request_stb_array_tag_match,
b_request_stb_array_index_match => c.b_request_stb_array_index_match,
b_request_stb_array_block_word_offset_match => c.b_request_stb_array_block_word_offset_match,
b_request_stb_array_word_byte_offset_match => c.b_request_stb_array_word_byte_offset_match,
b_request_stb_array_size_match => c.b_request_stb_array_size_match,
b_stb_array_block_change_index_match => c.b_stb_array_block_change_index_match,
b_stb_array_block_change_tag_match => c.b_stb_array_block_change_tag_match
);
cpu_l1mem_data_cache_dp_out_vram <= (
raddr => c.a_vram_raddr,
waddr => c.b_vram_waddr
);
cpu_l1mem_data_cache_dp_out_mram <= (
raddr => c.a_mram_raddr,
waddr => c.b_mram_waddr
);
cpu_l1mem_data_cache_dp_out_tram <= (
addr => c.a_tram_addr,
wdata => c.a_tram_wdata
);
cpu_l1mem_data_cache_dp_out_dram <= (
banken => c.a_dram_banken,
addr => c.a_dram_addr,
wdata => c.a_dram_wdata
);
cpu_l1mem_data_cache_replace_dp_in <= (
rindex => c.a_replace_rindex,
windex => c.b_replace_windex,
wstate => c.b_replace_wstate
);
cpu_l1mem_data_cache_dp_out <= (
paddr => c.b_result_paddr,
data => c.b_result_data
);
cpu_mmu_data_dp_in <= (
vpn => c.a_request_vpn
);
sys_master_dp_out <= (
size => c.a_sys_size,
paddr => c.a_sys_paddr,
data => c.a_sys_data
);
process (clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/syncram_banked_1r1w_inferred-rtl.vhdl
|
1
|
2388
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
architecture rtl of syncram_banked_1r1w_inferred is
constant banks : natural := 2**log2_banks;
type bank_data_type is array(banks-1 downto 0) of std_ulogic_vector(word_bits-1 downto 0);
type comb_type is record
bank_re : std_ulogic_vector(banks-1 downto 0);
bank_we : std_ulogic_vector(banks-1 downto 0);
bank_rdata, bank_wdata : bank_data_type;
end record;
signal c : comb_type;
begin
bank_loop : for n in 0 to banks-1 generate
c.bank_we(n) <= we and wbanken(n);
c.bank_re(n) <= re and rbanken(n);
word_bit_loop : for m in word_bits-1 downto 0 generate
c.bank_wdata(n)(m) <= wdata(n, m);
rdata(n, m) <= c.bank_rdata(n)(m);
end generate;
syncram : entity work.syncram_1r1w(rtl)
generic map (
addr_bits => addr_bits,
data_bits => word_bits,
write_first => write_first
)
port map (
clk => clk,
we => c.bank_we(n),
waddr => waddr,
wdata => c.bank_wdata(n),
re => c.bank_re(n),
raddr => raddr,
rdata => c.bank_rdata(n)
);
end generate;
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/or1knd/i5/cpu_or1knd_i5_pipe_ctrl.vhdl
|
1
|
2935
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library isa;
use isa.or1k_pkg.all;
use work.cpu_bpb_pkg.all;
use work.cpu_btb_pkg.all;
use work.cpu_or1knd_i5_pkg.all;
use work.cpu_or1knd_i5_pipe_pkg.all;
use work.cpu_l1mem_inst_pkg.all;
use work.cpu_l1mem_data_pkg.all;
use work.cpu_or1knd_i5_mmu_inst_pkg.all;
use work.cpu_or1knd_i5_mmu_data_pkg.all;
entity cpu_or1knd_i5_pipe_ctrl is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_or1knd_i5_pipe_dp_in_ctrl : out cpu_or1knd_i5_pipe_dp_in_ctrl_type;
cpu_or1knd_i5_pipe_dp_out_ctrl : in cpu_or1knd_i5_pipe_dp_out_ctrl_type;
cpu_or1knd_i5_pipe_ctrl_in_misc : in cpu_or1knd_i5_pipe_ctrl_in_misc_type;
cpu_or1knd_i5_pipe_ctrl_out_misc : out cpu_or1knd_i5_pipe_ctrl_out_misc_type;
cpu_l1mem_inst_ctrl_in : out cpu_l1mem_inst_ctrl_in_type;
cpu_l1mem_inst_ctrl_out : in cpu_l1mem_inst_ctrl_out_type;
cpu_l1mem_data_ctrl_in : out cpu_l1mem_data_ctrl_in_type;
cpu_l1mem_data_ctrl_out : in cpu_l1mem_data_ctrl_out_type;
cpu_bpb_ctrl_in : out cpu_bpb_ctrl_in_type;
cpu_bpb_ctrl_out : in cpu_bpb_ctrl_out_type;
cpu_btb_ctrl_in : out cpu_btb_ctrl_in_type;
cpu_btb_ctrl_out : in cpu_btb_ctrl_out_type;
cpu_or1knd_i5_mmu_inst_ctrl_in_pipe : out cpu_or1knd_i5_mmu_inst_ctrl_in_pipe_type;
cpu_or1knd_i5_mmu_inst_ctrl_out_pipe : in cpu_or1knd_i5_mmu_inst_ctrl_out_pipe_type;
cpu_or1knd_i5_mmu_data_ctrl_in_pipe : out cpu_or1knd_i5_mmu_data_ctrl_in_pipe_type;
cpu_or1knd_i5_mmu_data_ctrl_out_pipe : in cpu_or1knd_i5_mmu_data_ctrl_out_pipe_type
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/mul_seq-rtl.vhdl
|
1
|
1604
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of mul_seq is
begin
mul : entity work.mul_seq_inferred(rtl)
generic map (
latency => latency,
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
clk => clk,
rstn => rstn,
en => en,
unsgnd => unsgnd,
src1 => src1,
src2 => src2,
valid => valid,
result => result
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/tech/inferred/addsub_inferred-rtl.vhdl
|
1
|
2391
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of addsub_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src_bits downto 0);
src2_tmp : std_ulogic_vector(src_bits downto 0);
result_tmp : std_ulogic_vector(src_bits downto 0);
result_msb : std_ulogic;
result_msb_carryin : std_ulogic;
carryout : std_ulogic;
end record;
signal c : comb_type;
begin
c.src1_tmp <= '0' & src1(src_bits-2 downto 0) & '1';
c.src2_tmp <= ('0' & src2(src_bits-2 downto 0) & carryin) xor (src_bits downto 0 => sub);
c.result_tmp <= std_ulogic_vector(unsigned(c.src1_tmp) + unsigned(c.src2_tmp));
c.result_msb_carryin <= c.result_tmp(src_bits);
c.result_msb <= (src1(src_bits-1) xor
src2(src_bits-1) xor
c.result_msb_carryin
);
c.carryout <= (((sub xor src1(src_bits-1)) and (src2(src_bits-1) or c.result_msb_carryin)) or
(src2(src_bits-1) and c.result_msb_carryin));
carryout <= c.carryout;
overflow <= c.carryout xor c.result_msb_carryin;
result <= c.result_msb & c.result_tmp(src_bits-1 downto 1);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/cpu/l1mem/data/cache/replace/none/cpu_l1mem_data_cache_replace_none-rtl.vhdl
|
1
|
1483
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
architecture rtl of cpu_l1mem_data_cache_replace_none is
begin
cpu_l1mem_data_cache_replace_none_ctrl_out <= (
rway => (0 => '1')
);
cpu_l1mem_data_cache_replace_none_dp_out <= (
rstate => ""
);
end;
|
apache-2.0
|
pgavin/carpe
|
hdl/sys/sys_pkg.vhdl
|
1
|
3590
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
use util.numeric_pkg.all;
use work.sys_config_pkg.all;
package sys_pkg is
constant sys_bus_bytes : natural := 2**sys_log2_bus_bytes;
constant sys_bus_bits : natural := sys_bus_bytes*byte_bits;
constant sys_transfer_size_bits : natural := bitsize(sys_log2_bus_bytes);
constant sys_max_burst_cycles : natural := 2**sys_log2_max_burst_cycles;
constant sys_burst_cycles_bits : natural := bitsize(sys_log2_max_burst_cycles);
subtype sys_paddr_type is std_ulogic_vector(sys_paddr_bits-1 downto 0);
subtype sys_bus_bytes_type is std_ulogic_vector2(sys_bus_bytes-1 downto 0, byte_bits-1 downto 0);
subtype sys_bus_type is std_ulogic_vector(sys_bus_bits-1 downto 0);
subtype sys_transfer_size_type is std_ulogic_vector(sys_transfer_size_bits-1 downto 0);
subtype sys_burst_cycles_type is std_ulogic_vector(sys_burst_cycles_bits-1 downto 0);
type sys_master_ctrl_out_type is record
-- a request is being made
request : std_ulogic;
-- big endian if true, otherwise little endian
be : std_ulogic;
-- this request is a write
write : std_ulogic;
-- this request is cacheable
cacheable : std_ulogic;
-- this request is privileged
priv : std_ulogic;
-- this request is for an instruction
inst : std_ulogic;
-- this request is part of a burst, but not the last request
burst : std_ulogic;
-- wrapping burst
bwrap : std_ulogic;
-- size of burst
bcycles : sys_burst_cycles_type;
end record;
type sys_master_dp_out_type is record
size : sys_transfer_size_type;
paddr : sys_paddr_type;
data : sys_bus_type;
end record;
type sys_slave_ctrl_out_type is record
ready : std_ulogic;
error : std_ulogic;
end record;
type sys_slave_dp_out_type is record
data : sys_bus_type;
end record;
type sys_master_ctrl_out_vector_type is array(natural range <>) of sys_master_ctrl_out_type;
type sys_master_dp_out_vector_type is array(natural range <>) of sys_master_dp_out_type;
type sys_slave_ctrl_out_vector_type is array(natural range <>) of sys_slave_ctrl_out_type;
type sys_slave_dp_out_vector_type is array(natural range <>) of sys_slave_dp_out_type;
end package;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op980_2.vhdl
|
1
|
5443
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op952_11.vhdl
|
1
|
5526
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net5
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net5,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net6,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net6
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net7
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op990_9.vhdl
|
1
|
7073
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net9
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net11
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net12
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net12,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op993_24.vhdl
|
1
|
6541
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/harder/circuit_bi1_0op328_2sk1_0.vhdl
|
1
|
5594
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.78e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.78e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 6.505e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcasc_2,
Wcasc_2init => 8e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcasc_2,
Wcasc_2init => 8e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.15e-06,
W => Wcm_1,
Wcm_1init => 4.25e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.15e-06,
W => Wcmcout_1,
Wcmcout_1init => 4.5e-06,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op954_0.vhdl
|
1
|
4201
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/harder/circuit_bi1_0op334_0sk1_0.vhdl
|
1
|
5607
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.94e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.94e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => W_0,
W_0init => 7.635e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => Wcasc_2,
Wcasc_2init => 7.215e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => Wcasc_2,
Wcasc_2init => 7.215e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.29e-05,
W => Wcm_1,
Wcm_1init => 4.67e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.29e-05,
W => Wcmout_1,
Wcmout_1init => 4.975e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => (pfak)*(WBias),
WBiasinit => 3.55e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.05e-06,
W => (pfak)*(WBias),
WBiasinit => 3.55e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/harder/circuit_bi1_0op330_5sk1_0.vhdl
|
1
|
7284
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.9e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.9e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 2.995e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.71e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.4e-06,
W => Wcm_2,
Wcm_2init => 1.3e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.4e-06,
W => Wcmout_2,
Wcmout_2init => 3.32e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.71e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.71e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.4e-06,
W => Wcm_2,
Wcm_2init => 1.3e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.4e-06,
W => Wcmout_2,
Wcmout_2init => 3.32e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.71e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3e-06,
W => Wcm_1,
Wcm_1init => 7.835e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3e-06,
W => Wcmout_1,
Wcmout_1init => 3.795e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 3.05e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 3.05e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 3.05e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 3.05e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 3.05e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 3.05e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/harder/circuit_bi1_0op337_11sk1_0.vhdl
|
1
|
7981
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.4e-06,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.4e-06,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => W_0,
W_0init => 7.525e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.4e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 3.4e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.51e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.51e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.51e-05,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8e-07,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.51e-05,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 6.5e-07,
W => Wsrc_2,
Wsrc_2init => 5.095e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 6.5e-07,
W => Wsrc_2,
Wsrc_2init => 5.095e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 4.715e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.35e-06,
W => Wcm_1,
Wcm_1init => 3.75e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.35e-06,
W => Wcmout_1,
Wcmout_1init => 3.575e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 4.715e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.12e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.12e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.4e-06,
W => WBias,
WBiasinit => 1.12e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => WBias,
WBiasinit => 1.12e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => WBias,
WBiasinit => 1.12e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.4e-06,
W => WBias,
WBiasinit => 1.12e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op961_14.vhdl
|
1
|
5465
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net7
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/harder/circuit_bi1_0op332_11sk1_0.vhdl
|
1
|
7262
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 4e-07
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcm_2,
Wcm_2init => 3.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcmout_2,
Wcmout_2init => 8e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcm_2,
Wcm_2init => 3.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.8e-06,
W => Wcmout_2,
Wcmout_2init => 8e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.3e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1e-05,
W => Wcm_1,
Wcm_1init => 7.935e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1e-05,
W => Wcmcout_1,
Wcmcout_1init => 3.735e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.6e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.6e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op982_7.vhdl
|
1
|
5054
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op950_5.vhdl
|
1
|
5525
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net5
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net5,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net6,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net6
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net7
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.