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stringlengths 5
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stringclasses 54
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stringlengths 0
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|---|---|---|---|---|---|
CyAScott/CIS4930.DatapathSynthesisTool
|
src/Synthesize/DataPath/Vhdl/c_multiplexer.vhd
|
1
|
893
|
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_multiplexer is
generic
(
width : integer := 4;
no_of_inputs : integer := 2;
select_size : integer := 1
);
port
(
input : in std_logic_vector(((width * no_of_inputs) - 1) downto 0);
mux_select : in std_logic_vector ((select_size - 1) downto 0);
output : out std_logic_vector ((width - 1) downto 0)
);
end c_multiplexer;
architecture behavior of c_multiplexer is
signal sel : integer := 0;
begin
process (mux_select)
variable val : integer := 0;
begin
if (mux_select(0) /= 'X') then
val := 0;
for i in select_size - 1 downto 0 loop
if mux_select(i) = '1' then
val := 2 ** i + val;
end if;
end loop;
sel <= val;
end if;
end process;
process (input, sel)
begin
output <= input(((sel + 1) * width - 1) downto (sel * width));
end process;
end behavior;
|
mit
|
CyAScott/CIS4930.DatapathSynthesisTool
|
docs/sample2/c_subtractor.vhd
|
1
|
1032
|
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_subtractor is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_subtractor;
architecture behavior of c_subtractor is
function bits_to_int (input : std_logic_vector) return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
end loop; return ret_val;
end bits_to_int;
begin
process (input1, input2)
variable value : integer;
variable result : std_logic_vector((width - 1) downto 0);
begin
value := bits_to_int(input1) - bits_to_int(input2);
if (value < 0) then
value := (2 ** width) + value;
end if;
for i in 0 to width - 1 loop
if (value rem 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
value := value / 2;
end loop;
output <= result;
end process;
end behavior;
|
mit
|
aortiz49/MIPS-Processor
|
Hardware/single_cycle_tb.vhd
|
1
|
813
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle_tb is
end single_cycle_tb;
architecture behv of single_cycle_tb is
signal clk : std_logic := '0';
signal pc_rst : std_logic := '0';
signal programCounter : std_logic_vector(31 downto 0);
signal instruction_out : std_logic_vector(31 downto 0);
signal instr_addr : std_logic_vector(7 downto 0);
begin
single_cycle1: entity work.single_cycle
port map (
clk => clk,
pc_rst => pc_rst,
programCounter => programCounter,
instruction_out => instruction_out,
instr_addr => instr_addr
);
clk <= not clk after 10 ns;
process
begin
pc_rst <= '1';
wait for 5 ns;
pc_rst <= '0';
wait;
end process;
end behv;
|
mit
|
aortiz49/MIPS-Processor
|
Hardware/zeroReg.vhd
|
1
|
571
|
library ieee;
use ieee.std_logic_1164.all;
entity zeroReg is
port(
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0)
);
end zeroReg;
architecture bhv of zeroReg is
begin
process(clk, rst)
begin
if rst = '1' then
output <= (others => '0');
elsif (clk = '1' and clk'event) then
if (en = '1') then
output <= input;
end if;
end if;
end process;
end bhv;
|
mit
|
aortiz49/MIPS-Processor
|
Hardware/alu_control.vhd
|
1
|
2130
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.MIPS_lib.all;
entity alu_control is
port(
ALUop : in std_logic_vector(2 downto 0);
funct : in std_logic_vector(5 downto 0);
shamt_in : in std_logic_vector(4 downto 0);
shamt_out : out std_logic_vector(4 downto 0);
control : out std_logic_vector(3 downto 0);
shdir : out std_logic
);
end alu_control ;
architecture bhv of alu_control is
begin
process(shamt_in,ALUop, funct)
begin
shdir <= '0'; -- shift left for lui (default))
shamt_out <= shamt_in;
case ALUop is
when ADD => -- Add for load/store/addi/addiu
control <= F_SUM;
when BEQ => -- sub for branching
control <= F_SUB;
when ANDI => -- and imm
control <= F_AND;
when ORI => -- or immediate
control <= F_OR;
when LUI => -- lui
shamt_out <= "10000";
control <= F_SHFT;
when SLTI => -- set if less than imm
control <= F_SLT;
when SLTIU => -- set if less than imm unsigned
control <= F_SLTU;
when R_TYPE => -- R-type instructions
shdir <= funct(1); -- for sll this bit is '0', for slr it's '1'
case funct IS
when CTRL_ADD =>
control <= F_SUM;
when CTRL_ADDU =>
control <= F_SUM;
when CTRL_SUB =>
control <= F_SUB;
when CTRL_SUBU =>
control <= F_SUB;
when CTRL_AND =>
control <= F_AND;
when CTRL_OR =>
control <= F_OR;
when CTRL_NOR =>
control <= F_NOR;
when CTRL_SLT =>
control <= F_SLT;
when CTRL_SLTU =>
control <= F_SLTU;
when CTRL_SLL =>
control <= F_SHFT;
when CTRL_SRL =>
control <= F_SHFT;
when others =>
control <= (others => '0');
end case;
when others =>
control <= (others => '0');
end case;
end process;
end bhv;
|
mit
|
aortiz49/MIPS-Processor
|
Testbenches/extender_tb.vhd
|
1
|
835
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity extender_tb is
end extender_tb;
architecture TB of extender_tb is
component extender
port(
in0 : in std_logic_vector(15 downto 0);
Sel : in std_logic;
out0 : out std_logic_vector(31 downto 0));
end component;
signal in0 : std_logic_vector(15 downto 0);
signal Sel : std_logic;
signal out0 : std_logic_vector(31 downto 0);
begin -- TB
UUT: entity work.extender
port map(
in0 => in0,
Sel => Sel,
out0 => out0);
process
begin
in0 <= x"7FFF";
Sel <= '0';
wait for 20 ns;
in0 <= x"7FFF";
Sel <= '1';
wait for 20 ns;
in0 <= x"FFFF";
Sel <= '0';
wait for 20 ns;
in0 <= x"FFFF";
Sel <= '1';
wait for 20 ns;
report "SIMULATION FINISHED!";
wait;
end process;
end TB;
|
mit
|
skrasser/papilio_synth
|
hdl/envelope.vhd
|
1
|
3383
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity envelope is
port (data_in : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0);
attack : in STD_LOGIC_VECTOR(3 downto 0); -- attack rate
delay : in STD_LOGIC_VECTOR(3 downto 0); -- delay rate
sustain : in STD_LOGIC_VECTOR(3 downto 0); -- sustain level
release : in STD_LOGIC_VECTOR(3 downto 0); -- release rate
gate : in STD_LOGIC;
clk : in STD_LOGIC
);
end envelope;
architecture behavioral of envelope is
begin
process(clk)
constant state_idle : std_logic_vector(2 downto 0) := "000";
constant state_attack : std_logic_vector(2 downto 0) := "001";
constant state_delay : std_logic_vector(2 downto 0) := "010";
constant state_sustain : std_logic_vector(2 downto 0) := "011";
constant state_release : std_logic_vector(2 downto 0) := "100";
variable state : std_logic_vector(2 downto 0) := state_idle;
variable sum : unsigned(22 downto 0) := (others => '0');
variable rate : unsigned(3 downto 0);
variable vol : unsigned(7 downto 0) := (others => '0');
variable datamod : unsigned(15 downto 0);
function trigger(asum : unsigned(22 downto 0);
arate : unsigned(3 downto 0)
) return boolean is
begin
-- bit 7 is set after 1.024 msec
if asum(to_integer(arate) + 7) = '1' then
return true;
else
return false;
end if;
end trigger;
begin
if rising_edge(clk) then
case state is
when state_idle =>
vol := (others => '0');
sum := (others => '0');
if gate = '1' then
state := state_attack;
end if;
when state_attack =>
sum := sum + 1;
if trigger(sum, unsigned(attack)) then
sum := (others => '0');
vol := vol + 1;
-- if up to maximum volume, then switch to delay state
if vol = 255 then
state := state_delay;
end if;
end if;
when state_delay =>
sum := sum + 1;
if trigger(sum, unsigned(delay)) then
sum := (others => '0');
vol := vol - 1;
if vol = unsigned(sustain & "0000") then
state := state_sustain;
end if;
end if;
when state_sustain =>
-- stay in this state as long as the gate is active
if gate = '0' then
state := state_release;
-- need to reset sum since this did not occur on trigger
sum := (others => '0');
end if;
when state_release =>
sum := sum + 1;
if gate = '1' then
-- new note played, go through idle state for setup
state := state_idle;
elsif trigger(sum, unsigned(release)) then
sum := (others => '0');
vol := vol - 1;
if vol = 0 then
state := state_idle;
end if;
end if;
when others =>
state := state_idle;
end case;
-- apply volume to incoming data
datamod := unsigned(data_in) * vol;
data_out <= std_logic_vector(datamod(15 downto 8));
end if;
end process;
end behavioral;
|
mit
|
aortiz49/MIPS-Processor
|
Testbenches/single_cycle_tb.vhd
|
1
|
3117
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle_tb is
end single_cycle_tb;
architecture behv of single_cycle_tb is
component single_cycle
port (
clk : in std_logic;
program_counter : out std_logic_vector(31 downto 0);
instruction : out std_logic_vector(31 downto 0);
ALUsrc_out : out std_logic;
RegDst_out : out std_logic;
RegWrite_out : out std_logic;
pc_rst : in std_logic;
shdir_out : out std_logic;
shamt_out : out std_logic_vector(4 downto 0);
ALUOp_out : out std_logic_vector(2 downto 0);
ALUControl_out : out std_logic_vector(3 downto 0);
RW_out : out std_logic_vector(4 downto 0);
RD1_out : out std_logic_vector(4 downto 0);
RD0_out : out std_logic_vector(4 downto 0);
RegFileOut1 : out std_logic_vector(31 downto 0);
RegFileOut0 : out std_logic_vector(31 downto 0);
Extend_out : out std_logic_vector(31 downto 0);
ALU_Result_out : out std_logic_vector(31 downto 0);
MemWrite_out : out std_logic;
C : out std_logic;
S : out std_logic;
V : out std_logic;
Z : out std_logic;
ExtOp_out : out std_logic
);
end component;
signal clk : std_logic := '0';
signal program_counter : std_logic_vector(31 downto 0);
signal instruction : std_logic_vector(31 downto 0);
signal ALUsrc_out : std_logic;
signal RegDst_out : std_logic;
signal RegWrite_out : std_logic;
signal MemWrite_out : std_logic;
signal pc_rst : std_logic;
signal shdir_out : std_logic;
signal shamt_out : std_logic_vector(4 downto 0);
signal ALUOp_out : std_logic_vector(2 downto 0);
signal ALUControl_out : std_logic_vector(3 downto 0);
signal RW_out : std_logic_vector(4 downto 0);
signal RD1_out : std_logic_vector(4 downto 0);
signal RD0_out : std_logic_vector(4 downto 0);
signal RegFileOut1 : std_logic_vector(31 downto 0);
signal RegFileOut0 : std_logic_vector(31 downto 0);
signal Extend_out : std_logic_vector(31 downto 0);
signal ALU_Result_out : std_logic_vector(31 downto 0);
signal C : std_logic;
signal S : std_logic;
signal V : std_logic;
signal Z : std_logic;
signal ExtOp_out : std_logic;
begin
single_cycle1: single_cycle
port map (
clk => clk,
program_counter => program_counter,
instruction => instruction,
ALUsrc_out => ALUsrc_out,
RegDst_out => RegDst_out,
RegWrite_out => RegWrite_out,
pc_rst => pc_rst,
shdir_out => shdir_out,
shamt_out => shamt_out,
ALUOp_out => ALUOp_out,
ALUControl_out => ALUControl_out,
RW_out => RW_out,
RD1_out => RD1_out,
RD0_out => RD0_out,
RegFileOut1 => RegFileOut1,
RegFileOut0 => RegFileOut0,
Extend_out => Extend_out,
ALU_Result_out => ALU_Result_out,
MemWrite_out => MemWrite_out,
C => C,
S => S,
V => V,
Z => Z,
Extop_out => ExtOp_out
);
clk <= not clk after 10 ns;
process
begin
pc_rst <= '1';
wait for 5 ns;
pc_rst <= '0';
wait;
end process;
end behv;
|
mit
|
jamesots/learnfpga
|
oscilloscope/vhdl/ftdi.vhdl
|
1
|
1391
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- this component sends stuff to the ftdi without caring whether the buffer
-- is full or not
entity ftdi is
port (
ftdi_write : in std_logic;
ftdi_value : in std_logic_vector(7 downto 0);
ftdi_ready : out std_logic := '1';
clk : in std_logic;
ftdi_d : inout std_logic_vector(7 downto 0);
ftdi_txe : in std_logic;
ftdi_rd: out std_logic := '1';
ftdi_wr: out std_logic := '1';
ftdi_siwua: out std_logic := '1'
);
end ftdi;
architecture Behavioral of ftdi is
signal data : std_logic_vector(7 downto 0);
signal step : natural := 0;
begin
process(clk)
variable char : std_logic_vector(7 downto 0);
begin
if rising_edge(clk) then
case step is
when 0 =>
if ftdi_write = '1' then
data <= ftdi_value after 1 ns;
ftdi_ready <= '0' after 1 ns;
step <= step + 1;
end if;
when 1 =>
if ftdi_txe = '0' then
ftdi_d <= data;
step <= step + 1;
end if;
when 4 =>
ftdi_wr <= '0';
step <= step + 1;
when 8 =>
ftdi_wr <= '1';
ftdi_ready <= '1';
ftdi_d <= "ZZZZZZZZ";
step <= 0;
when others =>
step <= step + 1;
end case;
end if;
end process;
end Behavioral;
|
mit
|
jamesots/learnfpga
|
drum1/vhdl/bus_sync.vhdl
|
2
|
934
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Synchronise all signals in a bus. The value on bus_in will
-- appear on bus_out two rising edges later.
-- Use this to synchronize gray counters. Synchronizing
-- busses with more than one signal changing at a time is
-- pointless.
entity bus_sync is
generic (
width : positive
);
port (
bus_in : in std_logic_vector(width - 1 downto 0) := (others => '0');
bus_out : out std_logic_vector(width - 1 downto 0);
clk : in std_logic
);
end bus_sync;
architecture behavioral of bus_sync is
signal temp : std_logic_vector(width - 1 downto 0) := (others => '0');
attribute shreg_extract : string;
attribute shreg_extract of temp : signal is "no";
begin
process(clk)
begin
if rising_edge(clk) then
for i in 0 to width - 1 loop
temp(i) <= bus_in(i);
bus_out(i) <= temp(i);
end loop;
end if;
end process;
end behavioral;
|
mit
|
jamesots/learnfpga
|
fifo/tb/gray_compare_tb.vhdl
|
1
|
2104
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY gray_compare_tb IS
END gray_compare_tb;
ARCHITECTURE behavior OF gray_compare_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gray_compare
GENERIC(
width : positive
);
PORT(
gray : IN std_logic_vector(width - 1 downto 0);
other_gray : IN std_logic_vector(width - 1 downto 0);
clk : IN std_logic;
eq : OUT std_logic;
looped : OUT std_logic
);
END COMPONENT;
--Inputs
signal head_gc : std_logic_vector(2 downto 0) := (others => '0');
signal tail_gc : std_logic_vector(2 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal eq : std_logic;
signal looped : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gray_compare GENERIC MAP (
width => 3
) PORT MAP (
gray => head_gc,
other_gray => tail_gc,
clk => clk,
eq => eq,
looped => looped
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- to start with, gcs are identical - same values, same loopiness,
-- so it should be empty
wait for 50 ns;
head_gc <= "000";
tail_gc <= "000";
wait for clk_period;
head_gc <= "001";
tail_gc <= "000";
wait for clk_period;
head_gc <= "011";
tail_gc <= "000";
wait for clk_period;
head_gc <= "010";
tail_gc <= "000";
wait for clk_period;
head_gc <= "110";
tail_gc <= "000";
wait for clk_period * 4;
head_gc <= "110";
tail_gc <= "001";
wait for clk_period * 4;
wait;
end process;
END;
|
mit
|
bravo95/SecondProcessor
|
psr_tb.vhd
|
1
|
2040
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY psr_tb IS
END psr_tb;
ARCHITECTURE behavior OF psr_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT psr
PORT(
clk : IN std_logic;
rst : IN std_logic;
nzvc : IN std_logic_vector(3 downto 0);
ncwp : IN std_logic_vector(4 downto 0);
cwp : OUT std_logic_vector(4 downto 0);
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal nzvc : std_logic_vector(3 downto 0) := (others => '0');
signal ncwp : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal cwp : std_logic_vector(4 downto 0);
signal c : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: psr PORT MAP (
clk => clk,
rst => rst,
nzvc => nzvc,
ncwp => ncwp,
cwp => cwp,
c => c
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
-- rst : IN std_logic;
-- nzvc : IN std_logic_vector(3 downto 0);
-- ncwp : IN std_logic_vector(4 downto 0);
wait for 2 ns;
nzvc <= "0001";
wait for 10 ns;
nzvc <= "0000";
wait for 10 ns;
nzvc <= "0101";
ncwp <= "00001";
wait for 10 ns;
nzvc <= "0000";
wait for 10 ns;
nzvc <= "0111";
wait for 10 ns;
nzvc <= "0010";
ncwp <= "00000";
wait for 10 ns;
rst <= '1';
nzvc <= "0101";
wait for 10 ns;
ncwp <= "00000";
nzvc <= "0010";
rst <= '0';
wait for 10 ns;
nzvc <= "1001";
wait;
end process;
END;
|
mit
|
gustapp/labdig
|
Exp4/transmissor.vhd
|
1
|
1362
|
library ieee;
use ieee.std_logic_1164.all;
entity transmissor is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
dado_serial : in std_logic;
CTS : in std_logic;
envioOk : out std_logic;
DTR : out std_logic;
RTS : out std_logic;
TD : out std_logic;
d_estado : out std_logic_vector(1 downto 0));
end transmissor;
architecture hierarquico of transmissor is
component FD_transmissor is
port(dado_serial : in std_logic;
enable_transmissao : in std_logic;
TD : out std_logic);
end component;
component UC_transmissor is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
CTS : in std_logic;
DTR : out std_logic;
RTS : out std_logic;
enable_transmissao : out std_logic;
s_estado : out std_logic_vector(1 downto 0));
end component;
signal s_enable_transmissao : std_logic;
begin
k1 : UC_transmissor port map (liga, enviar, reset, clock, CTS, DTR, RTS, s_enable_transmissao, d_estado);
k2 : FD_transmissor port map (dado_serial, s_enable_transmissao, TD);
envioOk <= s_enable_transmissao;
end hierarquico;
|
mit
|
gustapp/labdig
|
Exp2/shiftReg.vhd
|
1
|
660
|
library ieee;
use ieee.std_logic_1164.all;
entity shiftReg is
port(clock : in std_logic;
load : in std_logic;
shift : in std_logic;
e_s : in std_logic;
bit_out : out std_logic_vector(11 downto 0) := '0');
end shiftReg;
architecture exemplo of shiftReg is
signal IQ : std_logic_vector(11 downto 0);
signal paridade : std_logic;
begin
process (clock, load, shift, IQ)
begin
if (clock'event and clock = '1') then
if (shift = '1') then
bit_out <= IQ(0);
IQ <= RIN & IQ(11 downto 1);
end if;
end if;
saida <= IQ;
end process;
end exemplo;
|
mit
|
jamesots/learnfpga
|
drum1/vhdl/debounce.vhdl
|
1
|
592
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity debounce is
port (
clk : in std_logic;
din : in std_logic;
dout : out std_logic
);
end debounce;
architecture behavioral of debounce is
begin
process(clk)
variable count : natural := 0;
variable value : std_logic := '0';
begin
if rising_edge(clk) then
if value /= din then
value := din;
count := 0;
else
count := count + 1;
if count = 1000000 then
dout <= value after 1 ns;
end if;
end if;
end if;
end process;
end behavioral;
|
mit
|
jamesots/learnfpga
|
analogue2/tb/clock_divider_tb.vhdl
|
1
|
1388
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY clock_divider_tb IS
END clock_divider_tb;
ARCHITECTURE behavior OF clock_divider_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock_divider
GENERIC (
divisor : integer
);
PORT(
clk_in : IN std_logic;
clk_out : OUT std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal clk_in : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal clk_out : std_logic;
-- Clock period definitions
constant clk_in_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock_divider
GENERIC MAP (
divisor => 2
)
PORT MAP (
clk_in => clk_in,
clk_out => clk_out,
reset => reset
);
-- Clock process definitions
clk_in_process :process
begin
clk_in <= '0';
wait for clk_in_period/2;
clk_in <= '1';
wait for clk_in_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_in_period*10;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
gustapp/labdig
|
tictactoe/board_dec.vhd
|
1
|
3586
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--- 0 1 2 | Q W E
--- 3 4 5 | A S D
--- 6 7 8 | Z X C
entity board_dec is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
char : in std_logic_vector(6 downto 0);
single_0 : out std_logic;
single_1 : out std_logic;
single_2 : out std_logic;
single_3 : out std_logic;
single_4 : out std_logic;
single_5 : out std_logic;
single_6 : out std_logic;
single_7 : out std_logic;
single_8 : out std_logic
);
end board_dec;
architecture board_decode_arch of board_dec is
-- Define ASCIIg
constant Q : std_logic_vector(6 downto 0) := "1010001";
constant W : std_logic_vector(6 downto 0) := "1010111";
constant E : std_logic_vector(6 downto 0) := "1000101";
constant A : std_logic_vector(6 downto 0) := "1000001";
constant S : std_logic_vector(6 downto 0) := "1010011";
constant D : std_logic_vector(6 downto 0) := "1000100";
constant Z : std_logic_vector(6 downto 0) := "1011010";
constant X : std_logic_vector(6 downto 0) := "1011000";
constant C : std_logic_vector(6 downto 0) := "1000011";
begin
process (clock, reset, enable, char)
begin
if reset = '1' then
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
elsif clock'event and clock = '1' then
case char is
when Q =>
single_0 <= '1';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when W =>
single_0 <= '0';
single_1 <= '1';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when E =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '1';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when A =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '1';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when S =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '1';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when D =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '1';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
when Z =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '1';
single_7 <= '0';
single_8 <= '0';
when X =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '1';
single_8 <= '0';
when C =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '1';
when others =>
single_0 <= '0';
single_1 <= '0';
single_2 <= '0';
single_3 <= '0';
single_4 <= '0';
single_5 <= '0';
single_6 <= '0';
single_7 <= '0';
single_8 <= '0';
end case;
end if;
end process;
end board_decode_arch;
|
mit
|
gustapp/labdig
|
Exp4/FD_transmissor.vhd
|
1
|
377
|
library ieee;
use ieee.std_logic_1164.all;
entity FD_transmissor is
port(dado_serial : in std_logic;
enable_transmissao : in std_logic;
TD : out std_logic);
end FD_transmissor;
architecture combinatorio of FD_transmissor is
begin
process (dado_serial, enable_transmissao)
begin
TD <= dado_serial and enable_transmissao;
end process;
end combinatorio;
|
mit
|
gustapp/labdig
|
Exp5/contador_mod8.vhd
|
1
|
711
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_mod8 is
port(clock : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(2 downto 0);
fim : out std_logic);
end contador_mod8;
architecture exemplo of contador_mod8 is
signal IQ: unsigned(2 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if clock'event and clock = '1' then
if zera = '1' then
IQ <= (others => '0');
elsif conta = '1' then
IQ <= IQ + 1;
end if;
end if;
if IQ = 7 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
|
mit
|
bravo95/SecondProcessor
|
mux01_tb.vhd
|
1
|
1520
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux01_tb IS
END mux01_tb;
ARCHITECTURE behavior OF mux01_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux01
PORT(
crs2 : IN std_logic_vector(31 downto 0);
i : IN std_logic;
seuin : IN std_logic_vector(31 downto 0);
muxout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
signal seuin : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal muxout : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux01 PORT MAP (
crs2 => crs2,
i => i,
seuin => seuin,
muxout => muxout
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
i <= '0';
crs2 <= "11111111111111111111111111111111";
seuin <= "00000000000000000000000000001111";
i <= '0';
wait for 10 ns;
i <= '1';
crs2 <= "11110000000000000000000000000000";
seuin <= "00000000000000000000000000001111";
wait for 10 ns;
i <= '0';
crs2 <= "11110000000000000000000000000000";
seuin <= "00000000000000000000000000001111";
-- insert stimulus here
wait;
end process;
END;
|
mit
|
bravo95/SecondProcessor
|
regis_tb.vhd
|
1
|
1530
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY regis_tb IS
END regis_tb;
ARCHITECTURE behavior OF regis_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT regis
PORT(
clk : IN std_logic;
rst : IN std_logic;
datain : IN std_logic_vector(31 downto 0);
dataout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal datain : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal dataout : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: regis PORT MAP (
clk => clk,
rst => rst,
datain => datain,
dataout => dataout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
--rst <= '1';
datain <= "00000001100000000000000011010000";
wait for 100 ns;
datain <= "00000000000010000000000011010000";
wait for 100 ns;
rst <= '1';
wait for 10 ns;
rst <= '0';
datain <= "00010000000000000000000011010000";
wait for 90 ns;
rst <= '1';
wait for 10 ns;
rst <= '0';
datain <= "00000000000000000000000001000000";
wait for 90 ns;
wait;
end process;
END;
|
mit
|
gustapp/labdig
|
exp4/recepção/fluxo_de_dados_recepcao.vhd
|
1
|
426
|
library ieee;
use ieee.std_logic_1164.all;
entity fluxo_de_dados_recepcao is
port(RD : in std_logic;
enable_recepcao : in std_logic;
DadoRecebido : out std_logic);
end fluxo_de_dados_recepcao;
architecture fluxo_de_dados_recepcao_arch of fluxo_de_dados_recepcao is
begin
process (RD, enable_recepcao)
begin
DadoRecebido <= RD and enable_recepcao;
end process;
end fluxo_de_dados_recepcao_arch;
|
mit
|
bravo95/SecondProcessor
|
mux01.vhd
|
1
|
514
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity mux01 is
Port ( crs2 : in STD_LOGIC_VECTOR (31 downto 0);
i : in STD_LOGIC;
seuin : in STD_LOGIC_VECTOR (31 downto 0);
muxout : out STD_LOGIC_VECTOR (31 downto 0));
end mux01;
architecture Behavioral of mux01 is
begin
process (i,seuin,crs2 )
begin
if (i = '1') then
muxout <= seuin;
else
muxout <= crs2;
end if;
end process;
end Behavioral;
|
mit
|
jamesots/learnfpga
|
midi2/vhdl/midi.vhdl
|
2
|
1348
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity midi is
port (
-- clk must be a 31.25Hz clock
clk : in std_logic;
load : in std_logic;
data_in : in std_logic_vector(7 downto 0);
midi_out : out std_logic := '0';
ready : out std_logic := '1'
);
end midi;
architecture behavioral of midi is
component shift_out is
generic (
width : integer
);
port (
par_in : in std_logic_vector(width - 1 downto 0);
load : in std_logic;
ser_out : out std_logic;
clk : in std_logic;
ce : in std_logic
);
end component;
signal ce : std_logic := '1';
signal step : integer range 0 to 10 := 10;
signal is_ready : std_logic := '1';
begin
shift : shift_out
generic map (
width => 10
)
port map (
par_in => '0' & not data_in & '1',
load => load and is_ready,
ser_out => midi_out,
clk => clk,
ce => ce
);
ready <= is_ready;
process(clk)
begin
if rising_edge(clk) then
if load = '1' and is_ready = '1' then
step <= 0 after 1ns;
is_ready <= '0' after 1ns;
else
if step = 7 then
is_ready <= '1' after 1ns;
end if;
if step < 10 then
step <= step + 1 after 1ns;
end if;
end if;
end if;
end process;
end behavioral;
|
mit
|
jamesots/learnfpga
|
midi/vhdl/shift_out.vhdl
|
1
|
661
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_out is
port (
par_in : in std_logic_vector(9 downto 0);
load : in std_logic;
ser_out : out std_logic;
clk : in std_logic;
ce : in std_logic
);
end shift_out;
architecture behavioral of shift_out is
signal par : std_logic_vector(9 downto 0);
begin
process(clk, load)
variable data : std_logic;
begin
if rising_edge(clk) then
if (load = '1') then
par <= par_in;
data := '0';
elsif (ce = '1') then
data := par(0);
par <= '0' & par(9 downto 1);
end if;
end if;
ser_out <= data;
end process;
end behavioral;
|
mit
|
gustapp/labdig
|
Exp5/SIPO_shiftReg.vhd
|
1
|
601
|
SIlibrary IEEE;
use IEEE.std_logic_1164.all;
entity SIPO_shiftReg is
port (clock, reset, enable : in std_logic;
input_data : in std_logic;
saida : out std_logic_vector(7 downto 0):= (others => '1'));
end SIPO_shiftReg;
architecture behavioral of SIPO_shiftReg is
signal IQ: std_logic_vector(7 downto 0);
begin
process(clock, reset, enable, input_data)
begin
if(clock'event and clock = '1' ) then
if reset = '1' then
IQ <= (others => '0');
elsif enable = '1' then
IQ <= input_data & IQ(7 downto 1);
end if;
end if;
end process;
saida <= IQ;
end behavioral;
|
mit
|
JavierRizzoA/Sacagawea
|
sources/registers/Register4.vhd
|
1
|
614
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register4 is
Port (
d : in STD_LOGIC_VECTOR(3 downto 0) := "0000"; --Input.
load : in STD_LOGIC; --Load/Enable.
clr : in STD_LOGIC; --Async clear.
clk : in STD_LOGIC; --Clock.
q : out STD_LOGIC_VECTOR(3 downto 0) :="0000" --Output
);
end Register4;
architecture Behavioral of Register4 is
begin
process(clk, clr)
begin
if rising_edge(clk) then
if clr = '1' then
q <= "0000";
elsif load = '1' then
q <= d;
end if;
end if;
end process;
end Behavioral;
|
mit
|
masaruohashi/tic-tac-toe
|
modem/modem_transmissao.vhd
|
1
|
3360
|
-- modem_transmissao.vhd
--
-- componente que modela a transmissao de dados do modem
-- => usar para os testes de simulacao do projeto final
--
-- ATENCAO:
-- mudar comentarios nas linhas 90 ou 91 para selecionar contagem de atraso do CTS (sintese vs simulacao)
--
-- Labdig (3o quadrimestre de 2017)
library IEEE;
use IEEE.std_logic_1164.all;
entity modem_transmissao is
port ( clock, reset, DTR, RTS, TD: in STD_LOGIC;
CTS, TC: out STD_LOGIC );
end;
architecture modem_transmissao of modem_transmissao is
type estados_tx is (inicial_tx, espera_rts, ativa_tempo_cts, espera_tempo_cts, ativa_cts, em_transmissao);
signal Eatual, Eprox: estados_tx;
signal clear,enable,fim: STD_LOGIC;
begin
-- state memory
process (RESET, CLOCK)
begin
if RESET = '1' then
Eatual <= inicial_tx;
elsif CLOCK'event and CLOCK = '1' then
Eatual <= Eprox;
end if;
end process;
-- next-state logic
process (DTR, RTS, fim, Eatual)
variable contagem : integer range 0 to 9999;
begin
case Eatual is
when inicial_tx => if DTR='0' then Eprox <= espera_rts;
else Eprox <= inicial_tx;
end if;
when espera_rts => if DTR='1' then Eprox <= inicial_tx;
elsif RTS='0' then Eprox <= ativa_tempo_cts;
else Eprox <= espera_rts;
end if;
when ativa_tempo_cts => Eprox <= espera_tempo_cts;
when espera_tempo_cts => if fim='0' then Eprox <= espera_tempo_cts;
else Eprox <= ativa_cts;
end if;
when ativa_cts => Eprox <= em_transmissao;
when em_transmissao => if DTR='1' then Eprox <= inicial_tx;
elsif RTS='0' then Eprox <= em_transmissao;
else Eprox <= espera_rts;
end if;
when others => Eprox <= inicial_tx;
end case;
end process;
-- saidas
with Eatual select
CTS <= '0' when ativa_cts|em_transmissao, '1' when others;
with Eatual select
TC <= TD when em_transmissao, '0' when others;
-- sinais de controle da contagem para atraso do CTS
with Eatual select
clear <= '1' when ativa_cts, '0' when others;
with Eatual select
enable <= '1' when espera_tempo_cts, '0' when others;
-- contagem (atraso do CTS)
process (clear,enable,CLOCK)
variable contagem: integer range 0 to 9999;
begin
if CLOCK'event and CLOCK = '1' then
if clear='1' then contagem := 0;
elsif enable='1' then contagem := contagem+1;
else contagem := contagem;
end if;
end if;
-- if contagem = 9999 then fim<='1'; -- para clock de 50MHz -> atraso de 20ns x 10.000=200us
if contagem = 9 then fim<='1'; -- para teste de simulacao (atraso de 10 clocks)
else fim<='0';
end if;
end process;
end modem_transmissao;
|
mit
|
JavierRizzoA/Sacagawea
|
prueba_procesador.vhd
|
6
|
1021
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
mit
|
masaruohashi/tic-tac-toe
|
logica_jogo/logica_jogo.vhd
|
1
|
2277
|
-- VHDL da logica do jogo da velha
library ieee;
use ieee.std_logic_1164.all;
entity logica_jogo is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
fim_recepcao : in std_logic;
jogador_atual : in std_logic;
entrada_dado : in std_logic_vector(6 downto 0);
recebe_dado : out std_logic;
guarda_dado : out std_logic;
jogo_acabado : out std_logic;
jogador_vencedor: out std_logic;
empate : out std_logic;
pronto : out std_logic;
estados : out std_logic_vector(2 downto 0)
);
end logica_jogo;
architecture estrutural of logica_jogo is
component unidade_controle_logica_jogo is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
fim_recepcao : in std_logic;
jogada_ok : in std_logic;
fim_jogo : in std_logic;
recebe_dado : out std_logic;
insere_dado : out std_logic;
jogo_acabado : out std_logic;
pronto : out std_logic;
estados : out std_logic_vector(2 downto 0)
);
end component;
component fluxo_dados_logica_jogo is
port(
clock : in std_logic;
reset : in std_logic;
jogador_atual : in std_logic;
escreve_memoria : in std_logic;
entrada_dado : in std_logic_vector(6 downto 0);
fim_jogo : out std_logic;
jogada_ok : out std_logic;
jogador_vencedor : out std_logic;
empate : out std_logic
);
end component;
signal s_guarda_dado: std_logic; -- relacionados a recepção do dado
signal s_fim_jogo, s_jogada_ok: std_logic; -- relacionados a validações/verificações
begin
UC: unidade_controle_logica_jogo port map (clock, reset, start, fim_recepcao, s_jogada_ok, s_fim_jogo, recebe_dado, s_guarda_dado, jogo_acabado, pronto, estados);
FD: fluxo_dados_logica_jogo port map(clock, reset, jogador_atual, s_guarda_dado, entrada_dado, s_fim_jogo, s_jogada_ok, jogador_vencedor, empate);
guarda_dado <= s_guarda_dado;
end estrutural;
|
mit
|
masaruohashi/tic-tac-toe
|
uart/contador_16_recepcao.vhd
|
1
|
949
|
-- VHDL de um contador de modulo 16
-- OBS: Para esse experimento so eh utilizada a contagem ate 11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_16_recepcao is
port(
clock : in std_logic;
enable : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(3 downto 0);
fim : out std_logic
);
end contador_16_recepcao;
architecture exemplo of contador_16_recepcao is
signal IQ: unsigned(3 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if zera = '1' then
IQ <= (others => '0');
elsif clock'event and clock = '1' then
if (conta = '1' and enable = '1') then
IQ <= IQ + 1;
end if;
end if;
if IQ = 11 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
|
mit
|
JavierRizzoA/Sacagawea
|
sources/SWITCHES.vhd
|
1
|
1346
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:01:45 06/05/2016
-- Design Name:
-- Module Name: SWITCHES - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SWITCHES is
Port (
clk : in STD_LOGIC;
switch_enable : in STD_LOGIC;
switch_datos : out std_logic_vector(7 downto 0);
switch_in : in STD_LOGIC_VECTOR (7 downto 0)
);
end SWITCHES;
architecture Behavioral of SWITCHES is
begin
process(clk)
begin
if(clk'event and clk = '1') then
if(switch_enable = '1') then
switch_datos <= switch_in;
else
switch_datos <= "ZZZZZZZZ";
end if;
end if;
end process;
end Behavioral;
|
mit
|
masaruohashi/tic-tac-toe
|
uart/interface_recepcao.vhd
|
1
|
1317
|
-- VHDL do interface recepcao
library ieee;
use ieee.std_logic_1164.all;
entity interface_recepcao is
port(
clock: in std_logic;
reset: in std_logic;
pronto: in std_logic;
paridade_ok: in std_logic;
recebe_dado: in std_logic;
dado_entrada: in std_logic_vector(11 downto 0);
tem_dado_rec: out std_logic;
dado_rec: out std_logic_vector(11 downto 0)
);
end interface_recepcao;
architecture estrutural of interface_recepcao is
component unidade_controle_interface_recepcao is
port(
clock: in std_logic;
reset: in std_logic;
pronto: in std_logic;
recebe_dado: in std_logic;
tem_dado_rec: out std_logic;
habilita_registrador: out std_logic
);
end component;
component fluxo_dados_interface_recepcao is
port(
clock: in std_logic;
enable: in std_logic;
entrada: in std_logic_vector(11 downto 0);
saida: out std_logic_vector(11 downto 0)
);
end component;
signal sinal_habilita_registrador: std_logic;
begin
unidade_controle: unidade_controle_interface_recepcao port map (clock, reset, pronto, recebe_dado, tem_dado_rec, sinal_habilita_registrador);
fluxo_dados: fluxo_dados_interface_recepcao port map(clock, sinal_habilita_registrador, dado_entrada, dado_rec);
end estrutural;
|
mit
|
masaruohashi/tic-tac-toe
|
uart/uart.vhd
|
1
|
2119
|
-- uart.vhd
-- VHDL do circuito da UART
library ieee;
use ieee.std_logic_1164.all;
entity uart is
port(
clock: in std_logic;
reset: in std_logic;
entrada: in std_logic;
recebe_dado: in std_logic;
transmite_dado: in std_logic;
dado_trans: in std_logic_vector(6 downto 0);
saida: out std_logic;
dado_rec: out std_logic_vector(6 downto 0);
tem_dado_rec: out std_logic;
transm_andamento: out std_logic;
fim_transmissao: out std_logic
);
end uart;
architecture estrutural of uart is
component transmissao_serial is
port(
clock: in std_logic;
reset: in std_logic;
transmite_dado: in std_logic;
dados_trans: in std_logic_vector(6 downto 0);
saida: out std_logic;
fim_transmissao: out std_logic;
transmissao_andamento: out std_logic;
depuracao_tick: out std_logic
);
end component;
component recepcao_serial is
port(
clock: in std_logic;
reset: in std_logic;
entrada: in std_logic;
recebe_dado: in std_logic;
dado_rec: out std_logic_vector(11 downto 0);
tem_dado_rec: out std_logic;
dep_paridade_ok: out std_logic;
dep_tick_rx: out std_logic;
dep_estados: out std_logic_vector(5 downto 0);
dep_habilita_recepcao: out std_logic
);
end component;
signal sinal_dado_rec: std_logic_vector(11 downto 0);
begin
transmissao: transmissao_serial port map (clock, reset, transmite_dado, dado_trans, saida, fim_transmissao, transm_andamento, open);
recepcao: recepcao_serial port map(clock, reset, entrada, recebe_dado, sinal_dado_rec, tem_dado_rec, open, open, open, open);
dado_rec <= sinal_dado_rec(8 downto 2);
--display_1: hex7seg_en port map(sinal_dado_rec(5), sinal_dado_rec(4), sinal_dado_rec(3), sinal_dado_rec(2), '1', dado_rec(0), dado_rec(1), dado_rec(2), dado_rec(3), dado_rec(4), dado_rec(5), dado_rec(6));
--display_2: hex7seg_en port map('0', sinal_dado_rec(8), sinal_dado_rec(7), sinal_dado_rec(6), '1', dado_rec(7), dado_rec(8), dado_rec(9), dado_rec(10), dado_rec(11), dado_rec(12), dado_rec(13));
end estrutural;
|
mit
|
aleksandar-mitrevski/hw_sw
|
explorer/map.vhd
|
1
|
574
|
library ieee;
use ieee.std_logic_1164.all;
use work.exploration_pkg.all;
entity ExplorationGrid is port (
currentCellsInView: in gridArray;
grid : out gridArray);
end ExplorationGrid;
architecture explorationGrid of ExplorationGrid is
signal exploredGrid : gridArray;
begin
process(currentCellsInView)
begin
for i in 0 to currentCellsInView'length-1 loop
exploredGrid(i) <= '1';
end loop;
end process;
process(exploredGrid)
begin
grid <= exploredGrid;
end process;
end explorationGrid;
|
mit
|
sgstair/ledsign
|
firmware/matrixdriver/main.vhd
|
1
|
15436
|
--
-- This source is released under the MIT License (MIT)
--
-- Copyright (c) 2016 Stephen Stair ([email protected])
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity main is
Port (
clk : in STD_LOGIC;
fpgaled : buffer std_logic;
led_r0 : out std_logic;
led_g0 : out std_logic;
led_b0 : out std_logic;
led_r1 : out std_logic;
led_g1 : out std_logic;
led_b1 : out std_logic;
led_A : out std_logic;
led_B : out std_logic;
led_C : out std_logic;
led_D : out std_logic;
led_OE : out std_logic;
led_STB : out std_logic;
led_CLK : out std_logic;
flash_clk : inout std_logic;
flash_mosi : inout std_logic;
flash_miso : inout std_logic;
dbgio1 : inout std_logic;
usb_dp : inout std_logic;
usb_dm : inout std_logic;
usb_connect : inout std_logic
);
end main;
architecture Behavioral of main is
component framebuffer is
Generic ( RamSizeBits : integer := 14 );
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
frame_addr : in unsigned( (RamSizeBits-1) downto 0);
frame_readdata : out std_logic_vector(31 downto 0);
access_addr : in unsigned ( (RamSizeBits-1) downto 0);
access_readdata : out std_logic_vector(31 downto 0);
access_writedata : in std_logic_vector(31 downto 0);
access_writeenable : in std_logic );
end component;
component usb_device is
Port ( clk : in STD_LOGIC;
usb_dp : inout STD_LOGIC;
usb_dm : inout STD_LOGIC;
usb_connect : inout std_logic;
syncreset : in STD_LOGIC;
interface_addr : out unsigned(15 downto 0);
interface_read : in std_logic_vector(31 downto 0);
interface_write : out std_logic_vector(31 downto 0);
interface_re : out std_logic;
interface_we : out std_logic;
trace_byte : out std_logic_vector(7 downto 0);
trace_pulse : out std_logic);
end component;
component tracefifo is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
write_data : in std_logic_vector(7 downto 0);
write_pulse : in std_logic;
read_data : out std_logic_vector(7 downto 0);
has_data : out std_logic;
read_pulse : in std_logic );
end component;
signal usb_addr : unsigned(15 downto 0);
signal usb_readdata : std_logic_vector(31 downto 0);
signal usb_writedata : std_logic_vector(31 downto 0);
signal usb_re : std_logic;
signal usb_we : std_logic;
signal counter : unsigned(29 downto 0) := (others => '0');
signal syncreset : std_logic := '1';
signal syncresetcount : unsigned(3 downto 0) := X"1";
signal request_scanline : std_logic := '0';
signal scanline_working : std_logic := '0';
signal scanline_complete : std_logic := '0';
signal scanline_y : unsigned(3 downto 0) := (others => '0');
signal scanline_out_y : unsigned(3 downto 0) := (others => '0');
signal scanline_r0 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_g0 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_b0 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_r1 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_g1 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_b1 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_pixel : std_logic := '0';
signal bit_position : unsigned(3 downto 0) := (others => '0');
signal led_on_time : unsigned(7 downto 0) := X"10";
signal led_on_counter : unsigned(17 downto 0) := (others => '0');
signal start_oe : std_logic := '0';
signal oe_working : std_logic := '0';
signal oe_done : std_logic := '0';
type led_state_type is ( startoutput, output, display, advance );
signal waitcount : unsigned(3 downto 0);
signal led_state : led_state_type := startoutput;
signal display_completed : std_logic := '0';
signal frameread_addr : unsigned(13 downto 0);
signal frameread_data : std_logic_vector(31 downto 0);
signal frameaccess_addr : unsigned(13 downto 0);
signal frameaccess_readdata : std_logic_vector(31 downto 0);
signal frameaccess_writedata : std_logic_vector(31 downto 0);
signal frameaccess_writeenable :std_logic;
signal pixel_delay : unsigned(1 downto 0);
signal scanline_state : unsigned(2 downto 0);
signal dummy_timer : unsigned(19 downto 0);
type spi_mode_type is (command, writeaddress, writedata);
signal spibits : std_logic_vector(31 downto 0);
signal spibit : unsigned(4 downto 0);
signal spimode : spi_mode_type;
signal spioutbyte : std_logic_vector(7 downto 0);
signal spi_write_address : std_logic_vector(15 downto 0);
signal spi_write_data : std_logic_vector(23 downto 0);
signal spi_address_toggle : std_logic;
signal spi_data_toggle : std_logic;
signal spi_trace_toggle : std_logic;
signal address_toggle_buffer : std_logic_vector(4 downto 0);
signal data_toggle_buffer : std_logic_vector(4 downto 0);
signal trace_toggle_buffer : std_logic_vector(4 downto 0);
signal trace_write : std_logic_vector(7 downto 0);
signal trace_read : std_logic_vector(7 downto 0);
signal trace_write_pulse : std_logic;
signal trace_read_pulse : std_logic;
signal trace_has_data : std_logic;
begin
framebufferram: framebuffer
generic map ( RamSizeBits => 14 )
port map (
clk => clk,
reset => syncreset,
frame_addr => frameread_addr,
frame_readdata => frameread_data,
access_addr => frameaccess_addr,
access_readdata => frameaccess_readdata,
access_writedata => frameaccess_writedata,
access_writeenable => frameaccess_writeenable
);
usb_device_inst : usb_device
port map (
clk => clk,
usb_dp => usb_dp,
usb_dm => usb_dm,
usb_connect => usb_connect,
syncreset => syncreset,
interface_addr => usb_addr,
interface_read => usb_readdata,
interface_write => usb_writedata,
interface_re => usb_re,
interface_we => usb_we,
trace_byte => trace_write,
trace_pulse => trace_write_pulse
);
traceblock : tracefifo
Port map (
clk => clk,
reset => syncreset,
write_data => trace_write,
write_pulse => trace_write_pulse,
read_data => trace_read,
has_data => trace_has_data,
read_pulse => trace_read_pulse
);
fpgaled <= '0';
process(clk)
begin
if clk'event and clk = '1' then
counter <= counter + 1;
-- Generate reset
if syncresetcount = 0 then
syncreset <= '0';
else
syncreset <= '1';
syncresetcount <= syncresetcount + 1;
end if;
end if;
end process;
-- System to pull data from the framebuffer for LED panel, two pixels per 4 cycles
process(clk)
begin
if clk'event and clk = '1' then
scanline_pixel <= '0';
if request_scanline = '1' then
if scanline_working = '0' then
scanline_working <= '1';
-- Prepare to read data
frameread_addr <= "00000" & scanline_y & "00000";
pixel_delay <= "00";
else
if scanline_complete = '0' then
case pixel_delay is
when "00" =>
frameread_addr(10) <= '0';
when "01" =>
frameread_addr(10) <= '1';
scanline_r0 <= "00" & frameread_data(23 downto 16);
scanline_g0 <= "00" & frameread_data(15 downto 8);
scanline_b0 <= "00" & frameread_data(7 downto 0);
when "10" =>
scanline_r1 <= "00" & frameread_data(23 downto 16);
scanline_g1 <= "00" & frameread_data(15 downto 8);
scanline_b1 <= "00" & frameread_data(7 downto 0);
scanline_pixel <= '1';
-- Advance to next pixel.
frameread_addr(4 downto 0) <= frameread_addr(4 downto 0) + 1;
when "11" =>
if frameread_addr(4 downto 0) = "00000" then
scanline_complete <= '1';
end if;
when others =>
end case;
pixel_delay <= pixel_delay + 1;
end if;
end if;
else
scanline_complete <= '0';
scanline_working <= '0';
end if;
if syncreset = '1' then
scanline_complete <= '0';
scanline_working <= '0';
end if;
end if;
end process;
-- System to output scanline data into the LED matrix
process(clk)
begin
if clk'event and clk = '1' then
case scanline_state is
when "000" =>
led_clk <= '0';
when "001" =>
led_r0 <= scanline_r0(to_integer(bit_position));
led_g0 <= scanline_g0(to_integer(bit_position));
led_b0 <= scanline_b0(to_integer(bit_position));
led_r1 <= scanline_r1(to_integer(bit_position));
led_g1 <= scanline_g1(to_integer(bit_position));
led_b1 <= scanline_b1(to_integer(bit_position));
led_clk <= '0';
scanline_state <= "010";
when "010" =>
led_clk <= '1';
scanline_state <= "011";
when "011" =>
led_clk <= '1';
scanline_state <= "000";
when others =>
scanline_state <= "000";
end case;
if scanline_pixel = '1' then
scanline_state <= "001";
end if;
if syncreset = '1' then
led_r0 <= '0';
led_g0 <= '0';
led_b0 <= '0';
led_r1 <= '0';
led_g1 <= '0';
led_b1 <= '0';
led_clk <= '0';
scanline_state <= "000";
end if;
end if;
end process;
-- System to output enable for a specific number of cycles
led_d <= scanline_out_y(3);
led_c <= scanline_out_y(2);
led_b <= scanline_out_y(1);
led_a <= scanline_out_y(0);
led_oe <= not oe_working;
process(clk)
begin
if clk'event and clk = '1' then
oe_done <= '0';
if oe_working = '1' then
led_on_counter <= led_on_counter - 1;
if led_on_counter = 0 then
oe_done <= '1';
oe_working <= '0';
end if;
end if;
if start_oe = '1' then
case to_integer(bit_position) is
when 0 => led_on_counter <= "0000000000" & led_on_time;
when 1 => led_on_counter <= "000000000" & led_on_time & "0";
when 2 => led_on_counter <= "00000000" & led_on_time & "00";
when 3 => led_on_counter <= "0000000" & led_on_time & "000";
when 4 => led_on_counter <= "000000" & led_on_time & "0000";
when 5 => led_on_counter <= "00000" & led_on_time & "00000";
when 6 => led_on_counter <= "0000" & led_on_time & "000000";
when 7 => led_on_counter <= "000" & led_on_time & "0000000";
when others =>
led_on_counter <= "0000000000" & led_on_time;
end case;
oe_working <= '1';
end if;
if syncreset = '1' then
oe_working <= '0';
end if;
end if;
end process;
-- Coordinating state machine
process(clk)
begin
if clk'event and clk = '1' then
led_STB <= '0';
start_oe <= '0';
case led_state is
when startoutput =>
-- start pushing data into the display for a scanline
request_scanline <= '1';
led_state <= output;
when output =>
-- Wait until we're done with the scanline and the previous display
waitcount <= (others => '0');
if scanline_complete = '1' and oe_working = '0' then
request_scanline <= '0';
led_state <= display;
end if;
when display =>
-- Add a few cycles of delay to prevent any potential bleeding issues while latching data.
waitcount <= waitcount + 1;
case to_integer(waitcount) is
when 5 =>
-- Strobe to latch data, latch scanline out bits
led_STB <= '1';
scanline_out_y <= scanline_y;
when 10 =>
-- Start the display and move on to the next phase.
start_oe <= '1';
led_state <= advance;
when others =>
end case;
when advance =>
-- advance to the next bit position or scanline.
if bit_position = 7 then
scanline_y <= scanline_y + 1;
bit_position <= (others => '0');
else
bit_position <= bit_position + 1;
end if;
led_state <= startoutput;
when others =>
led_state <= startoutput;
end case;
if syncreset='1' then
led_state <= startoutput;
bit_position <= (others => '0');
scanline_y <= (others => '0');
scanline_out_y <= (others => '0');
waitcount <= (others => '0');
end if;
end if;
end process;
-- SPI interface
process(clk)
begin
if clk'event and clk = '1' then
frameaccess_writeenable <= '0';
trace_read_pulse <= '0';
address_toggle_buffer <= spi_address_toggle & address_toggle_buffer(4 downto 1);
data_toggle_buffer <= spi_data_toggle & data_toggle_buffer(4 downto 1);
trace_toggle_buffer <= spi_trace_toggle & trace_toggle_buffer(4 downto 1);
if trace_toggle_buffer(1) /= trace_toggle_buffer(0) then
trace_read_pulse <= '1';
end if;
if data_toggle_buffer(1) /= data_toggle_buffer(0) then
frameaccess_writedata <= X"00" & spi_write_data;
frameaccess_writeenable <= '1';
end if;
if frameaccess_writeenable = '1' then
frameaccess_addr <= frameaccess_addr + 1; -- Advance address on the next cycle.
end if;
if address_toggle_buffer(1) /= address_toggle_buffer(0) then
frameaccess_addr <= unsigned(spi_write_address(13 downto 0));
end if;
if syncreset = '1' then
address_toggle_buffer <= (others => '0');
data_toggle_buffer <= (others => '0');
end if;
end if;
end process;
spibits(0) <= flash_mosi;
flash_miso <= 'Z' when dbgio1 = '1' else spioutbyte(7);
process(flash_clk)
begin
if dbgio1 = '1' then -- CS signal is inactive
spibit <= (others => '0');
spioutbyte <= (others => '0');
spimode <= command;
elsif flash_clk'event and flash_clk = '1' then
spibits(31 downto 1) <= spibits(30 downto 0); -- Shift bits and prepare for next cycle.
spioutbyte <= spioutbyte(6 downto 0) & '0';
spibit <= spibit + 1;
case spimode is
when command =>
if spibit = 7 then
-- Decide what to do based on command in spibits(7 downto 0).
-- For now just treat all command bytes as a write data command.
spibit <= (others => '0');
spimode <= writeaddress;
end if;
when writeaddress =>
if spibit = 15 then
spi_write_address <= spibits(15 downto 0);
spibit <= (others => '0');
spi_address_toggle <= not spi_address_toggle;
spimode <= writedata;
end if;
when writedata =>
if spibit = 23 then
spi_write_data <= spibits(23 downto 0);
spibit <= (others => '0');
spi_data_toggle <= not spi_data_toggle;
end if;
when others =>
end case;
if spibit(2 downto 0) = 7 then
spi_trace_toggle <= not spi_trace_toggle;
spioutbyte <= trace_read;
end if;
end if;
end process;
end Behavioral;
|
mit
|
masterdezign/cellular-automata-clash-fpga
|
src/vhdl/Cellular/Cellular/Cellular.vhdl
|
1
|
4730
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.cellular_types.all;
entity Cellular is
port(-- clock
CLOCK : in cellular_types.clk_system;
-- reset
RST : in cellular_types.rst_system;
en : in boolean;
current_state : out std_logic_vector(15 downto 0));
end;
architecture structural of Cellular is
-- Cellular.hs:18:1-9
signal \c$r_rec\ : std_logic_vector(15 downto 0);
-- FPGA/CellularArray2.hs:(21,1)-(29,29)
signal prev : std_logic_vector(15 downto 0);
signal result : std_logic_vector(15 downto 0);
signal \c$tup_app_arg\ : cellular_types.array_of_std_logic_vector_1(0 to 15);
signal result_0 : cellular_types.array_of_std_logic(0 to 15);
-- FPGA/CellularArray2.hs:(21,1)-(29,29)
signal xs : cellular_types.array_of_std_logic_vector_16(0 to 15);
-- FPGA/CellularArray2.hs:(21,1)-(29,29)
signal \c$xs_app_arg\ : cellular_types.array_of_std_logic_vector_16(0 to 15);
-- Cellular.hs:18:1-9
signal cnt : unsigned(23 downto 0);
signal \c$vec\ : cellular_types.array_of_std_logic_vector_16(0 to 16);
signal \c$vec_0\ : cellular_types.array_of_std_logic_vector_16(0 to 15);
begin
-- register begin
cellular_register : block
signal cr_rec_reg : std_logic_vector(15 downto 0) := std_logic_vector'(x"0000") ;
begin
\c$r_rec\ <= cr_rec_reg;
cr_rec_r : process(CLOCK,RST)
begin
if RST = '1' then
cr_rec_reg <= std_logic_vector'(x"0000");
elsif rising_edge(CLOCK) then
if (en and (cnt = to_unsigned(0,24))) then
cr_rec_reg <= prev
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end if;
end process;
end block;
-- register end
-- register begin
cellular_register_0 : block
signal prev_reg : std_logic_vector(15 downto 0) := std_logic_vector'(x"0001") ;
begin
prev <= prev_reg;
prev_r : process(CLOCK,RST)
begin
if RST = '1' then
prev_reg <= std_logic_vector'(x"0001");
elsif rising_edge(CLOCK) then
if en then
prev_reg <= result
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end if;
end process;
end block;
-- register end
-- concatBitVector begin
concatbitvectoriter_loop : for i in 0 to (16 - 1) generate
result(((i * 1) + 1 - 1) downto (i * 1)) <= std_logic_vector'(\c$tup_app_arg\(\c$tup_app_arg\'high - i));
end generate;
-- concatBitVector end
-- map begin
map_r : for i_0 in \c$tup_app_arg\'range generate
begin
\c$tup_app_arg\(i_0) <= std_logic_vector'(0 => result_0(i_0));
end generate;
-- map end
-- map begin
map_r_0 : for i_1 in result_0'range generate
begin
fun : block
-- FPGA/CellularArray2.hs:(21,1)-(29,29)
signal wild1 : signed(63 downto 0);
signal \c$bv\ : std_logic_vector(7 downto 0);
begin
wild1 <= (signed(std_logic_vector(resize(unsigned((xs(i_1)(2 downto 0))),64))));
\c$bv\ <= std_logic_vector'(x"6E");
-- indexBitVector begin
indexbitvector : block
signal vec_index : integer range 0 to 8-1;
begin
vec_index <= to_integer((wild1))
-- pragma translate_off
mod 8
-- pragma translate_on
;
result_0(i_1) <= \c$bv\(vec_index);
end block;
-- indexBitVector end
end block;
end generate;
-- map end
\c$vec\ <= cellular_types.array_of_std_logic_vector_16'(std_logic_vector'(std_logic_vector(rotate_left(unsigned(\c$r_rec\),to_integer(to_signed(2,64))))) & \c$xs_app_arg\);
xs <= \c$vec\(0 to \c$vec\'high - 1);
\c$vec_0\ <= (xs);
-- map begin
map_r_1 : for i_2 in \c$xs_app_arg\'range generate
begin
\c$xs_app_arg\(i_2) <= std_logic_vector(rotate_left(unsigned(\c$vec_0\(i_2)),to_integer(to_signed(1,64))));
end generate;
-- map end
-- register begin
cellular_register_1 : block
signal cnt_reg : unsigned(23 downto 0) := to_unsigned(0,24) ;
begin
cnt <= cnt_reg;
cnt_r : process(CLOCK,RST)
begin
if RST = '1' then
cnt_reg <= to_unsigned(0,24);
elsif rising_edge(CLOCK) then
if en then
cnt_reg <= (cnt + to_unsigned(1,24))
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end if;
end process;
end block;
-- register end
current_state <= \c$r_rec\;
end;
|
mit
|
fabianz66/cursos-tec
|
taller-digital/Proyecto Final/tec-drums/ipcore_dir/memoria/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
mit
|
fabianz66/cursos-tec
|
taller-digital/Proyecto Final/Referencias/fpga/ipcore_dir/hw_multiplier.vhd
|
1
|
4208
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file hw_multiplier.vhd when simulating
-- the core, hw_multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY hw_multiplier IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END hw_multiplier;
ARCHITECTURE hw_multiplier_a OF hw_multiplier IS
-- synthesis translate_off
COMPONENT wrapped_hw_multiplier
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_hw_multiplier USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 32,
c_b_type => 0,
c_b_value => "10000001",
c_b_width => 32,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 1,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 63,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_hw_multiplier
PORT MAP (
clk => clk,
a => a,
b => b,
p => p
);
-- synthesis translate_on
END hw_multiplier_a;
|
mit
|
aleksandar-mitrevski/hw_sw
|
hybrid_velocity_counter/testbench.vhd
|
1
|
2190
|
library IEEE;
use IEEE.std_logic_1164.All;
use std.textio.all;
entity testbench is end testbench;
architecture tb_velocity of testbench is
signal clk : std_logic := '0';
signal encoder : std_logic := '0';
signal speed : real;
signal measurementType : std_logic;
file encoder_switching_times : text open read_mode is "switching_times.dat";
constant twenty_five_nsec : time := 25 ns;
component HybridVelocityCounter port (
clk : in std_logic;
encoder : in std_logic;
speed : out real;
measurementType: out std_logic);
end component HybridVelocityCounter;
begin
HybridVelocityCounter1 : HybridVelocityCounter
port map (
clk => clk,
encoder => encoder,
speed => speed,
measurementType => measurementType);
create_twenty_Mhz: process
begin
wait for twenty_five_nsec;
clk <= NOT clk;
end process;
change_encoder: process
variable currentLine : line;
variable waitTime : time;
variable timeChange : integer := 0;
begin
while not (endfile(encoder_switching_times)) loop
if timeChange = 1500 then
assert measurementType = '0' report "1 failed";
elsif timeChange = 3000 then
assert measurementType = '0' report "2 failed";
elsif timeChange = 4500 then
assert measurementType = '1' report "3 failed";
elsif timeChange = 6000 then
assert measurementType = '1' report "4 failed";
elsif timeChange = 7500 then
assert measurementType = '1' report "5 failed";
elsif timeChange = 9000 then
assert measurementType = '1' report "6 failed";
elsif timeChange = 10500 then
assert measurementType = '0' report "7 failed";
end if;
readline(encoder_switching_times, currentLine);
read(currentLine, waitTime);
timeChange := timeChange + (waitTime / 1 ns);
wait for waitTime;
encoder <= not encoder;
end loop;
wait;
end process;
end tb_velocity;
|
mit
|
Reiuiji/VHDL-Emporium
|
VHDL/Memory/TB_GenReg_16.vhd
|
1
|
2356
|
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_REG_S16 is
end TB_REG_S16;
architecture Behavioral of TB_REG_S16 is
component REG_S16 is
generic(
REG_WIDTH: integer:=4 -- select between 16 different possible registers
);
port(
CLOCK : in std_logic;
WE : in std_logic;
RESETN : in std_logic;
--Register A
REG_A_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
--Register B
REG_B_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_B : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
REG_A_IN_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
CONSTANT REG_WIDTH:integer:=4;
signal CLOCK : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal RESETN : STD_LOGIC := '0';
signal REG_A_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_B_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_B : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_A_IN_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A_IN : std_logic_vector(DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 15 24bit General purpose register
Reg1: REG_S16 port map(
CLOCK => Clock,
WE => WE,
RESETN => RESETN,
REG_A_ADDR => REG_A_ADDR,
REG_A => REG_A,
REG_B_ADDR => REG_B_ADDR,
REG_B => REG_B,
REG_A_IN_ADDR => REG_A_IN_ADDR,
REG_A_IN => REG_A_IN
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
REG_A_ADDR <= (others => '0');
REG_B_ADDR <= (others => '0');
REG_A_IN_ADDR <= (others => '0');
--Reset disable
RESETN <= '1'; wait for 2*period;
REG_A_IN <= x"FFFFFF";wait for 2*period;
--Enabling the register
WE <= '1'; wait for 2*period;
WE <= '0';
REG_A_IN_ADDR <= x"1";
WE <= '1'; wait for 2*period;
WE <= '0';
REG_B_ADDR <= x"1"; wait for 50*period;
end process;
end Behavioral;
|
mit
|
Reiuiji/VHDL-Emporium
|
VHDL/VGA Read - Write/scan_to_hex_tb.vhd
|
1
|
3771
|
--------------------------------------------------------------------------------
-- Company: UMD ECE
-- Engineers: Benjamin Doiron, Daniel Noyes
--
-- Create Date: 12:35:25 03/26/2014
-- Design Name: Scan to Hex Testbench
-- Module Name: scan_to_hex_tb
-- Project Name: Risc Machine Project 1
-- Target Device: Spartan 3E Board
-- Tool versions: Xilinx 14.7
-- Description: This is the testbench for reading scancodes and changing them into hex.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY scan_to_hex_tb IS
END scan_to_hex_tb;
ARCHITECTURE behavior OF scan_to_hex_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT scan_to_hex
PORT(
Send : IN std_logic;
Resetn : IN std_logic;
scancode : IN std_logic_vector(7 downto 0);
output : OUT std_logic_vector(23 downto 0);
outCount : out STD_LOGIC_VECTOR (3 downto 0);
hexdebug : out STD_LOGIC_VECTOR (3 downto 0);
outbufdebug : out STD_LOGIC_VECTOR (63 downto 0)
);
END COMPONENT;
--Inputs
signal Send : std_logic := '0';
signal Resetn : std_logic := '0';
signal scancode : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal hexdebug : std_logic_vector(3 downto 0);
signal output : std_logic_vector(23 downto 0);
signal counter : std_logic_vector(3 downto 0);
signal outbufdebug : STD_LOGIC_VECTOR (63 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: scan_to_hex PORT MAP (
Send => Send,
Resetn => Resetn,
scancode => scancode,
output => output,
outCount => counter,
hexdebug => hexdebug,
outbufdebug => outbufdebug
);
-- Stimulus process
stim_proc: process
begin
Resetn <= '1';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"26";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"26";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"5A";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"36";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"46";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"36";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"46";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"23";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"23";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"5A";
wait for 20 ns;
send <= '0';
end process;
END;
|
mit
|
fabianz66/cursos-tec
|
taller-digital/Proyecto Final/proyecto-final/test_i2s.vhd
|
1
|
3406
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:00 10/29/2013
-- Design Name:
-- Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/proyecto-final/test_i2s.vhd
-- Project Name: proyecto-final
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2s_output
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_i2s IS
END test_i2s;
ARCHITECTURE behavior OF test_i2s IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2s_output
PORT(
clk : IN std_logic;
data_l : IN std_logic_vector(15 downto 0);
data_r : IN std_logic_vector(15 downto 0);
accepted : OUT std_logic;
i2s_sd : OUT std_logic;
i2s_lrclk : OUT std_logic;
i2s_sclk : OUT std_logic;
i2s_mclk : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal data_l : std_logic_vector(15 downto 0) := (others => '0');
signal data_r : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal accepted : std_logic;
signal i2s_sd : std_logic;
signal i2s_lrclk : std_logic;
signal i2s_sclk : std_logic;
signal i2s_mclk : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant i2s_lrclk_period : time := 10 ns;
constant i2s_sclk_period : time := 10 ns;
constant i2s_mclk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2s_output PORT MAP (
clk => clk,
data_l => data_l,
data_r => data_r,
accepted => accepted,
i2s_sd => i2s_sd,
i2s_lrclk => i2s_lrclk,
i2s_sclk => i2s_sclk,
i2s_mclk => i2s_mclk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
i2s_lrclk_process :process
begin
i2s_lrclk <= '0';
wait for i2s_lrclk_period/2;
i2s_lrclk <= '1';
wait for i2s_lrclk_period/2;
end process;
i2s_sclk_process :process
begin
i2s_sclk <= '0';
wait for i2s_sclk_period/2;
i2s_sclk <= '1';
wait for i2s_sclk_period/2;
end process;
i2s_mclk_process :process
begin
i2s_mclk <= '0';
wait for i2s_mclk_period/2;
i2s_mclk <= '1';
wait for i2s_mclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
fabianz66/cursos-tec
|
taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/memoria/example_design/memoria_exdes.vhd
|
2
|
4328
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: memoria_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY memoria_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END memoria_exdes;
ARCHITECTURE xilinx OF memoria_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT memoria IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : memoria
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
mit
|
fabianz66/cursos-tec
|
taller-digital/Proyecto Final/proyecto-final/i2s_output.vhd
|
1
|
2363
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Generate I2S audio stream and master clock for the PMODI2S.
-- The chip is a Cirrus Logic CS4344 DAC
--
-- Drive with a 100MHz clock for 48,828 samples per second
--
-- 'accepted' will strobe when 'data_l' and 'data_r' are latched
--
-- 'data_l' and 'data_r' are assumed to be signed values.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2s_output is
Port ( clk : in STD_LOGIC;
data_l : in STD_LOGIC_VECTOR (15 downto 0);
data_r : in STD_LOGIC_VECTOR (15 downto 0);
accepted : out STD_LOGIC;
i2s_sd : out STD_LOGIC;
i2s_lrclk : out STD_LOGIC;
i2s_sclk : out STD_LOGIC;
i2s_mclk : out STD_LOGIC);
end i2s_output;
architecture Behavioral of i2s_output is
signal advance : std_logic := '0';
signal divider : unsigned( 4 downto 0) := (others => '0');
signal step : unsigned( 5 downto 0) := (others => '0');
signal shift_out : std_logic_vector(16 downto 0) := (others => '0');
signal hold_r : std_logic_vector(15 downto 0) := (others => '0');
begin
i2s_lrclk <= std_logic(step(5));
i2s_mclk <= std_logic(divider(1));
i2s_sclk <= std_logic(step(0));
i2s_sd <= shift_out(shift_out'high);
process(clk)
begin
if rising_edge(clk) then
accepted <= '0';
if advance = '1' then
if step(0) = '1' then
shift_out <= shift_out(shift_out'high-1 downto 0) & '1';
if step(5 downto 1) = "01111" then
shift_out(15 downto 0) <= hold_r;
elsif step(5 downto 1) = "11111" then
shift_out(15 downto 0) <= data_l xor x"8000";
hold_r <= data_r xor x"8000";
accepted <= '1';
end if;
end if;
step <= step + 1;
end if;
if divider = 0 then
advance <= '1';
else
advance <= '0';
end if;
divider <= divider + 1;
end if;
end process;
end Behavioral;
|
mit
|
Reiuiji/VHDL-Emporium
|
VHDL/Registers/Reg_Rising.vhd
|
1
|
1639
|
------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: RegF
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
--
-- Notes:
-- Clocked on RISING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the rising
-- clock cycle.
--
-- Additional Comments:
-- The register latches it's data on the RISING edge
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY RegR IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END RegR;
ARCHITECTURE Behavior OF RegR IS
BEGIN
PROCESS(Resetn, Clock,ENABLE)
BEGIN
IF Resetn = '0' THEN
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '1' THEN
OUTPUT <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
|
mit
|
aleksandar-mitrevski/hw_sw
|
filtered_edge_detector/filter_edge_detector_testbench.vhd
|
1
|
1595
|
library IEEE;
use IEEE.std_logic_1164.All;
entity filtered_edge_detector_testbench is end filtered_edge_detector_testbench;
architecture tb_filtered_edge_detector of filtered_edge_detector_testbench is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal level : std_logic := '0';
signal levelFiltered : std_logic := '0';
signal tick : std_logic;
constant twenty_five_nsec : time := 25 ns;
component FilteredEdgeDetector port (
clk : in std_logic;
reset : in std_logic;
level : in std_logic;
levelFiltered : inout std_logic;
tick : out std_logic);
end component FilteredEdgeDetector;
begin
FilteredEdgeDetector1 : FilteredEdgeDetector
port map (
clk => clk,
reset => reset,
level => level,
levelFiltered => levelFiltered,
tick => tick);
create_twenty_Mhz: process
begin
wait for twenty_five_nsec;
clk <= NOT clk;
end process;
level <= '1' after 20 ns,
'0' after 40 ns,
'1' after 100 ns,
'0' after 210 ns,
'1' after 225 ns,
'0' after 300 ns,
'1' after 500 ns,
'0' after 520 ns,
'1' after 540 ns,
'0' after 700 ns,
'1' after 730 ns,
'0' after 740 ns,
'1' after 900 ns,
'0' after 1100 ns,
'1' after 1300 ns,
'0' after 1340 ns,
'1' after 1350 ns,
'0' after 1500 ns;
end tb_filtered_edge_detector;
|
mit
|
Reiuiji/VHDL-Emporium
|
VHDL/Control Flow/MUX_4to1.vhd
|
1
|
648
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.UMDRISC_pkg.ALL;
entity MUX_4to1 is
Port (
SEL : in STD_LOGIC_VECTOR (1 downto 0); -- 4 bits
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_3 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_4 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end MUX_4to1;
architecture Behavioral of MUX_4to1 is
begin
with SEL select
OUTPUT<= IN_1 when "00",
IN_2 when "01",
IN_3 when "10",
IN_4 when others;
end Behavioral;
|
mit
|
ErikAndren/fpga-sramtest
|
SramTestGen.vhd
|
1
|
2929
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity SramTestGen is
generic (
AddrW : positive;
DataW : positive);
port (
Clk : in bit1;
Rst_N : in bit1;
--
Btn0 : in bit1;
Btn1 : in bit1;
Btn2 : in bit1;
Btn3 : in bit1;
--
We : out bit1;
Re : out bit1;
Addr : out word(AddrW-1 downto 0);
Data : out word(DataW-1 downto 0)
);
end entity SramTestGen;
architecture rtl of SramTestGen is
constant StartCnt : positive := 25000000;
signal StartCnt_D, StartCnt_N : word(bits(StartCnt)-1 downto 0);
signal Data_D, Data_N : word(4-1 downto 0);
signal Addr_D, Addr_N : word(2-1 downto 0);
signal Btn_D : word(4-1 downto 0);
signal StrobeCnt_D, StrobeCnt_N : word(bits(StartCnt)-1 downto 0);
begin -- rtl
StimSync : process (Clk, Rst_N)
begin -- process Stim
if Rst_N = '0' then -- asynchronous reset (active low)
StartCnt_D <= conv_word(StartCnt, StartCnt_D'length);
Data_D <= (others => '0');
Addr_D <= (others => '0');
Btn_D <= (others => '1');
StrobeCnt_D <= conv_word(StartCnt, StrobeCnt_D'length);
elsif Clk'event and Clk = '1' then -- rising clock edge
StartCnt_D <= StartCnt_N;
Data_D <= Data_N;
Addr_D <= Addr_N;
Btn_D <= Btn3 & Btn2 & Btn1 & Btn0;
StrobeCnt_D <= StrobeCnt_N;
end if;
end process StimSync;
StimAsync : process (StartCnt_D, Data_D, Addr_D, StrobeCnt_D, Btn0, Btn1)
begin
StartCnt_N <= StartCnt_D;
StrobeCnt_N <= StrobeCnt_D - 1;
--
We <= '0';
Re <= '0';
Addr <= (others => '0');
Data <= (others => '0');
Data_N <= Data_D;
Addr_N <= Addr_D;
if StartCnt_D > 0 then
StartCnt_N <= StartCnt_D - 1;
end if;
-- Perform write
if StartCnt_D = 12 then
We <= '1';
Addr <= (others => '0');
Data <= xt0("1111", Data'length);
end if;
if StartCnt_D = 10 then
We <= '1';
Addr <= conv_word(1, Addr'length);
Data <= xt0("1110", Data'length);
end if;
if StartCnt_D = 8 then
We <= '1';
Addr <= conv_word(2, Addr'length);
Data <= xt0("1100", Data'length);
end if;
if StartCnt_D = 6 then
We <= '1';
Addr <= conv_word(3, Addr'length);
Data <= xt0("1000", Data'length);
end if;
-- Perform first read
if StartCnt_D = 1 then
Re <= '1';
Addr <= (others => '0');
end if;
if (StrobeCnt_D = 0) then
if (Btn0 = '0') then
Addr_N <= Addr_D + 1;
Re <= '1';
Addr <= xt0(Addr_D + 1, Addr'length);
end if;
if (Btn1 = '0') then
Addr_N <= Addr_D - 1;
Re <= '1';
Addr <= xt0(Addr_D - 1, Addr'length);
end if;
end if;
end process;
end rtl;
|
mit
|
ziyan/altera-de2-ann
|
src/lib/float/fp_sub.vhd
|
1
|
253996
|
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: fp_sub.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" DIRECTION="SUB" OPTIMIZE="SPEED" PIPELINE=7 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_altfp_add_sub 2010:03:24:20:34:20:SJ cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altbarrel_shift_h0e IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END fp_sub_altbarrel_shift_h0e;
ARCHITECTURE RTL OF fp_sub_altbarrel_shift_h0e IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w718w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w740w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w762w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w722w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w744w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w713w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w757w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w680w(0) AND wire_lbarrel_shift_w678w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w675w(0) AND wire_lbarrel_shift_w674w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w701w(0) AND wire_lbarrel_shift_w699w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w696w(0) AND wire_lbarrel_shift_w695w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w723w(0) AND wire_lbarrel_shift_w721w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w718w(0) AND wire_lbarrel_shift_w717w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w745w(0) AND wire_lbarrel_shift_w743w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w740w(0) AND wire_lbarrel_shift_w739w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w767w(0) AND wire_lbarrel_shift_w765w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w762w(0) AND wire_lbarrel_shift_w761w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w670w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w691w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w713w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w735w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w757w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w680w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w679w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w675w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w701w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w700w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w696w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w723w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w722w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w718w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w745w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w744w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w740w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w767w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w766w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w762w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w679w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w700w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w722w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w744w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w766w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w670w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w691w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w713w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w735w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w757w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w770w & wire_lbarrel_shift_w748w & wire_lbarrel_shift_w726w & wire_lbarrel_shift_w704w & wire_lbarrel_shift_w683w);
wire_lbarrel_shift_w674w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w678w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w695w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w699w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w717w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w721w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w739w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w743w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w761w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w765w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range771w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range771w;
END IF;
END IF;
END PROCESS;
END RTL; --fp_sub_altbarrel_shift_h0e
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 data distance result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altbarrel_shift_6hb IS
PORT
(
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END fp_sub_altbarrel_shift_6hb;
ARCHITECTURE RTL OF fp_sub_altbarrel_shift_6hb IS
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w789w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w815w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w810w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w837w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w832w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w859w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w854w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range779w793w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range801w814w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range822w836w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range844w858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w784w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w805w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w884w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w788w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w792w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w809w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w813w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w831w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w835w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w853w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w857w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w879w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range822w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range777w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range800w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w794w(0) AND wire_rbarrel_shift_w792w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w789w(0) AND wire_rbarrel_shift_w788w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w815w(0) AND wire_rbarrel_shift_w813w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w810w(0) AND wire_rbarrel_shift_w809w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w837w(0) AND wire_rbarrel_shift_w835w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w832w(0) AND wire_rbarrel_shift_w831w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w859w(0) AND wire_rbarrel_shift_w857w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w854w(0) AND wire_rbarrel_shift_w853w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w881w(0) AND wire_rbarrel_shift_w879w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w876w(0) AND wire_rbarrel_shift_w875w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w784w(0) AND wire_rbarrel_shift_w_sbit_w_range777w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w805w(0) AND wire_rbarrel_shift_w_sbit_w_range800w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w827w(0) AND wire_rbarrel_shift_w_sbit_w_range820w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w849w(0) AND wire_rbarrel_shift_w_sbit_w_range842w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w871w(0) AND wire_rbarrel_shift_w_sbit_w_range864w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range782w794w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range779w793w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w789w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w815w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range801w814w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w810w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w837w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range822w836w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w832w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w859w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range844w858w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w854w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w881w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w880w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w876w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range779w793w(0) <= NOT wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range801w814w(0) <= NOT wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range822w836w(0) <= NOT wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range844w858w(0) <= NOT wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w880w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w784w(0) <= NOT wire_rbarrel_shift_w_sel_w_range782w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w805w(0) <= NOT wire_rbarrel_shift_w_sel_w_range803w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w827w(0) <= NOT wire_rbarrel_shift_w_sel_w_range825w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w849w(0) <= NOT wire_rbarrel_shift_w_sel_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w871w(0) <= NOT wire_rbarrel_shift_w_sel_w_range869w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w797w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w818w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w840w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w862w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w884w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w884w & wire_rbarrel_shift_w862w & wire_rbarrel_shift_w840w & wire_rbarrel_shift_w818w & wire_rbarrel_shift_w797w);
wire_rbarrel_shift_w788w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w792w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w809w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w813w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w831w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w835w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w853w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w857w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w875w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w879w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range779w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range801w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range822w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range844w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range842w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range864w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range777w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range800w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range820w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range782w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range803w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range825w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range847w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range869w(0) <= sel_w(4);
END RTL; --fp_sub_altbarrel_shift_6hb
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_3e8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --fp_sub_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_6e8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero920w921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero922w923w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero920w & wire_altpriority_encoder14_w_lg_w_lg_zero922w923w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0) <= wire_altpriority_encoder14_w_lg_zero920w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero922w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero920w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero922w923w(0) <= wire_altpriority_encoder14_w_lg_zero922w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0);
altpriority_encoder14 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --fp_sub_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_be8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero910w911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero910w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero912w913w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero910w & wire_altpriority_encoder12_w_lg_w_lg_zero912w913w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i) <= wire_altpriority_encoder12_w_lg_zero910w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero912w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero910w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero912w913w(i) <= wire_altpriority_encoder12_w_lg_zero912w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i);
END GENERATE loop52;
altpriority_encoder12 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --fp_sub_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END fp_sub_altpriority_encoder_3v7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --fp_sub_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fp_sub_altpriority_encoder_6v7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero945w946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero947w948w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero945w & wire_altpriority_encoder18_w_lg_w_lg_zero947w948w);
altpriority_encoder17 : fp_sub_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0) <= wire_altpriority_encoder18_w_lg_zero945w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero947w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero945w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero947w948w(0) <= wire_altpriority_encoder18_w_lg_zero947w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0);
altpriority_encoder18 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --fp_sub_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END fp_sub_altpriority_encoder_bv7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero936w937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero936w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero938w939w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero936w & wire_altpriority_encoder16_w_lg_w_lg_zero938w939w);
altpriority_encoder15 : fp_sub_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i) <= wire_altpriority_encoder16_w_lg_zero936w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero938w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero936w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero938w939w(i) <= wire_altpriority_encoder16_w_lg_zero938w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i);
END GENERATE loop55;
altpriority_encoder16 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --fp_sub_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_r08 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fp_sub_altpriority_encoder_r08;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_r08 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero901w902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero901w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero903w904w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero901w & wire_altpriority_encoder10_w_lg_w_lg_zero903w904w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i) <= wire_altpriority_encoder10_w_lg_zero901w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero903w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero901w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero903w904w(i) <= wire_altpriority_encoder10_w_lg_zero903w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i);
END GENERATE loop58;
altpriority_encoder10 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : fp_sub_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --fp_sub_altpriority_encoder_r08
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_rf8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_rf8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_rf8 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero957w958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero957w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero959w960w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero957w & wire_altpriority_encoder20_w_lg_w_lg_zero959w960w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i) <= wire_altpriority_encoder20_w_lg_zero957w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero959w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero957w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero959w960w(i) <= wire_altpriority_encoder20_w_lg_zero959w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i);
END GENERATE loop61;
altpriority_encoder20 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --fp_sub_altpriority_encoder_rf8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_qb6 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fp_sub_altpriority_encoder_qb6;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_qb6 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero894w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero894w895w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_r08
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_rf8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder8_w_lg_zero892w & wire_altpriority_encoder8_w_lg_w_lg_zero894w895w);
altpriority_encoder7 : fp_sub_altpriority_encoder_r08
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero894w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero892w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero894w895w(i) <= wire_altpriority_encoder8_w_lg_zero894w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i);
END GENERATE loop64;
altpriority_encoder8 : fp_sub_altpriority_encoder_rf8
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
END RTL; --fp_sub_altpriority_encoder_qb6
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_nh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1004w1005w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1004w1005w(0) <= NOT wire_altpriority_encoder27_w_data_range1004w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1004w1005w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1004w(0) <= data(0);
END RTL; --fp_sub_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_qh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero996w997w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero996w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero998w999w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0) <= wire_altpriority_encoder27_w_lg_zero996w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero996w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0);
altpriority_encoder27 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --fp_sub_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_vh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero986w987w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero986w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero988w989w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i) <= wire_altpriority_encoder25_w_lg_zero986w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero988w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero986w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i);
END GENERATE loop67;
altpriority_encoder25 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --fp_sub_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_fj8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_fj8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_fj8 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero976w977w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero978w979w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i) <= wire_altpriority_encoder23_w_lg_zero976w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero978w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero976w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i);
END GENERATE loop70;
altpriority_encoder23 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --fp_sub_altpriority_encoder_fj8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END fp_sub_altpriority_encoder_n28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1038w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1038w1039w(0) <= NOT wire_altpriority_encoder34_w_data_range1038w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1038w1039w);
wire_altpriority_encoder34_w_data_range1038w(0) <= data(0);
END RTL; --fp_sub_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fp_sub_altpriority_encoder_q28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w);
wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0) <= wire_altpriority_encoder33_w_lg_zero1031w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1031w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0);
altpriority_encoder33 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : fp_sub_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --fp_sub_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END fp_sub_altpriority_encoder_v28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1022w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i) <= wire_altpriority_encoder31_w_lg_zero1022w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1024w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1022w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i);
END GENERATE loop73;
altpriority_encoder31 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : fp_sub_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --fp_sub_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_f48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fp_sub_altpriority_encoder_f48;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_f48 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1013w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i) <= wire_altpriority_encoder29_w_lg_zero1013w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1015w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1013w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i);
END GENERATE loop76;
altpriority_encoder29 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : fp_sub_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --fp_sub_altpriority_encoder_f48
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_e48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fp_sub_altpriority_encoder_e48;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_e48 IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero967w968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero967w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero969w970w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_fj8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_f48
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero969w970w);
loop77 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i) <= wire_altpriority_encoder21_w_lg_zero967w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop77;
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero969w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop78;
wire_altpriority_encoder21_w_lg_zero967w(0) <= NOT wire_altpriority_encoder21_zero;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero969w970w(i) <= wire_altpriority_encoder21_w_lg_zero969w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i);
END GENERATE loop79;
altpriority_encoder21 : fp_sub_altpriority_encoder_fj8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : fp_sub_altpriority_encoder_f48
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
END RTL; --fp_sub_altpriority_encoder_e48
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 282
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altfp_add_sub_24k IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sub_altfp_add_sub_24k;
ARCHITECTURE RTL OF fp_sub_altfp_add_sub_24k IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w278w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w276w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w292w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_aligned_datab_sign_dffe15_wo336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range272w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range290w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT fp_sub_altbarrel_shift_h0e
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altbarrel_shift_6hb
PORT
(
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_qb6
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_e48
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop80 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop80;
loop81 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w278w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w276w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND wire_w_exp_amb_w_range274w(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop89;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop90 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop90;
loop91 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop93;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop94 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop94;
loop95 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop95;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo338w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop96 : FOR i IN 0 TO 4 GENERATE
wire_w292w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) AND wire_w_exp_diff_abs_w_range290w(i);
END GENERATE loop96;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop97 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop97;
loop98 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w279w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w273w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range272w(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop111;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= input_datab_infinite_dffe15_wo AND wire_w_lg_aligned_datab_sign_dffe15_wo336w(0);
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop112 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w(i) <= wire_w_exp_diff_abs_exceed_max_w_range289w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop112;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop113 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop113;
loop114 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop116;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_aligned_datab_sign_dffe15_wo336w(0) <= NOT aligned_datab_sign_dffe15_wo;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w275w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo338w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range289w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop117 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop117;
loop118 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop120;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w(0) <= wire_w_exp_diff_abs_exceed_max_w_range282w(0) OR wire_w_exp_diff_abs_w_range284w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w(0) <= wire_w_exp_diff_abs_exceed_max_w_range286w(0) OR wire_w_exp_diff_abs_w_range287w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25_wi;
add_sub_w2 <= (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo);
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12_wi;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13_wi;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14_wi;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12_wi;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13_wi;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14_wi;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12_wi;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13_wi;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14_wi;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12_wi;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13_wi;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14_wi;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12_wi;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13_wi;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14_wi;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12_wi;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13_wi;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14_wi;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25_wi;
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25_wi;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41_wi;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23_wi;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13_wi;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14_wi;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w275w276w OR wire_w_lg_exp_amb_mux_w273w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41_wi;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23_wi;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25_wi;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27_wi;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w(0) OR wire_w_lg_input_datab_infinite_dffe15_wo337w(0));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23_wi;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25_wi;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27_wi;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41_wi;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41_wi;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23_wi;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27_wi;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41_wi;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12_wi;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13_wi;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14_wi;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12_wi;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12_wi;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13_wi;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14_wi;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12_wi;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23_wi;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25_wi;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27_wi;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41_wi;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13_wi;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14_wi;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23_wi;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25_wi;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27_wi;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41_wi;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23_wi;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27_wi;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23_wi;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27_wi;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41_wi;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23_wi;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13_wi;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w279w OR wire_w_lg_w_lg_exp_amb_mux_w275w278w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23_wi;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13_wi;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14_wi;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w OR wire_w292w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41_wi;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23_wi;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25_wi;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27_wi;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23_wi;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27_wi;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range274w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range272w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range282w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range286w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range289w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range290w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range284w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range287w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : fp_sub_altbarrel_shift_h0e
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : fp_sub_altbarrel_shift_6hb
PORT MAP (
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : fp_sub_altpriority_encoder_qb6
PORT MAP (
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : fp_sub_altpriority_encoder_e48
PORT MAP (
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop121 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop121;
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop122;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop123;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop124;
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop125;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop126;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop127 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop127;
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop128;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop129;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --fp_sub_altfp_add_sub_24k
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sub;
ARCHITECTURE RTL OF fp_sub IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_sub_altfp_add_sub_24k
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
fp_sub_altfp_add_sub_24k_component : fp_sub_altfp_add_sub_24k
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "SUB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "7"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_constants.vhd
|
1
|
546
|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_constants
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
package ccsds_rxtx_constants is
constant RXTX_CST: integer := 1; -- DUMMY USELESS CONSTANT
end ccsds_rxtx_constants;
|
mit
|
plorefice/freon
|
tests/hdl/core/alu_tb.vhdl
|
1
|
11405
|
-- Design:
-- Testbench for the Arithmetic Logic Unit of the Freon core.
-- Tests taken from: https://github.com/riscv/riscv-tests
--
-- Authors:
-- Pietro Lorefice <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu_tb is
end entity; -- alu_tb
architecture tb of alu_tb is
constant T : time := 1 ns; -- arbitrary test time
signal opsel : std_logic_vector(2 downto 0) := (others => '0');
signal ctrl : std_logic := '0';
signal op1, op2, res : std_logic_vector(31 downto 0) := (others => '0');
begin
-- unit under test
uut : entity work.alu
generic map (XLEN => 32)
port map (
opsel => opsel,
ctrl => ctrl,
op1 => op1,
op2 => op2,
res => res
);
-- testbench process
tb_proc : process
begin
--##############################################################
-- [ADD]
--##############################################################
opsel <= "000"; ctrl <= '0';
op1 <= X"00000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[ADD] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"00000001"; wait for T;
assert res = X"00000002" report "[ADD] Wrong result" severity failure;
op1 <= X"00000003"; op2 <= X"00000007"; wait for T;
assert res = X"0000000A" report "[ADD] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"ffff8000" report "[ADD] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00000000"; wait for T;
assert res = X"80000000" report "[ADD] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"7fff8000" report "[ADD] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00007fff" report "[ADD] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00000000"; wait for T;
assert res = X"7fffffff" report "[ADD] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00007fff"; wait for T;
assert res = X"80007ffe" report "[ADD] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00007fff"; wait for T;
assert res = X"80007fff" report "[ADD] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"ffff8000"; wait for T;
assert res = X"7fff7fff" report "[ADD] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffffffff"; wait for T;
assert res = X"ffffffff" report "[ADD] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[ADD] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"ffffffff"; wait for T;
assert res = X"fffffffe" report "[ADD] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"7fffffff"; wait for T;
assert res = X"80000000" report "[ADD] Wrong result" severity failure;
--##############################################################
-- [SUB]
--##############################################################
opsel <= "000"; ctrl <= '1';
op1 <= X"00000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SUB] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[SUB] Wrong result" severity failure;
op1 <= X"00000003"; op2 <= X"00000007"; wait for T;
assert res = X"fffffffc" report "[SUB] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00008000" report "[SUB] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00000000"; wait for T;
assert res = X"80000000" report "[SUB] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"80008000" report "[SUB] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"00007fff"; wait for T;
assert res = X"ffff8001" report "[SUB] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00000000"; wait for T;
assert res = X"7fffffff" report "[SUB] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00007fff"; wait for T;
assert res = X"7fff8000" report "[SUB] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00007fff"; wait for T;
assert res = X"7fff8001" report "[SUB] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"ffff8000"; wait for T;
assert res = X"80007fff" report "[SUB] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000001" report "[SUB] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"00000001"; wait for T;
assert res = X"fffffffe" report "[SUB] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000000" report "[SUB] Wrong result" severity failure;
--##############################################################
-- [SLT]
--##############################################################
opsel <= "010"; ctrl <= '0';
op1 <= X"00000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"00000003"; op2 <= X"00000007"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"00000007"; op2 <= X"00000003"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00007fff"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"00000001"; wait for T;
assert res = X"00000001" report "[SLT] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000000" report "[SLT] Wrong result" severity failure;
--##############################################################
-- [SLTU]
--##############################################################
opsel <= "011"; ctrl <= '0';
op1 <= X"00000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000001"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000003"; op2 <= X"00000007"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000007"; op2 <= X"00000003"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00000000"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"00007fff"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"80000000"; op2 <= X"00007fff"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"7fffffff"; op2 <= X"ffff8000"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"00000000"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000001" report "[SLTU] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"00000001"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
op1 <= X"ffffffff"; op2 <= X"ffffffff"; wait for T;
assert res = X"00000000" report "[SLTU] Wrong result" severity failure;
--##############################################################
-- [AND]
--##############################################################
opsel <= "111"; ctrl <= '0';
op1 <= X"ff00ff00"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"0f000f00" report "[AND] Wrong result" severity failure;
op1 <= X"0ff00ff0"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"00f000f0" report "[AND] Wrong result" severity failure;
op1 <= X"00ff00ff"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"000f000f" report "[AND] Wrong result" severity failure;
op1 <= X"f00ff00f"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"f000f000" report "[AND] Wrong result" severity failure;
--##############################################################
-- [OR]
--##############################################################
opsel <= "110"; ctrl <= '0';
op1 <= X"ff00ff00"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"ff0fff0f" report "[OR] Wrong result" severity failure;
op1 <= X"0ff00ff0"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"fff0fff0" report "[OR] Wrong result" severity failure;
op1 <= X"00ff00ff"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"0fff0fff" report "[OR] Wrong result" severity failure;
op1 <= X"f00ff00f"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"f0fff0ff" report "[OR] Wrong result" severity failure;
--##############################################################
-- [XOR]
--##############################################################
opsel <= "100"; ctrl <= '0';
op1 <= X"ff00ff00"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"f00ff00f" report "[XOR] Wrong result" severity failure;
op1 <= X"0ff00ff0"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"ff00ff00" report "[XOR] Wrong result" severity failure;
op1 <= X"00ff00ff"; op2 <= X"0f0f0f0f"; wait for T;
assert res = X"0ff00ff0" report "[XOR] Wrong result" severity failure;
op1 <= X"f00ff00f"; op2 <= X"f0f0f0f0"; wait for T;
assert res = X"00ff00ff" report "[XOR] Wrong result" severity failure;
wait; -- Terminate testbench
end process; -- tb_proc
end architecture; -- tb
|
mit
|
dgfiloso/VHDL_DSED_P3
|
PIC/CPU.vhd
|
1
|
7507
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.PIC_pkg.ALL;
entity CPU is
port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
ROM_Data : in STD_LOGIC_VECTOR (11 downto 0);
ROM_Addr : out STD_LOGIC_VECTOR (11 downto 0);
RAM_Addr : out STD_LOGIC_VECTOR (7 downto 0);
RAM_Write : out STD_LOGIC;
RAM_OE : out STD_LOGIC;
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
DMA_RQ : in STD_LOGIC;
DMA_ACK : out STD_LOGIC;
SEND_comm : out STD_LOGIC;
DMA_READY : in STD_LOGIC;
Alu_op : out alu_op;
Index_Reg : in STD_LOGIC_VECTOR (7 downto 0);
FlagZ : in STD_LOGIC);
-- FlagC : in STD_LOGIC;
-- FlagN : in STD_LOGIC;
-- FlagE : in STD_LOGIC);
end CPU;
architecture Behavioral of CPU is
type State is (Idle, Fetch, Op_Fetch, Decode, Execute, Receive, Transmit);
signal current_state, next_state: State;
signal PC_reg, INS_reg, TMP_reg: std_logic_vector(7 downto 0);
signal PC_reg_tmp, INS_reg_tmp, TMP_reg_tmp: std_logic_vector(7 downto 0);
begin
ROM_Addr <= "0000" & PC_reg;
process(current_state, FlagZ, Index_Reg, DMA_RQ, DMA_READY, ROM_Data, PC_reg, INS_reg, TMP_reg)
begin
-- Valores por defecto
Databus <= "ZZZZZZZZ";
RAM_Addr <= "ZZZZZZZZ";
RAM_Write <= 'Z';
RAM_OE <= 'Z';
DMA_Ack <= '0';
Send_comm <= '0';
ALU_op <= nop;
next_state <= current_state;
INS_reg_tmp <= INS_reg;
PC_reg_tmp <= PC_reg;
TMP_reg_tmp <= TMP_reg;
case current_state is
when Idle =>
if DMA_RQ='1' then
next_state <= Receive;
else
next_state <= Fetch;
end if;
when Receive =>
DMA_ACK<='1';
if DMA_RQ='0' then
next_state <= Fetch;
end if;
when Fetch =>
INS_reg_tmp <= ROM_Data(7 downto 0);
PC_reg_tmp <= PC_reg+1;
next_state <= Decode;
when Decode =>
case INS_reg(7 downto 6) is
when TYPE_1 =>
next_state <= Execute;
when TYPE_2 =>
next_state <= Op_Fetch;
when TYPE_3 =>
if INS_reg(5 downto 3)=(LD & SRC_ACC) then
next_state <= Execute;
else
next_state <= Op_Fetch;
end if;
when TYPE_4 =>
next_state <= Transmit;
when others =>
end case;
when Op_Fetch =>
TMP_reg_tmp <= ROM_Data(7 downto 0);
PC_reg_tmp <= PC_reg+1;
next_state <= Execute;
when Execute =>
case INS_reg(7 downto 6) is
when TYPE_1 =>
case INS_reg(5 downto 0) is
when ALU_ADD =>
Alu_op <= op_add;
when ALU_SUB =>
Alu_op <= op_sub;
when ALU_SHIFTL =>
Alu_op <= op_shiftl;
when ALU_SHIFTR =>
Alu_op <= op_shiftr;
when ALU_AND =>
Alu_op <= op_and;
when ALU_OR =>
Alu_op <= op_or;
when ALU_XOR =>
Alu_op <= op_xor;
when ALU_CMPE =>
Alu_op <= op_cmpe;
when ALU_CMPL =>
Alu_op <= op_cmpl;
when ALU_CMPG =>
Alu_op <= op_cmpg;
when ALU_ASCII2BIN =>
Alu_op <= op_ascii2bin;
when ALU_BIN2ASCII =>
Alu_op <= op_bin2ascii;
when others =>
end case;
next_state <= Idle;
when TYPE_2 =>
case INS_reg(5 downto 0) is
when JMP_UNCOND =>
PC_reg_tmp <= TMP_reg;
when JMP_COND =>
if FlagZ='1' then
PC_reg_tmp <= TMP_reg;
end if;
when others =>
end case;
next_state <= Idle;
when TYPE_3 =>
if INS_reg(5)='0' then -- Registros o lectura de memoria
case INS_reg(4 downto 0) is
-- Transferencias entre registros
when SRC_ACC & DST_A =>
Alu_op <= op_mvacc2a;
next_state <= Idle;
when SRC_ACC & DST_B =>
Alu_op <= op_mvacc2b;
next_state <= Idle;
when SRC_ACC & DST_INDX =>
Alu_op <= op_mvacc2id;
next_state <= Idle;
-- Carga de registros con constantes
when SRC_CONSTANT & DST_A =>
Alu_op <= op_lda;
Databus <= TMP_reg(7 downto 0);
next_state <= Idle;
when SRC_CONSTANT & DST_B =>
Alu_op <= op_ldb;
Databus <= TMP_reg(7 downto 0);
next_state <= Idle;
when SRC_CONSTANT & DST_INDX =>
Alu_op <= op_ldid;
Databus <= TMP_reg(7 downto 0);
next_state <= Idle;
when SRC_CONSTANT & DST_ACC =>
Alu_op <= op_ldacc;
Databus <= TMP_reg(7 downto 0);
next_state <= Idle;
-- Carga de registros desde memoria
when SRC_MEM & DST_A =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0);
Alu_op <= op_lda;
next_state <= Idle;
when SRC_MEM & DST_B =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0);
Alu_op <= op_ldb;
next_state <= Idle;
when SRC_MEM & DST_ACC =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0);
Alu_op <= op_ldacc;
next_state <= Idle;
when SRC_MEM & DST_INDX =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0);
Alu_op <= op_ldid;
next_state <= Idle;
-- Carga de registros desde memoria indexada
when SRC_INDXD_MEM & DST_A =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
Alu_op <= op_lda;
next_state <= Idle;
when SRC_INDXD_MEM & DST_B =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
Alu_op <= op_ldb;
next_state <= Idle;
when SRC_INDXD_MEM & DST_ACC =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
Alu_op <= op_ldacc;
next_state <= Idle;
when SRC_INDXD_MEM & DST_INDX =>
RAM_OE <= '0';
RAM_Write <= '0';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
Alu_op <= op_ldid;
next_state <= Idle;
when others =>
end case;
else -- Escritura en memoria
Alu_op <= op_oeacc;
case INS_reg(4 downto 0) is
when SRC_ACC & DST_MEM =>
RAM_Write <= '1';
RAM_OE <= '1';
RAM_Addr <= TMP_reg(7 downto 0);
next_state <= Idle;
when SRC_ACC & DST_INDXD_MEM =>
RAM_Write <= '1';
RAM_OE <= '1';
RAM_Addr <= TMP_reg(7 downto 0)+Index_Reg;
next_state <= Idle;
when others =>
end case;
end if;
when TYPE_4 =>
when others =>
end case;
when Transmit =>
SEND_comm <= '1';
if DMA_READY='1' then
next_state <= Idle;
end if;
end case;
end process;
PROCESS (reset, clk)
BEGIN
if reset='0' then
current_state <= Idle;
PC_reg <= (others=>'0');
elsif clk'event and clk='1' then
current_state <= next_state;
PC_reg <= PC_reg_tmp;
INS_reg <= INS_reg_tmp;
TMP_reg <= TMP_reg_tmp;
end if;
END PROCESS;
end Behavioral;
|
mit
|
dgfiloso/VHDL_DSED_P3
|
PIC/tb_ALU.vhd
|
1
|
3139
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:50 11/28/2016
-- Design Name:
-- Module Name: C:/Users/Danns/Desktop/Practica 3/PIC/tb_ALU.vhd
-- Project Name: PIC
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
use work.PIC_pkg.ALL;
ENTITY tb_ALU IS
END tb_ALU;
ARCHITECTURE behavior OF tb_ALU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Reset : IN std_logic;
Clk : IN std_logic;
u_instruction : in alu_op;
FlagZ : OUT std_logic;
Index_Reg : OUT std_logic_vector(7 downto 0);
Databus : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Reset : std_logic := '0';
signal Clk : std_logic := '0';
signal u_instruction : alu_op := nop;
--BiDirs
signal Databus : std_logic_vector(7 downto 0) := (others => 'Z');
--Outputs
signal FlagZ : std_logic;
signal Index_Reg : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
Reset => Reset,
Clk => Clk,
u_instruction => u_instruction,
FlagZ => FlagZ,
Index_Reg => Index_Reg,
Databus => Databus
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Reset <= '0', '1' after 50 ns;
u_instruction <= op_lda, op_ldb after 100 ns, op_add after 150 ns, op_mvacc2a after 200 ns, op_sub after 250 ns, op_mvacc2id after 300 ns, op_cmpg after 350 ns,
op_lda after 400 ns, op_ascii2bin after 450 ns, op_lda after 500 ns, op_ascii2bin after 550 ns, op_lda after 600 ns, op_ascii2bin after 650 ns, op_oeacc after 700 ns;
Databus <= X"04" after 50 ns, X"01" after 100 ns, (others => 'Z') after 150 ns, X"35" after 400 ns, (others => 'Z') after 450 ns, X"20" after 500 ns, (others => 'Z') after 550 ns, X"87" after 600 ns, (others => 'Z') after 650 ns;
wait;
end process;
END;
|
mit
|
euryecetelecom/euryspace
|
hw/rtl/ccsds_rxtx/ccsds_rxtx_top.vhd
|
1
|
14279
|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_top
---- Version: 1.0.0
---- Description: CCSDS compliant RX/TX for space communications
---- TX Modulations: BPSK, QPSK, Offset-QPSK, QAM, Offset-QAM
---- RX Performances: QAM: min Eb/N0 = XdB, max frequency shift = X Hz (Doppler + speed), max frequency shift rate = X Hz / secs (Doppler + acceleration), synchronisation, agc / dynamic range, filters capabilities, multipaths, ...
---- This is the entry point / top level entity
---- WB slave interface, RX/TX external inputs/outputs
---- Synchronized with rising edge of clocks
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/26: initial release - only basic RX-TX capabilities through direct R/W on WB Bus / no dynamic configuration capabilities
---- 2016/10/18: major rework / implementation of new architecture
-------------------------------
-- TODO: additionnal modulations: ASK, FSK, GMSK, OFDM, CDMA
-- TODO: dynamic modulation and coding
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ccsds_rxtx_parameters.all;
use work.ccsds_rxtx_functions.all;
--use work.ccsds_rxtx_constants.all;
--=============================================================================
-- Entity declaration for ccsds_rxtx_top / overall rx-tx external physical inputs and outputs
--=============================================================================
entity ccsds_rxtx_top is
generic (
CCSDS_RXTX_RX_AUTO_ENABLED: boolean := RX_SYSTEM_AUTO_ENABLED;
CCSDS_RXTX_RX_PHYS_SIG_QUANT_DEPTH: integer := RX_PHYS_SIG_QUANT_DEPTH;
CCSDS_RXTX_TX_AUTO_ENABLED: boolean := TX_SYSTEM_AUTO_ENABLED;
CCSDS_RXTX_TX_AUTO_EXTERNAL: boolean := TX_SYSTEM_AUTO_EXTERNAL;
CCSDS_RXTX_TX_PHYS_SIG_QUANT_DEPTH: integer := TX_PHYS_SIG_QUANT_DEPTH;
CCSDS_RXTX_WB_ADDR_BUS_SIZE: integer := RXTX_SYSTEM_WB_ADDR_BUS_SIZE;
CCSDS_RXTX_WB_DATA_BUS_SIZE: integer := RXTX_SYSTEM_WB_DATA_BUS_SIZE
);
port(
-- system wide inputs
--rst_i: in std_logic; -- implement external system reset port?
-- system wide outputs
-- wishbone slave bus connections / to the master CPU
-- wb inputs
wb_adr_i: in std_logic_vector(CCSDS_RXTX_WB_ADDR_BUS_SIZE-1 downto 0); -- address input array
wb_clk_i: in std_logic; -- clock input / wb operations are always on rising edge of clk
wb_cyc_i: in std_logic; -- cycle input / valid bus cycle in progress
wb_dat_i: in std_logic_vector(CCSDS_RXTX_WB_DATA_BUS_SIZE-1 downto 0); -- data input array
--wb_lock_i: out std_logic; -- lock input / current bus cycle is uninterruptible
wb_rst_i: in std_logic; -- reset input
--wb_sel_i: in std_logic_vector(3 downto 0); -- select input array / related to wb_dat_i + wb_dat_o / indicates where valid data is placed on the array / provide data granularity
wb_stb_i: in std_logic; -- strobe input / slave is selected
--wb_tga_i: in std_logic; -- address tag type / related to wb_adr_i / qualified by wb_stb_i / TBD
--wb_tgc_i: in std_logic; -- cycle tag type / qualified by wb_cyc_i / TBD
--wb_tgd_i: in std_logic; -- data tag type / related to wb_dat_i / ex: parity protection, ecc, timestamps
wb_we_i: in std_logic; -- write enable input / indicates if cycle is of write or read type
-- wb outputs
wb_ack_o: out std_logic; -- acknowledge output / normal bus cycle termination
wb_dat_o: out std_logic_vector(CCSDS_RXTX_WB_DATA_BUS_SIZE-1 downto 0); -- data output array
wb_err_o: out std_logic; -- error output / abnormal bus cycle termination
wb_rty_o: out std_logic; -- retry output / not ready - retry bus cycle
--wb_tgd_o: out std_logic; -- data tag type / related to wb_dat_o / ex: parity protection, ecc, timestamps
-- RX connections
-- rx inputs
rx_clk_i: in std_logic; -- received samples clock
rx_sam_i_i: in std_logic_vector(CCSDS_RXTX_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- i samples
rx_sam_q_i: in std_logic_vector(CCSDS_RXTX_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- q samples
-- rx outputs
rx_ena_o: out std_logic; -- rx enabled status indicator
rx_irq_o: out std_logic; -- interrupt request output / data received indicator
-- TX connections
-- tx inputs
tx_clk_i: in std_logic; -- output samples clock
tx_dat_ser_i: in std_logic; -- direct data serial input
-- tx outputs
tx_buf_ful_o: out std_logic; -- buffer full / data overflow indicator
tx_clk_o: out std_logic; -- emitted samples clock
tx_ena_o: out std_logic; -- tx enabled status indicator
tx_idl_o: out std_logic; -- idle status / data-padding indicator
tx_sam_i_o: out std_logic_vector(CCSDS_RXTX_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- i samples
tx_sam_q_o: out std_logic_vector(CCSDS_RXTX_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0) -- q samples
);
end ccsds_rxtx_top;
--=============================================================================
-- architecture declaration / internal connections
--=============================================================================
architecture structure of ccsds_rxtx_top is
-- components declaration
component ccsds_rx is
generic (
CCSDS_RX_PHYS_SIG_QUANT_DEPTH : integer;
CCSDS_RX_DATA_BUS_SIZE: integer
);
port(
rst_i: in std_logic; -- system reset
ena_i: in std_logic; -- system enable
clk_i: in std_logic; -- input samples clock
sam_i_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
sam_q_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
dat_nxt_i: in std_logic; -- next data
irq_o: out std_logic; -- data ready to be read / IRQ signal
dat_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0); -- received data parallel output
dat_val_o: out std_logic; -- data valid
buf_dat_ful_o: out std_logic; -- data buffer status indicator
buf_fra_ful_o: out std_logic; -- frames buffer status indicator
buf_bit_ful_o: out std_logic; -- bits buffer status indicator
ena_o: out std_logic -- enabled status indicator
);
end component;
component ccsds_tx is
generic (
CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer;
CCSDS_TX_DATA_BUS_SIZE: integer
);
port(
rst_i: in std_logic;
ena_i: in std_logic;
clk_i: in std_logic;
in_sel_i: in std_logic;
dat_val_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
dat_ser_i: in std_logic;
buf_ful_o: out std_logic;
clk_o: out std_logic;
idl_o: out std_logic;
sam_i_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
ena_o: out std_logic
);
end component;
signal wire_rst: std_logic;
signal wire_rx_ena: std_logic := convert_boolean_to_std_logic(CCSDS_RXTX_RX_AUTO_ENABLED);
signal wire_rx_data_valid: std_logic;
signal wire_rx_data_next: std_logic := '0';
signal wire_rx_buffer_data_full: std_logic;
signal wire_rx_buffer_frames_full: std_logic;
signal wire_rx_buffer_bits_full: std_logic;
signal wire_tx_clk: std_logic;
signal wire_tx_ena: std_logic := convert_boolean_to_std_logic(CCSDS_RXTX_TX_AUTO_ENABLED);
signal wire_tx_ext: std_logic := convert_boolean_to_std_logic(CCSDS_RXTX_TX_AUTO_EXTERNAL);
signal wire_tx_data_valid: std_logic := '0';
signal wire_tx_buf_ful: std_logic;
signal wire_rx_data: std_logic_vector(CCSDS_RXTX_WB_DATA_BUS_SIZE-1 downto 0);
signal wire_tx_data: std_logic_vector(CCSDS_RXTX_WB_DATA_BUS_SIZE-1 downto 0) := (others => '0');
--=============================================================================
-- architecture begin
--=============================================================================
begin
-- components entities instantiation
rx_001: ccsds_rx
generic map(
CCSDS_RX_PHYS_SIG_QUANT_DEPTH => CCSDS_RXTX_RX_PHYS_SIG_QUANT_DEPTH,
CCSDS_RX_DATA_BUS_SIZE => CCSDS_RXTX_WB_DATA_BUS_SIZE
)
port map(
rst_i => wb_rst_i,
ena_i => wire_rx_ena,
clk_i => rx_clk_i,
sam_i_i => rx_sam_i_i,
sam_q_i => rx_sam_q_i,
dat_nxt_i => wire_rx_data_next,
irq_o => rx_irq_o,
dat_o => wire_rx_data,
dat_val_o => wire_rx_data_valid,
buf_dat_ful_o => wire_rx_buffer_data_full,
buf_fra_ful_o => wire_rx_buffer_frames_full,
buf_bit_ful_o => wire_rx_buffer_bits_full,
ena_o => rx_ena_o
);
tx_001: ccsds_tx
generic map(
CCSDS_TX_PHYS_SIG_QUANT_DEPTH => CCSDS_RXTX_TX_PHYS_SIG_QUANT_DEPTH,
CCSDS_TX_DATA_BUS_SIZE => CCSDS_RXTX_WB_DATA_BUS_SIZE
)
port map(
clk_i => tx_clk_i,
rst_i => wb_rst_i,
ena_i => wire_tx_ena,
in_sel_i => wire_tx_ext,
dat_val_i => wire_tx_data_valid,
dat_par_i => wire_tx_data,
dat_ser_i => tx_dat_ser_i,
buf_ful_o => wire_tx_buf_ful,
clk_o => tx_clk_o,
idl_o => tx_idl_o,
sam_i_o => tx_sam_i_o,
sam_q_o => tx_sam_q_o,
ena_o => tx_ena_o
);
tx_buf_ful_o <= wire_tx_buf_ful;
--=============================================================================
-- Begin of wbstartp
-- In charge of wishbone bus interactions + rx/tx management through it
--=============================================================================
-- read: wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_dat_i
-- write: wb_ack_o, wb_err_o, wb_rty_o, (rx_/tx_XXX:rst_i), wb_dat_o, wire_rst, wire_irq, wire_rx_ena, wire_tx_ena
-- r/w: wire_tx_ext
WBSTARTP : process (wb_clk_i)
variable ack_state: std_logic := '0';
-- variables instantiation
begin
-- on each wb clock rising edge
if rising_edge(wb_clk_i) then
-- wb reset signal received
if (wb_rst_i = '1') then
-- reinitialize all dyn elements to default value
ack_state := '0';
wire_rx_ena <= convert_boolean_to_std_logic(CCSDS_RXTX_RX_AUTO_ENABLED);
wire_tx_ena <= convert_boolean_to_std_logic(CCSDS_RXTX_TX_AUTO_ENABLED);
-- reinitialize all outputs
wire_tx_ext <= convert_boolean_to_std_logic(CCSDS_RXTX_TX_AUTO_EXTERNAL);
if (CCSDS_RXTX_TX_AUTO_EXTERNAL = false) then
wire_tx_data_valid <= '0';
else
wire_tx_data_valid <= '1';
end if;
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
else
if (wb_cyc_i = '1') and (wb_stb_i = '1') then
-- single classic standard read cycle
if (wb_we_i = '0') then
if (wb_adr_i = "0000") then
-- classic rx cycle - forward data from rx to master
if (ack_state = '0') then
wb_dat_o <= wire_rx_data;
wb_ack_o <= '0';
ack_state := '1';
else
wb_dat_o <= (others => '0');
wb_ack_o <= '1';
ack_state := '0';
end if;
else
wb_err_o <= '1';
wb_rty_o <= '1';
end if;
-- single write cycle
else
wb_dat_o <= (others => '0');
-- classic tx cycle - store and forward data from master to tx
if (wb_adr_i = "0000") then
-- check internal configuration
if (wire_tx_ext = '0') then
if (wire_tx_buf_ful = '0') and (ack_state = '0') then
wb_ack_o <= '1';
ack_state := '1';
wire_tx_data <= wb_dat_i;
wire_tx_data_valid <= '1';
else
if (ack_state = '1') then
wire_tx_data_valid <= '0';
wb_ack_o <= '0';
ack_state := '0';
else
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '1';
end if;
end if;
else
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '1';
end if;
-- RX configuration cycle - set general rx parameters
elsif (wb_adr_i = "0001") then
if (ack_state = '0') then
wire_rx_ena <= wb_dat_i(0);
wb_ack_o <= '1';
ack_state := '1';
else
wb_ack_o <= '0';
ack_state := '0';
end if;
-- TX configuration cycle - set general tx parameters
elsif (wb_adr_i = "0010") then
if (ack_state = '0') then
wire_tx_ena <= wb_dat_i(0);
wire_tx_ext <= wb_dat_i(1);
wb_ack_o <= '1';
ack_state := '1';
else
wb_ack_o <= '0';
ack_state := '0';
end if;
else
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '1';
end if;
end if;
else
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
ack_state := '0';
if (wire_tx_ext = '0') then
wire_tx_data_valid <= '0';
else
wire_tx_data_valid <= '1';
end if;
end if;
end if;
end if;
end process;
end structure;
--=============================================================================
-- architecture end
--=============================================================================
|
mit
|
jayvalentine/vhdl-risc-processor
|
adder_32_bit.vhd
|
1
|
4153
|
-- 32-bit adder circuit
-- this circuit adds two 32-bit unsigned numbers together, and supports previous-carry addition and subtraction
-- all code (c) 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity adder_32_bit is
port (
-- inputs
a_32 : in std_logic_vector(31 downto 0);
b_32 : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(1 downto 0);
enable : in std_logic;
-- outputs
sum_32 : out std_logic_vector(31 downto 0);
carry : out std_logic;
overflow : out std_logic
);
end entity adder_32_bit;
architecture adder_32_bit_arch of adder_32_bit is
-- signed values
signal a_signed : signed(31 downto 0);
signal b_signed : signed(31 downto 0);
signal sum_signed : signed(31 downto 0);
-- unsigned values
signal a_unsigned : unsigned(32 downto 0);
signal b_unsigned : unsigned(32 downto 0);
signal sum_unsigned : unsigned(32 downto 0);
begin
-- design implementation
add : process(enable, opcode, a_32, b_32, a_signed, b_signed, sum_signed, a_unsigned, b_unsigned, sum_unsigned)
begin
if enable = '1' then
-- converting inputs to signed vectors
a_signed <= signed(a_32);
b_signed <= signed(b_32);
-- converting inputs to unsigned vectors
a_unsigned <= '0' & unsigned(a_32);
b_unsigned <= '0' & unsigned(b_32);
-- performing addition/subtraction
-- opcode 00 is add signed
if opcode = "00" then
-- calculating signed sum
sum_signed <= a_signed + b_signed;
-- set unsigned sum to 0
sum_unsigned <= (others => '0');
-- if sign bit of sum is not the same as the sign bits of the two operands, set overflow flag
if a_signed(31) = '1' and b_signed(31) = '1' and sum_signed(31) = '0' then
overflow <= '1';
elsif a_signed(31) = '0' and b_signed(31) = '0' and sum_signed(31) = '1' then
overflow <= '1';
else
overflow <= '0';
end if;
-- carry out set to 0
carry <= '0';
-- opcode 01 is add unsigned
elsif opcode = "01" then
-- set signed sum to 0
sum_signed <= (others => '0');
-- calculating unsigned sum
sum_unsigned <= a_unsigned + b_unsigned;
-- msb of sum is carry out
carry <= sum_unsigned(32);
-- overflow flag set to 0
overflow <= '0';
-- opcode 10 is subtract signed
elsif opcode = "10" then
-- calculate signed sum
sum_signed <= a_signed - b_signed;
-- set unsigned sum to 0
sum_unsigned <= (others => '0');
-- if sign bit of sum is not the same as the sign bits of the two operands, set overflow flag
if a_signed(31) = '0' and b_signed(31) = '1' and sum_signed(31) = '1' then
overflow <= '1';
elsif a_signed(31) = '1' and b_signed(31) = '0' and sum_signed(31) = '0' then
overflow <= '1';
else
overflow <= '0';
end if;
-- carry out set to 0
carry <= '0';
-- opcode 11 is subtract unsigned
elsif opcode = "11" then
-- set signed sum to 0
sum_signed <= (others => '0');
-- calculate unsigned sum
sum_unsigned <= a_unsigned - b_unsigned;
-- if b > a set carry to 1
if b_unsigned > a_unsigned then
carry <= '1';
else
carry <= '0';
end if;
-- overflow set to 0
overflow <= '0';
-- otherwise error case, output 0
else
sum_signed <= (others => '0');
sum_unsigned <= (others => '0');
overflow <= '0';
carry <= '0';
end if;
if opcode(0) = '0' then
sum_32 <= std_logic_vector(sum_signed);
elsif opcode(0) = '1' then
sum_32 <= std_logic_vector(sum_unsigned(31 downto 0));
else
sum_32 <= (others => '0');
end if;
-- adder disabled, all outputs and signals 0
else
-- resetting internal signals
a_signed <= (others => '0');
b_signed <= (others => '0');
sum_signed <= (others => '0');
a_unsigned <= (others => '0');
b_unsigned <= (others => '0');
sum_unsigned <= (others => '0');
-- resetting outputs
carry <= '0';
overflow <= '0';
sum_32 <= (others => '0');
end if;
end process add;
end architecture adder_32_bit_arch;
|
mit
|
EPiCS/soundgates
|
hardware/basic/sawtooth/sawtooth.vhd
|
1
|
2047
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - sawtooth.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Sawtooth wave generator
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity sawtooth is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
end sawtooth;
architecture Behavioral of sawtooth is
signal x : signed (31 downto 0) := to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant upper : signed (31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant lower : signed (31 downto 0) := to_signed(integer(real(-1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
begin
saw <= x;
CALC_SAW : process (clk, rst)
begin
if rst = '1' then
x <= offset;
else
if rising_edge(clk) then
if ce = '1' then
x <= x + incr;
if x > upper then
x <= lower;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
IslamKhaledH/ArchitecturePorject
|
Project/AddSubIncDec.vhd
|
1
|
957
|
Library ieee;
Use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
ENTITY AddSubIncDec IS
port(
R1,R2: in std_logic_vector(15 downto 0);
OutPut : out std_logic_vector(15 downto 0);
OpCode :in std_logic_vector(4 downto 0);
--Z: out std_logic;
--V: out std_logic;
C: out std_logic
--N: out std_logic
);
END AddSubIncDec;
Architecture archi of AddSubIncDec is
Component my_nadder is
PORT (a, b : in std_logic_vector(15 downto 0) ;
s : out std_logic_vector(15 downto 0);
cout : out std_logic);
end component;
signal tmpR1 : std_logic_vector(15 downto 0);
signal tmpR2 : std_logic_vector(15 downto 0);
signal TempOut : std_logic_vector(15 downto 0);
begin
tmpR1 <= R1 ;
tmpR2 <= R2 when OpCode = "00010" else
-R2 when OpCode = "00011" else
"0000000000000001" when OpCode = "10010" else
(others => '1') when OpCode = "10011";
F : my_nadder port map(tmpR1,tmpR2,TempOut,C);
OutPut <= TempOut;
end archi;
|
mit
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_spdif.vhd
|
1
|
13599
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver. Top level entity for the receiver core. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2004/07/19 16:58:37 gedra
-- Fixed bug.
--
-- Revision 1.4 2004/07/12 17:06:41 gedra
-- Fixed bug with lock event generation.
--
-- Revision 1.3 2004/07/11 16:19:50 gedra
-- Bug-fix.
--
-- Revision 1.2 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.1 2004/06/26 14:13:56 gedra
-- Top level entity for receiver.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use work.rx_package.all;
entity rx_spdif is
generic (DATA_WIDTH: integer range 16 to 32;
ADDR_WIDTH: integer range 8 to 64;
CH_ST_CAPTURE: integer range 0 to 8;
WISHBONE_FREQ: natural);
port (
-- Wishbone interface
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_sel_i: in std_logic;
wb_stb_i: in std_logic;
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_bte_i: in std_logic_vector(1 downto 0);
wb_cti_i: in std_logic_vector(2 downto 0);
wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
wb_dat_i: in std_logic_vector(DATA_WIDTH -1 downto 0);
wb_ack_o: out std_logic;
wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- Interrupt line
rx_int_o: out std_logic;
-- SPDIF input signal
spdif_rx_i: in std_logic);
end rx_spdif;
architecture rtl of rx_spdif is
signal data_out, ver_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal ver_rd : std_logic;
signal conf_rxen, conf_sample, evt_en, conf_chas, conf_valid : std_logic;
signal conf_blken, conf_valen, conf_useren, conf_staten : std_logic;
signal conf_paren, config_rd, config_wr : std_logic;
signal conf_mode : std_logic_vector(3 downto 0);
signal conf_bits, conf_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal status_rd : std_logic;
signal stat_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal imask_bits, imask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal imask_rd, imask_wr : std_logic;
signal istat_dout, istat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal istat_rd, istat_wr, istat_lock : std_logic;
signal istat_lsbf, istat_hsbf, istat_paritya, istat_parityb: std_logic;
signal istat_cap : std_logic_vector(7 downto 0);
signal ch_st_cap_rd, ch_st_cap_wr, ch_st_data_rd: std_logic_vector(7 downto 0);
signal cap_dout : bus_array;
signal ch_data, ud_a_en, ud_b_en, cs_a_en, cs_b_en: std_logic;
signal mem_rd, sample_wr : std_logic;
signal sample_din, sample_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal sbuf_wr_adr, sbuf_rd_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
signal lock, rx_frame_start: std_logic;
signal rx_data, rx_data_en, rx_block_start: std_logic;
signal rx_channel_a, rx_error, lock_evt: std_logic;
begin
-- Data bus or'ing
DB16: if DATA_WIDTH = 16 generate
data_out <= ver_dout or conf_dout or stat_dout or imask_dout or istat_dout
when wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
end generate DB16;
DB32: if DATA_WIDTH = 32 generate
data_out <= ver_dout or conf_dout or stat_dout or imask_dout or istat_dout or
cap_dout(1) or cap_dout(2) or cap_dout(3) or cap_dout(4) or
cap_dout(5) or cap_dout(6) or cap_dout(7) or cap_dout(0) when
wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
end generate DB32;
-- Wishbone bus cycle decoder
WB: rx_wb_decoder
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_cyc_i => wb_cyc_i,
wb_bte_i => wb_bte_i,
wb_cti_i => wb_cti_i,
wb_adr_i => wb_adr_i,
data_out => data_out,
wb_ack_o => wb_ack_o,
wb_dat_o => wb_dat_o,
version_rd => ver_rd,
config_rd => config_rd,
config_wr => config_wr,
status_rd => status_rd,
intmask_rd => imask_rd,
intmask_wr => imask_wr,
intstat_rd => istat_rd,
intstat_wr => istat_wr,
mem_rd => mem_rd,
mem_addr => sbuf_rd_adr,
ch_st_cap_rd => ch_st_cap_rd,
ch_st_cap_wr => ch_st_cap_wr,
ch_st_data_rd => ch_st_data_rd);
-- Version register
VER : rx_ver_reg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
CH_ST_CAPTURE => CH_ST_CAPTURE)
port map (
ver_rd => ver_rd,
ver_dout => ver_dout);
-- Configuration register
CG32: if DATA_WIDTH = 32 generate
CONF: gen_control_reg
generic map (
DATA_WIDTH => 32,
ACTIVE_BIT_MASK => "11111100000000001111111100000000")
port map (
clk => wb_clk_i,
rst => wb_rst_i,
ctrl_wr => config_wr,
ctrl_rd => config_rd,
ctrl_din => wb_dat_i,
ctrl_dout => conf_dout,
ctrl_bits => conf_bits);
conf_mode(3 downto 0) <= conf_bits(23 downto 20);
conf_paren <= conf_bits(19);
conf_staten <= conf_bits(18);
conf_useren <= conf_bits(17);
conf_valen <= conf_bits(16);
end generate CG32;
CG16: if DATA_WIDTH = 16 generate
CONF: gen_control_reg
generic map (
DATA_WIDTH => 16,
ACTIVE_BIT_MASK => "1111110000000000")
port map (
clk => wb_clk_i,
rst => wb_rst_i,
ctrl_wr => config_wr,
ctrl_rd => config_rd,
ctrl_din => wb_dat_i,
ctrl_dout => conf_dout,
ctrl_bits => conf_bits);
conf_mode(3 downto 0) <= "0000";
conf_paren <= '0';
conf_staten <= '0';
conf_useren <= '0';
conf_valen <= '0';
end generate CG16;
conf_blken <= conf_bits(5);
conf_valid <= conf_bits(4);
conf_chas <= conf_bits(3);
evt_en <= conf_bits(2);
conf_sample <= conf_bits(1);
conf_rxen <= conf_bits(0);
-- status register
STAT : rx_status_reg
generic map (
DATA_WIDTH => DATA_WIDTH)
port map (
wb_clk_i => wb_clk_i,
status_rd => status_rd,
lock => lock,
chas => conf_chas,
rx_block_start => rx_block_start,
ch_data => rx_data,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en,
status_dout => stat_dout);
-- interrupt mask register
IM32: if DATA_WIDTH = 32 generate
IMASK: gen_control_reg
generic map (
DATA_WIDTH => 32,
ACTIVE_BIT_MASK => "11111000000000001111111100000000")
port map (
clk => wb_clk_i,
rst => wb_rst_i,
ctrl_wr => imask_wr,
ctrl_rd => imask_rd,
ctrl_din => wb_dat_i,
ctrl_dout => imask_dout,
ctrl_bits => imask_bits);
end generate IM32;
IM16: if DATA_WIDTH = 16 generate
IMASK: gen_control_reg
generic map (
DATA_WIDTH => 16,
ACTIVE_BIT_MASK => "1111100000000000")
port map (
clk => wb_clk_i,
rst => wb_rst_i,
ctrl_wr => imask_wr,
ctrl_rd => imask_rd,
ctrl_din => wb_dat_i,
ctrl_dout => imask_dout,
ctrl_bits => imask_bits);
end generate IM16;
-- interrupt status register
ISTAT: gen_event_reg
generic map (
DATA_WIDTH => DATA_WIDTH)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
evt_wr => istat_wr,
evt_rd => istat_rd,
evt_din => wb_dat_i,
evt_dout => istat_dout,
event => istat_events,
evt_mask => imask_bits,
evt_en => evt_en,
evt_irq => rx_int_o);
istat_events(0) <= lock_evt;
istat_events(1) <= istat_lsbf;
istat_events(2) <= istat_hsbf;
istat_events(3) <= istat_paritya;
istat_events(4) <= istat_parityb;
istat_events(15 downto 5) <= (others => '0');
IS32: if DATA_WIDTH = 32 generate
istat_events(23 downto 16) <= istat_cap(7 downto 0);
istat_events(31 downto 24) <= (others => '0');
end generate IS32;
-- capture registers
GCAP: if DATA_WIDTH = 32 and CH_ST_CAPTURE > 0 generate
CAPR: for k in 0 to CH_ST_CAPTURE - 1 generate
CHST: rx_cap_reg
port map (
clk => wb_clk_i,
rst => wb_rst_i,
cap_ctrl_wr => ch_st_cap_wr(k),
cap_ctrl_rd => ch_st_cap_rd(k),
cap_data_rd => ch_st_data_rd(k),
cap_din => wb_dat_i,
cap_dout => cap_dout(k),
cap_evt => istat_cap(k),
rx_block_start => rx_block_start,
ch_data => rx_data,
ud_a_en => ud_a_en,
ud_b_en => ud_b_en,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en);
end generate CAPR;
-- unused capture registers set to zero
UCAPR: if CH_ST_CAPTURE < 8 generate
UC: for k in CH_ST_CAPTURE to 7 generate
cap_dout(k) <= (others => '0');
end generate UC;
end generate UCAPR;
end generate GCAP;
-- Sample buffer memory
MEM: dpram
generic map (
DATA_WIDTH => DATA_WIDTH,
RAM_WIDTH => ADDR_WIDTH - 1)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => sample_din,
wr_en => sample_wr,
rd_en => mem_rd,
wr_addr => sbuf_wr_adr,
rd_addr => sbuf_rd_adr,
dout => sample_dout);
-- phase decoder
PDET: rx_phase_det
generic map (
WISHBONE_FREQ => WISHBONE_FREQ) -- WishBone frequency in MHz
port map (
wb_clk_i => wb_clk_i,
rxen => conf_rxen,
spdif => spdif_rx_i,
lock => lock,
lock_evt => lock_evt,
rx_data => rx_data,
rx_data_en => rx_data_en,
rx_block_start => rx_block_start,
rx_frame_start => rx_frame_start,
rx_channel_a => rx_channel_a,
rx_error => rx_error,
ud_a_en => ud_a_en,
ud_b_en => ud_b_en,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en);
-- frame decoder
FDEC: rx_decode
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH)
port map (
wb_clk_i => wb_clk_i,
conf_rxen => conf_rxen,
conf_sample => conf_sample,
conf_valid => conf_valid,
conf_mode => conf_mode,
conf_blken => conf_blken,
conf_valen => conf_valen,
conf_useren => conf_useren,
conf_staten => conf_staten,
conf_paren => conf_paren,
lock => lock,
rx_data => rx_data,
rx_data_en => rx_data_en,
rx_block_start => rx_block_start,
rx_frame_start => rx_frame_start,
rx_channel_a => rx_channel_a,
wr_en => sample_wr,
wr_addr => sbuf_wr_adr,
wr_data => sample_din,
stat_paritya => istat_paritya,
stat_parityb => istat_parityb,
stat_lsbf => istat_lsbf,
stat_hsbf => istat_hsbf);
end rtl;
|
mit
|
IslamKhaledH/ArchitecturePorject
|
Project/Mem_WB_Buffer.vhd
|
1
|
2264
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Mem_WB_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
pc_mux_input : in std_logic_vector(1 downto 0);
outport_en_input : in std_logic;
reg_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
LDM_immediate_input : in std_logic_vector(15 downto 0);
--------------------------------------------------------------------------------------------------------------------
pc_mux_output : out std_logic_vector(1 downto 0);
outport_en_output : out std_logic;
reg_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
write_back_mux_output: out std_logic_vector(1 downto 0);
LDM_immediate_output : out std_logic_vector(15 downto 0);
--R1_address_in3,R2_address_in3: in std_logic_vector(2 downto 0 );
--R1_address_out3,R2_address_out3: out std_logic_vector(2 downto 0 );
Rout_in2: out std_logic_vector(2 downto 0 );
Rout_out2: out std_logic_vector(2 downto 0 )
);
end Mem_WB_Buffer;
architecture arch_Mem_WB_Buffer of Mem_WB_Buffer is
component Regis is
port(
Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component nreg is
Generic ( n : integer := 16);
port(
Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0)
);
end component;
begin
pc_mux_map : nreg generic map (n=>2)port map(Clk,Rst,enable,pc_mux_input,pc_mux_output);
outport_en_map : Regis port map(Clk,Rst,enable,outport_en_input,outport_en_output);
reg_write_map : Regis port map(Clk,Rst,enable,reg_write_input,reg_write_output);
write_data_reg_mux_map : Regis port map(Clk,Rst,enable,write_data_reg_mux_input,write_data_reg_mux_output);
write_back_mux_map : nreg generic map (n=>16)port map(Clk,Rst,enable,write_back_mux_input,write_back_mux_output);
LDM_immediate_map : nreg generic map (n=>16)port map(Clk,Rst,enable,LDM_immediate_input,LDM_immediate_output);
end arch_Mem_WB_Buffer;
|
mit
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/util_i2c_mixer_v1_00_a/hdl/vhdl/util_i2c_mixer.vhd
|
2
|
1540
|
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.all;
entity util_i2c_mixer is
generic (
C_WIDTH: integer := 2
);
port (
upstream_scl_T : in std_logic;
upstream_scl_I : in std_logic;
upstream_scl_O : out std_logic;
upstream_sda_T : in std_logic;
upstream_sda_I : in std_logic;
upstream_sda_O : out std_logic;
downstream_scl_T : out std_logic;
downstream_scl_I : in std_logic_vector(C_WIDTH - 1 downto 0);
downstream_scl_O : out std_logic_vector(C_WIDTH - 1 downto 0);
downstream_sda_T : out std_logic;
downstream_sda_I : in std_logic_vector(C_WIDTH - 1 downto 0);
downstream_sda_O : out std_logic_vector(C_WIDTH - 1 downto 0)
);
end util_i2c_mixer;
architecture IMP of util_i2c_mixer is
begin
upstream_scl_O <= '1' when (downstream_scl_I = (downstream_scl_I'range => '1')) else '0';
upstream_sda_O <= '1' when (downstream_sda_I = (downstream_sda_I'range => '1')) else '0';
downstream_scl_T <= upstream_scl_T;
downstream_sda_T <= upstream_sda_T;
GEN: for i in 0 to C_WIDTH - 1 generate
downstream_scl_O(i) <= upstream_scl_I;
downstream_sda_O(i) <= upstream_sda_I;
end generate GEN;
end IMP;
|
mit
|
EPiCS/soundgates
|
hardware/hwt/pcores/hwt_pwm_v1_00_a/hdl/vhdl/hwt_pwm.vhd
|
1
|
13333
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_pwm
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating add envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_pwm is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_pwm;
architecture Behavioral of hwt_pwm is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_addrESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_pwm : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_pwm2: std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMData_pwm : std_logic_vector(0 to 31); -- add to local ram
signal i_RAMData_pwm : std_logic_vector(0 to 31); -- local ram to add
signal i_RAMData_pwm2: std_logic_vector(0 to 31);
signal o_RAMWE_pwm : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
signal s_zero : signed(31 downto 0) := to_signed(integer(real(-1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal s_one : signed(31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal refresh_state : std_logic;
signal process_state : integer range 0 to 2;
signal add_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant add_START : std_logic_vector(31 downto 0) := x"0000000F";
constant add_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_pwm <= std_logic_vector(add_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_addrESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_addrESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_pwm = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_pwm))) := o_RAMData_pwm;
else -- else needed, because add is consuming samples
i_RAMData_pwm <= local_ram(to_integer(unsigned(o_RAMAddr_pwm)));
i_RAMData_pwm2<= local_ram(to_integer(unsigned(o_RAMAddr_pwm2)));
end if;
end if;
end process;
add_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
o_RAMWE_pwm<= '0';
o_RAMAddr_pwm <= (others => '0');
o_RAMAddr_pwm2 <= std_logic_vector(to_signed(C_MAX_SAMPLE_COUNT,o_RAMAddr_pwm2'length));
refresh_state <= '0';
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = add_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = add_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when '0' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '1';
end if;
when '1' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.opt_arg_addr, std_logic_vector(to_unsigned(C_MAX_SAMPLE_COUNT,32)), std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '0';
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= '0';
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
if signed(i_RAMData_pwm) > signed(i_RAMData_pwm2) then
add_data <= s_one ;
else
add_data <= s_zero;
end if;
process_state <= 1;
when 1 =>
o_RAMData_pwm <= std_logic_vector(resize(add_data, 32));
o_RAMWE_pwm <= '1';
process_state <= 0;
when 2 =>
o_RAMWE_pwm <= '0';
o_RAMAddr_pwm <= std_logic_vector(unsigned(o_RAMAddr_pwm) + 1);
o_RAMAddr_pwm2 <= std_logic_vector(unsigned(o_RAMAddr_pwm2) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_pwm <= (others => '0');
o_RAMAddr_pwm2 <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_addr std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
|
mit
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/vhdl/axi_hdmi_tx_16b.vhd
|
1
|
11608
|
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_hdmi_tx_16b is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_hdmi_tx_16b;
architecture IMP of axi_hdmi_tx_16b is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_be : in std_logic_vector(7 downto 0);
vdma_last : in std_logic;
vdma_ready : out std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
hdmi_ref_clk => hdmi_ref_clk,
hdmi_clk => hdmi_clk,
hdmi_vsync => hdmi_vsync,
hdmi_hsync => hdmi_hsync,
hdmi_data_e => hdmi_data_e,
hdmi_data => hdmi_data,
vdma_clk => vdma_clk,
vdma_fs => vdma_fs,
vdma_fs_ret => vdma_fs_ret,
vdma_empty => vdma_empty,
vdma_almost_empty => vdma_almost_empty,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_be => M_AXIS_MM2S_TKEEP,
vdma_last => M_AXIS_MM2S_TLAST,
vdma_ready => M_AXIS_MM2S_TREADY,
up_status => up_status,
debug_trigger => debug_trigger,
debug_data => debug_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
|
mit
|
EPiCS/soundgates
|
hardware/basic/cordic/cordic_stage.vhd
|
1
|
3260
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - cordic_stage.vhd
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Part of the cordic implementation
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity cordic_stage is
Generic( stage : integer := 1;
alpha : real := 0.5
);
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ce : in STD_LOGIC;
x : in SIGNED (31 downto 0);
y : in SIGNED (31 downto 0);
z : in SIGNED (31 downto 0);
x_n : out SIGNED (31 downto 0);
y_n : out SIGNED (31 downto 0);
z_n : out SIGNED (31 downto 0)
);
end cordic_stage;
architecture Behavioral of cordic_stage is
-- registers
signal x_next : signed(31 downto 0) := (others => '0');
signal y_next : signed(31 downto 0) := (others => '0');
signal z_next : signed(31 downto 0) := (others => '0');
-- intermediate signals
signal x_next_i : signed(31 downto 0);
signal y_next_i : signed(31 downto 0);
signal z_next_i : signed(31 downto 0);
constant arctan_init : real := ARCTAN(alpha) * 2**SOUNDGATE_FIX_PT_SCALING;
constant scaled_arctan : signed(31 downto 0) := to_signed(integer(arctan_init), 32);
signal y_shift : signed(31 downto 0);
signal x_shift : signed(31 downto 0);
begin
SHIFT_PROCESS : process(x, y)
begin
y_shift <= shift_right(y, stage); -- x 2^-stage
x_shift <= shift_right(x, stage);
end process;
ARTIHM_PROCESS : process(x, y, z, x_shift, y_shift)
variable x_next : signed(31 downto 0);
variable y_next : signed(31 downto 0);
variable z_next : signed(31 downto 0);
begin
if z(31) = '0' then -- sgn = + 1
x_next := x + (-y_shift);
y_next := x_shift + y;
z_next := z + (-scaled_arctan);
else -- sgn = -1
x_next := x + y_shift;
y_next := (-x_shift) + y;
z_next := z + scaled_arctan;
end if;
x_next_i <= x_next;
y_next_i <= y_next;
z_next_i <= z_next;
end process;
REG_PROCESS : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
x_next <= (others => '0');
y_next <= (others => '0');
z_next <= (others => '0');
elsif ce = '1' then
x_next <= x_next_i;
y_next <= y_next_i;
z_next <= z_next_i;
end if;
end if;
end process;
x_n <= x_next;
y_n <= y_next;
z_n <= z_next;
end Behavioral;
|
mit
|
EPiCS/soundgates
|
hardware/basic/sub/sub.vhd
|
1
|
1464
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - sub.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: subtracts two samples
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity sub is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end sub;
architecture Behavioral of sub is
begin
adder : process (clk, rst, ce)
begin
if rising_edge(clk) then
if ce = '1' then
output <= wave1 - wave2;
end if;
end if;
end process;
end Behavioral;
|
mit
|
EPiCS/soundgates
|
hardware/hwt/pcores/hwt_sinus_v1_00_a/hdl/vhdl/hwt_sinus.vhd
|
1
|
12187
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sinus
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Hardware thread for a sine wave
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sinus is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sinus;
architecture Behavioral of hwt_sinus is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component nco is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SIN
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
end component nco;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_IDLE, STATE_REFRESH_HWT_ARGS, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := clog2(C_LOCAL_RAM_SIZE); -- 6
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_nco : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_nco : std_logic_vector(0 to 31); -- nco to local ram
signal i_RAMData_nco : std_logic_vector(0 to 31); -- local ram to nco
signal o_RAMWE_nco : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
----------------------------------------------------------------
-- Hardware arguements
----------------------------------------------------------------
signal hwtio : hwtio_t;
-- arg[0] = destination address
-- arg[1] = phase offset
-- arg[2] = phase increment
-- argc = 3
constant hwt_argc : integer := 3;
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal nco_ce : std_logic; -- nco clock enable (like a start/stop signal)
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
signal nco_data : signed(31 downto 0);
signal destaddr : std_logic_vector(DWORD_WIDTH - 1 downto 0);
signal phaseoffset : std_logic_vector(31 downto 0);
signal phaseincr : std_logic_vector(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant NCO_START : std_logic_vector(31 downto 0) := x"0000000F";
constant NCO_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Component related wiring
-----------------------------------
destaddr <= hwtio.argv(0);
phaseoffset <= hwtio.argv(1);
phaseincr <= hwtio.argv(2);
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_nco <= std_logic_vector(nco_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
nco_inst : nco
generic map(
FPGA_FREQUENCY => SND_COMP_CLK_FREQ,
WAVEFORM => SIN
)
port map(
clk => clk,
rst => rst,
ce => nco_ce,
phase_offset => signed(phaseoffset),
phase_incr => signed(phaseincr),
data => nco_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_nco = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_nco))) := o_RAMData_nco;
--else -- else not needed, because nco is not consuming any samples
-- i_RAMData_nco <= local_ram(conv_integer(unsigned(o_RAMAddr_nco)));
end if;
end if;
end process;
NCO_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
osif_ctrl_signal <= (others => '0');
state <= STATE_IDLE;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
nco_ce <= '0';
o_RAMWE_nco <= '0';
state_inner_process <= '0';
-- Initialize hwt args
hwtio.f_step <= 0;
hwtio.base_addr <= (others => '0');
done := False;
elsif rising_edge(clk) then
nco_ce <= '0';
o_RAMWE_nco <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
when STATE_IDLE =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = NCO_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_HWT_ARGS;
elsif osif_ctrl_signal = NCO_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_HWT_ARGS =>
get_hwt_args(i_osif, o_osif, i_memif, o_memif, hwtio, hwt_argc, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_nco <= '1';
nco_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_nco <= std_logic_vector(unsigned(o_RAMAddr_nco) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
when others =>
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_nco <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", destaddr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, destaddr, ignore, done);
if done then
state <= STATE_IDLE;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
|
mit
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/axi_i2s_adi.vhd
|
1
|
12135
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.i2s_controller;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_streaming_dma_rx_fifo;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl330_dma_fifo;
use adi_common_v1_00_a.axi_ctrlif;
entity axi_i2s_adi is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_SLOT_WIDTH : integer := 24;
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_DMA_TYPE : integer := 0;
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1
);
port
(
-- Serial Data interface
DATA_CLK_I : in std_logic;
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0);
-- AXI Streaming DMA TX interface
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- AXI Streaming DMA RX interface
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
--PL330 DMA TX interface
DMA_REQ_TX_ACLK : in std_logic;
DMA_REQ_TX_RSTN : in std_logic;
DMA_REQ_TX_DAVALID : in std_logic;
DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_TX_DAREADY : out std_logic;
DMA_REQ_TX_DRVALID : out std_logic;
DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_TX_DRLAST : out std_logic;
DMA_REQ_TX_DRREADY : in std_logic;
-- PL330 DMA RX interface
DMA_REQ_RX_ACLK : in std_logic;
DMA_REQ_RX_RSTN : in std_logic;
DMA_REQ_RX_DAVALID : in std_logic;
DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_RX_DAREADY : out std_logic;
DMA_REQ_RX_DRVALID : out std_logic;
DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_RX_DRLAST : out std_logic;
DMA_REQ_RX_DRREADY : in std_logic;
-- AXI bus interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : inout std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : inout std_logic;
S_AXI_AWREADY : inout std_logic
);
end entity axi_i2s_adi;
architecture Behavioral of axi_i2s_adi is
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal i2s_reset : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_enable : Boolean;
signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal tx_ack : std_logic;
signal tx_stb : std_logic;
signal rx_enable : Boolean;
signal rx_fifo_reset : std_logic;
signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal rx_ack : std_logic;
signal rx_stb : std_logic;
signal bclk_div_rate : natural range 0 to 255;
signal lrclk_div_rate : natural range 0 to 255;
signal period_len : integer range 0 to 65535;
signal I2S_RESET_REG : std_logic_vector(31 downto 0);
signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8))));
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
-- RX FIFO signals
signal audio_fifo_rx : RAM_TYPE;
signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal tvalid : std_logic := '0';
signal rx_tlast : std_logic;
signal drain_tx_dma : std_logic;
signal rx_sample : std_logic_vector(23 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 11;
signal rd_addr : integer range 0 to 11;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
signal tx_fifo_stb : std_logic;
signal rx_fifo_ack : std_logic;
signal cnt : integer range 0 to 2**16-1;
begin
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
cnt <= 0;
else
cnt <= (cnt + 1) mod 2**16;
end if;
end if;
end process;
streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate
tx_fifo : entity axi_streaming_dma_tx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8),
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
out_stb => tx_stb,
out_ack => tx_ack,
out_data => tx_data
);
end generate;
streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
period_len => period_len,
in_stb => rx_stb,
in_ack => rx_ack,
in_data => rx_data,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8),
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
M_AXIS_TDATA(7 downto 0) <= (others => '0');
end generate;
pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
tx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 0
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
in_data => wr_data(31 downto 8),
in_stb => tx_fifo_stb,
out_ack => tx_ack,
out_stb => tx_stb,
out_data => tx_data,
dclk => DMA_REQ_TX_ACLK,
dresetn => DMA_REQ_TX_RSTN,
davalid => DMA_REQ_TX_DAVALID,
daready => DMA_REQ_TX_DAREADY,
datype => DMA_REQ_TX_DATYPE,
drvalid => DMA_REQ_TX_DRVALID,
drready => DMA_REQ_TX_DRREADY,
drtype => DMA_REQ_TX_DRTYPE,
drlast => DMA_REQ_TX_DRLAST
);
end generate;
pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
rx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 1
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => rx_fifo_reset,
enable => rx_enable,
in_ack => rx_ack,
in_stb => rx_stb,
in_data => rx_data,
out_data => rx_sample,
out_ack => rx_fifo_ack,
dclk => DMA_REQ_RX_ACLK,
dresetn => DMA_REQ_RX_RSTN,
davalid => DMA_REQ_RX_DAVALID,
daready => DMA_REQ_RX_DAREADY,
datype => DMA_REQ_RX_DATYPE,
drvalid => DMA_REQ_RX_DRVALID,
drready => DMA_REQ_RX_DRREADY,
drtype => DMA_REQ_RX_DRTYPE,
drlast => DMA_REQ_RX_DRLAST
);
end generate;
ctrl : entity i2s_controller
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_BCLK_POL => C_BCLK_POL,
C_LRCLK_POL => C_LRCLK_POL,
C_NUM_CH => C_NUM_CH,
C_HAS_TX => C_HAS_TX,
C_HAS_RX => C_HAS_RX
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
data_clk => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
tx_enable => tx_enable,
tx_ack => tx_ack,
tx_stb => tx_stb,
tx_data => tx_data,
rx_enable => rx_enable,
rx_ack => rx_ack,
rx_stb => rx_stb,
rx_data => rx_data,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate
);
i2s_reset <= I2S_RESET_REG(0);
tx_fifo_reset <= I2S_RESET_REG(1);
rx_fifo_reset <= I2S_RESET_REG(2);
tx_enable <= I2S_CONTROL_REG(0) = '1';
rx_enable <= I2S_CONTROL_REG(1) = '1';
bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
ctrlif: entity axi_ctrlif
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_REG => 12
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
rd_stb => '1',
wr_addr => wr_addr,
wr_data => wr_data,
wr_ack => '1',
wr_stb => wr_stb
);
process(rd_addr)
begin
case rd_addr is
when 1 => rd_data <= I2S_CONTROL_REG and x"3";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 6 => rd_data <= PERIOD_LEN_REG and x"ffff";
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
when others => rd_data <= (others => '0');
end case;
end process;
process(S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0');
PERIOD_LEN_REG <= (others => '0');
else
-- Auto-clear the Reset Register bits
I2S_RESET_REG(0) <= '0';
I2S_RESET_REG(1) <= '0';
I2S_RESET_REG(2) <= '0';
if wr_stb = '1' then
case wr_addr is
when 0 => I2S_RESET_REG <= wr_data;
when 1 => I2S_CONTROL_REG <= wr_data;
when 2 => I2S_CLK_CONTROL_REG <= wr_data;
when 6 => PERIOD_LEN_REG <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
jandecaluwe/myhdl-examples
|
gray_counter/vhdl/gray_counter_16.vhd
|
1
|
1286
|
-- File: gray_counter_16.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_16 is
port (
gray_count: out unsigned(15 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_16;
architecture MyHDL of gray_counter_16 is
signal even: std_logic;
signal gray: unsigned(15 downto 0);
begin
GRAY_COUNTER_16_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(15 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((16 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 16-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_16_SEQ;
gray_count <= gray;
end architecture MyHDL;
|
mit
|
EPiCS/soundgates
|
hardware/hwt/pcores/hwt_sample_add_v1_00_a/hdl/vhdl/hwt_sample_add.vhd
|
1
|
13021
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sample_add
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating add envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sample_add is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sample_add;
architecture Behavioral of hwt_sample_add is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_add : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_add2: std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_add : std_logic_vector(0 to 31); -- add to local ram
signal i_RAMData_add : std_logic_vector(0 to 31); -- local ram to add
signal i_RAMData_add2: std_logic_vector(0 to 31);
signal o_RAMWE_add : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal refresh_state : std_logic;
signal process_state : integer range 0 to 2;
signal add_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant add_START : std_logic_vector(31 downto 0) := x"0000000F";
constant add_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_add <= std_logic_vector(add_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_add = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_add))) := o_RAMData_add;
else -- else needed, because add is consuming samples
i_RAMData_add <= local_ram(to_integer(unsigned(o_RAMAddr_add)));
i_RAMData_add2<= local_ram(to_integer(unsigned(o_RAMAddr_add2)));
end if;
end if;
end process;
add_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
o_RAMWE_add<= '0';
o_RAMAddr_add <= (others => '0');
o_RAMAddr_add2 <= std_logic_vector(to_signed(C_MAX_SAMPLE_COUNT,o_RAMAddr_add2'length));
refresh_state <= '0';
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = add_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = add_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when '0' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '1';
end if;
when '1' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.opt_arg_addr, std_logic_vector(to_unsigned(C_MAX_SAMPLE_COUNT,32)), std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '0';
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= '0';
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
add_data <= signed(i_RAMData_add) + signed(i_RAMData_add2);
process_state <= 1;
when 1 =>
o_RAMData_add <= std_logic_vector(resize(add_data, 32));
o_RAMWE_add <= '1';
process_state <= 0;
when 2 =>
o_RAMWE_add <= '0';
o_RAMAddr_add <= std_logic_vector(unsigned(o_RAMAddr_add) + 1);
o_RAMAddr_add2 <= std_logic_vector(unsigned(o_RAMAddr_add2) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_add <= (others => '0');
o_RAMAddr_add2 <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
|
mit
|
EPiCS/soundgates
|
hardware/basic/mul/mul.vhd
|
1
|
1548
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - mul.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: multiplies two samples
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity mul is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end mul;
architecture Behavioral of mul is
signal output64 : signed (63 downto 0);
begin
output <= output64(31 downto 0);
adder : process (clk, rst, ce)
begin
if rising_edge(clk) then
if ce = '1' then
output64 <= wave1 * wave2;
end if;
end if;
end process;
end Behavioral;
|
mit
|
PsichiX/linguist
|
samples/VHDL/foo.vhd
|
91
|
217
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
mit
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/vhdl/axi_upif.vhd
|
1
|
6926
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2011(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_upif is
generic (
C_S_AXI_MIN_SIZE : std_logic_vector := x"0000ffff";
C_BASEADDR : std_logic_vector := x"ffffffff";
C_HIGHADDR : std_logic_vector := x"00000000");
port (
up_rstn : out std_logic;
up_clk : out std_logic;
upif_sel : out std_logic;
upif_rwn : out std_logic;
upif_addr : out std_logic_vector(31 downto 0);
upif_wdata : out std_logic_vector(31 downto 0);
upif_wack : in std_logic;
upif_rdata : in std_logic_vector(31 downto 0);
upif_rack : in std_logic;
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(31 downto 0);
s_axi_awvalid : in std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(31 downto 0);
s_axi_arvalid : in std_logic;
s_axi_rready : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_awready : out std_logic);
end entity axi_upif;
architecture rtl of axi_upif is
constant ZERO_32 : std_logic_vector(31 downto 0) := (others => '0');
constant C_TIMEOUT : integer := 16;
constant C_NUM_CE : INTEGER_ARRAY_TYPE := (0 => (32));
constant C_ADDR_RANGE : SLV64_ARRAY_TYPE := (ZERO_32 & C_BASEADDR, ZERO_32 & C_HIGHADDR);
signal gnd : std_logic;
signal upif_sel_s : std_logic_vector(0 downto 0);
begin
gnd <= '0';
upif_sel <= upif_sel_s(0);
i_axi_lite_ipif: entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_DPHASE_TIMEOUT => C_TIMEOUT,
C_ARD_NUM_CE_ARRAY => C_NUM_CE,
C_ARD_ADDR_RANGE_ARRAY => C_ADDR_RANGE)
port map (
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_RREADY => s_axi_rready,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_AWREADY => s_axi_awready,
Bus2IP_Clk => up_clk,
Bus2IP_Resetn => up_rstn,
Bus2IP_Addr => upif_addr,
Bus2IP_RNW => upif_rwn,
Bus2IP_BE => open,
Bus2IP_CS => upif_sel_s,
Bus2IP_RdCE => open,
Bus2IP_WrCE => open,
Bus2IP_Data => upif_wdata,
IP2Bus_WrAck => upif_wack,
IP2Bus_RdAck => upif_rack,
IP2Bus_Error => gnd,
IP2Bus_Data => upif_rdata);
end rtl;
-- ***************************************************************************
-- ***************************************************************************
|
mit
|
EPiCS/soundgates
|
hardware/sndcomponents/nco/nco.vhd
|
1
|
6446
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - nco.vhd
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Numeric controlled oscillator top level entity
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity nco is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SIN
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
end nco;
architecture Behavioral of nco is
--------------------------------------------------------------------------------
-- Cordic related components and signals
--------------------------------------------------------------------------------
component cordic
generic ( pipeline_stages : integer := 24 );
port (
phi : in signed(31 downto 0); -- 0 < phi < 2 * pi
sin : out signed(31 downto 0);
cos : out signed(31 downto 0);
clk : in std_logic; -- clock
rst : in std_logic; -- reset
ce : in std_logic -- enable
);
end component cordic;
component sawtooth
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
end component sawtooth;
component square
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
duty_on : in signed(31 downto 0);
duty_off: in signed(31 downto 0);
sq : out signed(31 downto 0)
);
end component square;
component triangle
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
tri : out signed(31 downto 0)
);
end component triangle;
constant cordic_pipeline_stages : integer := 16;
constant standard_cordic_offset : integer := integer(real(MATH_PI * 2.0 * 2 ** SOUNDGATE_FIX_PT_SCALING));
signal cordic_phi_offset : signed(31 downto 0) := (others => '0');
signal cordic_phi_incr : signed(31 downto 0) := (others => '0');
signal cordic_phi_acc : signed(31 downto 0) := (others => '0');
signal cordic_threshold : signed(31 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- FOO related components and signals
--------------------------------------------------------------------------------
begin
SIN_GENERATOR : if WAVEFORM = SIN generate
CORDIC_INSTA : cordic
generic map(
pipeline_stages => cordic_pipeline_stages
)
port map(
clk => clk,
rst => rst,
ce => ce,
phi => cordic_phi_acc,
sin => data,
cos => open );
PHASE_STIMULIS_PROCESS : process(clk, rst)
begin
if rst = '1' then
cordic_phi_acc <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if (cordic_phi_acc + phase_incr) > standard_cordic_offset then
cordic_phi_acc <= phase_incr - (standard_cordic_offset - cordic_phi_acc);
else
cordic_phi_acc <= cordic_phi_acc + phase_incr;
end if;
end if;
end if;
end process;
end generate SIN_GENERATOR;
--------------------------------------------------------------------------------
-- SQUARE_GENERATOR : if WAVEFORM = SQU generate
--
-- SQUARE_INSTA : square
-- port map(
-- clk => clk,
-- ce => ce,
-- rst => rst,
-- incr => phase_incr,
-- offset => phase_offset,
-- duty_on => duty_on,
-- duty_off=> duty_off,
-- sq => data );
--
-- end generate SQUARE_GENERATOR;
--------------------------------------------------------------------------------
TRIANGLE_GENERATOR : if WAVEFORM = TRI generate
TRIANGLE_INSTA : triangle
port map(
clk => clk,
ce => ce,
rst => rst,
incr => phase_incr,
offset => phase_offset,
tri => data );
end generate TRIANGLE_GENERATOR;
--------------------------------------------------------------------------------
SAWTOOTH_GENERATOR : if WAVEFORM = SAW generate
SAWTOOTH_INSTA : sawtooth
port map(
clk => clk,
ce => ce,
rst => rst,
incr => phase_incr,
offset => phase_offset,
saw => data );
end generate SAWTOOTH_GENERATOR;
--------------------------------------------------------------------------------
end Behavioral;
|
mit
|
IslamKhaledH/ArchitecturePorject
|
Project/WriteBack.vhd
|
1
|
526
|
Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity WriteBack is
PORT ( Clk, rst : in std_logic;
DataIn1, DataIn2, DataIn3 : in std_logic_vector(15 downto 0);
ControlIn : in std_logic_vector (1 downto 0);
DataOut : out std_logic_vector (15 downto 0)
);
END WriteBack;
architecture arch_WriteBack of WriteBack is
begin
DataOut <= DataIn1 when ControlIn = "00" else
DataIn2 when ControlIn = "01" else
DataIn3 when ControlIn = "10" else
(others => '0');
end architecture arch_WriteBack;
|
mit
|
jandecaluwe/myhdl-examples
|
gray_counter/vhdl/gray_counter_8.vhd
|
1
|
1275
|
-- File: gray_counter_8.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_8 is
port (
gray_count: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_8;
architecture MyHDL of gray_counter_8 is
signal even: std_logic;
signal gray: unsigned(7 downto 0);
begin
GRAY_COUNTER_8_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(7 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((8 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 8-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_8_SEQ;
gray_count <= gray;
end architecture MyHDL;
|
mit
|
IslamKhaledH/ArchitecturePorject
|
Project/MemoryStage.vhd
|
1
|
2490
|
Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity Memory is
PORT ( Clk, rst, Mux_Selector, Memory_WriteEnable, Stack_WriteEnable, StackPushPop : in std_logic; --StackPushPop 0: psuh, 1: pop
--FlagEnable : in std_logic;
InputAddress, LoadAdress : in std_logic_vector(9 downto 0);
DataIn : in std_logic_vector(15 downto 0);
DataOut, M0, M1 : out std_logic_vector (15 downto 0);
Flags_Z_In, Flags_NF_In, Flags_V_In, Flags_C_In : in std_logic;
Flags_Z_Out, Flags_NF_Out, Flags_V_Out, Flags_C_Out : out std_logic;
BranchOpCode_In : in std_logic_vector (4 downto 0);
BranchR1_In : in std_logic_vector (15 downto 0);
Branch_Out : out std_logic_vector (15 downto 0)
);
END Memory;
architecture arch_Memory of Memory is
Component syncram2 is
Generic ( n : integer := 8);
port ( clk,rst : in std_logic;
we, weStack, stackPushPop : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0);
dataout0 : out std_logic_vector(15 downto 0);
dataout1 : out std_logic_vector(15 downto 0)
);
end component;
signal Address : std_logic_vector(9 downto 0);
signal DO,DO0,DO1 : std_logic_vector(15 downto 0);
signal dontCare1, dontCare2 : std_logic_vector (15 downto 0);
begin
Mem : syncram2 generic map(n=>10) port map(Clk, rst, Memory_WriteEnable, Stack_WriteEnable, StackPushPop, Address, datain,DO,DO0,DO1);
process (clk,rst)
begin
if rising_edge(clk) then
if Mux_Selector = '0' then
Address <= InputAddress;
else
Address <= LoadAdress;
end if;
DataOut <= DO;
M0 <= DO0;
M1 <= DO1;
if BranchOpCode_In = "10100" and Flags_Z_In = '1' then --JZ Rdst
Branch_Out <= BranchR1_In;
Flags_Z_Out <= '0';
elsif BranchOpCode_In = "10101" and Flags_NF_In = '1' then --JN Rdst
Branch_Out <= BranchR1_In;
Flags_NF_Out <= '0';
elsif BranchOpCode_In = "10110" and Flags_C_In = '1' then --JC Rdst
Branch_Out <= BranchR1_In;
Flags_C_Out <= '0';
elsif BranchOpCode_In = "10111" then --JMP Rdst
Branch_Out <= BranchR1_In;
elsif BranchOpCode_In = "11001" then --RET
Branch_Out <= DO;
elsif BranchOpCode_In = "11010" then --RTI --FLAGS RESTORED
Branch_Out <= DO;
Flags_Z_Out <= '0';
Flags_NF_Out <= '0';
Flags_C_Out <= '0';
Flags_V_Out <= '0';
else
Flags_Z_Out <= Flags_Z_In;
Flags_NF_Out <= Flags_NF_In;
Flags_C_Out <= Flags_C_In;
Flags_V_Out <= Flags_V_In;
end if;
end if;
end process;
end architecture arch_Memory;
|
mit
|
huljar/present-vhdl
|
src/present_top.vhd
|
1
|
2908
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity present_top is
generic(k: key_enum);
port(plaintext: in std_logic_vector(63 downto 0);
key: in std_logic_vector(key_bits(k)-1 downto 0);
clk: in std_logic;
reset: in std_logic;
ciphertext: out std_logic_vector(63 downto 0)
);
end present_top;
architecture behavioral of present_top is
signal data_state,
data_key_added,
data_substituted,
data_permuted: std_logic_vector(63 downto 0);
signal key_state,
key_updated: std_logic_vector(key_bits(k)-1 downto 0);
signal round_counter: std_logic_vector(4 downto 0);
component sub_layer
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end component;
component perm_layer
port(data_in: in std_logic_vector(63 downto 0);
data_out: out std_logic_vector(63 downto 0)
);
end component;
component key_schedule
generic(k: key_enum);
port(data_in: in std_logic_vector(key_bits(k)-1 downto 0);
round_counter: in std_logic_vector(4 downto 0);
data_out: out std_logic_vector(key_bits(k)-1 downto 0)
);
end component;
begin
SL: sub_layer port map(
data_in => data_key_added,
data_out => data_substituted
);
PL: perm_layer port map(
data_in => data_substituted,
data_out => data_permuted
);
KS: key_schedule generic map(
k => k
) port map(
data_in => key_state,
round_counter => round_counter,
data_out => key_updated
);
data_key_added <= data_state xor key_state(key_bits(k)-1 downto key_bits(k)-64);
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
data_state <= plaintext;
key_state <= key;
round_counter <= "00001";
ciphertext <= (others => '0');
else
data_state <= data_permuted;
key_state <= key_updated;
round_counter <= std_logic_vector(unsigned(round_counter) + 1);
-- when we are "past" the final round, i.e. the 31st round was finished,
-- the round counter addition overflows back to zero. Now set the output
-- signal to the ciphertext.
case round_counter is
when "00000" => ciphertext <= data_key_added;
when others => ciphertext <= (others => '0');
end case;
--if round_counter = "00000" then
-- ciphertext <= data_key_added;
--end if;
end if;
end if;
end process;
end behavioral;
|
mit
|
hamsternz/FPGA_DisplayPort
|
src/data_stream.vhd
|
1
|
23091
|
----------------------------------------------------------------------------------
-- Module Name: data_stream_test - Behavioral
--
-- Description: For sumulating the data stream, without the TX modules.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-29 | Updated for Opsis
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_stream_test is
port (
symbolclk : in STD_LOGIC;
symbols : out std_logic_vector(79 downto 0)
);
end data_stream_test;
architecture Behavioral of data_stream_test is
component test_source_800_600_RGB_444_ch4 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_3840_2160_YCC_422_ch2 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component insert_main_stream_attrbutes_four_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
signal M_value : std_logic_vector(23 downto 0);
signal N_value : std_logic_vector(23 downto 0);
signal H_visible : std_logic_vector(11 downto 0);
signal V_visible : std_logic_vector(11 downto 0);
signal H_total : std_logic_vector(11 downto 0);
signal V_total : std_logic_vector(11 downto 0);
signal H_sync_width : std_logic_vector(11 downto 0);
signal V_sync_width : std_logic_vector(11 downto 0);
signal H_start : std_logic_vector(11 downto 0);
signal V_start : std_logic_vector(11 downto 0);
signal H_vsync_active_high : std_logic;
signal V_vsync_active_high : std_logic;
signal flag_sync_clock : std_logic;
signal flag_YCCnRGB : std_logic;
signal flag_422n444 : std_logic;
signal flag_YCC_colour_709 : std_logic;
signal flag_range_reduced : std_logic;
signal flag_interlaced_even : std_logic;
signal flags_3d_Indicators : std_logic_vector(1 downto 0);
signal bits_per_colour : std_logic_vector(4 downto 0);
component insert_main_stream_attrbutes_two_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
component idle_pattern_inserter is
port (
clk : in std_logic;
channel_ready : in std_logic;
source_ready : in std_logic;
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component scrambler_reset_inserter is
port (
clk : in std_logic;
in_data : in std_logic_vector(71 downto 0);
out_data : out std_logic_vector(71 downto 0)
);
end component;
component scrambler is
port (
clk : in std_logic;
bypass0 : in std_logic;
bypass1 : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0)
);
end component;
component data_to_8b10b is
port (
clk : in std_logic;
forceneg : in std_logic_vector(1 downto 0);
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(19 downto 0)
);
end component;
component training_and_channel_delay is
port (
clk : in std_logic;
channel_delay : in std_logic_vector(1 downto 0);
clock_train : in std_logic;
align_train : in std_logic;
in_data : in std_logic_vector(17 downto 0);
out_data : out std_logic_vector(17 downto 0);
out_data0forceneg : out std_logic;
out_data1forceneg : out std_logic
);
end component;
signal support_RGB444 : std_logic := '0';
signal support_YCC444 : std_logic := '0';
signal support_YCC422 : std_logic := '0';
--------------------------------------------
-- EDID data
---------------------------------------------
signal edid_valid : std_logic := '0';
signal pixel_clock_x10k : std_logic_vector(15 downto 0) := (others => '0');
signal h_visible_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_blank_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_front_len : std_logic_vector(11 downto 0) := (others => '0');
signal h_sync_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_visible_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_blank_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_front_len : std_logic_vector(11 downto 0) := (others => '0');
signal v_sync_len : std_logic_vector(11 downto 0) := (others => '0');
signal interlaced : std_logic := '0';
--------------------------------------------
-- Display port data
---------------------------------------------
signal dp_valid : std_logic := '0';
signal dp_revision : std_logic_vector(7 downto 0) := (others => '0');
signal dp_link_rate_2_70 : std_logic := '0';
signal dp_link_rate_1_62 : std_logic := '0';
signal dp_extended_framing : std_logic := '0';
signal dp_link_count : std_logic_vector(3 downto 0) := (others => '0');
signal dp_max_downspread : std_logic_vector(7 downto 0) := (others => '0');
signal dp_coding_supported : std_logic_vector(7 downto 0) := (others => '0');
signal dp_port0_capabilities : std_logic_vector(15 downto 0) := (others => '0');
signal dp_port1_capabilities : std_logic_vector(15 downto 0) := (others => '0');
signal dp_norp : std_logic_vector(7 downto 0) := (others => '0');
--------------------------------------------------------------------------
signal tx_powerup : std_logic := '0';
signal tx_clock_train : std_logic := '0';
signal tx_align_train : std_logic := '0';
signal data_channel_0 : std_logic_vector(19 downto 0):= (others => '0');
------------------------------------------------
signal tx_debug : std_logic_vector(7 downto 0);
signal sink_channel_count : std_logic_vector(2 downto 0) := "000";
signal source_channel_count : std_logic_vector(2 downto 0) := "010";
signal active_channel_count : std_logic_vector(2 downto 0) := "000";
signal stream_channel_count : std_logic_vector(2 downto 0) := "000";
signal test_signal : std_logic_vector(8 downto 0);
signal scramble_bypass : std_logic;
signal test_signal_ready : std_logic;
signal test_signal_data : std_logic_vector(72 downto 0) := (others => '0'); -- With switching point
signal msa_merged_data : std_logic_vector(72 downto 0) := (others => '0'); -- With switching point
signal signal_data : std_logic_vector(71 downto 0) := (others => '0');
signal sr_inserted_data : std_logic_vector(71 downto 0) := (others => '0');
signal scrambled_data : std_logic_vector(71 downto 0) := (others => '0');
signal final_data : std_logic_vector(71 downto 0) := (others => '0');
signal force_parity_neg : std_logic_vector( 7 downto 0) := (others => '0');
signal hpd_irq : std_logic;
signal hpd_present : std_logic;
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
constant delay_index : std_logic_vector(7 downto 0) := "11100100"; -- 3,2,1,0 for use as a lookup table in the generate loop
signal count : unsigned(15 downto 0) := (others => '0');
begin
sink_channel_count <= dp_link_count(2 downto 0);
i_test_source: test_source_800_600_RGB_444_ch4 port map (
--i_test_source: test_source_3840_2160_YCC_422_ch2 port map (
M_value => M_value,
N_value => N_value,
H_visible => H_visible,
H_total => H_total,
H_sync_width => H_sync_width,
H_start => H_start,
V_visible => V_visible,
V_total => V_total,
V_sync_width => V_sync_width,
V_start => V_start,
H_vsync_active_high => H_vsync_active_high,
V_vsync_active_high => V_vsync_active_high,
flag_sync_clock => flag_sync_clock,
flag_YCCnRGB => flag_YCCnRGB,
flag_422n444 => flag_422n444,
flag_range_reduced => flag_range_reduced,
flag_interlaced_even => flag_interlaced_even,
flag_YCC_colour_709 => flag_YCC_colour_709,
flags_3d_Indicators => flags_3d_Indicators,
bits_per_colour => bits_per_colour,
stream_channel_count => stream_channel_count,
clk => symbolclk,
ready => test_signal_ready,
data => test_signal_data
);
--i_insert_main_stream_attrbutes_one_channel: insert_main_stream_attrbutes_one_channel port map (
--i_insert_main_stream_attrbutes_two_channels: insert_main_stream_attrbutes_two_channels port map (
i_insert_main_stream_attrbutes_four_channels: insert_main_stream_attrbutes_four_channels port map (
clk => symbolclk,
active => '1',
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value => M_value,
N_value => N_value,
H_visible => H_visible,
H_total => H_total,
H_sync_width => H_sync_width,
H_start => H_start,
V_visible => V_visible,
V_total => V_total,
V_sync_width => V_sync_width,
V_start => V_start,
H_vsync_active_high => H_vsync_active_high,
V_vsync_active_high => V_vsync_active_high,
flag_sync_clock => flag_sync_clock,
flag_YCCnRGB => flag_YCCnRGB,
flag_422n444 => flag_422n444,
flag_range_reduced => flag_range_reduced,
flag_interlaced_even => flag_interlaced_even,
flag_YCC_colour_709 => flag_YCC_colour_709,
flags_3d_Indicators => flags_3d_Indicators,
bits_per_colour => bits_per_colour,
-----------------------------------------------------
-- The stream of pixel data coming in
-----------------------------------------------------
in_data => test_signal_data,
-----------------------------------------------------
-- The stream of pixel data going out
-----------------------------------------------------
out_data => msa_merged_data
);
i_idle_pattern_inserter: idle_pattern_inserter port map (
clk => symbolclk,
channel_ready => '1',
source_ready => test_signal_ready,
in_data => msa_merged_data,
out_data => signal_data
);
i_scrambler_reset_inserter: scrambler_reset_inserter
port map (
clk => symbolclk,
in_data => signal_data,
out_data => sr_inserted_data
);
g_per_channel: for i in 0 to 3 generate
i_scrambler: scrambler
port map (
clk => symbolclk,
bypass0 => '1',
bypass1 => '1',
in_data => sr_inserted_data(17+i*18 downto 0+i*18),
out_data => scrambled_data(17+i*18 downto 0+i*18)
);
i_train_channel: training_and_channel_delay port map (
clk => symbolclk,
channel_delay => delay_index(1+i*2 downto 0+i*2),
clock_train => tx_clock_train,
align_train => tx_align_train,
in_data => scrambled_data(17+i*18 downto 0+i*18),
out_data => final_data(17+i*18 downto 0+i*18),
out_data0forceneg => force_parity_neg(0+i*2),
out_data1forceneg => force_parity_neg(1+i*2)
);
i_data_to_8b10b: data_to_8b10b port map (
clk => symbolclk,
in_data => final_data(17+i*18 downto 0+i*18),
out_data => symbols(19+i*20 downto 0+i*20),
forceneg => force_parity_neg(1+i*2 downto 0+i*2)
);
end generate;
end Behavioral;
|
mit
|
FranciscoKnebel/ufrgs-projects
|
neander/neanderImplementation/ipcore_dir/dualBRAM/simulation/checker.vhd
|
69
|
5607
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
mit
|
huljar/present-vhdl
|
sim/present128_axis_tb.vhd
|
1
|
4862
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:37:59 02/28/2017
-- Design Name:
-- Module Name: /home/julian/Projekt/Xilinx Projects/present-vhdl/src/present_tb.vhd
-- Project Name: present-vhdl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: present_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.std_logic_textio.ALL;
USE work.util.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY present128_axis_tb IS
END present128_axis_tb;
ARCHITECTURE behavior OF present128_axis_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT axi_stream_wrapper
GENERIC(
k : key_enum
);
PORT(
ACLK : IN std_logic;
ARESETN : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(31 downto 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TVALID : IN std_logic;
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TDATA : OUT std_logic_vector(31 downto 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TREADY : IN std_logic
);
END COMPONENT;
--Inputs
signal ACLK : std_logic := '0';
signal ARESETN : std_logic := '0';
signal S_AXIS_TDATA : std_logic_vector(31 downto 0) := (others => '0');
signal S_AXIS_TLAST : std_logic := '0';
signal S_AXIS_TVALID : std_logic := '0';
signal M_AXIS_TREADY : std_logic := '0';
--Outputs
signal S_AXIS_TREADY : std_logic;
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(31 downto 0);
signal M_AXIS_TLAST : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
-- Other signals
signal ciphertext : std_logic_vector(63 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: axi_stream_wrapper GENERIC MAP (
k => K_128
) PORT MAP (
ACLK => ACLK,
ARESETN => ARESETN,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
-- Clock process definitions
clk_process: process
begin
ACLK <= '0';
wait for clk_period/2;
ACLK <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable ct: line;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- write plaintext
ARESETN <= '1';
S_AXIS_TVALID <= '1';
S_AXIS_TDATA <= x"01234567";
wait for clk_period;
assert (S_AXIS_TREADY = '1') report "ERROR: axi slave is not ready!" severity error;
wait for clk_period;
S_AXIS_TDATA <= x"89ABCDEF";
wait for clk_period;
-- write key
S_AXIS_TDATA <= x"01234567";
wait for clk_period;
S_AXIS_TDATA <= x"89ABCDEF";
wait for clk_period;
S_AXIS_TDATA <= x"01234567";
wait for clk_period;
S_AXIS_TDATA <= x"89ABCDEF";
wait for clk_period;
S_AXIS_TDATA <= (others => '0');
S_AXIS_TVALID <= '0';
wait for clk_period;
assert (S_AXIS_TREADY = '0') report "ERROR: axi slave is still ready after reading data!" severity error;
-- wait for processing
wait for clk_period*34;
assert (M_AXIS_TVALID = '1') report "ERROR: axi master is not ready in time!" severity error;
-- read ciphertext
M_AXIS_TREADY <= '1';
wait for clk_period;
ciphertext(63 downto 32) <= M_AXIS_TDATA;
wait for clk_period;
ciphertext(31 downto 0) <= M_AXIS_TDATA;
wait for clk_period;
assert (M_AXIS_TVALID = '0') report "ERROR: axi master is still valid after writing all output!" severity error;
M_AXIS_TREADY <= '0';
-- print ciphertext
hwrite(ct, ciphertext);
report "Ciphertext is " & ct.all & " (expected value: 0E9D28685E671DD6)";
deallocate(ct);
wait;
end process;
END;
|
mit
|
hamsternz/FPGA_DisplayPort
|
src/dp_aux_messages.vhd
|
1
|
12459
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: dp_aux_messages - Behavioral
--
-- Description: Messages that will be sent over thr DisplayPort AUX interface
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dp_aux_messages is
port ( clk : in std_logic;
-- Interface to send messages
msg_de : in std_logic;
msg : in std_logic_vector(7 downto 0);
busy : out std_logic;
--- Interface to the AUX Channel
aux_tx_wr_en : out std_logic;
aux_tx_data : out std_logic_vector(7 downto 0));
end dp_aux_messages;
architecture arch of dp_aux_messages is
signal counter : unsigned(11 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
case counter is
-- Write to I2C device at x50 (EDID)
when x"010" => aux_tx_data <= x"40"; aux_tx_wr_en <= '1';
when x"011" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"012" => aux_tx_data <= x"50"; aux_tx_wr_en <= '1';
when x"013" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"014" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
-- Read a block of EDID data
when x"020" => aux_tx_data <= x"50"; aux_tx_wr_en <= '1';
when x"021" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"022" => aux_tx_data <= x"50"; aux_tx_wr_en <= '1';
when x"023" => aux_tx_data <= x"0F"; aux_tx_wr_en <= '1';
-- Read Sink count
when x"030" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"031" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"032" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"033" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
-- Read DP configuration registers (12 of them)
when x"040" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"041" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"042" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"043" => aux_tx_data <= x"0B"; aux_tx_wr_en <= '1';
-- Write DPCD powerstate D3
when x"050" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"051" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"052" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"053" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"054" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
-- Set channel coding (8b/10b)
when x"060" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"061" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"062" => aux_tx_data <= x"08"; aux_tx_wr_en <= '1';
when x"063" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"064" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
-- Set link bandwidth 2.70 Gb/s
when x"070" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"071" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"072" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"073" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"074" => aux_tx_data <= x"0A"; aux_tx_wr_en <= '1';
-- Write Link Downspread
when x"080" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"081" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"082" => aux_tx_data <= x"07"; aux_tx_wr_en <= '1';
when x"083" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"084" => aux_tx_data <= x"10"; aux_tx_wr_en <= '1';
-- Set link count 1
when x"090" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"091" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"092" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"093" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"094" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1'; -- Standard framing, one channel
-- Set link count 2
when x"0A0" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"0A1" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0A2" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0A3" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0A4" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
-- Set link count 4
when x"0B0" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"0B1" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0B2" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0B3" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0B4" => aux_tx_data <= x"04"; aux_tx_wr_en <= '1';
-- Set training pattern 1
when x"0C0" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"0C1" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0C2" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"0C3" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0C4" => aux_tx_data <= x"21"; aux_tx_wr_en <= '1';
-- Read link status for all four lanes
when x"0D0" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"0D1" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"0D2" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0D3" => aux_tx_data <= x"07"; aux_tx_wr_en <= '1';
-- Read the Adjust_Request registers
when x"0E0" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"0E1" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"0E2" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"0E3" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
-- Set training pattern 2
when x"0F0" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"0F1" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0F2" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"0F3" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0F4" => aux_tx_data <= x"22"; aux_tx_wr_en <= '1';
-- Resd lane align status for all four lanes
when x"100" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"101" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"102" => aux_tx_data <= x"04"; aux_tx_wr_en <= '1';
when x"103" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
-- Turn off training patterns / Switch to normal
when x"110" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"111" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"112" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"113" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"114" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1'; -- Scrambler enabled
-- Set Premp level 0, votage 0.4V
when x"140" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"141" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"142" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"143" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"144" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"145" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"146" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"147" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
-- Set Premp level 0, votage 0.6V
when x"160" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"161" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"162" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"163" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"164" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"165" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"166" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"167" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
-- Set Premp level 0, votage 0.8V -- Max voltage
when x"180" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"181" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"182" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"183" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"184" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"185" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"186" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"187" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when others => aux_tx_data <= x"00"; aux_tx_wr_en <= '0';
end case;
----------------------------
-- Move on to the next word?
----------------------------
if counter(3 downto 0) = x"F" then
busy <= '0';
else
counter <= counter+1;
end if;
----------------------------------------
-- Are we being asked to send a message?
--
-- But only do it of we are not already
-- sending something!
----------------------------------------
if msg_de = '1' and counter(3 downto 0) = x"F" then
counter <= unsigned(msg & x"0");
busy <= '1';
end if;
end if;
end process;
end architecture;
|
mit
|
lenchv/fpga-lab.node.js
|
vhdl/user_code.vhd
|
1
|
7865
|
---------------------------------------------------------
-- Здес код, который может использовать все утсройства --
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity user_code is
port(
buttons: in std_logic_vector(7 downto 0);
led: out std_logic_vector(7 downto 0);
web_output_write_o: out std_logic;
web_output_data_o: out std_logic_vector(7 downto 0);
web_output_ready_i: in std_logic;
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
-- PS/2
web_ps2_kbd_data: inout std_logic;
web_ps2_kbd_clk: inout std_logic;
ps2_data1: inout std_logic;
ps2_clk1: inout std_logic;
ps2_data2: inout std_logic;
ps2_clk2: inout std_logic;
reset_o: out std_logic;
-- 50 Mhz
clk: in std_logic
);
end user_code;
architecture Behavioral of user_code is
signal reset : std_logic := '1';
type state is (s_wait, s_data, s_done);
signal ps2d_out, ps2c_out,
ps2d_i, ps2c_i,
idle, rx_done,
tx_wr_ps2, tx_done: std_logic;
signal rx_data, tx_data: std_logic_vector(7 downto 0);
type state_type is (send_ED, rec_ack, send_lock, wait_send);
signal s : state_type := send_ED;
signal led_kbd, led_shift: std_logic_vector(7 downto 0) := (others => '0');
begin
reset_o <= reset;
reset_proc: process(clk)
variable counter: unsigned(1 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if counter = "11" then
reset <= '0';
else
reset <= '1';
counter := counter + 1;
end if;
end if;
end process;
web_ps2_kbd_data <= '0' when ps2d_out = '0' else 'Z';
web_ps2_kbd_clk <= '0' when ps2c_out = '0' else 'Z';
ps2d_i <= '0' when web_ps2_kbd_data = '0' else '1';
ps2c_i <= '0' when web_ps2_kbd_clk = '0' else '1';
---- ![не проходит один такт, проверить на физ клавиатуре]! --
inst_ps2_rx: entity work.ps2_rx
port map (
clk => clk,
reset => reset,
ps2d => ps2d_i,
ps2c => ps2c_i,
rx_en => idle,
rx_done => rx_done,
dout => rx_data
);
inst_ps2_tx: entity work.ps2_tx
port map (
clk => clk,
reset => reset,
ps2d_out => ps2d_out,
ps2c_out => ps2c_out,
ps2d_in => ps2d_i,
ps2c_in => ps2c_i,
tx_idle => idle,
din => tx_data,
wr_ps2 => tx_wr_ps2,
tx_done => tx_done
);
proc_out: process(reset, clk)
begin
if reset = '1' then
web_output_write_o <= '0';
elsif rising_edge(clk) then
web_output_write_o <= '0';
if rx_done = '1' then
web_output_data_o <= rx_data;
web_output_write_o <= '1';
end if;
end if;
end process;
led <= led_shift;
proc_rx: process(reset, clk)
variable realesed, ext_code: boolean;
begin
if reset = '1' then
led_kbd <= (others => '0');
realesed := false;
ext_code := false;
led_shift <= (others => '0');
elsif rising_edge(clk) then
tx_wr_ps2 <= '0';
case s is
when send_ED =>
if rot_center = '1' then
tx_data <= X"F4";
tx_wr_ps2 <= '1';
s <= rec_ack;
elsif buttons(4) = '1' then
tx_data <= X"AA";
tx_wr_ps2 <= '1';
s <= rec_ack;
elsif rx_done='1' then
if realesed then
realesed := false;
elsif ext_code then
case rx_data is
-- left
when X"6B" =>
led_shift <= led_shift(6 downto 0) & '1';
-- right
when X"74" =>
led_shift <= '0' & led_shift(7 downto 1);
when others => null;
end case;
ext_code := false;
else
case rx_data is
when X"77" =>
led_kbd(1) <= not led_kbd(1);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"7E" =>
led_kbd(0) <= not led_kbd(0);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"58" =>
led_kbd(2) <= not led_kbd(2);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"5A" =>
tx_data <= X"EE";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"76" =>
tx_data <= X"FF";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"05" =>
tx_data <= X"FE";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"E0" =>
ext_code := true;
when X"F0" =>
realesed := true;
when others => null;
end case;
end if;
end if;
when rec_ack =>
if rx_done = '1' then
if tx_data = X"ED" and rx_data = X"FA" then
s <= send_lock;
else
s <= send_ED;
end if;
end if;
when send_lock =>
tx_data <= led_kbd;
tx_wr_ps2 <= '1';
s <= wait_send;
when wait_send =>
if tx_done = '1' then
s <= send_ED;
end if;
end case;
end if;
end process;
-- proc_rx: process(reset, ps2c_i)
-- variable counter: unsigned(2 downto 0);
-- begin
-- if reset = '1' then
-- rx_done <= '0';
-- rx_data <= (others => '0');
-- elsif rising_edge(ps2c_i) then
-- rx_done <= '0';
-- if idle = '1' then
-- case s is
-- when s_wait =>
-- if ps2d_i = '0' then
-- s <= s_data;
-- counter := "111";
-- end if;
-- when s_data =>
-- rx_data <= ps2d_i & rx_data(7 downto 1);
-- if counter = "000" then
-- s <= s_done;
-- else
-- counter := counter - "001";
-- end if;
-- when s_done =>
-- rx_done <= '1';
-- --led <= rx_data;
-- s <= s_wait;
-- end case;
-- end if;
-- end if;
-- end process;
-- proc_tx: process(reset, ps2c_i)
-- variable counter: unsigned(3 downto 0);
-- begin
-- if reset = '1' then
-- idle <= '1';
-- s_tx <= s_wait;
-- state_send <= s_wait;
-- ps2d_out <= 'Z';
-- ps2c_out <= 'Z';
-- led <= (others => '0');
-- elsif rising_edge(ps2c_i) then
-- web_output_write_o <= '0';
-- case s_tx is
-- when s_wait =>
-- idle <= '1';
-- if rx_done = '1' then
-- s_tx <= s_data;
-- tx_data <= rx_data;
-- counter := "0000";
-- idle <= '0';
-- ps2c_out <= '0';
-- state_send <= s_wait;
-- end if;
-- when s_data =>
-- if counter = "0001" then
-- ps2c_out <= 'Z';
-- ps2d_out <= '0';
-- elsif counter > "0001" and counter < "1010" then
-- ps2d_out <= tx_data(0);
-- tx_data <= '0' & tx_data(7 downto 1);
-- elsif counter = "1010" then
-- if ps2d_i = '0' then
-- web_output_data_o <= "00000001";
-- web_output_write_o <= '1';
-- end if;
-- s_tx <= s_done;
-- end if;
-- counter := counter + 1;
-- when s_done =>
-- ps2d_out <= 'Z';
-- ps2c_out <= 'Z';
-- s_tx <= s_wait;
-- end case;
-- end if;
-- end process;
end Behavioral;
|
mit
|
csrhau/sandpit
|
VHDL/single_port_ram/test_ram.vhdl
|
1
|
1442
|
library ieee;
use ieee.std_logic_1164.all;
entity test_ram is
end test_ram;
architecture behavioural of test_ram is
component RAM is
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector(9 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component RAM;
signal clock : std_logic;
signal write_enable : std_logic;
signal address : std_logic_vector(9 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
begin
ramcell : RAM port map (clock, write_enable, address, data_in, data_out);
process
begin
clock <= '0';
wait for 1 ns;
address <= "0000000000";
write_enable <= '1';
data_in <= "01010101";
clock <= '1';
wait for 1 ns;
assert data_out = "00000000"
report "RAM should be zero initialized" severity error;
clock <= '0';
wait for 1 ns;
write_enable <= '0';
data_in <= "11110000";
clock <= '1';
wait for 1 ns;
assert data_out = "01010101"
report "data should have been written and returned" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_out = "01010101"
report "data should not be overwritten with write_enable false" severity error;
wait;
end process;
end behavioural;
|
mit
|
gxliu/ARM-Cortex-M0
|
tb/tb_memory.vhd
|
1
|
2283
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
ENTITY tb_memory IS
END tb_memory;
ARCHITECTURE behavior OF tb_memory IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT memory_no_clk
PORT(
clk : IN std_logic;
write_en : IN std_logic;
addr_1 : IN std_logic_vector(31 downto 0);
addr_2 : IN std_logic_vector(31 downto 0);
data_w2 : IN std_logic_vector(31 downto 0);
data_r1 : OUT std_logic_vector(31 downto 0);
data_r2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal write_en : std_logic := '0';
signal addr_1 : std_logic_vector(31 downto 0) := (others => '0');
signal addr_2 : std_logic_vector(31 downto 0) := (others => '0');
signal data_w2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal data_r1 : std_logic_vector(31 downto 0);
signal data_r2 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: memory_no_clk PORT MAP (
clk => clk,
write_en => write_en,
addr_1 => addr_1,
addr_2 => addr_2,
data_w2 => data_w2,
data_r1 => data_r1,
data_r2 => data_r2
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
addr1_process :process
begin
if unsigned(addr_1) = 7 then
addr_1 <= (others=>'0');
else
addr_1 <= std_logic_vector(unsigned(addr_1) + 1);
end if;
wait for 2*clk_period;
end process;
addr2_process :process
begin
if unsigned(addr_2) = 7 then
addr_2 <= (others=>'0');
else
addr_2 <= std_logic_vector(unsigned(addr_2) + 1);
end if;
wait for 3*clk_period;
end process;
write_en_process :process
begin
write_en <= '1';
wait for 2*clk_period;
write_en <= '0';
wait for 8*clk_period;
end process;
data_process :process
begin
data_w2 <= std_logic_vector(unsigned(data_w2) + 1);
wait for clk_period;
end process;
END;
|
mit
|
lvoudour/arty-uart
|
sim/tb_uart.vhd
|
1
|
5915
|
--------------------------------------------------------------------------------
--
-- UART Loopback Testbench
--
-- Self checking testbench that wires the UART in loopback configuration (Rx
-- data is echoed back to Tx). An ASCII text is transmitted from the external
-- device and the testbench checks that the same text is received by the
-- external device.
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb_uart is
end entity tb_uart;
architecture behv of tb_uart is
------------------------------------------
-- uart_tx
------------------------------------------
-- Emulates an external UART device Tx
-- txdata : Data to transmit
-- tx : Tx data line
-- T_UART : UART period (bit duration)
procedure uart_tx (
variable txdata : in std_logic_vector(7 downto 0);
signal tx : inout std_logic;
constant T_UART : in time) is
begin
tx <= '0'; -- start bit
wait for T_UART;
for i in 0 to 7 loop
tx <= txdata(i);
wait for T_UART;
end loop;
tx <= '1'; -- stop bit
wait for T_UART;
end uart_tx;
------------------------------------------
-- uart_rx
------------------------------------------
-- Emulates an external UART device Rx
-- rx : Rx data line
-- rxdata : Data received
-- T_UART : UART period (bit duration)
procedure uart_rx (
signal rx : in std_logic;
variable rxdata : out std_logic_vector(7 downto 0);
constant T_UART : in time) is
begin
wait until falling_edge(rx);
wait for T_UART/2;
for n in 0 to 7 loop
wait for T_UART;
rxdata(n) := rx;
end loop;
wait for T_UART;
assert (rx = '1') report "Incorrect UART stop bit" severity error;
end uart_rx;
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
constant C_UART_PERIOD : time := 800 ns; -- 1.25 Mbaud
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal tx_i : std_logic := '1';
signal tx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal tx_data_wr_i : std_logic := '0';
signal tx_fifo_full_i : std_logic := '0';
signal rx_i : std_logic := '1';
signal rx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal rx_data_rd_i : std_logic := '0';
signal rx_fifo_empty_i : std_logic := '0';
signal transmitted_text : string(1 to 9) := "TEST_1234";
begin
clk <= not clk after C_CLK_PERIOD/2;
rst <= '1', '0' after 1000 ns;
-- Loopback. Connect rx fifo output to tx fifo input
tx_data_i <= rx_data_i;
-- External device UART transmitter
proc_external_uart_tx:
process
variable txdata : std_logic_vector(7 downto 0) := (others=>'0');
begin
wait until falling_edge(rst);
-- transmit each character of the string (least significant char first)
for n in transmitted_text'range loop
wait for 133 ns; -- wait some arbitrary amount of time
txdata := std_logic_vector(to_unsigned(character'pos(transmitted_text(n)), 8));
uart_tx(txdata, rx_i, C_UART_PERIOD);
end loop;
wait;
end process;
-- Read/Write UART Rx/Tx FIFOs
proc_loopback:
process
begin
wait until falling_edge(rst);
-- Repeat for every character
for n in transmitted_text'range loop
-- wait until rx fifo has some data
if (rx_fifo_empty_i='1') then
wait until rx_fifo_empty_i = '0';
end if;
-- Read pulse
wait until rising_edge(clk);
rx_data_rd_i <= '1';
wait until rising_edge(clk);
rx_data_rd_i <= '0';
-- check if tx fifo is full before writing
-- any data (not really necessary in loopback
-- configuration)
if (tx_fifo_full_i = '1') then
wait until tx_fifo_full_i = '0';
end if;
-- Write pulse
wait until rising_edge(clk);
tx_data_wr_i <= '1';
wait until rising_edge(clk);
tx_data_wr_i <= '0';
end loop;
wait;
end process;
-- External device UART receiver
proc_external_uart_rx:
process
variable rxdata : std_logic_vector(7 downto 0) := (others=>'0');
variable received_text : string(transmitted_text'range);
begin
-- Receive characters and store them in a string
for n in transmitted_text'range loop
uart_rx(tx_i, rxdata, C_UART_PERIOD);
received_text(n) := character'val(to_integer(unsigned(rxdata)));
end loop;
-- Fail simulation if received text is not equal to the transmitted text
assert (received_text = transmitted_text)
report "Received text: " & received_text & " is not equal to trasmitted text: " & transmitted_text
severity failure;
-- All is well. Report success
assert false
report "Successfuly received transmitted text: " & received_text
severity note;
wait;
end process;
------------------------------------------------
-- UART
------------------------------------------------
uart_inst : entity work.uart(rtl)
generic map(
G_BAUD_RATE => 1250000,
G_CLOCK_FREQ => 100.0e6
)
port map(
clk => clk,
rst => rst,
tx_data_in => tx_data_i,
tx_data_wr_in => tx_data_wr_i,
tx_fifo_full_out => tx_fifo_full_i,
tx_out => tx_i,
rx_in => rx_i,
rx_data_rd_in => rx_data_rd_i,
rx_data_out => rx_data_i,
rx_fifo_empty_out => rx_fifo_empty_i
);
end architecture behv;
|
mit
|
PRETgroup/goFB
|
goEFB/out/enforcement_types_WaterBoilerEnforcer.vhdl
|
1
|
668
|
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-14T16:53:23+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package enforcement_types_WaterBoilerEnforcer is
type enforced_signals_WaterBoilerEnforcer is record
--put the enforced signals in here
Pboiler : unsigned(7 downto 0);
Fin : unsigned(7 downto 0);
Fout : unsigned(7 downto 0);
Fop : unsigned(7 downto 0);
Lboiler : unsigned(7 downto 0);
Hboiler : std_logic;
Cin : std_logic;
Vin : unsigned(7 downto 0);
Vop : unsigned(7 downto 0);
Vout : unsigned(7 downto 0);
Aop : std_logic;
end record;
end enforcement_types_WaterBoilerEnforcer;
|
mit
|
csrhau/sandpit
|
VHDL/image_read/pgm_types.vhdl
|
1
|
509
|
library ieee;
use ieee.std_logic_1164.all;
package pgm_types is
subtype pixel is natural range 255 downto 0;
type pixel_array is array(natural range <>, natural range <>) of pixel;
type pixel_array_ptr is access pixel_array;
type pgm_header is record
rows : natural;
cols : natural;
maxval : natural;
end record;
type pgm_image is record
rows : natural;
cols : natural;
maxval : natural;
content : pixel_array_ptr;
end record;
end package pgm_types;
|
mit
|
csrhau/sandpit
|
VHDL/data_types/test_array.vhdl
|
1
|
1476
|
library ieee;
use ieee.std_logic_1164.all;
entity test_array is
end test_array;
architecture behavioural of test_array is
-- This is how to specify unconstrained ranges.
type board1 is array(integer range <>, integer range <>) of integer range 0 to 1;
type board2 is array(5 downto 0, 5 downto 0) of integer range 0 to 1;
-- Can't seem to define board2 in terms of board1 :(.
signal state1 : board1(5 downto 0, 5 downto 0);
signal state2 : board2;
type kB_ram is array(0 to 1023) of std_logic_vector(7 downto 0);
signal initializeme : kB_ram := (others => (others => '1')); -- Nested initialization!
signal blockinit : kB_ram := (0 => "00000000",
1 => "00000001",
2 to 10 => "01010101",
others => (others => '1'));
begin
process
begin
assert initializeme(4) = "11111111"
report "Should have initialized correctly" severity error;
assert blockinit(0) = "00000000"
report "Should have initialized correctly" severity error;
assert blockinit(1) = "00000001"
report "Should have initialized correctly" severity error;
for i in 2 to 10 loop
assert blockinit(i) = "01010101"
report "Should have initialized correctly" severity error;
end loop;
assert blockinit(100) = "11111111"
report "Should have initialized correctly" severity error;
wait;
end process;
end behavioural;
|
mit
|
csrhau/sandpit
|
VHDL/vga_imdisplay/test_vga_rom.vhdl
|
1
|
1947
|
library ieee;
use ieee.std_logic_1164.all;
use work.memory_types.all;
entity test_vga_rom is
end test_vga_rom;
architecture behavioural of test_vga_rom is
component VGA_ROM is
generic (
contents: vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in natural range vga_memory'range;
data : out std_logic_vector(7 downto 0)
);
end component;
signal clock : std_logic;
signal enable : std_logic;
signal address : natural range vga_memory'range;
signal output : std_logic_vector(7 downto 0);
constant test_storage : vga_memory := (
0 => "00000000",
1 => "00000001",
2 => "00000010",
3 => "00000011",
4 => "00000100",
5 => "11110000",
6 => "11110000",
7 => "11110000",
8 => "11110000",
9 => "11110000",
10 => "11110000",
11 => "11110000",
12 => "11110000",
13 => "11110000",
14 => "11110000",
15 => "11110000",
others => "00000000"
);
begin
ROMCELL : VGA_ROM generic map (test_storage)
port map (clock, enable, address, output);
process
begin
enable <= '1';
address <= 0;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000000"
report "result should be 0" severity error;
address <= 1;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000001"
report "result should be 1" severity error;
address <= 2000;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000000"
report "result should be zero" severity error;
enable <= '0';
address <= 1;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000000"
report "result should be 0 when disabled" severity error;
wait;
end process;
end behavioural;
|
mit
|
tuura/fantasi
|
dependencies/accumulator.vhdl
|
1
|
1241
|
-- Generic accumulator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Generic_accumulator IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N downto 0));
END Generic_accumulator;
ARCHITECTURE structural OF Generic_accumulator IS
COMPONENT Generic_register IS
GENERIC (N : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N-1 downto 0));
END COMPONENT;
SIGNAL sum : std_logic_vector(N downto 0);
SIGNAL data_out : std_logic_vector(N downto 0);
BEGIN
sum <= ('0' & DIN) + (data_out);
REG_ACCUMULATOR: Generic_register
GENERIC MAP( N + 1 )
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
DIN => sum,
DOUT => data_out);
DOUT <= data_out;
END structural;
|
mit
|
PRETgroup/goFB
|
examples/goFB_only/vhdl/pc2_conveyor/vhdl/BoxDropper_SIFB.vhd
|
2
|
3268
|
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Basic Function Block for BoxDropper_SIFB
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BoxDropper_SIFB is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
--input events
box_dropper_run_changed_eI : in std_logic := '0';
--input variables
box_dropper_run_I : in std_logic := '0'; --type was BOOL
--special emitted internal vars for I/O
tx_box_dropper_run : out std_logic; --type was BOOL
--for done signal
done : out std_logic
);
end entity;
architecture rtl of BoxDropper_SIFB is
-- Build an enumerated type for the state machine
type state_type is (STATE_Start);
-- Register to hold the current state
signal state : state_type := STATE_Start;
-- signals to store variable sampled on enable
signal box_dropper_run : std_logic := '0'; --register for input
-- signals for enabling algorithms
signal boxdropper_alg_alg_en : std_logic := '0';
signal boxdropper_alg_alg_done : std_logic := '1';
-- signal for algorithm completion
signal AlgorithmsStart : std_logic := '0';
signal AlgorithmsDone : std_logic;
--internal variables
begin
-- Registers for data variables (only updated on relevant events)
process (clk)
begin
if rising_edge(clk) then
if sync = '1' then
if box_dropper_run_changed_eI = '1' then
box_dropper_run <= box_dropper_run_I;
end if;
end if;
end if;
end process;
-- Logic to advance to the next state
process (clk, reset)
begin
if reset = '1' then
state <= STATE_Start;
AlgorithmsStart <= '1';
elsif (rising_edge(clk)) then
if AlgorithmsStart = '1' then --algorithms should be triggered only once via this pulse signal
AlgorithmsStart <= '0';
elsif enable = '1' then
--default values
state <= state;
AlgorithmsStart <= '0';
--next state logic
case state is
when STATE_Start =>
if true then
state <= STATE_Start;
AlgorithmsStart <= '1';
end if;
end case;
end if;
end if;
end process;
-- Event outputs and internal algorithm triggers depend solely on the current state
process (state)
begin
--default values
--algorithms
boxdropper_alg_alg_en <= '0';
case state is
when STATE_Start =>
boxdropper_alg_alg_en <= '1';
end case;
end process;
-- Algorithms process
process(clk)
begin
if rising_edge(clk) then
if AlgorithmsStart = '1' then
if boxdropper_alg_alg_en = '1' then -- Algorithm boxdropper_alg
boxdropper_alg_alg_done <= '0';
end if;
end if;
if boxdropper_alg_alg_done = '0' then -- Algorithm boxdropper_alg
--begin algorithm raw text
tx_box_dropper_run <= box_dropper_run;
boxdropper_alg_alg_done <= '1';
--end algorithm raw text
end if;
end if;
end process;
--Done signal
AlgorithmsDone <= (not AlgorithmsStart) and (not enable) and boxdropper_alg_alg_done;
Done <= AlgorithmsDone;
end rtl;
|
mit
|
csrhau/sandpit
|
VHDL/GOL_simple/board.vhdl
|
1
|
1436
|
library ieee;
use ieee.std_logic_1164.all;
use work.board_config.all;
entity board is
generic (
init_state : board_state
);
port (
clock : in std_logic;
state : out board_state
);
end board;
architecture structural of board is
component cell is
generic (
begin_alive : integer range 0 to 1
);
port (
clock : in std_logic;
nw, nn, ne : in integer range 0 to 1;
ww, ee : in integer range 0 to 1;
sw, ss, se : in integer range 0 to 1;
alive: out integer range 0 to 1
);
end component;
signal state_s : board_state; -- := init_state;
begin
ROW:
for row in 0 to ROWS generate
COL:
for col in 0 to COLS generate
cellx: cell generic map (begin_alive => init_state(row, col))
port map (clock,
state_s((row - 1) mod ROWS, (col - 1) mod COLS), state_s((row - 1) mod ROWS, col), state_s((row - 1) mod ROWS, (col + 1) mod COLS),
state_s(row, (col - 1) mod COLS), state_s(row, (col + 1) mod COLS),
state_s((row + 1) mod ROWS, (col - 1) mod COLS), state_s((row + 1) mod ROWS, col), state_s((row + 1) mod ROWS, (col + 1) mod COLS),
state_s(row, col));
end generate COL; -- COLS
end generate ROW; -- ROWS
state <= state_s;
end structural;
|
mit
|
csrhau/sandpit
|
VHDL/tdma_bus/test_byte_bus.vhdl
|
1
|
1415
|
library ieee;
use ieee.std_logic_1164.all;
entity test_byte_bus is
end test_byte_bus;
architecture behavioural of test_byte_bus is
component byte_bus is
generic (
bus_length : natural
);
port (
clock : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end component byte_bus;
signal clock: std_logic;
signal data_bus : std_logic_vector(7 downto 0);
begin
BBUS: byte_bus generic map(4)
port map (clock, data_bus);
process
begin
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000000"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000001"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000010"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000011"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000000"
report "Writer should cycle back to start" severity error;
wait;
end process;
end behavioural;
|
mit
|
csrhau/sandpit
|
VHDL/vga_bindisplay/init_funcs.vhdl
|
1
|
1779
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
use std.textio.all;
package init_funcs is
function read_file(data_file_name: string) return vga_memory_ptr;
function chr(sl: std_logic) return character;
function str(slv: std_logic_vector) return string;
end package init_funcs;
package body init_funcs is
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function read_file(data_file_name: string) return vga_memory_ptr is
variable state_ptr : vga_memory_ptr;
variable data_line : line;
variable text_line : line;
variable pixel_value: natural range 255 downto 0;
file data_file : text open read_mode is data_file_name;
begin
state_ptr := new vga_memory;
for i in vga_memory'reverse_range loop -- range would operate downto, and reverse the image! (this took 3 hours)
readline(data_file, data_line);
read(data_line, pixel_value);
if pixel_value < 128 then
state_ptr(i) := '0';
else
state_ptr(i) := '1';
end if;
end loop;
return state_ptr;
end function read_file;
end package body init_funcs;
|
mit
|
csrhau/sandpit
|
VHDL/image_read/read_funcs.vhdl
|
1
|
1211
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.pgm_types.all;
package read_funcs is
function read_pgm_image(pgm_file_name: string) return pgm_image;
end package read_funcs;
package body read_funcs is
function read_pgm_image(pgm_file_name: string) return pgm_image is
variable image : pgm_image;
variable int_temp : integer;
variable pgm_line : line;
file pgm_file : text open read_mode is pgm_file_name;
begin
readline(pgm_file, pgm_line); -- HEADER - TODO check it says pgm
readline(pgm_file, pgm_line); -- ROWS COLS
read(pgm_line, image.rows);
read(pgm_line, image.cols);
readline(pgm_file, pgm_line); -- MAXVAL
read(pgm_line, image.maxval);
-- Begin reading actual data
image.content := new pixel_array(image.rows-1 downto 0, image.cols-1 downto 0);
ROW: for r in image.rows-1 downto 0 loop
readline(pgm_file, pgm_line);
COL: for c in image.cols-1 downto 0 loop
read(pgm_line, int_temp);
image.content(r, c) := int_temp;
end loop COL;
end loop ROW;
file_close(pgm_file);
return image;
end function read_pgm_image;
end package body read_funcs;
|
mit
|
gxliu/ARM-Cortex-M0
|
hdl/regfile_no_clk.vhd
|
1
|
1170
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity regfile_no_clk is
port ( clk : in std_logic;
write_en: in std_logic;
addr_r1 : in std_logic_vector (3 downto 0);
addr_r2 : in std_logic_vector (3 downto 0);
addr_w1 : in std_logic_vector (3 downto 0);
data_w1 : in std_logic_vector (31 downto 0);
pc_next : in std_logic_vector (31 downto 0);
data_r1 : out std_logic_vector (31 downto 0);
data_r2 : out std_logic_vector (31 downto 0);
data_pc : out std_logic_vector (31 downto 0));
end regfile_no_clk;
architecture Behavioral of regfile_no_clk is
type type_reg_file is array(15 downto 0) of std_logic_vector(31 downto 0) ;
signal reg_file : type_reg_file := (others => (others => '0'));
begin
write_port : process(clk)
begin
if rising_edge(clk) then
if write_en = '1' then
reg_file(conv_integer(addr_w1)) <= data_w1;
end if;
reg_file(15) <= pc_next;
end if;
end process;
data_r1 <= reg_file(conv_integer(addr_r1));
data_r2 <= reg_file(conv_integer(addr_r2));
data_pc <= reg_file(15);
end Behavioral;
|
mit
|
csrhau/sandpit
|
VHDL/rom/rom.vhdl
|
2
|
550
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
entity ROM is
generic (
contents : memory_16b
);
port (
clock : in std_logic;
address : in std_logic_vector(3 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity ROM;
architecture behavioural of ROM is
constant storage : memory_16b := contents;
begin
process(clock)
begin
if rising_edge(clock) then
data <= storage(to_integer(unsigned(address)));
end if;
end process;
end behavioural;
|
mit
|
csrhau/sandpit
|
VHDL/vga_imdisplay/test_vga_system.vhdl
|
2
|
2495
|
library ieee;
use ieee.std_logic_1164.all;
use work.init_funcs.all;
use std.textio.all;
entity test_vga_system is
end test_vga_system;
architecture behavioural of test_vga_system is
component VGA_system is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
clock : in std_logic; -- 100 MHz Clock
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 1)
);
end component VGA_system;
signal clock : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(2 downto 1);
begin
SYSTEM: VGA_system port map (
clock,
hsync,
vsync,
red,
green,
blue
);
process
variable vsync_holder : std_logic;
variable hsync_holder : std_logic;
variable log_line, data_line : line;
file file_pointer: text is out "vga_log.txt";
begin
for i in 1 to 2000000 loop
vsync_holder := vsync;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Delay2 -> Read
wait for 5 ns;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Read -> Update
wait for 5 ns;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Update -> Delay1
wait for 5 ns;
write(data_line, now); -- write the line.
write(data_line, ':'); -- write the line.
-- Write the hsync
write(data_line, ' ');
write(data_line, chr(hsync)); -- write the line.
-- Write the vsync
write(data_line, ' ');
write(data_line, chr(vsync)); -- write the line.
-- Write the red
write(data_line, ' ');
write(data_line, str(red)); -- write the line.
-- Write the green
write(data_line, ' ');
write(data_line, str(green)); -- write the line.
-- Write the blue
write(data_line, ' ');
write(data_line, str(blue)); -- write the line.
writeline(file_pointer, data_line); -- write the contents into the file.
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Delay1 -> Delay2
wait for 5 ns;
end loop;
wait;
end process;
end behavioural;
|
mit
|
lvoudour/arty-uart
|
src/fifo_srl.vhd
|
1
|
4597
|
--------------------------------------------------------------------------------
--
-- Shift register (SRL) based synchronous FIFO
--
-- Signals:
-- clk : clock
-- rst : synchronous reset (active high)
-- din : data input
-- wr_en : write enable
-- full : FIFO full flag
-- dout : data output
-- rd_en : read enable
-- empty : FIFO empty flag
--
-- Parameters:
-- G_DATA_WIDTH : Bit width of the data input/output
-- G_DEPTH : FIFO depth
--
-- This design takes advantage of the SRL blocks in Xilinx FPGAs. Optimal
-- G_DEPTH is 16 (SRL16) or 32 (SRL32).
--
-- Read/Write:
-- dout is valid 1 clk cycle after rd_en goes high. din is written into the
-- FIFO 1 clk cycle after wr_en goes high.
-- Simultaneous rd/wr operations do not change the state of the FIFO (ie. FIFO
-- will not go empty or full)
--
-- Empty/Full flags
-- At reset empty flag is set high and full low. Empty flag goes low 1 clk cycle
-- after the first wr_en and high after the last valid rd_en. Full goes high 1
-- clk cycle after the last valid wr_en and low after the first rd_en.
-- Any subsequent rd_en/wr_en when empty/full respecively is ignored and FIFO
-- state doesn't change (ie. it stays empty or full)
--
-- Arty FPGA board specific notes:
-- Vivado infers SRL blocks (SRL16 when using the default G_DEPTH=16). Should
-- work for other Xilinx FPGAs as well. Should be slightly faster than an
-- equivalent distributed RAM impelementation for depths up to 32 words. Same
-- type of FIFO can be generated using the Xilinx FIFO generator (if you don't
-- mind the device specific netlist).
--
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity fifo_srl is
generic(
G_DATA_WIDTH : positive := 8;
G_DEPTH : positive := 16
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
wr_en : in std_logic;
full : out std_logic;
dout : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
rd_en : in std_logic;
empty : out std_logic
);
end entity fifo_srl;
architecture rtl of fifo_srl is
constant C_ADDR_WIDTH : natural := natural(ceil(log2(real(G_DEPTH))));
type srl16_array is array (G_DEPTH-1 downto 0) of std_logic_vector (G_DATA_WIDTH-1 downto 0);
signal fifo : srl16_array := (others=>(others=>'0'));
signal ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal inc_ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal dec_ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal empty_r : std_logic := '1';
signal full_r : std_logic := '0';
signal wr_rd : std_logic_vector(1 downto 0) := "00";
begin
wr_rd <= wr_en & rd_en;
inc_ptr <= ptr + 1;
dec_ptr <= ptr - 1;
proc_data:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
ptr <= (others=>'0');
full_r <= '0';
empty_r <= '1';
else
case wr_rd is
-- Read operation
-- Read the data and decrement the pointer if not empty.
-- FIFO is empty if the next pointer decrement reaches zero.
when "01" =>
if (empty_r = '0') then
dout <= fifo(to_integer(dec_ptr));
ptr <= dec_ptr;
end if;
full_r <= '0';
if (dec_ptr = 0) then
empty_r <= '1';
end if;
-- Write operation
-- Write the data and increment the pointer if not full.
-- FIFO is full if the next pointer increment reaches zero.
when "10" =>
if (full_r = '0') then
fifo <= fifo(G_DEPTH-2 downto 0) & din;
ptr <= inc_ptr;
end if;
empty_r <= '0';
if (inc_ptr = 0) then
full_r <= '1';
end if;
-- Simultaneous read/write
-- Read and write data without moving the pointer
when "11" =>
fifo <= fifo(G_DEPTH-2 downto 0) & din;
dout <= fifo(to_integer(dec_ptr));
-- No operation
when others =>
null;
end case;
end if;
end if;
end process;
full <= full_r;
empty <= empty_r;
end architecture rtl;
|
mit
|
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_lock_axi4_read_cntrl.vhd
|
1
|
3160
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_gpio_pack.all;
entity koc_lock_axi4_read_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000"
);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
reg_control : in std_logic_vector(axi_data_width-1 downto 0)
);
end koc_lock_axi4_read_cntrl;
architecture Behavioral of koc_lock_axi4_read_cntrl is
type state_type is (state_wait,state_read);
signal state : state_type := state_wait;
signal axi_arready_buff : std_logic := '0';
signal axi_rvalid_buff : std_logic := '0';
signal axi_araddr_buff : std_logic_vector(axi_address_width-1 downto 0);
begin
axi_arready <= axi_arready_buff;
axi_rvalid <= axi_rvalid_buff;
axi_rresp <= axi_resp_okay;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '0';
state <= state_wait;
else
case state is
when state_wait=>
if axi_arvalid='1' and axi_arready_buff='1' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '1';
state <= state_read;
if axi_araddr=reg_control_offset then
axi_rdata <= reg_control;
else
axi_rdata <= (others=>'0');
end if;
else
axi_arready_buff <= '1';
end if;
when state_read=>
if axi_rvalid_buff='1' and axi_rready='1' then
axi_rvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
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