repo_name
stringlengths 6
79
| path
stringlengths 5
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stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/synth/system_ov7670_controller_0_0.vhd
|
5
|
4423
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_0_0_arch : ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_transform_0_1/ip/affine_block_ieee754_fp_to_uint_0_1/sim/affine_block_ieee754_fp_to_uint_0_1.vhd
|
2
|
3219
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_to_uint:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_to_uint_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END affine_block_ieee754_fp_to_uint_0_1;
ARCHITECTURE affine_block_ieee754_fp_to_uint_0_1_arch OF affine_block_ieee754_fp_to_uint_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_to_uint_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_to_uint IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT ieee754_fp_to_uint;
BEGIN
U0 : ieee754_fp_to_uint
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_ieee754_fp_to_uint_0_1_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.vhdl
|
1
|
1525
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:48:14 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_color_test_0_0 is
Port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_vga_color_test_0_0;
architecture stub of system_vga_color_test_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_color_test,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ipshared/bf57/ov7670_registers.vhd
|
6
|
5235
|
-- Company:
-- Engineer: Mike Field <[email protected]>
--
-- Description: Register settings for the OV7670 Camera (partially from OV7670.c
-- in the Linux Kernel
-- Edited by : Christopher Wilson <[email protected]>
------------------------------------------------------------------------------------
--
-- Notes:
-- 1) Regarding the WITH SELECT Statement:
-- WITH sreg(sel) SELECT
-- finished <= '1' when x"FFFF",
-- '0' when others;
-- This means the transfer is finished the first time sreg ends up as "FFFF",
-- I.E. Need Sequential Addresses in the below case statements
--
-- Common Debug Issues:
--
-- Red Appearing as Green / Green Appearing as Pink
-- Solution: Register Corrections Below
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end ov7670_registers;
architecture Structural of ov7670_registers is
signal sreg : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0) := (others => '0');
begin
command <= sreg;
with sreg select finished <= '1' when x"FFFF", '0' when others;
process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
elsif advance = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
case address is
when x"00" => sreg <= x"1280"; -- COM7 Reset
when x"01" => sreg <= x"1280"; -- COM7 Reset
when x"02" => sreg <= x"1204"; -- COM7 Size & RGB output
when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off
when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off
when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format
when x"07" => sreg <= x"0400"; -- COM1 no CCIR601
when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565
when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window
when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling
when x"0B" => sreg <= x"4f40"; --x"4fb3"; -- MTX1 - colour conversion matrix
when x"0C" => sreg <= x"5034"; --x"50b3"; -- MTX2 - colour conversion matrix
when x"0D" => sreg <= x"510C"; --x"5100"; -- MTX3 - colour conversion matrix
when x"0E" => sreg <= x"5217"; --x"523d"; -- MTX4 - colour conversion matrix
when x"0F" => sreg <= x"5329"; --x"53a7"; -- MTX5 - colour conversion matrix
when x"10" => sreg <= x"5440"; --x"54e4"; -- MTX6 - colour conversion matrix
when x"11" => sreg <= x"581e"; --x"589e"; -- MTXS - Matrix sign and auto contrast
when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust
when x"13" => sreg <= x"1100"; -- CLKRC Enable double clock Prescaler - Fin/(1+1)
when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits)
when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits)
when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP
when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits)
when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits)
when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits
when x"1A" => sreg <= x"0e61"; -- COM5(0x0E) 0x61
when x"1B" => sreg <= x"0f4b"; -- COM6(0x0F) 0x4B
when x"1C" => sreg <= x"1602"; --
when x"1D" => sreg <= x"1e37"; -- MVFP (0x1E) 0x07 -- FLIP AND MIRROR IMAGE 0x3x
when x"1E" => sreg <= x"2102";
when x"1F" => sreg <= x"2291";
when x"20" => sreg <= x"2907";
when x"21" => sreg <= x"330b";
when x"22" => sreg <= x"350b";
when x"23" => sreg <= x"371d";
when x"24" => sreg <= x"3871";
when x"25" => sreg <= x"392a";
when x"26" => sreg <= x"3c78"; -- COM12 (0x3C) 0x78
when x"27" => sreg <= x"4d40";
when x"28" => sreg <= x"4e20";
when x"29" => sreg <= x"6900"; -- GFIX (0x69) 0x00
when x"2A" => sreg <= x"6b4a";
when x"2B" => sreg <= x"7410";
when x"2C" => sreg <= x"8d4f";
when x"2D" => sreg <= x"8e00";
when x"2E" => sreg <= x"8f00";
when x"2F" => sreg <= x"9000";
when x"30" => sreg <= x"9100";
when x"31" => sreg <= x"9600";
when x"32" => sreg <= x"9a00";
when x"33" => sreg <= x"b084";
when x"34" => sreg <= x"b10c";
when x"35" => sreg <= x"b20e";
when x"36" => sreg <= x"b382";
when x"37" => sreg <= x"b80a";
when others => sreg <= x"ffff";
end case;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ipshared/bf57/ov7670_registers.vhd
|
6
|
5235
|
-- Company:
-- Engineer: Mike Field <[email protected]>
--
-- Description: Register settings for the OV7670 Camera (partially from OV7670.c
-- in the Linux Kernel
-- Edited by : Christopher Wilson <[email protected]>
------------------------------------------------------------------------------------
--
-- Notes:
-- 1) Regarding the WITH SELECT Statement:
-- WITH sreg(sel) SELECT
-- finished <= '1' when x"FFFF",
-- '0' when others;
-- This means the transfer is finished the first time sreg ends up as "FFFF",
-- I.E. Need Sequential Addresses in the below case statements
--
-- Common Debug Issues:
--
-- Red Appearing as Green / Green Appearing as Pink
-- Solution: Register Corrections Below
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end ov7670_registers;
architecture Structural of ov7670_registers is
signal sreg : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0) := (others => '0');
begin
command <= sreg;
with sreg select finished <= '1' when x"FFFF", '0' when others;
process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
elsif advance = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
case address is
when x"00" => sreg <= x"1280"; -- COM7 Reset
when x"01" => sreg <= x"1280"; -- COM7 Reset
when x"02" => sreg <= x"1204"; -- COM7 Size & RGB output
when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off
when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off
when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format
when x"07" => sreg <= x"0400"; -- COM1 no CCIR601
when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565
when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window
when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling
when x"0B" => sreg <= x"4f40"; --x"4fb3"; -- MTX1 - colour conversion matrix
when x"0C" => sreg <= x"5034"; --x"50b3"; -- MTX2 - colour conversion matrix
when x"0D" => sreg <= x"510C"; --x"5100"; -- MTX3 - colour conversion matrix
when x"0E" => sreg <= x"5217"; --x"523d"; -- MTX4 - colour conversion matrix
when x"0F" => sreg <= x"5329"; --x"53a7"; -- MTX5 - colour conversion matrix
when x"10" => sreg <= x"5440"; --x"54e4"; -- MTX6 - colour conversion matrix
when x"11" => sreg <= x"581e"; --x"589e"; -- MTXS - Matrix sign and auto contrast
when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust
when x"13" => sreg <= x"1100"; -- CLKRC Enable double clock Prescaler - Fin/(1+1)
when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits)
when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits)
when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP
when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits)
when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits)
when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits
when x"1A" => sreg <= x"0e61"; -- COM5(0x0E) 0x61
when x"1B" => sreg <= x"0f4b"; -- COM6(0x0F) 0x4B
when x"1C" => sreg <= x"1602"; --
when x"1D" => sreg <= x"1e37"; -- MVFP (0x1E) 0x07 -- FLIP AND MIRROR IMAGE 0x3x
when x"1E" => sreg <= x"2102";
when x"1F" => sreg <= x"2291";
when x"20" => sreg <= x"2907";
when x"21" => sreg <= x"330b";
when x"22" => sreg <= x"350b";
when x"23" => sreg <= x"371d";
when x"24" => sreg <= x"3871";
when x"25" => sreg <= x"392a";
when x"26" => sreg <= x"3c78"; -- COM12 (0x3C) 0x78
when x"27" => sreg <= x"4d40";
when x"28" => sreg <= x"4e20";
when x"29" => sreg <= x"6900"; -- GFIX (0x69) 0x00
when x"2A" => sreg <= x"6b4a";
when x"2B" => sreg <= x"7410";
when x"2C" => sreg <= x"8d4f";
when x"2D" => sreg <= x"8e00";
when x"2E" => sreg <= x"8f00";
when x"2F" => sreg <= x"9000";
when x"30" => sreg <= x"9100";
when x"31" => sreg <= x"9600";
when x"32" => sreg <= x"9a00";
when x"33" => sreg <= x"b084";
when x"34" => sreg <= x"b10c";
when x"35" => sreg <= x"b20e";
when x"36" => sreg <= x"b382";
when x"37" => sreg <= x"b80a";
when others => sreg <= x"ffff";
end case;
end if;
end process;
end Structural;
|
mit
|
ashikpoojari/Hardware-Security
|
DES CryptoCore/src/s7.vhd
|
2
|
3965
|
library ieee;
use ieee.std_logic_1164.all;
entity s7 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s7;
architecture behaviour of s7 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
end case;
end process;
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_stub.vhdl
|
1
|
1744
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:41:34 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_zed_hdmi_0_0 -prefix
-- system_zed_hdmi_0_0_ system_zed_hdmi_0_0_stub.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_zed_hdmi_0_0 is
Port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end system_zed_hdmi_0_0;
architecture stub of system_zed_hdmi_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "zed_hdmi,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/zybo_vga/zybo_vga.srcs/sources_1/new/zybo_vga.vhd
|
2
|
1222
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: zybo_vga - Structural
-- Description: Breakout for the vga output on the Zybo
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zybo_vga is
port(
clk : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(15 downto 0);
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end zybo_vga;
architecture Structural of zybo_vga is
signal r : std_logic_vector(4 downto 0) := "00000";
signal g : std_logic_vector(5 downto 0) := "000000";
signal b : std_logic_vector(4 downto 0) := "00000";
begin
process(clk)
begin
if falling_edge(clk) then
if active = '1' then
r <= rgb(15 downto 11);
g <= rgb(10 downto 5);
b <= rgb(4 downto 0);
end if;
end if;
end process;
vga_r <= r;
vga_g <= g;
vga_b <= b;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/video_passthrough_vga/video_passthrough_vga.srcs/sources_1/bd/system/ipshared/ed87/zybo_vga.vhd
|
2
|
1222
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: zybo_vga - Structural
-- Description: Breakout for the vga output on the Zybo
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zybo_vga is
port(
clk : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(15 downto 0);
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end zybo_vga;
architecture Structural of zybo_vga is
signal r : std_logic_vector(4 downto 0) := "00000";
signal g : std_logic_vector(5 downto 0) := "000000";
signal b : std_logic_vector(4 downto 0) := "00000";
begin
process(clk)
begin
if falling_edge(clk) then
if active = '1' then
r <= rgb(15 downto 11);
g <= rgb(10 downto 5);
b <= rgb(4 downto 0);
end if;
end if;
end process;
vga_r <= r;
vga_g <= g;
vga_b <= b;
end Structural;
|
mit
|
SoCdesign/audiomixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/vhdl/axi_hdmi_tx_16b.vhd
|
3
|
11922
|
-- ***************************************************************************
-- ***************************************************************************
-- [email protected] (c) Analog Devices Inc.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_hdmi_tx_16b is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_hdmi_tx_16b;
architecture IMP of axi_hdmi_tx_16b is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_be : in std_logic_vector(7 downto 0);
vdma_last : in std_logic;
vdma_ready : out std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
hdmi_ref_clk => hdmi_ref_clk,
hdmi_clk => hdmi_clk,
hdmi_vsync => hdmi_vsync,
hdmi_hsync => hdmi_hsync,
hdmi_data_e => hdmi_data_e,
hdmi_data => hdmi_data,
vdma_clk => vdma_clk,
vdma_fs => vdma_fs,
vdma_fs_ret => vdma_fs_ret,
vdma_empty => vdma_empty,
vdma_almost_empty => vdma_almost_empty,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_be => M_AXIS_MM2S_TKEEP,
vdma_last => M_AXIS_MM2S_TLAST,
vdma_ready => M_AXIS_MM2S_TREADY,
up_status => up_status,
debug_trigger => debug_trigger,
debug_data => debug_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl
|
1
|
5906
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 is
port (
rgb_888 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 : entity is "rgb565_to_rgb888";
end system_rgb565_to_rgb888_0_0_rgb565_to_rgb888;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 is
begin
\rgb_888_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(5),
Q => rgb_888(5),
R => '0'
);
\rgb_888_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(6),
Q => rgb_888(6),
R => '0'
);
\rgb_888_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(7),
Q => rgb_888(7),
R => '0'
);
\rgb_888_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(8),
Q => rgb_888(8),
R => '0'
);
\rgb_888_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(9),
Q => rgb_888(9),
R => '0'
);
\rgb_888_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(10),
Q => rgb_888(10),
R => '0'
);
\rgb_888_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(11),
Q => rgb_888(11),
R => '0'
);
\rgb_888_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(12),
Q => rgb_888(12),
R => '0'
);
\rgb_888_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(13),
Q => rgb_888(13),
R => '0'
);
\rgb_888_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(14),
Q => rgb_888(14),
R => '0'
);
\rgb_888_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(15),
Q => rgb_888(15),
R => '0'
);
\rgb_888_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(0),
Q => rgb_888(0),
R => '0'
);
\rgb_888_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(1),
Q => rgb_888(1),
R => '0'
);
\rgb_888_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(2),
Q => rgb_888(2),
R => '0'
);
\rgb_888_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(3),
Q => rgb_888(3),
R => '0'
);
\rgb_888_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(4),
Q => rgb_888(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_0_0 : entity is "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_0_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_0_0;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 20 downto 3 );
begin
rgb_888(23 downto 21) <= \^rgb_888\(18 downto 16);
rgb_888(20 downto 16) <= \^rgb_888\(20 downto 16);
rgb_888(15 downto 14) <= \^rgb_888\(9 downto 8);
rgb_888(13 downto 3) <= \^rgb_888\(13 downto 3);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_rgb565_to_rgb888_0_0_rgb565_to_rgb888
port map (
clk => clk,
rgb_565(15 downto 0) => rgb_565(15 downto 0),
rgb_888(15 downto 13) => \^rgb_888\(18 downto 16),
rgb_888(12 downto 11) => \^rgb_888\(20 downto 19),
rgb_888(10 downto 9) => \^rgb_888\(9 downto 8),
rgb_888(8 downto 5) => \^rgb_888\(13 downto 10),
rgb_888(4 downto 0) => \^rgb_888\(7 downto 3)
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/sim/system_vga_color_test_0_0.vhd
|
6
|
3409
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_color_test:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_color_test_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_color_test_0_0;
ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_color_test IS
GENERIC (
H_SIZE : INTEGER;
V_SIZE : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_color_test;
BEGIN
U0 : vga_color_test
GENERIC MAP (
H_SIZE => 640,
V_SIZE => 480
)
PORT MAP (
clk_25 => clk_25,
xaddr => xaddr,
yaddr => yaddr,
rgb => rgb
);
END system_vga_color_test_0_0_arch;
|
mit
|
SoCdesign/audiomixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/adau1761_audio.vhd
|
1
|
18133
|
------------------------------------------------------------------------------
-- adau1761_audio.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: adau1761_audio.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 20 11:28:03 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library adau1761_audio_v1_00_a;
use adau1761_audio_v1_00_a.user_logic;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity adau1761_audio is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
--AC_SDA : INOUT std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 downto 0);
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : OUT std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity adau1761_audio;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of adau1761_audio is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 2;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal AC_SDA_tmp : std_logic;
signal clk_48_s : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity adau1761_audio_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
clk_100 => clk_100,
clk_48_o => clk_48_s,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
new_sample => new_sample,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
clk_48_o <= clk_48_s;
--AC_SDA_tmp <= AC_SDA_I when AC_SDA_T = '0' else 'Z';
--AC_SDA_O <= AC_SDA_tmp;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/sim/system_vga_pll_0_0.vhd
|
3
|
3216
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_pll:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_pll_0_0 IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END system_vga_pll_0_0;
ARCHITECTURE system_vga_pll_0_0_arch OF system_vga_pll_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_pll_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_pll IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END COMPONENT vga_pll;
BEGIN
U0 : vga_pll
PORT MAP (
clk_100 => clk_100,
clk_50 => clk_50,
clk_25 => clk_25,
clk_12_5 => clk_12_5,
clk_6_25 => clk_6_25
);
END system_vga_pll_0_0_arch;
|
mit
|
SoCdesign/audiomixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/i2s_rx_tx.vhd
|
3
|
6004
|
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity i2s_rx_tx is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port(
-- Global signals
CLK_I : in std_logic;
RST_I : in std_logic;
-- Control signals
START_TX_I : in std_logic;
START_RX_I : in std_logic;
STOP_RX_I : in std_logic;
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0);
-- Data input from user logic
TX_DATA_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0);
OE_S_O : out std_logic;
-- Data output to user logic
RX_DATA_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0);
WE_S_O : out std_logic;
-- I2S Interface signals
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic
);
end i2s_rx_tx;
architecture Behavioral of i2s_rx_tx is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal TxEn : std_logic;
signal RxEn : std_logic;
signal LRCLK_int : std_logic;
signal D_S_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal WE_S_O_int : std_logic;
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component i2s_controller
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port(
CLK_I : in std_logic; -- System clock (100 MHz)
RST_I : in std_logic; -- System reset
BCLK_O : out std_logic; -- Bit Clock
LRCLK_O : out std_logic; -- Frame Clock
SDATA_O : out std_logic; -- Serial Data Output
SDATA_I : in std_logic; -- Serial Data Input
EN_TX_I : in std_logic; -- Enable TX
EN_RX_I : in std_logic; -- Enable RX
OE_S_O : out std_logic; -- Request new Slot Data
WE_S_O : out std_logic; -- Valid Slot Data
D_S_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
D_S_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameters
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0)
);
end component;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Instantiate the I2S transmitter module
------------------------------------------------------------------------
Inst_I2sRxTx: i2s_controller
generic map(
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_MSB_POS => C_MSB_POS,
C_FRM_SYNC => C_FRM_SYNC,
C_LRCLK_POL => C_LRCLK_POL,
C_BCLK_POL => C_BCLK_POL
)
port map(
CLK_I => CLK_I,
RST_I => RST_I,
EN_TX_I => TxEn,
EN_RX_I => RxEn,
OE_S_O => OE_S_O,
WE_S_O => WE_S_O_int,
D_S_I => TX_DATA_I,
D_S_O => D_S_O_int,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_int,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
DIV_RATE_I => DIV_RATE_I,
LRCLK_RATE_I => LRCLK_RATE_I
);
LRCLK_O <= LRCLK_int;
TxEn <= START_TX_I;
------------------------------------------------------------------------
-- Assert receive enable
------------------------------------------------------------------------
RXEN_PROC: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (START_RX_I = '1') then
RxEn <= '1';
elsif (STOP_RX_I = '1') then
RxEn <= '0';
end if;
end if;
end process RXEN_PROC;
------------------------------------------------------------------------
-- Select RX Data
------------------------------------------------------------------------
RX_DATA_SEL: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if(WE_S_O_int = '1') then
RX_DATA_O <= D_S_O_int;
end if;
end if;
end process RX_DATA_SEL;
WE_S_O <= WE_S_O_int;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ipshared/6198/ov7670_vga.vhd
|
6
|
1332
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: ov7670_vga - Structural
-- Description: The ov7670 can produce 8-bits of data - pclk runs two cycles to produce RGB565
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ov7670_vga is
port(
clk_x2 : in std_logic;
active : in std_logic;
data : in std_logic_vector(7 downto 0);
rgb : out std_logic_vector(15 downto 0)
);
end ov7670_vga;
architecture Structural of ov7670_vga is
signal data_pair : std_logic_vector(15 downto 0);
signal cycle : std_logic := '0';
begin
process(clk_x2)
begin
if rising_edge(clk_x2) then
if active = '0' then
cycle <= '0';
else
if cycle = '0' then
data_pair(7 downto 0) <= data;
cycle <= '1';
else
data_pair(15 downto 8) <= data;
cycle <= '0';
end if;
end if;
end if;
if falling_edge(clk_x2) and cycle = '1' then
rgb <= data_pair;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/ov7670_vga/ov7670_vga.srcs/sources_1/new/ov7670_vga.vhd
|
6
|
1332
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: ov7670_vga - Structural
-- Description: The ov7670 can produce 8-bits of data - pclk runs two cycles to produce RGB565
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ov7670_vga is
port(
clk_x2 : in std_logic;
active : in std_logic;
data : in std_logic_vector(7 downto 0);
rgb : out std_logic_vector(15 downto 0)
);
end ov7670_vga;
architecture Structural of ov7670_vga is
signal data_pair : std_logic_vector(15 downto 0);
signal cycle : std_logic := '0';
begin
process(clk_x2)
begin
if rising_edge(clk_x2) then
if active = '0' then
cycle <= '0';
else
if cycle = '0' then
data_pair(7 downto 0) <= data;
cycle <= '1';
else
data_pair(15 downto 8) <= data;
cycle <= '0';
end if;
end if;
end if;
if falling_edge(clk_x2) and cycle = '1' then
rgb <= data_pair;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.vhdl
|
1
|
1571
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 18 23:18:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.vhdl
-- Design : system_xlconstant_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xlconstant_0_0 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_xlconstant_0_0 : entity is "yes";
end system_xlconstant_0_0;
architecture STRUCTURE of system_xlconstant_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
dout(0) <= \<const1>\;
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/synth/system_rgb888_to_g8_0_0.vhd
|
4
|
3886
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_g8:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_g8_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_rgb888_to_g8_0_0;
ARCHITECTURE system_rgb888_to_g8_0_0_arch OF system_rgb888_to_g8_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_g8_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_g8 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT rgb888_to_g8;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb888_to_g8_0_0_arch: ARCHITECTURE IS "rgb888_to_g8,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb888_to_g8_0_0_arch : ARCHITECTURE IS "system_rgb888_to_g8_0_0,rgb888_to_g8,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb888_to_g8_0_0_arch: ARCHITECTURE IS "system_rgb888_to_g8_0_0,rgb888_to_g8,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb888_to_g8,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb888_to_g8
PORT MAP (
clk => clk,
rgb888 => rgb888,
g8 => g8
);
END system_rgb888_to_g8_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/arctan/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
|
3
|
142619
|
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`protect end_protected
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_rotation_generator_0_0/system_affine_rotation_generator_0_0_sim_netlist.vhdl
|
1
|
165007
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 14:24:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_rotation_generator_0_0/system_affine_rotation_generator_0_0_sim_netlist.vhdl
-- Design : system_affine_rotation_generator_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_affine_rotation_generator_0_0_affine_rotation_generator is
port (
a00 : out STD_LOGIC_VECTOR ( 26 downto 0 );
a01 : out STD_LOGIC_VECTOR ( 29 downto 0 );
reset : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_affine_rotation_generator_0_0_affine_rotation_generator : entity is "affine_rotation_generator";
end system_affine_rotation_generator_0_0_affine_rotation_generator;
architecture STRUCTURE of system_affine_rotation_generator_0_0_affine_rotation_generator is
signal \^a01\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \a01[0]_i_1_n_0\ : STD_LOGIC;
signal \a01[10]_i_1_n_0\ : STD_LOGIC;
signal \a01[11]_i_1_n_0\ : STD_LOGIC;
signal \a01[12]_i_1_n_0\ : STD_LOGIC;
signal \a01[13]_i_1_n_0\ : STD_LOGIC;
signal \a01[14]_i_1_n_0\ : STD_LOGIC;
signal \a01[15]_i_1_n_0\ : STD_LOGIC;
signal \a01[16]_i_1_n_0\ : STD_LOGIC;
signal \a01[17]_i_1_n_0\ : STD_LOGIC;
signal \a01[18]_i_1_n_0\ : STD_LOGIC;
signal \a01[19]_i_1_n_0\ : STD_LOGIC;
signal \a01[1]_i_1_n_0\ : STD_LOGIC;
signal \a01[20]_i_1_n_0\ : STD_LOGIC;
signal \a01[21]_i_1_n_0\ : STD_LOGIC;
signal \a01[22]_i_1_n_0\ : STD_LOGIC;
signal \a01[23]_i_1_n_0\ : STD_LOGIC;
signal \a01[24]_i_1_n_0\ : STD_LOGIC;
signal \a01[25]_i_1_n_0\ : STD_LOGIC;
signal \a01[25]_i_2_n_0\ : STD_LOGIC;
signal \a01[25]_i_3_n_0\ : STD_LOGIC;
signal \a01[25]_i_4_n_0\ : STD_LOGIC;
signal \a01[25]_i_5_n_0\ : STD_LOGIC;
signal \a01[26]_i_1_n_0\ : STD_LOGIC;
signal \a01[27]_i_1_n_0\ : STD_LOGIC;
signal \a01[28]_i_1_n_0\ : STD_LOGIC;
signal \a01[29]_i_10_n_0\ : STD_LOGIC;
signal \a01[29]_i_11_n_0\ : STD_LOGIC;
signal \a01[29]_i_12_n_0\ : STD_LOGIC;
signal \a01[29]_i_1_n_0\ : STD_LOGIC;
signal \a01[29]_i_2_n_0\ : STD_LOGIC;
signal \a01[29]_i_3_n_0\ : STD_LOGIC;
signal \a01[29]_i_4_n_0\ : STD_LOGIC;
signal \a01[29]_i_5_n_0\ : STD_LOGIC;
signal \a01[29]_i_6_n_0\ : STD_LOGIC;
signal \a01[29]_i_7_n_0\ : STD_LOGIC;
signal \a01[29]_i_8_n_0\ : STD_LOGIC;
signal \a01[29]_i_9_n_0\ : STD_LOGIC;
signal \a01[2]_i_1_n_0\ : STD_LOGIC;
signal \a01[3]_i_1_n_0\ : STD_LOGIC;
signal \a01[4]_i_1_n_0\ : STD_LOGIC;
signal \a01[5]_i_1_n_0\ : STD_LOGIC;
signal \a01[6]_i_1_n_0\ : STD_LOGIC;
signal \a01[7]_i_1_n_0\ : STD_LOGIC;
signal \a01[8]_i_1_n_0\ : STD_LOGIC;
signal \a01[9]_i_1_n_0\ : STD_LOGIC;
signal angle : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \angle1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \angle1_carry__0_n_0\ : STD_LOGIC;
signal \angle1_carry__0_n_1\ : STD_LOGIC;
signal \angle1_carry__0_n_2\ : STD_LOGIC;
signal \angle1_carry__0_n_3\ : STD_LOGIC;
signal \angle1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \angle1_carry__1_n_0\ : STD_LOGIC;
signal \angle1_carry__1_n_1\ : STD_LOGIC;
signal \angle1_carry__1_n_2\ : STD_LOGIC;
signal \angle1_carry__1_n_3\ : STD_LOGIC;
signal \angle1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \angle1_carry__2_n_0\ : STD_LOGIC;
signal \angle1_carry__2_n_1\ : STD_LOGIC;
signal \angle1_carry__2_n_2\ : STD_LOGIC;
signal \angle1_carry__2_n_3\ : STD_LOGIC;
signal angle1_carry_i_1_n_0 : STD_LOGIC;
signal angle1_carry_i_2_n_0 : STD_LOGIC;
signal angle1_carry_i_3_n_0 : STD_LOGIC;
signal angle1_carry_i_4_n_0 : STD_LOGIC;
signal angle1_carry_i_5_n_0 : STD_LOGIC;
signal angle1_carry_n_0 : STD_LOGIC;
signal angle1_carry_n_1 : STD_LOGIC;
signal angle1_carry_n_2 : STD_LOGIC;
signal angle1_carry_n_3 : STD_LOGIC;
signal \angle2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__0_n_0\ : STD_LOGIC;
signal \angle2_carry__0_n_1\ : STD_LOGIC;
signal \angle2_carry__0_n_2\ : STD_LOGIC;
signal \angle2_carry__0_n_3\ : STD_LOGIC;
signal \angle2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__1_n_0\ : STD_LOGIC;
signal \angle2_carry__1_n_1\ : STD_LOGIC;
signal \angle2_carry__1_n_2\ : STD_LOGIC;
signal \angle2_carry__1_n_3\ : STD_LOGIC;
signal \angle2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__2_n_0\ : STD_LOGIC;
signal \angle2_carry__2_n_1\ : STD_LOGIC;
signal \angle2_carry__2_n_2\ : STD_LOGIC;
signal \angle2_carry__2_n_3\ : STD_LOGIC;
signal \angle2_carry__3_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__3_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__3_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__3_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__3_n_0\ : STD_LOGIC;
signal \angle2_carry__3_n_1\ : STD_LOGIC;
signal \angle2_carry__3_n_2\ : STD_LOGIC;
signal \angle2_carry__3_n_3\ : STD_LOGIC;
signal \angle2_carry__4_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__4_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__4_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__4_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__4_n_0\ : STD_LOGIC;
signal \angle2_carry__4_n_1\ : STD_LOGIC;
signal \angle2_carry__4_n_2\ : STD_LOGIC;
signal \angle2_carry__4_n_3\ : STD_LOGIC;
signal \angle2_carry__5_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__5_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__5_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__5_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__5_n_0\ : STD_LOGIC;
signal \angle2_carry__5_n_1\ : STD_LOGIC;
signal \angle2_carry__5_n_2\ : STD_LOGIC;
signal \angle2_carry__5_n_3\ : STD_LOGIC;
signal \angle2_carry__6_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__6_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__6_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__6_n_2\ : STD_LOGIC;
signal \angle2_carry__6_n_3\ : STD_LOGIC;
signal angle2_carry_i_1_n_0 : STD_LOGIC;
signal angle2_carry_i_2_n_0 : STD_LOGIC;
signal angle2_carry_i_3_n_0 : STD_LOGIC;
signal angle2_carry_i_4_n_0 : STD_LOGIC;
signal angle2_carry_n_0 : STD_LOGIC;
signal angle2_carry_n_1 : STD_LOGIC;
signal angle2_carry_n_2 : STD_LOGIC;
signal angle2_carry_n_3 : STD_LOGIC;
signal \angle[10]_i_1_n_0\ : STD_LOGIC;
signal \angle[11]_i_1_n_0\ : STD_LOGIC;
signal \angle[12]_i_1_n_0\ : STD_LOGIC;
signal \angle[13]_i_1_n_0\ : STD_LOGIC;
signal \angle[14]_i_1_n_0\ : STD_LOGIC;
signal \angle[15]_i_1_n_0\ : STD_LOGIC;
signal \angle[16]_i_1_n_0\ : STD_LOGIC;
signal \angle[17]_i_1_n_0\ : STD_LOGIC;
signal \angle[18]_i_1_n_0\ : STD_LOGIC;
signal \angle[19]_i_1_n_0\ : STD_LOGIC;
signal \angle[1]_i_1_n_0\ : STD_LOGIC;
signal \angle[20]_i_1_n_0\ : STD_LOGIC;
signal \angle[21]_i_1_n_0\ : STD_LOGIC;
signal \angle[22]_i_1_n_0\ : STD_LOGIC;
signal \angle[23]_i_1_n_0\ : STD_LOGIC;
signal \angle[24]_i_1_n_0\ : STD_LOGIC;
signal \angle[25]_i_1_n_0\ : STD_LOGIC;
signal \angle[26]_i_1_n_0\ : STD_LOGIC;
signal \angle[27]_i_1_n_0\ : STD_LOGIC;
signal \angle[28]_i_1_n_0\ : STD_LOGIC;
signal \angle[29]_i_1_n_0\ : STD_LOGIC;
signal \angle[2]_i_1_n_0\ : STD_LOGIC;
signal \angle[30]_i_1_n_0\ : STD_LOGIC;
signal \angle[31]_i_1_n_0\ : STD_LOGIC;
signal \angle[3]_i_1_n_0\ : STD_LOGIC;
signal \angle[4]_i_1_n_0\ : STD_LOGIC;
signal \angle[5]_i_1_n_0\ : STD_LOGIC;
signal \angle[6]_i_1_n_0\ : STD_LOGIC;
signal \angle[7]_i_1_n_0\ : STD_LOGIC;
signal \angle[8]_i_1_n_0\ : STD_LOGIC;
signal \angle[9]_i_1_n_0\ : STD_LOGIC;
signal \cosine[0]_i_1_n_0\ : STD_LOGIC;
signal \cosine[10]_i_1_n_0\ : STD_LOGIC;
signal \cosine[10]_i_2_n_0\ : STD_LOGIC;
signal \cosine[10]_i_3_n_0\ : STD_LOGIC;
signal \cosine[10]_i_4_n_0\ : STD_LOGIC;
signal \cosine[11]_i_1_n_0\ : STD_LOGIC;
signal \cosine[12]_i_1_n_0\ : STD_LOGIC;
signal \cosine[12]_i_2_n_0\ : STD_LOGIC;
signal \cosine[12]_i_3_n_0\ : STD_LOGIC;
signal \cosine[13]_i_1_n_0\ : STD_LOGIC;
signal \cosine[14]_i_1_n_0\ : STD_LOGIC;
signal \cosine[14]_i_2_n_0\ : STD_LOGIC;
signal \cosine[14]_i_3_n_0\ : STD_LOGIC;
signal \cosine[14]_i_4_n_0\ : STD_LOGIC;
signal \cosine[15]_i_1_n_0\ : STD_LOGIC;
signal \cosine[16]_i_1_n_0\ : STD_LOGIC;
signal \cosine[17]_i_1_n_0\ : STD_LOGIC;
signal \cosine[18]_i_1_n_0\ : STD_LOGIC;
signal \cosine[19]_i_10_n_0\ : STD_LOGIC;
signal \cosine[19]_i_11_n_0\ : STD_LOGIC;
signal \cosine[19]_i_12_n_0\ : STD_LOGIC;
signal \cosine[19]_i_1_n_0\ : STD_LOGIC;
signal \cosine[19]_i_2_n_0\ : STD_LOGIC;
signal \cosine[19]_i_3_n_0\ : STD_LOGIC;
signal \cosine[19]_i_4_n_0\ : STD_LOGIC;
signal \cosine[19]_i_5_n_0\ : STD_LOGIC;
signal \cosine[19]_i_6_n_0\ : STD_LOGIC;
signal \cosine[19]_i_7_n_0\ : STD_LOGIC;
signal \cosine[19]_i_8_n_0\ : STD_LOGIC;
signal \cosine[19]_i_9_n_0\ : STD_LOGIC;
signal \cosine[1]_i_1_n_0\ : STD_LOGIC;
signal \cosine[20]_i_1_n_0\ : STD_LOGIC;
signal \cosine[20]_i_2_n_0\ : STD_LOGIC;
signal \cosine[21]_i_1_n_0\ : STD_LOGIC;
signal \cosine[22]_i_10_n_0\ : STD_LOGIC;
signal \cosine[22]_i_11_n_0\ : STD_LOGIC;
signal \cosine[22]_i_12_n_0\ : STD_LOGIC;
signal \cosine[22]_i_13_n_0\ : STD_LOGIC;
signal \cosine[22]_i_14_n_0\ : STD_LOGIC;
signal \cosine[22]_i_15_n_0\ : STD_LOGIC;
signal \cosine[22]_i_1_n_0\ : STD_LOGIC;
signal \cosine[22]_i_2_n_0\ : STD_LOGIC;
signal \cosine[22]_i_3_n_0\ : STD_LOGIC;
signal \cosine[22]_i_4_n_0\ : STD_LOGIC;
signal \cosine[22]_i_5_n_0\ : STD_LOGIC;
signal \cosine[22]_i_6_n_0\ : STD_LOGIC;
signal \cosine[22]_i_7_n_0\ : STD_LOGIC;
signal \cosine[22]_i_8_n_0\ : STD_LOGIC;
signal \cosine[22]_i_9_n_0\ : STD_LOGIC;
signal \cosine[23]_i_1_n_0\ : STD_LOGIC;
signal \cosine[23]_i_2_n_0\ : STD_LOGIC;
signal \cosine[23]_i_3_n_0\ : STD_LOGIC;
signal \cosine[24]_i_1_n_0\ : STD_LOGIC;
signal \cosine[24]_i_2_n_0\ : STD_LOGIC;
signal \cosine[24]_i_3_n_0\ : STD_LOGIC;
signal \cosine[24]_i_4_n_0\ : STD_LOGIC;
signal \cosine[24]_i_5_n_0\ : STD_LOGIC;
signal \cosine[24]_i_6_n_0\ : STD_LOGIC;
signal \cosine[24]_i_7_n_0\ : STD_LOGIC;
signal \cosine[24]_i_8_n_0\ : STD_LOGIC;
signal \cosine[24]_i_9_n_0\ : STD_LOGIC;
signal \cosine[25]_i_1_n_0\ : STD_LOGIC;
signal \cosine[25]_i_2_n_0\ : STD_LOGIC;
signal \cosine[25]_i_3_n_0\ : STD_LOGIC;
signal \cosine[25]_i_4_n_0\ : STD_LOGIC;
signal \cosine[25]_i_5_n_0\ : STD_LOGIC;
signal \cosine[25]_i_6_n_0\ : STD_LOGIC;
signal \cosine[29]_i_10_n_0\ : STD_LOGIC;
signal \cosine[29]_i_11_n_0\ : STD_LOGIC;
signal \cosine[29]_i_12_n_0\ : STD_LOGIC;
signal \cosine[29]_i_13_n_0\ : STD_LOGIC;
signal \cosine[29]_i_14_n_0\ : STD_LOGIC;
signal \cosine[29]_i_15_n_0\ : STD_LOGIC;
signal \cosine[29]_i_16_n_0\ : STD_LOGIC;
signal \cosine[29]_i_17_n_0\ : STD_LOGIC;
signal \cosine[29]_i_18_n_0\ : STD_LOGIC;
signal \cosine[29]_i_19_n_0\ : STD_LOGIC;
signal \cosine[29]_i_20_n_0\ : STD_LOGIC;
signal \cosine[29]_i_21_n_0\ : STD_LOGIC;
signal \cosine[29]_i_22_n_0\ : STD_LOGIC;
signal \cosine[29]_i_23_n_0\ : STD_LOGIC;
signal \cosine[29]_i_24_n_0\ : STD_LOGIC;
signal \cosine[29]_i_25_n_0\ : STD_LOGIC;
signal \cosine[29]_i_26_n_0\ : STD_LOGIC;
signal \cosine[29]_i_27_n_0\ : STD_LOGIC;
signal \cosine[29]_i_28_n_0\ : STD_LOGIC;
signal \cosine[29]_i_29_n_0\ : STD_LOGIC;
signal \cosine[29]_i_2_n_0\ : STD_LOGIC;
signal \cosine[29]_i_30_n_0\ : STD_LOGIC;
signal \cosine[29]_i_31_n_0\ : STD_LOGIC;
signal \cosine[29]_i_32_n_0\ : STD_LOGIC;
signal \cosine[29]_i_33_n_0\ : STD_LOGIC;
signal \cosine[29]_i_34_n_0\ : STD_LOGIC;
signal \cosine[29]_i_35_n_0\ : STD_LOGIC;
signal \cosine[29]_i_3_n_0\ : STD_LOGIC;
signal \cosine[29]_i_4_n_0\ : STD_LOGIC;
signal \cosine[29]_i_5_n_0\ : STD_LOGIC;
signal \cosine[29]_i_6_n_0\ : STD_LOGIC;
signal \cosine[29]_i_7_n_0\ : STD_LOGIC;
signal \cosine[29]_i_8_n_0\ : STD_LOGIC;
signal \cosine[29]_i_9_n_0\ : STD_LOGIC;
signal \cosine[2]_i_1_n_0\ : STD_LOGIC;
signal \cosine[3]_i_1_n_0\ : STD_LOGIC;
signal \cosine[4]_i_1_n_0\ : STD_LOGIC;
signal \cosine[4]_i_2_n_0\ : STD_LOGIC;
signal \cosine[4]_i_3_n_0\ : STD_LOGIC;
signal \cosine[5]_i_1_n_0\ : STD_LOGIC;
signal \cosine[6]_i_1_n_0\ : STD_LOGIC;
signal \cosine[6]_i_2_n_0\ : STD_LOGIC;
signal \cosine[7]_i_1_n_0\ : STD_LOGIC;
signal \cosine[7]_i_2_n_0\ : STD_LOGIC;
signal \cosine[7]_i_3_n_0\ : STD_LOGIC;
signal \cosine[7]_i_4_n_0\ : STD_LOGIC;
signal \cosine[7]_i_5_n_0\ : STD_LOGIC;
signal \cosine[8]_i_1_n_0\ : STD_LOGIC;
signal \cosine[8]_i_2_n_0\ : STD_LOGIC;
signal \cosine[8]_i_3_n_0\ : STD_LOGIC;
signal \cosine[9]_i_1_n_0\ : STD_LOGIC;
signal \cosine[9]_i_2_n_0\ : STD_LOGIC;
signal \cosine[9]_i_3_n_0\ : STD_LOGIC;
signal \cosine[9]_i_4_n_0\ : STD_LOGIC;
signal \cosine[9]_i_5_n_0\ : STD_LOGIC;
signal \cosine[9]_i_6_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__1_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__1_n_1\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__1_n_2\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__2_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__2_n_1\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__2_n_2\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__2_n_3\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \counter[0]_i_1_n_0\ : STD_LOGIC;
signal \counter[0]_i_3_n_0\ : STD_LOGIC;
signal \counter[0]_i_4_n_0\ : STD_LOGIC;
signal \counter[0]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_2_n_0\ : STD_LOGIC;
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_2_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_2_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_2_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_2_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_2_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_2_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal counter_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \i__carry__0_i_10_n_0\ : STD_LOGIC;
signal \i__carry__0_i_11_n_0\ : STD_LOGIC;
signal \i__carry__0_i_12_n_0\ : STD_LOGIC;
signal \i__carry__0_i_13_n_0\ : STD_LOGIC;
signal \i__carry__0_i_14_n_0\ : STD_LOGIC;
signal \i__carry__0_i_15_n_0\ : STD_LOGIC;
signal \i__carry__0_i_16_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1_n_1\ : STD_LOGIC;
signal \i__carry__0_i_1_n_2\ : STD_LOGIC;
signal \i__carry__0_i_1_n_3\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
signal \i__carry__0_i_6_n_0\ : STD_LOGIC;
signal \i__carry__0_i_7_n_0\ : STD_LOGIC;
signal \i__carry__0_i_8_n_0\ : STD_LOGIC;
signal \i__carry__0_i_8_n_1\ : STD_LOGIC;
signal \i__carry__0_i_8_n_2\ : STD_LOGIC;
signal \i__carry__0_i_8_n_3\ : STD_LOGIC;
signal \i__carry__0_i_9_n_0\ : STD_LOGIC;
signal \i__carry__1_i_10_n_0\ : STD_LOGIC;
signal \i__carry__1_i_11_n_0\ : STD_LOGIC;
signal \i__carry__1_i_12_n_0\ : STD_LOGIC;
signal \i__carry__1_i_13_n_0\ : STD_LOGIC;
signal \i__carry__1_i_14_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_1\ : STD_LOGIC;
signal \i__carry__1_i_1_n_2\ : STD_LOGIC;
signal \i__carry__1_i_1_n_3\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_1\ : STD_LOGIC;
signal \i__carry__1_i_2_n_2\ : STD_LOGIC;
signal \i__carry__1_i_2_n_3\ : STD_LOGIC;
signal \i__carry__1_i_3_n_0\ : STD_LOGIC;
signal \i__carry__1_i_4_n_0\ : STD_LOGIC;
signal \i__carry__1_i_5_n_0\ : STD_LOGIC;
signal \i__carry__1_i_6_n_0\ : STD_LOGIC;
signal \i__carry__1_i_7_n_0\ : STD_LOGIC;
signal \i__carry__1_i_8_n_0\ : STD_LOGIC;
signal \i__carry__1_i_9_n_0\ : STD_LOGIC;
signal \i__carry__2_i_10_n_0\ : STD_LOGIC;
signal \i__carry__2_i_11_n_0\ : STD_LOGIC;
signal \i__carry__2_i_12_n_0\ : STD_LOGIC;
signal \i__carry__2_i_13_n_0\ : STD_LOGIC;
signal \i__carry__2_i_14_n_0\ : STD_LOGIC;
signal \i__carry__2_i_15_n_0\ : STD_LOGIC;
signal \i__carry__2_i_16_n_0\ : STD_LOGIC;
signal \i__carry__2_i_1_n_0\ : STD_LOGIC;
signal \i__carry__2_i_2_n_0\ : STD_LOGIC;
signal \i__carry__2_i_3_n_0\ : STD_LOGIC;
signal \i__carry__2_i_4_n_0\ : STD_LOGIC;
signal \i__carry__2_i_4_n_1\ : STD_LOGIC;
signal \i__carry__2_i_4_n_2\ : STD_LOGIC;
signal \i__carry__2_i_4_n_3\ : STD_LOGIC;
signal \i__carry__2_i_5_n_0\ : STD_LOGIC;
signal \i__carry__2_i_6_n_0\ : STD_LOGIC;
signal \i__carry__2_i_7_n_0\ : STD_LOGIC;
signal \i__carry__2_i_8_n_0\ : STD_LOGIC;
signal \i__carry__2_i_9_n_2\ : STD_LOGIC;
signal \i__carry__2_i_9_n_3\ : STD_LOGIC;
signal \i__carry_i_10_n_0\ : STD_LOGIC;
signal \i__carry_i_11_n_0\ : STD_LOGIC;
signal \i__carry_i_12_n_0\ : STD_LOGIC;
signal \i__carry_i_13_n_0\ : STD_LOGIC;
signal \i__carry_i_14_n_0\ : STD_LOGIC;
signal \i__carry_i_15_n_0\ : STD_LOGIC;
signal \i__carry_i_16_n_0\ : STD_LOGIC;
signal \i__carry_i_17_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_1\ : STD_LOGIC;
signal \i__carry_i_1_n_2\ : STD_LOGIC;
signal \i__carry_i_1_n_3\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal \i__carry_i_5_n_0\ : STD_LOGIC;
signal \i__carry_i_6_n_0\ : STD_LOGIC;
signal \i__carry_i_7_n_0\ : STD_LOGIC;
signal \i__carry_i_8_n_0\ : STD_LOGIC;
signal \i__carry_i_9_n_0\ : STD_LOGIC;
signal \i__carry_i_9_n_1\ : STD_LOGIC;
signal \i__carry_i_9_n_2\ : STD_LOGIC;
signal \i__carry_i_9_n_3\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 1 );
signal NLW_angle1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_angle1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_angle1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_angle1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_angle2_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_angle2_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_counter0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter0_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter0_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter0_inferred__0/i__carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_i__carry__2_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_i__carry__2_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \a01[29]_i_11\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \a01[29]_i_6\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \a01[29]_i_9\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \angle[10]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \angle[11]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \angle[12]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \angle[13]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \angle[14]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \angle[15]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \angle[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \angle[17]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \angle[18]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \angle[19]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \angle[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \angle[20]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \angle[21]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \angle[22]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \angle[23]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \angle[24]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \angle[25]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \angle[26]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \angle[27]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \angle[28]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \angle[29]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \angle[2]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \angle[30]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \angle[31]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \angle[3]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \angle[4]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \angle[5]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \angle[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \angle[8]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \angle[9]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cosine[10]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cosine[12]_i_3\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \cosine[14]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cosine[19]_i_10\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \cosine[19]_i_11\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \cosine[19]_i_12\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cosine[19]_i_2\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cosine[19]_i_5\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \cosine[19]_i_7\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \cosine[19]_i_9\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cosine[24]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \cosine[24]_i_5\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \cosine[24]_i_7\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cosine[24]_i_8\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cosine[24]_i_9\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \cosine[29]_i_10\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \cosine[29]_i_11\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cosine[29]_i_13\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \cosine[29]_i_14\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \cosine[29]_i_15\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cosine[29]_i_16\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \cosine[29]_i_17\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cosine[29]_i_18\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \cosine[29]_i_19\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \cosine[29]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \cosine[29]_i_20\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cosine[29]_i_21\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \cosine[29]_i_22\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cosine[29]_i_23\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cosine[29]_i_24\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \cosine[29]_i_25\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cosine[29]_i_26\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cosine[29]_i_27\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \cosine[29]_i_28\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \cosine[29]_i_29\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cosine[29]_i_3\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \cosine[29]_i_30\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cosine[29]_i_31\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cosine[29]_i_32\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cosine[29]_i_33\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \cosine[29]_i_34\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \cosine[29]_i_35\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cosine[29]_i_9\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cosine[4]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \cosine[6]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \cosine[7]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cosine[7]_i_3\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \cosine[7]_i_5\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \cosine[8]_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cosine[9]_i_4\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cosine[9]_i_5\ : label is "soft_lutpair34";
begin
a01(29 downto 0) <= \^a01\(29 downto 0);
\a01[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E291D5F7E6B39180"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(0),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[0]_i_1_n_0\
);
\a01[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1F791A29191E6C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(10),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[10]_i_1_n_0\
);
\a01[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D180F7F7F7E6E6A2"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(11),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[11]_i_1_n_0\
);
\a01[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3A2F7C4F7F7E6C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(12),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[12]_i_1_n_0\
);
\a01[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2B3D5C4A2B3A2A2"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(13),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[13]_i_1_n_0\
);
\a01[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1F780F7C4C48080"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(14),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[14]_i_1_n_0\
);
\a01[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBCBE98A23436102"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[25]_i_4_n_0\,
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \^a01\(15),
O => \a01[15]_i_1_n_0\
);
\a01[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2A2B3C4C4C491A2"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(16),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[16]_i_1_n_0\
);
\a01[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0D580B3C4A2D5E6"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(17),
I3 => \a01[29]_i_3_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[17]_i_1_n_0\
);
\a01[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE269B13DF57FE76"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_4_n_0\,
I3 => \^a01\(18),
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[18]_i_1_n_0\
);
\a01[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2F7C4D5C4F79180"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(19),
I3 => \a01[29]_i_3_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[19]_i_1_n_0\
);
\a01[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2A2A2A2A29191E6"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(1),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[1]_i_1_n_0\
);
\a01[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF37FC74CE46A820"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_4_n_0\,
I3 => \^a01\(20),
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[20]_i_1_n_0\
);
\a01[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD15CE46EC64EC64"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \^a01\(21),
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[25]_i_4_n_0\,
O => \a01[21]_i_1_n_0\
);
\a01[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE36FC74DC54CC44"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \^a01\(22),
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[25]_i_4_n_0\,
O => \a01[22]_i_1_n_0\
);
\a01[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D898101099991111"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[25]_i_4_n_0\,
I3 => \a01[29]_i_4_n_0\,
I4 => \^a01\(23),
I5 => \a01[29]_i_3_n_0\,
O => \a01[23]_i_1_n_0\
);
\a01[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE26EE66EF67EF67"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \^a01\(24),
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[25]_i_4_n_0\,
O => \a01[24]_i_1_n_0\
);
\a01[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF37FF77FE76FF77"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \^a01\(25),
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[25]_i_4_n_0\,
O => \a01[25]_i_1_n_0\
);
\a01[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => \cosine[29]_i_3_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_7_n_0\,
I3 => \cosine[19]_i_5_n_0\,
I4 => \a01[29]_i_6_n_0\,
I5 => \cosine[19]_i_6_n_0\,
O => \a01[25]_i_2_n_0\
);
\a01[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFDFFFF"
)
port map (
I0 => \cosine[29]_i_7_n_0\,
I1 => \cosine[29]_i_3_n_0\,
I2 => \cosine[24]_i_3_n_0\,
I3 => \a01[25]_i_5_n_0\,
I4 => \cosine[19]_i_5_n_0\,
I5 => \cosine[19]_i_6_n_0\,
O => \a01[25]_i_3_n_0\
);
\a01[25]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \a01[29]_i_7_n_0\,
I1 => \cosine[7]_i_5_n_0\,
I2 => \cosine[25]_i_6_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[7]_i_3_n_0\,
O => \a01[25]_i_4_n_0\
);
\a01[25]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(7),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(7),
I5 => \cosine[25]_i_5_n_0\,
O => \a01[25]_i_5_n_0\
);
\a01[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFF5F5"
)
port map (
I0 => \a01[29]_i_2_n_0\,
I1 => \a01[29]_i_3_n_0\,
I2 => \^a01\(26),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_5_n_0\,
O => \a01[26]_i_1_n_0\
);
\a01[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFF5F5"
)
port map (
I0 => \a01[29]_i_2_n_0\,
I1 => \a01[29]_i_3_n_0\,
I2 => \^a01\(27),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_5_n_0\,
O => \a01[27]_i_1_n_0\
);
\a01[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFF5F5"
)
port map (
I0 => \a01[29]_i_2_n_0\,
I1 => \a01[29]_i_3_n_0\,
I2 => \^a01\(28),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_5_n_0\,
O => \a01[28]_i_1_n_0\
);
\a01[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFF5F5"
)
port map (
I0 => \a01[29]_i_2_n_0\,
I1 => \a01[29]_i_3_n_0\,
I2 => \^a01\(29),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_5_n_0\,
O => \a01[29]_i_1_n_0\
);
\a01[29]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \cosine[24]_i_7_n_0\,
I1 => \cosine[24]_i_9_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[25]_i_6_n_0\,
I5 => \cosine[7]_i_5_n_0\,
O => \a01[29]_i_10_n_0\
);
\a01[29]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \cosine[29]_i_7_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_9_n_0\,
I3 => \cosine[29]_i_11_n_0\,
O => \a01[29]_i_11_n_0\
);
\a01[29]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF7FFFFFFFF"
)
port map (
I0 => \cosine[29]_i_30_n_0\,
I1 => \cosine[29]_i_10_n_0\,
I2 => \cosine[24]_i_3_n_0\,
I3 => \cosine[29]_i_17_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[19]_i_5_n_0\,
O => \a01[29]_i_12_n_0\
);
\a01[29]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00040000"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[19]_i_5_n_0\,
I2 => \a01[29]_i_6_n_0\,
I3 => \cosine[29]_i_3_n_0\,
I4 => \cosine[29]_i_7_n_0\,
O => \a01[29]_i_2_n_0\
);
\a01[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \a01[29]_i_7_n_0\,
I1 => \cosine[7]_i_5_n_0\,
I2 => \cosine[25]_i_6_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[29]_i_4_n_0\,
I5 => \cosine[7]_i_3_n_0\,
O => \a01[29]_i_3_n_0\
);
\a01[29]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \a01[29]_i_7_n_0\,
I1 => \cosine[7]_i_5_n_0\,
I2 => \cosine[25]_i_6_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[29]_i_5_n_0\,
I5 => \cosine[7]_i_3_n_0\,
O => \a01[29]_i_4_n_0\
);
\a01[29]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF1FFF1FFF11111"
)
port map (
I0 => \a01[29]_i_8_n_0\,
I1 => \a01[29]_i_9_n_0\,
I2 => \a01[29]_i_7_n_0\,
I3 => \a01[29]_i_10_n_0\,
I4 => \a01[29]_i_11_n_0\,
I5 => \a01[29]_i_12_n_0\,
O => \a01[29]_i_5_n_0\
);
\a01[29]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[29]_i_17_n_0\,
I2 => \cosine[24]_i_3_n_0\,
O => \a01[29]_i_6_n_0\
);
\a01[29]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[9]_i_6_n_0\,
I1 => \cosine[29]_i_14_n_0\,
I2 => \cosine[29]_i_16_n_0\,
I3 => \cosine[24]_i_8_n_0\,
I4 => \cosine[9]_i_5_n_0\,
O => \a01[29]_i_7_n_0\
);
\a01[29]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF7F"
)
port map (
I0 => \cosine[29]_i_30_n_0\,
I1 => \cosine[29]_i_10_n_0\,
I2 => \cosine[19]_i_5_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[29]_i_17_n_0\,
I5 => \cosine[24]_i_3_n_0\,
O => \a01[29]_i_8_n_0\
);
\a01[29]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \cosine[29]_i_9_n_0\,
I1 => \cosine[29]_i_11_n_0\,
I2 => \cosine[29]_i_7_n_0\,
O => \a01[29]_i_9_n_0\
);
\a01[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3D5E691D5C4F7C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(2),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[2]_i_1_n_0\
);
\a01[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0D5B3A2C4F7E6E6"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(3),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[3]_i_1_n_0\
);
\a01[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3E680B3C4F7E6C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(4),
I3 => \a01[29]_i_3_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[4]_i_1_n_0\
);
\a01[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0A2C4D580F7A280"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(5),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[5]_i_1_n_0\
);
\a01[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EDBD2535DDDE5556"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \a01[29]_i_4_n_0\,
I4 => \^a01\(6),
I5 => \a01[25]_i_4_n_0\,
O => \a01[6]_i_1_n_0\
);
\a01[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F391B3A2C4C4A2A2"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(7),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[7]_i_1_n_0\
);
\a01[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2E6B3B3B3E680C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(8),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[8]_i_1_n_0\
);
\a01[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3B39191A2A2C4C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(9),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[9]_i_1_n_0\
);
\a01_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[0]_i_1_n_0\,
Q => \^a01\(0),
R => '0'
);
\a01_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[10]_i_1_n_0\,
Q => \^a01\(10),
R => '0'
);
\a01_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[11]_i_1_n_0\,
Q => \^a01\(11),
R => '0'
);
\a01_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[12]_i_1_n_0\,
Q => \^a01\(12),
R => '0'
);
\a01_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[13]_i_1_n_0\,
Q => \^a01\(13),
R => '0'
);
\a01_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[14]_i_1_n_0\,
Q => \^a01\(14),
R => '0'
);
\a01_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[15]_i_1_n_0\,
Q => \^a01\(15),
R => '0'
);
\a01_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[16]_i_1_n_0\,
Q => \^a01\(16),
R => '0'
);
\a01_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[17]_i_1_n_0\,
Q => \^a01\(17),
R => '0'
);
\a01_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[18]_i_1_n_0\,
Q => \^a01\(18),
R => '0'
);
\a01_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[19]_i_1_n_0\,
Q => \^a01\(19),
R => '0'
);
\a01_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[1]_i_1_n_0\,
Q => \^a01\(1),
R => '0'
);
\a01_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[20]_i_1_n_0\,
Q => \^a01\(20),
R => '0'
);
\a01_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[21]_i_1_n_0\,
Q => \^a01\(21),
R => '0'
);
\a01_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[22]_i_1_n_0\,
Q => \^a01\(22),
R => '0'
);
\a01_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[23]_i_1_n_0\,
Q => \^a01\(23),
R => '0'
);
\a01_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[24]_i_1_n_0\,
Q => \^a01\(24),
R => '0'
);
\a01_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[25]_i_1_n_0\,
Q => \^a01\(25),
R => '0'
);
\a01_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[26]_i_1_n_0\,
Q => \^a01\(26),
R => '0'
);
\a01_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[27]_i_1_n_0\,
Q => \^a01\(27),
R => '0'
);
\a01_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[28]_i_1_n_0\,
Q => \^a01\(28),
R => '0'
);
\a01_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[29]_i_1_n_0\,
Q => \^a01\(29),
R => '0'
);
\a01_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[2]_i_1_n_0\,
Q => \^a01\(2),
R => '0'
);
\a01_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[3]_i_1_n_0\,
Q => \^a01\(3),
R => '0'
);
\a01_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[4]_i_1_n_0\,
Q => \^a01\(4),
R => '0'
);
\a01_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[5]_i_1_n_0\,
Q => \^a01\(5),
R => '0'
);
\a01_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[6]_i_1_n_0\,
Q => \^a01\(6),
R => '0'
);
\a01_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[7]_i_1_n_0\,
Q => \^a01\(7),
R => '0'
);
\a01_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[8]_i_1_n_0\,
Q => \^a01\(8),
R => '0'
);
\a01_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[9]_i_1_n_0\,
Q => \^a01\(9),
R => '0'
);
angle1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => angle1_carry_n_0,
CO(2) => angle1_carry_n_1,
CO(1) => angle1_carry_n_2,
CO(0) => angle1_carry_n_3,
CYINIT => '1',
DI(3) => p_1_in(7),
DI(2) => p_1_in(5),
DI(1) => angle1_carry_i_1_n_0,
DI(0) => '0',
O(3 downto 0) => NLW_angle1_carry_O_UNCONNECTED(3 downto 0),
S(3) => angle1_carry_i_2_n_0,
S(2) => angle1_carry_i_3_n_0,
S(1) => angle1_carry_i_4_n_0,
S(0) => angle1_carry_i_5_n_0
);
\angle1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => angle1_carry_n_0,
CO(3) => \angle1_carry__0_n_0\,
CO(2) => \angle1_carry__0_n_1\,
CO(1) => \angle1_carry__0_n_2\,
CO(0) => \angle1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \angle1_carry__0_i_1_n_0\,
DI(2) => \angle1_carry__0_i_2_n_0\,
DI(1) => \angle1_carry__0_i_3_n_0\,
DI(0) => \angle1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_angle1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \angle1_carry__0_i_5_n_0\,
S(2) => \angle1_carry__0_i_6_n_0\,
S(1) => \angle1_carry__0_i_7_n_0\,
S(0) => \angle1_carry__0_i_8_n_0\
);
\angle1_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(14),
I1 => p_1_in(15),
O => \angle1_carry__0_i_1_n_0\
);
\angle1_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(12),
I1 => p_1_in(13),
O => \angle1_carry__0_i_2_n_0\
);
\angle1_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(10),
I1 => p_1_in(11),
O => \angle1_carry__0_i_3_n_0\
);
\angle1_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(8),
I1 => p_1_in(9),
O => \angle1_carry__0_i_4_n_0\
);
\angle1_carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(14),
I1 => p_1_in(15),
O => \angle1_carry__0_i_5_n_0\
);
\angle1_carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(12),
I1 => p_1_in(13),
O => \angle1_carry__0_i_6_n_0\
);
\angle1_carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(10),
I1 => p_1_in(11),
O => \angle1_carry__0_i_7_n_0\
);
\angle1_carry__0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(8),
I1 => p_1_in(9),
O => \angle1_carry__0_i_8_n_0\
);
\angle1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \angle1_carry__0_n_0\,
CO(3) => \angle1_carry__1_n_0\,
CO(2) => \angle1_carry__1_n_1\,
CO(1) => \angle1_carry__1_n_2\,
CO(0) => \angle1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \angle1_carry__1_i_1_n_0\,
DI(2) => \angle1_carry__1_i_2_n_0\,
DI(1) => \angle1_carry__1_i_3_n_0\,
DI(0) => \angle1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_angle1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \angle1_carry__1_i_5_n_0\,
S(2) => \angle1_carry__1_i_6_n_0\,
S(1) => \angle1_carry__1_i_7_n_0\,
S(0) => \angle1_carry__1_i_8_n_0\
);
\angle1_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(22),
I1 => p_1_in(23),
O => \angle1_carry__1_i_1_n_0\
);
\angle1_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(20),
I1 => p_1_in(21),
O => \angle1_carry__1_i_2_n_0\
);
\angle1_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(18),
I1 => p_1_in(19),
O => \angle1_carry__1_i_3_n_0\
);
\angle1_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(16),
I1 => p_1_in(17),
O => \angle1_carry__1_i_4_n_0\
);
\angle1_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(22),
I1 => p_1_in(23),
O => \angle1_carry__1_i_5_n_0\
);
\angle1_carry__1_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(20),
I1 => p_1_in(21),
O => \angle1_carry__1_i_6_n_0\
);
\angle1_carry__1_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(18),
I1 => p_1_in(19),
O => \angle1_carry__1_i_7_n_0\
);
\angle1_carry__1_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(16),
I1 => p_1_in(17),
O => \angle1_carry__1_i_8_n_0\
);
\angle1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \angle1_carry__1_n_0\,
CO(3) => \angle1_carry__2_n_0\,
CO(2) => \angle1_carry__2_n_1\,
CO(1) => \angle1_carry__2_n_2\,
CO(0) => \angle1_carry__2_n_3\,
CYINIT => '0',
DI(3) => \angle1_carry__2_i_1_n_0\,
DI(2) => \angle1_carry__2_i_2_n_0\,
DI(1) => \angle1_carry__2_i_3_n_0\,
DI(0) => \angle1_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_angle1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \angle1_carry__2_i_5_n_0\,
S(2) => \angle1_carry__2_i_6_n_0\,
S(1) => \angle1_carry__2_i_7_n_0\,
S(0) => \angle1_carry__2_i_8_n_0\
);
\angle1_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(30),
I1 => p_1_in(31),
O => \angle1_carry__2_i_1_n_0\
);
\angle1_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(28),
I1 => p_1_in(29),
O => \angle1_carry__2_i_2_n_0\
);
\angle1_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(26),
I1 => p_1_in(27),
O => \angle1_carry__2_i_3_n_0\
);
\angle1_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(24),
I1 => p_1_in(25),
O => \angle1_carry__2_i_4_n_0\
);
\angle1_carry__2_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(30),
I1 => p_1_in(31),
O => \angle1_carry__2_i_5_n_0\
);
\angle1_carry__2_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(28),
I1 => p_1_in(29),
O => \angle1_carry__2_i_6_n_0\
);
\angle1_carry__2_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(26),
I1 => p_1_in(27),
O => \angle1_carry__2_i_7_n_0\
);
\angle1_carry__2_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(24),
I1 => p_1_in(25),
O => \angle1_carry__2_i_8_n_0\
);
angle1_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in(2),
I1 => p_1_in(3),
O => angle1_carry_i_1_n_0
);
angle1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(6),
I1 => p_1_in(7),
O => angle1_carry_i_2_n_0
);
angle1_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(4),
I1 => p_1_in(5),
O => angle1_carry_i_3_n_0
);
angle1_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(3),
I1 => p_1_in(2),
O => angle1_carry_i_4_n_0
);
angle1_carry_i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(1),
O => angle1_carry_i_5_n_0
);
angle2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => angle2_carry_n_0,
CO(2) => angle2_carry_n_1,
CO(1) => angle2_carry_n_2,
CO(0) => angle2_carry_n_3,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => angle(2),
DI(0) => '0',
O(3 downto 0) => p_1_in(4 downto 1),
S(3) => angle2_carry_i_1_n_0,
S(2) => angle2_carry_i_2_n_0,
S(1) => angle2_carry_i_3_n_0,
S(0) => angle2_carry_i_4_n_0
);
\angle2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => angle2_carry_n_0,
CO(3) => \angle2_carry__0_n_0\,
CO(2) => \angle2_carry__0_n_1\,
CO(1) => \angle2_carry__0_n_2\,
CO(0) => \angle2_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(8 downto 5),
S(3) => \angle2_carry__0_i_1_n_0\,
S(2) => \angle2_carry__0_i_2_n_0\,
S(1) => \angle2_carry__0_i_3_n_0\,
S(0) => \angle2_carry__0_i_4_n_0\
);
\angle2_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(8),
O => \angle2_carry__0_i_1_n_0\
);
\angle2_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(7),
O => \angle2_carry__0_i_2_n_0\
);
\angle2_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(6),
O => \angle2_carry__0_i_3_n_0\
);
\angle2_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(5),
O => \angle2_carry__0_i_4_n_0\
);
\angle2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__0_n_0\,
CO(3) => \angle2_carry__1_n_0\,
CO(2) => \angle2_carry__1_n_1\,
CO(1) => \angle2_carry__1_n_2\,
CO(0) => \angle2_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(12 downto 9),
S(3) => \angle2_carry__1_i_1_n_0\,
S(2) => \angle2_carry__1_i_2_n_0\,
S(1) => \angle2_carry__1_i_3_n_0\,
S(0) => \angle2_carry__1_i_4_n_0\
);
\angle2_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(12),
O => \angle2_carry__1_i_1_n_0\
);
\angle2_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(11),
O => \angle2_carry__1_i_2_n_0\
);
\angle2_carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(10),
O => \angle2_carry__1_i_3_n_0\
);
\angle2_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(9),
O => \angle2_carry__1_i_4_n_0\
);
\angle2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__1_n_0\,
CO(3) => \angle2_carry__2_n_0\,
CO(2) => \angle2_carry__2_n_1\,
CO(1) => \angle2_carry__2_n_2\,
CO(0) => \angle2_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(16 downto 13),
S(3) => \angle2_carry__2_i_1_n_0\,
S(2) => \angle2_carry__2_i_2_n_0\,
S(1) => \angle2_carry__2_i_3_n_0\,
S(0) => \angle2_carry__2_i_4_n_0\
);
\angle2_carry__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(16),
O => \angle2_carry__2_i_1_n_0\
);
\angle2_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(15),
O => \angle2_carry__2_i_2_n_0\
);
\angle2_carry__2_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(14),
O => \angle2_carry__2_i_3_n_0\
);
\angle2_carry__2_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(13),
O => \angle2_carry__2_i_4_n_0\
);
\angle2_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__2_n_0\,
CO(3) => \angle2_carry__3_n_0\,
CO(2) => \angle2_carry__3_n_1\,
CO(1) => \angle2_carry__3_n_2\,
CO(0) => \angle2_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(20 downto 17),
S(3) => \angle2_carry__3_i_1_n_0\,
S(2) => \angle2_carry__3_i_2_n_0\,
S(1) => \angle2_carry__3_i_3_n_0\,
S(0) => \angle2_carry__3_i_4_n_0\
);
\angle2_carry__3_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(20),
O => \angle2_carry__3_i_1_n_0\
);
\angle2_carry__3_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(19),
O => \angle2_carry__3_i_2_n_0\
);
\angle2_carry__3_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(18),
O => \angle2_carry__3_i_3_n_0\
);
\angle2_carry__3_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(17),
O => \angle2_carry__3_i_4_n_0\
);
\angle2_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__3_n_0\,
CO(3) => \angle2_carry__4_n_0\,
CO(2) => \angle2_carry__4_n_1\,
CO(1) => \angle2_carry__4_n_2\,
CO(0) => \angle2_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(24 downto 21),
S(3) => \angle2_carry__4_i_1_n_0\,
S(2) => \angle2_carry__4_i_2_n_0\,
S(1) => \angle2_carry__4_i_3_n_0\,
S(0) => \angle2_carry__4_i_4_n_0\
);
\angle2_carry__4_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(24),
O => \angle2_carry__4_i_1_n_0\
);
\angle2_carry__4_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(23),
O => \angle2_carry__4_i_2_n_0\
);
\angle2_carry__4_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(22),
O => \angle2_carry__4_i_3_n_0\
);
\angle2_carry__4_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(21),
O => \angle2_carry__4_i_4_n_0\
);
\angle2_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__4_n_0\,
CO(3) => \angle2_carry__5_n_0\,
CO(2) => \angle2_carry__5_n_1\,
CO(1) => \angle2_carry__5_n_2\,
CO(0) => \angle2_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(28 downto 25),
S(3) => \angle2_carry__5_i_1_n_0\,
S(2) => \angle2_carry__5_i_2_n_0\,
S(1) => \angle2_carry__5_i_3_n_0\,
S(0) => \angle2_carry__5_i_4_n_0\
);
\angle2_carry__5_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(28),
O => \angle2_carry__5_i_1_n_0\
);
\angle2_carry__5_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(27),
O => \angle2_carry__5_i_2_n_0\
);
\angle2_carry__5_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(26),
O => \angle2_carry__5_i_3_n_0\
);
\angle2_carry__5_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(25),
O => \angle2_carry__5_i_4_n_0\
);
\angle2_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__5_n_0\,
CO(3 downto 2) => \NLW_angle2_carry__6_CO_UNCONNECTED\(3 downto 2),
CO(1) => \angle2_carry__6_n_2\,
CO(0) => \angle2_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_angle2_carry__6_O_UNCONNECTED\(3),
O(2 downto 0) => p_1_in(31 downto 29),
S(3) => '0',
S(2) => \angle2_carry__6_i_1_n_0\,
S(1) => \angle2_carry__6_i_2_n_0\,
S(0) => \angle2_carry__6_i_3_n_0\
);
\angle2_carry__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(31),
O => \angle2_carry__6_i_1_n_0\
);
\angle2_carry__6_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(30),
O => \angle2_carry__6_i_2_n_0\
);
\angle2_carry__6_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(29),
O => \angle2_carry__6_i_3_n_0\
);
angle2_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(4),
O => angle2_carry_i_1_n_0
);
angle2_carry_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(3),
O => angle2_carry_i_2_n_0
);
angle2_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => angle(2),
O => angle2_carry_i_3_n_0
);
angle2_carry_i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(1),
O => angle2_carry_i_4_n_0
);
\angle[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(10),
I1 => \angle1_carry__2_n_0\,
O => \angle[10]_i_1_n_0\
);
\angle[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(11),
I1 => \angle1_carry__2_n_0\,
O => \angle[11]_i_1_n_0\
);
\angle[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(12),
I1 => \angle1_carry__2_n_0\,
O => \angle[12]_i_1_n_0\
);
\angle[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(13),
I1 => \angle1_carry__2_n_0\,
O => \angle[13]_i_1_n_0\
);
\angle[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(14),
I1 => \angle1_carry__2_n_0\,
O => \angle[14]_i_1_n_0\
);
\angle[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(15),
I1 => \angle1_carry__2_n_0\,
O => \angle[15]_i_1_n_0\
);
\angle[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(16),
I1 => \angle1_carry__2_n_0\,
O => \angle[16]_i_1_n_0\
);
\angle[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(17),
I1 => \angle1_carry__2_n_0\,
O => \angle[17]_i_1_n_0\
);
\angle[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(18),
I1 => \angle1_carry__2_n_0\,
O => \angle[18]_i_1_n_0\
);
\angle[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(19),
I1 => \angle1_carry__2_n_0\,
O => \angle[19]_i_1_n_0\
);
\angle[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(1),
I1 => \angle1_carry__2_n_0\,
O => \angle[1]_i_1_n_0\
);
\angle[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(20),
I1 => \angle1_carry__2_n_0\,
O => \angle[20]_i_1_n_0\
);
\angle[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(21),
I1 => \angle1_carry__2_n_0\,
O => \angle[21]_i_1_n_0\
);
\angle[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(22),
I1 => \angle1_carry__2_n_0\,
O => \angle[22]_i_1_n_0\
);
\angle[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(23),
I1 => \angle1_carry__2_n_0\,
O => \angle[23]_i_1_n_0\
);
\angle[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(24),
I1 => \angle1_carry__2_n_0\,
O => \angle[24]_i_1_n_0\
);
\angle[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(25),
I1 => \angle1_carry__2_n_0\,
O => \angle[25]_i_1_n_0\
);
\angle[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(26),
I1 => \angle1_carry__2_n_0\,
O => \angle[26]_i_1_n_0\
);
\angle[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(27),
I1 => \angle1_carry__2_n_0\,
O => \angle[27]_i_1_n_0\
);
\angle[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(28),
I1 => \angle1_carry__2_n_0\,
O => \angle[28]_i_1_n_0\
);
\angle[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(29),
I1 => \angle1_carry__2_n_0\,
O => \angle[29]_i_1_n_0\
);
\angle[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(2),
I1 => \angle1_carry__2_n_0\,
O => \angle[2]_i_1_n_0\
);
\angle[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(30),
I1 => \angle1_carry__2_n_0\,
O => \angle[30]_i_1_n_0\
);
\angle[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(31),
I1 => \angle1_carry__2_n_0\,
O => \angle[31]_i_1_n_0\
);
\angle[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(3),
I1 => \angle1_carry__2_n_0\,
O => \angle[3]_i_1_n_0\
);
\angle[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(4),
I1 => \angle1_carry__2_n_0\,
O => \angle[4]_i_1_n_0\
);
\angle[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(5),
I1 => \angle1_carry__2_n_0\,
O => \angle[5]_i_1_n_0\
);
\angle[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(6),
I1 => \angle1_carry__2_n_0\,
O => \angle[6]_i_1_n_0\
);
\angle[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(7),
I1 => \angle1_carry__2_n_0\,
O => \angle[7]_i_1_n_0\
);
\angle[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(8),
I1 => \angle1_carry__2_n_0\,
O => \angle[8]_i_1_n_0\
);
\angle[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(9),
I1 => \angle1_carry__2_n_0\,
O => \angle[9]_i_1_n_0\
);
\angle_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[10]_i_1_n_0\,
Q => angle(10),
R => reset
);
\angle_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[11]_i_1_n_0\,
Q => angle(11),
R => reset
);
\angle_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[12]_i_1_n_0\,
Q => angle(12),
R => reset
);
\angle_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[13]_i_1_n_0\,
Q => angle(13),
R => reset
);
\angle_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[14]_i_1_n_0\,
Q => angle(14),
R => reset
);
\angle_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[15]_i_1_n_0\,
Q => angle(15),
R => reset
);
\angle_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[16]_i_1_n_0\,
Q => angle(16),
R => reset
);
\angle_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[17]_i_1_n_0\,
Q => angle(17),
R => reset
);
\angle_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[18]_i_1_n_0\,
Q => angle(18),
R => reset
);
\angle_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[19]_i_1_n_0\,
Q => angle(19),
R => reset
);
\angle_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[1]_i_1_n_0\,
Q => angle(1),
R => reset
);
\angle_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[20]_i_1_n_0\,
Q => angle(20),
R => reset
);
\angle_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[21]_i_1_n_0\,
Q => angle(21),
R => reset
);
\angle_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[22]_i_1_n_0\,
Q => angle(22),
R => reset
);
\angle_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[23]_i_1_n_0\,
Q => angle(23),
R => reset
);
\angle_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[24]_i_1_n_0\,
Q => angle(24),
R => reset
);
\angle_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[25]_i_1_n_0\,
Q => angle(25),
R => reset
);
\angle_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[26]_i_1_n_0\,
Q => angle(26),
R => reset
);
\angle_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[27]_i_1_n_0\,
Q => angle(27),
R => reset
);
\angle_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[28]_i_1_n_0\,
Q => angle(28),
R => reset
);
\angle_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[29]_i_1_n_0\,
Q => angle(29),
R => reset
);
\angle_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[2]_i_1_n_0\,
Q => angle(2),
R => reset
);
\angle_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[30]_i_1_n_0\,
Q => angle(30),
R => reset
);
\angle_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[31]_i_1_n_0\,
Q => angle(31),
R => reset
);
\angle_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[3]_i_1_n_0\,
Q => angle(3),
R => reset
);
\angle_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[4]_i_1_n_0\,
Q => angle(4),
R => reset
);
\angle_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[5]_i_1_n_0\,
Q => angle(5),
R => reset
);
\angle_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[6]_i_1_n_0\,
Q => angle(6),
R => reset
);
\angle_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[7]_i_1_n_0\,
Q => angle(7),
R => reset
);
\angle_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[8]_i_1_n_0\,
Q => angle(8),
R => reset
);
\angle_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[9]_i_1_n_0\,
Q => angle(9),
R => reset
);
\cosine[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55520C3600000000"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[25]_i_5_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[25]_i_2_n_0\,
O => \cosine[0]_i_1_n_0\
);
\cosine[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020202000"
)
port map (
I0 => \cosine[10]_i_2_n_0\,
I1 => \cosine[10]_i_3_n_0\,
I2 => \cosine[29]_i_7_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[10]_i_4_n_0\,
I5 => \cosine[29]_i_3_n_0\,
O => \cosine[10]_i_1_n_0\
);
\cosine[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"11441FE4"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[25]_i_4_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
O => \cosine[10]_i_2_n_0\
);
\cosine[10]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[24]_i_3_n_0\,
I2 => \cosine[29]_i_17_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[19]_i_5_n_0\,
O => \cosine[10]_i_3_n_0\
);
\cosine[10]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(6),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(6),
I5 => \cosine[29]_i_4_n_0\,
O => \cosine[10]_i_4_n_0\
);
\cosine[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A37E0"
)
port map (
I0 => \cosine[29]_i_5_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[25]_i_3_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[22]_i_2_n_0\,
O => \cosine[11]_i_1_n_0\
);
\cosine[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF06A6"
)
port map (
I0 => \cosine[25]_i_3_n_0\,
I1 => \cosine[25]_i_4_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[12]_i_2_n_0\,
I5 => \cosine[19]_i_3_n_0\,
O => \cosine[12]_i_1_n_0\
);
\cosine[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFB"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[19]_i_5_n_0\,
I2 => \cosine[29]_i_13_n_0\,
I3 => \cosine[29]_i_17_n_0\,
I4 => \cosine[12]_i_3_n_0\,
O => \cosine[12]_i_2_n_0\
);
\cosine[12]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBAAAA"
)
port map (
I0 => \cosine[24]_i_3_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
O => \cosine[12]_i_3_n_0\
);
\cosine[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF6FFF0FFF4FF14"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[24]_i_5_n_0\,
I4 => \cosine[29]_i_4_n_0\,
I5 => \cosine[25]_i_3_n_0\,
O => \cosine[13]_i_1_n_0\
);
\cosine[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \cosine[14]_i_2_n_0\,
I1 => \cosine[19]_i_6_n_0\,
I2 => \cosine[19]_i_5_n_0\,
I3 => \cosine[14]_i_3_n_0\,
I4 => \cosine[19]_i_3_n_0\,
O => \cosine[14]_i_1_n_0\
);
\cosine[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBAF0044"
)
port map (
I0 => \cosine[25]_i_3_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
O => \cosine[14]_i_2_n_0\
);
\cosine[14]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFABBAAAAA"
)
port map (
I0 => \cosine[14]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_3_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[24]_i_3_n_0\,
O => \cosine[14]_i_3_n_0\
);
\cosine[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(7),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(7),
I5 => \cosine[29]_i_13_n_0\,
O => \cosine[14]_i_4_n_0\
);
\cosine[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBAFFAAEFBEFAAE"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[25]_i_3_n_0\,
O => \cosine[15]_i_1_n_0\
);
\cosine[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000040623F4"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[22]_i_2_n_0\,
O => \cosine[16]_i_1_n_0\
);
\cosine[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFABFBFFFAEEAE"
)
port map (
I0 => \cosine[24]_i_5_n_0\,
I1 => \cosine[25]_i_4_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_3_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[29]_i_5_n_0\,
O => \cosine[17]_i_1_n_0\
);
\cosine[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBABBFEFEEBEE"
)
port map (
I0 => \cosine[24]_i_5_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[29]_i_5_n_0\,
O => \cosine[18]_i_1_n_0\
);
\cosine[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \cosine[19]_i_2_n_0\,
I1 => \cosine[19]_i_3_n_0\,
I2 => \cosine[19]_i_4_n_0\,
I3 => \cosine[19]_i_5_n_0\,
I4 => \cosine[19]_i_6_n_0\,
I5 => \cosine[19]_i_7_n_0\,
O => \cosine[19]_i_1_n_0\
);
\cosine[19]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(11),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(11),
I4 => reset,
O => \cosine[19]_i_10_n_0\
);
\cosine[19]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(8),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(8),
I4 => reset,
O => \cosine[19]_i_11_n_0\
);
\cosine[19]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(9),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(9),
I4 => reset,
O => \cosine[19]_i_12_n_0\
);
\cosine[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4C3C"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[29]_i_5_n_0\,
O => \cosine[19]_i_2_n_0\
);
\cosine[19]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \cosine[19]_i_8_n_0\,
I1 => \cosine[29]_i_14_n_0\,
I2 => \cosine[29]_i_3_n_0\,
O => \cosine[19]_i_3_n_0\
);
\cosine[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEEEEFE"
)
port map (
I0 => \cosine[29]_i_13_n_0\,
I1 => \cosine[29]_i_17_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[24]_i_3_n_0\,
O => \cosine[19]_i_4_n_0\
);
\cosine[19]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[19]_i_9_n_0\,
I1 => \cosine[19]_i_10_n_0\,
I2 => \cosine[19]_i_11_n_0\,
I3 => \cosine[19]_i_12_n_0\,
O => \cosine[19]_i_5_n_0\
);
\cosine[19]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \cosine[29]_i_10_n_0\,
I1 => \cosine[29]_i_30_n_0\,
O => \cosine[19]_i_6_n_0\
);
\cosine[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8C38"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[25]_i_4_n_0\,
O => \cosine[19]_i_7_n_0\
);
\cosine[19]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABBBBAABAAAAA"
)
port map (
I0 => \cosine[29]_i_16_n_0\,
I1 => reset,
I2 => p_1_in(28),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(28),
O => \cosine[19]_i_8_n_0\
);
\cosine[19]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(10),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(10),
I4 => reset,
O => \cosine[19]_i_9_n_0\
);
\cosine[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFBBFEEFEFFABBA"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[29]_i_5_n_0\,
O => \cosine[1]_i_1_n_0\
);
\cosine[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000BBB6"
)
port map (
I0 => \cosine[29]_i_5_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[29]_i_8_n_0\,
I5 => \cosine[20]_i_2_n_0\,
O => \cosine[20]_i_1_n_0\
);
\cosine[20]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFD5"
)
port map (
I0 => \cosine[29]_i_7_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[29]_i_3_n_0\,
O => \cosine[20]_i_2_n_0\
);
\cosine[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004105D7E"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[22]_i_2_n_0\,
O => \cosine[21]_i_1_n_0\
);
\cosine[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0105010105111114"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[25]_i_5_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[29]_i_5_n_0\,
I5 => \cosine[25]_i_4_n_0\,
O => \cosine[22]_i_1_n_0\
);
\cosine[22]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(24),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(24),
I5 => \cosine[29]_i_19_n_0\,
O => \cosine[22]_i_10_n_0\
);
\cosine[22]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(22),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(22),
I5 => \cosine[29]_i_21_n_0\,
O => \cosine[22]_i_11_n_0\
);
\cosine[22]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(26),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(26),
I5 => \cosine[29]_i_29_n_0\,
O => \cosine[22]_i_12_n_0\
);
\cosine[22]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(10),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(10),
I5 => \cosine[19]_i_12_n_0\,
O => \cosine[22]_i_13_n_0\
);
\cosine[22]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(12),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(12),
I5 => \cosine[19]_i_10_n_0\,
O => \cosine[22]_i_14_n_0\
);
\cosine[22]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(8),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(8),
I5 => \cosine[29]_i_17_n_0\,
O => \cosine[22]_i_15_n_0\
);
\cosine[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \cosine[22]_i_3_n_0\,
I1 => \cosine[22]_i_4_n_0\,
I2 => \cosine[22]_i_5_n_0\,
I3 => \cosine[22]_i_6_n_0\,
I4 => \cosine[22]_i_7_n_0\,
I5 => \cosine[22]_i_8_n_0\,
O => \cosine[22]_i_2_n_0\
);
\cosine[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \cosine[22]_i_9_n_0\,
I1 => \cosine[29]_i_14_n_0\,
I2 => \cosine[22]_i_10_n_0\,
I3 => \cosine[22]_i_11_n_0\,
I4 => \cosine[9]_i_6_n_0\,
I5 => \cosine[22]_i_12_n_0\,
O => \cosine[22]_i_3_n_0\
);
\cosine[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[22]_i_13_n_0\,
I1 => \cosine[22]_i_14_n_0\,
I2 => \cosine[24]_i_3_n_0\,
I3 => \cosine[22]_i_15_n_0\,
O => \cosine[22]_i_4_n_0\
);
\cosine[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(18),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(18),
I5 => \cosine[29]_i_25_n_0\,
O => \cosine[22]_i_5_n_0\
);
\cosine[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(20),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(20),
I5 => \cosine[29]_i_23_n_0\,
O => \cosine[22]_i_6_n_0\
);
\cosine[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(14),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(14),
I5 => \cosine[29]_i_35_n_0\,
O => \cosine[22]_i_7_n_0\
);
\cosine[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(16),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(16),
I5 => \cosine[29]_i_33_n_0\,
O => \cosine[22]_i_8_n_0\
);
\cosine[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABBBBAABAAAAA"
)
port map (
I0 => \cosine[29]_i_13_n_0\,
I1 => reset,
I2 => p_1_in(29),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(29),
O => \cosine[22]_i_9_n_0\
);
\cosine[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000001D"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[23]_i_2_n_0\,
I4 => \cosine[23]_i_3_n_0\,
I5 => \cosine[29]_i_3_n_0\,
O => \cosine[23]_i_1_n_0\
);
\cosine[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[29]_i_17_n_0\,
I2 => \cosine[24]_i_3_n_0\,
I3 => \cosine[25]_i_3_n_0\,
I4 => \cosine[19]_i_5_n_0\,
O => \cosine[23]_i_2_n_0\
);
\cosine[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBAAFBFFFFFFFFFF"
)
port map (
I0 => reset,
I1 => p_1_in(6),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(6),
I5 => \cosine[29]_i_7_n_0\,
O => \cosine[23]_i_3_n_0\
);
\cosine[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020202000"
)
port map (
I0 => \cosine[24]_i_3_n_0\,
I1 => \cosine[29]_i_8_n_0\,
I2 => \cosine[29]_i_7_n_0\,
I3 => \cosine[29]_i_6_n_0\,
I4 => \cosine[24]_i_4_n_0\,
I5 => \cosine[29]_i_3_n_0\,
O => \cosine[24]_i_1_n_0\
);
\cosine[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEF0FFFFFFFE"
)
port map (
I0 => \cosine[29]_i_5_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[24]_i_5_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[25]_i_5_n_0\,
O => \cosine[24]_i_2_n_0\
);
\cosine[24]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(1),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(1),
I4 => reset,
O => \cosine[24]_i_3_n_0\
);
\cosine[24]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDFDDDDFFDFFFFF"
)
port map (
I0 => \cosine[29]_i_4_n_0\,
I1 => reset,
I2 => p_1_in(2),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(2),
O => \cosine[24]_i_4_n_0\
);
\cosine[24]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[24]_i_6_n_0\,
I1 => \cosine[24]_i_7_n_0\,
I2 => \cosine[7]_i_5_n_0\,
I3 => \cosine[24]_i_8_n_0\,
I4 => \cosine[24]_i_9_n_0\,
O => \cosine[24]_i_5_n_0\
);
\cosine[24]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[29]_i_14_n_0\,
I1 => \cosine[9]_i_5_n_0\,
I2 => \cosine[29]_i_16_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[9]_i_6_n_0\,
O => \cosine[24]_i_6_n_0\
);
\cosine[24]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[29]_i_35_n_0\,
I1 => \cosine[29]_i_32_n_0\,
I2 => \cosine[19]_i_10_n_0\,
I3 => \cosine[29]_i_34_n_0\,
O => \cosine[24]_i_7_n_0\
);
\cosine[24]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[29]_i_21_n_0\,
I1 => \cosine[29]_i_18_n_0\,
I2 => \cosine[29]_i_23_n_0\,
I3 => \cosine[29]_i_20_n_0\,
O => \cosine[24]_i_8_n_0\
);
\cosine[24]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[29]_i_25_n_0\,
I1 => \cosine[29]_i_22_n_0\,
I2 => \cosine[29]_i_33_n_0\,
I3 => \cosine[29]_i_24_n_0\,
O => \cosine[24]_i_9_n_0\
);
\cosine[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"080AAAAAAAAAAAA8"
)
port map (
I0 => \cosine[25]_i_2_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[25]_i_5_n_0\,
O => \cosine[25]_i_1_n_0\
);
\cosine[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => \cosine[29]_i_7_n_0\,
I1 => \cosine[29]_i_3_n_0\,
I2 => \cosine[25]_i_6_n_0\,
I3 => \cosine[29]_i_17_n_0\,
I4 => \cosine[19]_i_5_n_0\,
I5 => \cosine[19]_i_6_n_0\,
O => \cosine[25]_i_2_n_0\
);
\cosine[25]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(5),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(5),
I4 => reset,
O => \cosine[25]_i_3_n_0\
);
\cosine[25]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(4),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(4),
I4 => reset,
O => \cosine[25]_i_4_n_0\
);
\cosine[25]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(6),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(6),
I4 => reset,
O => \cosine[25]_i_5_n_0\
);
\cosine[25]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \cosine[24]_i_3_n_0\,
I1 => \cosine[25]_i_5_n_0\,
I2 => \cosine[25]_i_3_n_0\,
O => \cosine[25]_i_6_n_0\
);
\cosine[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055150000"
)
port map (
I0 => \cosine[29]_i_3_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[29]_i_6_n_0\,
I4 => \cosine[29]_i_7_n_0\,
I5 => \cosine[29]_i_8_n_0\,
O => p_0_out
);
\cosine[29]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_22_n_0\,
I1 => \cosine[29]_i_23_n_0\,
I2 => \cosine[29]_i_24_n_0\,
I3 => \cosine[29]_i_25_n_0\,
O => \cosine[29]_i_10_n_0\
);
\cosine[29]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_26_n_0\,
I1 => \cosine[29]_i_27_n_0\,
I2 => \cosine[29]_i_28_n_0\,
I3 => \cosine[29]_i_29_n_0\,
O => \cosine[29]_i_11_n_0\
);
\cosine[29]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => \cosine[19]_i_5_n_0\,
I1 => \cosine[29]_i_30_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[24]_i_3_n_0\,
I5 => \cosine[29]_i_31_n_0\,
O => \cosine[29]_i_12_n_0\
);
\cosine[29]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(31),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(31),
I4 => reset,
O => \cosine[29]_i_13_n_0\
);
\cosine[29]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(30),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(30),
I4 => reset,
O => \cosine[29]_i_14_n_0\
);
\cosine[29]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(28),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(28),
I4 => reset,
O => \cosine[29]_i_15_n_0\
);
\cosine[29]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(29),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(29),
I4 => reset,
O => \cosine[29]_i_16_n_0\
);
\cosine[29]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(7),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(7),
I4 => reset,
O => \cosine[29]_i_17_n_0\
);
\cosine[29]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(22),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(22),
I4 => reset,
O => \cosine[29]_i_18_n_0\
);
\cosine[29]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(23),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(23),
I4 => reset,
O => \cosine[29]_i_19_n_0\
);
\cosine[29]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \cosine[29]_i_9_n_0\,
I1 => \cosine[29]_i_10_n_0\,
I2 => \cosine[29]_i_7_n_0\,
I3 => \cosine[29]_i_11_n_0\,
I4 => \cosine[29]_i_12_n_0\,
O => \cosine[29]_i_2_n_0\
);
\cosine[29]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(20),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(20),
I4 => reset,
O => \cosine[29]_i_20_n_0\
);
\cosine[29]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(21),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(21),
I4 => reset,
O => \cosine[29]_i_21_n_0\
);
\cosine[29]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(18),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(18),
I4 => reset,
O => \cosine[29]_i_22_n_0\
);
\cosine[29]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(19),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(19),
I4 => reset,
O => \cosine[29]_i_23_n_0\
);
\cosine[29]_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(16),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(16),
I4 => reset,
O => \cosine[29]_i_24_n_0\
);
\cosine[29]_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(17),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(17),
I4 => reset,
O => \cosine[29]_i_25_n_0\
);
\cosine[29]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(26),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(26),
I4 => reset,
O => \cosine[29]_i_26_n_0\
);
\cosine[29]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(27),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(27),
I4 => reset,
O => \cosine[29]_i_27_n_0\
);
\cosine[29]_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(24),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(24),
I4 => reset,
O => \cosine[29]_i_28_n_0\
);
\cosine[29]_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(25),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(25),
I4 => reset,
O => \cosine[29]_i_29_n_0\
);
\cosine[29]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \cosine[29]_i_11_n_0\,
I1 => \cosine[29]_i_9_n_0\,
O => \cosine[29]_i_3_n_0\
);
\cosine[29]_i_30\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_32_n_0\,
I1 => \cosine[29]_i_33_n_0\,
I2 => \cosine[29]_i_34_n_0\,
I3 => \cosine[29]_i_35_n_0\,
O => \cosine[29]_i_30_n_0\
);
\cosine[29]_i_31\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[29]_i_17_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[25]_i_3_n_0\,
O => \cosine[29]_i_31_n_0\
);
\cosine[29]_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(14),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(14),
I4 => reset,
O => \cosine[29]_i_32_n_0\
);
\cosine[29]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(15),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(15),
I4 => reset,
O => \cosine[29]_i_33_n_0\
);
\cosine[29]_i_34\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(12),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(12),
I4 => reset,
O => \cosine[29]_i_34_n_0\
);
\cosine[29]_i_35\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(13),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(13),
I4 => reset,
O => \cosine[29]_i_35_n_0\
);
\cosine[29]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(3),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(3),
I4 => reset,
O => \cosine[29]_i_4_n_0\
);
\cosine[29]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(2),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(2),
I4 => reset,
O => \cosine[29]_i_5_n_0\
);
\cosine[29]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDFDDDDFFDFFFFF"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => reset,
I2 => p_1_in(6),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(6),
O => \cosine[29]_i_6_n_0\
);
\cosine[29]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_13_n_0\,
I1 => \cosine[29]_i_14_n_0\,
I2 => \cosine[29]_i_15_n_0\,
I3 => \cosine[29]_i_16_n_0\,
O => \cosine[29]_i_7_n_0\
);
\cosine[29]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[24]_i_3_n_0\,
I2 => \cosine[29]_i_17_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[19]_i_5_n_0\,
O => \cosine[29]_i_8_n_0\
);
\cosine[29]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_18_n_0\,
I1 => \cosine[29]_i_19_n_0\,
I2 => \cosine[29]_i_20_n_0\,
I3 => \cosine[29]_i_21_n_0\,
O => \cosine[29]_i_9_n_0\
);
\cosine[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FECEFFEFFEFFFFFE"
)
port map (
I0 => \cosine[25]_i_3_n_0\,
I1 => \cosine[22]_i_2_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[29]_i_4_n_0\,
I5 => \cosine[29]_i_5_n_0\,
O => \cosine[2]_i_1_n_0\
);
\cosine[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100040501051150"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[25]_i_4_n_0\,
O => \cosine[3]_i_1_n_0\
);
\cosine[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \cosine[4]_i_2_n_0\,
I1 => \cosine[19]_i_6_n_0\,
I2 => \cosine[19]_i_5_n_0\,
I3 => \cosine[4]_i_3_n_0\,
I4 => \cosine[29]_i_3_n_0\,
I5 => \cosine[29]_i_7_n_0\,
O => \cosine[4]_i_1_n_0\
);
\cosine[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF331D0C"
)
port map (
I0 => \cosine[25]_i_3_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[29]_i_4_n_0\,
O => \cosine[4]_i_2_n_0\
);
\cosine[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEAEAAA"
)
port map (
I0 => \cosine[29]_i_17_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[24]_i_3_n_0\,
O => \cosine[4]_i_3_n_0\
);
\cosine[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00150514"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[29]_i_4_n_0\,
O => \cosine[5]_i_1_n_0\
);
\cosine[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFAFFFFFFFF"
)
port map (
I0 => \cosine[24]_i_3_n_0\,
I1 => \cosine[25]_i_5_n_0\,
I2 => \cosine[24]_i_5_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[6]_i_2_n_0\,
O => \cosine[6]_i_1_n_0\
);
\cosine[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"82979D9D"
)
port map (
I0 => \cosine[29]_i_5_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
O => \cosine[6]_i_2_n_0\
);
\cosine[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[7]_i_2_n_0\,
I1 => \cosine[7]_i_3_n_0\,
I2 => \cosine[7]_i_4_n_0\,
I3 => \cosine[7]_i_5_n_0\,
I4 => \cosine[9]_i_3_n_0\,
O => \cosine[7]_i_1_n_0\
);
\cosine[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F7000A0"
)
port map (
I0 => \cosine[29]_i_4_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
O => \cosine[7]_i_2_n_0\
);
\cosine[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cosine[24]_i_9_n_0\,
I1 => \cosine[24]_i_7_n_0\,
O => \cosine[7]_i_3_n_0\
);
\cosine[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEEEFEFFEEEE"
)
port map (
I0 => \cosine[29]_i_13_n_0\,
I1 => \cosine[29]_i_16_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[25]_i_4_n_0\,
O => \cosine[7]_i_4_n_0\
);
\cosine[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[19]_i_12_n_0\,
I1 => \cosine[19]_i_9_n_0\,
I2 => \cosine[29]_i_17_n_0\,
I3 => \cosine[19]_i_11_n_0\,
O => \cosine[7]_i_5_n_0\
);
\cosine[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000444000000000"
)
port map (
I0 => \cosine[29]_i_8_n_0\,
I1 => \cosine[29]_i_7_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[8]_i_2_n_0\,
I4 => \cosine[29]_i_3_n_0\,
I5 => \cosine[8]_i_3_n_0\,
O => \cosine[8]_i_1_n_0\
);
\cosine[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA9A9999AA9AAAAA"
)
port map (
I0 => \cosine[29]_i_4_n_0\,
I1 => reset,
I2 => p_1_in(4),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(4),
O => \cosine[8]_i_2_n_0\
);
\cosine[8]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"33DD3FD3"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_5_n_0\,
O => \cosine[8]_i_3_n_0\
);
\cosine[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF6A"
)
port map (
I0 => \cosine[29]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[9]_i_2_n_0\,
I4 => \cosine[9]_i_3_n_0\,
O => \cosine[9]_i_1_n_0\
);
\cosine[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[7]_i_3_n_0\,
I1 => \cosine[29]_i_13_n_0\,
I2 => \cosine[29]_i_16_n_0\,
I3 => \cosine[9]_i_4_n_0\,
I4 => \cosine[7]_i_5_n_0\,
O => \cosine[9]_i_2_n_0\
);
\cosine[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[9]_i_5_n_0\,
I1 => \cosine[24]_i_8_n_0\,
I2 => \cosine[29]_i_14_n_0\,
I3 => \cosine[9]_i_6_n_0\,
I4 => \cosine[24]_i_3_n_0\,
O => \cosine[9]_i_3_n_0\
);
\cosine[9]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0CCD0"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[29]_i_4_n_0\,
O => \cosine[9]_i_4_n_0\
);
\cosine[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[29]_i_29_n_0\,
I1 => \cosine[29]_i_26_n_0\,
I2 => \cosine[29]_i_19_n_0\,
I3 => \cosine[29]_i_28_n_0\,
O => \cosine[9]_i_5_n_0\
);
\cosine[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(28),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(28),
I5 => \cosine[29]_i_27_n_0\,
O => \cosine[9]_i_6_n_0\
);
\cosine_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[0]_i_1_n_0\,
Q => a00(0),
R => '0'
);
\cosine_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[10]_i_1_n_0\,
Q => a00(10),
R => '0'
);
\cosine_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[11]_i_1_n_0\,
Q => a00(11),
R => '0'
);
\cosine_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[12]_i_1_n_0\,
Q => a00(12),
R => '0'
);
\cosine_reg[13]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[13]_i_1_n_0\,
Q => a00(13),
S => \cosine[24]_i_1_n_0\
);
\cosine_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[14]_i_1_n_0\,
Q => a00(14),
R => '0'
);
\cosine_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[15]_i_1_n_0\,
Q => a00(15),
R => '0'
);
\cosine_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[16]_i_1_n_0\,
Q => a00(16),
R => '0'
);
\cosine_reg[17]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[17]_i_1_n_0\,
Q => a00(17),
S => \cosine[24]_i_1_n_0\
);
\cosine_reg[18]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[18]_i_1_n_0\,
Q => a00(18),
S => \cosine[24]_i_1_n_0\
);
\cosine_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[19]_i_1_n_0\,
Q => a00(19),
R => '0'
);
\cosine_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[1]_i_1_n_0\,
Q => a00(1),
R => '0'
);
\cosine_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[20]_i_1_n_0\,
Q => a00(20),
R => '0'
);
\cosine_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[21]_i_1_n_0\,
Q => a00(21),
R => '0'
);
\cosine_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[22]_i_1_n_0\,
Q => a00(22),
R => '0'
);
\cosine_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[23]_i_1_n_0\,
Q => a00(23),
R => '0'
);
\cosine_reg[24]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[24]_i_2_n_0\,
Q => a00(24),
S => \cosine[24]_i_1_n_0\
);
\cosine_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[25]_i_1_n_0\,
Q => a00(25),
R => '0'
);
\cosine_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[29]_i_2_n_0\,
Q => a00(26),
R => '0'
);
\cosine_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[2]_i_1_n_0\,
Q => a00(2),
R => '0'
);
\cosine_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[3]_i_1_n_0\,
Q => a00(3),
R => '0'
);
\cosine_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[4]_i_1_n_0\,
Q => a00(4),
R => '0'
);
\cosine_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[5]_i_1_n_0\,
Q => a00(5),
R => '0'
);
\cosine_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[6]_i_1_n_0\,
Q => a00(6),
R => '0'
);
\cosine_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[7]_i_1_n_0\,
Q => a00(7),
R => '0'
);
\cosine_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[8]_i_1_n_0\,
Q => a00(8),
R => '0'
);
\cosine_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[9]_i_1_n_0\,
Q => a00(9),
R => '0'
);
\counter0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter0_inferred__0/i__carry_n_0\,
CO(2) => \counter0_inferred__0/i__carry_n_1\,
CO(1) => \counter0_inferred__0/i__carry_n_2\,
CO(0) => \counter0_inferred__0/i__carry_n_3\,
CYINIT => '1',
DI(3) => p_0_in(7),
DI(2) => \i__carry_i_2_n_0\,
DI(1) => \i__carry_i_3_n_0\,
DI(0) => \i__carry_i_4_n_0\,
O(3 downto 0) => \NLW_counter0_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry_i_5_n_0\,
S(2) => \i__carry_i_6_n_0\,
S(1) => \i__carry_i_7_n_0\,
S(0) => \i__carry_i_8_n_0\
);
\counter0_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \counter0_inferred__0/i__carry_n_0\,
CO(3) => \counter0_inferred__0/i__carry__0_n_0\,
CO(2) => \counter0_inferred__0/i__carry__0_n_1\,
CO(1) => \counter0_inferred__0/i__carry__0_n_2\,
CO(0) => \counter0_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => p_0_in(15),
DI(2) => '0',
DI(1) => \i__carry__0_i_2_n_0\,
DI(0) => \i__carry__0_i_3_n_0\,
O(3 downto 0) => \NLW_counter0_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__0_i_4_n_0\,
S(2) => \i__carry__0_i_5_n_0\,
S(1) => \i__carry__0_i_6_n_0\,
S(0) => \i__carry__0_i_7_n_0\
);
\counter0_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \counter0_inferred__0/i__carry__0_n_0\,
CO(3) => \counter0_inferred__0/i__carry__1_n_0\,
CO(2) => \counter0_inferred__0/i__carry__1_n_1\,
CO(1) => \counter0_inferred__0/i__carry__1_n_2\,
CO(0) => \counter0_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3) => p_0_in(23),
DI(2 downto 1) => B"00",
DI(0) => p_0_in(17),
O(3 downto 0) => \NLW_counter0_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__1_i_3_n_0\,
S(2) => \i__carry__1_i_4_n_0\,
S(1) => \i__carry__1_i_5_n_0\,
S(0) => \i__carry__1_i_6_n_0\
);
\counter0_inferred__0/i__carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \counter0_inferred__0/i__carry__1_n_0\,
CO(3) => \counter0_inferred__0/i__carry__2_n_0\,
CO(2) => \counter0_inferred__0/i__carry__2_n_1\,
CO(1) => \counter0_inferred__0/i__carry__2_n_2\,
CO(0) => \counter0_inferred__0/i__carry__2_n_3\,
CYINIT => '0',
DI(3) => \i__carry__2_i_1_n_0\,
DI(2) => \i__carry__2_i_2_n_0\,
DI(1) => \i__carry__2_i_3_n_0\,
DI(0) => p_0_in(25),
O(3 downto 0) => \NLW_counter0_inferred__0/i__carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__2_i_5_n_0\,
S(2) => \i__carry__2_i_6_n_0\,
S(1) => \i__carry__2_i_7_n_0\,
S(0) => \i__carry__2_i_8_n_0\
);
\counter[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => reset,
I1 => \counter0_inferred__0/i__carry__2_n_0\,
O => \counter[0]_i_1_n_0\
);
\counter[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(3),
O => \counter[0]_i_3_n_0\
);
\counter[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(2),
O => \counter[0]_i_4_n_0\
);
\counter[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(1),
O => \counter[0]_i_5_n_0\
);
\counter[0]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(0),
O => p_0_in(0)
);
\counter[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(15),
O => \counter[12]_i_2_n_0\
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(14),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(13),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(12),
O => \counter[12]_i_5_n_0\
);
\counter[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(19),
O => \counter[16]_i_2_n_0\
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(18),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(17),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(16),
O => \counter[16]_i_5_n_0\
);
\counter[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(23),
O => \counter[20]_i_2_n_0\
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(22),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(21),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(20),
O => \counter[20]_i_5_n_0\
);
\counter[24]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(27),
O => \counter[24]_i_2_n_0\
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(26),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(25),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(24),
O => \counter[24]_i_5_n_0\
);
\counter[28]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(31),
O => \counter[28]_i_2_n_0\
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(30),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(29),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(28),
O => \counter[28]_i_5_n_0\
);
\counter[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(7),
O => \counter[4]_i_2_n_0\
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(6),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(5),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(4),
O => \counter[4]_i_5_n_0\
);
\counter[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(11),
O => \counter[8]_i_2_n_0\
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(10),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(9),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(8),
O => \counter[8]_i_5_n_0\
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[0]_i_2_n_7\,
Q => counter_reg(0),
R => \counter[0]_i_1_n_0\
);
\counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[0]_i_2_n_0\,
CO(2) => \counter_reg[0]_i_2_n_1\,
CO(1) => \counter_reg[0]_i_2_n_2\,
CO(0) => \counter_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \counter_reg[0]_i_2_n_4\,
O(2) => \counter_reg[0]_i_2_n_5\,
O(1) => \counter_reg[0]_i_2_n_6\,
O(0) => \counter_reg[0]_i_2_n_7\,
S(3) => \counter[0]_i_3_n_0\,
S(2) => \counter[0]_i_4_n_0\,
S(1) => \counter[0]_i_5_n_0\,
S(0) => p_0_in(0)
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[8]_i_1_n_5\,
Q => counter_reg(10),
R => \counter[0]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[8]_i_1_n_4\,
Q => counter_reg(11),
R => \counter[0]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[12]_i_1_n_7\,
Q => counter_reg(12),
R => \counter[0]_i_1_n_0\
);
\counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_1_n_0\,
CO(3) => \counter_reg[12]_i_1_n_0\,
CO(2) => \counter_reg[12]_i_1_n_1\,
CO(1) => \counter_reg[12]_i_1_n_2\,
CO(0) => \counter_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_1_n_4\,
O(2) => \counter_reg[12]_i_1_n_5\,
O(1) => \counter_reg[12]_i_1_n_6\,
O(0) => \counter_reg[12]_i_1_n_7\,
S(3) => \counter[12]_i_2_n_0\,
S(2) => \counter[12]_i_3_n_0\,
S(1) => \counter[12]_i_4_n_0\,
S(0) => \counter[12]_i_5_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[12]_i_1_n_6\,
Q => counter_reg(13),
R => \counter[0]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[12]_i_1_n_5\,
Q => counter_reg(14),
R => \counter[0]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[12]_i_1_n_4\,
Q => counter_reg(15),
R => \counter[0]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[16]_i_1_n_7\,
Q => counter_reg(16),
R => \counter[0]_i_1_n_0\
);
\counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_1_n_0\,
CO(3) => \counter_reg[16]_i_1_n_0\,
CO(2) => \counter_reg[16]_i_1_n_1\,
CO(1) => \counter_reg[16]_i_1_n_2\,
CO(0) => \counter_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_1_n_4\,
O(2) => \counter_reg[16]_i_1_n_5\,
O(1) => \counter_reg[16]_i_1_n_6\,
O(0) => \counter_reg[16]_i_1_n_7\,
S(3) => \counter[16]_i_2_n_0\,
S(2) => \counter[16]_i_3_n_0\,
S(1) => \counter[16]_i_4_n_0\,
S(0) => \counter[16]_i_5_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[16]_i_1_n_6\,
Q => counter_reg(17),
R => \counter[0]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[16]_i_1_n_5\,
Q => counter_reg(18),
R => \counter[0]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[16]_i_1_n_4\,
Q => counter_reg(19),
R => \counter[0]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[0]_i_2_n_6\,
Q => counter_reg(1),
R => \counter[0]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[20]_i_1_n_7\,
Q => counter_reg(20),
R => \counter[0]_i_1_n_0\
);
\counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_1_n_0\,
CO(3) => \counter_reg[20]_i_1_n_0\,
CO(2) => \counter_reg[20]_i_1_n_1\,
CO(1) => \counter_reg[20]_i_1_n_2\,
CO(0) => \counter_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_1_n_4\,
O(2) => \counter_reg[20]_i_1_n_5\,
O(1) => \counter_reg[20]_i_1_n_6\,
O(0) => \counter_reg[20]_i_1_n_7\,
S(3) => \counter[20]_i_2_n_0\,
S(2) => \counter[20]_i_3_n_0\,
S(1) => \counter[20]_i_4_n_0\,
S(0) => \counter[20]_i_5_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[20]_i_1_n_6\,
Q => counter_reg(21),
R => \counter[0]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[20]_i_1_n_5\,
Q => counter_reg(22),
R => \counter[0]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[20]_i_1_n_4\,
Q => counter_reg(23),
R => \counter[0]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[24]_i_1_n_7\,
Q => counter_reg(24),
R => \counter[0]_i_1_n_0\
);
\counter_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_1_n_0\,
CO(3) => \counter_reg[24]_i_1_n_0\,
CO(2) => \counter_reg[24]_i_1_n_1\,
CO(1) => \counter_reg[24]_i_1_n_2\,
CO(0) => \counter_reg[24]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_1_n_4\,
O(2) => \counter_reg[24]_i_1_n_5\,
O(1) => \counter_reg[24]_i_1_n_6\,
O(0) => \counter_reg[24]_i_1_n_7\,
S(3) => \counter[24]_i_2_n_0\,
S(2) => \counter[24]_i_3_n_0\,
S(1) => \counter[24]_i_4_n_0\,
S(0) => \counter[24]_i_5_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[24]_i_1_n_6\,
Q => counter_reg(25),
R => \counter[0]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[24]_i_1_n_5\,
Q => counter_reg(26),
R => \counter[0]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[24]_i_1_n_4\,
Q => counter_reg(27),
R => \counter[0]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[28]_i_1_n_7\,
Q => counter_reg(28),
R => \counter[0]_i_1_n_0\
);
\counter_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_1_n_0\,
CO(3) => \NLW_counter_reg[28]_i_1_CO_UNCONNECTED\(3),
CO(2) => \counter_reg[28]_i_1_n_1\,
CO(1) => \counter_reg[28]_i_1_n_2\,
CO(0) => \counter_reg[28]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_1_n_4\,
O(2) => \counter_reg[28]_i_1_n_5\,
O(1) => \counter_reg[28]_i_1_n_6\,
O(0) => \counter_reg[28]_i_1_n_7\,
S(3) => \counter[28]_i_2_n_0\,
S(2) => \counter[28]_i_3_n_0\,
S(1) => \counter[28]_i_4_n_0\,
S(0) => \counter[28]_i_5_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[28]_i_1_n_6\,
Q => counter_reg(29),
R => \counter[0]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[0]_i_2_n_5\,
Q => counter_reg(2),
R => \counter[0]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[28]_i_1_n_5\,
Q => counter_reg(30),
R => \counter[0]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[28]_i_1_n_4\,
Q => counter_reg(31),
R => \counter[0]_i_1_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[0]_i_2_n_4\,
Q => counter_reg(3),
R => \counter[0]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[4]_i_1_n_7\,
Q => counter_reg(4),
R => \counter[0]_i_1_n_0\
);
\counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[0]_i_2_n_0\,
CO(3) => \counter_reg[4]_i_1_n_0\,
CO(2) => \counter_reg[4]_i_1_n_1\,
CO(1) => \counter_reg[4]_i_1_n_2\,
CO(0) => \counter_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_1_n_4\,
O(2) => \counter_reg[4]_i_1_n_5\,
O(1) => \counter_reg[4]_i_1_n_6\,
O(0) => \counter_reg[4]_i_1_n_7\,
S(3) => \counter[4]_i_2_n_0\,
S(2) => \counter[4]_i_3_n_0\,
S(1) => \counter[4]_i_4_n_0\,
S(0) => \counter[4]_i_5_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[4]_i_1_n_6\,
Q => counter_reg(5),
R => \counter[0]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[4]_i_1_n_5\,
Q => counter_reg(6),
R => \counter[0]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[4]_i_1_n_4\,
Q => counter_reg(7),
R => \counter[0]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[8]_i_1_n_7\,
Q => counter_reg(8),
R => \counter[0]_i_1_n_0\
);
\counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_1_n_0\,
CO(3) => \counter_reg[8]_i_1_n_0\,
CO(2) => \counter_reg[8]_i_1_n_1\,
CO(1) => \counter_reg[8]_i_1_n_2\,
CO(0) => \counter_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_1_n_4\,
O(2) => \counter_reg[8]_i_1_n_5\,
O(1) => \counter_reg[8]_i_1_n_6\,
O(0) => \counter_reg[8]_i_1_n_7\,
S(3) => \counter[8]_i_2_n_0\,
S(2) => \counter[8]_i_3_n_0\,
S(1) => \counter[8]_i_4_n_0\,
S(0) => \counter[8]_i_5_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[8]_i_1_n_6\,
Q => counter_reg(9),
R => \counter[0]_i_1_n_0\
);
\i__carry__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__0_i_8_n_0\,
CO(3) => \i__carry__0_i_1_n_0\,
CO(2) => \i__carry__0_i_1_n_1\,
CO(1) => \i__carry__0_i_1_n_2\,
CO(0) => \i__carry__0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(16 downto 13),
S(3) => \i__carry__0_i_9_n_0\,
S(2) => \i__carry__0_i_10_n_0\,
S(1) => \i__carry__0_i_11_n_0\,
S(0) => \i__carry__0_i_12_n_0\
);
\i__carry__0_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(15),
O => \i__carry__0_i_10_n_0\
);
\i__carry__0_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(14),
O => \i__carry__0_i_11_n_0\
);
\i__carry__0_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(13),
O => \i__carry__0_i_12_n_0\
);
\i__carry__0_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(12),
O => \i__carry__0_i_13_n_0\
);
\i__carry__0_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(11),
O => \i__carry__0_i_14_n_0\
);
\i__carry__0_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(10),
O => \i__carry__0_i_15_n_0\
);
\i__carry__0_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(9),
O => \i__carry__0_i_16_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(10),
I1 => p_0_in(11),
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(8),
I1 => p_0_in(9),
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(14),
I1 => p_0_in(15),
O => \i__carry__0_i_4_n_0\
);
\i__carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(12),
I1 => p_0_in(13),
O => \i__carry__0_i_5_n_0\
);
\i__carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(11),
I1 => p_0_in(10),
O => \i__carry__0_i_6_n_0\
);
\i__carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(8),
I1 => p_0_in(9),
O => \i__carry__0_i_7_n_0\
);
\i__carry__0_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry_i_1_n_0\,
CO(3) => \i__carry__0_i_8_n_0\,
CO(2) => \i__carry__0_i_8_n_1\,
CO(1) => \i__carry__0_i_8_n_2\,
CO(0) => \i__carry__0_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(12 downto 9),
S(3) => \i__carry__0_i_13_n_0\,
S(2) => \i__carry__0_i_14_n_0\,
S(1) => \i__carry__0_i_15_n_0\,
S(0) => \i__carry__0_i_16_n_0\
);
\i__carry__0_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(16),
O => \i__carry__0_i_9_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__1_i_2_n_0\,
CO(3) => \i__carry__1_i_1_n_0\,
CO(2) => \i__carry__1_i_1_n_1\,
CO(1) => \i__carry__1_i_1_n_2\,
CO(0) => \i__carry__1_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(24 downto 21),
S(3) => \i__carry__1_i_7_n_0\,
S(2) => \i__carry__1_i_8_n_0\,
S(1) => \i__carry__1_i_9_n_0\,
S(0) => \i__carry__1_i_10_n_0\
);
\i__carry__1_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(21),
O => \i__carry__1_i_10_n_0\
);
\i__carry__1_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(20),
O => \i__carry__1_i_11_n_0\
);
\i__carry__1_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(19),
O => \i__carry__1_i_12_n_0\
);
\i__carry__1_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(18),
O => \i__carry__1_i_13_n_0\
);
\i__carry__1_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(17),
O => \i__carry__1_i_14_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__0_i_1_n_0\,
CO(3) => \i__carry__1_i_2_n_0\,
CO(2) => \i__carry__1_i_2_n_1\,
CO(1) => \i__carry__1_i_2_n_2\,
CO(0) => \i__carry__1_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(20 downto 17),
S(3) => \i__carry__1_i_11_n_0\,
S(2) => \i__carry__1_i_12_n_0\,
S(1) => \i__carry__1_i_13_n_0\,
S(0) => \i__carry__1_i_14_n_0\
);
\i__carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(22),
I1 => p_0_in(23),
O => \i__carry__1_i_3_n_0\
);
\i__carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(20),
I1 => p_0_in(21),
O => \i__carry__1_i_4_n_0\
);
\i__carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(18),
I1 => p_0_in(19),
O => \i__carry__1_i_5_n_0\
);
\i__carry__1_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(16),
I1 => p_0_in(17),
O => \i__carry__1_i_6_n_0\
);
\i__carry__1_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(24),
O => \i__carry__1_i_7_n_0\
);
\i__carry__1_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(23),
O => \i__carry__1_i_8_n_0\
);
\i__carry__1_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(22),
O => \i__carry__1_i_9_n_0\
);
\i__carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(30),
I1 => p_0_in(31),
O => \i__carry__2_i_1_n_0\
);
\i__carry__2_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(28),
O => \i__carry__2_i_10_n_0\
);
\i__carry__2_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(27),
O => \i__carry__2_i_11_n_0\
);
\i__carry__2_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(26),
O => \i__carry__2_i_12_n_0\
);
\i__carry__2_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(25),
O => \i__carry__2_i_13_n_0\
);
\i__carry__2_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(31),
O => \i__carry__2_i_14_n_0\
);
\i__carry__2_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(30),
O => \i__carry__2_i_15_n_0\
);
\i__carry__2_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(29),
O => \i__carry__2_i_16_n_0\
);
\i__carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(28),
I1 => p_0_in(29),
O => \i__carry__2_i_2_n_0\
);
\i__carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(26),
I1 => p_0_in(27),
O => \i__carry__2_i_3_n_0\
);
\i__carry__2_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__1_i_1_n_0\,
CO(3) => \i__carry__2_i_4_n_0\,
CO(2) => \i__carry__2_i_4_n_1\,
CO(1) => \i__carry__2_i_4_n_2\,
CO(0) => \i__carry__2_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(28 downto 25),
S(3) => \i__carry__2_i_10_n_0\,
S(2) => \i__carry__2_i_11_n_0\,
S(1) => \i__carry__2_i_12_n_0\,
S(0) => \i__carry__2_i_13_n_0\
);
\i__carry__2_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(30),
I1 => p_0_in(31),
O => \i__carry__2_i_5_n_0\
);
\i__carry__2_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(28),
I1 => p_0_in(29),
O => \i__carry__2_i_6_n_0\
);
\i__carry__2_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(26),
I1 => p_0_in(27),
O => \i__carry__2_i_7_n_0\
);
\i__carry__2_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(24),
I1 => p_0_in(25),
O => \i__carry__2_i_8_n_0\
);
\i__carry__2_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__2_i_4_n_0\,
CO(3 downto 2) => \NLW_i__carry__2_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \i__carry__2_i_9_n_2\,
CO(0) => \i__carry__2_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_i__carry__2_i_9_O_UNCONNECTED\(3),
O(2 downto 0) => p_0_in(31 downto 29),
S(3) => '0',
S(2) => \i__carry__2_i_14_n_0\,
S(1) => \i__carry__2_i_15_n_0\,
S(0) => \i__carry__2_i_16_n_0\
);
\i__carry_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry_i_9_n_0\,
CO(3) => \i__carry_i_1_n_0\,
CO(2) => \i__carry_i_1_n_1\,
CO(1) => \i__carry_i_1_n_2\,
CO(0) => \i__carry_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(8 downto 5),
S(3) => \i__carry_i_10_n_0\,
S(2) => \i__carry_i_11_n_0\,
S(1) => \i__carry_i_12_n_0\,
S(0) => \i__carry_i_13_n_0\
);
\i__carry_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(8),
O => \i__carry_i_10_n_0\
);
\i__carry_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(7),
O => \i__carry_i_11_n_0\
);
\i__carry_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(6),
O => \i__carry_i_12_n_0\
);
\i__carry_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(5),
O => \i__carry_i_13_n_0\
);
\i__carry_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(4),
O => \i__carry_i_14_n_0\
);
\i__carry_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(3),
O => \i__carry_i_15_n_0\
);
\i__carry_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(2),
O => \i__carry_i_16_n_0\
);
\i__carry_i_17\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(1),
O => \i__carry_i_17_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(4),
I1 => p_0_in(5),
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(2),
I1 => p_0_in(3),
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => counter_reg(0),
I1 => p_0_in(1),
O => \i__carry_i_4_n_0\
);
\i__carry_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(6),
I1 => p_0_in(7),
O => \i__carry_i_5_n_0\
);
\i__carry_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(4),
I1 => p_0_in(5),
O => \i__carry_i_6_n_0\
);
\i__carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(2),
I1 => p_0_in(3),
O => \i__carry_i_7_n_0\
);
\i__carry_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(0),
I1 => p_0_in(1),
O => \i__carry_i_8_n_0\
);
\i__carry_i_9\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \i__carry_i_9_n_0\,
CO(2) => \i__carry_i_9_n_1\,
CO(1) => \i__carry_i_9_n_2\,
CO(0) => \i__carry_i_9_n_3\,
CYINIT => counter_reg(0),
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(4 downto 1),
S(3) => \i__carry_i_14_n_0\,
S(2) => \i__carry_i_15_n_0\,
S(1) => \i__carry_i_16_n_0\,
S(0) => \i__carry_i_17_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_affine_rotation_generator_0_0 is
port (
clk_25 : in STD_LOGIC;
reset : in STD_LOGIC;
a00 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_affine_rotation_generator_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_affine_rotation_generator_0_0 : entity is "system_affine_rotation_generator_0_0,affine_rotation_generator,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_affine_rotation_generator_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_affine_rotation_generator_0_0 : entity is "affine_rotation_generator,Vivado 2016.4";
end system_affine_rotation_generator_0_0;
architecture STRUCTURE of system_affine_rotation_generator_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^a00\ : STD_LOGIC_VECTOR ( 28 to 28 );
signal \^a01\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \^a11\ : STD_LOGIC_VECTOR ( 25 downto 0 );
begin
a00(31) <= \<const0>\;
a00(30) <= \<const0>\;
a00(29) <= \^a00\(28);
a00(28) <= \^a00\(28);
a00(27) <= \^a00\(28);
a00(26) <= \^a00\(28);
a00(25 downto 0) <= \^a11\(25 downto 0);
a01(31) <= \<const1>\;
a01(30) <= \<const0>\;
a01(29 downto 0) <= \^a01\(29 downto 0);
a10(31) <= \<const0>\;
a10(30) <= \<const0>\;
a10(29 downto 0) <= \^a01\(29 downto 0);
a11(31) <= \<const0>\;
a11(30) <= \<const0>\;
a11(29) <= \^a00\(28);
a11(28) <= \^a00\(28);
a11(27) <= \^a00\(28);
a11(26) <= \^a00\(28);
a11(25 downto 0) <= \^a11\(25 downto 0);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_affine_rotation_generator_0_0_affine_rotation_generator
port map (
a00(26) => \^a00\(28),
a00(25 downto 0) => \^a11\(25 downto 0),
a01(29 downto 0) => \^a01\(29 downto 0),
clk_25 => clk_25,
reset => reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_0/system_auto_us_0_sim_netlist.vhdl
|
1
|
589114
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:15:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_0/system_auto_us_0_sim_netlist.vhdl
-- Design : system_auto_us_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer is
port (
first_mi_word_q : out STD_LOGIC;
first_word : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
use_wrap_buffer : out STD_LOGIC;
wrap_buffer_available : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
use_wrap_buffer_reg_0 : out STD_LOGIC;
first_word_reg_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[2]_0\ : out STD_LOGIC;
\current_word_1_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[2]_1\ : out STD_LOGIC;
\USE_RTL_ADDR.addr_q_reg[4]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
pop_mi_data : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 66 downto 0 );
s_axi_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
\current_word_1_reg[2]_1\ : in STD_LOGIC;
\current_word_1_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer : entity is "axi_dwidth_converter_v2_1_11_r_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer is
signal M_AXI_RDATA_I : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \USE_RTL_ADDR.addr_q[4]_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_7_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^current_word_1_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word\ : STD_LOGIC;
signal \^first_word_reg_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rresp_wrap_buffer : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rlast\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_3_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_4_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_5_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_6_n_0 : STD_LOGIC;
signal \^use_wrap_buffer\ : STD_LOGIC;
signal use_wrap_buffer_i_1_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_2_n_0 : STD_LOGIC;
signal \^use_wrap_buffer_reg_0\ : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal \wrap_buffer_available_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_buffer_available_i_2__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_5\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_6\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_7\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_2__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[4]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[6]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_4 : label is "soft_lutpair34";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_5 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \s_axi_rresp[0]_INST_0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair38";
begin
\current_word_1_reg[2]_0\(2 downto 0) <= \^current_word_1_reg[2]_0\(2 downto 0);
first_mi_word_q <= \^first_mi_word_q\;
first_word <= \^first_word\;
first_word_reg_0(2 downto 0) <= \^first_word_reg_0\(2 downto 0);
s_axi_rlast <= \^s_axi_rlast\;
use_wrap_buffer <= \^use_wrap_buffer\;
use_wrap_buffer_reg_0 <= \^use_wrap_buffer_reg_0\;
wrap_buffer_available <= \^wrap_buffer_available\;
\M_AXI_RDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(0),
Q => M_AXI_RDATA_I(0),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(10),
Q => M_AXI_RDATA_I(10),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(11),
Q => M_AXI_RDATA_I(11),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(12),
Q => M_AXI_RDATA_I(12),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(13),
Q => M_AXI_RDATA_I(13),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(14),
Q => M_AXI_RDATA_I(14),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(15),
Q => M_AXI_RDATA_I(15),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(16),
Q => M_AXI_RDATA_I(16),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(17),
Q => M_AXI_RDATA_I(17),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(18),
Q => M_AXI_RDATA_I(18),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(19),
Q => M_AXI_RDATA_I(19),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(1),
Q => M_AXI_RDATA_I(1),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(20),
Q => M_AXI_RDATA_I(20),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(21),
Q => M_AXI_RDATA_I(21),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(22),
Q => M_AXI_RDATA_I(22),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(23),
Q => M_AXI_RDATA_I(23),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(24),
Q => M_AXI_RDATA_I(24),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(25),
Q => M_AXI_RDATA_I(25),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(26),
Q => M_AXI_RDATA_I(26),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(27),
Q => M_AXI_RDATA_I(27),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(28),
Q => M_AXI_RDATA_I(28),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(29),
Q => M_AXI_RDATA_I(29),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(2),
Q => M_AXI_RDATA_I(2),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(30),
Q => M_AXI_RDATA_I(30),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(31),
Q => M_AXI_RDATA_I(31),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(32),
Q => M_AXI_RDATA_I(32),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(33),
Q => M_AXI_RDATA_I(33),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(34),
Q => M_AXI_RDATA_I(34),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(35),
Q => M_AXI_RDATA_I(35),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(36),
Q => M_AXI_RDATA_I(36),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(37),
Q => M_AXI_RDATA_I(37),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(38),
Q => M_AXI_RDATA_I(38),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(39),
Q => M_AXI_RDATA_I(39),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(3),
Q => M_AXI_RDATA_I(3),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(40),
Q => M_AXI_RDATA_I(40),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(41),
Q => M_AXI_RDATA_I(41),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(42),
Q => M_AXI_RDATA_I(42),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(43),
Q => M_AXI_RDATA_I(43),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(44),
Q => M_AXI_RDATA_I(44),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(45),
Q => M_AXI_RDATA_I(45),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(46),
Q => M_AXI_RDATA_I(46),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(47),
Q => M_AXI_RDATA_I(47),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(48),
Q => M_AXI_RDATA_I(48),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(49),
Q => M_AXI_RDATA_I(49),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(4),
Q => M_AXI_RDATA_I(4),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(50),
Q => M_AXI_RDATA_I(50),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(51),
Q => M_AXI_RDATA_I(51),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(52),
Q => M_AXI_RDATA_I(52),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(53),
Q => M_AXI_RDATA_I(53),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(54),
Q => M_AXI_RDATA_I(54),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(55),
Q => M_AXI_RDATA_I(55),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(56),
Q => M_AXI_RDATA_I(56),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(57),
Q => M_AXI_RDATA_I(57),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(58),
Q => M_AXI_RDATA_I(58),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(59),
Q => M_AXI_RDATA_I(59),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(5),
Q => M_AXI_RDATA_I(5),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(60),
Q => M_AXI_RDATA_I(60),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(61),
Q => M_AXI_RDATA_I(61),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(62),
Q => M_AXI_RDATA_I(62),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(63),
Q => M_AXI_RDATA_I(63),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(6),
Q => M_AXI_RDATA_I(6),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(7),
Q => M_AXI_RDATA_I(7),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(8),
Q => M_AXI_RDATA_I(8),
R => s_axi_aresetn
);
\M_AXI_RDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(9),
Q => M_AXI_RDATA_I(9),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => s_axi_rlast_INST_0_i_6_n_0,
I2 => \USE_RTL_ADDR.addr_q[4]_i_5_n_0\,
I3 => s_axi_rlast_INST_0_i_5_n_0,
I4 => \USE_RTL_ADDR.addr_q[4]_i_6_n_0\,
I5 => \USE_RTL_ADDR.addr_q[4]_i_7_n_0\,
O => \USE_RTL_ADDR.addr_q_reg[4]\
);
\USE_RTL_ADDR.addr_q[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
O => \USE_RTL_ADDR.addr_q[4]_i_5_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
O => \USE_RTL_ADDR.addr_q[4]_i_6_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => \USE_RTL_ADDR.addr_q[4]_i_7_n_0\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => Q(66),
Q => \^first_mi_word_q\,
S => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => \^first_mi_word_q\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA533A5"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFA051111FA05"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I4 => \^first_mi_word_q\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(2),
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
O => \USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(3),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(2),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I5 => \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0),
O => \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => s_axi_rlast_INST_0_i_6_n_0,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \^first_mi_word_q\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I5 => s_axi_rlast_INST_0_i_6_n_0,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1DE2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => \^first_mi_word_q\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(6),
I3 => \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(6),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I5 => \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050500030"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => s_axi_rlast_INST_0_i_6_n_0,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => s_axi_aresetn
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_mi_data,
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => s_axi_aresetn
);
\current_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0),
Q => \^first_word_reg_0\(0),
R => s_axi_aresetn
);
\current_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1),
Q => \^first_word_reg_0\(1),
R => s_axi_aresetn
);
\current_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2),
Q => \^first_word_reg_0\(2),
R => s_axi_aresetn
);
first_word_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^s_axi_rlast\,
Q => \^first_word\,
S => s_axi_aresetn
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F2000000FFFFFFFF"
)
port map (
I0 => \^s_axi_rlast\,
I1 => \^use_wrap_buffer\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I3 => s_axi_rready,
I4 => rd_cmd_valid,
I5 => mr_rvalid,
O => \m_payload_i_reg[0]\(0)
);
\pre_next_word_1[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^current_word_1_reg[2]_0\(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(10),
O => \pre_next_word_1_reg[2]_0\
);
\pre_next_word_1[2]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => \^current_word_1_reg[2]_0\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(9),
O => \pre_next_word_1_reg[2]_1\
);
\pre_next_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^current_word_1_reg[2]_0\(0),
R => s_axi_aresetn
);
\pre_next_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^current_word_1_reg[2]_0\(1),
R => s_axi_aresetn
);
\pre_next_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => \^current_word_1_reg[2]_0\(2),
R => s_axi_aresetn
);
\rresp_wrap_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(64),
Q => rresp_wrap_buffer(0),
R => s_axi_aresetn
);
\rresp_wrap_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => m_valid_i_reg(0),
D => Q(65),
Q => rresp_wrap_buffer(1),
R => s_axi_aresetn
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(0),
I1 => M_AXI_RDATA_I(32),
I2 => \^use_wrap_buffer\,
I3 => Q(0),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(32),
O => s_axi_rdata(0)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(10),
I1 => M_AXI_RDATA_I(42),
I2 => \^use_wrap_buffer\,
I3 => Q(10),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(42),
O => s_axi_rdata(10)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(11),
I1 => M_AXI_RDATA_I(43),
I2 => \^use_wrap_buffer\,
I3 => Q(11),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(43),
O => s_axi_rdata(11)
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(12),
I1 => M_AXI_RDATA_I(44),
I2 => \^use_wrap_buffer\,
I3 => Q(12),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(44),
O => s_axi_rdata(12)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(13),
I1 => M_AXI_RDATA_I(45),
I2 => \^use_wrap_buffer\,
I3 => Q(13),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(45),
O => s_axi_rdata(13)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(14),
I1 => M_AXI_RDATA_I(46),
I2 => \^use_wrap_buffer\,
I3 => Q(14),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(46),
O => s_axi_rdata(14)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(15),
I1 => M_AXI_RDATA_I(47),
I2 => \^use_wrap_buffer\,
I3 => Q(15),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(47),
O => s_axi_rdata(15)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(16),
I1 => M_AXI_RDATA_I(48),
I2 => \^use_wrap_buffer\,
I3 => Q(16),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(48),
O => s_axi_rdata(16)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(17),
I1 => M_AXI_RDATA_I(49),
I2 => \^use_wrap_buffer\,
I3 => Q(17),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(49),
O => s_axi_rdata(17)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(18),
I1 => M_AXI_RDATA_I(50),
I2 => \^use_wrap_buffer\,
I3 => Q(18),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(50),
O => s_axi_rdata(18)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(19),
I1 => M_AXI_RDATA_I(51),
I2 => \^use_wrap_buffer\,
I3 => Q(19),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(51),
O => s_axi_rdata(19)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(1),
I1 => M_AXI_RDATA_I(33),
I2 => \^use_wrap_buffer\,
I3 => Q(1),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(33),
O => s_axi_rdata(1)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(20),
I1 => M_AXI_RDATA_I(52),
I2 => \^use_wrap_buffer\,
I3 => Q(20),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(52),
O => s_axi_rdata(20)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(21),
I1 => M_AXI_RDATA_I(53),
I2 => \^use_wrap_buffer\,
I3 => Q(21),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(53),
O => s_axi_rdata(21)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(22),
I1 => M_AXI_RDATA_I(54),
I2 => \^use_wrap_buffer\,
I3 => Q(22),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(54),
O => s_axi_rdata(22)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(23),
I1 => M_AXI_RDATA_I(55),
I2 => \^use_wrap_buffer\,
I3 => Q(23),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(55),
O => s_axi_rdata(23)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(24),
I1 => M_AXI_RDATA_I(56),
I2 => \^use_wrap_buffer\,
I3 => Q(24),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(56),
O => s_axi_rdata(24)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(25),
I1 => M_AXI_RDATA_I(57),
I2 => \^use_wrap_buffer\,
I3 => Q(25),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(57),
O => s_axi_rdata(25)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(26),
I1 => M_AXI_RDATA_I(58),
I2 => \^use_wrap_buffer\,
I3 => Q(26),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(58),
O => s_axi_rdata(26)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(27),
I1 => M_AXI_RDATA_I(59),
I2 => \^use_wrap_buffer\,
I3 => Q(27),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(59),
O => s_axi_rdata(27)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(28),
I1 => M_AXI_RDATA_I(60),
I2 => \^use_wrap_buffer\,
I3 => Q(28),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(60),
O => s_axi_rdata(28)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(29),
I1 => M_AXI_RDATA_I(61),
I2 => \^use_wrap_buffer\,
I3 => Q(29),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(61),
O => s_axi_rdata(29)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(2),
I1 => M_AXI_RDATA_I(34),
I2 => \^use_wrap_buffer\,
I3 => Q(2),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(34),
O => s_axi_rdata(2)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(30),
I1 => M_AXI_RDATA_I(62),
I2 => \^use_wrap_buffer\,
I3 => Q(30),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(62),
O => s_axi_rdata(30)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(31),
I1 => M_AXI_RDATA_I(63),
I2 => \^use_wrap_buffer\,
I3 => Q(31),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(63),
O => s_axi_rdata(31)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(3),
I1 => M_AXI_RDATA_I(35),
I2 => \^use_wrap_buffer\,
I3 => Q(3),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(35),
O => s_axi_rdata(3)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(4),
I1 => M_AXI_RDATA_I(36),
I2 => \^use_wrap_buffer\,
I3 => Q(4),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(36),
O => s_axi_rdata(4)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(5),
I1 => M_AXI_RDATA_I(37),
I2 => \^use_wrap_buffer\,
I3 => Q(5),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(37),
O => s_axi_rdata(5)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(6),
I1 => M_AXI_RDATA_I(38),
I2 => \^use_wrap_buffer\,
I3 => Q(6),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(38),
O => s_axi_rdata(6)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(7),
I1 => M_AXI_RDATA_I(39),
I2 => \^use_wrap_buffer\,
I3 => Q(7),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(39),
O => s_axi_rdata(7)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(8),
I1 => M_AXI_RDATA_I(40),
I2 => \^use_wrap_buffer\,
I3 => Q(8),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(40),
O => s_axi_rdata(8)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => M_AXI_RDATA_I(9),
I1 => M_AXI_RDATA_I(41),
I2 => \^use_wrap_buffer\,
I3 => Q(9),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
I5 => Q(41),
O => s_axi_rdata(9)
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F100F1000000"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => \^use_wrap_buffer_reg_0\,
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[0]_0\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(8),
I5 => s_axi_rlast_INST_0_i_3_n_0,
O => \^s_axi_rlast\
);
s_axi_rlast_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEEEFEFFFFFFFF"
)
port map (
I0 => s_axi_rlast_INST_0_i_4_n_0,
I1 => s_axi_rlast_INST_0_i_5_n_0,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7),
I5 => s_axi_rlast_INST_0_i_6_n_0,
O => \^use_wrap_buffer_reg_0\
);
s_axi_rlast_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^first_word_reg_0\(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(11),
O => s_axi_rlast_INST_0_i_3_n_0
);
s_axi_rlast_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4),
O => s_axi_rlast_INST_0_i_4_n_0
);
s_axi_rlast_INST_0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(6),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
O => s_axi_rlast_INST_0_i_5_n_0
);
s_axi_rlast_INST_0_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050500030"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(2),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => \^first_mi_word_q\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(3),
O => s_axi_rlast_INST_0_i_6_n_0
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(0),
I1 => \^use_wrap_buffer\,
I2 => Q(64),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(1),
I1 => \^use_wrap_buffer\,
I2 => Q(65),
O => s_axi_rresp(1)
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888888888888A"
)
port map (
I0 => s_axi_rready,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I2 => \current_word_1_reg[2]_1\,
I3 => \^use_wrap_buffer\,
I4 => \^use_wrap_buffer_reg_0\,
I5 => \^wrap_buffer_available\,
O => s_ready_i_reg
);
use_wrap_buffer_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCCBECC0CCC0C"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I1 => \^use_wrap_buffer\,
I2 => \^s_axi_rlast\,
I3 => use_wrap_buffer_i_2_n_0,
I4 => \^use_wrap_buffer_reg_0\,
I5 => \^wrap_buffer_available\,
O => use_wrap_buffer_i_1_n_0
);
use_wrap_buffer_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => mr_rvalid,
I2 => rd_cmd_valid,
I3 => s_axi_rready,
O => use_wrap_buffer_i_2_n_0
);
use_wrap_buffer_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => use_wrap_buffer_i_1_n_0,
Q => \^use_wrap_buffer\,
R => s_axi_aresetn
);
\wrap_buffer_available_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF800008888"
)
port map (
I0 => m_valid_i_reg(0),
I1 => s_axi_rready,
I2 => \^use_wrap_buffer_reg_0\,
I3 => use_wrap_buffer_i_2_n_0,
I4 => \wrap_buffer_available_i_2__0_n_0\,
I5 => \^wrap_buffer_available\,
O => \wrap_buffer_available_i_1__0_n_0\
);
\wrap_buffer_available_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => \^use_wrap_buffer_reg_0\,
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
O => \wrap_buffer_available_i_2__0_n_0\
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \wrap_buffer_available_i_1__0_n_0\,
Q => \^wrap_buffer_available\,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer is
port (
first_word_q : out STD_LOGIC;
\USE_REGISTER.M_AXI_WLAST_q_reg_0\ : out STD_LOGIC;
p_251_in : out STD_LOGIC;
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
wrap_buffer_available : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_1\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[3]_0\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
wr_cmd_valid : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer : entity is "axi_dwidth_converter_v2_1_11_w_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer is
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\ : STD_LOGIC;
signal \^use_register.m_axi_wlast_q_reg_0\ : STD_LOGIC;
signal \^use_rtl_curr_word.current_word_q_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg_0\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg_1\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg_2\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^use_rtl_length.length_counter_q_reg[3]_0\ : STD_LOGIC;
signal \^use_rtl_length.length_counter_q_reg[7]_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\ : STD_LOGIC;
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0\ : STD_LOGIC;
signal first_mi_word_q : STD_LOGIC;
signal \^first_word_q\ : STD_LOGIC;
signal \^m_axi_wlast\ : STD_LOGIC;
signal \^m_axi_wstrb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_wvalid\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_251_in\ : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal wstrb_wrap_buffer_1 : STD_LOGIC;
signal wstrb_wrap_buffer_2 : STD_LOGIC;
signal wstrb_wrap_buffer_3 : STD_LOGIC;
signal wstrb_wrap_buffer_4 : STD_LOGIC;
signal wstrb_wrap_buffer_5 : STD_LOGIC;
signal wstrb_wrap_buffer_6 : STD_LOGIC;
signal wstrb_wrap_buffer_7 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_7\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.first_mi_word_q_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.first_mi_word_q_i_6\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.first_mi_word_q_i_7\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[0]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9\ : label is "soft_lutpair47";
begin
\USE_REGISTER.M_AXI_WLAST_q_reg_0\ <= \^use_register.m_axi_wlast_q_reg_0\;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) <= \^use_rtl_curr_word.current_word_q_reg[2]_0\(2 downto 0);
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ <= \^use_rtl_length.first_mi_word_q_reg_0\;
\USE_RTL_LENGTH.first_mi_word_q_reg_1\ <= \^use_rtl_length.first_mi_word_q_reg_1\;
\USE_RTL_LENGTH.first_mi_word_q_reg_2\ <= \^use_rtl_length.first_mi_word_q_reg_2\;
\USE_RTL_LENGTH.length_counter_q_reg[3]_0\ <= \^use_rtl_length.length_counter_q_reg[3]_0\;
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ <= \^use_rtl_length.length_counter_q_reg[7]_0\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(2 downto 0) <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(2 downto 0);
first_word_q <= \^first_word_q\;
m_axi_wlast <= \^m_axi_wlast\;
m_axi_wstrb(7 downto 0) <= \^m_axi_wstrb\(7 downto 0);
m_axi_wvalid <= \^m_axi_wvalid\;
p_251_in <= \^p_251_in\;
wrap_buffer_available <= \^wrap_buffer_available\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000B847"
)
port map (
I0 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(0),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\,
I2 => Q(11),
I3 => Q(8),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0\,
I5 => \^use_rtl_length.length_counter_q_reg[3]_0\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"D000D0D000000000"
)
port map (
I0 => \^m_axi_wvalid\,
I1 => m_axi_wready,
I2 => s_axi_wvalid,
I3 => \^wrap_buffer_available\,
I4 => Q(12),
I5 => wr_cmd_valid,
O => \^use_rtl_length.first_mi_word_q_reg_2\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => Q(3),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => first_mi_word_q,
I4 => Q(4),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\
);
\USE_REGISTER.M_AXI_WLAST_q_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wlast,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \^m_axi_wlast\,
O => \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\
);
\USE_REGISTER.M_AXI_WLAST_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\,
Q => \^m_axi_wlast\,
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_REGISTER.M_AXI_WVALID_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\,
Q => \^m_axi_wvalid\,
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0),
Q => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1),
Q => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2),
Q => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[7]_0\(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.first_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wlast,
Q => \^first_word_q\,
S => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^use_rtl_curr_word.current_word_q_reg[2]_0\(2),
I1 => Q(14),
I2 => \^first_word_q\,
I3 => Q(10),
O => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^use_rtl_curr_word.current_word_q_reg[2]_0\(1),
I1 => Q(14),
I2 => \^first_word_q\,
I3 => Q(9),
O => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^use_rtl_curr_word.current_word_q_reg[2]_0\(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^use_rtl_curr_word.current_word_q_reg[2]_0\(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => \^use_rtl_curr_word.current_word_q_reg[2]_0\(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.first_mi_word_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000400000000"
)
port map (
I0 => \^use_rtl_length.first_mi_word_q_reg_0\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\,
I2 => \^use_rtl_length.first_mi_word_q_reg_1\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\,
I5 => \^use_rtl_length.first_mi_word_q_reg_2\,
O => \^p_251_in\
);
\USE_RTL_LENGTH.first_mi_word_q_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEAE"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[3]_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => first_mi_word_q,
I3 => Q(2),
O => \^use_rtl_length.first_mi_word_q_reg_0\
);
\USE_RTL_LENGTH.first_mi_word_q_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\,
I1 => Q(13),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I3 => \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\,
I4 => \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\,
I5 => \^use_rtl_length.length_counter_q_reg[7]_0\,
O => \^use_rtl_length.first_mi_word_q_reg_1\
);
\USE_RTL_LENGTH.first_mi_word_q_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
O => \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\
);
\USE_RTL_LENGTH.first_mi_word_q_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
O => \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => s_axi_wlast,
Q => first_mi_word_q,
S => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => first_mi_word_q,
I2 => Q(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA533A5"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => Q(0),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => first_mi_word_q,
I4 => Q(1),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B847"
)
port map (
I0 => Q(2),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \^use_rtl_length.length_counter_q_reg[3]_0\,
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB874B847"
)
port map (
I0 => Q(3),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I3 => \^use_rtl_length.length_counter_q_reg[3]_0\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I5 => Q(2),
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => Q(0),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => first_mi_word_q,
I4 => Q(1),
O => \^use_rtl_length.length_counter_q_reg[3]_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCAACCAAC3AAC355"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I1 => Q(4),
I2 => Q(3),
I3 => first_mi_word_q,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I5 => \^use_rtl_length.first_mi_word_q_reg_0\,
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => Q(5),
I2 => Q(4),
I3 => first_mi_word_q,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I5 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000305050003"
)
port map (
I0 => Q(2),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => \^use_rtl_length.length_counter_q_reg[3]_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => first_mi_word_q,
I5 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => Q(6),
I2 => Q(5),
I3 => first_mi_word_q,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I5 => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21DE2E2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => first_mi_word_q,
I2 => Q(7),
I3 => \^use_rtl_length.length_counter_q_reg[7]_0\,
I4 => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => Q(5),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I3 => first_mi_word_q,
I4 => Q(6),
O => \^use_rtl_length.length_counter_q_reg[7]_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000305050003"
)
port map (
I0 => Q(3),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I2 => \^use_rtl_length.first_mi_word_q_reg_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I4 => first_mi_word_q,
I5 => Q(4),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^p_251_in\,
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(0),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => p_1_in(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(1),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => p_1_in(1)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(2),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => p_1_in(2)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(3),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => p_1_in(3)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(4),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => p_1_in(4)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(5),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => p_1_in(5)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(6),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => p_1_in(6)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => s_axi_wdata(7),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => p_1_in(7)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(0),
Q => m_axi_wdata(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(1),
Q => m_axi_wdata(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(2),
Q => m_axi_wdata(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(3),
Q => m_axi_wdata(3),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(4),
Q => m_axi_wdata(4),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(5),
Q => m_axi_wdata(5),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(6),
Q => m_axi_wdata(6),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(7),
Q => m_axi_wdata(7),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I2 => \^m_axi_wstrb\(0),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0\,
Q => \^m_axi_wstrb\(0),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0\,
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0]\,
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(10),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(11),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(12),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(13),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(14),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_1,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(15),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(8),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => s_axi_wdata(9),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\,
Q => m_axi_wdata(10),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\,
Q => m_axi_wdata(11),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\,
Q => m_axi_wdata(12),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\,
Q => m_axi_wdata(13),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\,
Q => m_axi_wdata(14),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\,
Q => m_axi_wdata(15),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\,
Q => m_axi_wdata(8),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\,
Q => m_axi_wdata(9),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_1,
I2 => \^m_axi_wstrb\(1),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0\,
Q => \^m_axi_wstrb\(1),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_1,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0\,
Q => wstrb_wrap_buffer_1,
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(16),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(17),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(18),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(19),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(20),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(21),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(22),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_2,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => s_axi_wdata(23),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\,
Q => m_axi_wdata(16),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\,
Q => m_axi_wdata(17),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\,
Q => m_axi_wdata(18),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\,
Q => m_axi_wdata(19),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\,
Q => m_axi_wdata(20),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\,
Q => m_axi_wdata(21),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\,
Q => m_axi_wdata(22),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\,
Q => m_axi_wdata(23),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_2,
I2 => \^m_axi_wstrb\(2),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0\,
Q => \^m_axi_wstrb\(2),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_2,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0\,
Q => wstrb_wrap_buffer_2,
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(24),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(25),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(26),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(27),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(28),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(29),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(30),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_3,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => s_axi_wdata(31),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\,
I4 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\,
Q => m_axi_wdata(24),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\,
Q => m_axi_wdata(25),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\,
Q => m_axi_wdata(26),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\,
Q => m_axi_wdata(27),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\,
Q => m_axi_wdata(28),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\,
Q => m_axi_wdata(29),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\,
Q => m_axi_wdata(30),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\,
Q => m_axi_wdata(31),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_3,
I2 => \^m_axi_wstrb\(3),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0\,
Q => \^m_axi_wstrb\(3),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_3,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0\,
Q => wstrb_wrap_buffer_3,
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(0),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(1),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(2),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(3),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(4),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(5),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(6),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_4,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => s_axi_wdata(7),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\,
Q => m_axi_wdata(32),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\,
Q => m_axi_wdata(33),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\,
Q => m_axi_wdata(34),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\,
Q => m_axi_wdata(35),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\,
Q => m_axi_wdata(36),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\,
Q => m_axi_wdata(37),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\,
Q => m_axi_wdata(38),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\,
Q => m_axi_wdata(39),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_4,
I2 => \^m_axi_wstrb\(4),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0\,
Q => \^m_axi_wstrb\(4),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_4,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0\,
Q => wstrb_wrap_buffer_4,
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(8),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(9),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(10),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(11),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(12),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(13),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(14),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_5,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => s_axi_wdata(15),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\,
Q => m_axi_wdata(40),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\,
Q => m_axi_wdata(41),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\,
Q => m_axi_wdata(42),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\,
Q => m_axi_wdata(43),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\,
Q => m_axi_wdata(44),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\,
Q => m_axi_wdata(45),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\,
Q => m_axi_wdata(46),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\,
Q => m_axi_wdata(47),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_5,
I2 => \^m_axi_wstrb\(5),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0\,
Q => \^m_axi_wstrb\(5),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_5,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0\,
Q => wstrb_wrap_buffer_5,
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(16),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(17),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(18),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(19),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(20),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(21),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(22),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_6,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => s_axi_wdata(23),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\,
Q => m_axi_wdata(48),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\,
Q => m_axi_wdata(49),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\,
Q => m_axi_wdata(50),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\,
Q => m_axi_wdata(51),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\,
Q => m_axi_wdata(52),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\,
Q => m_axi_wdata(53),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\,
Q => m_axi_wdata(54),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\,
Q => m_axi_wdata(55),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_6,
I2 => \^m_axi_wstrb\(6),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0\,
Q => \^m_axi_wstrb\(6),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_6,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0\,
Q => wstrb_wrap_buffer_6,
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(24),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(25),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(26),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(27),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(28),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(29),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(30),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \out\,
O => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEFEA"
)
port map (
I0 => \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\,
I1 => Q(2),
I2 => first_mi_word_q,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I4 => \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\,
I5 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFDFD5"
)
port map (
I0 => Q(13),
I1 => Q(7),
I2 => first_mi_word_q,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I4 => \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0\,
I5 => \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I4 => wstrb_wrap_buffer_7,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F044F000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => s_axi_wdata(31),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9\,
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9\,
I1 => \^wrap_buffer_available\,
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\,
I4 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^use_rtl_length.first_mi_word_q_reg_0\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0\,
I4 => \^use_rtl_length.length_counter_q_reg[7]_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => first_mi_word_q,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
O => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\,
Q => m_axi_wdata(56),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\,
Q => m_axi_wdata(57),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\,
Q => m_axi_wdata(58),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\,
Q => m_axi_wdata(59),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\,
Q => m_axi_wdata(60),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\,
Q => m_axi_wdata(61),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\,
Q => m_axi_wdata(62),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\,
Q => m_axi_wdata(63),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44F4F4F4"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => wstrb_wrap_buffer_7,
I2 => \^m_axi_wstrb\(7),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0\,
Q => \^m_axi_wstrb\(7),
R => \^use_register.m_axi_wlast_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wstrb_wrap_buffer_7,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0\,
Q => wstrb_wrap_buffer_7,
R => SR(0)
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
Q => \^wrap_buffer_available\,
R => \^use_register.m_axi_wlast_q_reg_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice is
port (
s_ready_i_reg_0 : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
s_axi_arready : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 44 downto 0 );
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\ : STD_LOGIC_VECTOR ( 27 downto 0 );
signal \USE_READ.read_addr_inst/access_need_extra_word__3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst/cmd_next_word_ii__10\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arburst[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arburst[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arburst[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arburst[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_arlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal sr_araddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sr_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_arvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1__0\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1__0\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_5\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_axi_araddr[2]_INST_0_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_axi_arburst[0]_INST_0_i_2\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_axi_arburst[1]_INST_0_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_3\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_4\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_3\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_6\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_4\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_5\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_6\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_axi_arlen[7]_INST_0_i_2\ : label is "soft_lutpair72";
begin
Q(44 downto 0) <= \^q\(44 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(27 downto 0) <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(27 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
sr_arvalid <= \^sr_arvalid\;
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(10)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFAAAE"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFCECFEAAFCA8"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => sr_arsize(0),
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF888"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_4_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => s_axi_arlen_ii(1),
I3 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFEEFFFEEEEE"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => sr_arsize(0),
I3 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I4 => s_axi_arlen_ii(1),
I5 => s_axi_arlen_ii(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000022202AA"
)
port map (
I0 => sr_araddr(2),
I1 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414144414141044"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => sr_araddr(0),
I2 => s_axi_arlen_ii(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8848488848884888"
)
port map (
I0 => sr_araddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\,
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFC0000EEFC"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030200"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2228282828282828"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13),
I1 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\,
I5 => sr_araddr(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7888788877887888"
)
port map (
I0 => sr_araddr(2),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13),
I2 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0\,
I4 => s_axi_arlen_ii(1),
I5 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF08088888080"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I2 => sr_arburst(1),
I3 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I4 => sr_arburst(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => sr_araddr(0),
I1 => sr_araddr(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000100010000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888882288888828"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\,
I1 => sr_araddr(1),
I2 => sr_arsize(0),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
I5 => sr_araddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13),
I1 => \USE_READ.read_addr_inst/cmd_next_word_ii__10\(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF5FF07000A00F8"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
I5 => sr_araddr(2),
O => \USE_READ.read_addr_inst/cmd_next_word_ii__10\(2)
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100010001000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0\,
I1 => sr_araddr(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(13),
I1 => sr_araddr(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5554555455540000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\,
I1 => sr_araddr(2),
I2 => sr_araddr(1),
I3 => sr_araddr(0),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"13100000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => s_axi_arlen_ii(2),
I3 => \m_axi_arburst[0]_INST_0_i_2_n_0\,
I4 => \^q\(33),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(25)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFE0000000000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \^q\(33),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(26)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(27)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(8)
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(9)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => s_axi_aresetn
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEFCCCCCCCC"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I2 => s_axi_arlen_ii(0),
I3 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => sr_araddr(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000040400"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => sr_araddr(0),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => sr_arsize(0),
I5 => s_axi_arlen_ii(1),
O => \m_axi_araddr[0]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFA0A0A0B0"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I2 => sr_araddr(1),
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => \m_axi_araddr[1]_INST_0_i_3_n_0\,
O => m_axi_araddr(1)
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[1]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(7),
I3 => s_axi_arlen_ii(5),
I4 => s_axi_arlen_ii(4),
O => \m_axi_araddr[1]_INST_0_i_2_n_0\
);
\m_axi_araddr[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000400044444"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => sr_araddr(1),
I2 => \m_axi_araddr[1]_INST_0_i_4_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I5 => s_axi_arlen_ii(0),
O => \m_axi_araddr[1]_INST_0_i_3_n_0\
);
\m_axi_araddr[1]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
O => \m_axi_araddr[1]_INST_0_i_4_n_0\
);
\m_axi_araddr[1]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[1]_INST_0_i_5_n_0\
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABABAB00000000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I2 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
I5 => sr_araddr(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
O => \m_axi_araddr[2]_INST_0_i_1_n_0\
);
\m_axi_araddr[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
I2 => s_axi_arlen_ii(7),
I3 => s_axi_arlen_ii(6),
I4 => s_axi_arlen_ii(3),
I5 => s_axi_arlen_ii(2),
O => \m_axi_araddr[2]_INST_0_i_2_n_0\
);
\m_axi_araddr[2]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
O => \m_axi_araddr[2]_INST_0_i_3_n_0\
);
\m_axi_arburst[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00004000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => \^q\(33),
I2 => s_axi_arlen_ii(2),
I3 => sr_arburst(1),
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => \m_axi_arburst[0]_INST_0_i_1_n_0\,
O => m_axi_arburst(0)
);
\m_axi_arburst[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF10000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \^q\(33),
I3 => sr_arburst(1),
I4 => \m_axi_arburst[0]_INST_0_i_2_n_0\,
I5 => sr_arburst(0),
O => \m_axi_arburst[0]_INST_0_i_1_n_0\
);
\m_axi_arburst[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"03030700"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
O => \m_axi_arburst[0]_INST_0_i_2_n_0\
);
\m_axi_arburst[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFDFF00FF00"
)
port map (
I0 => \^q\(33),
I1 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arburst[1]_INST_0_i_1_n_0\,
I3 => \m_axi_arburst[1]_INST_0_i_2_n_0\,
I4 => sr_arburst(0),
I5 => sr_arburst(1),
O => m_axi_arburst(1)
);
\m_axi_arburst[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(0),
I2 => sr_arsize(2),
O => \m_axi_arburst[1]_INST_0_i_1_n_0\
);
\m_axi_arburst[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00A000BB00B100"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => sr_arburst(1),
I4 => sr_arsize(1),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arburst[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00151515FFEAEAEA"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(0),
I5 => \USE_READ.read_addr_inst/access_need_extra_word__3\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(0)
);
\m_axi_arlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_1_n_0\
);
\m_axi_arlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF8F8F800000000"
)
port map (
I0 => sr_araddr(2),
I1 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
I5 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
O => \USE_READ.read_addr_inst/access_need_extra_word__3\
);
\m_axi_arlen[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_3_n_0\
);
\m_axi_arlen[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030202"
)
port map (
I0 => sr_araddr(2),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"151515EA15EA15EA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[1]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(1)
);
\m_axi_arlen[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFAAEAAA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_5_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I2 => sr_araddr(0),
I3 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I4 => sr_araddr(2),
I5 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
O => \m_axi_arlen[1]_INST_0_i_1_n_0\
);
\m_axi_arlen[1]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_araddr(0),
I3 => sr_araddr(2),
I4 => s_axi_arlen_ii(0),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_10_n_0\
);
\m_axi_arlen[1]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(2),
O => \m_axi_arlen[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E888"
)
port map (
I0 => sr_araddr(2),
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(1),
I4 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
O => \m_axi_arlen[1]_INST_0_i_3_n_0\
);
\m_axi_arlen[1]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => s_axi_arlen_ii(2),
I5 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[1]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F4000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_9_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_10_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I5 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
O => \m_axi_arlen[1]_INST_0_i_5_n_0\
);
\m_axi_arlen[1]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_6_n_0\
);
\m_axi_arlen[1]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_7_n_0\
);
\m_axi_arlen[1]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000A800"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_8_n_0\
);
\m_axi_arlen[1]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A800A800A800"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(2),
I2 => s_axi_arlen_ii(2),
I3 => s_axi_arlen_ii(1),
I4 => sr_araddr(0),
I5 => s_axi_arlen_ii(0),
O => \m_axi_arlen[1]_INST_0_i_9_n_0\
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555566656665666"
)
port map (
I0 => \m_axi_arlen[2]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[2]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(2)
);
\m_axi_arlen[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEAAAEAAAEAAA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
O => \m_axi_arlen[2]_INST_0_i_1_n_0\
);
\m_axi_arlen[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[2]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00003777FFFFC888"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I5 => \m_axi_arlen[3]_INST_0_i_3_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(3)
);
\m_axi_arlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5540400000000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I1 => sr_araddr(1),
I2 => s_axi_arlen_ii(0),
I3 => s_axi_arlen_ii(1),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
O => \m_axi_arlen[3]_INST_0_i_1_n_0\
);
\m_axi_arlen[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040400040000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => sr_araddr(2),
I4 => s_axi_arlen_ii(2),
I5 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
O => \m_axi_arlen[3]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_7_n_0\,
O => \m_axi_arlen[3]_INST_0_i_3_n_0\
);
\m_axi_arlen[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arburst(1),
I2 => sr_arburst(0),
I3 => \^q\(33),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[3]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \m_axi_arlen[3]_INST_0_i_5_n_0\
);
\m_axi_arlen[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA80"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_araddr(0),
I3 => s_axi_arlen_ii(1),
O => \m_axi_arlen[3]_INST_0_i_6_n_0\
);
\m_axi_arlen[3]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[3]_INST_0_i_7_n_0\
);
\m_axi_arlen[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555566656665666"
)
port map (
I0 => \m_axi_arlen[4]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[4]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(4),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(4)
);
\m_axi_arlen[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F0800000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
O => \m_axi_arlen[4]_INST_0_i_1_n_0\
);
\m_axi_arlen[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[4]_INST_0_i_2_n_0\
);
\m_axi_arlen[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"07070F0F07F8F0F0"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \m_axi_arlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(5),
I5 => \m_axi_arlen[5]_INST_0_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(5)
);
\m_axi_arlen[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0000000A0000000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(4),
I4 => s_axi_arlen_ii(5),
I5 => s_axi_arlen_ii(7),
O => \m_axi_arlen[5]_INST_0_i_1_n_0\
);
\m_axi_arlen[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A0C00"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[5]_INST_0_i_2_n_0\
);
\m_axi_arlen[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"556A6A6A"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(7),
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(6),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(6)
);
\m_axi_arlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0000000A0000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(4),
I4 => s_axi_arlen_ii(5),
I5 => s_axi_arlen_ii(7),
O => \m_axi_arlen[6]_INST_0_i_1_n_0\
);
\m_axi_arlen[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000100010000000"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => \^q\(33),
I4 => sr_arburst(0),
I5 => sr_arburst(1),
O => \m_axi_arlen[6]_INST_0_i_2_n_0\
);
\m_axi_arlen[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(4),
I3 => s_axi_arlen_ii(5),
I4 => s_axi_arlen_ii(7),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]\(7)
);
\m_axi_arlen[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \^q\(33),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => s_axi_arlen_ii(3),
O => \m_axi_arlen[7]_INST_0_i_1_n_0\
);
\m_axi_arlen[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \m_axi_arlen[7]_INST_0_i_2_n_0\
);
\m_axi_arlen[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => sr_araddr(2),
I1 => s_axi_arlen_ii(0),
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => sr_arsize(1),
O => \m_axi_arlen[7]_INST_0_i_3_n_0\
);
\m_axi_arsize[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFFFFFFE"
)
port map (
I0 => sr_arsize(0),
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => m_axi_arsize(0)
);
\m_axi_arsize[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFFFFFFE"
)
port map (
I0 => sr_arsize(1),
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => m_axi_arsize(1)
);
\m_axi_arsize[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000100000000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(1),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => sr_arsize(2),
O => m_axi_arsize(2)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_arvalid\,
O => \m_payload_i[31]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(0),
Q => sr_araddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(10),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(11),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(12),
Q => \^q\(9),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(13),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(14),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(15),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(16),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(17),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(18),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(19),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(1),
Q => sr_araddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(20),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(21),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(22),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(23),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(24),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(25),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(26),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(27),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(28),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(29),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(2),
Q => sr_araddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(30),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(31),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(32),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(33),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(34),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(35),
Q => sr_arsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(36),
Q => sr_arsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(37),
Q => sr_arsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(38),
Q => sr_arburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(39),
Q => sr_arburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(3),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(40),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(41),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(42),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(43),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(44),
Q => s_axi_arlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(45),
Q => s_axi_arlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(46),
Q => s_axi_arlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(47),
Q => s_axi_arlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(48),
Q => s_axi_arlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(49),
Q => s_axi_arlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(4),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(50),
Q => s_axi_arlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(51),
Q => s_axi_arlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(52),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(53),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(54),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(55),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(56),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(57),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(58),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(5),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(59),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(60),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(6),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(7),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(8),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(9),
Q => \^q\(6),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B100"
)
port map (
I0 => \^s_axi_arready\,
I1 => cmd_push_block_reg,
I2 => s_axi_arvalid,
I3 => \^s_ready_i_reg_0\,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_arvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"DD5F0000"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => cmd_push_block_reg,
I2 => s_axi_arvalid,
I3 => \^sr_arvalid\,
I4 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_arready\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 is
port (
\aresetn_d_reg[1]\ : out STD_LOGIC;
sr_awvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
\m_axi_awregion[3]\ : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ : out STD_LOGIC;
\in\ : out STD_LOGIC_VECTOR ( 24 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 is
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\ : STD_LOGIC;
signal \^aresetn_d_reg[1]\ : STD_LOGIC;
signal \^in\ : STD_LOGIC_VECTOR ( 24 downto 0 );
signal \m_axi_awaddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \^m_axi_awregion[3]\ : STD_LOGIC_VECTOR ( 41 downto 0 );
signal \m_payload_i[31]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[3]\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[4]\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[5]\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal s_axi_awlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal sr_awaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sr_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_awvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_axi_awaddr[0]_INST_0_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_axi_awaddr[1]_INST_0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_axi_awaddr[1]_INST_0_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_3\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_4\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_3\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_4\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_8\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_axi_awburst[0]_INST_0\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_axi_awburst[1]_INST_0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_3\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_axi_awlen[1]_INST_0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_axi_awlen[2]_INST_0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_axi_awlen[5]_INST_0_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_awlen[6]_INST_0_i_3\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_axi_awlen[6]_INST_0_i_4\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_10\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_13\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_14\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_2\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_4\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_6\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_axi_awsize[0]_INST_0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_axi_awsize[1]_INST_0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_axi_awsize[2]_INST_0\ : label is "soft_lutpair93";
begin
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\;
\aresetn_d_reg[1]\ <= \^aresetn_d_reg[1]\;
\in\(24 downto 0) <= \^in\(24 downto 0);
\m_axi_awregion[3]\(41 downto 0) <= \^m_axi_awregion[3]\(41 downto 0);
s_axi_awready <= \^s_axi_awready\;
sr_awvalid <= \^sr_awvalid\;
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
O => \^in\(10)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAE"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => s_axi_awlen_ii(0),
I2 => sr_awsize(0),
I3 => sr_awsize(2),
I4 => sr_awsize(1),
O => \^in\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAFEBA"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(0),
I4 => sr_awsize(1),
I5 => sr_awsize(2),
O => \^in\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
O => \^in\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => sr_awaddr(2),
O => \^in\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"380038003800C800"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => sr_awaddr(0),
I2 => s_axi_awlen_ii(0),
I3 => \^in\(8),
I4 => sr_awburst(0),
I5 => sr_awburst(1),
O => \^in\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414141141414144"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I2 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I3 => sr_awburst(1),
I4 => sr_awburst(0),
I5 => sr_awaddr(1),
O => \^in\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00100000FFFFFFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => \m_axi_awaddr[2]_INST_0_i_4_n_0\,
I2 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I3 => \m_axi_awaddr[5]_INST_0_i_4_n_0\,
I4 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I5 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000E00000000000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => sr_awaddr(0),
I3 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I4 => sr_awsize(0),
I5 => s_axi_awlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"03EFFC00FC0003EF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_6_n_0\,
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\,
O => \^in\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => sr_awaddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001010100"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(0),
I4 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I5 => sr_awaddr(0),
O => \^in\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4441444144414444"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => sr_awaddr(1),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
I5 => sr_awaddr(0),
O => \^in\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4015151515404040"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\,
I2 => sr_awaddr(1),
I3 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I4 => sr_awsize(1),
I5 => sr_awaddr(2),
O => \^in\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"000E"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000200020000"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(0),
I5 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
O => \^in\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awaddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
O => \^in\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awaddr(2),
I1 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
O => \^in\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
O => \^in\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
O => \^in\(8)
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
O => \^in\(9)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '1',
Q => \^aresetn_d_reg[1]\,
R => s_axi_aresetn
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A2AAAAAA"
)
port map (
I0 => sr_awaddr(0),
I1 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(0),
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
I5 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(0)
);
\m_axi_awaddr[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(1),
O => \m_axi_awaddr[0]_INST_0_i_1_n_0\
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"008A"
)
port map (
I0 => sr_awaddr(1),
I1 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF1B"
)
port map (
I0 => sr_awsize(0),
I1 => s_axi_awlen_ii(1),
I2 => s_axi_awlen_ii(0),
I3 => sr_awsize(1),
I4 => sr_awsize(2),
O => \m_axi_awaddr[1]_INST_0_i_1_n_0\
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88008F00"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I3 => sr_awaddr(2),
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awaddr(2)
);
\m_axi_awaddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I3 => \m_axi_awaddr[2]_INST_0_i_4_n_0\,
I4 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I5 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
O => \m_axi_awaddr[2]_INST_0_i_1_n_0\
);
\m_axi_awaddr[2]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I1 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\
);
\m_axi_awaddr[2]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0033557F"
)
port map (
I0 => sr_awsize(1),
I1 => s_axi_awlen_ii(0),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(2),
O => \m_axi_awaddr[2]_INST_0_i_3_n_0\
);
\m_axi_awaddr[2]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \m_axi_awaddr[2]_INST_0_i_4_n_0\
);
\m_axi_awaddr[2]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0A0C00000A0C"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => s_axi_awlen_ii(2),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(0),
O => \m_axi_awaddr[2]_INST_0_i_5_n_0\
);
\m_axi_awaddr[2]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAEFFFFFFFFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => s_axi_awlen_ii(2),
I2 => \^in\(8),
I3 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I4 => sr_awburst(0),
I5 => sr_awburst(1),
O => \m_axi_awaddr[2]_INST_0_i_6_n_0\
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A9AAAAAA999AAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[3]\,
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I5 => \m_axi_awaddr[3]_INST_0_i_2_n_0\,
O => m_axi_awaddr(3)
);
\m_axi_awaddr[3]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(3),
O => \m_axi_awaddr[3]_INST_0_i_1_n_0\
);
\m_axi_awaddr[3]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"53"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => s_axi_awlen_ii(1),
I2 => sr_awsize(0),
O => \m_axi_awaddr[3]_INST_0_i_2_n_0\
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[4]\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_payload_i_reg_n_0_[3]\,
I3 => \m_axi_awaddr[4]_INST_0_i_1_n_0\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(4)
);
\m_axi_awaddr[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAA2A28AAAAAAA"
)
port map (
I0 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(0),
O => \m_axi_awaddr[4]_INST_0_i_1_n_0\
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA6AAAAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[5]\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => \m_payload_i_reg_n_0_[3]\,
I4 => \m_payload_i_reg_n_0_[4]\,
I5 => \m_axi_awaddr[5]_INST_0_i_3_n_0\,
O => m_axi_awaddr(5)
);
\m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101010101000"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_4_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_5_n_0\,
I2 => \m_axi_awaddr[5]_INST_0_i_6_n_0\,
I3 => sr_awaddr(2),
I4 => sr_awaddr(1),
I5 => sr_awaddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\
);
\m_axi_awaddr[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAA8"
)
port map (
I0 => \^m_axi_awregion[3]\(30),
I1 => s_axi_awlen_ii(0),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(2),
I4 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I5 => \^in\(24),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\
);
\m_axi_awaddr[5]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"30233323"
)
port map (
I0 => \m_axi_awaddr[3]_INST_0_i_2_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_8_n_0\,
I2 => sr_awsize(2),
I3 => sr_awsize(1),
I4 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
O => \m_axi_awaddr[5]_INST_0_i_3_n_0\
);
\m_axi_awaddr[5]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
O => \m_axi_awaddr[5]_INST_0_i_4_n_0\
);
\m_axi_awaddr[5]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => s_axi_awlen_ii(2),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(0),
I4 => \^m_axi_awregion[3]\(30),
O => \m_axi_awaddr[5]_INST_0_i_5_n_0\
);
\m_axi_awaddr[5]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_awlen_ii(6),
I1 => s_axi_awlen_ii(5),
I2 => s_axi_awlen_ii(3),
I3 => s_axi_awlen_ii(4),
I4 => s_axi_awlen_ii(7),
I5 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
O => \m_axi_awaddr[5]_INST_0_i_6_n_0\
);
\m_axi_awaddr[5]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_axi_awlen_ii(3),
I1 => s_axi_awlen_ii(7),
I2 => s_axi_awlen_ii(6),
I3 => s_axi_awlen_ii(4),
I4 => s_axi_awlen_ii(5),
O => \m_axi_awaddr[5]_INST_0_i_7_n_0\
);
\m_axi_awaddr[5]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"000A000C"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => s_axi_awlen_ii(5),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
O => \m_axi_awaddr[5]_INST_0_i_8_n_0\
);
\m_axi_awaddr[5]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFAFAEECCEA88"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(1),
I2 => s_axi_awlen_ii(0),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(1),
I5 => sr_awsize(2),
O => \m_axi_awaddr[5]_INST_0_i_9_n_0\
);
\m_axi_awburst[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awburst(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awburst(0)
);
\m_axi_awburst[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awburst(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awburst(1)
);
\m_axi_awlen[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9599"
)
port map (
I0 => \m_axi_awlen[0]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[0]_INST_0_i_2_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => s_axi_awlen_ii(0),
O => \^in\(0)
);
\m_axi_awlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF0000E000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I3 => sr_awaddr(2),
I4 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
O => \m_axi_awlen[0]_INST_0_i_1_n_0\
);
\m_axi_awlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"575F5757575F5F5F"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I1 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I2 => \m_axi_awlen[0]_INST_0_i_3_n_0\,
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[0]_INST_0_i_2_n_0\
);
\m_axi_awlen[0]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \m_axi_awlen[0]_INST_0_i_3_n_0\
);
\m_axi_awlen[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"959A"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => s_axi_awlen_ii(1),
O => \^in\(1)
);
\m_axi_awlen[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1FF2E00"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I4 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
O => \^in\(2)
);
\m_axi_awlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08880800F777F7FF"
)
port map (
I0 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I4 => s_axi_awlen_ii(1),
I5 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
O => \^in\(3)
);
\m_axi_awlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCDFCFDFFCDFFFD"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => sr_awsize(1),
I4 => s_axi_awlen_ii(3),
I5 => s_axi_awlen_ii(2),
O => \m_axi_awlen[3]_INST_0_i_1_n_0\
);
\m_axi_awlen[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I1 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
O => \^in\(4)
);
\m_axi_awlen[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFF00008000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
O => \^in\(5)
);
\m_axi_awlen[5]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00003222"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I2 => sr_awaddr(2),
I3 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
O => \m_axi_awlen[5]_INST_0_i_1_n_0\
);
\m_axi_awlen[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"2E"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
O => \m_axi_awlen[5]_INST_0_i_2_n_0\
);
\m_axi_awlen[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000DFFFFFFF"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I2 => \m_axi_awlen[6]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_1_n_0\,
O => \^in\(6)
);
\m_axi_awlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055004000000000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
I2 => sr_awaddr(2),
I3 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I5 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
O => \m_axi_awlen[6]_INST_0_i_1_n_0\
);
\m_axi_awlen[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FACACACACACACACA"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => \m_axi_awaddr[5]_INST_0_i_8_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => sr_awsize(1),
I4 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[6]_INST_0_i_2_n_0\
);
\m_axi_awlen[6]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I1 => sr_awburst(1),
I2 => sr_awburst(0),
O => \m_axi_awlen[6]_INST_0_i_3_n_0\
);
\m_axi_awlen[6]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(0),
O => \m_axi_awlen[6]_INST_0_i_4_n_0\
);
\m_axi_awlen[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00040000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[7]_INST_0_i_3_n_0\,
I3 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_6_n_0\,
O => \^in\(7)
);
\m_axi_awlen[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF3FFFF55555555"
)
port map (
I0 => s_axi_awlen_ii(6),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(7),
I5 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => \m_axi_awlen[7]_INST_0_i_1_n_0\
);
\m_axi_awlen[7]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"E000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I3 => sr_awaddr(2),
O => \m_axi_awlen[7]_INST_0_i_10_n_0\
);
\m_axi_awlen[7]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDD1111D1DD"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[7]_INST_0_i_13_n_0\,
I3 => s_axi_awlen_ii(2),
I4 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_15_n_0\,
O => \m_axi_awlen[7]_INST_0_i_11_n_0\
);
\m_axi_awlen[7]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF3F3F5F5F0FF"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => s_axi_awlen_ii(5),
I2 => sr_awsize(2),
I3 => s_axi_awlen_ii(6),
I4 => sr_awsize(1),
I5 => sr_awsize(0),
O => \m_axi_awlen[7]_INST_0_i_12_n_0\
);
\m_axi_awlen[7]_INST_0_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
O => \m_axi_awlen[7]_INST_0_i_13_n_0\
);
\m_axi_awlen[7]_INST_0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"03080008"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(6),
O => \m_axi_awlen[7]_INST_0_i_14_n_0\
);
\m_axi_awlen[7]_INST_0_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"3530353535353535"
)
port map (
I0 => s_axi_awlen_ii(3),
I1 => s_axi_awlen_ii(1),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
I5 => s_axi_awlen_ii(2),
O => \m_axi_awlen[7]_INST_0_i_15_n_0\
);
\m_axi_awlen[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[7]_INST_0_i_7_n_0\,
O => \m_axi_awlen[7]_INST_0_i_2_n_0\
);
\m_axi_awlen[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF5F7FFFFFFFF"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I2 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I3 => \m_axi_awlen[7]_INST_0_i_10_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
I5 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
O => \m_axi_awlen[7]_INST_0_i_3_n_0\
);
\m_axi_awlen[7]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_12_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => s_axi_awlen_ii(3),
O => \m_axi_awlen[7]_INST_0_i_4_n_0\
);
\m_axi_awlen[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E222EEEEE222E222"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \^in\(10),
I3 => s_axi_awlen_ii(6),
I4 => \m_axi_awlen[7]_INST_0_i_13_n_0\,
I5 => s_axi_awlen_ii(7),
O => \m_axi_awlen[7]_INST_0_i_5_n_0\
);
\m_axi_awlen[7]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awlen_ii(7),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => \m_axi_awlen[7]_INST_0_i_6_n_0\
);
\m_axi_awlen[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBFBB"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_14_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => sr_awsize(1),
I3 => s_axi_awlen_ii(7),
I4 => sr_awsize(0),
I5 => sr_awsize(2),
O => \m_axi_awlen[7]_INST_0_i_7_n_0\
);
\m_axi_awlen[7]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"08AE08AE08AE0808"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I1 => sr_awaddr(1),
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I3 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I4 => sr_awburst(1),
I5 => sr_awburst(0),
O => \m_axi_awlen[7]_INST_0_i_8_n_0\
);
\m_axi_awlen[7]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFAFFFBFFFBFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_5_n_0\,
I1 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I2 => sr_awburst(1),
I3 => sr_awburst(0),
I4 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I5 => sr_awaddr(2),
O => \m_axi_awlen[7]_INST_0_i_9_n_0\
);
\m_axi_awsize[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awsize(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(0)
);
\m_axi_awsize[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awsize(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(1)
);
\m_axi_awsize[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awsize(2),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(2)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_awvalid\,
O => \m_payload_i[31]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(0),
Q => sr_awaddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(10),
Q => \^m_axi_awregion[3]\(4),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(11),
Q => \^m_axi_awregion[3]\(5),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(12),
Q => \^m_axi_awregion[3]\(6),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(13),
Q => \^m_axi_awregion[3]\(7),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(14),
Q => \^m_axi_awregion[3]\(8),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(15),
Q => \^m_axi_awregion[3]\(9),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(16),
Q => \^m_axi_awregion[3]\(10),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(17),
Q => \^m_axi_awregion[3]\(11),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(18),
Q => \^m_axi_awregion[3]\(12),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(19),
Q => \^m_axi_awregion[3]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(1),
Q => sr_awaddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(20),
Q => \^m_axi_awregion[3]\(14),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(21),
Q => \^m_axi_awregion[3]\(15),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(22),
Q => \^m_axi_awregion[3]\(16),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(23),
Q => \^m_axi_awregion[3]\(17),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(24),
Q => \^m_axi_awregion[3]\(18),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(25),
Q => \^m_axi_awregion[3]\(19),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(26),
Q => \^m_axi_awregion[3]\(20),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(27),
Q => \^m_axi_awregion[3]\(21),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(28),
Q => \^m_axi_awregion[3]\(22),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(29),
Q => \^m_axi_awregion[3]\(23),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(2),
Q => sr_awaddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(30),
Q => \^m_axi_awregion[3]\(24),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(31),
Q => \^m_axi_awregion[3]\(25),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(32),
Q => \^m_axi_awregion[3]\(26),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(33),
Q => \^m_axi_awregion[3]\(27),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(34),
Q => \^m_axi_awregion[3]\(28),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(35),
Q => sr_awsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(36),
Q => sr_awsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(37),
Q => sr_awsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(38),
Q => sr_awburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(39),
Q => sr_awburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(3),
Q => \m_payload_i_reg_n_0_[3]\,
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(40),
Q => \^m_axi_awregion[3]\(29),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(41),
Q => \^m_axi_awregion[3]\(30),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(42),
Q => \^m_axi_awregion[3]\(31),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(43),
Q => \^m_axi_awregion[3]\(32),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(44),
Q => s_axi_awlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(45),
Q => s_axi_awlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(46),
Q => s_axi_awlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(47),
Q => s_axi_awlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(48),
Q => s_axi_awlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(49),
Q => s_axi_awlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(4),
Q => \m_payload_i_reg_n_0_[4]\,
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(50),
Q => s_axi_awlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(51),
Q => s_axi_awlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(52),
Q => \^m_axi_awregion[3]\(33),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(53),
Q => \^m_axi_awregion[3]\(34),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(54),
Q => \^m_axi_awregion[3]\(35),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(55),
Q => \^m_axi_awregion[3]\(36),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(56),
Q => \^m_axi_awregion[3]\(37),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(57),
Q => \^m_axi_awregion[3]\(38),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(58),
Q => \^m_axi_awregion[3]\(39),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(5),
Q => \m_payload_i_reg_n_0_[5]\,
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(59),
Q => \^m_axi_awregion[3]\(40),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(60),
Q => \^m_axi_awregion[3]\(41),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(6),
Q => \^m_axi_awregion[3]\(0),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(7),
Q => \^m_axi_awregion[3]\(1),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(8),
Q => \^m_axi_awregion[3]\(2),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(9),
Q => \^m_axi_awregion[3]\(3),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B100"
)
port map (
I0 => \^s_axi_awready\,
I1 => cmd_push_block_reg,
I2 => s_axi_awvalid,
I3 => \aresetn_d_reg[1]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^sr_awvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"DD5F0000"
)
port map (
I0 => \aresetn_d_reg[1]_0\,
I1 => cmd_push_block_reg,
I2 => s_axi_awvalid,
I3 => \^sr_awvalid\,
I4 => \^aresetn_d_reg[1]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_awready\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 66 downto 0 );
s_axi_aclk : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rvalid : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \^m_axi_rready\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^mr_rvalid\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 66 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair28";
begin
m_axi_rready <= \^m_axi_rready\;
mr_rvalid <= \^mr_rvalid\;
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => skid_buffer(65)
);
\m_payload_i[66]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast,
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(0),
Q => Q(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(10),
Q => Q(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(11),
Q => Q(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(12),
Q => Q(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(13),
Q => Q(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(14),
Q => Q(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(15),
Q => Q(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(16),
Q => Q(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(17),
Q => Q(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(18),
Q => Q(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(19),
Q => Q(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(1),
Q => Q(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(20),
Q => Q(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(21),
Q => Q(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(22),
Q => Q(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(23),
Q => Q(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(24),
Q => Q(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(25),
Q => Q(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(26),
Q => Q(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(27),
Q => Q(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(28),
Q => Q(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(29),
Q => Q(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(2),
Q => Q(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(30),
Q => Q(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(31),
Q => Q(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(32),
Q => Q(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(33),
Q => Q(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(34),
Q => Q(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(35),
Q => Q(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(36),
Q => Q(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(37),
Q => Q(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(38),
Q => Q(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(39),
Q => Q(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(3),
Q => Q(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(40),
Q => Q(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(41),
Q => Q(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(42),
Q => Q(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(43),
Q => Q(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(44),
Q => Q(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(45),
Q => Q(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(46),
Q => Q(46),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(47),
Q => Q(47),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(48),
Q => Q(48),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(49),
Q => Q(49),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(4),
Q => Q(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(50),
Q => Q(50),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(51),
Q => Q(51),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(52),
Q => Q(52),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(53),
Q => Q(53),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(54),
Q => Q(54),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(55),
Q => Q(55),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(56),
Q => Q(56),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(57),
Q => Q(57),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(58),
Q => Q(58),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(59),
Q => Q(59),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(5),
Q => Q(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(60),
Q => Q(60),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(61),
Q => Q(61),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(62),
Q => Q(62),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(63),
Q => Q(63),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(64),
Q => Q(64),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(65),
Q => Q(65),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(66),
Q => Q(66),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(6),
Q => Q(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(7),
Q => Q(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(8),
Q => Q(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => skid_buffer(9),
Q => Q(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDFDFDFD00000000"
)
port map (
I0 => \^m_axi_rready\,
I1 => m_axi_rvalid,
I2 => \^mr_rvalid\,
I3 => rd_cmd_valid,
I4 => use_wrap_buffer_reg,
I5 => \aresetn_d_reg[1]\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^mr_rvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5FFD500000000"
)
port map (
I0 => \^mr_rvalid\,
I1 => rd_cmd_valid,
I2 => use_wrap_buffer_reg,
I3 => \^m_axi_rready\,
I4 => m_axi_rvalid,
I5 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^m_axi_rready\,
R => '0'
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rlast,
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^m_axi_rready\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo is
port (
\USE_RTL_CURR_WORD.first_word_q_reg\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.current_word_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
wrap_buffer_available_reg : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg\ : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
p_251_in : in STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[0]\ : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
first_word_q : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
cmd_push_block : in STD_LOGIC;
sr_awvalid : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[5]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[3]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo;
architecture STRUCTURE of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^use_rtl_curr_word.current_word_q_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^use_rtl_curr_word.first_word_q_reg\ : STD_LOGIC;
signal \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0\ : STD_LOGIC;
signal \^use_rtl_curr_word.pre_next_word_q_reg[1]\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 2 downto 1 );
signal cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal data_Exists_I_i_2_n_0 : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal wr_cmd_complete_wrap : STD_LOGIC;
signal wr_cmd_first_word : STD_LOGIC_VECTOR ( 2 downto 1 );
signal wr_cmd_mask : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_cmd_next_word : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_cmd_offset : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_3\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2\ : label is "soft_lutpair51";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_3\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_3\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_3\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_4\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair55";
attribute SOFT_HLUTNM of data_Exists_I_i_2 : label is "soft_lutpair54";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair60";
attribute SOFT_HLUTNM of s_ready_i_i_2 : label is "soft_lutpair60";
attribute SOFT_HLUTNM of wrap_buffer_available_i_2 : label is "soft_lutpair53";
begin
Q(14 downto 0) <= \^q\(14 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\;
\USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0) <= \^use_rtl_curr_word.current_word_q_reg[2]\(2 downto 0);
\USE_RTL_CURR_WORD.first_word_q_reg\ <= \^use_rtl_curr_word.first_word_q_reg\;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ <= \^use_rtl_curr_word.pre_next_word_q_reg[1]\;
\USE_RTL_LENGTH.first_mi_word_q_reg\ <= \^use_rtl_length.first_mi_word_q_reg\;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ <= \^use_rtl_length.first_mi_word_q_reg_0\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA080000FFFFFFFF"
)
port map (
I0 => s_axi_wlast,
I1 => \USE_RTL_CURR_WORD.current_word_q_reg[0]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\,
I4 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I5 => \^use_rtl_curr_word.first_word_q_reg\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \^use_rtl_length.first_mi_word_q_reg\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg[5]\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[3]\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0\,
I4 => \^q\(13),
I5 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0001FFFF"
)
port map (
I0 => \^use_rtl_curr_word.current_word_q_reg[2]\(2),
I1 => \^use_rtl_curr_word.current_word_q_reg[2]\(1),
I2 => wr_cmd_complete_wrap,
I3 => \^use_rtl_curr_word.current_word_q_reg[2]\(0),
I4 => \^q\(13),
I5 => \^q\(14),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(2),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => cmd_step(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => wr_cmd_mask(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => wr_cmd_mask(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => wr_cmd_mask(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q => wr_cmd_offset(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => \^q\(8),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => cmd_last_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => cmd_last_word(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => wr_cmd_next_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => \^q\(9),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => \^q\(10),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => \^q\(11),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => wr_cmd_first_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => wr_cmd_first_word(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => \^q\(12),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => wr_cmd_complete_wrap,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => \^q\(13),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(14),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => cmd_step(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => cmd_step(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
D => data_Exists_I,
Q => \^use_rtl_curr_word.first_word_q_reg\,
R => s_axi_aresetn
);
\USE_REGISTER.M_AXI_WVALID_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FFFF00800080"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0\,
I2 => s_axi_wvalid,
I3 => \USE_REGISTER.M_AXI_WVALID_q_i_3_n_0\,
I4 => m_axi_wready,
I5 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
O => \USE_REGISTER.M_AXI_WVALID_q_reg\
);
\USE_REGISTER.M_AXI_WVALID_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAABAA"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\,
I1 => \^use_rtl_length.first_mi_word_q_reg\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\,
I3 => \^use_rtl_length.first_mi_word_q_reg_0\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
O => \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => wrap_buffer_available,
I1 => \^q\(12),
I2 => \^use_rtl_curr_word.first_word_q_reg\,
O => \USE_REGISTER.M_AXI_WVALID_q_i_3_n_0\
);
\USE_RTL_ADDR.addr_q[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA9A55555565"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => cmd_push_block,
I2 => sr_awvalid,
I3 => buffer_Full_q,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I5 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BF40F40B"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I1 => valid_Write,
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFF2000FFBA0045"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I2 => valid_Write,
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080800C8080"
)
port map (
I0 => data_Exists_I_i_2_n_0,
I1 => data_Exists_I,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I3 => buffer_Full_q,
I4 => sr_awvalid,
I5 => cmd_push_block,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I3 => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\,
I4 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => cmd_push_block,
I1 => sr_awvalid,
I2 => buffer_Full_q,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
O => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => s_axi_aresetn
);
\USE_RTL_CURR_WORD.current_word_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(0),
I1 => wr_cmd_next_word(0),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
O => \^use_rtl_curr_word.current_word_q_reg[2]\(0)
);
\USE_RTL_CURR_WORD.current_word_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(1),
I1 => \^q\(9),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(1),
O => \^use_rtl_curr_word.current_word_q_reg[2]\(1)
);
\USE_RTL_CURR_WORD.current_word_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(2),
I1 => \^q\(10),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2),
O => \^use_rtl_curr_word.current_word_q_reg[2]\(2)
);
\USE_RTL_CURR_WORD.first_word_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA08AA00000000"
)
port map (
I0 => s_axi_wvalid,
I1 => \^q\(12),
I2 => wrap_buffer_available,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I4 => m_axi_wready,
I5 => \^use_rtl_curr_word.first_word_q_reg\,
O => E(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002AAA2AAA80008"
)
port map (
I0 => wr_cmd_mask(0),
I1 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
I2 => \^q\(14),
I3 => first_word_q,
I4 => wr_cmd_next_word(0),
I5 => cmd_step(0),
O => D(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8882228222288828"
)
port map (
I0 => wr_cmd_mask(1),
I1 => cmd_step(1),
I2 => \^q\(9),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(1),
I5 => \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0\,
O => D(1)
);
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(14),
I1 => first_word_q,
O => \^use_rtl_curr_word.pre_next_word_q_reg[1]\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2882828228282882"
)
port map (
I0 => wr_cmd_mask(2),
I1 => cmd_step(2),
I2 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\,
I3 => cmd_step(1),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0\,
I5 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\,
O => D(2)
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => cmd_step(0),
I1 => wr_cmd_next_word(0),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
O => \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_awvalid,
I2 => cmd_push_block,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.first_mi_word_q_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"999A9995"
)
port map (
I0 => \^q\(8),
I1 => \^q\(11),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(0),
O => \^use_rtl_length.first_mi_word_q_reg_0\
);
\USE_RTL_LENGTH.first_mi_word_q_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(1),
I1 => wr_cmd_first_word(1),
I2 => first_word_q,
I3 => \^q\(14),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(1),
O => \^use_rtl_length.first_mi_word_q_reg\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00040000"
)
port map (
I0 => cmd_push_block,
I1 => sr_awvalid,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7FFFFF"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\,
Q => buffer_Full_q,
R => s_axi_aresetn
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F00"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => \^q\(13),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A200000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => wr_cmd_first_word(2),
I2 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
I5 => s_axi_wstrb(0),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"80FF"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => s_axi_wlast,
I2 => p_251_in,
I3 => \out\,
O => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005457"
)
port map (
I0 => wr_cmd_first_word(2),
I1 => first_word_q,
I2 => \^q\(14),
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"D500"
)
port map (
I0 => \^q\(13),
I1 => s_axi_wstrb(1),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A200000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => wr_cmd_first_word(2),
I2 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
I5 => s_axi_wstrb(1),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"D500"
)
port map (
I0 => \^q\(13),
I1 => s_axi_wstrb(2),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A200000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => wr_cmd_first_word(2),
I2 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
I5 => s_axi_wstrb(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"D500"
)
port map (
I0 => \^q\(13),
I1 => s_axi_wstrb(3),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A200000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => wr_cmd_first_word(2),
I2 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I4 => wr_cmd_offset(2),
I5 => s_axi_wstrb(3),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7500"
)
port map (
I0 => \^q\(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wstrb(0),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888800080"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => s_axi_wstrb(0),
I2 => wr_cmd_first_word(2),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[39]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7500"
)
port map (
I0 => \^q\(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wstrb(1),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888800080"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => s_axi_wstrb(1),
I2 => wr_cmd_first_word(2),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[47]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7500"
)
port map (
I0 => \^q\(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wstrb(2),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888800080"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => s_axi_wstrb(2),
I2 => wr_cmd_first_word(2),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[55]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFBF"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg[0]\,
I1 => \^q\(13),
I2 => \^use_rtl_length.first_mi_word_q_reg_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_1\,
I4 => \^use_rtl_length.first_mi_word_q_reg\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7500"
)
port map (
I0 => \^q\(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wstrb(3),
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"75557575FFFFFFFF"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wrap_buffer_available,
I4 => \^q\(12),
I5 => s_axi_wvalid,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888800080"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => s_axi_wstrb(3),
I2 => wr_cmd_first_word(2),
I3 => \^use_rtl_curr_word.pre_next_word_q_reg[1]\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[63]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0\,
I2 => s_axi_wvalid,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => \^q\(12),
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0)
);
cmd_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_awvalid,
I3 => m_axi_awready,
O => cmd_push_block0
);
data_Exists_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"C4C4C4C4C4CFC4C4"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0\,
I1 => data_Exists_I,
I2 => data_Exists_I_i_2_n_0,
I3 => buffer_Full_q,
I4 => sr_awvalid,
I5 => cmd_push_block,
O => next_Data_Exists
);
data_Exists_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(4),
O => data_Exists_I_i_2_n_0
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => s_axi_aresetn
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => sr_awvalid,
I1 => cmd_push_block,
I2 => buffer_Full_q,
O => m_axi_awvalid
);
s_axi_wready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAA8A8A"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wrap_buffer_available,
I4 => \^q\(12),
O => s_axi_wready
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"B000"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
I2 => m_axi_awready,
I3 => \out\,
O => s_ready_i_reg
);
wrap_buffer_available_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFAAAA"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => s_axi_wlast,
I3 => p_251_in,
I4 => wrap_buffer_available,
O => wrap_buffer_available_reg
);
wrap_buffer_available_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0\,
I1 => wrap_buffer_available,
I2 => \^q\(12),
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => s_axi_wvalid,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 is
port (
\M_AXI_RDATA_I_reg[63]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
pop_mi_data : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
first_word_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\current_word_1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC;
\M_AXI_RDATA_I_reg[63]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]\ : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
first_word : in STD_LOGIC;
\current_word_1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
mr_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
wrap_buffer_available_reg_0 : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[2]_0\ : in STD_LOGIC;
\pre_next_word_1_reg[1]\ : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
\out\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1;
architecture STRUCTURE of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rdata_i_reg[63]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10]\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17]\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18]\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8]\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9]\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal \^current_word_1_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal \data_Exists_I_i_2__0_n_0\ : STD_LOGIC;
signal \^first_word_reg\ : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal \pre_next_word_1[1]_i_2_n_0\ : STD_LOGIC;
signal \pre_next_word_1[2]_i_5_n_0\ : STD_LOGIC;
signal rd_cmd_complete_wrap : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rd_cmd_mask : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_cmd_modified : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 0 to 0 );
signal rd_cmd_offset : STD_LOGIC_VECTOR ( 2 to 2 );
signal rd_cmd_packed_wrap : STD_LOGIC;
signal s_axi_rlast_INST_0_i_7_n_0 : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \M_AXI_RDATA_I[63]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1__0\ : label is "soft_lutpair39";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \cmd_push_block_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \current_word_1[0]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \data_Exists_I_i_2__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \pre_next_word_1[1]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of s_axi_rvalid_INST_0 : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \s_ready_i_i_2__1\ : label is "soft_lutpair43";
begin
E(0) <= \^e\(0);
\M_AXI_RDATA_I_reg[63]\ <= \^m_axi_rdata_i_reg[63]\;
Q(12 downto 0) <= \^q\(12 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\;
\USE_RTL_LENGTH.first_mi_word_q_reg\ <= \^use_rtl_length.first_mi_word_q_reg\;
\current_word_1_reg[2]\(2 downto 0) <= \^current_word_1_reg[2]\(2 downto 0);
first_word_reg <= \^first_word_reg\;
\M_AXI_RDATA_I[63]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => mr_rvalid,
I1 => \^m_axi_rdata_i_reg[63]\,
I2 => first_mi_word_q,
I3 => use_wrap_buffer,
I4 => rd_cmd_packed_wrap,
O => \M_AXI_RDATA_I_reg[63]_0\(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AA02FFFFFFFF"
)
port map (
I0 => \^e\(0),
I1 => wrap_buffer_available,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[7]\,
I3 => use_wrap_buffer,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\,
I5 => \^m_axi_rdata_i_reg[63]\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01FDFE02FFFFFFFF"
)
port map (
I0 => \current_word_1_reg[2]_0\(2),
I1 => \^q\(12),
I2 => first_word,
I3 => \^q\(11),
I4 => \^q\(8),
I5 => \^first_word_reg\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => rd_cmd_mask(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => rd_cmd_mask(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => rd_cmd_mask(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q => rd_cmd_offset(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => \^q\(8),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => rd_cmd_next_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => \^q\(9),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => \^q\(10),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => rd_cmd_first_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => rd_cmd_first_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => \^q\(11),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => rd_cmd_packed_wrap,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => rd_cmd_complete_wrap,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => rd_cmd_modified,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(12),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9]\,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
D => data_Exists_I,
Q => \^m_axi_rdata_i_reg[63]\,
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA9A55555565"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => buffer_Full_q,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I5 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BF40F40B"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I1 => valid_Write,
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFF4000FFF4000B"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I1 => valid_Write,
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080800C8080"
)
port map (
I0 => \data_Exists_I_i_2__0_n_0\,
I1 => data_Exists_I,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I3 => buffer_Full_q,
I4 => sr_arvalid,
I5 => cmd_push_block,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\,
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808888888888"
)
port map (
I0 => valid_Write,
I1 => \^m_axi_rdata_i_reg[63]\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[29]_0\,
I3 => use_wrap_buffer,
I4 => wrap_buffer_available_reg_0,
I5 => \^e\(0),
O => \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => s_axi_aresetn
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_arvalid,
I2 => cmd_push_block,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.first_mi_word_q_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000808080008000"
)
port map (
I0 => mr_rvalid,
I1 => \^m_axi_rdata_i_reg[63]\,
I2 => s_axi_rready,
I3 => \^use_rtl_length.first_mi_word_q_reg\,
I4 => use_wrap_buffer,
I5 => wrap_buffer_available_reg,
O => pop_mi_data
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00040000"
)
port map (
I0 => cmd_push_block,
I1 => sr_arvalid,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7FFFFF"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\,
Q => buffer_Full_q,
R => s_axi_aresetn
);
\cmd_push_block_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => m_axi_arready,
O => cmd_push_block0
);
\current_word_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(0),
I1 => rd_cmd_next_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[2]\(0),
O => \^current_word_1_reg[2]\(0)
);
\current_word_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(1),
I1 => \^q\(9),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[2]\(1),
O => \^current_word_1_reg[2]\(1)
);
\current_word_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(2),
I1 => \^q\(10),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[2]\(2),
O => \^current_word_1_reg[2]\(2)
);
\data_Exists_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C4C4C4C4C4CFC4C4"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0\,
I1 => data_Exists_I,
I2 => \data_Exists_I_i_2__0_n_0\,
I3 => buffer_Full_q,
I4 => sr_arvalid,
I5 => cmd_push_block,
O => next_Data_Exists
);
\data_Exists_I_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(4),
O => \data_Exists_I_i_2__0_n_0\
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => s_axi_aresetn
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => sr_arvalid,
I1 => cmd_push_block,
I2 => buffer_Full_q,
O => m_axi_arvalid
);
\m_payload_i[66]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDDDDDDDDF"
)
port map (
I0 => rd_cmd_modified,
I1 => \^q\(12),
I2 => \^current_word_1_reg[2]\(2),
I3 => \^current_word_1_reg[2]\(1),
I4 => rd_cmd_complete_wrap,
I5 => \^current_word_1_reg[2]\(0),
O => \^use_rtl_length.first_mi_word_q_reg\
);
\pre_next_word_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002AAA2AAA80008"
)
port map (
I0 => rd_cmd_mask(0),
I1 => \pre_next_word_1_reg[2]\(0),
I2 => \^q\(12),
I3 => first_word,
I4 => rd_cmd_next_word(0),
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8]\,
O => D(0)
);
\pre_next_word_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8882228222288828"
)
port map (
I0 => rd_cmd_mask(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9]\,
I2 => \^q\(9),
I3 => \pre_next_word_1[1]_i_2_n_0\,
I4 => \pre_next_word_1_reg[2]\(1),
I5 => \pre_next_word_1[2]_i_5_n_0\,
O => D(1)
);
\pre_next_word_1[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(12),
I1 => first_word,
O => \pre_next_word_1[1]_i_2_n_0\
);
\pre_next_word_1[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA80"
)
port map (
I0 => s_axi_rready,
I1 => \^m_axi_rdata_i_reg[63]\,
I2 => mr_rvalid,
I3 => use_wrap_buffer,
O => \^e\(0)
);
\pre_next_word_1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2828288228828282"
)
port map (
I0 => rd_cmd_mask(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10]\,
I2 => \pre_next_word_1_reg[2]_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9]\,
I4 => \pre_next_word_1_reg[1]\,
I5 => \pre_next_word_1[2]_i_5_n_0\,
O => D(2)
);
\pre_next_word_1[2]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8]\,
I1 => rd_cmd_next_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[2]\(0),
O => \pre_next_word_1[2]_i_5_n_0\
);
\s_axi_rdata[31]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005457"
)
port map (
I0 => \^q\(11),
I1 => first_word,
I2 => \^q\(12),
I3 => \current_word_1_reg[2]_0\(2),
I4 => rd_cmd_offset(2),
O => \s_axi_rdata[31]\
);
s_axi_rlast_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE0201FD"
)
port map (
I0 => \current_word_1_reg[2]_0\(0),
I1 => \^q\(12),
I2 => first_word,
I3 => rd_cmd_first_word(0),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17]\,
I5 => s_axi_rlast_INST_0_i_7_n_0,
O => \^first_word_reg\
);
s_axi_rlast_INST_0_i_7: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18]\,
I1 => rd_cmd_first_word(1),
I2 => first_word,
I3 => \^q\(12),
I4 => \current_word_1_reg[2]_0\(1),
O => s_axi_rlast_INST_0_i_7_n_0
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^m_axi_rdata_i_reg[63]\,
I1 => mr_rvalid,
I2 => use_wrap_buffer,
O => s_axi_rvalid
);
\s_ready_i_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B000"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
I2 => m_axi_arready,
I3 => \out\,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer is
port (
wr_cmd_valid : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.current_word_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
wrap_buffer_available_reg : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg\ : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
p_251_in : in STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[0]\ : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
first_word_q : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
sr_awvalid : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[5]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[3]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer is
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
Q(14 downto 0) => Q(14 downto 0),
SR(0) => SR(0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\,
\USE_REGISTER.M_AXI_WVALID_q_reg\ => \USE_REGISTER.M_AXI_WVALID_q_reg\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
\USE_RTL_CURR_WORD.current_word_q_reg[0]\ => \USE_RTL_CURR_WORD.current_word_q_reg[0]\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0) => \USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0),
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0),
\USE_RTL_CURR_WORD.first_word_q_reg\ => wr_cmd_valid,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ => \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\ => \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0) => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_RTL_LENGTH.first_mi_word_q_reg_0\,
\USE_RTL_LENGTH.length_counter_q_reg[0]\ => \USE_RTL_LENGTH.length_counter_q_reg[0]\,
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
\USE_RTL_LENGTH.length_counter_q_reg[3]\ => \USE_RTL_LENGTH.length_counter_q_reg[3]\,
\USE_RTL_LENGTH.length_counter_q_reg[5]\ => \USE_RTL_LENGTH.length_counter_q_reg[5]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0),
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
first_word_q => first_word_q,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_wready => m_axi_wready,
\out\ => \out\,
p_251_in => p_251_in,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
s_ready_i_reg => s_ready_i_reg,
sr_awvalid => sr_awvalid,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => wrap_buffer_available_reg
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ is
port (
rd_cmd_valid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
pop_mi_data : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
first_word_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\current_word_1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC;
\M_AXI_RDATA_I_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]\ : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
first_word : in STD_LOGIC;
\current_word_1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
mr_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
wrap_buffer_available_reg_0 : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[2]_0\ : in STD_LOGIC;
\pre_next_word_1_reg[1]\ : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
\out\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\;
architecture STRUCTURE of \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ is
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
\M_AXI_RDATA_I_reg[63]\ => rd_cmd_valid,
\M_AXI_RDATA_I_reg[63]_0\(0) => \M_AXI_RDATA_I_reg[63]\(0),
Q(12 downto 0) => Q(12 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\USE_RTL_LENGTH.length_counter_q_reg[7]\ => \USE_RTL_LENGTH.length_counter_q_reg[7]\,
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
\current_word_1_reg[2]\(2 downto 0) => \current_word_1_reg[2]\(2 downto 0),
\current_word_1_reg[2]_0\(2 downto 0) => \current_word_1_reg[2]_0\(2 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg => first_word_reg,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
pop_mi_data => pop_mi_data,
\pre_next_word_1_reg[1]\ => \pre_next_word_1_reg[1]\,
\pre_next_word_1_reg[2]\(2 downto 0) => \pre_next_word_1_reg[2]\(2 downto 0),
\pre_next_word_1_reg[2]_0\ => \pre_next_word_1_reg[2]_0\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \s_axi_rdata[31]\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => s_ready_i_reg,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => wrap_buffer_available_reg,
wrap_buffer_available_reg_0 => wrap_buffer_available_reg_0
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 66 downto 0 );
s_axi_aclk : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rvalid : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice is
begin
r_pipe: entity work.\system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
Q(66 downto 0) => Q(66 downto 0),
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
rd_cmd_valid => rd_cmd_valid,
s_axi_aclk => s_axi_aclk,
use_wrap_buffer_reg => use_wrap_buffer_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
port (
s_ready_i_reg : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
sr_awvalid : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
\m_axi_awregion[3]\ : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
cmd_push_block_reg_0 : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\;
architecture STRUCTURE of \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
signal \^aresetn_d_reg[1]\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC;
begin
\aresetn_d_reg[1]\ <= \^aresetn_d_reg[1]\;
s_ready_i_reg <= \^s_ready_i_reg\;
ar_pipe: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice
port map (
Q(44 downto 0) => Q(44 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(27 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(27 downto 0),
\aresetn_d_reg[0]\ => \^aresetn_d_reg[1]\,
cmd_push_block_reg => cmd_push_block_reg,
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 0) => \s_axi_arregion[3]\(60 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => \^s_ready_i_reg\,
sr_arvalid => sr_arvalid
);
aw_pipe: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0
port map (
D(60 downto 0) => D(60 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ => \in\(24),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ => \in\(25),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \in\(26),
\aresetn_d_reg[1]\ => \^aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \^s_ready_i_reg\,
cmd_push_block_reg => cmd_push_block_reg_0,
\in\(24) => \in\(27),
\in\(23 downto 0) => \in\(23 downto 0),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
\m_axi_awregion[3]\(41 downto 0) => \m_axi_awregion[3]\(41 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
sr_awvalid => sr_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer is
port (
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
\m_axi_awregion[3]\ : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_rready : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer : entity is "axi_dwidth_converter_v2_1_11_axi_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer is
signal \^m_axi_rlast\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_10\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_11\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_12\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_13\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_14\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_15\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_16\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_18\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_19\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_2\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_28\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_8\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_9\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_1\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_11\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_12\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_13\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_14\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_15\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_16\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_17\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_18\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_19\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_2\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_20\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_21\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_22\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_23\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_24\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_25\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_26\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_27\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_28\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_29\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_3\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_30\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_31\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_32\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_33\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_34\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_35\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_36\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_37\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_47\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_48\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_55\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_56\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_58\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_59\ : STD_LOGIC;
signal cmd_complete_wrap_i : STD_LOGIC;
signal cmd_complete_wrap_i_6 : STD_LOGIC;
signal cmd_first_word_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_first_word_i_4 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_fix_i : STD_LOGIC;
signal cmd_fix_i_8 : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 0 to 0 );
signal cmd_modified_i : STD_LOGIC;
signal cmd_modified_i_7 : STD_LOGIC;
signal cmd_packed_wrap_i : STD_LOGIC;
signal cmd_packed_wrap_i_5 : STD_LOGIC;
signal current_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal current_word_q : STD_LOGIC_VECTOR ( 2 downto 0 );
signal first_mi_word_q : STD_LOGIC;
signal first_word : STD_LOGIC;
signal first_word_q : STD_LOGIC;
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_wvalid\ : STD_LOGIC;
signal mr_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mr_rvalid : STD_LOGIC;
signal next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal next_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_102_out : STD_LOGIC;
signal p_131_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_160_out : STD_LOGIC;
signal p_189_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 22 downto 16 );
signal p_1_out_3 : STD_LOGIC_VECTOR ( 22 downto 16 );
signal p_222_out : STD_LOGIC;
signal p_251_in : STD_LOGIC;
signal p_41_out : STD_LOGIC;
signal p_71_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal pop_mi_data : STD_LOGIC;
signal pop_si_data : STD_LOGIC;
signal pre_next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_q : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 2 to 2 );
signal rd_cmd_fix : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 2 downto 1 );
signal rd_cmd_valid : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC;
signal si_register_slice_inst_n_0 : STD_LOGIC;
signal si_register_slice_inst_n_1 : STD_LOGIC;
signal si_register_slice_inst_n_109 : STD_LOGIC;
signal si_register_slice_inst_n_110 : STD_LOGIC;
signal si_register_slice_inst_n_111 : STD_LOGIC;
signal si_register_slice_inst_n_112 : STD_LOGIC;
signal si_register_slice_inst_n_113 : STD_LOGIC;
signal si_register_slice_inst_n_114 : STD_LOGIC;
signal si_register_slice_inst_n_146 : STD_LOGIC;
signal si_register_slice_inst_n_147 : STD_LOGIC;
signal si_register_slice_inst_n_148 : STD_LOGIC;
signal si_register_slice_inst_n_149 : STD_LOGIC;
signal si_register_slice_inst_n_150 : STD_LOGIC;
signal si_register_slice_inst_n_151 : STD_LOGIC;
signal sr_arvalid : STD_LOGIC;
signal sr_awvalid : STD_LOGIC;
signal use_wrap_buffer : STD_LOGIC;
signal wr_cmd_first_word : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_cmd_fix : STD_LOGIC;
signal wr_cmd_modified : STD_LOGIC;
signal wr_cmd_next_word : STD_LOGIC_VECTOR ( 2 downto 1 );
signal wr_cmd_packed_wrap : STD_LOGIC;
signal wr_cmd_valid : STD_LOGIC;
signal wrap_buffer_available : STD_LOGIC;
signal wrap_buffer_available_0 : STD_LOGIC;
begin
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(7 downto 0);
m_axi_wvalid <= \^m_axi_wvalid\;
s_axi_rlast <= \^s_axi_rlast\;
\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst\: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice
port map (
E(0) => \r_pipe/p_1_in\,
Q(66) => \^m_axi_rlast\,
Q(65 downto 64) => mr_rresp(1 downto 0),
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
\aresetn_d_reg[0]\ => si_register_slice_inst_n_1,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_0,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
rd_cmd_valid => rd_cmd_valid,
s_axi_aclk => s_axi_aclk,
use_wrap_buffer_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\
);
\USE_READ.gen_non_fifo_r_upsizer.read_data_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
E(0) => p_15_in,
Q(66) => \^m_axi_rlast\,
Q(65 downto 64) => mr_rresp(1 downto 0),
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2 downto 0) => next_word(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ => \USE_READ.read_addr_inst_n_3\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \USE_READ.read_addr_inst_n_18\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12) => rd_cmd_fix,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(11) => rd_cmd_first_word(2),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(10 downto 9) => rd_cmd_next_word(2 downto 1),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(8) => \USE_READ.read_addr_inst_n_8\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7) => \USE_READ.read_addr_inst_n_9\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(6) => \USE_READ.read_addr_inst_n_10\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(5) => \USE_READ.read_addr_inst_n_11\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(4) => \USE_READ.read_addr_inst_n_12\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(3) => \USE_READ.read_addr_inst_n_13\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(2) => \USE_READ.read_addr_inst_n_14\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(1) => \USE_READ.read_addr_inst_n_15\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(0) => \USE_READ.read_addr_inst_n_16\,
\USE_RTL_ADDR.addr_q_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\,
\current_word_1_reg[0]_0\ => \USE_READ.read_addr_inst_n_19\,
\current_word_1_reg[2]_0\(2 downto 0) => pre_next_word_1(2 downto 0),
\current_word_1_reg[2]_1\ => \USE_READ.read_addr_inst_n_2\,
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg_0(2 downto 0) => current_word_1(2 downto 0),
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in\,
m_valid_i_reg(0) => p_7_in,
mr_rvalid => mr_rvalid,
pop_mi_data => pop_mi_data,
\pre_next_word_1_reg[2]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\,
\pre_next_word_1_reg[2]_1\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\,
rd_cmd_valid => rd_cmd_valid,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => \^s_axi_rlast\,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_ready_i_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\,
wrap_buffer_available => wrap_buffer_available
);
\USE_READ.read_addr_inst\: entity work.\system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
E(0) => p_15_in,
\M_AXI_RDATA_I_reg[63]\(0) => p_7_in,
Q(12) => rd_cmd_fix,
Q(11) => rd_cmd_first_word(2),
Q(10 downto 9) => rd_cmd_next_word(2 downto 1),
Q(8) => \USE_READ.read_addr_inst_n_8\,
Q(7) => \USE_READ.read_addr_inst_n_9\,
Q(6) => \USE_READ.read_addr_inst_n_10\,
Q(5) => \USE_READ.read_addr_inst_n_11\,
Q(4) => \USE_READ.read_addr_inst_n_12\,
Q(3) => \USE_READ.read_addr_inst_n_13\,
Q(2) => \USE_READ.read_addr_inst_n_14\,
Q(1) => \USE_READ.read_addr_inst_n_15\,
Q(0) => \USE_READ.read_addr_inst_n_16\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_READ.read_addr_inst_n_2\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_READ.read_addr_inst_n_18\,
\USE_RTL_LENGTH.length_counter_q_reg[7]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\,
\current_word_1_reg[2]\(2 downto 0) => next_word(2 downto 0),
\current_word_1_reg[2]_0\(2 downto 0) => current_word_1(2 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg => \USE_READ.read_addr_inst_n_19\,
\in\(27) => cmd_fix_i,
\in\(26) => cmd_modified_i,
\in\(25) => cmd_complete_wrap_i,
\in\(24) => cmd_packed_wrap_i,
\in\(23 downto 21) => cmd_first_word_i(2 downto 0),
\in\(20 downto 14) => p_1_out(22 downto 16),
\in\(13) => si_register_slice_inst_n_146,
\in\(12) => si_register_slice_inst_n_147,
\in\(11) => si_register_slice_inst_n_148,
\in\(10) => si_register_slice_inst_n_149,
\in\(9) => si_register_slice_inst_n_150,
\in\(8) => si_register_slice_inst_n_151,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
pop_mi_data => pop_mi_data,
\pre_next_word_1_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\,
\pre_next_word_1_reg[2]\(2 downto 0) => pre_next_word_1(2 downto 0),
\pre_next_word_1_reg[2]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\,
rd_cmd_valid => rd_cmd_valid,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\s_axi_rdata[31]\ => \USE_READ.read_addr_inst_n_3\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => \USE_READ.read_addr_inst_n_28\,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => \^s_axi_rlast\,
wrap_buffer_available_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\
);
\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer
port map (
D(2 downto 0) => pre_next_word_2(2 downto 0),
E(0) => pop_si_data,
Q(14) => wr_cmd_fix,
Q(13) => wr_cmd_modified,
Q(12) => wr_cmd_packed_wrap,
Q(11) => wr_cmd_first_word(0),
Q(10 downto 9) => wr_cmd_next_word(2 downto 1),
Q(8) => cmd_last_word(0),
Q(7) => \USE_WRITE.write_addr_inst_n_11\,
Q(6) => \USE_WRITE.write_addr_inst_n_12\,
Q(5) => \USE_WRITE.write_addr_inst_n_13\,
Q(4) => \USE_WRITE.write_addr_inst_n_14\,
Q(3) => \USE_WRITE.write_addr_inst_n_15\,
Q(2) => \USE_WRITE.write_addr_inst_n_16\,
Q(1) => \USE_WRITE.write_addr_inst_n_17\,
Q(0) => \USE_WRITE.write_addr_inst_n_18\,
SR(0) => \USE_WRITE.write_addr_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2 downto 0) => next_word_1(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\ => \USE_WRITE.write_addr_inst_n_48\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\ => \USE_WRITE.write_addr_inst_n_47\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\ => \USE_WRITE.write_addr_inst_n_19\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ => \USE_WRITE.write_addr_inst_n_21\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\ => \USE_WRITE.write_addr_inst_n_24\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\ => \USE_WRITE.write_addr_inst_n_26\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\ => \USE_WRITE.write_addr_inst_n_28\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\ => \USE_WRITE.write_addr_inst_n_30\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\ => \USE_WRITE.write_addr_inst_n_32\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\ => \USE_WRITE.write_addr_inst_n_34\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\ => \USE_WRITE.write_addr_inst_n_36\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ => \USE_WRITE.write_addr_inst_n_2\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \USE_WRITE.write_addr_inst_n_20\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0\ => \USE_WRITE.write_addr_inst_n_23\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1\ => \USE_WRITE.write_addr_inst_n_25\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2\ => \USE_WRITE.write_addr_inst_n_27\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3\ => \USE_WRITE.write_addr_inst_n_29\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4\ => \USE_WRITE.write_addr_inst_n_31\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5\ => \USE_WRITE.write_addr_inst_n_33\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6\ => \USE_WRITE.write_addr_inst_n_35\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7\ => \USE_WRITE.write_addr_inst_n_55\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ => \USE_WRITE.write_addr_inst_n_22\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_WRITE.write_addr_inst_n_58\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ => \USE_WRITE.write_addr_inst_n_59\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\(0) => \USE_WRITE.write_addr_inst_n_37\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0) => p_41_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3\(0) => p_71_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4\(0) => p_102_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5\(0) => p_131_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6\(0) => p_160_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7\(0) => p_189_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8\(0) => p_222_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9\ => \USE_WRITE.write_addr_inst_n_3\,
\USE_REGISTER.M_AXI_WLAST_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => pre_next_word_q(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14\,
\USE_RTL_LENGTH.first_mi_word_q_reg_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15\,
\USE_RTL_LENGTH.first_mi_word_q_reg_2\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16\,
\USE_RTL_LENGTH.length_counter_q_reg[3]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20\,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(2 downto 0) => current_word_q(2 downto 0),
first_word_q => first_word_q,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => \^m_axi_wvalid\,
\out\ => \out\,
p_251_in => p_251_in,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_valid => wr_cmd_valid,
wrap_buffer_available => wrap_buffer_available_0
);
\USE_WRITE.write_addr_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer
port map (
D(2 downto 0) => pre_next_word_2(2 downto 0),
E(0) => pop_si_data,
Q(14) => wr_cmd_fix,
Q(13) => wr_cmd_modified,
Q(12) => wr_cmd_packed_wrap,
Q(11) => wr_cmd_first_word(0),
Q(10 downto 9) => wr_cmd_next_word(2 downto 1),
Q(8) => cmd_last_word(0),
Q(7) => \USE_WRITE.write_addr_inst_n_11\,
Q(6) => \USE_WRITE.write_addr_inst_n_12\,
Q(5) => \USE_WRITE.write_addr_inst_n_13\,
Q(4) => \USE_WRITE.write_addr_inst_n_14\,
Q(3) => \USE_WRITE.write_addr_inst_n_15\,
Q(2) => \USE_WRITE.write_addr_inst_n_16\,
Q(1) => \USE_WRITE.write_addr_inst_n_17\,
Q(0) => \USE_WRITE.write_addr_inst_n_18\,
SR(0) => \USE_WRITE.write_addr_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_WRITE.write_addr_inst_n_2\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_WRITE.write_addr_inst_n_19\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17\,
\USE_REGISTER.M_AXI_WVALID_q_reg\ => \USE_WRITE.write_addr_inst_n_59\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \^m_axi_wvalid\,
\USE_RTL_CURR_WORD.current_word_q_reg[0]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0) => next_word_1(2 downto 0),
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => current_word_q(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\ => \USE_WRITE.write_addr_inst_n_22\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0) => pre_next_word_q(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_WRITE.write_addr_inst_n_47\,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_WRITE.write_addr_inst_n_48\,
\USE_RTL_LENGTH.length_counter_q_reg[0]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20\,
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14\,
\USE_RTL_LENGTH.length_counter_q_reg[3]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19\,
\USE_RTL_LENGTH.length_counter_q_reg[5]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\ => \USE_WRITE.write_addr_inst_n_3\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ => \USE_WRITE.write_addr_inst_n_35\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1\ => \USE_WRITE.write_addr_inst_n_55\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ => \USE_WRITE.write_addr_inst_n_36\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0) => p_222_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\ => \USE_WRITE.write_addr_inst_n_33\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ => \USE_WRITE.write_addr_inst_n_34\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0) => p_189_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\ => \USE_WRITE.write_addr_inst_n_31\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ => \USE_WRITE.write_addr_inst_n_32\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0) => p_160_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\ => \USE_WRITE.write_addr_inst_n_29\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ => \USE_WRITE.write_addr_inst_n_30\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0) => p_131_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\ => \USE_WRITE.write_addr_inst_n_27\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ => \USE_WRITE.write_addr_inst_n_28\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0) => p_102_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\ => \USE_WRITE.write_addr_inst_n_25\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ => \USE_WRITE.write_addr_inst_n_26\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0) => p_71_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\ => \USE_WRITE.write_addr_inst_n_23\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ => \USE_WRITE.write_addr_inst_n_24\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0) => p_41_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\ => \USE_WRITE.write_addr_inst_n_20\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ => \USE_WRITE.write_addr_inst_n_21\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0) => \USE_WRITE.write_addr_inst_n_37\,
first_word_q => first_word_q,
\in\(27) => cmd_fix_i_8,
\in\(26) => cmd_modified_i_7,
\in\(25) => cmd_complete_wrap_i_6,
\in\(24) => cmd_packed_wrap_i_5,
\in\(23 downto 21) => cmd_first_word_i_4(2 downto 0),
\in\(20 downto 14) => p_1_out_3(22 downto 16),
\in\(13) => si_register_slice_inst_n_109,
\in\(12) => si_register_slice_inst_n_110,
\in\(11) => si_register_slice_inst_n_111,
\in\(10) => si_register_slice_inst_n_112,
\in\(9) => si_register_slice_inst_n_113,
\in\(8) => si_register_slice_inst_n_114,
\in\(7 downto 0) => \^m_axi_awlen\(7 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_wready => m_axi_wready,
\out\ => \out\,
p_251_in => p_251_in,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
s_ready_i_reg => \USE_WRITE.write_addr_inst_n_56\,
sr_awvalid => sr_awvalid,
wr_cmd_valid => wr_cmd_valid,
wrap_buffer_available => wrap_buffer_available_0,
wrap_buffer_available_reg => \USE_WRITE.write_addr_inst_n_58\
);
si_register_slice_inst: entity work.\system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\
port map (
D(60 downto 0) => D(60 downto 0),
Q(44 downto 0) => Q(44 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(27) => cmd_fix_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(26) => cmd_modified_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(25) => cmd_complete_wrap_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(24) => cmd_packed_wrap_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(23 downto 21) => cmd_first_word_i(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(20 downto 14) => p_1_out(22 downto 16),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(13) => si_register_slice_inst_n_146,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(12) => si_register_slice_inst_n_147,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(11) => si_register_slice_inst_n_148,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(10) => si_register_slice_inst_n_149,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(9) => si_register_slice_inst_n_150,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(8) => si_register_slice_inst_n_151,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
\aresetn_d_reg[1]\ => si_register_slice_inst_n_1,
cmd_push_block_reg => \USE_READ.read_addr_inst_n_28\,
cmd_push_block_reg_0 => \USE_WRITE.write_addr_inst_n_56\,
\in\(27) => cmd_fix_i_8,
\in\(26) => cmd_modified_i_7,
\in\(25) => cmd_complete_wrap_i_6,
\in\(24) => cmd_packed_wrap_i_5,
\in\(23 downto 21) => cmd_first_word_i_4(2 downto 0),
\in\(20 downto 14) => p_1_out_3(22 downto 16),
\in\(13) => si_register_slice_inst_n_109,
\in\(12) => si_register_slice_inst_n_110,
\in\(11) => si_register_slice_inst_n_111,
\in\(10) => si_register_slice_inst_n_112,
\in\(9) => si_register_slice_inst_n_113,
\in\(8) => si_register_slice_inst_n_114,
\in\(7 downto 0) => \^m_axi_awlen\(7 downto 0),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
\m_axi_awregion[3]\(41 downto 0) => \m_axi_awregion[3]\(41 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 0) => \s_axi_arregion[3]\(60 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg => si_register_slice_inst_n_0,
sr_arvalid => sr_arvalid,
sr_awvalid => sr_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_top is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_RATIO : integer;
attribute C_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "axi_dwidth_converter_v2_1_11_top";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 16;
end system_auto_us_0_axi_dwidth_converter_v2_1_11_top;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
begin
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^s_axi_bready\ <= s_axi_bready;
m_axi_bready <= \^s_axi_bready\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rid(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_upsizer.gen_full_upsizer.axi_upsizer_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer
port map (
D(60 downto 57) => s_axi_awregion(3 downto 0),
D(56 downto 53) => s_axi_awqos(3 downto 0),
D(52) => s_axi_awlock(0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 40) => s_axi_awcache(3 downto 0),
D(39 downto 38) => s_axi_awburst(1 downto 0),
D(37 downto 35) => s_axi_awsize(2 downto 0),
D(34 downto 32) => s_axi_awprot(2 downto 0),
D(31 downto 0) => s_axi_awaddr(31 downto 0),
Q(44 downto 41) => m_axi_arregion(3 downto 0),
Q(40 downto 37) => m_axi_arqos(3 downto 0),
Q(36) => m_axi_arlock(0),
Q(35 downto 32) => m_axi_arcache(3 downto 0),
Q(31 downto 29) => m_axi_arprot(2 downto 0),
Q(28 downto 0) => m_axi_araddr(31 downto 3),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awready => m_axi_awready,
\m_axi_awregion[3]\(41 downto 38) => m_axi_awregion(3 downto 0),
\m_axi_awregion[3]\(37 downto 34) => m_axi_awqos(3 downto 0),
\m_axi_awregion[3]\(33) => m_axi_awlock(0),
\m_axi_awregion[3]\(32 downto 29) => m_axi_awcache(3 downto 0),
\m_axi_awregion[3]\(28 downto 26) => m_axi_awprot(2 downto 0),
\m_axi_awregion[3]\(25 downto 0) => m_axi_awaddr(31 downto 6),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => m_axi_wvalid,
\out\ => s_axi_aresetn,
s_axi_aclk => s_axi_aclk,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 57) => s_axi_arregion(3 downto 0),
\s_axi_arregion[3]\(56 downto 53) => s_axi_arqos(3 downto 0),
\s_axi_arregion[3]\(52) => s_axi_arlock(0),
\s_axi_arregion[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arregion[3]\(43 downto 40) => s_axi_arcache(3 downto 0),
\s_axi_arregion[3]\(39 downto 38) => s_axi_arburst(1 downto 0),
\s_axi_arregion[3]\(37 downto 35) => s_axi_arsize(2 downto 0),
\s_axi_arregion[3]\(34 downto 32) => s_axi_arprot(2 downto 0),
\s_axi_arregion[3]\(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_us_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_us_0 : entity is "system_auto_us_0,axi_dwidth_converter_v2_1_11_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_us_0 : entity is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
end system_auto_us_0;
architecture STRUCTURE of system_auto_us_0 is
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of inst : label is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of inst : label is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of inst : label is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of inst : label is 1;
attribute C_RATIO : integer;
attribute C_RATIO of inst : label is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of inst : label is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of inst : label is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of inst : label is 16;
begin
inst: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_top
port map (
m_axi_aclk => '0',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => '0',
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl
|
1
|
70096
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:42:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_ref_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0_vga_sync_ref is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
start : out STD_LOGIC;
active : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_ref_0_0_vga_sync_ref : entity is "vga_sync_ref";
end system_vga_sync_ref_0_0_vga_sync_ref;
architecture STRUCTURE of system_vga_sync_ref_0_0_vga_sync_ref is
signal \^active\ : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_6_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_6_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_6_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_10_n_0\ : STD_LOGIC;
signal \counter[31]_i_11_n_0\ : STD_LOGIC;
signal \counter[31]_i_12_n_0\ : STD_LOGIC;
signal \counter[31]_i_13_n_0\ : STD_LOGIC;
signal \counter[31]_i_14_n_0\ : STD_LOGIC;
signal \counter[31]_i_15_n_0\ : STD_LOGIC;
signal \counter[31]_i_16_n_0\ : STD_LOGIC;
signal \counter[31]_i_17_n_0\ : STD_LOGIC;
signal \counter[31]_i_18_n_0\ : STD_LOGIC;
signal \counter[31]_i_19_n_0\ : STD_LOGIC;
signal \counter[31]_i_1_n_0\ : STD_LOGIC;
signal \counter[31]_i_2_n_0\ : STD_LOGIC;
signal \counter[31]_i_4_n_0\ : STD_LOGIC;
signal \counter[31]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_7_n_0\ : STD_LOGIC;
signal \counter[31]_i_8_n_0\ : STD_LOGIC;
signal \counter[31]_i_9_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_6_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_2\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_3\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_5\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_6\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \h_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^start\ : STD_LOGIC;
signal start_i_1_n_0 : STD_LOGIC;
signal start_i_2_n_0 : STD_LOGIC;
signal start_i_3_n_0 : STD_LOGIC;
signal start_i_4_n_0 : STD_LOGIC;
signal start_i_5_n_0 : STD_LOGIC;
signal start_i_6_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_10_n_0\ : STD_LOGIC;
signal \state[1]_i_11_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_6_n_0\ : STD_LOGIC;
signal \state[1]_i_7_n_0\ : STD_LOGIC;
signal \state[1]_i_8_n_0\ : STD_LOGIC;
signal \state[1]_i_9_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg[9]_i_10_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_9_n_0\ : STD_LOGIC;
signal \v_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[31]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[31]_i_15\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \counter[31]_i_18\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count_reg[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_8\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of start_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of start_i_6 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_7\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_8\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_9\ : label is "soft_lutpair8";
begin
active <= \^active\;
start <= \^start\;
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000002FFFE"
)
port map (
I0 => \^active\,
I1 => active_i_2_n_0,
I2 => \v_count_reg[9]_i_1_n_0\,
I3 => start_i_2_n_0,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_1_n_0\,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => counter(25),
I2 => counter(26),
I3 => counter(24),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => \counter[31]_i_7_n_0\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => \^active\,
R => '0'
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter(0),
O => p_2_in(0)
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(10)
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(11)
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(12)
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(12),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(11),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(10),
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(9),
O => \counter[12]_i_6_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(13)
);
\counter[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(14)
);
\counter[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(15)
);
\counter[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(16)
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(16),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(15),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(14),
O => \counter[16]_i_5_n_0\
);
\counter[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(13),
O => \counter[16]_i_6_n_0\
);
\counter[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(17)
);
\counter[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(18)
);
\counter[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(19)
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(1)
);
\counter[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(20)
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(20),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(19),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(18),
O => \counter[20]_i_5_n_0\
);
\counter[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(17),
O => \counter[20]_i_6_n_0\
);
\counter[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(21)
);
\counter[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(22)
);
\counter[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(23)
);
\counter[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(24)
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(24),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(23),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(22),
O => \counter[24]_i_5_n_0\
);
\counter[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(21),
O => \counter[24]_i_6_n_0\
);
\counter[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(25)
);
\counter[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(26)
);
\counter[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(27)
);
\counter[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(28)
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(28),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(27),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(26),
O => \counter[28]_i_5_n_0\
);
\counter[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(25),
O => \counter[28]_i_6_n_0\
);
\counter[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(29)
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(2)
);
\counter[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(30)
);
\counter[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => vsync,
I1 => rst,
O => \counter[31]_i_1_n_0\
);
\counter[31]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(24),
I1 => counter(26),
I2 => counter(25),
O => \counter[31]_i_10_n_0\
);
\counter[31]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(31),
O => \counter[31]_i_11_n_0\
);
\counter[31]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(30),
O => \counter[31]_i_12_n_0\
);
\counter[31]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(29),
O => \counter[31]_i_13_n_0\
);
\counter[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_14_n_0\
);
\counter[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(31),
I1 => counter(30),
I2 => counter(29),
O => \counter[31]_i_15_n_0\
);
\counter[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFFFFFFFFFF"
)
port map (
I0 => counter(2),
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => \counter[31]_i_16_n_0\
);
\counter[31]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(4),
I1 => counter(8),
I2 => counter(6),
I3 => counter(5),
O => \counter[31]_i_17_n_0\
);
\counter[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(10),
I1 => counter(11),
O => \counter[31]_i_18_n_0\
);
\counter[31]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(13),
I3 => counter(12),
O => \counter[31]_i_19_n_0\
);
\counter[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \counter[31]_i_2_n_0\
);
\counter[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044404440"
)
port map (
I0 => \counter[31]_i_4_n_0\,
I1 => \counter_reg[31]_i_5_n_5\,
I2 => \counter[31]_i_6_n_0\,
I3 => \counter[31]_i_7_n_0\,
I4 => \counter[31]_i_8_n_0\,
I5 => \counter[31]_i_9_n_0\,
O => p_2_in(31)
);
\counter[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => start_i_5_n_0,
I2 => start_i_4_n_0,
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => start_i_3_n_0,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_4_n_0\
);
\counter[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFEFEFF"
)
port map (
I0 => \counter[31]_i_14_n_0\,
I1 => counter(28),
I2 => counter(27),
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_15_n_0\,
O => \counter[31]_i_6_n_0\
);
\counter[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \counter[31]_i_16_n_0\,
I1 => \counter[31]_i_17_n_0\,
I2 => counter(7),
I3 => counter(9),
I4 => \counter[31]_i_18_n_0\,
I5 => \counter[31]_i_19_n_0\,
O => \counter[31]_i_7_n_0\
);
\counter[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFBFFF"
)
port map (
I0 => \h_count_reg[9]_i_5_n_0\,
I1 => counter(3),
I2 => counter(0),
I3 => counter(7),
I4 => counter(6),
I5 => \h_count_reg[9]_i_2_n_0\,
O => \counter[31]_i_8_n_0\
);
\counter[31]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter[31]_i_19_n_0\,
I1 => counter(10),
I2 => counter(11),
I3 => counter(8),
I4 => counter(9),
O => \counter[31]_i_9_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(3)
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(4)
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(4),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(3),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(2),
O => \counter[4]_i_5_n_0\
);
\counter[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(1),
O => \counter[4]_i_6_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(5)
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(6)
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(7)
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(8)
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(8),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(7),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(6),
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(5),
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(9)
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(0),
Q => counter(0),
R => \counter[31]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(10),
Q => counter(10),
R => \counter[31]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(11),
Q => counter(11),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(12),
Q => counter(12),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2) => \counter_reg[12]_i_2_n_1\,
CO(1) => \counter_reg[12]_i_2_n_2\,
CO(0) => \counter_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter[12]_i_3_n_0\,
S(2) => \counter[12]_i_4_n_0\,
S(1) => \counter[12]_i_5_n_0\,
S(0) => \counter[12]_i_6_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(13),
Q => counter(13),
R => \counter[31]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(14),
Q => counter(14),
R => \counter[31]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(15),
Q => counter(15),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(16),
Q => counter(16),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3) => \counter_reg[16]_i_2_n_0\,
CO(2) => \counter_reg[16]_i_2_n_1\,
CO(1) => \counter_reg[16]_i_2_n_2\,
CO(0) => \counter_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_2_n_4\,
O(2) => \counter_reg[16]_i_2_n_5\,
O(1) => \counter_reg[16]_i_2_n_6\,
O(0) => \counter_reg[16]_i_2_n_7\,
S(3) => \counter[16]_i_3_n_0\,
S(2) => \counter[16]_i_4_n_0\,
S(1) => \counter[16]_i_5_n_0\,
S(0) => \counter[16]_i_6_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(17),
Q => counter(17),
R => \counter[31]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(18),
Q => counter(18),
R => \counter[31]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(19),
Q => counter(19),
R => \counter[31]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(1),
Q => counter(1),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(20),
Q => counter(20),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_2_n_0\,
CO(3) => \counter_reg[20]_i_2_n_0\,
CO(2) => \counter_reg[20]_i_2_n_1\,
CO(1) => \counter_reg[20]_i_2_n_2\,
CO(0) => \counter_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_2_n_4\,
O(2) => \counter_reg[20]_i_2_n_5\,
O(1) => \counter_reg[20]_i_2_n_6\,
O(0) => \counter_reg[20]_i_2_n_7\,
S(3) => \counter[20]_i_3_n_0\,
S(2) => \counter[20]_i_4_n_0\,
S(1) => \counter[20]_i_5_n_0\,
S(0) => \counter[20]_i_6_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(21),
Q => counter(21),
R => \counter[31]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(22),
Q => counter(22),
R => \counter[31]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(23),
Q => counter(23),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(24),
Q => counter(24),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_2_n_0\,
CO(3) => \counter_reg[24]_i_2_n_0\,
CO(2) => \counter_reg[24]_i_2_n_1\,
CO(1) => \counter_reg[24]_i_2_n_2\,
CO(0) => \counter_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_2_n_4\,
O(2) => \counter_reg[24]_i_2_n_5\,
O(1) => \counter_reg[24]_i_2_n_6\,
O(0) => \counter_reg[24]_i_2_n_7\,
S(3) => \counter[24]_i_3_n_0\,
S(2) => \counter[24]_i_4_n_0\,
S(1) => \counter[24]_i_5_n_0\,
S(0) => \counter[24]_i_6_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(25),
Q => counter(25),
R => \counter[31]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(26),
Q => counter(26),
R => \counter[31]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(27),
Q => counter(27),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(28),
Q => counter(28),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_2_n_0\,
CO(3) => \counter_reg[28]_i_2_n_0\,
CO(2) => \counter_reg[28]_i_2_n_1\,
CO(1) => \counter_reg[28]_i_2_n_2\,
CO(0) => \counter_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_2_n_4\,
O(2) => \counter_reg[28]_i_2_n_5\,
O(1) => \counter_reg[28]_i_2_n_6\,
O(0) => \counter_reg[28]_i_2_n_7\,
S(3) => \counter[28]_i_3_n_0\,
S(2) => \counter[28]_i_4_n_0\,
S(1) => \counter[28]_i_5_n_0\,
S(0) => \counter[28]_i_6_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(29),
Q => counter(29),
R => \counter[31]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(2),
Q => counter(2),
R => \counter[31]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(30),
Q => counter(30),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(31),
Q => counter(31),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\(3 downto 2),
CO(1) => \counter_reg[31]_i_5_n_2\,
CO(0) => \counter_reg[31]_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_counter_reg[31]_i_5_O_UNCONNECTED\(3),
O(2) => \counter_reg[31]_i_5_n_5\,
O(1) => \counter_reg[31]_i_5_n_6\,
O(0) => \counter_reg[31]_i_5_n_7\,
S(3) => '0',
S(2) => \counter[31]_i_11_n_0\,
S(1) => \counter[31]_i_12_n_0\,
S(0) => \counter[31]_i_13_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(3),
Q => counter(3),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(4),
Q => counter(4),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_2_n_0\,
CO(2) => \counter_reg[4]_i_2_n_1\,
CO(1) => \counter_reg[4]_i_2_n_2\,
CO(0) => \counter_reg[4]_i_2_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_2_n_4\,
O(2) => \counter_reg[4]_i_2_n_5\,
O(1) => \counter_reg[4]_i_2_n_6\,
O(0) => \counter_reg[4]_i_2_n_7\,
S(3) => \counter[4]_i_3_n_0\,
S(2) => \counter[4]_i_4_n_0\,
S(1) => \counter[4]_i_5_n_0\,
S(0) => \counter[4]_i_6_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(5),
Q => counter(5),
R => \counter[31]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(6),
Q => counter(6),
R => \counter[31]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(7),
Q => counter(7),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(8),
Q => counter(8),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_2_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(9),
Q => counter(9),
R => \counter[31]_i_1_n_0\
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_reg__0\(0),
O => \plusOp__0\(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_reg__0\(0),
I1 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(3),
I1 => \h_count_reg_reg__0\(1),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(2),
O => \plusOp__0\(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(3),
I4 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(5),
I1 => \h_count_reg_reg__0\(2),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(1),
I4 => \h_count_reg_reg__0\(3),
I5 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(6),
I1 => \h_count_reg[9]_i_7_n_0\,
I2 => \h_count_reg_reg__0\(5),
O => \plusOp__0\(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(7),
I1 => \h_count_reg_reg__0\(5),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(6),
O => \plusOp__0\(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(8),
I1 => \h_count_reg_reg__0\(6),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(5),
I4 => \h_count_reg_reg__0\(7),
O => \plusOp__0\(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDFDDDDDDDDD"
)
port map (
I0 => rst,
I1 => vsync,
I2 => \counter[31]_i_9_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \h_count_reg[9]_i_5_n_0\,
I5 => \h_count_reg[9]_i_6_n_0\,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(9),
I1 => \h_count_reg_reg__0\(7),
I2 => \h_count_reg_reg__0\(5),
I3 => \h_count_reg[9]_i_7_n_0\,
I4 => \h_count_reg_reg__0\(6),
I5 => \h_count_reg_reg__0\(8),
O => \plusOp__0\(9)
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state_reg_n_0_[0]\,
I2 => counter(6),
I3 => counter(7),
I4 => counter(0),
I5 => counter(3),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => counter(1),
I1 => counter(2),
I2 => counter(4),
I3 => counter(5),
O => \h_count_reg[9]_i_5_n_0\
);
\h_count_reg[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_5_n_0\,
I1 => counter(24),
I2 => counter(26),
I3 => counter(25),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \h_count_reg[9]_i_8_n_0\,
O => \h_count_reg[9]_i_6_n_0\
);
\h_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \h_count_reg_reg__0\(4),
I1 => \h_count_reg_reg__0\(3),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(0),
I4 => \h_count_reg_reg__0\(2),
O => \h_count_reg[9]_i_7_n_0\
);
\h_count_reg[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
O => \h_count_reg[9]_i_8_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \h_count_reg_reg__0\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \h_count_reg_reg__0\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \h_count_reg_reg__0\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \h_count_reg_reg__0\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \h_count_reg_reg__0\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \h_count_reg_reg__0\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \h_count_reg_reg__0\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \h_count_reg_reg__0\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \h_count_reg_reg__0\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \h_count_reg_reg__0\(9),
R => \h_count_reg[9]_i_1_n_0\
);
start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000220E0000"
)
port map (
I0 => \^start\,
I1 => start_i_2_n_0,
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => start_i_1_n_0
);
start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \h_count_reg[9]_i_6_n_0\,
I1 => start_i_3_n_0,
I2 => start_i_4_n_0,
I3 => start_i_5_n_0,
O => start_i_2_n_0
);
start_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(4),
I3 => counter(6),
O => start_i_3_n_0
);
start_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(3),
I1 => counter(1),
I2 => counter(2),
I3 => counter(11),
I4 => start_i_6_n_0,
O => start_i_4_n_0
);
start_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(5),
I1 => counter(13),
I2 => counter(8),
I3 => counter(9),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => start_i_5_n_0
);
start_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => counter(7),
I1 => counter(0),
I2 => counter(10),
I3 => counter(12),
O => start_i_6_n_0
);
start_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => start_i_1_n_0,
Q => \^start\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE560000"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state[1]_i_2_n_0\,
I2 => start_i_2_n_0,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E6E2"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state[1]_i_2_n_0\,
I2 => \state[1]_i_3_n_0\,
I3 => \state_reg_n_0_[0]\,
I4 => \state[1]_i_4_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(1),
O => \state[1]_i_10_n_0\
);
\state[1]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(27),
I1 => counter(28),
O => \state[1]_i_11_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444F44444444"
)
port map (
I0 => \counter[31]_i_7_n_0\,
I1 => \h_count_reg[9]_i_6_n_0\,
I2 => \state[1]_i_5_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \v_count_reg[9]_i_7_n_0\,
I1 => \v_count_reg_reg__0\(9),
I2 => \v_count_reg_reg__0\(6),
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
I5 => \v_count_reg_reg__0\(8),
O => \state[1]_i_3_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABAAAAAAAA"
)
port map (
I0 => \counter[31]_i_1_n_0\,
I1 => \state[1]_i_8_n_0\,
I2 => \state[1]_i_9_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => start_i_4_n_0,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \state[1]_i_10_n_0\,
I1 => counter(7),
I2 => counter(5),
I3 => \h_count_reg[9]_i_2_n_0\,
I4 => \state[1]_i_9_n_0\,
I5 => \v_count_reg[9]_i_9_n_0\,
O => \state[1]_i_5_n_0\
);
\state[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(25),
I1 => counter(26),
I2 => \state[1]_i_11_n_0\,
I3 => counter(16),
I4 => counter(31),
I5 => \v_count_reg[9]_i_8_n_0\,
O => \state[1]_i_6_n_0\
);
\state[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => counter(18),
I1 => counter(17),
I2 => counter(19),
I3 => \v_count_reg[9]_i_10_n_0\,
I4 => counter(24),
O => \state[1]_i_7_n_0\
);
\state[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(13),
I1 => counter(5),
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => counter(9),
I5 => counter(14),
O => \state[1]_i_8_n_0\
);
\state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(30),
I1 => counter(29),
I2 => counter(4),
I3 => counter(8),
O => \state[1]_i_9_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \v_count_reg_reg__0\(0),
O => plusOp(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \v_count_reg_reg__0\(0),
I1 => \v_count_reg_reg__0\(1),
O => plusOp(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_reg__0\(2),
I1 => \v_count_reg_reg__0\(0),
I2 => \v_count_reg_reg__0\(1),
O => plusOp(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
O => plusOp(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(4),
I1 => \v_count_reg_reg__0\(2),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(1),
I4 => \v_count_reg_reg__0\(3),
O => plusOp(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(5),
I1 => \v_count_reg_reg__0\(3),
I2 => \v_count_reg_reg__0\(1),
I3 => \v_count_reg_reg__0\(0),
I4 => \v_count_reg_reg__0\(2),
I5 => \v_count_reg_reg__0\(4),
O => plusOp(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \v_count_reg_reg__0\(6),
I1 => \v_count_reg[9]_i_7_n_0\,
I2 => \v_count_reg_reg__0\(5),
O => plusOp(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \v_count_reg_reg__0\(7),
I1 => \v_count_reg_reg__0\(5),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(6),
O => plusOp(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(8),
I1 => \v_count_reg_reg__0\(6),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
O => plusOp(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \v_count_reg[9]_i_6_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(21),
I1 => counter(20),
I2 => counter(23),
I3 => counter(22),
O => \v_count_reg[9]_i_10_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(9),
I1 => \v_count_reg_reg__0\(7),
I2 => \v_count_reg_reg__0\(8),
I3 => \v_count_reg_reg__0\(6),
I4 => \v_count_reg[9]_i_7_n_0\,
I5 => \v_count_reg_reg__0\(5),
O => plusOp(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \v_count_reg[9]_i_8_n_0\,
I1 => counter(7),
I2 => counter(8),
I3 => \h_count_reg[9]_i_5_n_0\,
I4 => \v_count_reg[9]_i_9_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(11),
I1 => counter(10),
I2 => counter(9),
I3 => counter(14),
I4 => counter(12),
I5 => counter(13),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(28),
I1 => counter(27),
I2 => counter(29),
I3 => counter(30),
I4 => counter(31),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \v_count_reg[9]_i_10_n_0\,
I1 => counter(18),
I2 => counter(19),
I3 => counter(16),
I4 => counter(17),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
I4 => \v_count_reg_reg__0\(4),
O => \v_count_reg[9]_i_7_n_0\
);
\v_count_reg[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(15),
O => \v_count_reg[9]_i_8_n_0\
);
\v_count_reg[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => counter(3),
I1 => counter(0),
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
O => \v_count_reg[9]_i_9_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(0),
Q => \v_count_reg_reg__0\(0),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(1),
Q => \v_count_reg_reg__0\(1),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(2),
Q => \v_count_reg_reg__0\(2),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(3),
Q => \v_count_reg_reg__0\(3),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(4),
Q => \v_count_reg_reg__0\(4),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(5),
Q => \v_count_reg_reg__0\(5),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(6),
Q => \v_count_reg_reg__0\(6),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(7),
Q => \v_count_reg_reg__0\(7),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(8),
Q => \v_count_reg_reg__0\(8),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(9),
Q => \v_count_reg_reg__0\(9),
R => \counter[31]_i_1_n_0\
);
\xaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(0),
Q => xaddr(0),
R => '0'
);
\xaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(1),
Q => xaddr(1),
R => '0'
);
\xaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(2),
Q => xaddr(2),
R => '0'
);
\xaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(3),
Q => xaddr(3),
R => '0'
);
\xaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(4),
Q => xaddr(4),
R => '0'
);
\xaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(5),
Q => xaddr(5),
R => '0'
);
\xaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(6),
Q => xaddr(6),
R => '0'
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(7),
Q => xaddr(7),
R => '0'
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(8),
Q => xaddr(8),
R => '0'
);
\xaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(9),
Q => xaddr(9),
R => '0'
);
\yaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(0),
Q => yaddr(0),
R => '0'
);
\yaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(1),
Q => yaddr(1),
R => '0'
);
\yaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(2),
Q => yaddr(2),
R => '0'
);
\yaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(3),
Q => yaddr(3),
R => '0'
);
\yaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(4),
Q => yaddr(4),
R => '0'
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(5),
Q => yaddr(5),
R => '0'
);
\yaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(6),
Q => yaddr(6),
R => '0'
);
\yaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(7),
Q => yaddr(7),
R => '0'
);
\yaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(8),
Q => yaddr(8),
R => '0'
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(9),
Q => yaddr(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_ref_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_ref_0_0 : entity is "system_vga_sync_ref_0_0,vga_sync_ref,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_ref_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_ref_0_0 : entity is "vga_sync_ref,Vivado 2016.4";
end system_vga_sync_ref_0_0;
architecture STRUCTURE of system_vga_sync_ref_0_0 is
begin
U0: entity work.system_vga_sync_ref_0_0_vga_sync_ref
port map (
active => active,
clk => clk,
rst => rst,
start => start,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_stub.vhdl
|
1
|
1189
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 22:11:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_stub.vhdl
-- Design : system_xlconstant_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_xlconstant_0_1 is
Port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_xlconstant_0_1;
architecture stub of system_xlconstant_0_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "dout[31:0]";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_stub.vhdl
|
1
|
1509
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 23:35:06 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_stub.vhdl
-- Design : system_zed_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_zed_vga_0_0 is
Port (
clk : in STD_LOGIC;
active : in STD_LOGIC;
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end system_zed_vga_0_0;
architecture stub of system_zed_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,active,rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "zed_vga,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/vga_address_unpack/vga_address_unpack.srcs/sources_1/new/vga_address_unpack.vhd
|
1
|
418
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_address_unpack is
port (
addr_pack : in std_logic_vector(31 downto 0);
x_addr : out std_logic_vector(9 downto 0);
y_addr : out std_logic_vector(9 downto 0)
);
end vga_address_unpack;
architecture Behavioral of vga_address_unpack is
begin
x_addr <= addr_pack(9 downto 0);
y_addr <= addr_pack(19 downto 10);
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_stub.vhdl
|
1
|
1595
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 10:58:35 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_stub.vhdl
-- Design : system_vga_hessian_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_hessian_0_0 is
Port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_vga_hessian_0_0;
architecture stub of system_vga_hessian_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_hessian,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/sim/system_rgb888_to_g8_0_0.vhd
|
4
|
3255
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_g8:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_g8_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_rgb888_to_g8_0_0;
ARCHITECTURE system_rgb888_to_g8_0_0_arch OF system_rgb888_to_g8_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_g8_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_g8 IS
PORT (
clk : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
g8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT rgb888_to_g8;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb888_to_g8
PORT MAP (
clk => clk,
rgb888 => rgb888,
g8 => g8
);
END system_rgb888_to_g8_0_0_arch;
|
mit
|
Digilent/vivado-library
|
ip/AXI_DPTI_1.0/src/AXI_S_To_DPTI_Converter.vhd
|
1
|
9941
|
------------------------------------------------------------------------------
--
-- File: AXI_S_to_DPTI_converter.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module reads data from the AXI STREAM interface and sends it to the DPTI
-- interface. It will require a 32 bit TDATA bus, 4 bit TKEEP, TVALID and TLAST
-- as inputs and it will output the TREADY signal. It uses the DPTI clock of 60 MHz
-- to perform all the operations and it will use the maximum bandwidth of the DPTI
-- interface which is 480 mbps as long as valid data is received from the AXI STREAM
-- interface. In order to achieve this, FOR loops have been used which will generate
-- combinational logic that allows the simultaneous verification of all of the 4 TKEEP
-- bits received. Along with the DPTI clock, the module also reads the PROG_TXEN
-- signal and it will generate the PROG_D bus and PROG_WRN signal. In order to control
-- the module, two AXI Lite registers are used, one for direction/control and one for
-- the lenght of the transfer, which are synchronized in the top module.
-- The module also uses a reset signal aResetTx which is generated in the top module.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;
entity AXI_S_to_DPTI_converter is
Port (
-- clock, reset and DPTI signals
pResetnTx : in std_logic;
PROG_CLK : in std_logic;
pTxe : in std_logic;
pWr : out std_logic;
pDataOut : out std_logic_vector (7 downto 0);
-- AXI Stream signals
pOutTready : out std_logic;
pInTdata : in std_logic_vector (31 downto 0);
pInTvalid : in std_logic;
pInTlast : in std_logic;
pInTkeep : in std_logic_vector (3 downto 0);
-- AXI Lite registers
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pTxLengthEmpty : out std_logic
);
end AXI_S_to_DPTI_converter;
architecture Behavioral of AXI_S_to_DPTI_converter is
--------------------------------------------------------------------------------------------------------------------------
signal pTxEnDir : std_logic := '0';
signal pLengthTxCnt : std_logic_vector (22 downto 0) := (others => '0');
signal Index : integer range 0 to 3;
signal pCtlOutTready : std_logic := '0';
signal pCtlWr : std_logic := '1';
signal pTransferInvalidFlag : std_logic := '1';
signal pAuxTdata : std_logic_vector(31 downto 0);
signal pAuxTkeep : std_logic_vector(3 downto 0) := (others => '0');
--------------------------------------------------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------------------------------------------------
pWr <= pCtlWr;
pOutTready <= pCtlOutTready;
--------------------------------------------------------------------------------------------------------------------------
pTxLengthEmpty <= '1' when pLengthTxCnt = 0 else '0'; -- we check to see if we are currently doing a tranfer. this will be a part of the AXI Lite status register
-- Generating TREADY signal which will request data from the AXI STREAM interface
pCtlOutTready <= '1' when (pAuxTkeep = "0001" or pAuxTkeep = "0010" or pAuxTkeep = "0100" or pAuxTkeep = "1000" or (pAuxTkeep = "0000" )) and pTxe = '0' and pLengthTxCnt > 0 else '0';
-- new data will be requested when we have at most one valid data byte in the current TDATA bus. other conditions are that a transfer must be in progress and the DPTI interface can accept more data
pTransferInvalidFlag <= '1' when pTxe = '1' and pCtlWr = '0' else '0'; -- detecting if a transfer has failed because the FT_TXE signal from FTDI was '1'
--------------------------------------------------------------------------------------------------------------------------
generate_WR: process (PROG_CLK, pLengthTxCnt, pResetnTx) -- PROG_WRN is generated
begin
if pResetnTx = '0' then
pCtlWr <= '1';
else if rising_edge (PROG_CLK) then
if pAuxTkeep /= 0 and pLengthTxCnt > 0 then -- check if the transfer is not finnished and there is at least one valid data byte
pCtlWr <= '0'; -- when the signal is 0 then the byte currently on the PROG_D bus is valid
else -- if valid data is not available or the transfer is completed
pCtlWr <= '1'; -- PROG_WRN is '1'
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
read_Tkeep_and_Tdata: process (PROG_CLK, pResetnTx)
variable aux_tkindex : integer;
begin
if pResetnTx = '0' then
aux_tkindex := 0;
pAuxTkeep <= (others => '0');
pAuxTdata <= (others => '0');
else if rising_edge(PROG_CLK)then
if pLengthTxCnt > 0 and pTxe = '0' and pTxEnDir = '1' then -- check to see if a transfer is in progress
if (pAuxTkeep = 0 or pAuxTkeep = 1 or pAuxTkeep = 2 or pAuxTkeep = 4 or pAuxTkeep = 8) and pInTvalid = '1' then -- check if the current set of TDATA and TKEEP contains at most one valid byte of data
pAuxTkeep <= pInTkeep; --new tkeep is read
pAuxTdata <= pInTdata; --new data is read
-- TDATA and TKEEP are used in the "generate_pDataOut" process below
else -- if more than one valid bytes exist
for Index in 3 downto 0 loop -- we use a FOR loop to check all of the bytes simultaneously
if pAuxTkeep (Index) = '1' then -- each valid byte is identified by checking TKEEP
aux_tkindex := Index;
end if;
end loop;
pAuxTkeep(aux_tkindex) <= '0'; --reset one bit at a time after sending the corresponding valid byte to the DPTI interface
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_pDataOut: process (PROG_CLK, pResetnTx)
begin
if pResetnTx = '0' then
pDataOut <= (others => '0');
pLengthTxCnt <= (others=>'0');
else if rising_edge(PROG_CLK) then
if pOvalidControl = '1' and pLengthTxCnt = 0 then -- the control bit (and the direction) can only be changed when the module is idle
pTxEnDir <= pAXI_L_Control(0); -- Reading control byte from AXI LITE register. Bit (0) sets the transfer's direction.
end if;
if pOvalidLength = '1' and pTxEnDir = '1' then -- checking if the module was enabled and if valid value is present in register
pLengthTxCnt (22 downto 0) <= pAXI_L_Length(22 downto 0); -- LENGTH register is read
end if;
if pLengthTxCnt > 0 and pTxe = '0' and pTxEnDir = '1' then -- conditions for starting transfer
for Index in 3 downto 0 loop -- the FOR loop allows us to check all of the bytes simultaneously
if pAuxTkeep (Index) = '1' then -- we identify the valid byte's position
pDataOut(7 downto 0) <= pAuxTdata((8 * (Index + 1)) -1 downto (8 * (Index))); -- the valid byte is extracted and sent to the DPTI interface
pLengthTxCnt <= pLengthTxCnt - '1'; -- since one valid byte was transferred, length is decremented
end if;
end loop;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
end Behavioral;
|
mit
|
SLongofono/digital-design-final-project
|
memory.vhd
|
1
|
911
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
port (
clk : in std_logic;
rst : in std_logic;
write : in std_logic;
address_read : in integer;
address_write : in integer;
write_data : in std_logic_vector(11 downto 0);
read_data : out std_logic_vector(11 downto 0)
);
end memory;
architecture behav of memory is
type ram is array (0 to 307199) of std_logic_vector(11 downto 0);
signal myram : ram := (others => "101010101010");
signal read_address : integer;
begin
process(clk, rst)
begin
-- **Note** Not synthesizable if a reset is added
if rising_edge(clk) then
if ('1' = write ) then
myram(address_write) <= write_data;
end if;
read_address <= address_read;
end if;
end process;
read_data <= myram(read_address);
end behav;
|
mit
|
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_streibs.vhd
|
1
|
2145
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_streibs_DSP48_6 is
port (
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(23 - 1 downto 0);
in2: in std_logic_vector(32 - 1 downto 0);
dout: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of hls_contrast_streibs_DSP48_6 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(signed(in1), 25));
b <= signed(resize(signed(in0), 18));
c <= signed(resize(signed(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 32));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_streibs is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_streibs is
component hls_contrast_streibs_DSP48_6 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_streibs_DSP48_6_U : component hls_contrast_streibs_DSP48_6
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
Digilent/vivado-library
|
ip/usb2device_v1_0/src/ULPI.vhd
|
2
|
25696
|
-------------------------------------------------------------------------------
--
-- File: ULPI.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles ULPI transmissions (NOPID, PID, EXTW, REGW, EXTR, REGR)
-- and reception
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ULPI is
Port (
Ulpi_Clk : in STD_LOGIC; --ULPI input clock. Generated by the USB PHY
reset : in STD_LOGIC; -- Reset siganl from upper layers. Resets all logic in this module
--ULPI Bus
u_Ulpi_Data : inout STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir : in STD_LOGIC;
u_Ulpi_Nxt : in STD_LOGIC;
u_Ulpi_Stp : out STD_LOGIC;
u_Ulpi_Reset : out STD_LOGIC;
--Command signals for ULPI State machine
u_Send_NOOP_CMD : in STD_LOGIC;
u_Send_NOPID_CMD : in STD_LOGIC;
u_Send_PID_CMD : in STD_LOGIC;
u_Send_EXTW_CMD : in STD_LOGIC;
u_Send_REGW_CMD : in STD_LOGIC;
u_Send_EXTR_CMD : in STD_LOGIC;
u_Send_REGR_CMD : in STD_LOGIC;
u_Send_STP_CMD : in STD_LOGIC;
u_Send_Last : in STD_LOGIC;
u_Send_Err : in STD_LOGIC;
u_USB_Mode : in STD_LOGIC;
--Interface with upper layers
u_Tx_Data : in STD_LOGIC_VECTOR (7 downto 0); -- packet data to be transmitted
u_Tx_Data_En : out STD_LOGIC; -- data strobe; indicates to the upper layers when to place valid data on tx_data
u_Tx_Pid : in STD_LOGIC_VECTOR (3 downto 0); -- PID field associated with transmit packet (PID) commands
u_Tx_Regw_Data : in STD_LOGIC_VECTOR (7 downto 0); --Register data associated with the REGW, EXTW commands
u_Tx_Reg_Addr : in STD_LOGIC_VECTOR (7 downto 0); --Immediate address associated with the REGW, EXTW commands
u_Tx_Cmd_Done : out STD_LOGIC; --NOPID, NOOP, PID, EXTW, REGW, REGR, EXTR command completed, ready for next command
u_Tx_Pid_Phase_Done : out STD_LOGIC;
u_CRC16_En : out STD_LOGIC; --indicates to upper layers to consider the current byte as part of the sequence on which CRC16 is computed
u_Ulpi_Dir_Out : out STD_LOGIC;
u_Rx_Data : out STD_LOGIC_VECTOR (7 downto 0); --data received on the ULPI bus
u_Rx_Packet_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Cmd_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Register_Data : out STD_LOGIC_VECTOR (7 downto 0); --Data received in turn of REGR_CMD or EXTW_CMD
u_Rx_Register_Data_Received : out STD_LOGIC; -- indicates if u_Rx_Register_Data is valid
--UTMI+ signals
u_LineState : out STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : out STD_LOGIC_VECTOR (1 downto 0);
u_RxEvent : out STD_LOGIC_VECTOR (1 downto 0);
u_RxActive : out STD_LOGIC;
u_ID : out STD_LOGIC;
u_Alt_Int : out STD_LOGIC;
state_ind : out STD_LOGIC_VECTOR(5 downto 0) --for debug purposes
);
end ULPI;
architecture Behavioral of ULPI is
constant TXCMD_NOOP : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant TXCMD_NOPID : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant TXCMD_PID : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant TXCMD_REGR : STD_LOGIC_VECTOR (7 downto 0) := "11101110";
constant TXCMD_REGW : STD_LOGIC_VECTOR (7 downto 0) := "10101110";
constant TXCMD_EXTR : STD_LOGIC_VECTOR (7 downto 0) := "11101111";
constant TXCMD_EXTW : STD_LOGIC_VECTOR (7 downto 0) := "10101111";
type state_type is (IDLE, SEND_STP, REGR_END, FSM_ERROR, ABORT, RECEIVE, PID_CMD, PID_DATA, PID_DATA_LAST, PID_STP, PID_DATA_ERR, PID_WAIT_J1, PID_WAIT_J2, PID_WAIT_FSEOP1, PID_WAIT_FSEOP2, PID_WAIT_HSEOP1, PID_WAIT_HSEOP2, PID_WAIT_EOP, NOPID_CMD, NOPID_DATA, NOPID_DATA_LAST, NOPID_STP, REGR_CMD1, REGR_CMD2, REGR_TURN, REGR_DATA, REGW_CMD, REGW_DATA, REGW_STP, EXTW_CMD, EXTW_ADDR, EXTW_DATA, EXTW_STP, EXTR_CMD1, EXTR_CMD2, EXTR_ADDR, EXTR_TURN, EXTR_DATA, EXTR_STP);
signal u_Ulpi_State, u_Ulpi_Next_State : state_type;
signal u_Ulpi_Dir_q : STD_LOGIC;
signal u_Ulpi_Dir_qq : STD_LOGIC;
signal u_Ulpi_Stp_Fsm : STD_LOGIC;
signal u_Txmux_Out_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Out_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal t_data_debug : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txcmd_Code : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Ctrl_8b_Commands : STD_LOGIC; --used to select TX_CMDs made up of 8 constant bits : NOPID, EXTW, EXTR on ULPI bus
signal u_Txmux_Ctrl_Extreg_Addr : STD_LOGIC; --used to select the extended register address on the ULPI bus
signal u_Txmux_Ctrl_Register_Commands : STD_LOGIC; --used to select REGW and REGR commands on the ULPI bus
signal u_Txmux_Ctrl_Data : STD_LOGIC; --used to select data bytes on ULPI bus
signal u_Txmux_Ctrl_Reg_Data : STD_LOGIC; --used to select the register data to be written on the ULPI bus
signal u_Txmux_Ctrl_PID_Command : STD_LOGIC; --used to select PID commands : 4 constant bits (0100) + 4PID bits on ULPI bus
--signal idle_state : STD_LOGIC;
signal u_Receive_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rx_CMD : STD_LOGIC;
signal u_Rx_CMD_Fsm : STD_LOGIC;
signal u_Reg_Data_Latch: STD_LOGIC;
signal u_Packet_Received: STD_LOGIC;
signal u_Rxdemux_Register_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Receive_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rxdemux_LineState : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_Vbus : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent_q : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_ID : STD_LOGIC;
signal u_Rxdemux_Alt_Int : STD_LOGIC;
signal state_ind_fsm : STD_LOGIC_VECTOR(5 downto 0);
signal debug_clk : STD_LOGIC := '0';
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of state_ind : signal is "true";
--attribute keep of state_ind : signal is "true";
--attribute mark_debug of u_Ulpi_Dir : signal is "true";
--attribute keep of u_Ulpi_Dir : signal is "true";
--attribute mark_debug of u_Ulpi_Nxt : signal is "true";
--attribute keep of u_Ulpi_Nxt : signal is "true";
--attribute mark_debug of u_Ulpi_Stp : signal is "true";
--attribute keep of u_Ulpi_Stp : signal is "true";
--attribute mark_debug of u_Receive_Data_q : signal is "true";
--attribute keep of u_Receive_Data_q : signal is "true";
--attribute mark_debug of u_Txmux_Out_Data_q : signal is "true";
--attribute keep of u_Txmux_Out_Data_q : signal is "true";
--attribute mark_debug of u_Ulpi_Stp_Fsm : signal is "true";
--attribute keep of u_Ulpi_Stp_Fsm : signal is "true";
--attribute mark_debug of debug_clk : signal is "true";
--attribute keep of debug_clk : signal is "true";
begin
u_Ulpi_Reset <= reset;
u_Ulpi_Dir_Out <= u_Ulpi_Dir_q;
u_Rx_Register_Data_Received <= u_Reg_Data_Latch;
u_Rx_Data <= u_Receive_Data_q;
u_Rx_Register_Data <= u_Rxdemux_Register_Data;
--rx_en <= rx_data_en;
u_Rxdemux_LineState <= u_Receive_Data(1 downto 0);
u_Rxdemux_Vbus <= u_Receive_Data(3 downto 2);
u_Rxdemux_RxEvent <= u_Receive_Data(5 downto 4);
u_RxEvent <= u_Rxdemux_RxEvent_q;
u_Rxdemux_ID <= u_Receive_Data(6);
u_Rxdemux_Alt_Int <= u_Receive_Data(7);
bidirbuf: for i in 0 to 7 generate
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => u_Receive_Data(i), -- Buffer output
IO => u_Ulpi_Data(i), -- Buffer inout port (connect directly to top-level port)
I => u_Txmux_Out_Data_q(i), -- Buffer input
T => u_Ulpi_Dir_q -- 3-state enable input, high=input, low=output
);
end generate;
--decide if rx_data carries data/RXCMD
u_Packet_Received <= u_Ulpi_Dir and u_Ulpi_Nxt;
u_Rx_CMD <= (u_Ulpi_Dir_q and u_Ulpi_Dir) and (not u_Ulpi_Nxt);
RXACTIVE_PROC: process (Ulpi_Clk, u_Packet_Received, u_Rxdemux_RxEvent_q, u_Ulpi_Dir_q)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0' or u_Ulpi_Dir = '0') then
u_RxActive <= '0';
elsif (u_Ulpi_Dir_q = '1' and u_Packet_Received = '1') then
u_RxActive <= '1';
end if;
end if;
end process;
STATE_CHANGE: process (Ulpi_Clk) --For debug purposes
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
debug_clk <= not debug_clk;
end if;
end process;
--ULPI output signals are registered
DATA_STP_Q_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Txmux_Out_Data_q <= (others => '0');
u_Ulpi_Stp <= '0';
else
u_Ulpi_Stp <= u_Ulpi_Stp_Fsm;
u_Txmux_Out_Data_q <= u_Txmux_Out_Data;
end if;
end if;
end process;
--register receive data/control signals (outputs to upper layers)
RX_Q_PROC: process(Ulpi_Clk)
begin
if(Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Rx_Cmd_Received <= '0';
u_Ulpi_Dir_q <= '0';
u_Ulpi_Dir_qq <= '0';
u_Rx_Packet_Received <= '0';
u_Receive_Data_q <= (others => '0');
u_LineState <= (others => '0');
u_Vbus <= (others => '0');
u_Rxdemux_RxEvent_q <= (others => '0');
u_ID <= '0';
u_Alt_Int <= '0';
u_Rxdemux_Register_Data <= (others => '0');
t_data_debug <= (others => '0');
else
t_data_debug <= u_Txmux_Out_Data;
u_Rx_Cmd_Received <= u_Rx_CMD;
u_Ulpi_Dir_q <= u_Ulpi_Dir;
u_Ulpi_Dir_qq <= u_Ulpi_Dir_q;
u_Rx_Packet_Received <= u_Packet_Received;
u_Receive_Data_q <= u_Receive_Data;
if((u_Rx_CMD = '1') and (u_Rx_CMD_Fsm = '1')) then
u_LineState <= u_Rxdemux_LineState;
u_Vbus <= u_Rxdemux_Vbus;
u_Rxdemux_RxEvent_q <= u_Rxdemux_RxEvent;
u_ID <= u_Rxdemux_ID;
u_Alt_Int <= u_Rxdemux_Alt_Int;
elsif ( u_Reg_Data_Latch = '1') then
u_Rxdemux_Register_Data <= u_Receive_Data;
end if;
end if;
end if;
end process;
--Combinational process that selects the byte to be placed on the ULPI data bus
--It can be a TX Command, Packet Data, PID, Register Address, Register Data
TXMUX_PROC: process(Ulpi_Clk, u_Txmux_Ctrl_Data, u_Txmux_Ctrl_Extreg_Addr, u_Txmux_Ctrl_PID_Command, u_Txmux_Ctrl_8b_Commands, u_Txmux_Ctrl_Register_Commands, u_Tx_Data, u_Tx_Pid, u_Txcmd_Code, u_Tx_Reg_Addr, u_Txmux_Ctrl_Reg_Data, u_Tx_Regw_Data)
begin
if(u_Txmux_Ctrl_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Data;
elsif (u_Txmux_Ctrl_PID_Command = '1') then
u_Txmux_Out_Data(3 downto 0) <= u_Tx_Pid;
u_Txmux_Out_Data(7 downto 4) <= TXCMD_PID;
elsif (u_Txmux_Ctrl_8b_Commands = '1') then
u_Txmux_Out_Data <= u_Txcmd_Code;
elsif (u_Txmux_Ctrl_Register_Commands = '1') then
u_Txmux_Out_Data(7 downto 6) <= u_Txcmd_Code(7 downto 6);
u_Txmux_Out_Data(5 downto 0) <= u_Tx_Reg_Addr(5 downto 0);
elsif (u_Txmux_Ctrl_Extreg_Addr = '1') then
u_Txmux_Out_Data <= u_Tx_Reg_Addr;
elsif (u_Txmux_Ctrl_Reg_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Regw_Data;
else
u_Txmux_Out_Data <= (others => '0');
end if;
end process;
-- ULPI State Machine. Implements the framework required for transmit commands( NOPID,
-- PID, EXTW, REGW, EXTR, REGR) and decodes received data
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Ulpi_State <= IDLE;
state_ind <= (others => '0');
else
u_Ulpi_State <= u_Ulpi_Next_State;
state_ind <= state_ind_fsm;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Ulpi_State, u_Ulpi_Dir_q, u_Receive_Data_q ,u_Rx_CMD, u_Send_Last, u_Send_Err, u_Ulpi_Dir, u_Ulpi_Dir_qq, u_USB_Mode, u_Receive_Data, u_Ulpi_Nxt, u_Send_NOPID_CMD, u_Send_PID_CMD,u_Send_REGW_CMD,u_Send_EXTW_CMD,u_Send_REGR_CMD,u_Send_EXTR_CMD,u_Send_NOOP_CMD, u_Send_STP_CMD)
begin
--declare default state for next_state to avoid latches
u_Ulpi_Next_State <= u_Ulpi_State;
state_ind_fsm <= "000000";
u_Ulpi_Stp_Fsm <= '0';
u_Txmux_Ctrl_Data <= '0';
u_Txmux_Ctrl_Reg_Data <= '0';
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Register_Commands <= '0';
u_Tx_Data_En <= '0';
u_Txmux_Ctrl_PID_Command <= '0';
u_Txcmd_Code <= (others => '0');
u_Rx_CMD_Fsm <= '0';
u_Tx_Cmd_Done <= '0';
u_CRC16_En <= '0';
u_Txmux_Ctrl_Extreg_Addr <= '0';
u_Reg_Data_Latch <= '0';
u_Tx_Pid_Phase_Done <= '0';
case (u_Ulpi_State) is
when IDLE =>
state_ind_fsm <= "000000";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= (others => '0');
if ( u_Ulpi_Dir = '0') then
if(u_Send_NOPID_CMD = '1') then
u_Ulpi_Next_State <= NOPID_CMD;
elsif (u_Send_PID_CMD = '1') then
u_Ulpi_Next_State <= PID_CMD;
elsif (u_Send_REGW_CMD = '1') then
u_Ulpi_Next_State <= REGW_CMD;
elsif (u_Send_EXTW_CMD = '1') then
u_Ulpi_Next_State <= EXTW_CMD;
elsif (u_Send_REGR_CMD = '1') then
u_Ulpi_Next_State <= REGR_CMD1;
elsif (u_Send_EXTR_CMD = '1') then
u_Ulpi_Next_State <= EXTR_CMD1;
elsif (u_Send_NOOP_CMD = '1') then
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= IDLE;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
--SEND PID_CMD -- No support for packet abort
when PID_CMD =>
state_ind_fsm <= "000001";
u_Txmux_Ctrl_PID_Command <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_PID_Command <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Tx_Data_En <= '1';
u_CRC16_En <= '1';
if (u_Send_Last = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
else
u_Tx_Pid_Phase_Done <= '1';
u_Ulpi_Next_State <= PID_DATA;
end if;
end if;
when PID_DATA =>
state_ind_fsm <= "000010";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_CRC16_En <= '1';
u_Tx_Data_En <= '1';
if (u_Send_Last = '1') then
if (u_Send_Err = '0') then
u_Ulpi_Next_State <= PID_DATA_LAST;
else
u_Ulpi_Next_State <= PID_DATA_ERR;
end if;
end if;
else
u_Tx_Data_En <= '0';
end if;
when PID_DATA_LAST =>
state_ind_fsm <= "000011";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Data <= '0';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
end if;
when PID_STP =>
state_ind_fsm <= "000100";
u_Ulpi_Next_State <= PID_WAIT_EOP;
when PID_WAIT_EOP =>
state_ind_fsm <= "000101";
--if(ulpi_dir = '1') then
if(u_USB_Mode = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
else
u_Ulpi_Next_State <= PID_WAIT_FSEOP1;
end if;
--end if;
when PID_WAIT_HSEOP1 =>
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP2;
end if;
when PID_WAIT_HSEOP2 =>
state_ind_fsm <= "000110";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data(1 downto 0) = "00") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
end if;
end if;
when PID_WAIT_FSEOP1 =>
state_ind_fsm <= "000111";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_FSEOP2;
end if;
when PID_WAIT_FSEOP2 =>
state_ind_fsm <= "001000";
if(u_Ulpi_Dir_qq = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data_q(1 downto 0) = "00") then
u_Ulpi_Next_State <= PID_WAIT_J1;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
end if;
when PID_WAIT_J1 =>
state_ind_fsm <= "001001";
if (u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_J2;
end if;
when PID_WAIT_J2 =>
state_ind_fsm <= "001010";
if(u_Receive_Data_q(1 downto 0) = "01") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
when PID_DATA_ERR =>
state_ind_fsm <= "001011";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Txcmd_Code <= (others => '1');
u_Txmux_Ctrl_8b_Commands <= '1';
u_Ulpi_Next_State <= IDLE; --The link must wait for an RX_CMD indicating a SE0 to J transition before transmitting another packet : Not implemented
--SEND NOPID
when NOPID_CMD =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001100";
u_Txcmd_Code <= TXCMD_NOPID;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Next_State <= NOPID_DATA;
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when NOPID_DATA =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001101";
u_Txmux_Ctrl_Data <= '1';
if (u_Ulpi_Nxt = '1') then
if (u_Send_Last = '1') then
u_Ulpi_Next_State <= NOPID_DATA_LAST;
end if;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_DATA_LAST =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001110";
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= NOPID_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_STP =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001111";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGW
when REGW_CMD =>
state_ind_fsm <= "010000";
u_Txcmd_Code <= TXCMD_REGW;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= REGW_DATA;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_DATA =>
state_ind_fsm <= "010001";
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= REGW_STP;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_STP =>
state_ind_fsm <= "010010";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
--SEND EXTW Not Working!
when EXTW_CMD =>
state_ind_fsm <= "010011";
u_Txcmd_Code <= TXCMD_EXTW;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTW_ADDR;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_ADDR =>
state_ind_fsm <= "010100";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTW_DATA;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_DATA =>
state_ind_fsm <= "010101";
if (u_Ulpi_Dir = '0') then
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= EXTW_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_STP =>
state_ind_fsm <= "010110";
if (u_Ulpi_Dir = '0') then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
u_Ulpi_Stp_Fsm <= '1';
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGR
when REGR_CMD1 =>
state_ind_fsm <= "010111";
u_Txcmd_Code <= TXCMD_REGR;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Ulpi_Next_State <= REGR_TURN;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_TURN =>
state_ind_fsm <= "011000";
if(u_Ulpi_Dir = '1') then
if(u_Ulpi_Nxt = '0') then
u_Reg_Data_Latch <= '1';
u_Ulpi_Next_State <= REGR_DATA;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
end if;
when REGR_DATA =>
state_ind_fsm <= "011010";
if(u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= REGR_END;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_END =>
u_Tx_Cmd_Done <= '1';
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
--SEND EXTR Not Working!
when EXTR_CMD1 =>
state_ind_fsm <= "011011";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= TXCMD_EXTR;
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTR_ADDR;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_ADDR =>
state_ind_fsm <= "011101";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTR_TURN;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_TURN =>
state_ind_fsm <= "011110";
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= EXTR_DATA;
end if;
when EXTR_DATA =>
state_ind_fsm <= "011111";
u_Tx_Cmd_Done <= '1';
u_Reg_Data_Latch <= '1';
if (u_Ulpi_Nxt = '0') then
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
end if;
--ABORT
when ABORT =>
state_ind_fsm <= "100000";
u_Ulpi_Next_State <= IDLE;
when SEND_STP =>
state_ind_fsm <= "100010";
u_Ulpi_Stp_Fsm <= '1';
if (u_Ulpi_Dir_q = '0') then
u_Ulpi_Next_State <= IDLE;
end if;
--RECEIVE
when RECEIVE =>
state_ind_fsm <= "100001";
if(u_Ulpi_Dir = '1') then
if (u_Send_STP_CMD = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= SEND_STP;
elsif(u_Rx_CMD = '1') then
u_Rx_CMD_Fsm <= '1';
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when others =>
u_Ulpi_Next_State <= IDLE;
end case;
end process;
end Behavioral;
|
mit
|
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/sub_to_adder.vhd
|
1
|
2265
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:32:17 07/10/05
-- Design Name:
-- Module Name: sub_to_adder - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sub_to_adder is
Port ( pixel_in1 : in std_logic_vector(8 downto 0);
pixel_in2 : in std_logic_vector(8 downto 0);
pixel_in3 : in std_logic_vector(8 downto 0);
pixel_in4 : in std_logic_vector(8 downto 0);
pixel_in5 : in std_logic_vector(8 downto 0);
pixel_in6 : in std_logic_vector(8 downto 0);
adder_out : out std_logic_vector(10 downto 0));
end sub_to_adder;
architecture Behavioral of sub_to_adder is
component sub_abs_component
Port ( pixel_in1 : in std_logic_vector(8 downto 0);
pixel_in2 : in std_logic_vector(8 downto 0);
sub_abs_out : out std_logic_vector(8 downto 0));
end component;
component combination
port( x1 : in std_logic_vector(8 downto 0);
x2 : in std_logic_vector(8 downto 0);
x3 : in std_logic_vector(8 downto 0);
-- x4_1 : in std_logic_vector(8 downto 0);
-- x5_1 : in std_logic_vector(8 downto 0);
Output : out std_logic_vector(10 downto 0));
end component;
signal A : std_logic_vector(8 downto 0);
signal B : std_logic_vector(8 downto 0);
signal C : std_logic_vector(8 downto 0);
begin
element1: sub_abs_component port map(
pixel_in1,
pixel_in2,
A );
element2: sub_abs_component port map(
pixel_in3,
pixel_in4,
B);
element3: sub_abs_component port map(
pixel_in5,
pixel_in6,
C);
element4: combination port map(
A,
B,
C,
adder_out);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/fifo_w8_d1_A.vhd
|
3
|
4422
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d1_A_shiftReg;
architecture rtl of fifo_w8_d1_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d1_A is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d1_A is
component fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d1_A_shiftReg : fifo_w8_d1_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/AXIvideo2Mat.vhd
|
1
|
66885
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC;
img_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_out_full_n : IN STD_LOGIC;
img_rows_V_out_write : OUT STD_LOGIC;
img_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_out_full_n : IN STD_LOGIC;
img_cols_V_out_write : OUT STD_LOGIC );
end;
architecture behav of AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal AXI_video_strm_V_data_V_0_data_out : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_payload_A : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_payload_B : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_data_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_last_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal stream_in_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
signal ap_block_pp1_stage0 : BOOLEAN;
signal exitcond_i_reg_504 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_reg_513 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
signal ap_block_pp2_stage0 : BOOLEAN;
signal eol_2_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal img_rows_V_blk_n : STD_LOGIC;
signal img_cols_V_blk_n : STD_LOGIC;
signal img_data_stream_0_V_blk_n : STD_LOGIC;
signal img_data_stream_1_V_blk_n : STD_LOGIC;
signal img_data_stream_2_V_blk_n : STD_LOGIC;
signal img_rows_V_out_blk_n : STD_LOGIC;
signal img_cols_V_out_blk_n : STD_LOGIC;
signal t_V_2_reg_278 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_i_reg_289 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_reg_301 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_i_reg_312 : STD_LOGIC_VECTOR (23 downto 0);
signal axi_last_V_3_i_reg_359 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_3_i_reg_371 : STD_LOGIC_VECTOR (23 downto 0);
signal rows_V_reg_465 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_state1 : BOOLEAN;
signal cols_V_reg_470 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_data_V_reg_475 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_last_V_reg_483 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond4_i_fu_402_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_V_fu_407_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_V_reg_499 : STD_LOGIC_VECTOR (31 downto 0);
signal exitcond_i_fu_413_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state5_pp1_stage0_iter0 : BOOLEAN;
signal ap_predicate_op71_read_state6 : BOOLEAN;
signal ap_block_state6_pp1_stage0_iter1 : BOOLEAN;
signal ap_block_pp1_stage0_11001 : BOOLEAN;
signal j_V_fu_418_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
signal brmerge_i_fu_427_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state8_pp2_stage0_iter0 : BOOLEAN;
signal ap_block_state9_pp2_stage0_iter1 : BOOLEAN;
signal ap_block_pp2_stage0_11001 : BOOLEAN;
signal ap_block_pp1_stage0_subdone : BOOLEAN;
signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_block_pp2_stage0_subdone : BOOLEAN;
signal ap_phi_mux_eol_2_i_phi_fu_351_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_i_reg_247 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal axi_data_V1_i_reg_257 : STD_LOGIC_VECTOR (23 downto 0);
signal t_V_reg_267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_phi_mux_eol_i_phi_fu_293_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_p_Val2_s_phi_fu_340_p4 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp1_iter1_p_Val2_s_reg_336 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_block_pp1_stage0_01001 : BOOLEAN;
signal sof_1_i_fu_176 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_user_V_fu_393_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_idle_pp1 : STD_LOGIC;
signal ap_enable_pp1 : STD_LOGIC;
signal ap_idle_pp2 : STD_LOGIC;
signal ap_enable_pp2 : STD_LOGIC;
signal ap_condition_515 : BOOLEAN;
begin
AXI_video_strm_V_data_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out))) then
AXI_video_strm_V_data_V_0_sel_rd <= not(AXI_video_strm_V_data_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) then
AXI_video_strm_V_data_V_0_sel_wr <= not(AXI_video_strm_V_data_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_out))) then
AXI_video_strm_V_last_V_0_sel_rd <= not(AXI_video_strm_V_last_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) then
AXI_video_strm_V_last_V_0_sel_wr <= not(AXI_video_strm_V_last_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_out))) then
AXI_video_strm_V_user_V_0_sel_rd <= not(AXI_video_strm_V_user_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) then
AXI_video_strm_V_user_V_0_sel_wr <= not(AXI_video_strm_V_user_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (exitcond_i_fu_413_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_phi_mux_eol_2_i_phi_fu_351_p4 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
axi_data_V1_i_reg_257_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_data_V1_i_reg_257 <= tmp_data_V_reg_475;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_data_V1_i_reg_257 <= axi_data_V_3_i_reg_371;
end if;
end if;
end process;
axi_data_V_1_i_reg_312_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
axi_data_V_1_i_reg_312 <= ap_phi_mux_p_Val2_s_phi_fu_340_p4;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
axi_data_V_1_i_reg_312 <= axi_data_V1_i_reg_257;
end if;
end if;
end process;
axi_data_V_3_i_reg_371_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_data_V_3_i_reg_371 <= axi_data_V_1_i_reg_312;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_data_V_3_i_reg_371 <= AXI_video_strm_V_data_V_0_data_out;
end if;
end if;
end process;
axi_last_V1_i_reg_247_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_last_V1_i_reg_247 <= tmp_last_V_reg_483;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_last_V1_i_reg_247 <= axi_last_V_3_i_reg_359;
end if;
end if;
end process;
axi_last_V_3_i_reg_359_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_last_V_3_i_reg_359 <= eol_reg_301;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_last_V_3_i_reg_359 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_2_i_reg_348_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
eol_2_i_reg_348 <= eol_i_reg_289;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
eol_2_i_reg_348 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_i_reg_289_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_i_reg_289 <= ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_i_reg_289 <= ap_const_lv1_0;
end if;
end if;
end process;
eol_reg_301_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_reg_301 <= ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_reg_301 <= axi_last_V1_i_reg_247;
end if;
end if;
end process;
sof_1_i_fu_176_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_fu_413_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
sof_1_i_fu_176 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
sof_1_i_fu_176 <= ap_const_lv1_1;
end if;
end if;
end process;
t_V_2_reg_278_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_fu_413_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
t_V_2_reg_278 <= j_V_fu_418_p2;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
t_V_2_reg_278 <= ap_const_lv32_0;
end if;
end if;
end process;
t_V_reg_267_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
t_V_reg_267 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
t_V_reg_267 <= i_V_reg_499;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_A)) then
AXI_video_strm_V_data_V_0_payload_A <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_B)) then
AXI_video_strm_V_data_V_0_payload_B <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_A)) then
AXI_video_strm_V_last_V_0_payload_A <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_B)) then
AXI_video_strm_V_last_V_0_payload_B <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_A)) then
AXI_video_strm_V_user_V_0_payload_A <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_B)) then
AXI_video_strm_V_user_V_0_payload_B <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_fu_413_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
brmerge_i_reg_513 <= brmerge_i_fu_427_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
cols_V_reg_470 <= img_cols_V_dout;
rows_V_reg_465 <= img_rows_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
exitcond_i_reg_504 <= exitcond_i_fu_413_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
i_V_reg_499 <= i_V_fu_407_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
tmp_data_V_reg_475 <= AXI_video_strm_V_data_V_0_data_out;
tmp_last_V_reg_483 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, AXI_video_strm_V_data_V_0_vld_out, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, exitcond4_i_fu_402_p2, ap_CS_fsm_state4, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0_subdone, ap_enable_reg_pp2_iter0, ap_block_pp2_stage0_subdone, tmp_user_V_fu_393_p1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((tmp_user_V_fu_393_p1 = ap_const_lv1_0) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state2;
elsif (((tmp_user_V_fu_393_p1 = ap_const_lv1_1) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
if (((exitcond4_i_fu_402_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_pp1_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
when ap_ST_fsm_pp2_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
AXI_video_strm_V_data_V_0_ack_in <= AXI_video_strm_V_data_V_0_state(1);
AXI_video_strm_V_data_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_348, ap_predicate_op71_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op71_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_data_V_0_data_out_assign_proc : process(AXI_video_strm_V_data_V_0_payload_A, AXI_video_strm_V_data_V_0_payload_B, AXI_video_strm_V_data_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_sel)) then
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_B;
else
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_data_V_0_load_A <= (not(AXI_video_strm_V_data_V_0_sel_wr) and AXI_video_strm_V_data_V_0_state_cmp_full);
AXI_video_strm_V_data_V_0_load_B <= (AXI_video_strm_V_data_V_0_state_cmp_full and AXI_video_strm_V_data_V_0_sel_wr);
AXI_video_strm_V_data_V_0_sel <= AXI_video_strm_V_data_V_0_sel_rd;
AXI_video_strm_V_data_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_data_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_data_V_0_vld_out <= AXI_video_strm_V_data_V_0_state(0);
AXI_video_strm_V_dest_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_348, ap_predicate_op71_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op71_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_dest_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_ack_in <= AXI_video_strm_V_last_V_0_state(1);
AXI_video_strm_V_last_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_348, ap_predicate_op71_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op71_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_last_V_0_data_out_assign_proc : process(AXI_video_strm_V_last_V_0_payload_A, AXI_video_strm_V_last_V_0_payload_B, AXI_video_strm_V_last_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_sel)) then
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_B;
else
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_last_V_0_load_A <= (not(AXI_video_strm_V_last_V_0_sel_wr) and AXI_video_strm_V_last_V_0_state_cmp_full);
AXI_video_strm_V_last_V_0_load_B <= (AXI_video_strm_V_last_V_0_state_cmp_full and AXI_video_strm_V_last_V_0_sel_wr);
AXI_video_strm_V_last_V_0_sel <= AXI_video_strm_V_last_V_0_sel_rd;
AXI_video_strm_V_last_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_last_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_vld_out <= AXI_video_strm_V_last_V_0_state(0);
AXI_video_strm_V_user_V_0_ack_in <= AXI_video_strm_V_user_V_0_state(1);
AXI_video_strm_V_user_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_348, ap_predicate_op71_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op71_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_user_V_0_data_out_assign_proc : process(AXI_video_strm_V_user_V_0_payload_A, AXI_video_strm_V_user_V_0_payload_B, AXI_video_strm_V_user_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_sel)) then
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_B;
else
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_user_V_0_load_A <= (not(AXI_video_strm_V_user_V_0_sel_wr) and AXI_video_strm_V_user_V_0_state_cmp_full);
AXI_video_strm_V_user_V_0_load_B <= (AXI_video_strm_V_user_V_0_state_cmp_full and AXI_video_strm_V_user_V_0_sel_wr);
AXI_video_strm_V_user_V_0_sel <= AXI_video_strm_V_user_V_0_sel_rd;
AXI_video_strm_V_user_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_user_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_user_V_0_vld_out <= AXI_video_strm_V_user_V_0_state(0);
ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(4);
ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(7);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state7 <= ap_CS_fsm(5);
ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_01001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_predicate_op71_read_state6)
begin
ap_block_pp1_stage0_01001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op71_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_predicate_op71_read_state6)
begin
ap_block_pp1_stage0_11001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op71_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_predicate_op71_read_state6)
begin
ap_block_pp1_stage0_subdone <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op71_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp2_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_348)
begin
ap_block_pp2_stage0_11001 <= ((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_pp2_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_348)
begin
ap_block_pp2_stage0_subdone <= ((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
ap_block_state1 <= ((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state5_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp1_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond_i_reg_504, ap_predicate_op71_read_state6)
begin
ap_block_state6_pp1_stage0_iter1 <= (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op71_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state8_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp2_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, eol_2_i_reg_348)
begin
ap_block_state9_pp2_stage0_iter1 <= ((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out));
end process;
ap_condition_515_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504)
begin
ap_condition_515 <= ((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0));
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond4_i_fu_402_p2, ap_CS_fsm_state4)
begin
if (((exitcond4_i_fu_402_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0)
begin
if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))) then
ap_idle_pp1 <= ap_const_logic_1;
else
ap_idle_pp1 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter0)
begin
if (((ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))) then
ap_idle_pp2 <= ap_const_logic_1;
else
ap_idle_pp2 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, brmerge_i_reg_513, eol_reg_301, ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323, ap_condition_515)
begin
if ((ap_const_boolean_1 = ap_condition_515)) then
if ((brmerge_i_reg_513 = ap_const_lv1_1)) then
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 <= eol_reg_301;
elsif ((brmerge_i_reg_513 = ap_const_lv1_0)) then
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323;
end if;
else
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323;
end if;
end process;
ap_phi_mux_eol_2_i_phi_fu_351_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_i_reg_348)
begin
if (((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_phi_mux_eol_2_i_phi_fu_351_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_eol_2_i_phi_fu_351_p4 <= eol_2_i_reg_348;
end if;
end process;
ap_phi_mux_eol_i_phi_fu_293_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504, eol_i_reg_289, ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4)
begin
if (((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_phi_mux_eol_i_phi_fu_293_p4 <= ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4;
else
ap_phi_mux_eol_i_phi_fu_293_p4 <= eol_i_reg_289;
end if;
end process;
ap_phi_mux_p_Val2_s_phi_fu_340_p4_assign_proc : process(AXI_video_strm_V_data_V_0_data_out, brmerge_i_reg_513, axi_data_V_1_i_reg_312, ap_phi_reg_pp1_iter1_p_Val2_s_reg_336, ap_condition_515)
begin
if ((ap_const_boolean_1 = ap_condition_515)) then
if ((brmerge_i_reg_513 = ap_const_lv1_1)) then
ap_phi_mux_p_Val2_s_phi_fu_340_p4 <= axi_data_V_1_i_reg_312;
elsif ((brmerge_i_reg_513 = ap_const_lv1_0)) then
ap_phi_mux_p_Val2_s_phi_fu_340_p4 <= AXI_video_strm_V_data_V_0_data_out;
else
ap_phi_mux_p_Val2_s_phi_fu_340_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_336;
end if;
else
ap_phi_mux_p_Val2_s_phi_fu_340_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_336;
end if;
end process;
ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323 <= "X";
ap_phi_reg_pp1_iter1_p_Val2_s_reg_336 <= "XXXXXXXXXXXXXXXXXXXXXXXX";
ap_predicate_op71_read_state6_assign_proc : process(exitcond_i_reg_504, brmerge_i_reg_513)
begin
ap_predicate_op71_read_state6 <= ((brmerge_i_reg_513 = ap_const_lv1_0) and (exitcond_i_reg_504 = ap_const_lv1_0));
end process;
ap_ready_assign_proc : process(exitcond4_i_fu_402_p2, ap_CS_fsm_state4)
begin
if (((exitcond4_i_fu_402_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
brmerge_i_fu_427_p2 <= (sof_1_i_fu_176 or ap_phi_mux_eol_i_phi_fu_293_p4);
exitcond4_i_fu_402_p2 <= "1" when (t_V_reg_267 = rows_V_reg_465) else "0";
exitcond_i_fu_413_p2 <= "1" when (t_V_2_reg_278 = cols_V_reg_470) else "0";
i_V_fu_407_p2 <= std_logic_vector(unsigned(t_V_reg_267) + unsigned(ap_const_lv32_1));
img_cols_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_blk_n <= img_cols_V_empty_n;
else
img_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_out_full_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_out_blk_n <= img_cols_V_out_full_n;
else
img_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_out_din <= img_cols_V_dout;
img_cols_V_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_out_write <= ap_const_logic_1;
else
img_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img_cols_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_read <= ap_const_logic_1;
else
img_cols_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_0_V_blk_n_assign_proc : process(img_data_stream_0_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504)
begin
if (((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_blk_n <= img_data_stream_0_V_full_n;
else
img_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_0_V_din <= ap_phi_mux_p_Val2_s_phi_fu_340_p4(8 - 1 downto 0);
img_data_stream_0_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_blk_n_assign_proc : process(img_data_stream_1_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504)
begin
if (((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_blk_n <= img_data_stream_1_V_full_n;
else
img_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_1_V_din <= ap_phi_mux_p_Val2_s_phi_fu_340_p4(15 downto 8);
img_data_stream_1_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_blk_n_assign_proc : process(img_data_stream_2_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504)
begin
if (((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_blk_n <= img_data_stream_2_V_full_n;
else
img_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_2_V_din <= ap_phi_mux_p_Val2_s_phi_fu_340_p4(23 downto 16);
img_data_stream_2_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
img_rows_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_blk_n <= img_rows_V_empty_n;
else
img_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_out_full_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_out_blk_n <= img_rows_V_out_full_n;
else
img_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_out_din <= img_rows_V_dout;
img_rows_V_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_out_write <= ap_const_logic_1;
else
img_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img_rows_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_read <= ap_const_logic_1;
else
img_rows_V_read <= ap_const_logic_0;
end if;
end process;
j_V_fu_418_p2 <= std_logic_vector(unsigned(t_V_2_reg_278) + unsigned(ap_const_lv32_1));
stream_in_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_0_state, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504, brmerge_i_reg_513, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_i_reg_348)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((brmerge_i_reg_513 = ap_const_lv1_0) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
stream_in_TDATA_blk_n <= AXI_video_strm_V_data_V_0_state(0);
else
stream_in_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
stream_in_TREADY <= AXI_video_strm_V_dest_V_0_state(1);
tmp_user_V_fu_393_p1 <= AXI_video_strm_V_user_V_0_data_out;
end behav;
|
mit
|
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/DPHY_LaneSCNN.vhd
|
1
|
9673
|
-------------------------------------------------------------------------------
--
-- File: DPHY_LaneSCNN.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements a MIPI D-PHY 1.0 CIL-SCNN lane: slave (receiver) clock.
-- It is architecture-independent by itself, but the instantiated HS-Clocking has
-- its own requirements. The D-PHY physical interface is assumed to be de-multiplexed
-- into low-power LP(1:0) and high-speed HS inputs by external circuitry (outside
-- the FPGA). On the logic side data is forwarded via the PPI interface as
-- described in the D-PHY spec Annex A.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
use work.DebugLib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DPHY_LaneSCNN is
Generic (
kGenerateMMCM : boolean := false;
kRefClkFreqHz : natural := 200_000_000;
kAddDelay_ps : integer := 0
);
Port (
aLP : in STD_LOGIC_VECTOR (1 downto 0);
aHS : in STD_LOGIC;
RefClk : in STD_LOGIC; --200MHz
RxDDRClkHS : out STD_LOGIC;
RxByteClkHS : out STD_LOGIC;
aRxClkActiveHS : out STD_LOGIC;
aForceRxmode : in STD_LOGIC;
aStopstate : out STD_LOGIC;
aEnable : in STD_LOGIC;
aRxUlpsClkNot : out std_logic; --Receive Ultra-Low Power State on Clock Lane.
aUlpsActiveNot : out std_logic; --ULP State (not) Active.
debug : out DebugSCNN_Type
);
end DPHY_LaneSCNN;
architecture Behavioral of DPHY_LaneSCNN is
function MAX(LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end;
type state_type is (stInit, stStop, stHS_Prpr, stHS_Term, stHS_Clk, stHS_End, stULPS, stULPS_Exit, stULPS_Rqst);
signal state, nstate : state_type := stInit;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one_hot";
signal cLP, cLPGlitch : std_logic_vector(1 downto 0);
signal cIntRst : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of cLP: signal is "TRUE";
alias CtlClk : std_logic is RefClk;
alias kCtlClkFreqHz : natural is kRefClkFreqHz;
constant kTInit : natural := natural(ceil(100.0 / 10.0**6 * real(kCtlClkFreqHz))); --100us
constant kTClkTermEn : natural := natural(ceil(38.0 / 10.0**9 * real(kCtlClkFreqHz))); --38ns
constant kTClkSettle : natural := natural(ceil(95.0 / 10.0**9 * real(kCtlClkFreqHz))); --95ns min
constant kTMinRx : natural := natural(ceil(20.0 / 10.0**9 * real(kCtlClkFreqHz))); --20ns
signal cClkSettleTout : std_logic;
signal cDelayCnt : natural range 0 to MAX(kTInit,MAX(kTClkTermEn, kTClkSettle)) := 0;
signal aClkLocked, cClkLocked, cHSRst, cDelayCntEn, aHSClkLocked, cHSClkLocked, cHSClkLocked_q, cHSClkLost : std_logic;
signal cEnable : std_logic;
begin
debug.cIntRst <= cIntRst;
debug.cLP <= cLP;
debug.cHSRst <= cHSRst;
debug.cHSClkLocked <= cHSClkLocked;
debug.state <= std_logic_vector(to_unsigned(state_type'pos(state), 4));
debug.cClkSettleTout <= cClkSettleTout;
SyncAsyncEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => aEnable,
OutClk => CtlClk,
oOut => cEnable);
cIntRst <= not cEnable;
aStopstate <= '1' when state = stStop else
'0';
aRxUlpsClkNot <= '0' when state = stULPS or state = stULPS_Exit else
'1';
aUlpsActiveNot <= '0' when state = stULPS else
'1';
aRxClkActiveHS <= aHSClkLocked;
-------------------------------------------------------------------------------
-- Synchronize LP signals into the CtlClk domain, then filter glitches
-------------------------------------------------------------------------------
GenSyncLP: for i in 0 to 1 generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => aLP(i),
OutClk => CtlClk,
oOut => cLPGlitch(i));
--TODO: LP 0 not in sync with LP 1; OK? because on HS-entry LPs don't change
-- simultaneously, only on HS-exit, where they both rise to 1 together.
-- On HS-exit only the "11" condition is used, so this skew at most delays exit.
GlitchFilterLP: entity work.GlitchFilter
generic map (
kNoOfPeriodsToFilter => kTMinRx)
port map (
SampleClk => CtlClk,
sIn => cLPGlitch(i),
sOut => cLP(i),
sRst => cIntRst);
end generate GenSyncLP;
DelayCounter: process(CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cDelayCntEn = '0') then
cDelayCnt <= 0;
elsif (cDelayCntEn = '1') then
cDelayCnt <= cDelayCnt + 1;
end if;
end if;
end process DelayCounter;
cClkSettleTout <= '1' when cDelayCnt = kTClkSettle-1
else '0';
--Outputs
cDelayCntEn <= '1' when state = stHS_Term else
'0';
ModeFSM_SyncProc: process (CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cIntRst = '1') then
state <= stInit;
else
state <= nstate;
end if;
end if;
end process;
cHSRst <= '0' when state = stHS_Clk and cIntRst = '0' else
'1';
ModeFSM_NextStateProc: process (state, cLP, cClkSettleTout, cClkLocked, cHSClkLost)
begin
nstate <= state;
case (state) is
when stInit =>
if cLP = "11" then
nstate <= stStop;
end if;
when stStop =>
if cLP = "01" then -- HS-Rqst
nstate <= stHS_Prpr;
elsif cLP = "10" then -- ULPS-Rqst
nstate <= stULPS_Rqst;
end if;
when stULPS_Rqst =>
if (cLP = "11" or cLP = "01") then
nstate <= stStop;
elsif (cLP = "00") then
nstate <= stULPS;
end if;
when stULPS =>
if (cLP = "10") then
nstate <= stULPS_Exit;
end if;
when stULPS_Exit =>
if (cLP = "11") then
nstate <= stStop;
end if;
when stHS_Prpr =>
if (cLP = "11") then
nstate <= stStop;
elsif cLP = "00" then -- Bridge
nstate <= stHS_Term;
end if;
when stHS_Term =>
if (cLP = "11") then
nstate <= stStop;
elsif (cLP = "00" and cClkSettleTout = '1') then -- Bridge
nstate <= stHS_Clk;
end if;
when stHS_Clk =>
if (cHSClkLost = '1') then --Clock lost
nstate <= stHS_End;
elsif (cLP = "11") then -- Stop, we might not have seen the loss of clock
nstate <= stStop;
end if;
when stHS_End =>
if (cLP = "11") then -- Stop
nstate <= stStop;
end if;
end case;
end process;
HSClockingX: entity work.HS_Clocking
Generic map (
kGenerateMMCM => kGenerateMMCM,
kCtlClkFreqHz => kCtlClkFreqHz,
kRefClkFreqHz => kRefClkFreqHz,
kAddDelay_ps => kAddDelay_ps
)
Port map (
HS_Clock => aHS,
HS_SerClk => RxDDRClkHS,
HS_Div4Clk => RxByteClkHS,
CtlClk => CtlClk,
cRst => cHSRst,
aLocked => aHSClkLocked,
dbg_cBUFR_Rst => debug.cBUFR_Rst,
dbg_cMMCM_Rst => debug.cMMCM_Rst,
dbg_cMMCM_RstTout => debug.cMMCM_RstTout,
dbg_cMMCM_Locked => debug.cMMCM_Locked
);
SyncAsyncLocked: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => cHSRst,
aIn => aHSClkLocked,
OutClk => CtlClk,
oOut => cHSClkLocked);
process(CtlClk)
begin
if Rising_Edge(CtlClk) then
cHSClkLocked_q <= cHSClkLocked;
end if;
end process;
cHSClkLost <= cHSClkLocked_q and not cHSClkLocked;
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/axi_i2s_adi_1.2/hdl/adi_common/pl330_dma_fifo.vhd
|
7
|
3411
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity pl330_dma_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32;
FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
-- PL330 DMA interface
dclk : in std_logic;
dresetn : in std_logic;
davalid : in std_logic;
daready : out std_logic;
datype : in std_logic_vector(1 downto 0);
drvalid : out std_logic;
drready : in std_logic;
drtype : out std_logic_vector(1 downto 0);
drlast : out std_logic;
DBG : out std_logic_vector(7 downto 0)
);
end;
architecture imp of pl330_dma_fifo is
signal request_data : Boolean;
type state_type is (IDLE, REQUEST, WAITING, FLUSH);
signal state : state_type;
signal i_in_ack : std_logic;
signal i_out_stb : std_logic;
begin
in_ack <= i_in_ack;
out_stb <= i_out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => i_in_ack,
in_data => in_data,
out_stb => i_out_stb,
out_ack => out_ack,
out_data => out_data
);
request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1';
drlast <= '0';
daready <= '1';
drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0';
drtype <= "00" when state = REQUEST else "10";
DBG(0) <= davalid;
DBG(2 downto 1) <= datype;
DBG(3) <= '1' when request_data else '0';
process (state)
begin
case state is
when IDLE => DBG(5 downto 4) <= "00";
when REQUEST => DBG(5 downto 4) <= "01";
when WAITING => DBG(5 downto 4) <= "10";
when FLUSH => DBG(5 downto 4) <= "11";
end case;
end process;
pl330_req_fsm: process (dclk) is
begin
if rising_edge(dclk) then
if dresetn = '0' then
state <= IDLE;
else
-- The controller may send a FLUSH request at any time and it won't
-- respond to any of our requests until we've ack the FLUSH request.
-- The FLUSH request is also supposed to reset our state machine, so
-- go back to idle after having acked the FLUSH.
if davalid = '1' and datype = "10" then
state <= FLUSH;
else
case state is
-- Nothing to do, wait for the fifo to run empty
when IDLE =>
if request_data and enable then
state <= REQUEST;
end if;
-- Send out a request to the PL330
when REQUEST =>
if drready = '1' then
state <= WAITING;
end if;
-- Wait for a ACK from the PL330 that it did transfer the data
when WAITING =>
if fifo_reset = '1' then
state <= IDLE;
elsif davalid = '1' then
if datype = "00" then
state <= IDLE;
end if;
end if;
-- Send out an ACK for the flush
when FLUSH =>
if drready = '1' then
state <= IDLE;
end if;
end case;
end if;
end if;
end if;
end process;
end;
|
mit
|
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/Block_Mat_exit1573_p.vhd
|
1
|
28144
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_Mat_exit1573_p is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
height : IN STD_LOGIC_VECTOR (15 downto 0);
width : IN STD_LOGIC_VECTOR (15 downto 0);
min : IN STD_LOGIC_VECTOR (7 downto 0);
max : IN STD_LOGIC_VECTOR (7 downto 0);
min_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
min_out_full_n : IN STD_LOGIC;
min_out_write : OUT STD_LOGIC;
img0_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_rows_V_out_full_n : IN STD_LOGIC;
img0_rows_V_out_write : OUT STD_LOGIC;
img0_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_cols_V_out_full_n : IN STD_LOGIC;
img0_cols_V_out_write : OUT STD_LOGIC;
img2_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_rows_V_out_full_n : IN STD_LOGIC;
img2_rows_V_out_write : OUT STD_LOGIC;
img2_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_cols_V_out_full_n : IN STD_LOGIC;
img2_cols_V_out_write : OUT STD_LOGIC;
img3_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_rows_V_out_full_n : IN STD_LOGIC;
img3_rows_V_out_write : OUT STD_LOGIC;
img3_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_cols_V_out_full_n : IN STD_LOGIC;
img3_cols_V_out_write : OUT STD_LOGIC;
p_cols_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_out_out_full_n : IN STD_LOGIC;
p_cols_assign_cast_out_out_write : OUT STD_LOGIC;
p_rows_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_out_out_full_n : IN STD_LOGIC;
p_rows_assign_cast_out_out_write : OUT STD_LOGIC;
tmp_3_cast_out_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
tmp_3_cast_out_out_full_n : IN STD_LOGIC;
tmp_3_cast_out_out_write : OUT STD_LOGIC;
max_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
max_out_full_n : IN STD_LOGIC;
max_out_write : OUT STD_LOGIC );
end;
architecture behav of Block_Mat_exit1573_p is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal min_out_blk_n : STD_LOGIC;
signal img0_rows_V_out_blk_n : STD_LOGIC;
signal img0_cols_V_out_blk_n : STD_LOGIC;
signal img2_rows_V_out_blk_n : STD_LOGIC;
signal img2_cols_V_out_blk_n : STD_LOGIC;
signal img3_rows_V_out_blk_n : STD_LOGIC;
signal img3_cols_V_out_blk_n : STD_LOGIC;
signal p_cols_assign_cast_out_out_blk_n : STD_LOGIC;
signal p_rows_assign_cast_out_out_blk_n : STD_LOGIC;
signal tmp_3_cast_out_out_blk_n : STD_LOGIC;
signal max_out_blk_n : STD_LOGIC;
signal ap_block_state1 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_block_state1_assign_proc : process(real_start, ap_done_reg, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
ap_block_state1 <= ((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
img0_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img0_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img0_cols_V_out_blk_n <= img0_cols_V_out_full_n;
else
img0_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img0_cols_V_out_din <= width;
img0_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img0_cols_V_out_write <= ap_const_logic_1;
else
img0_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img0_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img0_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img0_rows_V_out_blk_n <= img0_rows_V_out_full_n;
else
img0_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img0_rows_V_out_din <= height;
img0_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img0_rows_V_out_write <= ap_const_logic_1;
else
img0_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img2_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img2_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img2_cols_V_out_blk_n <= img2_cols_V_out_full_n;
else
img2_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img2_cols_V_out_din <= width;
img2_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img2_cols_V_out_write <= ap_const_logic_1;
else
img2_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img2_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img2_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img2_rows_V_out_blk_n <= img2_rows_V_out_full_n;
else
img2_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img2_rows_V_out_din <= height;
img2_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img2_rows_V_out_write <= ap_const_logic_1;
else
img2_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img3_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img3_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img3_cols_V_out_blk_n <= img3_cols_V_out_full_n;
else
img3_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img3_cols_V_out_din <= width;
img3_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img3_cols_V_out_write <= ap_const_logic_1;
else
img3_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img3_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img3_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img3_rows_V_out_blk_n <= img3_rows_V_out_full_n;
else
img3_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img3_rows_V_out_din <= height;
img3_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img3_rows_V_out_write <= ap_const_logic_1;
else
img3_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
internal_ap_ready_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
max_out_blk_n_assign_proc : process(ap_CS_fsm_state1, max_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
max_out_blk_n <= max_out_full_n;
else
max_out_blk_n <= ap_const_logic_1;
end if;
end process;
max_out_din <= max;
max_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
max_out_write <= ap_const_logic_1;
else
max_out_write <= ap_const_logic_0;
end if;
end process;
min_out_blk_n_assign_proc : process(ap_CS_fsm_state1, min_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
min_out_blk_n <= min_out_full_n;
else
min_out_blk_n <= ap_const_logic_1;
end if;
end process;
min_out_din <= min;
min_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
min_out_write <= ap_const_logic_1;
else
min_out_write <= ap_const_logic_0;
end if;
end process;
p_cols_assign_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, p_cols_assign_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
p_cols_assign_cast_out_out_blk_n <= p_cols_assign_cast_out_out_full_n;
else
p_cols_assign_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_out_out_din <= width(12 - 1 downto 0);
p_cols_assign_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_out_out_write <= ap_const_logic_1;
else
p_cols_assign_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, p_rows_assign_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
p_rows_assign_cast_out_out_blk_n <= p_rows_assign_cast_out_out_full_n;
else
p_rows_assign_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_out_out_din <= height(12 - 1 downto 0);
p_rows_assign_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_out_out_write <= ap_const_logic_1;
else
p_rows_assign_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
tmp_3_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, tmp_3_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
tmp_3_cast_out_out_blk_n <= tmp_3_cast_out_out_full_n;
else
tmp_3_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
tmp_3_cast_out_out_din <= min;
tmp_3_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_3_cast_out_out_write <= ap_const_logic_1;
else
tmp_3_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
serial_addition/inverter.vhd
|
1
|
472
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity inverter is
Port ( x : in std_logic;
y : out std_logic);
end inverter;
architecture Behavioral of inverter is
begin
y <= not x;
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/src/PkgZmodDAC.vhd
|
1
|
10207
|
-------------------------------------------------------------------------------
--
-- File: PkgZmodDAC.vhd
-- Author: Tudor Gherman
-- Original Project: Zmod DAC 1411 Low Level Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This package contains the constants and functions used for the
-- ZmodDAC1411_Controller IP
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PkgZmodDAC is
--Timing parameters
constant ktS : time := 2 ns; -- Setup time between CSB and SCLK
constant ktH : time := 2 ns; -- Hold time between CSB and SCLK
constant ktDS : time := 2 ns; -- Setup time between the data and the rising edge of SCLK
constant ktDH : time := 2 ns; -- Hold time between the data and the rising edge of SCLK
constant ktclk : time := 40 ns; -- minimum period of the SCLK
constant kSclkHigh : time := 10 ns; -- SCLK pulse width high (min)
constant kSclkLow : time := 10 ns; -- SCLK pulse width low (min)
--constant kSclkT_Max : time := 10 ns; -- SCLK pulse width low (min)
constant kSclkT_Min : time := 50 ns; -- SCLK pulse width low (min)
--constant kNoCommandBits : integer := 16; -- minimum period of the SCLK
constant kNoDataBits : integer := 8; -- minimum period of the SCLK
constant kTdcoMax : time := 4.4 ns;
constant kRelayConfigTime : time := 3ms; -- relay set and reset signals
--ADC Model Registers
constant aReg00_Mask : std_logic_vector(7 downto 0) := "01100110";
--Implementation constants
constant kCS_PulseWidthHigh : integer := 31; --CS pulse width high not specified for AD8717
constant kSPI_DataWidth : integer := 8; --ADI_SPI module data width
constant kSPI_CommandWidth : integer := 8; --ADI_SPI module command width
constant kSPI_AddrWidth : integer := kSPI_CommandWidth - 3; --ADI_SPI module command width
constant kSPI_SysClkDiv : integer := 4; --ADI_SPI module system clock divide constant
--No minimum SPI clock frequency specified by AD9717. The maximum frequency is 25MHz.
constant kCount20us : unsigned := to_unsigned (1999, 24); --Constant used to measure 20us with a clock frequency of 100MHz
constant kCount4ms : unsigned := to_unsigned (399999, 24); --Constant used to measure 4ms with a clock frequency of 100MHz
constant kCount150ms : unsigned := to_unsigned (14999999, 24); --Constant used to measure 150ms with a clock frequency of 100MHz
constant kCfgTimeout : unsigned := to_unsigned (14999999, 24); --Constant used to measure 150ms with a clock frequency of 100MHz
type FsmStatesSPI_t is (StIdle, StWrite, StRead1, StRead2, StRead3, StDone, StAssertCS);
type FsmStates_t is (StStart, StWriteConfigReg, StWaitDoneWriteReg, StReadControlReg,
StWaitDoneReadReg, StCheckCmdCnt, StInitDone, StIdle, StExtSPI_WrCmd,
StWaitDoneExtWrReg, StExtSPI_RdCmd, StWaitDoneExtRdReg, StRegExtRxData, StError);
type DAC_SPI_Commands_t is array (13 downto 0) of std_logic_vector(15 downto 0);
type DAC_SPI_Readback_t is array (13 downto 0) of std_logic_vector(7 downto 0);
-- List of commands sent to the AD9717 during the initialization process.
constant kDAC_SPI_Cmd : DAC_SPI_Commands_t := (
x"0E00", -- 13. Cal Control: Disable calibration clock.
x"1200", -- 12. Memory R/W: clear CALEN.
x"0FC0", -- 11. Cal Memory: Read CALSTAT. Read ONLY!
x"1210", -- 10. Memory R/W: CALEN - initialize self calibration.
x"0E3A", -- 9. Cal Control - step 3: Select Q DAC, I DAC self calibration.
x"0E0A", -- 8. Cal Control - step 2: Enable calibration clock.
x"0E02", -- 7. Cal Control - step 1: DIVSEL - calibration clock divide ratio from DAC clock rate set to 64.
x"1200", -- 6. Memory R/W: Self calibration step 1 (Write 0x00 to Register 0x12).
x"1400", -- 5. CLKMODE: Clear Reaquire bit in CLKMODE register.
x"1408", -- 4. CLKMODE: Toggle (step 2-set) Reaquire bit in CLKMODE register.
x"1400", -- 3. CLKMODE: Toggle (step 1-clear) Reaquire bit in CLKMODE register.
x"02B4", -- 2. Data Control: 2's Complement input data format, IDATA latched on DCLKIO rising edge,
-- I first of pair on data input pads, data clock input enable, data clock output disable.
x"0000", -- 1. SPI Control : Clear Reset.
x"0020" -- 0. SPI Control : Set Reset.
);
-- List of data expected to be read back fro the AD9717 at each step (after each register write) of the initialization process.
constant DAC_SPI_mask : DAC_SPI_Readback_t := (
x"00",
x"00",
x"3F",
x"EF",
x"00",
x"00",
x"00",
x"EF",
x"C3",
x"CB",
x"C3",
x"40",
x"80",
x"80"
);
constant kCmdTotal : integer := 13;
constant kCmdRdCalstatIndex : integer := 11; --Read ID command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
-- Constant used to measure 300 calibration clock cycles with a calibration clock divide ratio from DAC clock rate set to 64.
constant kCalTimeout : unsigned := to_unsigned (19200, 24);
-- Number of commands to load in the TX command FIFO for the CommandFIFO module
constant kCmdFIFO_NoWrCmds : integer := 4;
-- Command list loaded in the TX command FIFO of the CommandFIFO module
type CmdFIFO_WrCmdList_t is array (kCmdFIFO_NoWrCmds downto 0) of std_logic_vector(23 downto 0);
constant kCmdFIFO_WrList : CmdFIFO_WrCmdList_t := (
x"801F04", -- read Version register
x"0002B4", -- write Data Control register
x"8002B0", -- read Data Control register
x"0002B0", -- write Data Control register
x"000000" -- dummy
);
-- Number of commands expected to be returned and loaded in the RX command FIFO of
-- the SPI_IAP_AD9717_TestModule module in the tb_TestTop test bench.
-- It should be equal to the number of read commands in the kCmdFIFO_WrList.
constant kCmdFIFO_NoRdCmds : integer := 2;
-- Data expected in return after sending the kCmdFIFO_WrList commands by the CommandFIFO module
type CmdFIFO_RdCmdList_t is array (kCmdFIFO_NoRdCmds-1 downto 0) of std_logic_vector(7 downto 0);
constant kCmdFIFO_RdList : CmdFIFO_RdCmdList_t := (x"04",x"B0");
constant kCmdFIFO_RdListMask : CmdFIFO_RdCmdList_t := (x"00",x"40");
constant kCmdFIFO_Timeout : unsigned (23 downto 0) := x"000600";
end PkgZmodDAC;
|
mit
|
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
binary_multiplier_16/binary_multiplier_16.vhd
|
1
|
2367
|
-- Binary Multiplier with n = 4: VHDL Description
-- See Figures 8-6 and 8-7 for block diagram and ASM Chart
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity binary_multiplier is
port(CLK, RESET, G, LOADB, LOADQ: in std_logic;
MULT_IN: in std_logic_vector(15 downto 0);
MULT_OUT: out std_logic_vector(31 downto 0));
end binary_multiplier;
architecture behavior_16 of binary_multiplier is
type state_type is (IDLE, MUL0, MUL1);
signal state, next_state : state_type;
signal A, B, Q: std_logic_vector(15 downto 0);
signal P: std_logic_vector(3 downto 0);
signal C, Z: std_logic;
begin
Z <= not( P(3) OR P(2) OR P(1) OR P(0) );
MULT_OUT <= A & Q;
state_register: process (CLK, RESET)
begin
if (RESET = '1') then
state <= IDLE;
elsif (CLK'event and CLK = '1') then
state <= next_state;
end if;
end process;
next_state_func: process (G, Z, state)
begin
case state is
when IDLE =>
if G = '1' then
next_state <= MUL0;
else
next_state <= IDLE;
end if;
when MUL0 =>
next_state <= MUL1;
when MUL1 =>
if Z = '1' then
next_state <= IDLE;
else
next_state <= MUL0;
end if;
end case;
end process;
datapath_func: process (CLK)
variable CA: std_logic_vector(16 downto 0);
begin
if (CLK'event and CLK = '1') then
if LOADB = '1' then
B <= MULT_IN;
end if;
if LOADQ = '1' then
Q <= MULT_IN;
end if;
case state is
when IDLE =>
if G = '1' then
C <= '0';
A <= "0000000000000000";
P <= "1111";
end if;
when MUL0 =>
if Q(0) = '1' then
CA := ('0' & A) + ('0' & B);
else
CA := C & A;
end if;
C <= CA(16);
A <= CA(15 downto 0);
when MUL1 =>
C <= '0';
A <= C & A(15 downto 1);
Q <= A(0) & Q(15 downto 1);
P <= P - "0001";
end case;
end if;
end process;
end behavior_16;
|
mit
|
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/sub_abs_component.vhd
|
1
|
1597
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:12:05 07/08/05
-- Design Name:
-- Module Name: sub_abs_component - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sub_abs_component is
Port ( pixel_in1 : in std_logic_vector(8 downto 0);
pixel_in2 : in std_logic_vector(8 downto 0);
sub_abs_out : out std_logic_vector(8 downto 0));
end sub_abs_component;
architecture Behavioral of sub_abs_component is
component prj_sub
port(
Pixel_in1 : in std_logic_vector(8 downto 0);
Pixel_in2 : in std_logic_vector(8 downto 0);
sub_out : out std_logic_vector(8 downto 0)
);
end component;
component absolute
port(
x : in std_logic_vector(8 downto 0);
y : out std_logic_vector(8 downto 0)
);
end component;
signal F : std_logic_vector(8 downto 0);
begin
element1: prj_sub port map(
Pixel_in1,
Pixel_in2,
F);
element2: absolute port map(
F ,
sub_abs_out);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enqcK.vhd
|
1
|
1608
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_saturation_enqcK is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din0_WIDTH :integer := 32;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din0 :in std_logic_vector(27 downto 0);
din1 :in std_logic_vector(27 downto 0);
din2 :in std_logic_vector(27 downto 0);
din3 :in std_logic_vector(27 downto 0);
din4 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(27 downto 0));
end entity;
architecture rtl of hls_saturation_enqcK is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(27 downto 0);
signal mux_1_1 : std_logic_vector(27 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(27 downto 0);
begin
sel <= din4;
-- Generate level 1 logic
mux_1_0 <= din0 when sel(0) = '0' else din1;
mux_1_1 <= din2 when sel(0) = '0' else din3;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
mit
|
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/tb_TestDataPath_all.vhd
|
2
|
6005
|
-------------------------------------------------------------------------------
--
-- File: tb_TestDataPath_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to test the DataPath & ADC_Calibration modules
-- with static/dynamic calibration and in normal operation/test mode
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestDataPath_all is
-- Port ( );
end tb_TestDataPath_all;
architecture Behavioral of tb_TestDataPath_all is
constant kADC_Width : integer range 10 to 16 := 14;
constant kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
constant kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
constant kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010100010";
constant kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111000101";
constant kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010010010";
constant kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101101010101";
constant kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101000110010";
constant kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010001";
begin
-- Test the DataPath & ADC_Calibration modules with static calibration and in normal operation.
InstDataPathStaticCalib: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => false,
kSimTestMode => '0',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with dynamic calibration and in normal operation.
InstDataPathExtCalib: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => true,
kSimTestMode => '0',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with static calibration and in test mode.
InstDataPathStaticCalibTestMode: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => false,
kSimTestMode => '1',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
-- Test the DataPath & ADC_Calibration modules with dynamic calibration and in test mode.
InstDataPathExtCalibTestMode: entity work.tb_TestDataPathCalib
Generic Map(
kADC_Width => kADC_Width,
kExtCalibEn => true,
kSimTestMode => '1',
kCh1LgMultCoefStatic => kCh1LgMultCoefStatic,
kCh1LgAddCoefStatic => kCh1LgAddCoefStatic,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2LgMultCoefStatic => kCh2LgMultCoefStatic,
kCh2LgAddCoefStatic => kCh2LgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic
);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/tb/tb_ECC.vhd
|
1
|
4540
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/27/2017 03:44:54 PM
-- Design Name:
-- Module Name: tb_ECC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use STD.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ECC is
-- Port ( );
end tb_ECC;
architecture Behavioral of tb_ECC is
component ECC is
Port (
StreamClk : in std_logic;
sHeaderIn : in std_logic_vector(31 downto 0);
sCE : in std_logic;
sReady : out std_logic;
sHeaderOut : out std_logic_vector(31 downto 0);
sValid: out std_logic; --asserted for one cycle when ECC processing is done and correct data is present on sHeaderOut
sError: out std_logic; --asserted for one cycle when ECC processing detected an error
sRst : in std_logic
);
end component;
constant kClkPeriod : time := 10ns;
type stimulus_t is array (natural range <>) of std_logic_vector(31 downto 0);
constant kStimulus : stimulus_t := (x"3F01F037", x"3F01F037");
signal StreamClk, sRst, sCE, sReady, sValid, sError : std_logic := '0';
signal sHeaderIn, sHeaderOut : std_logic_vector(31 downto 0);
begin
StreamClk <= not StreamClk after kClkPeriod / 2;
process
variable temp : std_logic_vector(31 downto 0);
begin
sRst <= '1';
wait for 5*kClkPeriod;
sCE <= '0';
sRst <= '0';
wait until Rising_Edge(StreamClk);
for i in kStimulus'range loop
wait until Rising_Edge(StreamClk);
-- unmodified stimulus
assert (sReady = '1') report "DUT ECC is not ready when it should be" severity failure;
sCE <= '1';
sHeaderIn <= kStimulus(i);
wait until Rising_Edge(StreamClk);
sCE <= '0';
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
assert (sValid = '1' and sError = '0' and sHeaderOut = sHeaderIn) report "ECC error where there should not be one" severity failure;
for iBit in 29 downto 0 loop -- Bits 31 and 30 (7 and 6 of ECC) are always 0
wait until Rising_Edge(StreamClk);
-- modified stimulus (one bit flipped)
assert (sReady = '1') report "DUT ECC is not ready when it should be" severity failure;
sCE <= '1';
temp := kStimulus(i);
temp(iBit) := not temp(iBit);
sHeaderIn <= temp;
wait until Rising_Edge(StreamClk);
sCE <= '0';
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
assert (sValid = '1' and sError = '1' and sHeaderOut = kStimulus(i)) report "ECC one-bit error was not fixed" severity failure;
end loop;
for iBit in 29 downto 0 loop
for iBit2 in 29 downto 0 loop
if (iBit /= iBit2) then
wait until Rising_Edge(StreamClk);
-- modified stimulus (one bit flipped)
assert (sReady = '1') report "DUT ECC is not ready when it should be" severity failure;
sCE <= '1';
temp := kStimulus(i);
temp(iBit) := not temp(iBit);
temp(iBit2) := not temp(iBit2);
sHeaderIn <= temp;
wait until Rising_Edge(StreamClk);
sCE <= '0';
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
assert (sValid = '0' and sError = '1') report "ECC two-bit error was not detected" severity failure;
end if;
end loop;
end loop;
end loop;
wait;
end process;
DUT: ECC
Port map (
StreamClk => StreamClk,
sHeaderIn => sHeaderIn,
sCE => sCE,
sReady => sReady,
sHeaderOut => sHeaderOut,
sValid => sValid,
sError => sError,
sRst => sRst
);
end Behavioral;
|
mit
|
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_my_part/full_adder.vhd
|
2
|
805
|
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
port
(
in1 : in std_logic;
in2 : in std_logic;
c_in : in std_logic;
sum : out std_logic;
c_out : out std_logic
);
end full_adder;
architecture Behavioral of full_adder is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
begin
s1 <= (in1 xor in2);
s2 <= (c_in and s1);
s3 <= (in1 and in2);
sum <= (s1 xor c_in);
c_out <= (s2 or s3);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/usb2device_v1_0/src/DMA_Operations.vhd
|
2
|
18504
|
-------------------------------------------------------------------------------
--
-- File: DMA_Operations.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is responsible with implementing the S2MM and MM2S frameworks for the DMA engine
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DMA_Operations is
generic (
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := "0100000000";
C_M_AXI_ADDR_WIDTH : integer := 10;
C_M_AXI_DATA_WIDTH : integer := 32;
C_M_TRANSACTIONS_NUM : integer := 4
);
Port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
dma_transfer_complete : out std_logic;
start_dma_s2mm : in STD_LOGIC;
start_dma_mm2s : in STD_LOGIC;
dma_source_dest_address : in STD_LOGIC_VECTOR(31 downto 0);
dma_transfer_length : in STD_LOGIC_VECTOR(31 downto 0)
);
end DMA_Operations;
architecture Behavioral of DMA_Operations is
COMPONENT axi_master
PORT(
M_AXI_ACLK : IN std_logic;
M_AXI_ARESETN : IN std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BRESP : IN std_logic_vector(1 downto 0);
M_AXI_BVALID : IN std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RDATA : IN std_logic_vector(31 downto 0);
M_AXI_RRESP : IN std_logic_vector(1 downto 0);
M_AXI_RVALID : IN std_logic;
INIT_WRITE : IN std_logic;
INIT_READ : IN std_logic;
WRITE_DATA : IN std_logic_vector(31 downto 0);
WRITE_ADDRESS : IN std_logic_vector(9 downto 0);
READ_ADDRESS : IN std_logic_vector(9 downto 0);
M_AXI_AWADDR : OUT std_logic_vector(9 downto 0);
M_AXI_AWPROT : OUT std_logic_vector(2 downto 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_WDATA : OUT std_logic_vector(31 downto 0);
M_AXI_WSTRB : OUT std_logic_vector(3 downto 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_BREADY : OUT std_logic;
M_AXI_ARADDR : OUT std_logic_vector(9 downto 0);
M_AXI_ARPROT : OUT std_logic_vector(2 downto 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_RREADY : OUT std_logic;
WRITE_COMPLETE : OUT std_logic;
READ_COMPLETE : OUT std_logic;
READ_DATA : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
type state_type is (IDLE, S2MM_WRITE_DMASR, MM2S_WRITE_DMASR, S2MM_READ_STATUS1, S2MM_READ_STATUS2, WRITE_S2MM_DMACR, WRITE_S2MM_SA, INIT_S2MM_WRITE_LENGTH, MM2S_READ_STATUS1, MM2S_READ_STATUS2, WRITE_MM2S_DMACR, WRITE_MM2S_SA, INIT_MM2S_WRITE_LENGTH);
signal state, next_state : state_type;
-- signal state_ind_dma : STD_LOGIC_VECTOR(4 downto 0);
signal init_write_dma : STD_LOGIC;
signal init_read_dma : STD_LOGIC;
signal init_write_dma_reg : STD_LOGIC;
signal init_read_dma_reg : STD_LOGIC;
signal dma_reg_write_address : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal dma_reg_read_address : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal dma_reg_write_data : STD_LOGIC_VECTOR(31 downto 0);
signal dma_reg_read_data : STD_LOGIC_VECTOR(31 downto 0);
signal dma_reg_write_complete : STD_LOGIC;
signal dma_reg_read_complete : STD_LOGIC;
signal clear_first_transfer_s2mm : STD_LOGIC;
signal is_first_transfer_s2mm : STD_LOGIC;
signal clear_first_transfer_mm2s : STD_LOGIC;
signal is_first_transfer_mm2s : STD_LOGIC;
signal dma_transfer_complete_fsm : STD_LOGIC;
signal start_dma_mm2s_r : STD_LOGIC;
signal start_dma_s2mm_r : STD_LOGIC;
signal start_dma_mm2s_pulse : STD_LOGIC;
signal start_dma_s2mm_pulse : STD_LOGIC;
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of state_ind_dma : signal is "true";
-- attribute keep of state_ind_dma : signal is "true";
-- attribute mark_debug of dma_reg_read_complete : signal is "true";
-- attribute keep of dma_reg_read_complete : signal is "true";
-- attribute mark_debug of is_first_transfer_s2mm : signal is "true";
-- attribute keep of is_first_transfer_s2mm : signal is "true";
begin
DEBUG_REG_DATA <= dma_reg_read_data;
dma_transfer_complete <= dma_transfer_complete_fsm;
Inst_axi_master: axi_master PORT MAP(
M_AXI_ACLK => CLK,
M_AXI_ARESETN => RESETN,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY,
INIT_WRITE => init_write_dma_reg,
INIT_READ => init_read_dma_reg,
WRITE_COMPLETE => dma_reg_write_complete,
READ_COMPLETE => dma_reg_read_complete,
WRITE_DATA => dma_reg_write_data,
WRITE_ADDRESS => dma_reg_write_address,
READ_DATA => dma_reg_read_data,
READ_ADDRESS => dma_reg_read_address
);
MM2S_PULSE_PROC: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
start_dma_mm2s_r <= '0';
start_dma_mm2s_pulse <= '0';
else
start_dma_mm2s_r <= start_dma_mm2s;
start_dma_mm2s_pulse <= start_dma_mm2s and (not start_dma_mm2s_r);
end if;
end if;
end process;
S2MM_PULSE_PROC: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
start_dma_s2mm_r <= '0';
start_dma_s2mm_pulse <= '0';
else
start_dma_s2mm_r <= start_dma_s2mm;
start_dma_s2mm_pulse <= start_dma_s2mm and (not start_dma_s2mm_r);
end if;
end if;
end process;
FIRST_DMA_TRANSFER_S2MM: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
is_first_transfer_s2mm <= '1';
elsif (clear_first_transfer_s2mm = '1') then
is_first_transfer_s2mm <= '0';
end if;
end if;
end process;
FIRST_DMA_TRANSFER_MM2S: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
is_first_transfer_mm2s <= '1';
elsif (clear_first_transfer_mm2s = '1') then
is_first_transfer_mm2s <= '0';
end if;
end if;
end process;
SYNC_PROC: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
state <= IDLE;
init_write_dma_reg <= '0';
init_read_dma_reg <= '0';
else
state <= next_state;
init_write_dma_reg <= init_write_dma;
init_read_dma_reg <= init_read_dma;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (state, dma_reg_write_complete, dma_reg_read_complete, dma_transfer_length, is_first_transfer_mm2s, is_first_transfer_s2mm, start_dma_s2mm_pulse, dma_reg_read_data, start_dma_mm2s_pulse, dma_source_dest_address)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
state_ind_dma <= "00000";
dma_transfer_complete_fsm <= '0';
init_write_dma <= '0';
init_read_dma <= '0';
dma_reg_write_address <= (others=>'0');
dma_reg_read_address <= (others=>'0');
dma_reg_write_data <= (others=>'0');
clear_first_transfer_s2mm <= '0';
clear_first_transfer_mm2s <= '0';
--insert statements to decode next_state
--below is a simple example
case state is
when IDLE =>
state_ind_dma <= "00000";
--init_write_dma <= '1';
if (start_dma_s2mm_pulse = '1') then
init_read_dma <= '1'; -- initiate axi_master read
next_state <= S2MM_READ_STATUS1;
elsif (start_dma_mm2s_pulse = '1') then
init_read_dma <= '1'; -- initiate axi_master read
next_state <= MM2S_READ_STATUS1;
end if;
when S2MM_READ_STATUS1 =>
state_ind_dma <= "00001";
init_write_dma <= '0';
dma_reg_read_address <= "0000110100";
--dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_read_complete = '1') then
if (dma_reg_read_data(1) = '1' or (dma_reg_read_data(1) = '0' and is_first_transfer_s2mm = '1')) then --DMA controller idle
init_write_dma <= '1'; -- initiate axi_master write
next_state <= WRITE_S2MM_DMACR;
else
init_read_dma <= '1';
next_state <= S2MM_READ_STATUS1;
end if;
end if;
when WRITE_S2MM_DMACR =>
state_ind_dma <= "00010";
init_write_dma <= '0';
dma_reg_write_address <= "0000110000";
dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_write_complete = '1') then
init_write_dma <= '1';
next_state <= WRITE_S2MM_SA;
else
next_state <= WRITE_S2MM_DMACR;
end if;
when WRITE_S2MM_SA =>
state_ind_dma <= "00011";
init_write_dma <= '0';
dma_reg_write_address <= "0001001000";
dma_reg_write_data <= dma_source_dest_address;
if (dma_reg_write_complete = '1') then
init_write_dma <= '1';
next_state <= INIT_S2MM_WRITE_LENGTH;
end if;
when INIT_S2MM_WRITE_LENGTH =>
state_ind_dma <= "00100";
clear_first_transfer_s2mm <= '1';
dma_reg_write_address <= "0001011000";
dma_reg_write_data <= dma_transfer_length;
if (dma_reg_write_complete = '1') then
init_read_dma <= '1';
next_state <= S2MM_READ_STATUS2;
end if;
when S2MM_READ_STATUS2 =>
state_ind_dma <= "00101";
dma_reg_read_address <= "0000110100";
---dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_read_complete = '1') then
if (dma_reg_read_data(12) = '1' and dma_reg_read_data(1) = '1') then --IOC detected
--dma_transfer_complete_fsm <= '1';
init_write_dma <= '1';
next_state <= S2MM_WRITE_DMASR;
else
init_read_dma <= '1';
next_state <= S2MM_READ_STATUS2;
end if;
end if;
when S2MM_WRITE_DMASR =>
state_ind_dma <= "00110";
dma_reg_write_address <= "0000110100";
dma_reg_write_data <= "00000000000000000001000000000000";
if (dma_reg_write_complete = '1') then
dma_transfer_complete_fsm <= '1';
next_state <= IDLE;
end if;
when MM2S_READ_STATUS1 =>
state_ind_dma <= "00111";
init_write_dma <= '0';
dma_reg_read_address <= "0000000100";
--dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_read_complete = '1') then
if (dma_reg_read_data(1) = '1' or (dma_reg_read_data(1) = '0' and is_first_transfer_mm2s = '1')) then
init_write_dma <= '1'; -- initiate axi_master write
next_state <= WRITE_MM2S_DMACR;
else
init_read_dma <= '1';
next_state <= MM2S_READ_STATUS1;
end if;
end if;
when WRITE_MM2S_DMACR =>
state_ind_dma <= "01000";
init_write_dma <= '0';
dma_reg_write_address <= "0000000000";
dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_write_complete = '1') then
init_write_dma <= '1';
next_state <= WRITE_MM2S_SA;
else
next_state <= WRITE_MM2S_DMACR;
end if;
when WRITE_MM2S_SA =>
state_ind_dma <= "01001";
init_write_dma <= '0';
dma_reg_write_address <= "0000011000";
dma_reg_write_data <= dma_source_dest_address;
if (dma_reg_write_complete = '1') then
init_write_dma <= '1';
next_state <= INIT_MM2S_WRITE_LENGTH;
end if;
when INIT_MM2S_WRITE_LENGTH =>
state_ind_dma <= "01010";
clear_first_transfer_mm2s <= '1';
dma_reg_write_address <= "0000101000";
dma_reg_write_data <= dma_transfer_length;
if (dma_reg_write_complete = '1') then
init_read_dma <= '1';
next_state <= MM2S_READ_STATUS2;
end if;
when MM2S_READ_STATUS2 =>
state_ind_dma <= "01011";
dma_reg_read_address <= "0000000100";
--dma_reg_write_data <= "00000000000000000000000000000001";
if (dma_reg_read_complete = '1') then
if (dma_reg_read_data(12) = '1' and dma_reg_read_data(1) = '1') then --IOC detected
--dma_transfer_complete_fsm <= '1';
init_write_dma <= '1';
next_state <= MM2S_WRITE_DMASR;
else
init_read_dma <= '1';
next_state <= MM2S_READ_STATUS2;
end if;
end if;
when MM2S_WRITE_DMASR =>
state_ind_dma <= "01100";
dma_reg_write_address <= "0000000100";
dma_reg_write_data <= "00000000000000000001000000000000";
if (dma_reg_write_complete = '1') then
dma_transfer_complete_fsm <= '1';
next_state <= IDLE;
end if;
when others =>
next_state <= IDLE;
end case;
end process;
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/rgb2dpvid_v1_0/src/rgb2dpvid.vhd
|
2
|
4161
|
-------------------------------------------------------------------------------
--
-- File: rgb2dpvid.vhd
-- Author: Mihaita Nagy
-- Original Project: RGB to Displayport Video
-- Date: 12 November 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- Converts a kDataWidth-bit RGB interface (VGA compatible) given as input to a
-- Displayport Video interface
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rgb2dpvid is
generic(
-- Width of the input data bus
kDataWidth : integer := 24
);
port(
-- RGB interface
PixelClk : in std_logic;
pData : in std_logic_vector((kDataWidth-1) downto 0);
pHSync : in std_logic;
pVSync : in std_logic;
pVde : in std_logic;
-- Displayport Video interface
pVidClk : out std_logic;
pVidPixel0 : out std_logic_vector(47 downto 0);
pVidHSync : out std_logic;
pVidVSync : out std_logic;
pVidOddEven : out std_logic;
pVidRst : out std_logic;
pVidEnable : out std_logic
);
end rgb2dpvid;
architecture rtl of rgb2dpvid is
begin
-- Video clock the same as the pixel clock
pVidClk <= PixelClk;
-- Odd/Even qualifier not used
pVidOddEven <= '0';
-- Also reset is not used
pVidRst <= '0';
-- Synchronous process to distribute the video data
SyncIns: process(PixelClk)
begin
if rising_edge(PixelClk) then
pVidHSync <= pHSync;
pVidVSync <= pVSync;
pVidEnable <= pVde;
-- Red component
pVidPixel0(47 downto 47-((kDataWidth/3)-1)) <= pData((kDataWidth-1) downto (kDataWidth-kDataWidth/3));
pVidPixel0(39 downto 32) <= (others => '0');
-- Green component
pVidPixel0(31 downto 31-((kDataWidth/3)-1)) <= pData(((kDataWidth-2*kDataWidth/3)-1) downto 0);
pVidPixel0(23 downto 16) <= (others => '0');
-- Blue component
pVidPixel0(15 downto 15-((kDataWidth/3)-1)) <= pData(((kDataWidth-kDataWidth/3)-1) downto (kDataWidth-2*kDataWidth/3));
pVidPixel0(7 downto 0) <= (others => '0');
end if;
end process SyncIns;
end rtl;
|
mit
|
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_strebkb.vhd
|
1
|
1686
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_strebkb_DSP48_0 is
port (
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(22 - 1 downto 0);
p: out std_logic_vector(29 - 1 downto 0));
end entity;
architecture behav of hls_contrast_strebkb_DSP48_0 is
signal a_cvt: unsigned(8 - 1 downto 0);
signal b_cvt: unsigned(22 - 1 downto 0);
signal p_cvt: unsigned(29 - 1 downto 0);
attribute keep : string;
attribute keep of a_cvt : signal is "true";
attribute keep of b_cvt : signal is "true";
attribute keep of p_cvt : signal is "true";
begin
a_cvt <= unsigned(a);
b_cvt <= unsigned(b);
p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 29));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_strebkb is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_strebkb is
component hls_contrast_strebkb_DSP48_0 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_strebkb_DSP48_0_U : component hls_contrast_strebkb_DSP48_0
port map (
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
hangmann/fpga-heater
|
simple_timebase_v1_00_a/hdl/vhdl/simple_timebase.vhd
|
1
|
11626
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library simple_timebase_v1_00_a;
use simple_timebase_v1_00_a.user_logic;
entity simple_timebase is
generic
(
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
);
port
(
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity simple_timebase;
architecture IMP of simple_timebase is
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR,
ZERO_ADDR_PAD & USER_SLV_HIGHADDR
);
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG)
);
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
USER_LOGIC_I : entity simple_timebase_v1_00_a.user_logic
generic map
(
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
mit
|
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/fifo_w16_d4_A.vhd
|
2
|
4437
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d4_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d4_A_shiftReg;
architecture rtl of fifo_w16_d4_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d4_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d4_A is
component fifo_w16_d4_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d4_A_shiftReg : fifo_w16_d4_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
Digilent/vivado-library
|
ip/axi_ps2_1.0/src/SyncAsync.vhd
|
34
|
3727
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/dvi2rgb/src/SyncAsync.vhd
|
34
|
3727
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
mit
|
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
serial_addition/full_adder.vhd
|
1
|
947
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
Port (
a : in std_logic;
b : in std_logic;
c_in : in std_logic;
sum : out std_logic;
c_out : out std_logic;
for_augend : out std_logic;
for_addend : out std_logic;
for_c_in : out std_logic;
for_c_out : out std_logic;
for_sum : out std_logic
);
end full_adder;
architecture Behavioral of full_adder is
signal s1, s2 ,s3: std_logic;
begin
s1 <= a xor b;
s2 <= c_in and s1;
s3 <= a and b;
sum <= s1 xor c_in;
c_out <= s2 or s3;
for_augend <= a;
for_addend <= b;
for_c_in <= c_in;
for_c_out <= s2 or s3;
for_sum <= s1 xor c_in;
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/GainOffsetCalib.vhd
|
1
|
12019
|
-------------------------------------------------------------------------------
--
-- File: GainOffsetCalib.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module applies the gain and offset calibration to the raw data samples
-- received from the DataPath module.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity GainOffsetCalib is
Generic (
-- ADC/DAC number of bits
kWidth : integer range 10 to 16 := 14;
-- ADC/DAC dynamic/static calibration
kExtCalibEn : boolean := true;
-- When asserted, kInvert determines the sign inversion of the data samples
-- received. Used to compensate the physical inversion of some of the
-- channels on the PCB at the ADC/DAC input/output on the Zmod.
kInvert : boolean := false;
-- Low gain multiplicative (gain) compensation coefficient parameter
kLgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Low gain additive (offset) compensation coefficient parameter
kLgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- High gain multiplicative (gain) compensation coefficient parameter
kHgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- High gain additive (offset) compensation coefficient parameter
kHgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000"
);
Port (
-- Sampling clock
SamplingClk : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in the SamplingClk domain)
acRst_n : in STD_LOGIC;
-- cTestMode is used to bypass the calibration block. When this signal
-- is asserted, raw samples are provided on the data interface
cTestMode : in STD_LOGIC;
-- If at the start of the acquisition, this module puts on cCalibDataOut output signal the first acquired and calibrated samples,
-- together with cDataCalibValid = '1', but doDataAxisTready is not asserted, in the next clock cycle the value on cCalibDataOut will change,
-- since it will take the values of the next calibrated samples. This violates the AXI Stream interface specification.
-- This signal was added to prevent that. In a top level this signal should be connected to an AXI Stream Slave TREADY signal.
cDataAcceptanceReady : in STD_LOGIC;
-- Low gain gain compensation coefficient external port
cExtLgMultCoef : in std_logic_vector (17 downto 0);
-- Low gain offset compensation coefficient external port
cExtLgAddCoef : in std_logic_vector (17 downto 0);
-- High gain gain compensation coefficient external port
cExtHgMultCoef : in std_logic_vector (17 downto 0);
-- High gain offset compensation coefficient external port
cExtHgAddCoef : in std_logic_vector (17 downto 0);
-- Gain Relay State (1 -> High Gain; 0 -> Low Gain)
cGainState : in std_logic;
-- Raw data input
cDataRaw : in STD_LOGIC_VECTOR (kWidth-1 downto 0);
-- Raw data valid signal
cDataInValid : in STD_LOGIC;
-- Calibrated output data
cCalibDataOut : out STD_LOGIC_VECTOR (15 downto 0);
-- Output data valid signal
cDataCalibValid : out STD_LOGIC
);
end GainOffsetCalib;
architecture Behavioral of GainOffsetCalib is
signal cDataRaw18bSigned : signed(17 downto 0);
signal cDataRaw18b : std_logic_vector(17 downto 0);
signal cCalibMult : signed(35 downto 0);
signal cCalibAdd : signed(35 downto 0);
signal cCoefAdd : std_logic_vector(35 downto 0);
signal cCoefAddSigned : signed(35 downto 0);
signal cCoefMult : std_logic_vector(17 downto 0);
signal cCoefMultSigned : signed(17 downto 0);
signal cCoefMultLg, cCoefMultHg : std_logic_vector (17 downto 0);
signal cCoefAddLg, cCoefAddHg : std_logic_vector (17 downto 0);
signal cDataInValidR : STD_LOGIC;
signal cDataCalibValidLoc : std_logic;
signal cCalibDataOutLoc : std_logic_vector(15 downto 0);
signal cFirstWordAccepted : std_logic;
constant kDummy : std_logic_vector (17-kWidth downto 0) := (others => '0');
begin
--Channel1 low gain gain compensation coefficient (output port or IP parameter).
cCoefMultLg <= cExtLgMultCoef when kExtCalibEn = true else kLgMultCoefStatic;
--Channel1 high gain gain compensation coefficient (output port or IP parameter).
cCoefMultHg <= cExtHgMultCoef when kExtCalibEn = true else kHgMultCoefStatic;
--Channel1 low gain offset compensation coefficient (output port or IP parameter).
cCoefAddLg <= cExtLgAddCoef when kExtCalibEn = true else kLgAddCoefStatic;
--Channel1 high gain offset compensation coefficient (output port or IP parameter).
cCoefAddHg <= cExtHgAddCoef when kExtCalibEn = true else kHgAddCoefStatic;
-- Numerical representation of the calibration module's signals:
-- The first operation of the calibration block is represented by the multiplication
-- of the raw data input by the multiplicative coefficient. The multiplier's
-- operands are represented as follows:
-- 1. The input raw data is considered to be a fractional number < 1, consisting
-- of a sign bit and 17 fractional bits.
-- 2. The multiplicative coefficient, which can be slightly higher or slightly
-- lower than 1, is also represented on 18 bits, i.e. 1 sign bit, 1 integer bit,
-- and 16 fractional bis.
-- The result of the multiplication is a 36 bit number, consisting of a sign bit,
-- 2 integer bits and 33 fractional bits. Thus, to apply the additive coefficient,
-- (which is interpreted by the module as a 18 bit fractional number - 1 sign bit
-- + 17 fractional bits)the additive coefficient is also converted to this format
-- (sign extended by 2 bits and padded with 16 fractional bits).
-- Determine the additive coefficient based on the channel's gain relay state
-- and convert it to a 36 bit representation (as explained above).
ProcAddCoef : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCoefAdd <= (others => '0');
elsif (rising_edge(SamplingClk)) then
if (cGainState = '0') then --Low Gain
cCoefAdd <= cCoefAddLg(17) & cCoefAddLg(17) & cCoefAddLg & x"0000";
else --High Gain
cCoefAdd <= cCoefAddHg(17) & cCoefAddHg(17) & cCoefAddHg & x"0000";
end if;
end if;
end process;
-- Determine the multiplicative coefficient based on the channel's gain relay state.
ProcMultCoef : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCoefMult <= "010000000000000000";
elsif (rising_edge(SamplingClk)) then
if (cGainState = '0') then
cCoefMult <= cCoefMultLg;
else
cCoefMult <= cCoefMultHg;
end if;
end if;
end process;
cDataRaw18b <= cDataRaw & kDummy;
-- Invert raw data input if the analog channel is inverted at the
-- ADC/DAC input/output. Inversion of the minimum negative value (-2^kWidth)
-- needs to be done explicitly.
ProcInvert : process (cDataRaw18b)
begin
if (kInvert = false) then
if (cDataRaw18b = "100000000000000000") then
-- For the inverted channel, because the inversion is done at the FPGA
-- level, the minimum negative value is -2^kWidth+1. For symmetry
-- reasons the non inverted channel also limits the minimum negative value
-- at -2^kWidth+1.
cDataRaw18bSigned <= "100000000000000001";
else
cDataRaw18bSigned <= signed(cDataRaw18b);
end if;
else
if (cDataRaw18b = "100000000000000000") then
cDataRaw18bSigned <= "011111111111111111";
else
cDataRaw18bSigned <= - signed (cDataRaw18b);
end if;
end if;
end process;
cCoefMultSigned <= signed (cCoefMult);
cCoefAddSigned <= signed (cCoefAdd);
-- Apply the multiplicative coefficient. Register multiplication result.
ProcRegMultResult : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCalibMult <= (others => '0');
cDataInValidR <= '0';
elsif (rising_edge(SamplingClk)) then
cCalibMult <= cDataRaw18bSigned * cCoefMultSigned;
--Data out valid flag must be synchronized with its corresponding sample.
cDataInValidR <= cDataInValid;
end if;
end process;
-- Apply additive coefficient.
cCalibAdd <= cCalibMult + cCoefAddSigned;
-- Register calibration result; the calibration output is saturated at
-- 2^kWidth - 1 for positive values or -2^kWidth for negative values;
-- the calibration process is bypassed if cTestMode = '1'.
-- If at the start of the acquisition, this module puts on cCalibDataOut output signal the first acquired and calibrated samples,
-- together with cDataCalibValid = '1', but doDataAxisTready is not asserted, in the next clock cycle the value on cCalibDataOut will change,
-- since it will take the values of the next calibrated samples. This violates the AXI Stream interface specification.
ProcCalibDataAndValid : process (SamplingClk, acRst_n, cDataAcceptanceReady)
begin
if (acRst_n = '0') then
cCalibDataOut <= (others => '0');
cDataCalibValidLoc <= '0';
cFirstWordAccepted <= '0';
elsif (rising_edge(SamplingClk)) then
cDataCalibValidLoc <= cDataInValidR;
if (cDataCalibValidLoc = '1' and cDataAcceptanceReady = '1') then
cFirstWordAccepted <= '1';
end if;
if(cFirstWordAccepted = '0' or (cDataCalibValidLoc = '1' and cDataAcceptanceReady = '1')) then
cCalibDataOut <= cCalibDataOutLoc;
end if;
end if;
end process;
cDataCalibValid <= cDataCalibValidLoc;
cCalibDataOutLoc <= cDataRaw18b(17 downto 2) when cTestMode = '1' else
x"8000" when ((cCalibAdd(35) = '1') and (cCalibAdd(34 downto 33) /= "11")) else
x"7FFF" when ((cCalibAdd(35) = '0') and (cCalibAdd(34 downto 33) /= "00")) else
(std_logic_vector(cCalibAdd(33 downto 18)));
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/axi_ps2_1.0/src/axi_ps2_v1_0_S_AXI.vhd
|
1
|
22984
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_ps2_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
lTxDataReg : out std_logic_vector (31 downto 0);
lRxDataReg : in std_logic_vector (31 downto 0);
lRxAck : out std_logic;
lTxTrig : out std_logic;
lStatusReg : in std_logic_vector (31 downto 0);
IsrBitTxNoAck : in std_logic;
IsrBitTxAck : in std_logic;
IsrBitRxOvf : in std_logic;
IsrBitRxErr : in std_logic;
IsrBitRxFull : in std_logic;
SrstOut : out std_logic;
IntrOut : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_ps2_v1_0_S_AXI;
architecture arch_imp of axi_ps2_v1_0_S_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
signal TxDataWriteTrig : std_logic := '0';
signal SrstWriteTrig : std_logic := '0';
signal AuxRxAck : std_logic := '0';
signal CtlSrstOut : std_logic := '0';
signal a_IsrBuffReg :std_logic_vector (3 downto 0);
signal IsrBuffClr : std_logic := '0';
--------------------------------------------------
---- Number of Slave Registers 7
signal a_SrstReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_StsReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_RxDataReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_TxDataReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_GieReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_IsrReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_IerReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
a_StsReg <= lStatusReg;
a_RxDataReg <= lRxDataReg;
lTxDataReg <= a_TxDataReg ; --TX Data sent to TX FIFO
lTxTrig <= TxDataWriteTrig; --new data has been written to the TX Data register
lRxAck <= axi_rvalid when AuxRxAck = '1' else '0'; --this signal indicates when data has been read from the RX Data register
--interrupt signal generated
IntrOut <= a_GieReg(0) and ((a_IsrReg(30) and a_IerReg(30)) or (a_IsrReg(29) and a_IerReg(29)) or (a_IsrReg(28) and a_IerReg(28) ) or (a_IsrReg(27) and a_IerReg(27)) or (a_IsrReg(26) and a_IerReg(26)));
-- IntrOut <= (a_IsrReg(30) and a_IerReg(30)) or (a_IsrReg(29) and a_IerReg(29)) or (a_IsrReg(28) and a_IerReg(28) ) or (a_IsrReg(27) and a_IerReg(27)) or (IsrBitRxFull and a_IerReg(26));
SrstOut <= CtlSrstOut;
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' then
a_SrstReg <= (others => '0');
a_TxDataReg <= (others => '0');
TxDataWriteTrig <= '0';
SrstWriteTrig <= '0';
else
TxDataWriteTrig <= '0';
SrstWriteTrig <= '0';
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
a_SrstReg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
SrstWriteTrig <= '1';--signal indicates that the register has been written
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
a_TxDataReg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
TxDataWriteTrig <= '1';--signal indicates that the register has been written
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
end if;
end loop;
when others =>
a_SrstReg <= a_SrstReg;
a_TxDataReg <= a_TxDataReg;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (a_SrstReg, a_StsReg, a_RxDataReg, a_TxDataReg, a_GieReg, a_IsrReg, a_IerReg, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
AuxRxAck <= '0';
case loc_addr is
when b"000" =>
reg_data_out <= a_SrstReg;
when b"001" =>
reg_data_out <= a_StsReg;
when b"010" =>
reg_data_out <= a_RxDataReg;
AuxRxAck <= '1';
when b"011" =>
reg_data_out <= a_TxDataReg;
when b"100" =>
reg_data_out <= a_GieReg;
when b"101" =>
reg_data_out <= a_IsrReg;
when b"110" =>
reg_data_out <= a_IerReg;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--ISR signals buffer which helps the hw to avoid software-hardware conflicts on the ISR
a_IsrBuffReg_PROC: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' or IsrBuffClr = '1' then
a_IsrBuffReg <= (others => '0');
elsif (IsrBitTxNoAck = '1' or IsrBitTxAck = '1' or IsrBitRxOvf = '1' or IsrBitRxErr = '1') then
a_IsrBuffReg(3) <= IsrBitTxNoack or a_IsrBuffReg(3);
a_IsrBuffReg(2) <= IsrBitTxack or a_IsrBuffReg(2);
a_IsrBuffReg(1) <= IsrBitRxOvf or a_IsrBuffReg(1);
a_IsrBuffReg(0) <= IsrBitRxErr or a_IsrBuffReg(0);
end if;
end if;
end process;
--ISR management
a_IsrReg_PROC: process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' then
a_IsrReg <= (others => '0');
IsrBuffClr <= '0';
else
IsrBuffClr <= '0';
a_IsrReg(26) <= IsrBitRxFull;--This interrupt is not software resetable
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "101") then
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- using this construct gives the register toggle-on-write access
a_IsrReg(byte_index*8+7 downto byte_index*8) <= (a_IsrReg(byte_index*8+7 downto byte_index*8)) and (not (S_AXI_WDATA(byte_index*8+7 downto byte_index*8)));
end if;
end loop;
elsif (a_IsrBuffReg(3) = '1' or a_IsrBuffReg(2) = '1' or a_IsrBuffReg(1) = '1' or a_IsrBuffReg(0) = '1') then
--by or-ing the current value with the potentially new value, all the bits that are '1' will remain '1'
--clearing an interrupt is done above
a_IsrReg(30) <= a_IsrBuffReg(3) or a_IsrReg(30);
a_IsrReg(29) <= a_IsrBuffReg(2) or a_IsrReg(29);
a_IsrReg(28) <= a_IsrBuffReg(1) or a_IsrReg(28);
a_IsrReg(27) <= a_IsrBuffReg(0) or a_IsrReg(27);
IsrBuffClr <= '1';
end if;
end if;
end if;
end process;
--IER management
a_IerReg_PROC: process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' then
a_IerReg <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "110") then
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
--IER is only managed by the software
a_IerReg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
end if;
end if;
end if;
end process;
--GIE management
a_GieReg_PROC: process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' then
a_GieReg <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "100") then
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
--GIE is only managed by the software
a_GieReg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- GieWriteTrig <= '1';
end if;
end loop;
end if;
end if;
end if;
end process;
--Software reset process
a_SrstReg_PROC: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
CtlSrstOut <= '0';
--the hardwear is reset when 0xA is written to the register
elsif SrstWriteTrig = '1' and a_SrstReg = "00000000000000000000000000001010" then
CtlSrstOut <= '1';
else
CtlSrstOut <= '0';
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
mit
|
danesgo/i2s-rec-zybo
|
i2s-rec.vhd
|
1
|
3043
|
----------------------------------------------------------------------------------
-- Engineer: Daniel González
--
-- Create Date: 22:08:55 09/27/2015
-- Design Name:
-- Module Name: i2s_rec - Behavioral
-- Project Name:
-- Target Devices: Zybo Developing Board
-- Tool versions:
-- Description: i2s comunication module for recording audio trough the on board codec SSM2603 in slave mode, using default
-- configurations, Mic input(mono) 24-bit ADC @ 48KHz.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- SSM2603 Codec on the zybo
-- Rec Mono (One Channel) Fs=48Khz, BCLK = 1.152MHz (48000Hz * 24bits = 1.152Mhz)
entity i2s_rec is
generic(
width: integer := 24 -- Single Channel 24 bit ADC.
);
port(
clk: in std_logic; -- main zybo clock 125 MHz
recdat: in std_logic; -- data to be recorded
rst: in std_logic; --reset
--output
mclk: out std_logic; -- 12.2MHz (obtained from the SSM2603 codec datasheet)
bclk: out std_logic; -- 1.152MHz
reclrc: out std_logic; -- always low = '0' because it's always channel 1
mute: out std_logic; -- always high = '1' because it's never muted
done: out std_logic;
d_out: out std_logic_vector(width-1 downto 0)
);
end i2s_rec;
architecture Behavioral of i2s_rec is
--Signals Declarations
signal bclk_s: std_logic; --bit serial clock signal
signal mclk_s: std_logic; --master clock signal
signal CLKcount: integer range 0 to 55 := 0; -- Clock counter and divider 125MHz/1.152MHz = 108.5
signal CLKcnt: integer range 0 to 6 := 0; -- Clock counter an divider 125MHz/12.288MHz = 10.17
signal b_cnt: integer range 0 to width := 0;-- received bit counter
signal b_reg: std_logic_vector (width-1 downto 0); --received data vector
begin
Frec_DividerBCLK: process(clk, rst) begin
if (rst = '1') then
--reset state
bclk_s <= '0';
CLKcount <= 0;
elsif rising_edge(clk) then
if (CLKcount = 53) then --supposed to be 54 but that generates 1.136MHz
bclk_s <= not(bclk_s);
CLKcount <= 0;
else
CLKcount <= CLKcount + 1;
end if;
end if;
end process;
Frec_DividerMCLK: process(clk, rst) begin
if (rst = '1') then
--reset state
mclk_s <= '0';
CLKcnt <= 0;
elsif rising_edge(clk) then
if (CLKcnt = 4) then --supposed to be 5 but that generates 10.416MHz
mclk_s <= not(mclk_s);
CLKcnt <= 0;
else
CLKcnt <= CLKcnt + 1;
end if;
end if;
end process;
Data_ret: process(bclk_s, rst) begin
if (rst = '1') then
--reset state
elsif rising_edge(bclk_s) then
if (b_cnt = width-1) then
b_reg <= b_reg(width - 2 downto 0) & recdat; --Chapus!
b_cnt <= 0;
done <= '1';
else
b_reg <= b_reg(width - 2 downto 0) & recdat;
b_cnt <= b_cnt + 1;
done <= '0';
end if;
end if;
end process;
bclk <= bclk_s;
mclk <= mclk_s;
reclrc <= '0';
mute <= '1';
d_out <= b_reg;
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/fifo_w8_d3_A.vhd
|
2
|
4426
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d3_A_shiftReg;
architecture rtl of fifo_w8_d3_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d3_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d3_A is
component fifo_w8_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d3_A_shiftReg : fifo_w8_d3_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/combine_g_bar.vhd
|
1
|
3278
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:20:08 07/12/05
-- Design Name:
-- Module Name: combine_g_bar - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity combine_g_bar is
Port ( g1 : in std_logic_vector(8 downto 0);
g2 : in std_logic_vector(8 downto 0);
b1 : in std_logic_vector(8 downto 0);
b2 : in std_logic_vector(8 downto 0);
b3 : in std_logic_vector(8 downto 0);
b4 : in std_logic_vector(8 downto 0);
g1_2 : in std_logic_vector(8 downto 0);
g2_2 : in std_logic_vector(8 downto 0);
b1_2 : in std_logic_vector(8 downto 0);
b2_2 : in std_logic_vector(8 downto 0);
b3_2 : in std_logic_vector(8 downto 0);
b4_2 : in std_logic_vector(8 downto 0);
g_bar : out std_logic_vector(8 downto 0));
end combine_g_bar;
architecture Behavioral of combine_g_bar is
component sub_to_adder
Port ( pixel_in1 : in std_logic_vector(8 downto 0);
pixel_in2 : in std_logic_vector(8 downto 0);
pixel_in3 : in std_logic_vector(8 downto 0);
pixel_in4 : in std_logic_vector(8 downto 0);
pixel_in5 : in std_logic_vector(8 downto 0);
pixel_in6 : in std_logic_vector(8 downto 0);
adder_out : out std_logic_vector(10 downto 0));
end component;
component compare
Port ( Dhor : in std_logic_vector(10 downto 0);
Dver : in std_logic_vector(10 downto 0);
choose : out std_logic );
end component;
component adder_shift
Port ( g1 , g2 : in std_logic_vector(8 downto 0);
-- C0 : in std_logic;
S : out std_logic_vector(8 downto 0) );
end component;
component mux2t1_zoe
Port ( G1_adder_shift : in std_logic_vector(8 downto 0);
G2_adder_shift : in std_logic_vector(8 downto 0);
sele : in std_logic;
G_bar : out std_logic_vector(8 downto 0));
end component;
signal adder_out1: std_logic_vector(10 downto 0);
signal adder_out2: std_logic_vector(10 downto 0);
signal choose: std_logic;
signal G_choose1: std_logic_vector(8 downto 0);
signal G_choose2: std_logic_vector(8 downto 0);
begin
element1: sub_to_adder port map(
g1,g2,b1,b2,b3,b4,adder_out1);
element2: sub_to_adder port map(
g1_2,g2_2,b1_2,b2_2,b3_2,b4_2,adder_out2);
element3: compare port map(
adder_out1,adder_out2,choose);
element4: adder_shift port map(
g1,g2,G_choose1);
element5: adder_shift port map(
g1_2,g2_2,G_choose2);
element6: mux2t1_zoe port map(
G_choose1 , G_choose2 , choose , g_bar);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/tb/tb_MIPI_DPHY_Receiver.vhd
|
1
|
21767
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/26/2016 01:54:29 PM
-- Design Name:
-- Module Name: tb_MIPI_DPHY_Receiver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_MIPI_DPHY_Receiver is
-- Port ( );
end tb_MIPI_DPHY_Receiver;
architecture Behavioral of tb_MIPI_DPHY_Receiver is
component MIPI_DPHY_Receiver is
generic (
-- Users to add parameters here
kVersionMajor : natural := 0; -- TCL-propagated from VLNV
kVersionMinor : natural := 0; -- TCL-propagated from VLNV
kNoOfDataLanes : natural range 1 to 2:= 2;
kGenerateMMCM : boolean := false;
kGenerateAXIL : boolean := false;
kAddDelayClk_ps : integer := 0;
kAddDelayData0_ps : integer := 0;
kAddDelayData1_ps : integer := 0;
kRefClkFreqHz : integer := 200_000_000; -- TCL-propagated
kDebug : boolean := true;
kLPFromLane0 : boolean := true;
kSharedLogic : boolean := true;
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 4;
C_S_AXI_LITE_FREQ_HZ : integer := 100_000_000 -- TCL-propagated
);
port (
-- Users to add ports here
dphy_clk_hs_p : in std_logic;
dphy_clk_hs_n : in std_logic;
dphy_clk_lp_p : in std_logic;
dphy_clk_lp_n : in std_logic;
dphy_data_hs_p : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_hs_n : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_lp_p : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_lp_n : in std_logic_vector(kNoOfDataLanes-1 downto 0);
RefClk : in std_logic; --200MHz
aRst : in std_logic; --Only to be de-asserted when RefClk is valid
rDlyCtrlLockedIn : in std_logic; --if IDELAYCTRL instantiated externally, input its locked signal
rDlyCtrlLockedOut : out std_logic; --if IDELAYCTRL instantiated internally, output its locked signal
--PHY-Protocol Interface (PPI)
--Clock lane
RxDDRClkHS : out std_logic; --Receiver DDR Clock (may be used by the protocol)
aRxClkActiveHS : out std_logic; --Receiver Clock Active
aClkStopstate : out std_logic; --Lane is in Stop state
aClkEnable : in std_logic; --Enable Lane Module
aClkUlpsActiveNot : out std_logic; --ULP State (not) Active
aRxUlpsClkNot : out std_logic; --Receive Ultra-Low Power State on Clock Lane
aClkForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
aClkErrControl : out std_logic; --Control Error
RxByteClkHS : out std_logic; --High-Speed Receive Byte Clock
--Data lane 0
aD0Stopstate : out std_logic; --Lane is in Stop state
aD0Enable : in std_logic; --Enable Lane Module
aD0UlpsActiveNot : out std_logic; --ULP State (not) Active
rbD0RxDataHS : out std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbD0RxValidHS : out std_logic; --High-Speed Receive Data Valid
rbD0RxActiveHS : out std_logic; --High-Speed Reception Active
rbD0RxSyncHS : out std_logic; --Receiver Synchronization Observed (pulse)
rbD0ErrSotHS : out std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbD0ErrSotSyncHS : out std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD0ForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
D0RxClkEsc : out std_logic; --Escape mode Receive Clock (not periodic)
aD0RxDataEsc : out std_logic_vector(7 downto 0); --Escape mode Receive Data
aD0RxValidEsc : out std_logic; --Escape mode Receive Data Valid
aD0RxLpdtEsc : out std_logic; --Escape Low-Power Data Receive Mode
aD0RxUlpsEsc : out std_logic; --Escape Ultra-Low Power (Receive) mode
aD0RxTriggerEsc : out std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aD0ErrEsc : out std_logic; --Escape Entry Error
aD0ErrControl : out std_logic; --Control Error
--Data lane 1
aD1Stopstate : out std_logic; --Lane is in Stop state
aD1Enable : in std_logic; --Enable Lane Module
aD1UlpsActiveNot : out std_logic; --ULP State (not) Active
rbD1RxDataHS : out std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbD1RxValidHS : out std_logic; --High-Speed Receive Data Valid
rbD1RxActiveHS : out std_logic; --High-Speed Reception Active
rbD1RxSyncHS : out std_logic; --Receiver Synchronization Observed (pulse)
rbD1ErrSotHS : out std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbD1ErrSotSyncHS : out std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD1ForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
D1RxClkEsc : out std_logic; --Escape mode Receive Clock (not periodic)
aD1RxDataEsc : out std_logic_vector(7 downto 0); --Escape mode Receive Data
aD1RxValidEsc : out std_logic; --Escape mode Receive Data Valid
aD1RxLpdtEsc : out std_logic; --Escape Low-Power Data Receive Mode
aD1RxUlpsEsc : out std_logic; --Escape Ultra-Low Power (Receive) mode
aD1RxTriggerEsc : out std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aD1ErrEsc : out std_logic; --Escape Entry Error
aD1ErrControl : out std_logic; --Control Error
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end component MIPI_DPHY_Receiver;
function max(l : time; r : time) return time is
begin
if (l > r) then
return l;
else
return r;
end if;
end function max;
constant kUI : time := 2 ns; --500Mbps
constant kNoOfDataLanes : natural := 2;
constant kRefClkPeriod : time := 5 ns;
constant kTRst : time := 1us;
constant kT_LPX : time := 50 ns;
constant kT_HS_PREPARE : time := 40 ns + 4*kUI;
constant kT_HS_ZERO : time := 100 ns + 6*kUI;
constant kT_HS_TRAIL : time := max(1*8*kUI, 60 ns + 1*4*kUI);
constant kT_HS_EXIT : time := 100 ns;
constant kTInit : time := 100 us;
constant kT_CLK_PREPARE : time := 38ns; --max 95ns
constant kT_CLK_ZERO : time := 300ns - kT_CLK_PREPARE;
constant kT_CLK_PRE : time := 8*kUI;
constant kT_CLK_POST : time := 60 ns + 52*kUI;
constant kT_CLK_TRAIL : time := 60ns;
constant kSyncSeq : std_logic_vector(7 downto 0) := "10111000"; --least significant bit
type mem is array (natural range <>) of std_logic_vector(15 downto 0);
constant data_stim : mem := (x"78CC", x"0F00",
x"00FF", x"0200", x"DCB9", x"72F3", x"D4BB", x"5AB8", x"75C8", x"7CC2", x"F881", x"DF05", x"00FF", x"0100",
x"00F0",
--dummy data
x"04fc", x"3729"
);
type vector1 is array (natural range <>) of std_logic;
type vector2 is array (natural range <>) of std_logic_vector(1 downto 0);
type vector4 is array (natural range <>) of std_logic_vector(3 downto 0);
type vector8 is array (natural range <>) of std_logic_vector(7 downto 0);
signal RefClk, aRst : std_logic := '0';
signal DPHY_DataHS : std_logic_vector(0 to kNoOfDataLanes-1);
signal DPHY_DataLP : vector2(0 to kNoOfDataLanes-1);
signal DPHY_ClkHS : std_logic;
signal DPHY_ClkLP : std_logic_vector(1 downto 0);
signal RxDDRClkHS, RxByteClkHS : std_logic;
signal aRxClkActiveHS, aClkStopstate, aClkUlpsActiveNot, aRxUlpsClkNot, aClkErrControl : std_logic;
signal aClkEnable, aClkForceRxmode : std_logic;
signal aDxStopstate, aDxForceRxmode, aDxEnable, aDxUlpsActiveNot, rbDxRxValidHS, rbDxRxActiveHS, rbDxRxSyncHS,
aDxErrEsc, aDxErrControl, rbDxErrSotHS, rbDxErrSotSyncHS : vector1(0 to kNoOfDataLanes-1);
signal rbDxRxDataHS : vector8(0 to kNoOfDataLanes-1);
signal fClockReady,fData0Ready, fData1Ready : boolean := false;
procedure Stopstate(dur : in time; signal LP : out std_logic_vector(1 downto 0); signal HS : out std_logic) is
begin
LP <= "11";
HS <= 'X';
wait for dur;
end procedure;
procedure HS_Rqst(signal LP : out std_logic_vector(1 downto 0)) is
begin
LP <= "01";
wait for kT_LPX;
end procedure;
procedure HS_Prepare(signal LP : out std_logic_vector(1 downto 0)) is
begin
LP <= "00";
wait for kT_HS_PREPARE;
end procedure;
procedure HS_Zero(signal HS : out std_logic) is
begin
HS <= '0';
wait for kT_HS_ZERO;
end procedure;
procedure HS_Send0(nbits : in natural; signal HS : out std_logic) is
begin
for i in 0 to nbits-1 loop
HS <= '0';
wait until DPHY_ClkHS'event;
end loop;
end procedure;
procedure HS_Send(byte : in std_logic_vector(7 downto 0); signal HS : out std_logic) is
begin
for i in 0 to 7 loop
wait for kUI / 2; --90deg phase difference between data and clock
HS <= byte(i);
wait until DPHY_ClkHS'event;
end loop;
end procedure;
procedure HS_Trail(signal HS : out std_logic) is
begin
wait for kUI / 2;
HS <= '0';
wait for kT_HS_TRAIL;
end procedure;
begin
--200MHz reference clock
RefClk <= not RefClk after kRefClkPeriod / 2;
--Startup reset
aRst <= '1', '0' after kTRst;
aClkEnable <= '0', '1' after kTRst;
aDxEnable(0) <= '0', '1' after kTRst;
aDxEnable(1) <= '0', '1' after kTRst;
aClkForceRxmode <= '0';
aDxForceRxmode(0) <= '0';
aDxForceRxmode(1) <= '0';
ClockStimulus: process
procedure HS_Prepare is
begin
DPHY_ClkLP <= "00";
wait for kT_CLK_PREPARE;
end procedure;
procedure HS_Zero is
begin
DPHY_ClkHS <= '0';
wait for kT_CLK_ZERO;
end procedure;
procedure HS_ClkPrePost(t : in time) is
variable start : time;
begin
start := now;
loop
DPHY_ClkHS <= not DPHY_ClkHS;
wait for kUI;
if (now - start > t) then
exit;
end if;
end loop;
end procedure;
procedure HS_Trail is
begin
wait for kUI / 2;
DPHY_ClkHS <= '0';
wait for kT_CLK_TRAIL;
end procedure;
begin
Stopstate(kTInit + 1 us, DPHY_ClkLP, DPHY_ClkHS);
HS_Rqst(DPHY_ClkLP);
HS_Prepare;
HS_Zero;
HS_ClkPrePost(kT_CLK_PRE);
fClockReady <= true;
loop
DPHY_ClkHS <= not DPHY_ClkHS;
wait for kUI;
if (fData0Ready and fData1Ready) then
exit;
end if;
end loop;
HS_ClkPrePost(kT_CLK_POST);
HS_Trail;
Stopstate(kT_HS_EXIT, DPHY_ClkLP, DPHY_ClkHS);
wait;
end process ClockStimulus;
DataStimulus0: process
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10.0; -- the range of random values created will be 0 to +1000.
variable to_send : natural;
begin
Stopstate(kTInit + 1 us, DPHY_DataLP(0), DPHY_DataHS(0));
wait until fClockReady;
HS_Rqst(DPHY_DataLP(0));
HS_Prepare(DPHY_DataLP(0));
wait for kUI; -- this will test different word alignments
HS_Zero(DPHY_DataHS(0));
wait until Falling_Edge(DPHY_ClkHS);
HS_Send(kSyncSeq, DPHY_DataHS(0));
uniform(seed1, seed2, rand); -- generate random number
for j in data_stim'range loop
HS_Send(data_stim(j)(7 downto 0), DPHY_DataHS(0));
end loop;
-- for j in 0 to integer(rand*range_of_rand) loop
-- case (j) is
-- when 0 => HS_Send(x"DE",DPHY_DataHS(0));
-- when 1 => HS_Send(x"AD",DPHY_DataHS(0));
-- when 2 => HS_Send(x"BE",DPHY_DataHS(0));
-- when 3 => HS_Send(x"EF",DPHY_DataHS(0));
-- when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)), DPHY_DataHS(0));
-- end case;
-- end loop;
HS_Trail(DPHY_DataHS(0));
Stopstate(kT_HS_EXIT, DPHY_DataLP(0), DPHY_DataHS(0));
HS_Rqst(DPHY_DataLP(0));
HS_Prepare(DPHY_DataLP(0));
wait for kUI; -- this will test different word alignments
HS_Zero(DPHY_DataHS(0));
wait until Falling_Edge(DPHY_ClkHS);
HS_Send(kSyncSeq, DPHY_DataHS(0));
uniform(seed1, seed2, rand); -- generate random number
for j in data_stim'range loop
HS_Send(data_stim(j)(7 downto 0), DPHY_DataHS(0));
end loop;
-- for j in 0 to integer(rand*range_of_rand) loop
-- case (j) is
-- when 0 => HS_Send(x"DE",DPHY_DataHS(0));
-- when 1 => HS_Send(x"AD",DPHY_DataHS(0));
-- when 2 => HS_Send(x"BE",DPHY_DataHS(0));
-- when 3 => HS_Send(x"EF",DPHY_DataHS(0));
-- when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)), DPHY_DataHS(0));
-- end case;
-- end loop;
HS_Trail(DPHY_DataHS(0));
Stopstate(kT_HS_EXIT, DPHY_DataLP(0), DPHY_DataHS(0));
fData0Ready <= true;
wait;
end process DataStimulus0;
DataStimulus1: process
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10.0; -- the range of random values created will be 0 to +1000.
variable to_send : natural;
begin
Stopstate(kTInit + 1 us, DPHY_DataLP(1), DPHY_DataHS(1));
wait until fClockReady;
HS_Rqst(DPHY_DataLP(1));
HS_Prepare(DPHY_DataLP(1));
wait for kUI; -- this will test different word alignments
HS_Zero(DPHY_DataHS(1));
wait until Falling_Edge(DPHY_ClkHS);
HS_Send(kSyncSeq, DPHY_DataHS(1));
uniform(seed1, seed2, rand); -- generate random number
for j in data_stim'range loop
HS_Send(data_stim(j)(15 downto 8), DPHY_DataHS(1));
end loop;
-- for j in 0 to integer(rand*range_of_rand) loop
-- case (j) is
-- when 0 => HS_Send(x"DE",DPHY_DataHS(1));
-- when 1 => HS_Send(x"AD",DPHY_DataHS(1));
-- when 2 => HS_Send(x"BE",DPHY_DataHS(1));
-- when 3 => HS_Send(x"EF",DPHY_DataHS(1));
-- when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)), DPHY_DataHS(1));
-- end case;
-- end loop;
HS_Trail(DPHY_DataHS(1));
Stopstate(kT_HS_EXIT, DPHY_DataLP(1), DPHY_DataHS(1));
HS_Rqst(DPHY_DataLP(1));
HS_Prepare(DPHY_DataLP(1));
wait for kUI; -- this will test different word alignments
HS_Zero(DPHY_DataHS(1));
wait until Falling_Edge(DPHY_ClkHS);
HS_Send(kSyncSeq, DPHY_DataHS(1));
uniform(seed1, seed2, rand); -- generate random number
for j in data_stim'range loop
HS_Send(data_stim(j)(15 downto 8), DPHY_DataHS(1));
end loop;
-- for j in 0 to integer(rand*range_of_rand) loop
-- case (j) is
-- when 0 => HS_Send(x"DE",DPHY_DataHS(1));
-- when 1 => HS_Send(x"AD",DPHY_DataHS(1));
-- when 2 => HS_Send(x"BE",DPHY_DataHS(1));
-- when 3 => HS_Send(x"EF",DPHY_DataHS(1));
-- when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)), DPHY_DataHS(1));
-- end case;
-- end loop;
HS_Trail(DPHY_DataHS(1));
Stopstate(kT_HS_EXIT, DPHY_DataLP(1), DPHY_DataHS(1));
fData1Ready <= true;
wait;
end process DataStimulus1;
DUT: MIPI_DPHY_Receiver
generic map (
kNoOfDataLanes => kNoOfDataLanes,
kDebug => false,
kSharedLogic => true,
kGenerateMMCM => false,
kAddDelayClk_ps => 0,
kAddDelayData0_ps => 0,
kAddDelayData1_ps => -500
)
port map (
dphy_clk_hs_p => DPHY_ClkHS,
dphy_clk_hs_n => not DPHY_ClkHS,
dphy_clk_lp_n => DPHY_ClkLP(0), --Dn is LP(0)
dphy_clk_lp_p => DPHY_ClkLP(1), --Dp is LP(1)
dphy_data_hs_p => DPHY_DataHS,
dphy_data_hs_n => not DPHY_DataHS,
dphy_data_lp_n => DPHY_DataLP(0)(0) & DPHY_DataLP(1)(0), --Dn is LP(0)
dphy_data_lp_p => DPHY_DataLP(0)(1) & DPHY_DataLP(1)(1), --Dp is LP(1)
RefClk => RefClk,
aRst => aRst,
rDlyCtrlLockedIn => '0', --unused if kSharedLogic=true
--PHY-Protocol Interface (PPI)
--Clock lane
RxDDRClkHS => RxDDRClkHS, --Receiver DDR Clock (may be used by the protocol)
aRxClkActiveHS => aRxClkActiveHS, --Receiver Clock Active
aClkStopstate => aClkStopstate, --Lane is in Stop state
aClkEnable => aClkEnable, --Enable Lane Module
aClkUlpsActiveNot => aClkUlpsActiveNot, --ULP State (not) Active
aRxUlpsClkNot => aRxUlpsClkNot, --Receive Ultra-Low Power State on Clock Lane
aClkForceRxmode => aClkForceRxmode, --Force Lane Module Into Receive mode / Wait for Stop state
aClkErrControl => aClkErrControl, --Control Error
RxByteClkHS => RxByteClkHS, --High-Speed Receive Byte Clock
--Data lane 0
aD0Stopstate => aDxStopstate(0), --Lane is in Stop state
aD0Enable => aDxEnable(0), --Enable Lane Module
aD0UlpsActiveNot => aDxUlpsActiveNot(0), --ULP State (not) Active
rbD0RxDataHS => rbDxRxDataHS(0), --High-Speed Receive Data (least-significant first)
rbD0RxValidHS => rbDxRxValidHS(0), --High-Speed Receive Data Valid
rbD0RxActiveHS => rbDxRxActiveHS(0), --High-Speed Reception Active
rbD0RxSyncHS => rbDxRxSyncHS(0), --Receiver Synchronization Observed (pulse)
rbD0ErrSotHS => rbDxErrSotHS(0), --Start-of-Transmission (SoT) Error (pulse)
rbD0ErrSotSyncHS => rbDxErrSotSyncHS(0), --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD0ForceRxmode => aDxForceRxmode(0), --Force Lane Module Into Receive mode / Wait for Stop state
D0RxClkEsc => open, --Escape mode Receive Clock (not periodic)
aD0RxDataEsc => open, --Escape mode Receive Data
aD0RxValidEsc => open, --Escape mode Receive Data Valid
aD0RxLpdtEsc => open, --Escape Low-Power Data Receive Mode
aD0RxUlpsEsc => open, --Escape Ultra-Low Power (Receive) mode
aD0RxTriggerEsc => open, --Escape mode Receive Trigger 3-0
aD0ErrEsc => aDxErrEsc(0), --Escape Entry Error
aD0ErrControl => aDxErrControl(0), --Control Error
--Data lane 1
aD1Stopstate => aDxStopstate(1), --Lane is in Stop state
aD1Enable => aDxEnable(1), --Enable Lane Module
aD1UlpsActiveNot => aDxUlpsActiveNot(1), --ULP State (not) Active
rbD1RxDataHS => rbDxRxDataHS(1), --High-Speed Receive Data (least-significant first)
rbD1RxValidHS => rbDxRxValidHS(1), --High-Speed Receive Data Valid
rbD1RxActiveHS => rbDxRxActiveHS(1), --High-Speed Reception Active
rbD1RxSyncHS => rbDxRxSyncHS(1), --Receiver Synchronization Observed (pulse)
rbD1ErrSotHS => rbDxErrSotHS(1), --Start-of-Transmission (SoT) Error (pulse)
rbD1ErrSotSyncHS => rbDxErrSotSyncHS(1), --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD1ForceRxmode => aDxForceRxmode(1), --Force Lane Module Into Receive mode / Wait for Stop state
D1RxClkEsc => open, --Escape mode Receive Clock (not periodic)
aD1RxDataEsc => open, --Escape mode Receive Data
aD1RxValidEsc => open, --Escape mode Receive Data Valid
aD1RxLpdtEsc => open, --Escape Low-Power Data Receive Mode
aD1RxUlpsEsc => open, --Escape Ultra-Low Power (Receive) mode
aD1RxTriggerEsc => open, --Escape mode Receive Trigger 3-0
aD1ErrEsc => aDxErrEsc(1), --Escape Entry Error
aD1ErrControl => aDxErrControl(1), --Control Error
-- -- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk => '0',
s_axi_lite_aresetn => '0',
s_axi_lite_awaddr => (others => '0'),
s_axi_lite_awprot => (others => '0'),
s_axi_lite_awvalid => '0',
s_axi_lite_awready => open,
s_axi_lite_wdata => (others => '0'),
s_axi_lite_wstrb => (others => '0'),
s_axi_lite_wvalid => '0',
s_axi_lite_wready => open,
s_axi_lite_bresp => open,
s_axi_lite_bvalid => open,
s_axi_lite_bready => '0',
s_axi_lite_araddr => (others => '0'),
s_axi_lite_arprot => (others => '0'),
s_axi_lite_arvalid => '0',
s_axi_lite_arready => open,
s_axi_lite_rdata => open,
s_axi_lite_rresp => open,
s_axi_lite_rvalid => open,
s_axi_lite_rready => '0'
);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_dEe.vhd
|
1
|
9702
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_dEe_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_dEe_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 to 73=> "00000000", 74 to 91=> "00000001", 92 to 101=> "00000010", 102 to 108=> "00000011",
109 to 113=> "00000100", 114 to 118=> "00000101", 119 to 122=> "00000110", 123 to 125=> "00000111",
126 to 129=> "00001000", 130 to 132=> "00001001", 133 to 134=> "00001010", 135 to 137=> "00001011",
138 to 139=> "00001100", 140 to 141=> "00001101", 142 to 143=> "00001110", 144 to 145=> "00001111",
146 to 147=> "00010000", 148 to 149=> "00010001", 150 => "00010010", 151 to 152=> "00010011",
153 to 154=> "00010100", 155 => "00010101", 156 => "00010110", 157 to 158=> "00010111",
159 => "00011000", 160 => "00011001", 161 to 162=> "00011010", 163 => "00011011",
164 => "00011100", 165 => "00011101", 166 => "00011110", 167 => "00011111",
168 => "00100000", 169 => "00100001", 170 => "00100010", 171 => "00100011",
172 => "00100100", 173 => "00100101", 174 => "00100110", 175 => "00100111",
176 => "00101000", 177 => "00101001", 178 => "00101010", 179 => "00101011",
180 => "00101101", 181 => "00101110", 182 => "00101111", 183 => "00110001",
184 => "00110010", 185 => "00110011", 186 => "00110101", 187 => "00110110",
188 => "00111000", 189 => "00111001", 190 => "00111011", 191 => "00111100",
192 => "00111110", 193 => "00111111", 194 => "01000001", 195 => "01000011",
196 => "01000100", 197 => "01000110", 198 => "01001000", 199 => "01001010",
200 => "01001100", 201 => "01001110", 202 => "01010000", 203 => "01010010",
204 => "01010100", 205 => "01010110", 206 => "01011000", 207 => "01011010",
208 => "01011100", 209 => "01011110", 210 => "01100001", 211 => "01100011",
212 => "01100101", 213 => "01101000", 214 => "01101010", 215 => "01101101",
216 => "01101111", 217 => "01110010", 218 => "01110100", 219 => "01110111",
220 => "01111010", 221 => "01111101", 222 => "10000000", 223 => "10000010",
224 => "10000101", 225 => "10001000", 226 => "10001011", 227 => "10001111",
228 => "10010010", 229 => "10010101", 230 => "10011000", 231 => "10011100",
232 => "10011111", 233 => "10100010", 234 => "10100110", 235 => "10101010",
236 => "10101101", 237 => "10110001", 238 => "10110101", 239 => "10111000",
240 => "10111100", 241 => "11000000", 242 => "11000100", 243 => "11001000",
244 => "11001101", 245 => "11010001", 246 => "11010101", 247 => "11011001",
248 => "11011110", 249 => "11100010", 250 => "11100111", 251 => "11101100",
252 => "11110000", 253 => "11110101", 254 => "11111010", 255 => "11111111" );
signal mem1 : mem_array := (
0 to 73=> "00000000", 74 to 91=> "00000001", 92 to 101=> "00000010", 102 to 108=> "00000011",
109 to 113=> "00000100", 114 to 118=> "00000101", 119 to 122=> "00000110", 123 to 125=> "00000111",
126 to 129=> "00001000", 130 to 132=> "00001001", 133 to 134=> "00001010", 135 to 137=> "00001011",
138 to 139=> "00001100", 140 to 141=> "00001101", 142 to 143=> "00001110", 144 to 145=> "00001111",
146 to 147=> "00010000", 148 to 149=> "00010001", 150 => "00010010", 151 to 152=> "00010011",
153 to 154=> "00010100", 155 => "00010101", 156 => "00010110", 157 to 158=> "00010111",
159 => "00011000", 160 => "00011001", 161 to 162=> "00011010", 163 => "00011011",
164 => "00011100", 165 => "00011101", 166 => "00011110", 167 => "00011111",
168 => "00100000", 169 => "00100001", 170 => "00100010", 171 => "00100011",
172 => "00100100", 173 => "00100101", 174 => "00100110", 175 => "00100111",
176 => "00101000", 177 => "00101001", 178 => "00101010", 179 => "00101011",
180 => "00101101", 181 => "00101110", 182 => "00101111", 183 => "00110001",
184 => "00110010", 185 => "00110011", 186 => "00110101", 187 => "00110110",
188 => "00111000", 189 => "00111001", 190 => "00111011", 191 => "00111100",
192 => "00111110", 193 => "00111111", 194 => "01000001", 195 => "01000011",
196 => "01000100", 197 => "01000110", 198 => "01001000", 199 => "01001010",
200 => "01001100", 201 => "01001110", 202 => "01010000", 203 => "01010010",
204 => "01010100", 205 => "01010110", 206 => "01011000", 207 => "01011010",
208 => "01011100", 209 => "01011110", 210 => "01100001", 211 => "01100011",
212 => "01100101", 213 => "01101000", 214 => "01101010", 215 => "01101101",
216 => "01101111", 217 => "01110010", 218 => "01110100", 219 => "01110111",
220 => "01111010", 221 => "01111101", 222 => "10000000", 223 => "10000010",
224 => "10000101", 225 => "10001000", 226 => "10001011", 227 => "10001111",
228 => "10010010", 229 => "10010101", 230 => "10011000", 231 => "10011100",
232 => "10011111", 233 => "10100010", 234 => "10100110", 235 => "10101010",
236 => "10101101", 237 => "10110001", 238 => "10110101", 239 => "10111000",
240 => "10111100", 241 => "11000000", 242 => "11000100", 243 => "11001000",
244 => "11001101", 245 => "11010001", 246 => "11010101", 247 => "11011001",
248 => "11011110", 249 => "11100010", 250 => "11100111", 251 => "11101100",
252 => "11110000", 253 => "11110101", 254 => "11111010", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_dEe is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_dEe is
component Loop_loop_height_dEe_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_dEe_rom_U : component Loop_loop_height_dEe_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
chrismasters/fpga-space-invaders
|
project/registerarray.vhd
|
1
|
3350
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- selector encoding
-- 00000001 - B
-- 00000010 - C
-- 00000100 - D
-- 00001000 - E
-- 00010000 - H
-- 00100000 - L
-- 00000011 - BC
-- 00001100 - DE
-- 00110000 - HL
-- 01000000 - SP
-- 10000000 - PC
entity RegisterArray is
Port (
clk : in STD_LOGIC;
selector : in STD_LOGIC_VECTOR (7 downto 0);
dataIn : in STD_LOGIC_VECTOR (15 downto 0);
dataOut : out STD_LOGIC_VECTOR (15 downto 0);
load : in STD_LOGIC
);
end RegisterArray;
architecture Behavioral of RegisterArray is
COMPONENT OneByteRegister
PORT(
clk : IN std_logic;
load : IN std_logic;
dataIn : IN std_logic_vector(7 downto 0);
dataOut : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT DoubleByteRegister
PORT(
clk : IN std_logic;
load : IN std_logic;
dataIn : IN std_logic_vector(15 downto 0);
dataOut : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
signal bIn : std_logic_vector(7 downto 0);
signal cIn : std_logic_vector(7 downto 0);
signal dIn : std_logic_vector(7 downto 0);
signal eIn : std_logic_vector(7 downto 0);
signal hIn : std_logic_vector(7 downto 0);
signal lIn : std_logic_vector(7 downto 0);
signal spIn : std_logic_vector(15 downto 0);
--signal pcIn : std_logic_vector(15 downto 0);
signal bOut : std_logic_vector(7 downto 0);
signal cOut : std_logic_vector(7 downto 0);
signal dOut : std_logic_vector(7 downto 0);
signal eOut : std_logic_vector(7 downto 0);
signal hOut : std_logic_vector(7 downto 0);
signal lOut : std_logic_vector(7 downto 0);
signal spOut : std_logic_vector(15 downto 0);
begin
dataOut <=
"00000000" & bOut when selector = "00000001" else
"00000000" & cOut when selector = "00000010" else
"00000000" & dOut when selector = "00000100" else
"00000000" & eOut when selector = "00001000" else
"00000000" & hOut when selector = "00010000" else
"00000000" & lOut when selector = "00100000" else
bOut & cOut when selector = "00000011" else
dOut & eOut when selector = "00001100" else
hOut & lOut when selector = "00110000" else
spOut when selector = "01000000" else
--pcOut when selector = "10000000" else
(others => '0');
bIn <= dataIn(15 downto 8) when selector(0) = '1' and selector(1) = '1' else dataIn(7 downto 0);
cIn <= dataIn(7 downto 0);
dIn <= dataIn(15 downto 8) when selector(2) = '1' and selector(3) = '1' else dataIn(7 downto 0);
eIn <= dataIn(7 downto 0);
hIn <= dataIn(15 downto 8) when selector(4) = '1' and selector(5) = '1' else dataIn(7 downto 0);
lIn <= dataIn(7 downto 0);
b: OneByteRegister PORT MAP(clk => clk, load => load and selector(0), dataIn => bIn, dataOut => bOut);
c: OneByteRegister PORT MAP(clk => clk, load => load and selector(1), dataIn => cIn, dataOut => cOut);
d: OneByteRegister PORT MAP(clk => clk, load => load and selector(2), dataIn => dIn, dataOut => dOut);
e: OneByteRegister PORT MAP(clk => clk, load => load and selector(3), dataIn => eIn, dataOut => eOut);
h: OneByteRegister PORT MAP(clk => clk, load => load and selector(4), dataIn => hIn, dataOut => hOut);
l: OneByteRegister PORT MAP(clk => clk, load => load and selector(5), dataIn => lIn, dataOut => lOut);
sp: DoubleByteRegister PORT MAP(clk => clk, load => load and selector(6), dataIn => dataIn, dataOut => spOut);
--pc: DoubleByteRegister PORT MAP(clk => clk, load => load(7), dataIn => dataIn, dataOut => pcOut);
end Behavioral;
|
mit
|
chrismasters/fpga-notes
|
sdramcontroller/sdramcontroller_testbench.vhd
|
1
|
3498
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT sdramcontroller
PORT(
clk : IN std_logic;
addr : IN std_logic_vector(15 downto 0);
cmd : IN std_logic_vector(1 downto 0);
dataIn : IN std_logic_vector(7 downto 0);
dataOut : OUT std_logic_vector(7 downto 0);
ready : OUT std_logic;
chipCS : OUT std_logic;
chipWE : OUT std_logic;
chipCAS : OUT std_logic;
chipRAS : OUT std_logic;
chipDQML : OUT std_logic;
chipDQMH : OUT std_logic;
chipBA : OUT std_logic_vector(1 downto 0);
chipADDR : OUT std_logic_vector(11 downto 0);
chipDATA : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mt48lc4m16a2
PORT(
Addr : IN std_logic_vector(11 downto 0);
Ba : IN std_logic_vector(1 downto 0);
Clk : IN std_logic;
Cke : IN std_logic;
Cs_n : IN std_logic;
Ras_n : IN std_logic;
Cas_n : IN std_logic;
We_n : IN std_logic;
Dqm : IN std_logic_vector(1 downto 0);
Dq : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;
SIGNAL clk : std_logic;
SIGNAL clkinv : std_logic;
SIGNAL addr : std_logic_vector(15 downto 0) := (others => '0');
SIGNAL cmd : std_logic_vector(1 downto 0) := "00";
SIGNAL dataIn : std_logic_vector(7 downto 0) := (others => 'Z');
SIGNAL dataOut : std_logic_vector(7 downto 0) := (others => 'Z');
SIGNAL ready : std_logic;
SIGNAL chipCS : std_logic;
SIGNAL chipWE : std_logic;
SIGNAL chipCAS : std_logic;
SIGNAL chipRAS : std_logic;
SIGNAL chipDQML : std_logic;
SIGNAL chipDQMH : std_logic;
SIGNAL dqm : std_logic_vector(1 downto 0);
SIGNAL chipBA : std_logic_vector(1 downto 0);
SIGNAL chipADDR : std_logic_vector(11 downto 0);
SIGNAL chipDATA : std_logic_vector(15 downto 0) := (others => 'Z');
constant clk_period : time := 7.518ns;
BEGIN
dqm <= chipDQMH & chipDQML;
clkinv <= not clk;
uut: sdramcontroller PORT MAP(
clk => clk,
addr => addr,
dataIn => dataIn,
dataOut => dataOut,
cmd => cmd,
ready => ready,
chipCS => chipCS,
chipWE => chipWE,
chipCAS => chipCAS,
chipRAS => chipRAS,
chipDQML => chipDQML,
chipDQMH => chipDQMH,
chipBA => chipBA,
chipADDR => chipADDR,
chipDATA => chipDATA
);
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process clk_process;
Inst_mt48lc4m16a2: mt48lc4m16a2 PORT MAP(
Dq => chipDATA,
Addr => chipADDR,
Ba => chipBA,
Clk => clkinv,
Cke => '1',
Cs_n => chipCS,
Ras_n => chipRAS,
Cas_n => chipCAS,
We_n => chipWE,
Dqm => dqm
);
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
wait for 1000 ns;
--assert ready = '1' report "end of init sequence and controller not ready" severity failure;
addr <= "0000000000011110";
dataIn <= "11110101";
cmd <= "11";
wait for 20ns;
cmd <= "00";
wait for 30ns;
assert chipData = "0000000011110101" report "chipData out didn't contain right data" severity failure;
--chipDATA <= "0000000001010101";
addr <= "0000000000011110";
cmd <= "01";
wait for 20ns;
cmd <= "00";
wait for 60ns;
assert ready = '1' report "end of read sequence and controller not ready" severity failure;
assert dataOut = "11110101" report "data out didn't contain right data" severity failure;
--chipDATA <= (others => 'Z');
wait; -- will wait forever
END PROCESS tb;
END;
|
mit
|
chrismasters/fpga-space-invaders
|
project/ipcore_dir/clocks.vhd
|
1
|
6868
|
-- file: clocks.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____10.000______0.000______50.0______439.530____196.077
-- CLK_OUT2___133.333______0.000______50.0______230.136____196.077
-- CLK_OUT3___133.333____180.000______50.0______230.136____196.077
-- CLK_OUT4____25.000______0.000______50.0______364.543____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocks is
port
(-- Clock in ports
clkin : in std_logic;
-- Clock out ports
clk10mhz : out std_logic;
clk133mhz : out std_logic;
clk133mhzinv : out std_logic;
clk25mhz : out std_logic
);
end clocks;
architecture xilinx of clocks is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocks,clk_wiz_v3_6,{component_name=clocks,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3 : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clkin);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 80,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 6,
CLKOUT2_PHASE => 180.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 32,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => clk10mhz,
I => clkout0);
clkout2_buf : BUFG
port map
(O => clk133mhz,
I => clkout1);
clkout3_buf : BUFG
port map
(O => clk133mhzinv,
I => clkout2);
clkout4_buf : BUFG
port map
(O => clk25mhz,
I => clkout3);
end xilinx;
|
mit
|
chrismasters/fpga-notes
|
sdramcontroller/ipcore_dir/clks.vhd
|
1
|
6296
|
-- file: clks.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___133.333______0.000______50.0______230.136____196.077
-- CLK_OUT2___133.333____180.000______50.0______230.136____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clks is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end clks;
architecture xilinx of clks is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clks,clk_wiz_v3_6,{component_name=clks,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 6,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 180.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
mit
|
chrismasters/fpga-space-invaders
|
project/ipcore_dir/rom/example_design/rom_prod.vhd
|
1
|
9871
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: rom_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : rom.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END rom_prod;
ARCHITECTURE xilinx OF rom_prod IS
COMPONENT rom_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : rom_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
mit
|
chrismasters/fpga-space-invaders
|
project/ipcore_dir/ram/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
mit
|
nussbrot/code-exchange
|
wb_test/src/vhdl/wbi_test.vhd
|
2
|
10667
|
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2017 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used AND/OR copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
--*
--* @short INTERCON
--* Generated by TCL script gen_intercon.tcl. Do not edit this file.
--* @author wrupprecht
--*
-------------------------------------------------------------------------------
-- for defines see wbi_test.sxl
--
-- Generated Tue Jun 20 15:35:45 CEST 2017
--
-- Wishbone masters:
-- wbm_1
-- wbm_2
--
-- Wishbone slaves:
-- wbs_1
-- baseaddr 0x00000000 - size 0x00000100
-- wbs_2
-- baseaddr 0x00000200 - size 0x00000010
-- wbs_3
-- baseaddr 0x00100000 - size 0x00001000
--
-- Intercon type: SharedBus
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY rtl_lib;
ENTITY wbi_test IS
PORT (
-- wishbone master port(s)
-- wbm_1
i_wbm_1_o_cyc : IN STD_LOGIC;
i_wbm_1_o_stb : IN STD_LOGIC;
i_wbm_1_o_we : IN STD_LOGIC;
i_wbm_1_o_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbm_1_o_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbm_1_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_1_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_1_i_ack : OUT STD_LOGIC;
o_wbm_1_i_rty : OUT STD_LOGIC;
o_wbm_1_i_err : OUT STD_LOGIC;
-- wbm_2
i_wbm_2_o_cyc : IN STD_LOGIC;
i_wbm_2_o_stb : IN STD_LOGIC;
i_wbm_2_o_we : IN STD_LOGIC;
i_wbm_2_o_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbm_2_o_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbm_2_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_2_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_2_i_ack : OUT STD_LOGIC;
o_wbm_2_i_rty : OUT STD_LOGIC;
o_wbm_2_i_err : OUT STD_LOGIC;
-- wishbone slave port(s)
-- wbs_1
o_wbs_1_i_cyc : OUT STD_LOGIC;
o_wbs_1_i_stb : OUT STD_LOGIC;
o_wbs_1_i_we : OUT STD_LOGIC;
o_wbs_1_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_1_i_addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_wbs_1_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_1_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_1_o_ack : IN STD_LOGIC;
i_wbs_1_o_rty : IN STD_LOGIC;
i_wbs_1_o_err : IN STD_LOGIC;
-- wbs_2
o_wbs_2_i_cyc : OUT STD_LOGIC;
o_wbs_2_i_stb : OUT STD_LOGIC;
o_wbs_2_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_2_i_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbs_2_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_2_o_ack : IN STD_LOGIC;
i_wbs_2_o_rty : IN STD_LOGIC;
i_wbs_2_o_err : IN STD_LOGIC;
-- wbs_3
o_wbs_3_i_cyc : OUT STD_LOGIC;
o_wbs_3_i_stb : OUT STD_LOGIC;
o_wbs_3_i_we : OUT STD_LOGIC;
o_wbs_3_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_3_i_addr : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_wbs_3_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_3_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_3_o_ack : IN STD_LOGIC;
i_wbs_3_o_rty : IN STD_LOGIC;
i_wbs_3_o_err : IN STD_LOGIC;
-- clock and reset
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC := '1');
END ENTITY wbi_test;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF wbi_test IS
FUNCTION "AND" (
le : STD_LOGIC_VECTOR;
ri : STD_LOGIC)
RETURN STD_LOGIC_VECTOR IS
VARIABLE v_result : STD_LOGIC_VECTOR(le'RANGE);
BEGIN
FOR i IN le'RANGE LOOP
v_result(i) := le(i) AND ri;
END LOOP;
RETURN v_result;
END FUNCTION "AND";
SIGNAL s_wbm_1_bg : STD_LOGIC; -- bus grant
SIGNAL s_wbm_2_bg : STD_LOGIC; -- bus grant
SIGNAL s_wbs_1_ss : STD_LOGIC; -- slave select
SIGNAL s_wbs_2_ss : STD_LOGIC; -- slave select
SIGNAL s_wbs_3_ss : STD_LOGIC; -- slave select
BEGIN -- rtl
arbiter_sharedbus : BLOCK
SIGNAL s_wbm_1_bg_1 : STD_LOGIC;
SIGNAL s_wbm_1_bb_1 : STD_LOGIC;
SIGNAL s_wbm_1_bg_2 : STD_LOGIC;
SIGNAL s_wbm_1_bb_2 : STD_LOGIC;
SIGNAL s_wbm_1_bg_q : STD_LOGIC;
SIGNAL s_wbm_2_bg_1 : STD_LOGIC;
SIGNAL s_wbm_2_bb_1 : STD_LOGIC;
SIGNAL s_wbm_2_bg_2 : STD_LOGIC;
SIGNAL s_wbm_2_bb_2 : STD_LOGIC;
SIGNAL s_wbm_2_bg_q : STD_LOGIC;
SIGNAL s_wbm_1_traffic_ctrl_limit : STD_LOGIC;
SIGNAL s_wbm_2_traffic_ctrl_limit : STD_LOGIC;
SIGNAL s_ack : STD_LOGIC;
SIGNAL s_ce : STD_LOGIC;
SIGNAL s_idle : STD_LOGIC;
BEGIN -- arbiter
s_ack <= i_wbs_1_o_ack OR i_wbs_2_o_ack OR i_wbs_3_o_ack;
wb_traffic_supervision_1 : ENTITY rtl_lib.wb_traffic_supervision
GENERIC MAP (
g_priority => 1,
g_tot_priority => 2)
PORT MAP (
i_bg => s_wbm_1_bg,
i_ce => s_ce,
o_traffic_limit => s_wbm_1_traffic_ctrl_limit,
clk => clk,
rst_n => rst_n);
wb_traffic_supervision_2 : ENTITY rtl_lib.wb_traffic_supervision
GENERIC MAP (
g_priority => 1,
g_tot_priority => 2)
PORT MAP (
i_bg => s_wbm_2_bg,
i_ce => s_ce,
o_traffic_limit => s_wbm_2_traffic_ctrl_limit,
clk => clk,
rst_n => rst_n);
PROCESS (clk, rst_n)
BEGIN
IF (rst_n = '0') THEN
s_wbm_1_bg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (s_wbm_1_bg_q = '0') THEN
s_wbm_1_bg_q <= s_wbm_1_bg;
ELSIF (s_ack = '1') THEN
s_wbm_1_bg_q <= '0';
ELSIF (i_wbm_1_o_cyc = '0') THEN
s_wbm_1_bg_q <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst_n)
BEGIN
IF (rst_n = '0') THEN
s_wbm_2_bg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (s_wbm_2_bg_q = '0') THEN
s_wbm_2_bg_q <= s_wbm_2_bg;
ELSIF (s_ack = '1') THEN
s_wbm_2_bg_q <= '0';
ELSIF (i_wbm_2_o_cyc = '0') THEN
s_wbm_2_bg_q <= '0';
END IF;
END IF;
END PROCESS;
s_idle <= '1' WHEN (s_wbm_1_bg_q = '0' AND s_wbm_2_bg_q = '0') ELSE '0';
s_wbm_1_bg_1 <= '1' WHEN (s_idle = '1' AND i_wbm_1_o_cyc = '1' AND s_wbm_1_traffic_ctrl_limit = '0') ELSE '0';
s_wbm_1_bb_1 <= '1' WHEN (s_wbm_1_bg_1 = '1') ELSE '0';
s_wbm_2_bg_1 <= '1' WHEN (s_idle = '1' AND i_wbm_2_o_cyc = '1' AND s_wbm_2_traffic_ctrl_limit = '0' AND s_wbm_1_bb_1 = '0') ELSE '0';
s_wbm_2_bb_1 <= '1' WHEN (s_wbm_2_bg_1 = '1' OR s_wbm_1_bb_1 = '1') ELSE '0';
s_wbm_1_bg_2 <= '1' WHEN (s_idle = '1' AND s_wbm_2_bb_1 = '0' AND i_wbm_1_o_cyc = '1') ELSE '0';
s_wbm_1_bb_2 <= '1' WHEN (s_wbm_1_bg_2 = '1' OR s_wbm_2_bb_1 = '1') ELSE '0';
s_wbm_2_bg_2 <= '1' WHEN (s_idle = '1' AND s_wbm_1_bb_2 = '0' AND i_wbm_2_o_cyc = '1') ELSE '0';
s_wbm_2_bb_2 <= '1' WHEN (s_wbm_2_bg_2 = '1' OR s_wbm_1_bb_2 = '1') ELSE '0';
s_wbm_1_bg <= s_wbm_1_bg_q OR s_wbm_1_bg_1 OR s_wbm_1_bg_2;
s_wbm_2_bg <= s_wbm_2_bg_q OR s_wbm_2_bg_1 OR s_wbm_2_bg_2;
s_ce <= i_wbm_1_o_cyc OR i_wbm_2_o_cyc WHEN (s_idle = '1') ELSE '0';
END BLOCK arbiter_sharedbus;
decoder : BLOCK
SIGNAL s_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
s_addr <= (i_wbm_1_o_addr AND s_wbm_1_bg) OR (i_wbm_2_o_addr AND s_wbm_2_bg);
s_wbs_1_ss <=
'1' WHEN (s_addr(31 DOWNTO 8) = "000000000000000000000000") ELSE '0';
s_wbs_2_ss <=
'1' WHEN (s_addr(31 DOWNTO 4) = "0000000000000000000000100000") ELSE '0';
s_wbs_3_ss <=
'1' WHEN (s_addr(31 DOWNTO 12) = "00000000000100000000") ELSE '0';
o_wbs_1_i_addr <= s_addr(7 DOWNTO 0);
o_wbs_2_i_addr <= s_addr(3 DOWNTO 0);
o_wbs_3_i_addr <= s_addr(19 DOWNTO 0);
END BLOCK decoder;
mux : BLOCK
SIGNAL s_cyc : STD_LOGIC;
SIGNAL s_stb : STD_LOGIC;
SIGNAL s_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL s_we : STD_LOGIC;
SIGNAL s_data_m2s : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_data_s2m : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_ack : STD_LOGIC;
SIGNAL s_rty : STD_LOGIC;
SIGNAL s_err : STD_LOGIC;
BEGIN
-- cyc
s_cyc <= (i_wbm_1_o_cyc AND s_wbm_1_bg) OR (i_wbm_2_o_cyc AND s_wbm_2_bg);
o_wbs_1_i_cyc <= s_cyc AND s_wbs_1_ss;
o_wbs_2_i_cyc <= s_cyc AND s_wbs_2_ss;
o_wbs_3_i_cyc <= s_cyc AND s_wbs_3_ss;
-- stb
s_stb <= (i_wbm_1_o_stb AND s_wbm_1_bg) OR (i_wbm_2_o_stb AND s_wbm_2_bg);
o_wbs_1_i_stb <= s_stb AND s_wbs_1_ss;
o_wbs_2_i_stb <= s_stb AND s_wbs_2_ss;
o_wbs_3_i_stb <= s_stb AND s_wbs_3_ss;
-- sel
s_sel <= (i_wbm_1_o_sel AND s_wbm_1_bg) OR (i_wbm_2_o_sel AND s_wbm_2_bg);
o_wbs_1_i_sel <= s_sel;
o_wbs_2_i_sel <= s_sel;
o_wbs_3_i_sel <= s_sel;
-- we
s_we <= (i_wbm_1_o_we AND s_wbm_1_bg) OR (i_wbm_2_o_we AND s_wbm_2_bg);
o_wbs_1_i_we <= s_we;
o_wbs_3_i_we <= s_we;
-- data m2s
s_data_m2s <= (i_wbm_1_o_data AND s_wbm_1_bg) OR (i_wbm_2_o_data AND s_wbm_2_bg);
o_wbs_1_i_data <= s_data_m2s;
o_wbs_3_i_data <= s_data_m2s;
-- data s2m
s_data_s2m <= (i_wbs_1_o_data AND s_wbs_1_ss) OR (i_wbs_2_o_data AND s_wbs_2_ss) OR (i_wbs_3_o_data AND s_wbs_3_ss);
o_wbm_1_i_data <= s_data_s2m;
o_wbm_2_i_data <= s_data_s2m;
-- ack
s_ack <= i_wbs_1_o_ack OR i_wbs_2_o_ack OR i_wbs_3_o_ack;
o_wbm_1_i_ack <= s_ack AND s_wbm_1_bg;
o_wbm_2_i_ack <= s_ack AND s_wbm_2_bg;
-- rty
s_rty <= i_wbs_1_o_rty OR i_wbs_2_o_rty OR i_wbs_3_o_rty;
o_wbm_1_i_rty <= s_rty AND s_wbm_1_bg;
o_wbm_2_i_rty <= s_rty AND s_wbm_2_bg;
-- err
s_err <= i_wbs_1_o_err OR i_wbs_2_o_err OR i_wbs_3_o_err;
o_wbm_1_i_err <= s_err AND s_wbm_1_bg;
o_wbm_2_i_err <= s_err AND s_wbm_2_bg;
END BLOCK mux;
END ARCHITECTURE rtl;
|
mit
|
chrismasters/fpga-space-invaders
|
project/ipcore_dir/vram.vhd
|
1
|
6061
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 13,
c_addrb_width => 13,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "00",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 7168,
c_read_depth_b => 7168,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 7168,
c_write_depth_b => 7168,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
|
mit
|
chrismasters/fpga-notes
|
sdramcontroller/ipcore_dir/clks/example_design/clks_exdes.vhd
|
1
|
6458
|
-- file: clks_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clks_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1)
);
end clks_exdes;
architecture xilinx of clks_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component clks is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clks
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2));
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
|
mit
|
chrismasters/fpga-space-invaders
|
project/ipcore_dir/testmem/example_design/testmem_exdes.vhd
|
1
|
4601
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: testmem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY testmem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END testmem_exdes;
ARCHITECTURE xilinx OF testmem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT testmem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : testmem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/SinDPStratixVf400_safe_path.vhd
|
10
|
427
|
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SinDPStratixVf400_safe_path;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_castytod.vhd
|
10
|
18709
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_tanlut1.vhd
|
10
|
94202
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TANLUT1.VHD ***
--*** ***
--*** Function: Tangent Look Up Table ***
--*** (Generated by MATLAB Utility) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_tanlut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_tanlut1;
ARCHITECTURE rtl OF fp_tanlut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
WHEN "000000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131072,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174764,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
WHEN "000000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131074,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174780,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5);
WHEN "000000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196617,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5);
WHEN "000000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131082,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175036,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163860,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196644,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2074,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229433,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131114,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179133,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147516,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(204485,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163923,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(100723,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180334,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261788,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196752,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33207,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213175,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71403,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229604,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246559,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246041,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166927,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244778,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139469,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18368,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147699,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155934,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110829,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164174,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39099,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172418,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240249,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180668,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188924,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157429,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197186,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(8449,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205453,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140199,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213727,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96362,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222007,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(207256,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230295,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16983,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238589,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118443,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246891,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(56191,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255200,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131758,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251787,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135921,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182851,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140088,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170994,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144259,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148435,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196795,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152616,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(42877,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156801,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87190,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160991,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103258,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165186,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126910,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169386,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194144,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173592,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78984,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79918,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182019,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233473,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52073,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190470,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96910,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194704,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142940,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198944,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227466,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203191,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125851,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207444,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137961,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211704,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39590,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215970,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131044,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220243,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188568,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(250786,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228811,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94417,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20713,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69033,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241718,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16848,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246035,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166180,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250361,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32888,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254694,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181681,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128971,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131693,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88946,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133872,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184862,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110880,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138244,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150087,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140437,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61438,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142634,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128336,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144836,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110058,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147043,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(28193,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166641,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151471,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(23046,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153692,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(143802,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155919,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(26909,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158150,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219127,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160387,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218828,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162630,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48862,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164877,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256563,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167131,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169390,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63145,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171654,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233418,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173925,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89145,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176201,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178694,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178484,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2082,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180772,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108121,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183066,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259423,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185367,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218831,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187675,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11570,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189988,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187394,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192308,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247729,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194635,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218538,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196969,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126042,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199309,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258866,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201657,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119470,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204011,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259160,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180942,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208742,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174537,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211119,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213502,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226767,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215894,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79866,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218293,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118006,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220700,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108111,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223115,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79560,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225538,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62056,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227969,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85630,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180644,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232856,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115658,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235312,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183865,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237777,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154523,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240251,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(59395,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242733,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192751,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(245225,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62806,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(247725,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226729,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250235,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(193502,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252754,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258933,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255283,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194946,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257822,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36018,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260370,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79189,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131464,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132748,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63557,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134037,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101912,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135331,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182207,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136631,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60853,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137936,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18783,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139246,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(75024,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140561,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248849,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141883,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(35488,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143209,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241146,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144542,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99421,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145880,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154894,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147224,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(165983,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148574,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153522,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149930,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138624,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151292,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142687,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152660,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154035,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32592,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155415,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(224845,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(313,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158196,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168333,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159596,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227841,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161003,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162417,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115847,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163837,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(254593,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165265,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118901,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166699,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257978,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168141,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169590,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(151210,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171046,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219176,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172510,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140977,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173981,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205552,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175460,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177949,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176947,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85768,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178441,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219166,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179944,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(82294,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181454,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(228309,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182973,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(162236,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184500,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175979,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37616,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187580,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39982,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214250,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190694,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(67791,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192264,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157055,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193843,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252568,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195432,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125382,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197030,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71365,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198637,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(124791,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(58341,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201880,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169556,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203516,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(232268,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205163,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20904,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206819,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96928,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208485,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235993,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210162,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211850,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71183,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213548,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108271,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215257,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103923,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216977,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99249,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218708,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(136066,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220450,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222204,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242940,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223970,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225747,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249580,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227537,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(98477,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229338,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(255571,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231152,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(243824,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232979,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111333,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(234818,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169210,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236670,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205169,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238536,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7833,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240414,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153192,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242306,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169612,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244212,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110728,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248065,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248754,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250014,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251976,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230368,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253954,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111078,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255946,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(260182,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257954,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214570,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259978,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36603,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(262017,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52004,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31728,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133071,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199603,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134115,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170119,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135167,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(239798,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136228,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181565,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137298,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31195,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138376,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87334,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139463,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125082,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140559,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182447,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141665,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36078,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142779,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249858,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143904,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77779,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(146182,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52708,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147336,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(22748,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148500,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39467,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149674,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(147762,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150859,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131351,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152055,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37096,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153261,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175023,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154479,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69779,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155708,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33524,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156948,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158200,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111488,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159464,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69279,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160740,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45413,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162028,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95789,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163329,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(15442,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164642,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125012,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165968,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222206,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167308,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(106129,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168661,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101608,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170028,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161129,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95974,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174212,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(146219,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175636,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(120264,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177075,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90370,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178529,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130571,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179999,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54581,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181484,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182986,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(129087,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184504,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178815,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186039,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173083,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187591,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197786,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78873,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190748,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168858,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192354,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193978,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38109,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195621,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10173,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197283,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52606,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198965,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6187,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200666,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202389,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(72398,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142943,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205897,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(40664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207683,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145442,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(209492,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54008,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211323,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(152917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213178,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45809,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126393,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216959,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5720,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218886,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85177,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220838,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(245917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222817,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111146,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224822,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94854,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226854,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91265,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228913,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261427,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231001,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246970,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233118,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218857,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235265,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91152,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237442,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45510,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(239650,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7099,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241889,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169116,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(206583,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246467,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63025,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248806,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(212871,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251181,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88861,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253591,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179473,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194218,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(112522,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(261046,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184058,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131804,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202396,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(127604,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134429,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5700,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135772,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241668,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137138,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196914,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138527,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(24498,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139938,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145076,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(198575,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142833,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(93021,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144318,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(4818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145828,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116886,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147365,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94683,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148929,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(135102,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150521,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180373,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180573,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153793,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94005,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155474,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149742,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(157187,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61623,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158932,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77284,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160710,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192200,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150199,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164371,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230433,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166256,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199372,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168179,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(97853,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170140,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241724,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173961,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174185,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238269,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176272,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6999,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178402,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116996,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180578,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173338,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182802,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61011,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185074,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(208074,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187398,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(13879,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189773,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(209544,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192203,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237754,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194690,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89118,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197235,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(41457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199840,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137068,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202508,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184378,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(21881,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208043,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(44347,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210914,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156319,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213859,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36498,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216879,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188732,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(219979,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(109619,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126346,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226429,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89021,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229786,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(160435,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233237,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236784,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244509,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240434,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83006,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244189,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(215105,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(68494,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196984,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(189406,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249093,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132369,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(76283,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134621,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153043,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136947,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90777,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139350,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(80594,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141834,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118724,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144404,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(12410,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147063,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172855,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149818,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(49588,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152672,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235640,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155633,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117182,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158705,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242792,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161896,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237423,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165213,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125600,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168663,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83253,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191313,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175996,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191297,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179899,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(29637,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183972,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142533,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188228,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(171026,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192680,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38953,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197340,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248662,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202226,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(84469,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207353,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16170,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(212739,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177173,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218406,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161382,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224376,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140334,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230674,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156722,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237328,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218000,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244370,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(144312,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251834,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222783,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259761,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(51093,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134097,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16112,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138592,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11144,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143394,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60483,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148536,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(104003,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37731,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159996,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191255,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173350,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(113148,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180890,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(176944,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189110,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(163200,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(211327,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207994,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247747,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218914,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231037,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174172,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244573,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197553,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259786,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(53842,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138503,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202780,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148332,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62994,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159656,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230897,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172847,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240508,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183509,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207041,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119228,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229756,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71260,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258060,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153597,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147154,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32322,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171195,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78299,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204618,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(105365,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254248,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(141622,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167825,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(19278,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5);
WHEN "110010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246850,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149873,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5);
WHEN "110010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233251,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(216105,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(15,5);
WHEN "110010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132278,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191927,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(19,5);
WHEN others =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_cntsgn36.vhd
|
10
|
6463
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN36.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn36;
ARCHITECTURE rtl OF hcc_cntsgn36 IS
type positiontype IS ARRAY (9 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(35) OR frac(34) OR frac(33) OR frac(32);
possec(2) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(3) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(4) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(5) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(6) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(7) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(8) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(9) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(35) AND frac(34) AND frac(33) AND frac(32);
negsec(2) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(3) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(4) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(5) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(6) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(7) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(8) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(9) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 9 GENERATE
sec(k) <= (possec(k) AND NOT(frac(36))) OR (negsec(k) AND frac(36));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(9) <= sec(9) AND NOT(sec(8)) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND
NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(35 DOWNTO 32),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(31 DOWNTO 28),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(27 DOWNTO 24),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(23 DOWNTO 20),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(19 DOWNTO 16),
position=>position(5)(6 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(15 DOWNTO 12),
position=>position(6)(6 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(11 DOWNTO 8),
position=>position(7)(6 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>6)
PORT MAP (signbit=>frac(36),inbus=>frac(7 DOWNTO 4),
position=>position(8)(6 DOWNTO 1));
pnin: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>6)
PORT MAP (signbit=>frac(36),inbus=>lastfrac,
position=>position(9)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(36);
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8)) OR
(position(9)(k) AND sel(9));
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fpc_library_package_cmd.vhd
|
10
|
48869
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fpc_library_package_cmd.vhd
|
10
|
48869
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FPC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** ADSPB instantiated functions. Provides ***
--*** interface between ADSPB tool's types ***
--*** and hcc library elements ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE fpc_library_package_cmd IS
constant m_fpOutputScale : integer := 0; -- -ni: Fully pre-normalize single precision multipliers
constant m_fpRoundConvert : integer := 0; -- -rc: all conversions between signed and unsigned numbers
constant m_fpDoubleSpeed : integer := 1; -- -ds: Pipeline longer additions
constant m_fpOutputPipe : integer := 1; -- -op: Optimize away registers on simple internal output nodes
constant m_fpNormalisationSpeed : integer := 3; -- -ns: Normalization block performance (1,2 or 3)
constant m_SingleMantissaWidth : integer := 32; -- -mm: 0=>32-bit, 1=>36-bit
constant m_fpShiftSpeed : integer := 1; -- -ps: Remove pipelines out of large alignments
function deviceFamilyA5( f : string ) return integer;
function deviceFamily( f : string ) return integer;
function deviceFamilyS3( f : string ) return integer;
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN;
--***************************************************
--*** Single Precision ***
--***************************************************
COMPONENT fp_mult_sNorm_2_sInternal
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sNorm
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sNorm_2_sIEEE
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_sIEEE_2_sInternalSM_v31
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternal_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_sInternalSM_2_sInternal_v31
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sInternal_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sNorm_2_fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
--***************************************************
--*** Double Precision ***
--***************************************************
COMPONENT fp_mult_dNorm_2_dInternal
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_mult_dNorm_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_div_dNorm_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_addsub_dInternal_2_dInternal
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_exp_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_log_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recip_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_recipSqRt_dIEEE_2_dIEEE
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_dInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dNorm
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sNorm
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sInternal
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_sIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dIEEE
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_sIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dIEEE_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_Fixed
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_sIEEE_2_sIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT cast_dInternal_2_sInternal
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_abs_dIEEE_2_dIEEE
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END COMPONENT;
END fpc_library_package_cmd;
PACKAGE BODY fpc_library_package_cmd is
function sIEEE_2_real (arg : STD_LOGIC_VECTOR(31 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8;
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(31) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (UNSIGNED(arg(22 DOWNTO 0)))) / (2.0 ** 23);
expon := to_integer (UNSIGNED(arg (30 downto 23)));
exp := expon - expon_base;
if exp > expon_base then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac);
end if;
return sign;
end sIEEE_2_real;
function sNorm_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sNorm_2_real;
function sInternal_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(41 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternal_2_real;
function sInternalSM_2_real (arg : STD_LOGIC_VECTOR(44 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 8; -- the binary point is at 8 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (UNSIGNED(arg(42 DOWNTO 10)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (9 downto 0)));
exp := expon - expon_base;
sign := (2.0 ** exp) * frac;
return sign;
end sInternalSM_2_real;
function dIEEE_2_real (arg : STD_LOGIC_VECTOR(63 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11;
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
if arg(63) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
frac := REAL(to_integer (SIGNED('0' & arg(51 DOWNTO 21)))) / (2.0 ** 31); -- ignore low bits to fit within VHDL types
fraclo := REAL(to_integer (SIGNED('0' & arg(20 DOWNTO 0)))) / (2.0 ** 52);
expon := to_integer (SIGNED('0' & arg (62 downto 52)));
exp := expon - expon_base;
-- Fatal error (vsim-3421) if outside range -1e+308 +1e+308 which can still happen if exp = 1023
if exp >= 1023 then
sign := sign * 9.999e+307;
elsif expon = 0 then
sign := 0.0;
-- ignore denormalized mantissa
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end dIEEE_2_real;
function dNorm_2_real (arg : STD_LOGIC_VECTOR(69 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(66 DOWNTO 35)))) / (2.0 ** 30); -- SS.FFFFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
if exp >= 1024 then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dNorm_2_real;
function dInternal_2_real (arg : STD_LOGIC_VECTOR(79 DOWNTO 0)) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable exponent_width : INTEGER := 11; -- the binary point is at 10 even though there are 2 extra bits for overflow
variable frac : REAL := 0.0; -- Fraction
variable expon : INTEGER;
variable sign_bit : STD_LOGIC;
begin
if is_x(arg) then
return 0.0;
end if;
expon_base := 2**(exponent_width-1) -1;
frac := REAL(to_integer (SIGNED(arg(76 DOWNTO 45)))) / (2.0 ** 26); -- SSSSSS.FFF...FF
expon := to_integer (UNSIGNED(arg (12 downto 0)));
exp := expon - expon_base;
sign_bit := arg(76);
if exp >= 1024 then
-- perhaps
-- or (arg(74) /= sign_bit and exp >= 1023) or (arg(74) /= sign_bit and arg(75) /= sign_bit and exp >= 1022) then
sign := 0.0;
else
sign := (2.0 ** exp) * frac;
end if;
return sign;
end dInternal_2_real;
function vIEEE_2_real (arg : STD_LOGIC_VECTOR; expWidth : INTEGER; fracWidth : INTEGER) return REAL is
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable exponBase : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable fraclo : REAL := 0.0; -- Fraction (low order bits)
variable expon : INTEGER;
begin
if is_x(arg) then
return 0.0;
end if;
exponBase := 2**(expWidth-1) -1;
if arg(arg'high) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
if fracWidth > 31 then
frac := REAL(to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))))) / (2.0 ** 31);
fraclo := REAL(to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)))) / (2.0 ** fracWidth);
else
frac := REAL(to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)))) / (2.0 ** fracWidth);
fraclo := 0.0;
end if;
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
exp := expon - exponBase;
if exp > exponBase or exp >= 1023 then
sign := sign * 9.999e+307; -- NaN or Inf
elsif expon = 0 then
sign := 0.0; -- denormalized rounded to zero
else
sign := sign * (2.0 ** exp) * (1.0 + frac + fraclo);
end if;
return sign;
end vIEEE_2_real;
function sIEEEisNan (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(30 downto 23) = "11111111" and a(22 downto 0) /= "00000000000000000000000";
end sIEEEisNan;
function sIEEEisInf (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(30 downto 0) = "1111111100000000000000000000000" then
--if a(30 downto 23) = "11111111" then
return TRUE;
else
return FALSE;
end if;
end sIEEEisInf;
function sIEEEisNegative (a : STD_LOGIC_VECTOR(31 DOWNTO 0)) return BOOLEAN is
begin
return a(31) = '1';
end sIEEEisNegative;
function sIEEEisEqual (a, b : STD_LOGIC_VECTOR(31 DOWNTO 0); threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if sIEEEisNan(a) and sIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if sIEEEisInf(a) and sIEEEisInf(b) then
return sIEEEisNegative(a) = sIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if sIEEEisInf(a) or sIEEEisInf(b) then
return FALSE;
end if;
a_real := sIEEE_2_real(a);
b_real := sIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end sIEEEisEqual;
function dIEEEisNan (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(62 downto 52) = "11111111111" and a(51 downto 0) /= "0000000000000000000000000000000000000000000000000000";
end dIEEEisNan;
function dIEEEisInf (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
-- ignore sign bit since this returns true for -inf and +inf
if a(62 downto 0) = "111111111110000000000000000000000000000000000000000000000000000" then
--if a(62 downto 52) = "11111111111" then
return TRUE;
else
return FALSE;
end if;
end dIEEEisInf;
function dIEEEisNegative (a : STD_LOGIC_VECTOR(63 DOWNTO 0)) return BOOLEAN is
begin
return a(63) = '1';
end dIEEEisNegative;
function dIEEEisEqual (a, b : STD_LOGIC_VECTOR(63 DOWNTO 0); threshold : REAL := 0.000001; zero_threshold : REAL := 0.0000000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if dIEEEisNan(a) and dIEEEisNan(b) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if dIEEEisInf(a) and dIEEEisInf(b) then
return dIEEEisNegative(a) = dIEEEisNegative(b);
end if;
-- if only one is infinite then mismatch
if dIEEEisInf(a) or dIEEEisInf(b) then
return FALSE;
end if;
a_real := dIEEE_2_real(a);
b_real := dIEEE_2_real(b);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end dIEEEisEqual;
function vIEEEisNan (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return TRUE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac /= 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac /= 0);
end vIEEEisNan;
function vIEEEisInf (arg : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable expon : INTEGER;
variable expmax : INTEGER;
variable frac : INTEGER;
begin
-- ignore sign bit since this returns true for -inf and +inf
expon := to_integer (UNSIGNED(arg ((arg'high - 1) downto fracWidth)));
expmax := 2**expWidth - 1;
if (expon /= expmax) then
return FALSE;
end if;
if fracWidth > 31 then
frac := to_integer(UNSIGNED(arg((fracWidth - 1) DOWNTO (fracWidth - 31))));
if (frac /= 0) then
return FALSE;
end if;
frac := to_integer(UNSIGNED(arg((fracWidth - 32) DOWNTO 0)));
return (frac = 0);
end if;
frac := to_integer (UNSIGNED(arg((fracWidth - 1) DOWNTO 0)));
return (frac = 0);
end vIEEEisInf;
function vIEEEisNegative (arg : STD_LOGIC_VECTOR; we, wf : INTEGER) return BOOLEAN is
begin
return arg(arg'high) = '1';
end vIEEEisNegative;
function vIEEEisEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER; threshold : REAL := 0.001; zero_threshold : REAL := 0.0000001) return BOOLEAN is
variable a_real : REAL;
variable b_real : REAL;
variable max_real : REAL;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
a_real := vIEEE_2_real(a, expWidth, fracWidth);
b_real := vIEEE_2_real(b, expWidth, fracWidth);
-- find the max of the two numbers
if abs(a_real) > abs(b_real) then
max_real := abs(a_real);
else
max_real := abs(b_real);
end if;
-- if the max number is less than the zero threshold (then so is the other) and so we declare them to be "equal"
if max_real < zero_threshold then
return TRUE;
end if;
-- now we're comparing two numbers that aren't too close to zero so we can compare them by scaling the threshold by
-- the largest of the two
if abs(a_real - b_real) > threshold * max_real then
return FALSE; -- significant difference
else
return TRUE; -- match
end if;
end vIEEEisEqual;
function vIEEEisExactEqual (a, b : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
begin
-- if either contains XUZ etc then mismatch
if is_x(a) or is_x(b) then
return FALSE;
end if;
-- treat all NaNs as equal
if vIEEEisNan(a, expWidth, fracWidth) and vIEEEisNan(b, expWidth, fracWidth) then
return TRUE;
end if;
-- if they're both infinite then they match assuming the sign is right
if vIEEEisInf(a, expWidth, fracWidth) and vIEEEisInf(b, expWidth, fracWidth) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
-- if only one is infinite then mismatch
if vIEEEisInf(a, expWidth, fracWidth) or vIEEEisInf(b, expWidth, fracWidth) then
return FALSE;
end if;
if (vIEEEisSubnormal(a, expWidth, fracWidth) or vIEEEisZero(a, expWidth, fracWidth)) and
(vIEEEisSubnormal(b, expWidth, fracWidth) or vIEEEisZero(b, expWidth, fracWidth)) then
return vIEEEisNegative(a, expWidth, fracWidth) = vIEEEisNegative(b, expWidth, fracWidth);
end if;
if (a = b) then
return TRUE;
end if;
return FALSE;
end vIEEEisExactEqual;
function vIEEEisSubnormal (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA /= 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisSubnormal;
function vIEEEisZero (a : STD_LOGIC_VECTOR; expWidth, fracWidth : INTEGER) return BOOLEAN is
variable fracA: integer;
variable expA : integer;
begin
-- if either contains XUZ etc then mismatch
if is_x(a) then
return FALSE;
end if;
fracA := to_integer (UNSIGNED(a(fracWidth-1 downto 0)));
expA := to_integer (UNSIGNED(a(expWidth+fracWidth-1 downto fracWidth)));
if (expA = 0 and fracA = 0) then
return TRUE;
end if;
return FALSE;
end vIEEEisZero;
FUNCTION deviceFamilyA5 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" THEN
RETURN 2;
ELSIF f = "Arria V" THEN
RETURN 3;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamilyA5;
FUNCTION deviceFamily ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
ELSIF f = "Stratix V" or f = "Arria V" THEN
RETURN 2;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
END FUNCTION deviceFamily;
FUNCTION deviceFamilyS3 ( f : string )
RETURN integer IS
BEGIN
ASSERT f = "Stratix II" or f = "Stratix III" or f = "Stratix IV" or f = "Stratix V" or f = "Arria V" REPORT "fpc library : unknown device family" SEVERITY failure;
IF f = "Stratix II" THEN
RETURN 0;
END IF;
RETURN 1; -- "Stratix III" and "Stratix IV"
-- "Stratix V" also though many FPC components have not yet been optimized for this family
END FUNCTION deviceFamilyS3;
END fpc_library_package_cmd;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_range_table1.vhd
|
10
|
66434
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_rsft78.vhd
|
10
|
3744
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT78.VHD ***
--*** ***
--*** Function: 78 bit Arithmetic Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft78 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
END fp_rsft78;
ARCHITECTURE rtl of fp_rsft78 IS
signal levzip, levone, levtwo : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levthr, levfor, levfiv : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levsix : STD_LOGIC_VECTOR (78 DOWNTO 1);
BEGIN
levzip <= inbus;
gaa: FOR k IN 1 TO 77 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(1))) OR (levzip(k+1) AND shift(1));
END GENERATE;
levone(78) <= levzip(78) AND NOT(shift(1));
gba: FOR k IN 1 TO 76 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(2))) OR (levone(k+2) AND shift(2));
END GENERATE;
levtwo(77) <= levone(77) AND NOT(shift(2));
levtwo(78) <= levone(78) AND NOT(shift(2));
gca: FOR k IN 1 TO 74 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(3))) OR (levtwo(k+4) AND shift(3));
END GENERATE;
gcb: FOR k IN 75 TO 78 GENERATE
levthr(k) <= levtwo(k) AND NOT(shift(3));
END GENERATE;
gda: FOR k IN 1 TO 70 GENERATE
levfor(k) <= (levthr(k) AND NOT(shift(4))) OR (levthr(k+8) AND shift(4));
END GENERATE;
gdb: FOR k IN 71 TO 78 GENERATE
levfor(k) <= levthr(k) AND NOT(shift(4));
END GENERATE;
gea: FOR k IN 1 TO 62 GENERATE
levfiv(k) <= (levfor(k) AND NOT(shift(5))) OR (levfor(k+16) AND shift(5));
END GENERATE;
geb: FOR k IN 63 TO 78 GENERATE
levfiv(k) <= levfor(k) AND NOT(shift(5));
END GENERATE;
gfa: FOR k IN 1 TO 46 GENERATE
levsix(k) <= (levfiv(k) AND NOT(shift(6))) OR (levfiv(k+32) AND shift(6));
END GENERATE;
gfb: FOR k IN 47 TO 78 GENERATE
levsix(k) <= levfiv(k) AND NOT(shift(6));
END GENERATE;
outbus <= levsix;
END;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_rsft78.vhd
|
10
|
3744
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT78.VHD ***
--*** ***
--*** Function: 78 bit Arithmetic Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft78 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
END fp_rsft78;
ARCHITECTURE rtl of fp_rsft78 IS
signal levzip, levone, levtwo : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levthr, levfor, levfiv : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levsix : STD_LOGIC_VECTOR (78 DOWNTO 1);
BEGIN
levzip <= inbus;
gaa: FOR k IN 1 TO 77 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(1))) OR (levzip(k+1) AND shift(1));
END GENERATE;
levone(78) <= levzip(78) AND NOT(shift(1));
gba: FOR k IN 1 TO 76 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(2))) OR (levone(k+2) AND shift(2));
END GENERATE;
levtwo(77) <= levone(77) AND NOT(shift(2));
levtwo(78) <= levone(78) AND NOT(shift(2));
gca: FOR k IN 1 TO 74 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(3))) OR (levtwo(k+4) AND shift(3));
END GENERATE;
gcb: FOR k IN 75 TO 78 GENERATE
levthr(k) <= levtwo(k) AND NOT(shift(3));
END GENERATE;
gda: FOR k IN 1 TO 70 GENERATE
levfor(k) <= (levthr(k) AND NOT(shift(4))) OR (levthr(k+8) AND shift(4));
END GENERATE;
gdb: FOR k IN 71 TO 78 GENERATE
levfor(k) <= levthr(k) AND NOT(shift(4));
END GENERATE;
gea: FOR k IN 1 TO 62 GENERATE
levfiv(k) <= (levfor(k) AND NOT(shift(5))) OR (levfor(k+16) AND shift(5));
END GENERATE;
geb: FOR k IN 63 TO 78 GENERATE
levfiv(k) <= levfor(k) AND NOT(shift(5));
END GENERATE;
gfa: FOR k IN 1 TO 46 GENERATE
levsix(k) <= (levfiv(k) AND NOT(shift(6))) OR (levfiv(k+32) AND shift(6));
END GENERATE;
gfb: FOR k IN 47 TO 78 GENERATE
levsix(k) <= levfiv(k) AND NOT(shift(6));
END GENERATE;
outbus <= levsix;
END;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_alufp2x.vhd
|
10
|
10713
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_neg2x.vhd
|
10
|
2843
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NEG2X.VHD ***
--*** ***
--*** Function: Negation (for unary -ve) ***
--*** ***
--*** 13/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_neg2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_neg2x;
ARCHITECTURE rtl OF hcc_neg2x IS
signal aaff : STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC;
BEGIN
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64+13*xoutput+3*funcoutput LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
goa: IF (ieeeoutput = 1) GENERATE
cc(64) <= NOT(aaff(64));
cc(63 DOWNTO 1) <= aaff(63 DOWNTO 1);
ccsat <= '0';
cczip <= '0';
END GENERATE;
gob: IF (xoutput = 1) GENERATE
gxa: FOR k IN 14 TO 77 GENERATE
cc(k) <= NOT(aaff(k));
END GENERATE;
cc(13 DOWNTO 1) <= aaff(13 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
goc: IF (funcoutput = 1) GENERATE
cc(67) <= NOT(aaff(67));
cc(66 DOWNTO 1) <= aaff(66 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/hcc_rsftcomb32.vhd
|
10
|
3786
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftcomb32;
ARCHITECTURE rtl OF hcc_rsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k+16) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(32) AND shift(5));
END GENERATE;
levthr(32) <= levtwo(32);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_rsftcomb32.vhd
|
10
|
3786
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB32.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_rsftcomb32;
ARCHITECTURE rtl OF hcc_rsftcomb32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 29 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(30) <= (levzip(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(31) AND NOT(shift(2)) AND shift(1)) OR
(levzip(32) AND shift(2));
levone(31) <= (levzip(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(32) AND ((shift(2)) OR shift(1)));
levone(32) <= levzip(32);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 20 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 21 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(32) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(32) AND shift(4));
END GENERATE;
gbd: FOR k IN 29 TO 31 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(32) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(32) <= levone(32);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k+16) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 31 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(32) AND shift(5));
END GENERATE;
levthr(32) <= levtwo(32);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/CosPiDPStratixVf400.vhd
|
10
|
580991
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Debug Version 12.0
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from CosPiDPStratixVf400
-- VHDL created on Wed Sep 05 17:56:14 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
USE work.CosPiDPStratixVf400_safe_path.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240
entity CosPiDPStratixVf400 is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(63 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic;
bus_clk : in std_logic;
h_areset : in std_logic
);
end;
architecture normal of CosPiDPStratixVf400 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal biasMwShift_uid13_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal biasMwShiftMO_uid14_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cst01pWShift_uid15_fpCosPiTest_q : std_logic_vector (27 downto 0);
signal cstZwSwF_uid16_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal cstAllZWE_uid22_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_a : std_logic_vector(81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector(81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_o : std_logic_vector (81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_q : std_logic_vector (81 downto 0);
signal rangeReducedFxPX_uid53_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid53_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_a : std_logic_vector(80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_b : std_logic_vector(80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_o : std_logic_vector (80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal xIsInt_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_e : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid88_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal oneFracRPostExc2_uid89_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal expRPostExc1_uid93_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid93_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal mO_uid147_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal memoryC3_uid228_sinPiZTableGenerator_q : std_logic_vector(34 downto 0);
signal memoryC4_uid229_sinPiZTableGenerator_q : std_logic_vector(25 downto 0);
signal memoryC5_uid230_sinPiZTableGenerator_q : std_logic_vector(16 downto 0);
signal rndBit_uid245_sinPiZPolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid257_sinPiZPolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_q : std_logic_vector (33 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_a : std_logic_vector (25 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_b : std_logic_vector (27 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_zero_36_q : std_logic_vector (26 downto 0);
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0);
signal reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q : std_logic_vector (80 downto 0);
signal reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q : std_logic_vector (80 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q : std_logic_vector (79 downto 0);
signal reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q : std_logic_vector (80 downto 0);
signal reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0);
signal reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0);
signal reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0);
signal reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0);
signal reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0);
signal reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q : std_logic_vector (26 downto 0);
signal reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (6 downto 0);
signal reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q : std_logic_vector (79 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q : std_logic_vector (78 downto 0);
signal ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q : std_logic_vector (31 downto 0);
signal ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q : std_logic_vector (15 downto 0);
signal ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q : std_logic_vector (15 downto 0);
signal ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0);
signal ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0);
signal ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0);
signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic;
signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic;
signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0);
signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic;
signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ir : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal pad_o_uid17_uid49_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal pad_half_uid18_uid54_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal rndExpUpdate_uid74_uid75_fpCosPiTest_q : std_logic_vector (53 downto 0);
signal expFracComp_uid76_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal expFracComp_uid76_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal expFracComp_uid76_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal expFracComp_uid76_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRPostExc_uid90_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid90_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid97_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid97_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal memoryC0_uid225_sinPiZTableGenerator_q : std_logic_vector(57 downto 0);
signal memoryC1_uid226_sinPiZTableGenerator_q : std_logic_vector(49 downto 0);
signal memoryC2_uid227_sinPiZTableGenerator_q : std_logic_vector(42 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_q : std_logic_vector (35 downto 0);
signal ts3_uid247_sinPiZPolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid247_sinPiZPolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid247_sinPiZPolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid247_sinPiZPolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid253_sinPiZPolyEval_a : std_logic_vector(52 downto 0);
signal ts4_uid253_sinPiZPolyEval_b : std_logic_vector(52 downto 0);
signal ts4_uid253_sinPiZPolyEval_o : std_logic_vector (52 downto 0);
signal ts4_uid253_sinPiZPolyEval_q : std_logic_vector (52 downto 0);
signal ts5_uid259_sinPiZPolyEval_a : std_logic_vector(61 downto 0);
signal ts5_uid259_sinPiZPolyEval_b : std_logic_vector(61 downto 0);
signal ts5_uid259_sinPiZPolyEval_o : std_logic_vector (61 downto 0);
signal ts5_uid259_sinPiZPolyEval_q : std_logic_vector (61 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal cstHalfwSwFP1_uid19_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXIsMax_uid26_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid26_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid26_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid37_fpCosPiTest_a : std_logic_vector(13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_b : std_logic_vector(13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_o : std_logic_vector (13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid37_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_a : std_logic_vector(13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_b : std_logic_vector(13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_o : std_logic_vector (13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_a : std_logic_vector(79 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_b : std_logic_vector(79 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid24_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid24_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid24_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid51_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal oMFxpXFrac_uid51_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal z_uid56_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal z_uid56_fpCosPiTest_b : std_logic_vector (78 downto 0);
signal or_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid246_sinPiZPolyEval_q : std_logic_vector (44 downto 0);
signal cIncludingRoundingBit_uid252_sinPiZPolyEval_q : std_logic_vector (51 downto 0);
signal cIncludingRoundingBit_uid258_sinPiZPolyEval_q : std_logic_vector (60 downto 0);
signal prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in : std_logic_vector (53 downto 0);
signal prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (29 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_a : std_logic_vector(79 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_b : std_logic_vector(79 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid169_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid169_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (44 downto 0);
signal InvCosXIsOne_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal join_uid96_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal signRComp_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid157_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid157_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid163_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid163_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal s2_uid239_uid242_sinPiZPolyEval_q : std_logic_vector (36 downto 0);
signal add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (55 downto 0);
signal xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (79 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid60_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal alignedZLow_uid60_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal R_uid104_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid243_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT3_uid243_sinPiZPolyEval_b : std_logic_vector (34 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid249_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT4_uid249_sinPiZPolyEval_b : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (10 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal FxpX80_uid44_fpCosPiTest_in : std_logic_vector (80 downto 0);
signal FxpX80_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid45_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal fxpXFrac_uid45_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal s3_uid248_sinPiZPolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid248_sinPiZPolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid254_sinPiZPolyEval_in : std_logic_vector (52 downto 0);
signal s4_uid254_sinPiZPolyEval_b : std_logic_vector (51 downto 0);
signal s5_uid260_sinPiZPolyEval_in : std_logic_vector (61 downto 0);
signal s5_uid260_sinPiZPolyEval_b : std_logic_vector (60 downto 0);
signal oFracX_uid39_uid39_fpCosPiTest_q : std_logic_vector (52 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid42_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal fxpShifterBits_uid42_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal rVStage_uid145_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal rVStage_uid145_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal vStage_uid148_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (14 downto 0);
signal vStage_uid148_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (14 downto 0);
signal X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (46 downto 0);
signal X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (46 downto 0);
signal lowRangeB_uid233_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid233_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid234_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal highBBits_uid234_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid239_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid239_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid240_sinPiZPolyEval_in : std_logic_vector (28 downto 0);
signal highBBits_uid240_sinPiZPolyEval_b : std_logic_vector (27 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0);
signal lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid281_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (29 downto 0);
signal highBBits_uid281_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid296_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid296_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (24 downto 0);
signal lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (24 downto 0);
signal highBBits_uid311_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid311_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (106 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (105 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (104 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal InvFxpXFracHalf_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid171_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid171_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid173_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid173_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (70 downto 0);
signal LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (70 downto 0);
signal LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (54 downto 0);
signal LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (54 downto 0);
signal yT1_uid231_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT1_uid231_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid237_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT2_uid237_sinPiZPolyEval_b : std_logic_vector (25 downto 0);
signal xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal signR_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid103_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid159_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid159_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid161_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid161_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid165_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid165_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid167_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid167_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (9 downto 0);
signal yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (9 downto 0);
signal yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal R_uid284_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal R_uid284_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (36 downto 0);
signal R_uid299_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (71 downto 0);
signal R_uid299_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (45 downto 0);
signal R_uid314_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (78 downto 0);
signal R_uid314_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (34 downto 0);
signal xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (34 downto 0);
signal xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (7 downto 0);
signal xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (7 downto 0);
signal xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (15 downto 0);
signal FxpXFrac79_uid46_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal FxpXFrac79_uid46_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (51 downto 0);
signal yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (24 downto 0);
signal yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal oFracXExt_uid41_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(63 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(63 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid149_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_a : std_logic_vector(26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_b : std_logic_vector(26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_o : std_logic_vector (26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (52 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid175_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid175_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (10 downto 0);
signal pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_1_b : std_logic_vector (26 downto 0);
signal X48dto0_uid108_fxpX_uid43_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal X48dto0_uid108_fxpX_uid43_fpCosPiTest_b : std_logic_vector (48 downto 0);
signal X16dto0_uid111_fxpX_uid43_fpCosPiTest_in : std_logic_vector (16 downto 0);
signal X16dto0_uid111_fxpX_uid43_fpCosPiTest_b : std_logic_vector (16 downto 0);
signal InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid151_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid151_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal s1_uid233_uid236_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0);
signal expFracPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal rVStage_uid177_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid177_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid179_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid179_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (17 downto 0);
signal leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid153_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid153_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid155_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal vStage_uid155_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid181_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid181_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (72 downto 0);
signal LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (72 downto 0);
signal leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0);
signal rVStage_uid183_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid183_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in : std_logic_vector (72 downto 0);
signal LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b : std_logic_vector (72 downto 0);
signal LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b : std_logic_vector (64 downto 0);
signal LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal r_uid185_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (6 downto 0);
signal LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (77 downto 0);
signal LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b : std_logic_vector (78 downto 0);
signal LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
begin
--ld_xIn_v_to_xOut_v_notEnable(LOGICAL,852)
ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q;
ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor(LOGICAL,942)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q <= not (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a or ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b);
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top(CONSTANT,938)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q <= "0100101";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp(LOGICAL,939)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q <= "1" when ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a = ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b else "0";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg(REG,940)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q;
END IF;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena(REG,943)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q = "1") THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd(LOGICAL,944)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b <= VCC_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a and ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b;
--LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest(BITSELECT,133)@0
LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest(CONSTANT,132)
leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q <= "000000";
--leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest(BITJOIN,134)@0
leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest(BITSELECT,130)@0
LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(76 downto 0);
LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in(76 downto 0);
--leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest(CONSTANT,129)
leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q <= "0000";
--leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest(BITJOIN,131)@0
leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest(BITSELECT,127)@0
LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(78 downto 0);
LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in(78 downto 0);
--leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest(CONSTANT,126)
leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q <= "00";
--leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest(BITJOIN,128)@0
leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest(BITSELECT,122)@0
LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(56 downto 0);
LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in(56 downto 0);
--leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest(CONSTANT,121)
leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest(BITJOIN,123)@0
leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest(BITSELECT,119)@0
LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(64 downto 0);
LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in(64 downto 0);
--leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest(CONSTANT,118)
leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest(BITJOIN,120)@0
leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest(BITSELECT,116)@0
LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(72 downto 0);
LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in(72 downto 0);
--leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest(CONSTANT,115)
leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest(BITJOIN,117)@0
leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
--leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest(CONSTANT,112)
leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--X16dto0_uid111_fxpX_uid43_fpCosPiTest(BITSELECT,110)@0
X16dto0_uid111_fxpX_uid43_fpCosPiTest_in <= oFracXExt_uid41_fpCosPiTest_q(16 downto 0);
X16dto0_uid111_fxpX_uid43_fpCosPiTest_b <= X16dto0_uid111_fxpX_uid43_fpCosPiTest_in(16 downto 0);
--leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest(CONSTANT,109)
leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest(BITJOIN,111)@0
leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q <= X16dto0_uid111_fxpX_uid43_fpCosPiTest_b & leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
--X48dto0_uid108_fxpX_uid43_fpCosPiTest(BITSELECT,107)@0
X48dto0_uid108_fxpX_uid43_fpCosPiTest_in <= oFracXExt_uid41_fpCosPiTest_q(48 downto 0);
X48dto0_uid108_fxpX_uid43_fpCosPiTest_b <= X48dto0_uid108_fxpX_uid43_fpCosPiTest_in(48 downto 0);
--leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest(CONSTANT,106)
leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest(BITJOIN,108)@0
leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q <= X48dto0_uid108_fxpX_uid43_fpCosPiTest_b & leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
--cst01pWShift_uid15_fpCosPiTest(CONSTANT,14)
cst01pWShift_uid15_fpCosPiTest_q <= "0000000000000000000000000000";
--xIn(PORTIN,3)@0
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= xIn_0(51 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(51 downto 0);
--oFracX_uid39_uid39_fpCosPiTest(BITJOIN,38)@0
oFracX_uid39_uid39_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid41_fpCosPiTest(BITJOIN,40)@0
oFracXExt_uid41_fpCosPiTest_q <= cst01pWShift_uid15_fpCosPiTest_q & oFracX_uid39_uid39_fpCosPiTest_q;
--biasMwShiftMO_uid14_fpCosPiTest(CONSTANT,13)
biasMwShiftMO_uid14_fpCosPiTest_q <= "01111100011";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= xIn_0(62 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(62 downto 52);
--shiftValFxPX_uid40_fpCosPiTest(SUB,39)@0
shiftValFxPX_uid40_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid40_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid14_fpCosPiTest_q);
shiftValFxPX_uid40_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid40_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid40_fpCosPiTest_b));
shiftValFxPX_uid40_fpCosPiTest_q <= shiftValFxPX_uid40_fpCosPiTest_o(11 downto 0);
--fxpShifterBits_uid42_fpCosPiTest(BITSELECT,41)@0
fxpShifterBits_uid42_fpCosPiTest_in <= shiftValFxPX_uid40_fpCosPiTest_q(6 downto 0);
fxpShifterBits_uid42_fpCosPiTest_b <= fxpShifterBits_uid42_fpCosPiTest_in(6 downto 0);
--leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest(BITSELECT,113)@0
leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b;
leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in(6 downto 5);
--leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest(MUX,114)@0
leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b;
leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s, oFracXExt_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q, leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= oFracXExt_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest(BITSELECT,124)@0
leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(4 downto 0);
leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in(4 downto 3);
--leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest(MUX,125)@0
leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b;
leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s, leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q;
WHEN "01" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest(BITSELECT,135)@0
leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(2 downto 0);
leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in(2 downto 1);
--leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest(MUX,136)@0
leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b;
leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s, leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest(BITSELECT,138)@0
LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in <= leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q(79 downto 0);
LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in(79 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest(BITJOIN,139)@0
leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b & GND_q;
--reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3(REG,356)@0
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q <= leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q;
END IF;
END PROCESS;
--reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2(REG,357)@0
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q <= leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q;
END IF;
END PROCESS;
--leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest(BITSELECT,140)@0
leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(0 downto 0);
leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b(DELAY,547)@0
ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q, clk => clk, aclr => areset );
--leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest(MUX,141)@1
leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q;
leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s, reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q, reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q)
BEGIN
CASE leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s IS
WHEN "0" => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q;
WHEN "1" => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q;
WHEN OTHERS => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid45_fpCosPiTest(BITSELECT,44)@1
fxpXFrac_uid45_fpCosPiTest_in <= leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q(79 downto 0);
fxpXFrac_uid45_fpCosPiTest_b <= fxpXFrac_uid45_fpCosPiTest_in(79 downto 0);
--FxpXFrac79_uid46_fpCosPiTest(BITSELECT,45)@1
FxpXFrac79_uid46_fpCosPiTest_in <= fxpXFrac_uid45_fpCosPiTest_b;
FxpXFrac79_uid46_fpCosPiTest_b <= FxpXFrac79_uid46_fpCosPiTest_in(79 downto 79);
--FxpX80_uid44_fpCosPiTest(BITSELECT,43)@1
FxpX80_uid44_fpCosPiTest_in <= leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q;
FxpX80_uid44_fpCosPiTest_b <= FxpX80_uid44_fpCosPiTest_in(80 downto 80);
--Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest(LOGICAL,97)@1
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a <= FxpX80_uid44_fpCosPiTest_b;
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b <= FxpXFrac79_uid46_fpCosPiTest_b;
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q <= Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a xor Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b;
--ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c(DELAY,504)@1
ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q, xout => ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q, clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10000110011";
--xEvenInt_uid37_fpCosPiTest(COMPARE,36)@0
xEvenInt_uid37_fpCosPiTest_cin <= GND_q;
xEvenInt_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid37_fpCosPiTest_cin(0);
xEvenInt_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid37_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid37_fpCosPiTest_b));
xEvenInt_uid37_fpCosPiTest_c(0) <= xEvenInt_uid37_fpCosPiTest_o(13);
--ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a(DELAY,470)@0
ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid37_fpCosPiTest_c, xout => ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q, clk => clk, aclr => areset );
--InvXEvenInt_uid83_fpCosPiTest(LOGICAL,82)@2
InvXEvenInt_uid83_fpCosPiTest_a <= ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q;
InvXEvenInt_uid83_fpCosPiTest_q <= not InvXEvenInt_uid83_fpCosPiTest_a;
--biasMwShift_uid13_fpCosPiTest(CONSTANT,12)
biasMwShift_uid13_fpCosPiTest_q <= "01111100100";
--cosXIsOne_uid38_fpCosPiTest(COMPARE,37)@0
cosXIsOne_uid38_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid13_fpCosPiTest_q) & cosXIsOne_uid38_fpCosPiTest_cin(0);
cosXIsOne_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid38_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid38_fpCosPiTest_b));
cosXIsOne_uid38_fpCosPiTest_c(0) <= cosXIsOne_uid38_fpCosPiTest_o(13);
--ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a(DELAY,467)@0
ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid38_fpCosPiTest_c, xout => ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q, clk => clk, aclr => areset );
--InvCosXIsOne_uid79_fpCosPiTest(LOGICAL,78)@2
InvCosXIsOne_uid79_fpCosPiTest_a <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q;
InvCosXIsOne_uid79_fpCosPiTest_q <= not InvCosXIsOne_uid79_fpCosPiTest_a;
--signRComp_uid101_fpCosPiTest(LOGICAL,100)@2
signRComp_uid101_fpCosPiTest_a <= InvCosXIsOne_uid79_fpCosPiTest_q;
signRComp_uid101_fpCosPiTest_b <= InvXEvenInt_uid83_fpCosPiTest_q;
signRComp_uid101_fpCosPiTest_c <= ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q;
signRComp_uid101_fpCosPiTest_q <= signRComp_uid101_fpCosPiTest_a and signRComp_uid101_fpCosPiTest_b and signRComp_uid101_fpCosPiTest_c;
--cstZwSwF_uid16_fpCosPiTest(CONSTANT,15)
cstZwSwF_uid16_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000";
--cstHalfwSwFP1_uid19_fpCosPiTest(BITJOIN,18)@2
cstHalfwSwFP1_uid19_fpCosPiTest_q <= VCC_q & cstZwSwF_uid16_fpCosPiTest_q;
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0(REG,359)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--fxpXFracHalf_uid48_fpCosPiTest(LOGICAL,47)@2
fxpXFracHalf_uid48_fpCosPiTest_a <= reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q;
fxpXFracHalf_uid48_fpCosPiTest_b <= cstHalfwSwFP1_uid19_fpCosPiTest_q;
fxpXFracHalf_uid48_fpCosPiTest_q <= "1" when fxpXFracHalf_uid48_fpCosPiTest_a = fxpXFracHalf_uid48_fpCosPiTest_b else "0";
--InvFxpXFracHalf_uid102_fpCosPiTest(LOGICAL,101)@2
InvFxpXFracHalf_uid102_fpCosPiTest_a <= fxpXFracHalf_uid48_fpCosPiTest_q;
InvFxpXFracHalf_uid102_fpCosPiTest_q <= not InvFxpXFracHalf_uid102_fpCosPiTest_a;
--signR_uid103_fpCosPiTest(LOGICAL,102)@2
signR_uid103_fpCosPiTest_a <= InvFxpXFracHalf_uid102_fpCosPiTest_q;
signR_uid103_fpCosPiTest_b <= signRComp_uid101_fpCosPiTest_q;
signR_uid103_fpCosPiTest_q <= signR_uid103_fpCosPiTest_a and signR_uid103_fpCosPiTest_b;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg(DELAY,932)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid103_fpCosPiTest_q, xout => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q, clk => clk, aclr => areset );
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt(COUNTER,934)
-- every=1, low=0, high=37, step=1, init=1
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i = 36 THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i - 37;
ELSE
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg(REG,935)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux(MUX,936)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s <= VCC_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux: PROCESS (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s, ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q, ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem(DUALMEM,933)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq,
address_a => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa,
data_a => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia
);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111111";
--cstAllZWE_uid22_fpCosPiTest(CONSTANT,21)
cstAllZWE_uid22_fpCosPiTest_q <= "00000000000";
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1(REG,361)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--pad_o_uid17_uid49_fpCosPiTest(BITJOIN,48)@1
pad_o_uid17_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((79 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0(REG,362)@1
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q <= pad_o_uid17_uid49_fpCosPiTest_q;
END IF;
END PROCESS;
--oMFxpXFrac_uid49_fpCosPiTest(SUB,49)@2
oMFxpXFrac_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q);
oMFxpXFrac_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q);
oMFxpXFrac_uid49_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oMFxpXFrac_uid49_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
oMFxpXFrac_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid49_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid49_fpCosPiTest_b));
END IF;
END PROCESS;
oMFxpXFrac_uid49_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_o(81 downto 0);
--oMFxpXFrac_uid51_fpCosPiTest(BITSELECT,50)@3
oMFxpXFrac_uid51_fpCosPiTest_in <= oMFxpXFrac_uid49_fpCosPiTest_q(79 downto 0);
oMFxpXFrac_uid51_fpCosPiTest_b <= oMFxpXFrac_uid51_fpCosPiTest_in(79 downto 0);
--ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c(DELAY,443)@1
ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 80, depth => 2 )
PORT MAP ( xin => fxpXFrac_uid45_fpCosPiTest_b, xout => ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q, clk => clk, aclr => areset );
--ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b(DELAY,442)@1
ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => FxpXFrac79_uid46_fpCosPiTest_b, xout => ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q, clk => clk, aclr => areset );
--rangeReducedFxPX_uid53_fpCosPiTest(MUX,52)@3
rangeReducedFxPX_uid53_fpCosPiTest_s <= ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q;
rangeReducedFxPX_uid53_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid53_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE rangeReducedFxPX_uid53_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid53_fpCosPiTest_q <= ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid53_fpCosPiTest_q <= oMFxpXFrac_uid51_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid53_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--pad_half_uid18_uid54_fpCosPiTest(BITJOIN,53)@3
pad_half_uid18_uid54_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((78 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0(REG,363)@3
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q <= pad_half_uid18_uid54_fpCosPiTest_q;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid54_fpCosPiTest(SUB,54)@4
z_halfMRRFxPXE_uid54_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid54_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid53_fpCosPiTest_q);
z_halfMRRFxPXE_uid54_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
z_halfMRRFxPXE_uid54_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
z_halfMRRFxPXE_uid54_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid54_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid54_fpCosPiTest_b));
END IF;
END PROCESS;
z_halfMRRFxPXE_uid54_fpCosPiTest_q <= z_halfMRRFxPXE_uid54_fpCosPiTest_o(80 downto 0);
--z_uid56_fpCosPiTest(BITSELECT,55)@5
z_uid56_fpCosPiTest_in <= z_halfMRRFxPXE_uid54_fpCosPiTest_q(78 downto 0);
z_uid56_fpCosPiTest_b <= z_uid56_fpCosPiTest_in(78 downto 0);
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@5
zAddr_uid64_fpCosPiTest_in <= z_uid56_fpCosPiTest_b;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(78 downto 72);
--memoryC5_uid230_sinPiZTableGenerator(LOOKUP,229)@5
memoryC5_uid230_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (zAddr_uid64_fpCosPiTest_b) IS
WHEN "0000000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
WHEN "0000001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111110101101000";
WHEN "0000010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111101101011101";
WHEN "0000011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111100110001110";
WHEN "0000100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111100000000010";
WHEN "0000101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111011000000000";
WHEN "0000110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111010001101101";
WHEN "0000111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111001010010111";
WHEN "0001000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111000010110010";
WHEN "0001001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110111100010100";
WHEN "0001010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110110100011111";
WHEN "0001011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110101100101101";
WHEN "0001100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110100101101011";
WHEN "0001101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110011111011101";
WHEN "0001110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110010111001010";
WHEN "0001111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110010001011011";
WHEN "0010000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110001010101011";
WHEN "0010001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110000011011001";
WHEN "0010010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101111011000001";
WHEN "0010011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101110101001010";
WHEN "0010100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101101110100110";
WHEN "0010101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101100111100011";
WHEN "0010110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101011111111111";
WHEN "0010111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101011001001010";
WHEN "0011000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101010010100110";
WHEN "0011001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101001010011011";
WHEN "0011010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101000100011100";
WHEN "0011011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100111101010110";
WHEN "0011100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100110110111000";
WHEN "0011101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100101111110010";
WHEN "0011110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100100111110010";
WHEN "0011111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100100001010101";
WHEN "0100000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100011011011111";
WHEN "0100001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100010011110111";
WHEN "0100010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100001110001010";
WHEN "0100011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100000111000100";
WHEN "0100100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011111111110101";
WHEN "0100101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011111001010110";
WHEN "0100110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011110011000111";
WHEN "0100111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011101101000000";
WHEN "0101000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011100110000011";
WHEN "0101001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011011111111001";
WHEN "0101010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011011000100110";
WHEN "0101011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011010010101100";
WHEN "0101100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011001100010010";
WHEN "0101101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011000101010111";
WHEN "0101110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010111111101010";
WHEN "0101111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010111001010000";
WHEN "0110000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010110011010011";
WHEN "0110001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010101100101011";
WHEN "0110010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010100110111110";
WHEN "0110011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010011111111000";
WHEN "0110100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010011010110010";
WHEN "0110101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010010101001110";
WHEN "0110110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010001110010011";
WHEN "0110111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010001000111011";
WHEN "0111000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010000001111011";
WHEN "0111001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001111011111110";
WHEN "0111010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001110111001010";
WHEN "0111011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001110001110111";
WHEN "0111100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001101011000100";
WHEN "0111101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001100101010010";
WHEN "0111110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001100000011111";
WHEN "0111111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001011010001010";
WHEN "1000000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001010100111110";
WHEN "1000001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001001110110010";
WHEN "1000010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001001010111000";
WHEN "1000011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001000100111111";
WHEN "1000100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000111111001100";
WHEN "1000101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000111010001001";
WHEN "1000110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000110101010110";
WHEN "1000111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000110000011101";
WHEN "1001000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000101001110100";
WHEN "1001001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000100101111001";
WHEN "1001010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000011111111010";
WHEN "1001011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000011011110110";
WHEN "1001100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000010110001100";
WHEN "1001101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000010001001000";
WHEN "1001110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000001101111001";
WHEN "1001111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000001000000111";
WHEN "1010000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000000010111001";
WHEN "1010001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111111110110110";
WHEN "1010010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111111001111111";
WHEN "1010011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111110110010100";
WHEN "1010100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111110001011000";
WHEN "1010101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111101100010111";
WHEN "1010110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111101000010010";
WHEN "1010111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111100100010000";
WHEN "1011000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111100000111100";
WHEN "1011001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111011011111111";
WHEN "1011010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010111100000";
WHEN "1011011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010011110100";
WHEN "1011100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010000011100";
WHEN "1011101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111001011011110";
WHEN "1011110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000111111101";
WHEN "1011111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000100101011";
WHEN "1100000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000001100100";
WHEN "1100001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110111101101110";
WHEN "1100010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110111010011000";
WHEN "1100011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110110110000";
WHEN "1100100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110010011010";
WHEN "1100101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110000011110";
WHEN "1100110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110101100101100";
WHEN "1100111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110101000101110";
WHEN "1101000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100110100000";
WHEN "1101001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100100010001";
WHEN "1101010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100001000000";
WHEN "1101011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110011101101110";
WHEN "1101100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110011011011111";
WHEN "1101101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010111000100";
WHEN "1101110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010101110011";
WHEN "1101111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010001111100";
WHEN "1110000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010000001111";
WHEN "1110001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110001110011001";
WHEN "1110010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110001010100010";
WHEN "1110011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000111111000";
WHEN "1110100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000101110110";
WHEN "1110101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000101000100";
WHEN "1110110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000010100010";
WHEN "1110111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111111110011";
WHEN "1111000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111110010000";
WHEN "1111001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111100110111";
WHEN "1111010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111010111000";
WHEN "1111011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111000101000";
WHEN "1111100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110110110100";
WHEN "1111101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110101011010";
WHEN "1111110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110100000011";
WHEN "1111111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110010001011";
WHEN OTHERS =>
memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
END CASE;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a(DELAY,452)@5
ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => z_uid56_fpCosPiTest_b, xout => ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q, clk => clk, aclr => areset );
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@6
zPPolyEval_uid65_fpCosPiTest_in <= ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q(71 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(71 downto 27);
--yT1_uid231_sinPiZPolyEval(BITSELECT,230)@6
yT1_uid231_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid231_sinPiZPolyEval_b <= yT1_uid231_sinPiZPolyEval_in(44 downto 28);
--prodXY_uid262_pT1_uid232_sinPiZPolyEval(MULT,261)@6
prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid262_pT1_uid232_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid262_pT1_uid232_sinPiZPolyEval_b);
prodXY_uid262_pT1_uid232_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_a <= (others => '0');
prodXY_uid262_pT1_uid232_sinPiZPolyEval_b <= (others => '0');
prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_a <= yT1_uid231_sinPiZPolyEval_b;
prodXY_uid262_pT1_uid232_sinPiZPolyEval_b <= memoryC5_uid230_sinPiZTableGenerator_q;
prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr,34));
END IF;
END PROCESS;
prodXY_uid262_pT1_uid232_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_q <= prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval(BITSELECT,262)@9
prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in <= prodXY_uid262_pT1_uid232_sinPiZPolyEval_q;
prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in(33 downto 16);
--highBBits_uid234_sinPiZPolyEval(BITSELECT,233)@9
highBBits_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b;
highBBits_uid234_sinPiZPolyEval_b <= highBBits_uid234_sinPiZPolyEval_in(17 downto 1);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a(DELAY,638)@5
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q, clk => clk, aclr => areset );
--memoryC4_uid229_sinPiZTableGenerator(LOOKUP,228)@8
memoryC4_uid229_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
WHEN "0000001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110011111111100";
WHEN "0000010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100101101100110011";
WHEN "0000011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100100010011000101";
WHEN "0000100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100010010010010110";
WHEN "0000101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011111110011000100";
WHEN "0000110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011100101011001100";
WHEN "0000111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011001000001111000";
WHEN "0001000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001010100110101100100";
WHEN "0001001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001010000000010110001";
WHEN "0001010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001001010101111100100";
WHEN "0001011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001000100111000100010";
WHEN "0001100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000111110011011110101";
WHEN "0001101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000110111011001010101";
WHEN "0001110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000101111111000110001";
WHEN "0001111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000100111101101111110";
WHEN "0010000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000011111000010010110";
WHEN "0010001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000010101110100101111";
WHEN "0010010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000001100000110110101";
WHEN "0010011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000000001101111000000";
WHEN "0010100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111110110110101110011";
WHEN "0010101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111101011011010111001";
WHEN "0010110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111011111011110000110";
WHEN "0010111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111010010111100110100";
WHEN "0011000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111000101110111111001";
WHEN "0011001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110111000010100011101";
WHEN "0011010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110101010001000110011";
WHEN "0011011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110011011011101100111";
WHEN "0011100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110001100001110001111";
WHEN "0011101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101111100011110001010";
WHEN "0011110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101101100001110100101";
WHEN "0011111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101011011011000110110";
WHEN "0100000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101001001111111101110";
WHEN "0100001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100111000001001001111";
WHEN "0100010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100100101101100011001";
WHEN "0100011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100010010110001110000";
WHEN "0100100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011111111010101110110";
WHEN "0100101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011101011010111000111";
WHEN "0100110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011010110110110011110";
WHEN "0100111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011000001110100011110";
WHEN "0101000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001010101100010100010011";
WHEN "0101001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001010010110010001000111";
WHEN "0101010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001111111110001000100";
WHEN "0101011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001101000101100110110";
WHEN "0101100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001010001001001111011";
WHEN "0101101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000111001001000001110";
WHEN "0101110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000100000100011110110";
WHEN "0101111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000000111100001111001";
WHEN "0110000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000111101101111111011111";
WHEN "0110001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000111010011111111100110";
WHEN "0110010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110111001011110100100";
WHEN "0110011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110011110100010000111";
WHEN "0110100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110000011000010001001";
WHEN "0110101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000101100111000101000011";
WHEN "0110110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000101001010101101011111";
WHEN "0110111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000100101101110011101110";
WHEN "0111000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000100010000100000111110";
WHEN "0111001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000011110010101101110100";
WHEN "0111010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000011010100011010011110";
WHEN "0111011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000010110101101011010111";
WHEN "0111100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000010010110100011011101";
WHEN "0111101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000001110110111100001001";
WHEN "0111110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000001010110110110010000";
WHEN "0111111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000000110110011000001101";
WHEN "1000000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000000010101011011011001";
WHEN "1000001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111111110100000101110010";
WHEN "1000010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111111010010001110101001";
WHEN "1000011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111110110000000001101011";
WHEN "1000100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111110001101011001110011";
WHEN "1000101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111101101010010101011101";
WHEN "1000110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111101000110110101111111";
WHEN "1000111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111100100010111100111100";
WHEN "1001000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111011111110101110100100";
WHEN "1001001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111011011001111111110100";
WHEN "1001010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111010110100111101000111";
WHEN "1001011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111010001111011100101001";
WHEN "1001100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111001101001100111100001";
WHEN "1001101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111001000011011000101011";
WHEN "1001110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111000011100101100110010";
WHEN "1001111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110111110101110000000011";
WHEN "1010000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110111001110011001111101";
WHEN "1010001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110110100110101001110001";
WHEN "1010010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110101111110100101001011";
WHEN "1010011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110101010110000110010110";
WHEN "1010100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110100101101010100111010";
WHEN "1010101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110100000100001101101101";
WHEN "1010110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110011011010101110011000";
WHEN "1010111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110010110000111001010011";
WHEN "1011000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110010000110101101010010";
WHEN "1011001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110001011100010001000010";
WHEN "1011010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110000110001011111001110";
WHEN "1011011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110000000110010110110100";
WHEN "1011100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101111011010111010001000";
WHEN "1011101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101110101111001110001011";
WHEN "1011110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101110000011001011001100";
WHEN "1011111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101101010110110100111111";
WHEN "1100000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101100101010001011011001";
WHEN "1100001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101011111101010010000000";
WHEN "1100010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101011010000000101001000";
WHEN "1100011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101010100010100111110111";
WHEN "1100100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101001110100111011010110";
WHEN "1100101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101001000110110111101100";
WHEN "1100110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101000011000101000001000";
WHEN "1100111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100111101010001001010101";
WHEN "1101000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100110111011010110000011";
WHEN "1101001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100110001100010011011010";
WHEN "1101010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100101011101000100011001";
WHEN "1101011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100100101101100110100111";
WHEN "1101100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100011111101110111111010";
WHEN "1101101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100011001110000000101100";
WHEN "1101110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100010011101110011110101";
WHEN "1101111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100001101101100000010000";
WHEN "1110000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100000111100111010001011";
WHEN "1110001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100000001100000111111010";
WHEN "1110010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011111011011001110101000";
WHEN "1110011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011110101010000110010111";
WHEN "1110100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011101111000110001000001";
WHEN "1110101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011101000111001101001001";
WHEN "1110110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011100010101100011001010";
WHEN "1110111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011011100011101111010110";
WHEN "1111000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011010110001101110011110";
WHEN "1111001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011001111111100011010111";
WHEN "1111010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011001001101010000100101";
WHEN "1111011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011000011010110101101110";
WHEN "1111100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010111101000010001000000";
WHEN "1111101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010110110101100011000101";
WHEN "1111110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010110000010101101010111";
WHEN "1111111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010101001111110001011010";
WHEN OTHERS =>
memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid235_sinPiZPolyEval(ADD,234)@9
sumAHighB_uid235_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid229_sinPiZTableGenerator_q(25)) & memoryC4_uid229_sinPiZTableGenerator_q);
sumAHighB_uid235_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid234_sinPiZPolyEval_b(16)) & highBBits_uid234_sinPiZPolyEval_b);
sumAHighB_uid235_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid235_sinPiZPolyEval_b));
sumAHighB_uid235_sinPiZPolyEval_q <= sumAHighB_uid235_sinPiZPolyEval_o(26 downto 0);
--lowRangeB_uid233_sinPiZPolyEval(BITSELECT,232)@9
lowRangeB_uid233_sinPiZPolyEval_in <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid233_sinPiZPolyEval_b <= lowRangeB_uid233_sinPiZPolyEval_in(0 downto 0);
--s1_uid233_uid236_sinPiZPolyEval(BITJOIN,235)@9
s1_uid233_uid236_sinPiZPolyEval_q <= sumAHighB_uid235_sinPiZPolyEval_q & lowRangeB_uid233_sinPiZPolyEval_b;
--reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1(REG,373)@9
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q <= "0000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q <= s1_uid233_uid236_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor(LOGICAL,977)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q <= not (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a or ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg(REG,975)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q <= VCC_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena(REG,978)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd(LOGICAL,979)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b <= VCC_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a and ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b;
--yT2_uid237_sinPiZPolyEval(BITSELECT,236)@6
yT2_uid237_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT2_uid237_sinPiZPolyEval_b <= yT2_uid237_sinPiZPolyEval_in(44 downto 19);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt(COUNTER,971)
-- every=1, low=0, high=1, step=1, init=1
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i,1));
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg(REG,972)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux(MUX,973)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s <= VCC_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux: PROCESS (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
WHEN "1" => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem(DUALMEM,1059)
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia <= yT2_uid237_sinPiZPolyEval_b;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia
);
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q <= ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq(25 downto 0);
--ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg(DELAY,1058)
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q, xout => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--prodXY_uid265_pT2_uid238_sinPiZPolyEval(MULT,264)@10
prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid265_pT2_uid238_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid265_pT2_uid238_sinPiZPolyEval_b);
prodXY_uid265_pT2_uid238_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_a <= (others => '0');
prodXY_uid265_pT2_uid238_sinPiZPolyEval_b <= (others => '0');
prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_a <= ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q;
prodXY_uid265_pT2_uid238_sinPiZPolyEval_b <= reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q;
prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
prodXY_uid265_pT2_uid238_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_q <= prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval(BITSELECT,265)@13
prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in <= prodXY_uid265_pT2_uid238_sinPiZPolyEval_q;
prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in(53 downto 25);
--highBBits_uid240_sinPiZPolyEval(BITSELECT,239)@13
highBBits_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b;
highBBits_uid240_sinPiZPolyEval_b <= highBBits_uid240_sinPiZPolyEval_in(28 downto 1);
--reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1(REG,374)@13
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q <= "0000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q <= highBBits_uid240_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor(LOGICAL,1029)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top(CONSTANT,1025)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q <= "0101";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp(LOGICAL,1026)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg(REG,1027)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena(REG,1030)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd(LOGICAL,1031)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,1021)
-- every=1, low=0, high=5, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i = 4 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i - 5;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg(REG,1022)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux(MUX,1023)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem(DUALMEM,1020)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 6,
width_b => 7,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg(DELAY,1019)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC3_uid228_sinPiZTableGenerator(LOOKUP,227)@13
memoryC3_uid228_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
WHEN "0000001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000001010001100110101000111010101";
WHEN "0000010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000010100011001100101101010110011";
WHEN "0000011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000011110100110001101010100011011";
WHEN "0000100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000101000110010100111100101110011";
WHEN "0000101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000110010111110101111101101101000";
WHEN "0000110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000111101001010100001100001001101";
WHEN "0000111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001000111010101111000010100001000";
WHEN "0001000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001010001100000101111101001011010";
WHEN "0001001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001011011101011000011001000111110";
WHEN "0001010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001100101110100101110001001110101";
WHEN "0001011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001101111111101101100010100000001";
WHEN "0001100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001111010000101111001001101010110";
WHEN "0001101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010000100001101010000011000110101";
WHEN "0001110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010001110010011101101001010101000";
WHEN "0001111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010011000011001001011011101011111";
WHEN "0010000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010100010011101100110100011101011";
WHEN "0010001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010101100100000111010000011110001";
WHEN "0010010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010110110100011000001011111010110";
WHEN "0010011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011000000100011111000101110110101";
WHEN "0010100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011001010100011011011001000001011";
WHEN "0010101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011010100100001100100010010100101";
WHEN "0010110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011011110011110001111110110101010";
WHEN "0010111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011101000011001011001100000011011";
WHEN "0011000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011110010010010111100111000010100";
WHEN "0011001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011111100001010110101011110000110";
WHEN "0011010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100000110000000111111001110100010";
WHEN "0011011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100001111110101010101100100101101";
WHEN "0011100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100011001100111110100010110001111";
WHEN "0011101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100100011011000010111001001011111";
WHEN "0011110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100101101000110111001101001101001";
WHEN "0011111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100110110110011010111110011001100";
WHEN "0100000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101000000011101101101010000100110";
WHEN "0100001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101001010000101110101101000010110";
WHEN "0100010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101010011101011101100111100100100";
WHEN "0100011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101011101001111001110110000110010";
WHEN "0100100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101100110110000010111000000110011";
WHEN "0100101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101110000001111000001100011110100";
WHEN "0100110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101111001101011001010010000000001";
WHEN "0100111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110000011000100101100111100001110";
WHEN "0101000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110001100011011100101011010100101";
WHEN "0101001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110010101101111101111110000010101";
WHEN "0101010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110011111000001000111101011101100";
WHEN "0101011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110101000001111101001011001100010";
WHEN "0101100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110110001011011010000101101010010";
WHEN "0101101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110111010100011111001100111101100";
WHEN "0101110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111000011101001100000010000100010";
WHEN "0101111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111001100101100000000100001010000";
WHEN "0110000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111010101101011010110100011101100";
WHEN "0110001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111011110100111011110011000011110";
WHEN "0110010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111100111100000010100001101010000";
WHEN "0110011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111110000010101110100000001010000";
WHEN "0110100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111111001000111111010001101010001";
WHEN "0110101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000000001110110100010110001111010";
WHEN "0110110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000001010100001101001110111110101";
WHEN "0110111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000010011001001001011111110000001";
WHEN "0111000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000011011101101000101000010101111";
WHEN "0111001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000100100001101010001101000100100";
WHEN "0111010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000101100101001101110000011010101";
WHEN "0111011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000110101000010010110100001011010";
WHEN "0111100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000111101010111000111010101011110";
WHEN "0111101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001000101100111111101000110111000";
WHEN "0111110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001001101110100110100001111001100";
WHEN "0111111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001010101111101101001000001001010";
WHEN "1000000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001011110000010011000001001000011";
WHEN "1000001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001100110000010111101111101010011";
WHEN "1000010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001101101111111010111010011001111";
WHEN "1000011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001110101110111100000011010000110";
WHEN "1000100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001111101101011010110000011010010";
WHEN "1000101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010000101011010110100111100000101";
WHEN "1000110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010001101000101111001101110100011";
WHEN "1000111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010010100101100100001000101010010";
WHEN "1001000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010011100001110100111101001010100";
WHEN "1001001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010100011101100001010100001011100";
WHEN "1001010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010101011000101000110001011100100";
WHEN "1001011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010110010011001010111110000100100";
WHEN "1001100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010111001101000111011111001000111";
WHEN "1001101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011000000110011101111101001011111";
WHEN "1001110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011000111111001110000000110011110";
WHEN "1001111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011001110111010111001110111111110";
WHEN "1010000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011010101110111001010010001110110";
WHEN "1010001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011011100101110011110011000111101";
WHEN "1010010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011100011100000110011001001001001";
WHEN "1010011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011101010001110000101111000101100";
WHEN "1010100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011110000110110010011100011000111";
WHEN "1010101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011110111011001011001011101010011";
WHEN "1010110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011111101110111010100111100011100";
WHEN "1010111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100000100010000000011001111101101";
WHEN "1011000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100001010100011100001101110011100";
WHEN "1011001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100010000110001101101100011100011";
WHEN "1011010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100010110111010100100010100000100";
WHEN "1011011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100011100111110000011100000001010";
WHEN "1011100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100100010111100001000100001101001";
WHEN "1011101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100101000110100110000110001111011";
WHEN "1011110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100101110100111111010000100111001";
WHEN "1011111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100110100010101100001111010001101";
WHEN "1100000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100111001111101100101111101110000";
WHEN "1100001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100111111100000000011110011100101";
WHEN "1100010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101000100111100111001010011110100";
WHEN "1100011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101001010010100000100001001001101";
WHEN "1100100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101001111100101100010000111001000";
WHEN "1100101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101010100110001010001010100001101";
WHEN "1100110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101011001110111001111010101110101";
WHEN "1100111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101011110110111011010001101111010";
WHEN "1101000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101100011110001110000000111001111";
WHEN "1101001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101101000100110001110111010010001";
WHEN "1101010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101101101010100110100100110101101";
WHEN "1101011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101110001111101011111011001010101";
WHEN "1101100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101110110100000001101100000100000";
WHEN "1101101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101111010111100111100111010111000";
WHEN "1101110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101111111010011101100010000110110";
WHEN "1101111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110000011100100011001011010100000";
WHEN "1110000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110000111101111000011000011110011";
WHEN "1110001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110001011110011100111011010000000";
WHEN "1110010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110001111110010000100101111100001";
WHEN "1110011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110010011101010011001110010000111";
WHEN "1110100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110010111011100100100111111111001";
WHEN "1110101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110011011001000100101000000101011";
WHEN "1110110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110011110101110011000001011101010";
WHEN "1110111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110100010001101111101010010100010";
WHEN "1111000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110100101100111010011001000110011";
WHEN "1111001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101000111010011000011010000011";
WHEN "1111010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101100000111001011110100010010";
WHEN "1111011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101111001101101100001110011100";
WHEN "1111100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110010001101111000100101110110";
WHEN "1111101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110101000111101111110101001010";
WHEN "1111110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110111111011010000111000110000";
WHEN "1111111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110111010101000011010110000100000";
WHEN OTHERS =>
memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid241_sinPiZPolyEval(ADD,240)@14
sumAHighB_uid241_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid228_sinPiZTableGenerator_q(34)) & memoryC3_uid228_sinPiZTableGenerator_q);
sumAHighB_uid241_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q);
sumAHighB_uid241_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid241_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid241_sinPiZPolyEval_b));
sumAHighB_uid241_sinPiZPolyEval_q <= sumAHighB_uid241_sinPiZPolyEval_o(35 downto 0);
--lowRangeB_uid239_sinPiZPolyEval(BITSELECT,238)@13
lowRangeB_uid239_sinPiZPolyEval_in <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid239_sinPiZPolyEval_b <= lowRangeB_uid239_sinPiZPolyEval_in(0 downto 0);
--ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a(DELAY,652)@13
ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid239_sinPiZPolyEval_b, xout => ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--s2_uid239_uid242_sinPiZPolyEval(BITJOIN,241)@14
s2_uid239_uid242_sinPiZPolyEval_q <= sumAHighB_uid241_sinPiZPolyEval_q & ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q;
--yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval(BITSELECT,273)@14
yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q;
yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b <= yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in(36 downto 19);
--reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9(REG,375)@14
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor(LOGICAL,1042)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top(CONSTANT,1038)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q <= "0110";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp(LOGICAL,1039)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg(REG,1040)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena(REG,1043)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd(LOGICAL,1044)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1034)
-- every=1, low=0, high=6, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i = 5 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg(REG,1035)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux(MUX,1036)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem(DUALMEM,1033)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 3,
numwords_a => 7,
width_b => 45,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg(DELAY,1032)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--yT3_uid243_sinPiZPolyEval(BITSELECT,242)@15
yT3_uid243_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q;
yT3_uid243_sinPiZPolyEval_b <= yT3_uid243_sinPiZPolyEval_in(44 downto 10);
--xBottomBits_uid273_pT3_uid244_sinPiZPolyEval(BITSELECT,272)@15
xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b(7 downto 0);
xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b <= xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in(7 downto 0);
--pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval(BITJOIN,275)@15
pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q <= xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid272_pT3_uid244_sinPiZPolyEval(BITSELECT,271)@14
yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q(9 downto 0);
yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b <= yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in(9 downto 0);
--spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval(BITJOIN,274)@14
spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q <= GND_q & yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b;
--pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval(BITJOIN,276)@14
pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q <= spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6(REG,376)@14
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q;
END IF;
END PROCESS;
--xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval(BITSELECT,270)@15
xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b;
xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b <= xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in(34 downto 17);
--multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma(CHAINMULTADD,344)@15
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(1);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(1),38);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b),19));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q),19));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q),18));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q),18));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y(0);
END IF;
END PROCESS;
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s(0),37));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval(BITSELECT,278)@18
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q;
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in(36 downto 7);
--highBBits_uid281_pT3_uid244_sinPiZPolyEval(BITSELECT,280)@18
highBBits_uid281_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b;
highBBits_uid281_pT3_uid244_sinPiZPolyEval_b <= highBBits_uid281_pT3_uid244_sinPiZPolyEval_in(29 downto 1);
--reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1(REG,378)@18
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q <= highBBits_uid281_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval(BITSELECT,268)@14
yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q;
yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b <= yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in(36 downto 10);
--reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1(REG,377)@14
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q <= yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval(BITSELECT,267)@15
xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b;
xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b <= xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in(34 downto 8);
--topProd_uid270_pT3_uid244_sinPiZPolyEval(MULT,269)@15
topProd_uid270_pT3_uid244_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid270_pT3_uid244_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid270_pT3_uid244_sinPiZPolyEval_b);
topProd_uid270_pT3_uid244_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_a <= (others => '0');
topProd_uid270_pT3_uid244_sinPiZPolyEval_b <= (others => '0');
topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_a <= xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b;
topProd_uid270_pT3_uid244_sinPiZPolyEval_b <= reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q;
topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid270_pT3_uid244_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid270_pT3_uid244_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_q <= topProd_uid270_pT3_uid244_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0(REG,379)@18
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q <= topProd_uid270_pT3_uid244_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid282_pT3_uid244_sinPiZPolyEval(ADD,281)@19
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q(53)) & reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q);
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q);
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b));
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q <= sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid280_pT3_uid244_sinPiZPolyEval(BITSELECT,279)@18
lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b <= lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in(0 downto 0);
--ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a(DELAY,690)@18
ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b, xout => ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid280_uid283_pT3_uid244_sinPiZPolyEval(BITJOIN,282)@19
add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q <= sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q & ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q;
--R_uid284_pT3_uid244_sinPiZPolyEval(BITSELECT,283)@19
R_uid284_pT3_uid244_sinPiZPolyEval_in <= add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q(54 downto 0);
R_uid284_pT3_uid244_sinPiZPolyEval_b <= R_uid284_pT3_uid244_sinPiZPolyEval_in(54 downto 18);
--reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1(REG,380)@19
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q <= R_uid284_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor(LOGICAL,1016)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top(CONSTANT,1012)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q <= "01011";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp(LOGICAL,1013)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg(REG,1014)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena(REG,1017)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd(LOGICAL,1018)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,1008)
-- every=1, low=0, high=11, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i = 10 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i - 11;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i,4));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg(REG,1009)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux(MUX,1010)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem(DUALMEM,1007)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 12,
width_b => 7,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg(DELAY,1006)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC2_uid227_sinPiZTableGenerator(LOOKUP,226)@19
memoryC2_uid227_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000";
WHEN "0000001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000";
WHEN "0000010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101";
WHEN "0000011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011";
WHEN "0000100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110";
WHEN "0000101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100";
WHEN "0000110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001";
WHEN "0000111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000";
WHEN "0001000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001";
WHEN "0001001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011";
WHEN "0001010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010";
WHEN "0001011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110";
WHEN "0001100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000";
WHEN "0001101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101";
WHEN "0001110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110";
WHEN "0001111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001";
WHEN "0010000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111";
WHEN "0010001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110";
WHEN "0010010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110";
WHEN "0010011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000";
WHEN "0010100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100";
WHEN "0010101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000";
WHEN "0010110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011";
WHEN "0010111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001";
WHEN "0011000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101";
WHEN "0011001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001";
WHEN "0011010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000";
WHEN "0011011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111";
WHEN "0011100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010";
WHEN "0011101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100";
WHEN "0011110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100";
WHEN "0011111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101";
WHEN "0100000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010";
WHEN "0100001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100";
WHEN "0100010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010";
WHEN "0100011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111";
WHEN "0100100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111";
WHEN "0100101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011";
WHEN "0100110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000";
WHEN "0100111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001";
WHEN "0101000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011";
WHEN "0101001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010";
WHEN "0101010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010";
WHEN "0101011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110";
WHEN "0101100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111";
WHEN "0101101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010";
WHEN "0101110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010";
WHEN "0101111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011";
WHEN "0110000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110";
WHEN "0110001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001";
WHEN "0110010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101";
WHEN "0110011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100";
WHEN "0110100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000";
WHEN "0110101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101";
WHEN "0110110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001";
WHEN "0110111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100";
WHEN "0111000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100";
WHEN "0111001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110";
WHEN "0111010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100";
WHEN "0111011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111";
WHEN "0111100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101";
WHEN "0111101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100";
WHEN "0111110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100";
WHEN "0111111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110";
WHEN "1000000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110";
WHEN "1000001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101";
WHEN "1000010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000";
WHEN "1000011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001";
WHEN "1000100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111";
WHEN "1000101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001";
WHEN "1000110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110";
WHEN "1000111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111";
WHEN "1001000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011";
WHEN "1001001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100";
WHEN "1001010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000";
WHEN "1001011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101";
WHEN "1001100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111";
WHEN "1001101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010";
WHEN "1001110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000";
WHEN "1001111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100";
WHEN "1010000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100";
WHEN "1010001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010";
WHEN "1010010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101";
WHEN "1010011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100";
WHEN "1010100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110";
WHEN "1010101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011";
WHEN "1010110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001";
WHEN "1010111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110";
WHEN "1011000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111";
WHEN "1011001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001";
WHEN "1011010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110";
WHEN "1011011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101";
WHEN "1011100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001";
WHEN "1011101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101";
WHEN "1011110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011";
WHEN "1011111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001";
WHEN "1100000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010";
WHEN "1100001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111";
WHEN "1100010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010";
WHEN "1100011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111";
WHEN "1100100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010";
WHEN "1100101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000";
WHEN "1100110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011";
WHEN "1100111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001";
WHEN "1101000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101";
WHEN "1101001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100";
WHEN "1101010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111";
WHEN "1101011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000";
WHEN "1101100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101";
WHEN "1101101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101";
WHEN "1101110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101";
WHEN "1101111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011";
WHEN "1110000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100";
WHEN "1110001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011";
WHEN "1110010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111";
WHEN "1110011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011";
WHEN "1110100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001";
WHEN "1110101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111";
WHEN "1110110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101";
WHEN "1110111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111";
WHEN "1111000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001";
WHEN "1111001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100";
WHEN "1111010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011";
WHEN "1111011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011";
WHEN "1111100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011";
WHEN "1111101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011";
WHEN "1111110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001";
WHEN "1111111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101";
WHEN OTHERS =>
memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid245_sinPiZPolyEval(CONSTANT,244)
rndBit_uid245_sinPiZPolyEval_q <= "01";
--cIncludingRoundingBit_uid246_sinPiZPolyEval(BITJOIN,245)@19
cIncludingRoundingBit_uid246_sinPiZPolyEval_q <= memoryC2_uid227_sinPiZTableGenerator_q & rndBit_uid245_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0(REG,381)@19
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid246_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts3_uid247_sinPiZPolyEval(ADD,246)@20
ts3_uid247_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q);
ts3_uid247_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q(36)) & reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q);
ts3_uid247_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid247_sinPiZPolyEval_a) + SIGNED(ts3_uid247_sinPiZPolyEval_b));
ts3_uid247_sinPiZPolyEval_q <= ts3_uid247_sinPiZPolyEval_o(45 downto 0);
--s3_uid248_sinPiZPolyEval(BITSELECT,247)@20
s3_uid248_sinPiZPolyEval_in <= ts3_uid247_sinPiZPolyEval_q;
s3_uid248_sinPiZPolyEval_b <= s3_uid248_sinPiZPolyEval_in(45 downto 1);
--yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval(BITSELECT,285)@20
yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in <= s3_uid248_sinPiZPolyEval_b;
yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in(44 downto 18);
--reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9(REG,382)@20
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor(LOGICAL,1055)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top(CONSTANT,1051)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp(LOGICAL,1052)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg(REG,1053)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena(REG,1056)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd(LOGICAL,1057)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg(REG,1048)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux(MUX,1049)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem(DUALMEM,1046)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 13,
width_b => 45,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg(DELAY,1045)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--yT4_uid249_sinPiZPolyEval(BITSELECT,248)@21
yT4_uid249_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q;
yT4_uid249_sinPiZPolyEval_b <= yT4_uid249_sinPiZPolyEval_in(44 downto 2);
--xBottomBits_uid289_pT4_uid250_sinPiZPolyEval(BITSELECT,288)@21
xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in <= yT4_uid249_sinPiZPolyEval_b(15 downto 0);
xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b <= xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in(15 downto 0);
--pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval(BITJOIN,290)@21
pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q <= xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid288_pT4_uid250_sinPiZPolyEval(BITSELECT,287)@20
yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in <= s3_uid248_sinPiZPolyEval_b(17 downto 0);
yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b <= yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in(17 downto 0);
--ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a(DELAY,699)@20
ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b, xout => ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval(BITJOIN,289)@21
spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q;
--pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval(BITJOIN,291)@21
pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q <= spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6(REG,383)@21
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a(DELAY,693)@21
ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid249_sinPiZPolyEval_b, xout => ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval(BITSELECT,284)@22
xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in <= ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q;
xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b <= xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in(42 downto 16);
--multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma(CHAINMULTADD,345)@22
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(0),56);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(1),56);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b),28));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q),28));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q),27));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q),27));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(0),55));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval(BITSELECT,293)@25
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q;
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in(54 downto 8);
--highBBits_uid296_pT4_uid250_sinPiZPolyEval(BITSELECT,295)@25
highBBits_uid296_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b;
highBBits_uid296_pT4_uid250_sinPiZPolyEval_b <= highBBits_uid296_pT4_uid250_sinPiZPolyEval_in(46 downto 18);
--reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1(REG,385)@25
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q <= highBBits_uid296_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1(REG,384)@20
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b(DELAY,696)@21
ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q, clk => clk, aclr => areset );
--topProd_uid287_pT4_uid250_sinPiZPolyEval(MULT,286)@22
topProd_uid287_pT4_uid250_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid287_pT4_uid250_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid287_pT4_uid250_sinPiZPolyEval_b);
topProd_uid287_pT4_uid250_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_a <= (others => '0');
topProd_uid287_pT4_uid250_sinPiZPolyEval_b <= (others => '0');
topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_a <= xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b;
topProd_uid287_pT4_uid250_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q;
topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid287_pT4_uid250_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid287_pT4_uid250_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_q <= topProd_uid287_pT4_uid250_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0(REG,386)@25
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q <= topProd_uid287_pT4_uid250_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid297_pT4_uid250_sinPiZPolyEval(ADD,296)@26
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q(53)) & reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q);
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q);
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b));
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q <= sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid295_pT4_uid250_sinPiZPolyEval(BITSELECT,294)@25
lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b(17 downto 0);
lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b <= lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in(17 downto 0);
--ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a(DELAY,707)@25
ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b, xout => ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid295_uid298_pT4_uid250_sinPiZPolyEval(BITJOIN,297)@26
add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q <= sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q & ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q;
--R_uid299_pT4_uid250_sinPiZPolyEval(BITSELECT,298)@26
R_uid299_pT4_uid250_sinPiZPolyEval_in <= add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q(71 downto 0);
R_uid299_pT4_uid250_sinPiZPolyEval_b <= R_uid299_pT4_uid250_sinPiZPolyEval_in(71 downto 26);
--reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1(REG,387)@26
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q <= R_uid299_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor(LOGICAL,1003)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top(CONSTANT,999)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q <= "010010";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp(LOGICAL,1000)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg(REG,1001)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena(REG,1004)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd(LOGICAL,1005)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,995)
-- every=1, low=0, high=18, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i = 17 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i - 18;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i,5));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg(REG,996)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux(MUX,997)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem(DUALMEM,994)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 19,
width_b => 7,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg(DELAY,993)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC1_uid226_sinPiZTableGenerator(LOOKUP,225)@26
memoryC1_uid226_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC1_uid226_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110";
WHEN "0000001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011";
WHEN "0000010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110";
WHEN "0000011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110";
WHEN "0000100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011";
WHEN "0000101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100";
WHEN "0000110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000";
WHEN "0000111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010";
WHEN "0001000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111";
WHEN "0001001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110";
WHEN "0001010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101";
WHEN "0001011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101";
WHEN "0001100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001";
WHEN "0001101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110";
WHEN "0001110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100";
WHEN "0001111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111";
WHEN "0010000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000";
WHEN "0010001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100";
WHEN "0010010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010";
WHEN "0010011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010";
WHEN "0010100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100";
WHEN "0010101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100";
WHEN "0010110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000";
WHEN "0010111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000";
WHEN "0011000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110";
WHEN "0011001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010";
WHEN "0011010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100";
WHEN "0011011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000";
WHEN "0011100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010";
WHEN "0011101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110";
WHEN "0011110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010";
WHEN "0011111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010";
WHEN "0100000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001";
WHEN "0100001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101";
WHEN "0100010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011";
WHEN "0100011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000";
WHEN "0100100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111";
WHEN "0100101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001";
WHEN "0100110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110";
WHEN "0100111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001";
WHEN "0101000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000";
WHEN "0101001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001";
WHEN "0101010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001";
WHEN "0101011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110";
WHEN "0101100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110";
WHEN "0101101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000";
WHEN "0101110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100";
WHEN "0101111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011";
WHEN "0110000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100";
WHEN "0110001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101";
WHEN "0110010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001";
WHEN "0110011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010";
WHEN "0110100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100";
WHEN "0110101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111";
WHEN "0110110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111";
WHEN "0110111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000";
WHEN "0111000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100";
WHEN "0111001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111";
WHEN "0111010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111";
WHEN "0111011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111";
WHEN "0111100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011";
WHEN "0111101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011";
WHEN "0111110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010";
WHEN "0111111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101";
WHEN "1000000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101";
WHEN "1000001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010";
WHEN "1000010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001";
WHEN "1000011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111";
WHEN "1000100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011";
WHEN "1000101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001";
WHEN "1000110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100";
WHEN "1000111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001";
WHEN "1001000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011";
WHEN "1001001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010";
WHEN "1001010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101";
WHEN "1001011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100";
WHEN "1001100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010";
WHEN "1001101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001";
WHEN "1001110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000";
WHEN "1001111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100";
WHEN "1010000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100";
WHEN "1010001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010";
WHEN "1010010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101";
WHEN "1010011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111";
WHEN "1010100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010";
WHEN "1010101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101";
WHEN "1010110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101";
WHEN "1010111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011";
WHEN "1011000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101";
WHEN "1011001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010";
WHEN "1011010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001";
WHEN "1011011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001";
WHEN "1011100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100";
WHEN "1011101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011";
WHEN "1011110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100";
WHEN "1011111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101";
WHEN "1100000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000";
WHEN "1100001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011";
WHEN "1100010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011";
WHEN "1100011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001";
WHEN "1100100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101";
WHEN "1100101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000";
WHEN "1100110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111";
WHEN "1100111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010";
WHEN "1101000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010";
WHEN "1101001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110";
WHEN "1101010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011";
WHEN "1101011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110";
WHEN "1101100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101";
WHEN "1101101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010";
WHEN "1101110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110";
WHEN "1101111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110";
WHEN "1110000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100";
WHEN "1110001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100";
WHEN "1110010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000";
WHEN "1110011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001";
WHEN "1110100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001";
WHEN "1110101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101";
WHEN "1110110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011";
WHEN "1110111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001";
WHEN "1111000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011";
WHEN "1111001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111";
WHEN "1111010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101";
WHEN "1111011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110";
WHEN "1111100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010";
WHEN "1111101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110";
WHEN "1111110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001";
WHEN "1111111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111";
WHEN OTHERS =>
memoryC1_uid226_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110";
END CASE;
-- End reserved scope level
END PROCESS;
--cIncludingRoundingBit_uid252_sinPiZPolyEval(BITJOIN,251)@26
cIncludingRoundingBit_uid252_sinPiZPolyEval_q <= memoryC1_uid226_sinPiZTableGenerator_q & rndBit_uid245_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0(REG,388)@26
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid252_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts4_uid253_sinPiZPolyEval(ADD,252)@27
ts4_uid253_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q);
ts4_uid253_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q(45)) & reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q);
ts4_uid253_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid253_sinPiZPolyEval_a) + SIGNED(ts4_uid253_sinPiZPolyEval_b));
ts4_uid253_sinPiZPolyEval_q <= ts4_uid253_sinPiZPolyEval_o(52 downto 0);
--s4_uid254_sinPiZPolyEval(BITSELECT,253)@27
s4_uid254_sinPiZPolyEval_in <= ts4_uid253_sinPiZPolyEval_q;
s4_uid254_sinPiZPolyEval_b <= s4_uid254_sinPiZPolyEval_in(52 downto 1);
--yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval(BITSELECT,300)@27
yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in <= s4_uid254_sinPiZPolyEval_b;
yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in(51 downto 25);
--reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9(REG,389)@27
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor(LOGICAL,1092)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top(CONSTANT,1088)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q <= "010011";
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp(LOGICAL,1089)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg(REG,1090)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena(REG,1093)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd(LOGICAL,1094)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b <= VCC_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b;
--xBottomBits_uid304_pT5_uid256_sinPiZPolyEval(BITSELECT,303)@6
xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b(17 downto 0);
xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b <= xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in(17 downto 0);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1084)
-- every=1, low=0, high=19, step=1, init=1
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i - 19;
ELSE
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg(REG,1085)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux(MUX,1086)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem(DUALMEM,1083)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 5,
numwords_a => 20,
width_b => 18,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq(17 downto 0);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg(DELAY,1082)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset );
--pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval(BITJOIN,305)@28
pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid303_pT5_uid256_sinPiZPolyEval(BITSELECT,302)@27
yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in <= s4_uid254_sinPiZPolyEval_b(24 downto 0);
yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b <= yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in(24 downto 0);
--ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a(DELAY,716)@27
ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b, xout => ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval(BITJOIN,304)@28
spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q;
--pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval(BITJOIN,306)@28
pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q <= spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q & GND_q;
--reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6(REG,390)@28
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor(LOGICAL,1079)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top(CONSTANT,1075)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q <= "010100";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp(LOGICAL,1076)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg(REG,1077)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena(REG,1080)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd(LOGICAL,1081)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1071)
-- every=1, low=0, high=20, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i - 20;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i,5));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg(REG,1072)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux(MUX,1073)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem(DUALMEM,1070)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 5,
numwords_a => 21,
width_b => 45,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg(DELAY,1069)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval(BITSELECT,299)@29
xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q;
xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b <= xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in(44 downto 18);
--multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma(CHAINMULTADD,346)@29
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(0),56);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(1),56);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b),28));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q),28));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q),27));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q),27));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(0),55));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval(BITSELECT,308)@32
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q;
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in(54 downto 1);
--highBBits_uid311_pT5_uid256_sinPiZPolyEval(BITSELECT,310)@32
highBBits_uid311_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b;
highBBits_uid311_pT5_uid256_sinPiZPolyEval_b <= highBBits_uid311_pT5_uid256_sinPiZPolyEval_in(53 downto 25);
--reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1(REG,392)@32
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q <= highBBits_uid311_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1(REG,391)@27
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b(DELAY,713)@28
ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q, clk => clk, aclr => areset );
--topProd_uid302_pT5_uid256_sinPiZPolyEval(MULT,301)@29
topProd_uid302_pT5_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid302_pT5_uid256_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid302_pT5_uid256_sinPiZPolyEval_b);
topProd_uid302_pT5_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_a <= (others => '0');
topProd_uid302_pT5_uid256_sinPiZPolyEval_b <= (others => '0');
topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_a <= xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b;
topProd_uid302_pT5_uid256_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q;
topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid302_pT5_uid256_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid302_pT5_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_q <= topProd_uid302_pT5_uid256_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0(REG,393)@32
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q <= topProd_uid302_pT5_uid256_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid312_pT5_uid256_sinPiZPolyEval(ADD,311)@33
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q(53)) & reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q);
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q);
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b));
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q <= sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid310_pT5_uid256_sinPiZPolyEval(BITSELECT,309)@32
lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b(24 downto 0);
lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b <= lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in(24 downto 0);
--ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a(DELAY,724)@32
ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b, xout => ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid310_uid313_pT5_uid256_sinPiZPolyEval(BITJOIN,312)@33
add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q <= sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q & ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q;
--R_uid314_pT5_uid256_sinPiZPolyEval(BITSELECT,313)@33
R_uid314_pT5_uid256_sinPiZPolyEval_in <= add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q(78 downto 0);
R_uid314_pT5_uid256_sinPiZPolyEval_b <= R_uid314_pT5_uid256_sinPiZPolyEval_in(78 downto 25);
--reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1(REG,394)@33
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q <= R_uid314_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor(LOGICAL,990)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top(CONSTANT,986)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q <= "011001";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp(LOGICAL,987)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg(REG,988)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena(REG,991)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd(LOGICAL,992)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,982)
-- every=1, low=0, high=25, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i = 24 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i - 25;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i,5));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg(REG,983)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux(MUX,984)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem(DUALMEM,981)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 26,
width_b => 7,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg(DELAY,980)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC0_uid225_sinPiZTableGenerator(LOOKUP,224)@33
memoryC0_uid225_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000";
WHEN "0000001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010";
WHEN "0000010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100";
WHEN "0000011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001";
WHEN "0000100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010";
WHEN "0000101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101";
WHEN "0000110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101";
WHEN "0000111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101";
WHEN "0001000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010";
WHEN "0001001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101";
WHEN "0001010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010";
WHEN "0001011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111";
WHEN "0001100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010";
WHEN "0001101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110";
WHEN "0001110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110";
WHEN "0001111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111";
WHEN "0010000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111";
WHEN "0010001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100";
WHEN "0010010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111";
WHEN "0010011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000";
WHEN "0010100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110";
WHEN "0010101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100";
WHEN "0010110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110";
WHEN "0010111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011";
WHEN "0011000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111";
WHEN "0011001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011";
WHEN "0011010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001";
WHEN "0011011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101";
WHEN "0011100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111";
WHEN "0011101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001";
WHEN "0011110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111";
WHEN "0011111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001";
WHEN "0100000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001";
WHEN "0100001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100";
WHEN "0100010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110";
WHEN "0100011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000";
WHEN "0100100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100";
WHEN "0100101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111";
WHEN "0100110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010";
WHEN "0100111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101";
WHEN "0101000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100";
WHEN "0101001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111";
WHEN "0101010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101";
WHEN "0101011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000";
WHEN "0101100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111";
WHEN "0101101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010";
WHEN "0101110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111";
WHEN "0101111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110";
WHEN "0110000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101";
WHEN "0110001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111";
WHEN "0110010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101";
WHEN "0110011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101";
WHEN "0110100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010";
WHEN "0110101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001";
WHEN "0110110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011";
WHEN "0110111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111";
WHEN "0111000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101";
WHEN "0111001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110";
WHEN "0111010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111";
WHEN "0111011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100";
WHEN "0111100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101";
WHEN "0111101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101";
WHEN "0111110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011";
WHEN "0111111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110";
WHEN "1000000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101";
WHEN "1000001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001";
WHEN "1000010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101";
WHEN "1000011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110";
WHEN "1000100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011";
WHEN "1000101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101";
WHEN "1000110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111";
WHEN "1000111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111";
WHEN "1001000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001";
WHEN "1001001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001";
WHEN "1001010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010";
WHEN "1001011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010";
WHEN "1001100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100";
WHEN "1001101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110";
WHEN "1001110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011";
WHEN "1001111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101";
WHEN "1010000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110";
WHEN "1010001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111";
WHEN "1010010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001";
WHEN "1010011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001";
WHEN "1010100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100";
WHEN "1010101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010";
WHEN "1010110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000";
WHEN "1010111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110";
WHEN "1011000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000";
WHEN "1011001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000";
WHEN "1011010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110";
WHEN "1011011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101";
WHEN "1011100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000";
WHEN "1011101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110";
WHEN "1011110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101";
WHEN "1011111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010";
WHEN "1100000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000";
WHEN "1100001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111";
WHEN "1100010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001";
WHEN "1100011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000";
WHEN "1100100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110";
WHEN "1100101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001";
WHEN "1100110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001";
WHEN "1100111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010";
WHEN "1101000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101";
WHEN "1101001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110";
WHEN "1101010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011";
WHEN "1101011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100";
WHEN "1101100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001";
WHEN "1101101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100";
WHEN "1101110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111";
WHEN "1101111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101";
WHEN "1110000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010";
WHEN "1110001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101";
WHEN "1110010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111";
WHEN "1110011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001";
WHEN "1110100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000";
WHEN "1110101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101";
WHEN "1110110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011";
WHEN "1110111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100";
WHEN "1111000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110";
WHEN "1111001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001";
WHEN "1111010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011";
WHEN "1111011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001";
WHEN "1111100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110";
WHEN "1111101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010";
WHEN "1111110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111";
WHEN "1111111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011";
WHEN OTHERS =>
memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid257_sinPiZPolyEval(CONSTANT,256)
rndBit_uid257_sinPiZPolyEval_q <= "001";
--cIncludingRoundingBit_uid258_sinPiZPolyEval(BITJOIN,257)@33
cIncludingRoundingBit_uid258_sinPiZPolyEval_q <= memoryC0_uid225_sinPiZTableGenerator_q & rndBit_uid257_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0(REG,395)@33
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid258_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts5_uid259_sinPiZPolyEval(ADD,258)@34
ts5_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q);
ts5_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q(53)) & reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q);
ts5_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid259_sinPiZPolyEval_a) + SIGNED(ts5_uid259_sinPiZPolyEval_b));
ts5_uid259_sinPiZPolyEval_q <= ts5_uid259_sinPiZPolyEval_o(61 downto 0);
--s5_uid260_sinPiZPolyEval(BITSELECT,259)@34
s5_uid260_sinPiZPolyEval_in <= ts5_uid259_sinPiZPolyEval_q;
s5_uid260_sinPiZPolyEval_b <= s5_uid260_sinPiZPolyEval_in(61 downto 1);
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@34
fxpSinRes_uid67_fpCosPiTest_in <= s5_uid260_sinPiZPolyEval_b(58 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(58 downto 5);
--mul2xSinRes_uid68_fpCosPiTest_b_1(BITSELECT,317)@34
mul2xSinRes_uid68_fpCosPiTest_b_1_in <= fxpSinRes_uid67_fpCosPiTest_b;
mul2xSinRes_uid68_fpCosPiTest_b_1_b <= mul2xSinRes_uid68_fpCosPiTest_b_1_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1(REG,400)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_1_b;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor(LOGICAL,877)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q <= not (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a or ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b);
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top(CONSTANT,873)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q <= "010110";
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp(LOGICAL,874)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q <= "1" when ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a = ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b else "0";
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg(REG,875)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena(REG,878)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q = "1") THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd(LOGICAL,879)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b <= VCC_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a and ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b;
--LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest(BITSELECT,219)@9
LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q(77 downto 0);
LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in(77 downto 0);
--leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest(BITJOIN,220)@9
leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b & GND_q;
--LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest(BITSELECT,214)@9
LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(72 downto 0);
LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in(72 downto 0);
--leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest(BITJOIN,215)@9
leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest(BITSELECT,211)@9
LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest(BITJOIN,212)@9
leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest(BITSELECT,208)@9
LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(76 downto 0);
LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in(76 downto 0);
--leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest(BITJOIN,209)@9
leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest(BITSELECT,203)@9
LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(54 downto 0);
LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in(54 downto 0);
--leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest(BITJOIN,204)@9
leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest(BITSELECT,200)@9
LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in(62 downto 0);
--leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest(BITJOIN,201)@9
leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest(BITSELECT,197)@9
LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(70 downto 0);
LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in(70 downto 0);
--leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest(BITJOIN,198)@9
leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor(LOGICAL,954)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q <= not (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a or ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top(CONSTANT,950)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q <= "010";
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp(LOGICAL,951)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a = ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg(REG,952)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena(REG,955)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd(LOGICAL,956)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a and ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b;
--vStage_uid148_lzcZ_uid58_fpCosPiTest(BITSELECT,147)@5
vStage_uid148_lzcZ_uid58_fpCosPiTest_in <= z_uid56_fpCosPiTest_b(14 downto 0);
vStage_uid148_lzcZ_uid58_fpCosPiTest_b <= vStage_uid148_lzcZ_uid58_fpCosPiTest_in(14 downto 0);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,946)
-- every=1, low=0, high=2, step=1, init=1
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i = 1 THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i - 2;
ELSE
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i,2));
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg(REG,947)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux(MUX,948)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s, ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q, ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem(DUALMEM,957)
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia <= vStage_uid148_lzcZ_uid58_fpCosPiTest_b;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 2,
numwords_a => 3,
width_b => 15,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq(14 downto 0);
--leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest(BITJOIN,192)@9
leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q <= ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
--X46dto0_uid189_alignedZ_uid59_fpCosPiTest(BITSELECT,188)@5
X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in <= z_uid56_fpCosPiTest_b(46 downto 0);
X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b <= X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in(46 downto 0);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem(DUALMEM,945)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia <= X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 47,
widthad_a => 2,
numwords_a => 3,
width_b => 47,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq(46 downto 0);
--leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest(BITJOIN,189)@9
leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem(DUALMEM,970)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia <= z_uid56_fpCosPiTest_b;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 79,
widthad_a => 1,
numwords_a => 2,
width_b => 79,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq(78 downto 0);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg(DELAY,969)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q, xout => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q, clk => clk, aclr => areset );
--rVStage_uid145_lzcZ_uid58_fpCosPiTest(BITSELECT,144)@5
rVStage_uid145_lzcZ_uid58_fpCosPiTest_in <= z_uid56_fpCosPiTest_b;
rVStage_uid145_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_in(78 downto 15);
--vCount_uid146_lzcZ_uid58_fpCosPiTest(LOGICAL,145)@5
vCount_uid146_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_b;
vCount_uid146_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
vCount_uid146_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid146_lzcZ_uid58_fpCosPiTest_a = vCount_uid146_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g(DELAY,595)@5
ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid146_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q, clk => clk, aclr => areset );
--mO_uid147_lzcZ_uid58_fpCosPiTest(CONSTANT,146)
mO_uid147_lzcZ_uid58_fpCosPiTest_q <= "1111111111111111111111111111111111111111111111111";
--cStage_uid149_lzcZ_uid58_fpCosPiTest(BITJOIN,148)@5
cStage_uid149_lzcZ_uid58_fpCosPiTest_q <= vStage_uid148_lzcZ_uid58_fpCosPiTest_b & mO_uid147_lzcZ_uid58_fpCosPiTest_q;
--vStagei_uid151_lzcZ_uid58_fpCosPiTest(MUX,150)@5
vStagei_uid151_lzcZ_uid58_fpCosPiTest_s <= vCount_uid146_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid151_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid151_lzcZ_uid58_fpCosPiTest_s, rVStage_uid145_lzcZ_uid58_fpCosPiTest_b, cStage_uid149_lzcZ_uid58_fpCosPiTest_q)
BEGIN
CASE vStagei_uid151_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= cStage_uid149_lzcZ_uid58_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid153_lzcZ_uid58_fpCosPiTest(BITSELECT,152)@5
rVStage_uid153_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid151_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid153_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid153_lzcZ_uid58_fpCosPiTest_in(63 downto 32);
--reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0(REG,364)@5
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q <= "00000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid153_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid154_lzcZ_uid58_fpCosPiTest(LOGICAL,153)@6
vCount_uid154_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid154_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
vCount_uid154_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid154_lzcZ_uid58_fpCosPiTest_a = vCount_uid154_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f(DELAY,594)@6
ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid154_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q, clk => clk, aclr => areset );
--vStage_uid155_lzcZ_uid58_fpCosPiTest(BITSELECT,154)@5
vStage_uid155_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid151_lzcZ_uid58_fpCosPiTest_q(31 downto 0);
vStage_uid155_lzcZ_uid58_fpCosPiTest_b <= vStage_uid155_lzcZ_uid58_fpCosPiTest_in(31 downto 0);
--ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d(DELAY,562)@5
ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid155_lzcZ_uid58_fpCosPiTest_b, xout => ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q, clk => clk, aclr => areset );
--ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c(DELAY,561)@5
ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid153_lzcZ_uid58_fpCosPiTest_b, xout => ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid157_lzcZ_uid58_fpCosPiTest(MUX,156)@6
vStagei_uid157_lzcZ_uid58_fpCosPiTest_s <= vCount_uid154_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid157_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid157_lzcZ_uid58_fpCosPiTest_s, ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q, ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q)
BEGIN
CASE vStagei_uid157_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q;
WHEN OTHERS => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid159_lzcZ_uid58_fpCosPiTest(BITSELECT,158)@6
rVStage_uid159_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid157_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid159_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid159_lzcZ_uid58_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0(REG,365)@6
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q <= "0000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid159_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid160_lzcZ_uid58_fpCosPiTest(LOGICAL,159)@7
vCount_uid160_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid160_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
vCount_uid160_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid160_lzcZ_uid58_fpCosPiTest_a = vCount_uid160_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e(DELAY,593)@7
ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid160_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q, clk => clk, aclr => areset );
--vStage_uid161_lzcZ_uid58_fpCosPiTest(BITSELECT,160)@6
vStage_uid161_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid157_lzcZ_uid58_fpCosPiTest_q(15 downto 0);
vStage_uid161_lzcZ_uid58_fpCosPiTest_b <= vStage_uid161_lzcZ_uid58_fpCosPiTest_in(15 downto 0);
--ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d(DELAY,568)@6
ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => vStage_uid161_lzcZ_uid58_fpCosPiTest_b, xout => ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q, clk => clk, aclr => areset );
--ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c(DELAY,567)@6
ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => rVStage_uid159_lzcZ_uid58_fpCosPiTest_b, xout => ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid163_lzcZ_uid58_fpCosPiTest(MUX,162)@7
vStagei_uid163_lzcZ_uid58_fpCosPiTest_s <= vCount_uid160_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid163_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid163_lzcZ_uid58_fpCosPiTest_s, ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q, ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q)
BEGIN
CASE vStagei_uid163_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q;
WHEN OTHERS => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid165_lzcZ_uid58_fpCosPiTest(BITSELECT,164)@7
rVStage_uid165_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid163_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid165_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0(REG,366)@7
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid166_lzcZ_uid58_fpCosPiTest(LOGICAL,165)@8
vCount_uid166_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid166_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
vCount_uid166_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid166_lzcZ_uid58_fpCosPiTest_a = vCount_uid166_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid167_lzcZ_uid58_fpCosPiTest(BITSELECT,166)@7
vStage_uid167_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid163_lzcZ_uid58_fpCosPiTest_q(7 downto 0);
vStage_uid167_lzcZ_uid58_fpCosPiTest_b <= vStage_uid167_lzcZ_uid58_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3(REG,367)@7
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q <= vStage_uid167_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2(REG,368)@7
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vStagei_uid169_lzcZ_uid58_fpCosPiTest(MUX,168)@8
vStagei_uid169_lzcZ_uid58_fpCosPiTest_s <= vCount_uid166_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid169_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid169_lzcZ_uid58_fpCosPiTest_s, reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q, reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid169_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid171_lzcZ_uid58_fpCosPiTest(BITSELECT,170)@8
rVStage_uid171_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid169_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid171_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_in(7 downto 4);
--vCount_uid172_lzcZ_uid58_fpCosPiTest(LOGICAL,171)@8
vCount_uid172_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_b;
vCount_uid172_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
vCount_uid172_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid172_lzcZ_uid58_fpCosPiTest_a = vCount_uid172_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid173_lzcZ_uid58_fpCosPiTest(BITSELECT,172)@8
vStage_uid173_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid169_lzcZ_uid58_fpCosPiTest_q(3 downto 0);
vStage_uid173_lzcZ_uid58_fpCosPiTest_b <= vStage_uid173_lzcZ_uid58_fpCosPiTest_in(3 downto 0);
--vStagei_uid175_lzcZ_uid58_fpCosPiTest(MUX,174)@8
vStagei_uid175_lzcZ_uid58_fpCosPiTest_s <= vCount_uid172_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid175_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid175_lzcZ_uid58_fpCosPiTest_s, rVStage_uid171_lzcZ_uid58_fpCosPiTest_b, vStage_uid173_lzcZ_uid58_fpCosPiTest_b)
BEGIN
CASE vStagei_uid175_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= vStage_uid173_lzcZ_uid58_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid177_lzcZ_uid58_fpCosPiTest(BITSELECT,176)@8
rVStage_uid177_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid175_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid177_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_in(3 downto 2);
--vCount_uid178_lzcZ_uid58_fpCosPiTest(LOGICAL,177)@8
vCount_uid178_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_b;
vCount_uid178_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
vCount_uid178_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid178_lzcZ_uid58_fpCosPiTest_a = vCount_uid178_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid179_lzcZ_uid58_fpCosPiTest(BITSELECT,178)@8
vStage_uid179_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid175_lzcZ_uid58_fpCosPiTest_q(1 downto 0);
vStage_uid179_lzcZ_uid58_fpCosPiTest_b <= vStage_uid179_lzcZ_uid58_fpCosPiTest_in(1 downto 0);
--vStagei_uid181_lzcZ_uid58_fpCosPiTest(MUX,180)@8
vStagei_uid181_lzcZ_uid58_fpCosPiTest_s <= vCount_uid178_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid181_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid181_lzcZ_uid58_fpCosPiTest_s, rVStage_uid177_lzcZ_uid58_fpCosPiTest_b, vStage_uid179_lzcZ_uid58_fpCosPiTest_b)
BEGIN
CASE vStagei_uid181_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= vStage_uid179_lzcZ_uid58_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid183_lzcZ_uid58_fpCosPiTest(BITSELECT,182)@8
rVStage_uid183_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid181_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid183_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid183_lzcZ_uid58_fpCosPiTest_in(1 downto 1);
--vCount_uid184_lzcZ_uid58_fpCosPiTest(LOGICAL,183)@8
vCount_uid184_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid183_lzcZ_uid58_fpCosPiTest_b;
vCount_uid184_lzcZ_uid58_fpCosPiTest_b <= GND_q;
vCount_uid184_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid184_lzcZ_uid58_fpCosPiTest_a = vCount_uid184_lzcZ_uid58_fpCosPiTest_b else "0";
--r_uid185_lzcZ_uid58_fpCosPiTest(BITJOIN,184)@8
r_uid185_lzcZ_uid58_fpCosPiTest_q <= ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q & ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q & ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q & vCount_uid166_lzcZ_uid58_fpCosPiTest_q & vCount_uid172_lzcZ_uid58_fpCosPiTest_q & vCount_uid178_lzcZ_uid58_fpCosPiTest_q & vCount_uid184_lzcZ_uid58_fpCosPiTest_q;
--leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest(BITSELECT,194)@8
leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q;
leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in(6 downto 5);
--reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1(REG,369)@8
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest(MUX,195)@9
leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q, leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q, leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q;
WHEN "01" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= cstZwSwF_uid16_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest(BITSELECT,205)@8
leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1(REG,370)@8
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest(MUX,206)@9
leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s, leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q;
WHEN "01" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest(BITSELECT,216)@8
leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1(REG,371)@8
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest(MUX,217)@9
leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s, leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest(BITSELECT,221)@8
leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in(0 downto 0);
--reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1(REG,372)@8
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest(MUX,222)@9
leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s, leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q, leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s IS
WHEN "0" => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q;
WHEN "1" => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg(DELAY,869)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q, xout => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q, clk => clk, aclr => areset );
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg(REG,872)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=22, step=1, init=1
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i = 21 THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i - 22;
ELSE
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i,5));
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem(DUALMEM,870)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 79,
widthad_a => 5,
numwords_a => 23,
width_b => 79,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q(0),
clocken0 => VCC_q(0),
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq,
address_a => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa,
data_a => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia
);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq(78 downto 0);
--alignedZLow_uid60_fpCosPiTest(BITSELECT,59)@34
alignedZLow_uid60_fpCosPiTest_in <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q;
alignedZLow_uid60_fpCosPiTest_b <= alignedZLow_uid60_fpCosPiTest_in(78 downto 26);
--mul2xSinRes_uid68_fpCosPiTest_a_1(BITSELECT,315)@34
mul2xSinRes_uid68_fpCosPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & alignedZLow_uid60_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_a_1_b <= mul2xSinRes_uid68_fpCosPiTest_a_1_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0(REG,401)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a1_b1(MULT,321)@35
mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b1_b);
mul2xSinRes_uid68_fpCosPiTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b1_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b1_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_q <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1(BITSELECT,328)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1(REG,402)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a_0(BITSELECT,314)@34
mul2xSinRes_uid68_fpCosPiTest_a_0_in <= alignedZLow_uid60_fpCosPiTest_b(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_a_0_b <= mul2xSinRes_uid68_fpCosPiTest_a_0_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0(REG,403)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_0_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a0_b1(MULT,320)@35
mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b1_b);
mul2xSinRes_uid68_fpCosPiTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b1_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b1_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_q <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1(BITSELECT,326)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_zero_36(CONSTANT,331)
mul2xSinRes_uid68_fpCosPiTest_zero_36_q <= "000000000000000000000000000";
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2(BITJOIN,335)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q <= mul2xSinRes_uid68_fpCosPiTest_zero_36_q & mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b & mul2xSinRes_uid68_fpCosPiTest_zero_36_q;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1(BITSELECT,327)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_b_0(BITSELECT,316)@34
mul2xSinRes_uid68_fpCosPiTest_b_0_in <= fxpSinRes_uid67_fpCosPiTest_b(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_b_0_b <= mul2xSinRes_uid68_fpCosPiTest_b_0_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1(REG,398)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_0_b;
END IF;
END PROCESS;
--reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0(REG,399)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a1_b0(MULT,319)@35
mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b0_b);
mul2xSinRes_uid68_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b0_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b0_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_q <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0(BITSELECT,324)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1(BITJOIN,334)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q <= mul2xSinRes_uid68_fpCosPiTest_zero_36_q & mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b & mul2xSinRes_uid68_fpCosPiTest_zero_36_q;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC(LOGICAL,339)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1(BITSELECT,329)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0(BITSELECT,325)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1(REG,396)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_0_b;
END IF;
END PROCESS;
--reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0(REG,397)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_0_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a0_b0(MULT,318)@35
mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b0_b);
mul2xSinRes_uid68_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b0_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b0_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_q <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0(BITSELECT,323)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0(BITSELECT,322)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0(BITJOIN,333)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b & mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b & mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC(LOGICAL,338)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB(LOGICAL,337)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne(LOGICAL,340)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a or mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b or mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c;
--mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS(BITSELECT,341)@38
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q(106 downto 0);
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in(106 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ(BITJOIN,342)@38
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b & GND_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b(BITJOIN,349)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b(BITSELECT,352)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in(88 downto 0);
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in(108 downto 89);
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne(LOGICAL,336)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a(BITJOIN,347)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a(BITSELECT,351)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in(88 downto 0);
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in(108 downto 89);
--mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2(ADD,353)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin <= GND_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b) & '1';
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin(0);
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b));
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o(90);
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o(89 downto 1);
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b(DELAY,788)@38
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b : dspba_delay
GENERIC MAP ( width => 20, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset );
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a(DELAY,787)@38
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a : dspba_delay
GENERIC MAP ( width => 20, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset );
--mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2(ADD,354)@39
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c;
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q) & '1';
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin(0);
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b));
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o(20 downto 1);
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a(DELAY,790)@39
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a : dspba_delay
GENERIC MAP ( width => 89, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset );
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q(BITJOIN,355)@40
mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@40
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(106 downto 0);
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(106 downto 106);
--ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c(DELAY,462)@40
ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => normBit_uid69_fpCosPiTest_b, xout => ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q, clk => clk, aclr => areset );
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000";
--rndExpUpdate_uid74_uid75_fpCosPiTest(BITJOIN,74)@41
rndExpUpdate_uid74_uid75_fpCosPiTest_q <= ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,890)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,886)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "011100";
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,887)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,888)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,891)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,892)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,404)@8
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid185_lzcZ_uid58_fpCosPiTest_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,882)
-- every=1, low=0, high=28, step=1, init=1
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i = 27 THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i - 28;
ELSE
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,5));
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,883)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,884)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,881)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 29,
width_b => 7,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(6 downto 0);
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg(DELAY,880)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q, xout => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q, clk => clk, aclr => areset );
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111111110";
--expHardCase_uid61_fpCosPiTest(SUB,60)@40
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000" & ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(11 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@40
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(10 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(10 downto 0);
--highRes_uid70_fpCosPiTest(BITSELECT,69)@40
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(105 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(105 downto 53);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@40
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(104 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(104 downto 52);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@40
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@40
expFracPreRnd_uid73_uid73_fpCosPiTest_q <= expP_uid62_fpCosPiTest_b & fracRCompPreRnd_uid72_fpCosPiTest_q;
--reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0(REG,405)@40
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q <= expFracPreRnd_uid73_uid73_fpCosPiTest_q;
END IF;
END PROCESS;
--expFracComp_uid76_fpCosPiTest(ADD,75)@41
expFracComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q);
expFracComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid74_uid75_fpCosPiTest_q);
expFracComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid76_fpCosPiTest_a) + UNSIGNED(expFracComp_uid76_fpCosPiTest_b));
expFracComp_uid76_fpCosPiTest_q <= expFracComp_uid76_fpCosPiTest_o(64 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@41
expRComp_uid78_fpCosPiTest_in <= expFracComp_uid76_fpCosPiTest_q(63 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(63 downto 53);
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor(LOGICAL,929)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q <= not (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a or ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b);
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top(CONSTANT,925)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q <= "0100100";
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp(LOGICAL,926)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q <= "1" when ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a = ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b else "0";
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg(REG,927)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena(REG,930)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q = "1") THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd(LOGICAL,931)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a and ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b;
--fracXIsZero_uid28_fpCosPiTest(LOGICAL,27)@0
fracXIsZero_uid28_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid28_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid28_fpCosPiTest_q <= "1" when fracXIsZero_uid28_fpCosPiTest_a = fracXIsZero_uid28_fpCosPiTest_b else "0";
--InvFracXIsZero_uid30_fpCosPiTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpCosPiTest_a <= fracXIsZero_uid28_fpCosPiTest_q;
InvFracXIsZero_uid30_fpCosPiTest_q <= not InvFracXIsZero_uid30_fpCosPiTest_a;
--expXIsMax_uid26_fpCosPiTest(LOGICAL,25)@0
expXIsMax_uid26_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid26_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid26_fpCosPiTest_q <= "1" when expXIsMax_uid26_fpCosPiTest_a = expXIsMax_uid26_fpCosPiTest_b else "0";
--And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest(LOGICAL,30)@0
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a <= expXIsMax_uid26_fpCosPiTest_q;
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b <= InvFracXIsZero_uid30_fpCosPiTest_q;
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b;
--InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest(LOGICAL,31)@0
InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q;
InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a;
--And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a <= expXIsMax_uid26_fpCosPiTest_q;
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b <= fracXIsZero_uid28_fpCosPiTest_q;
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a and And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b;
--InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q;
InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a;
--expXIsZero_uid24_fpCosPiTest(LOGICAL,23)@0
expXIsZero_uid24_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid24_fpCosPiTest_b <= cstAllZWE_uid22_fpCosPiTest_q;
expXIsZero_uid24_fpCosPiTest_q <= "1" when expXIsZero_uid24_fpCosPiTest_a = expXIsZero_uid24_fpCosPiTest_b else "0";
--InvExpXIsZero_uid34_fpCosPiTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpCosPiTest_a <= expXIsZero_uid24_fpCosPiTest_q;
InvExpXIsZero_uid34_fpCosPiTest_q <= not InvExpXIsZero_uid34_fpCosPiTest_a;
--And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest(LOGICAL,34)@0
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a <= InvExpXIsZero_uid34_fpCosPiTest_q;
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q;
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b;
--And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest(LOGICAL,35)@0
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q;
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q;
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a(DELAY,472)@1
ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q, xout => ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q, clk => clk, aclr => areset );
--xIsHalf_uid85_fpCosPiTest(LOGICAL,84)@2
xIsHalf_uid85_fpCosPiTest_a <= ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q;
xIsHalf_uid85_fpCosPiTest_b <= fxpXFracHalf_uid48_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_c <= InvCosXIsOne_uid79_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_d <= InvXEvenInt_uid83_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_q <= xIsHalf_uid85_fpCosPiTest_a and xIsHalf_uid85_fpCosPiTest_b and xIsHalf_uid85_fpCosPiTest_c and xIsHalf_uid85_fpCosPiTest_d;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg(DELAY,919)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xIsHalf_uid85_fpCosPiTest_q, xout => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt(COUNTER,921)
-- every=1, low=0, high=36, step=1, init=1
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i = 35 THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i - 36;
ELSE
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i,6));
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg(REG,922)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux(MUX,923)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux: PROCESS (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s, ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q, ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem(DUALMEM,920)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 37,
width_b => 1,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq,
address_a => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa,
data_a => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia
);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--expRPostExc1_uid93_fpCosPiTest(MUX,92)@41
expRPostExc1_uid93_fpCosPiTest_s <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q;
expRPostExc1_uid93_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid93_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE expRPostExc1_uid93_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid93_fpCosPiTest_q <= expRComp_uid78_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid93_fpCosPiTest_q <= cstAllZWE_uid22_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid93_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor(LOGICAL,1105)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q <= not (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a or ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b);
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top(CONSTANT,1101)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q <= "0100011";
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp(LOGICAL,1102)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q <= "1" when ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a = ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b else "0";
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg(REG,1103)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena(REG,1106)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd(LOGICAL,1107)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b <= VCC_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a and ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b;
--ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a(DELAY,481)@0
ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOne_uid38_fpCosPiTest_c, xout => ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q, clk => clk, aclr => areset );
--ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d(DELAY,484)@0
ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => expXIsZero_uid24_fpCosPiTest_q, xout => ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q, clk => clk, aclr => areset );
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0(REG,358)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--fxpXFracZero_uid47_fpCosPiTest(LOGICAL,46)@2
fxpXFracZero_uid47_fpCosPiTest_a <= reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q;
fxpXFracZero_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid16_fpCosPiTest_q);
fxpXFracZero_uid47_fpCosPiTest_q <= "1" when fxpXFracZero_uid47_fpCosPiTest_a = fxpXFracZero_uid47_fpCosPiTest_b else "0";
--And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@2
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a <= fxpXFracZero_uid47_fpCosPiTest_q;
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b <= InvCosXIsOne_uid79_fpCosPiTest_q;
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q <= And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a and And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b;
--Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest(LOGICAL,80)@2
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a <= ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q;
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b <= And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q;
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q <= Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a or Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b;
--xIsInt_uid82_fpCosPiTest(LOGICAL,81)@2
xIsInt_uid82_fpCosPiTest_a <= ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q;
xIsInt_uid82_fpCosPiTest_b <= Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q;
xIsInt_uid82_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xIsInt_uid82_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
xIsInt_uid82_fpCosPiTest_q <= xIsInt_uid82_fpCosPiTest_a and xIsInt_uid82_fpCosPiTest_b;
END IF;
END PROCESS;
--or_uid95_fpCosPiTest(LOGICAL,94)@3
or_uid95_fpCosPiTest_a <= xIsInt_uid82_fpCosPiTest_q;
or_uid95_fpCosPiTest_b <= ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q;
or_uid95_fpCosPiTest_c <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q;
or_uid95_fpCosPiTest_q <= or_uid95_fpCosPiTest_a or or_uid95_fpCosPiTest_b or or_uid95_fpCosPiTest_c;
--excRNaN_uid86_fpCosPiTest(LOGICAL,85)@0
excRNaN_uid86_fpCosPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q;
excRNaN_uid86_fpCosPiTest_b <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q;
excRNaN_uid86_fpCosPiTest_q <= excRNaN_uid86_fpCosPiTest_a or excRNaN_uid86_fpCosPiTest_b;
--Or2ZeroExcRNaN_uid94_fpCosPiTest(LOGICAL,93)@0
Or2ZeroExcRNaN_uid94_fpCosPiTest_a <= GND_q;
Or2ZeroExcRNaN_uid94_fpCosPiTest_b <= excRNaN_uid86_fpCosPiTest_q;
Or2ZeroExcRNaN_uid94_fpCosPiTest_q <= Or2ZeroExcRNaN_uid94_fpCosPiTest_a or Or2ZeroExcRNaN_uid94_fpCosPiTest_b;
--ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a(DELAY,496)@0
ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => Or2ZeroExcRNaN_uid94_fpCosPiTest_q, xout => ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q, clk => clk, aclr => areset );
--join_uid96_fpCosPiTest(BITJOIN,95)@3
join_uid96_fpCosPiTest_q <= or_uid95_fpCosPiTest_q & ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt(COUNTER,1097)
-- every=1, low=0, high=35, step=1, init=1
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i = 34 THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i - 35;
ELSE
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i,6));
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg(REG,1098)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux(MUX,1099)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s <= VCC_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s, ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q, ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem(DUALMEM,1096)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia <= join_uid96_fpCosPiTest_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 6,
numwords_a => 36,
width_b => 2,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg(DELAY,1095)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q, xout => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q, clk => clk, aclr => areset );
--reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1(REG,406)@41
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q;
END IF;
END PROCESS;
--expRPostExc_uid97_fpCosPiTest(MUX,96)@42
expRPostExc_uid97_fpCosPiTest_s <= reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q;
expRPostExc_uid97_fpCosPiTest: PROCESS (expRPostExc_uid97_fpCosPiTest_s, expRPostExc1_uid93_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid97_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid97_fpCosPiTest_q <= expRPostExc1_uid93_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid97_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid97_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid97_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid97_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid89_fpCosPiTest(CONSTANT,88)
oneFracRPostExc2_uid89_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@41
fracRComp_uid77_fpCosPiTest_in <= expFracComp_uid76_fpCosPiTest_q(52 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(52 downto 1);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor(LOGICAL,903)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q <= not (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a or ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top(CONSTANT,899)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q <= "0100010";
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp(LOGICAL,900)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q <= "1" when ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a = ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b else "0";
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg(REG,901)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena(REG,904)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q = "1") THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd(LOGICAL,905)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a and ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b;
--reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4(REG,360)@2
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q <= xIsHalf_uid85_fpCosPiTest_q;
END IF;
END PROCESS;
--ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c(DELAY,483)@2
ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid48_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q, clk => clk, aclr => areset );
--or_uid87_fpCosPiTest(LOGICAL,86)@3
or_uid87_fpCosPiTest_a <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q;
or_uid87_fpCosPiTest_b <= xIsInt_uid82_fpCosPiTest_q;
or_uid87_fpCosPiTest_c <= ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q;
or_uid87_fpCosPiTest_d <= ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q;
or_uid87_fpCosPiTest_e <= reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q;
or_uid87_fpCosPiTest_f <= GND_q;
or_uid87_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
or_uid87_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
or_uid87_fpCosPiTest_q <= or_uid87_fpCosPiTest_a or or_uid87_fpCosPiTest_b or or_uid87_fpCosPiTest_c or or_uid87_fpCosPiTest_d or or_uid87_fpCosPiTest_e or or_uid87_fpCosPiTest_f;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt(COUNTER,895)
-- every=1, low=0, high=34, step=1, init=1
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i = 33 THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i - 34;
ELSE
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i,6));
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg(REG,896)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux(MUX,897)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux: PROCESS (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s, ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q, ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem(DUALMEM,894)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia <= or_uid87_fpCosPiTest_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 35,
width_b => 1,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq,
address_a => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa,
data_a => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia
);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg(DELAY,893)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q, xout => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q, clk => clk, aclr => areset );
--fracRPostExc1_uid88_fpCosPiTest(MUX,87)@41
fracRPostExc1_uid88_fpCosPiTest_s <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q;
fracRPostExc1_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid88_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE fracRPostExc1_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid88_fpCosPiTest_q <= fracRComp_uid77_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid88_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_nor(LOGICAL,853)
ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b);
--ld_xIn_v_to_xOut_v_mem_top(CONSTANT,849)
ld_xIn_v_to_xOut_v_mem_top_q <= "0100111";
--ld_xIn_v_to_xOut_v_cmp(LOGICAL,850)
ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q;
ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q);
ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0";
--ld_xIn_v_to_xOut_v_cmpReg(REG,851)
ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_sticky_ena(REG,854)
ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,855)
ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q;
ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b;
--ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,906)
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid86_fpCosPiTest_q, xout => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,845)
-- every=1, low=0, high=39, step=1, init=1
ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39;
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6));
--ld_xIn_v_to_xOut_v_replace_rdreg(REG,846)
ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_replace_rdmux(MUX,847)
ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q;
ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q)
BEGIN
CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS
WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,907)
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--fracRPostExc_uid90_fpCosPiTest(MUX,89)@42
fracRPostExc_uid90_fpCosPiTest_s <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
fracRPostExc_uid90_fpCosPiTest: PROCESS (fracRPostExc_uid90_fpCosPiTest_s, fracRPostExc1_uid88_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid90_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid90_fpCosPiTest_q <= fracRPostExc1_uid88_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid90_fpCosPiTest_q <= oneFracRPostExc2_uid89_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid104_fpCosPiTest(BITJOIN,103)@42
R_uid104_fpCosPiTest_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q & expRPostExc_uid97_fpCosPiTest_q & fracRPostExc_uid90_fpCosPiTest_q;
--ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,857)
ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset;
ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c;
ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 40,
width_b => 8,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_c_to_xOut_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_c_to_xOut_c_replace_mem_iq,
address_a => ld_xIn_c_to_xOut_c_replace_mem_aa,
data_a => ld_xIn_c_to_xOut_c_replace_mem_ia
);
ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0);
--ld_xIn_c_to_xOut_c_outputreg(DELAY,856)
ld_xIn_c_to_xOut_c_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,844)
ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset;
ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v;
ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_v_to_xOut_v_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_v_to_xOut_v_replace_mem_iq,
address_a => ld_xIn_v_to_xOut_v_replace_mem_aa,
data_a => ld_xIn_v_to_xOut_v_replace_mem_ia
);
ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0);
--ld_xIn_v_to_xOut_v_outputreg(DELAY,843)
ld_xIn_v_to_xOut_v_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset );
--xOut(PORTOUT,4)@42
xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q;
xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q;
xOut_0 <= R_uid104_fpCosPiTest_q;
end normal;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_divfp1x.vhd
|
10
|
20532
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVFP1X.VHD ***
--*** ***
--*** Function: Internal format single divide - ***
--*** unsigned mantissa ***
--*** ***
--*** Uses new multiplier based divider core ***
--*** from floating point library ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output, sign bug ***
--*** 11/08/09 - add divider interface output ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 13 (X) ***
--*** Latency = 13 (M) ***
--*** Latency = 13 (D) ***
--*** Latency = 13 + roundconvert (ieee) ***
--***************************************************
ENTITY hcc_divfp1x IS
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_divfp1x;
ARCHITECTURE rtl OF hcc_divfp1x IS
-- latency = 13 + ieeeoutput*roundconvert
type divexpfftype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (24 DOWNTO 1);
-- multiplier core interface
signal divinaaman, divinbbman : STD_LOGIC_VECTOR(mantissa DOWNTO 1);
signal divinaaexp, divinbbexp : STD_LOGIC_VECTOR(10 DOWNTO 1);
signal divinaaexpff, divinbbexpff : STD_LOGIC_VECTOR(10 DOWNTO 1);
signal divinaasat, divinaazip, divinaanan : STD_LOGIC;
signal divinbbsat, divinbbzip, divinbbnan : STD_LOGIC;
signal divinaasatff, divinaazipff, divinaananff : STD_LOGIC;
signal divinbbsatff, divinbbzipff, divinbbnanff : STD_LOGIC;
signal divinaasign, divinbbsign : STD_LOGIC;
signal divinaasignff, divinbbsignff : STD_LOGIC;
signal divsignff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal divsatff, divzipff, divnanff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal divexpff : divexpfftype;
signal dividend, divisor : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal divmannode : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- output section (x out)
signal signeddivmannode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divxmanff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divxexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal divxsatff, divxzipff, divxnanff : STD_LOGIC;
-- output section (mult out)
signal normalizemult : STD_LOGIC;
signal normmultnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal signedmultnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divmultmanff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divmultexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal divmultsatff, divmultzipff, divmultnanff : STD_LOGIC;
-- output section (div out)
signal normalizediv : STD_LOGIC;
signal normdivnode : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal divdivsignff : STD_LOGIC;
signal divdivmanff : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal divdivexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal divdivsatff, divdivzipff, divdivnanff : STD_LOGIC;
-- output section (ieeeout)
signal normalize : STD_LOGIC;
signal normmannode : STD_LOGIC_VECTOR (25 DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal ccmanff : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal ccexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal divexpminus : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccsignff, ccsatff, cczipff, ccnanff, ccoverff : STD_LOGIC;
signal manoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal ccexpplus : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expmax, expzero : STD_LOGIC;
signal manoutzero, manoutmax, expoutzero, expoutmax : STD_LOGIC;
-- Signals to convert division format to mult format
signal aaxor : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal bbxor : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- 12 latency
component fp_div_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dividend : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: IF (ieeeoutput = 1) GENERATE
gzb: FOR k IN 1 TO 24 GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT THE SIGN BIT IS PACKED IN THE MSB OF ***
--*** THE MANTISSA ***
--********************************************************
aaxor <= (others => aa(mantissa+10));
bbxor <= (others => bb(mantissa+10));
divinaaman <= (aa(mantissa+9 DOWNTO 11) & '0') XOR aaxor;
divinaaexp <= aa(10 DOWNTO 1);
divinbbman <= (bb(mantissa+9 DOWNTO 11) & '0') XOR bbxor;
divinbbexp <= bb(10 DOWNTO 1);
divinaasat <= aasat;
divinbbsat <= bbsat;
divinaazip <= aazip;
divinbbzip <= bbzip;
divinaanan <= aanan;
divinbbnan <= bbnan;
-- signbits packed in MSB of mantissas
divinaasign <= aa(mantissa+10);
divinbbsign <= bb(mantissa+10);
--**************************************************
--*** ***
--*** Divider Section ***
--*** ***
--**************************************************
gdda: IF (mantissa = 32) GENERATE
dividend <= divinaaman & "0000";
divisor <= divinbbman & "0000";
END GENERATE;
gddb: IF (mantissa = 36) GENERATE
dividend <= divinaaman;
divisor <= divinbbman;
END GENERATE;
-- 12 latency
div: fp_div_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dividend=>dividend,divisor=>divisor,
quotient=>divmannode);
-- 12 pipes here : 1 input stage, so 11 stages left
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 10 LOOP
divinaaexpff(k) <= '0';
divinbbexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
FOR j IN 1 TO 10 LOOP
divexpff(k)(j) <= '0';
END LOOP;
END LOOP;
divinaasignff <= '0';
divinbbsignff <= '0';
divinaasatff <= '0';
divinbbsatff <= '0';
divinaazipff <= '0';
divinbbzipff <= '0';
divinaananff <= '0';
divinbbnanff <= '0';
FOR k IN 1 TO 11 LOOP
divsignff(k) <= '0';
divsatff(k) <= '0';
divzipff(k) <= '0';
divnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divinaaexpff <= divinaaexp;
divinbbexpff <= divinbbexp;
divexpff(1)(10 DOWNTO 1) <= divinaaexpff - divinbbexpff;
divexpff(2)(10 DOWNTO 1) <= divexpff(1)(10 DOWNTO 1) + "0001111111";
FOR k IN 3 TO 11 LOOP
divexpff(k)(10 DOWNTO 1) <= divexpff(k-1)(10 DOWNTO 1);
END LOOP;
divinaasignff <= divinaasign;
divinbbsignff <= divinbbsign;
divsignff(1) <= divinaasignff XOR divinbbsignff;
FOR k IN 2 TO 11 LOOP
divsignff(k) <= divsignff(k-1);
END LOOP;
divinaasatff <= divinaasat;
divinbbsatff <= divinbbsat;
divinaazipff <= divinaazip;
divinbbzipff <= divinbbzip;
divinaananff <= divinaanan;
divinbbnanff <= divinbbnan;
-- special condition: infinity = x/0
divsatff(1) <= (divinaasatff OR divinbbsatff) OR
(NOT(divinaazipff) AND divinbbzipff);
divzipff(1) <= divinaazipff;
-- 0/0 or infinity/infinity is invalid OP, NAN out
divnanff(1) <= divinaananff OR divinbbnanff OR
(divinaazipff AND divinbbzipff) OR
(divinaasatff AND divinbbsatff);
FOR k IN 2 TO 11 LOOP
divsatff(k) <= divsatff(k-1);
divzipff(k) <= divzipff(k-1);
divnanff(k) <= divnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goxa: IF (xoutput = 1) GENERATE
goxb: FOR k IN 1 TO mantissa-5 GENERATE
signeddivmannode(k) <= divmannode(36-mantissa+5+k) XOR divsignff(11);
END GENERATE;
goxc: FOR k IN mantissa-4 TO mantissa GENERATE
signeddivmannode(k) <= divsignff(11);
END GENERATE;
pox: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
divxmanff(k) <= '0';
END LOOP;
divxexpff <= "0000000000";
divxsatff <= '0';
divxzipff <= '0';
divxnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divxmanff <= signeddivmannode;
divxexpff(10 DOWNTO 1) <= divexpff(11)(10 DOWNTO 1);
divxsatff <= divsatff(11);
divxzipff <= divzipff(11);
divxnanff <= divnanff(11);
END IF;
END IF;
END PROCESS;
cc(mantissa+10 DOWNTO 11) <= divxmanff;
cc(10 DOWNTO 1) <= divxexpff(10 DOWNTO 1);
ccsat <= divxsatff;
cczip <= divxzipff;
ccnan <= divxnanff;
END GENERATE;
--*********************************
--*** multiplier format output ***
--*********************************
gofa: IF (multoutput = 1) GENERATE
-- output either "01XXX" (0.5 < x < 1) or "1XXX" (1 < x < 2), normalize to "01XXX"
-- this is opposite direction to divider normalization
normalizemult <= NOT(divmannode(36));
goeb: FOR k IN 1 TO mantissa-1 GENERATE -- includes leading '1' and round bit
normmultnode(k) <= (divmannode(36-mantissa+k) AND normalizemult) OR
(divmannode(37-mantissa+k) AND NOT(normalizemult));
END GENERATE;
normmultnode(mantissa) <= '0';
goec: FOR k IN 1 TO mantissa GENERATE
signedmultnode(k) <= normmultnode(k) XOR divsignff(11);
END GENERATE;
pof: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
divmultmanff(k) <= '0';
END LOOP;
divmultexpff <= "0000000000";
divmultsatff <= '0';
divmultzipff <= '0';
divmultnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divmultmanff <= signedmultnode + divsignff(11);
divmultexpff(10 DOWNTO 1) <= divexpff(11)(10 DOWNTO 1) - normalizemult;
divmultsatff <= divsatff(11);
divmultzipff <= divzipff(11);
divmultnanff <= divnanff(11);
END IF;
END IF;
END PROCESS;
cc(mantissa+10 DOWNTO 11) <= divmultmanff;
cc(10 DOWNTO 1) <= divmultexpff(10 DOWNTO 1);
ccsat <= divmultsatff;
cczip <= divmultzipff;
ccnan <= divmultnanff;
END GENERATE;
--******************************
--*** divider format output ***
--******************************
goda: IF (divoutput = 1) GENERATE
-- output either "01XXX" (0.5 < x < 1) or "1XXX" (1 < x < 2), normalize to "1XXX"
normalizediv <= NOT(divmannode(36));
godb: FOR k IN 1 TO mantissa-1 GENERATE -- includes leading '1' and round bit
normdivnode(k) <= (divmannode(36-mantissa+k) AND normalizediv) OR
(divmannode(37-mantissa+k) AND NOT(normalizediv));
END GENERATE;
pof: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
divdivsignff <= '0';
FOR k IN 1 TO mantissa-1 LOOP
divdivmanff(k) <= '0';
END LOOP;
divdivexpff <= "0000000000";
divdivsatff <= '0';
divdivzipff <= '0';
divdivnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divdivsignff <= divsignff(11);
divdivmanff <= normdivnode;
divdivexpff(10 DOWNTO 1) <= divexpff(11)(10 DOWNTO 1) - normalizediv;
divdivsatff <= divsatff(11);
divdivzipff <= divzipff(11);
divdivnanff <= divnanff(11);
END IF;
END IF;
END PROCESS;
cc(mantissa+10) <= divdivsignff;
cc(mantissa+9 DOWNTO 11) <= divdivmanff;
cc(10 DOWNTO 1) <= divdivexpff(10 DOWNTO 1);
ccsat <= divdivsatff;
cczip <= divdivzipff;
ccnan <= divdivnanff;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "01XXX" (0.5 < x < 1) or "1XXX" (1 < x < 2), normalize to "1XXX"
normalize <= NOT(divmannode(36));
goeb: FOR k IN 1 TO 25 GENERATE -- includes leading '1' and round bit
normmannode(k) <= (divmannode(k+11) AND NOT(normalize)) OR
(divmannode(k+10) AND normalize);
END GENERATE;
-- always round, need
goec: IF (roundconvert = 0) GENERATE
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
signoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= (normmannode(k+1) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (divexpminus(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
signoutff <= divsignff(11);
END IF;
END IF;
END PROCESS;
divexpminus <= divexpff(11)(10 DOWNTO 1) - ("000000000" & normalize);
-- both '1' when true
expmax <= divexpminus(8) AND divexpminus(7) AND divexpminus(6) AND divexpminus(5) AND
divexpminus(4) AND divexpminus(3) AND divexpminus(2) AND divexpminus(1);
expzero <= NOT(divexpminus(8) OR divexpminus(7) OR divexpminus(6) OR divexpminus(5) OR
divexpminus(4) OR divexpminus(3) OR divexpminus(2) OR divexpminus(1));
-- any special condition turns mantissa zero
manoutzero <= divsatff(11) OR divzipff(11) OR expmax OR expzero OR
divexpminus(10) OR divexpminus(9);
manoutmax <= divnanff(11);
expoutzero <= divzipff(11) OR expzero OR divexpminus(10);
-- 12/05/09 - make sure ccexpminus = -1 doesnt create infinity
expoutmax <= (expmax AND NOT(divexpminus(9)) AND NOT(divexpminus(10))) OR
(divexpminus(9) AND NOT(divexpminus(10))) OR divnanff(11);
END GENERATE;
goed: IF (roundconvert = 1) GENERATE
manoverflow(1) <= normmannode(1);
gva: FOR k IN 2 TO 24 GENERATE
manoverflow(k) <= manoverflow(k-1) AND normmannode(k);
END GENERATE;
poeb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 24 LOOP
ccmanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
ccexpff(k) <= '0';
END LOOP;
ccsignff <= '0';
ccsatff <= '0';
cczipff <= '0';
ccnanff <= '0';
ccoverff <= '0';
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
signoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccmanff <= normmannode(25 DOWNTO 2) + (zerovec(23 DOWNTO 1) & normmannode(1));
ccexpff(10 DOWNTO 1) <= divexpff(11)(10 DOWNTO 1) - ("000000000" & normalize);
ccsignff <= divsignff(11);
ccsatff <= divsatff(11);
cczipff <= divzipff(11);
ccnanff <= divnanff(11);
ccoverff <= manoverflow(23);
FOR k IN 1 TO 23 LOOP
manoutff(k) <= (ccmanff(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (ccexpplus(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
signoutff <= ccsignff;
END IF;
END IF;
END PROCESS;
ccexpplus <= ccexpff + ("000000000" & ccoverff);
-- both '1' when true
expmax <= ccexpplus(8) AND ccexpplus(7) AND ccexpplus(6) AND ccexpplus(5) AND
ccexpplus(4) AND ccexpplus(3) AND ccexpplus(2) AND ccexpplus(1);
expzero <= NOT(ccexpplus(8) OR ccexpplus(7) OR ccexpplus(6) OR ccexpplus(5) OR
ccexpplus(4) OR ccexpplus(3) OR ccexpplus(2) OR ccexpplus(1));
-- any special condition turns mantissa zero
manoutzero <= ccsatff OR cczipff OR expmax OR expzero OR
ccexpplus(10) OR ccexpplus(9);
manoutmax <= ccnanff;
expoutzero <= cczipff OR expzero OR ccexpplus(10);
-- 12/05/09 - make sure ccexpplus = -1 doesnt create infinity
expoutmax <= (expmax AND NOT(ccexpplus(9)) AND NOT(ccexpplus(10))) OR
(ccexpplus(9) AND NOT(ccexpplus(10))) OR ccnanff;
END GENERATE;
cc(32) <= signoutff;
cc(31 DOWNTO 24) <= expoutff;
cc(23 DOWNTO 1) <= manoutff;
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_divfp1x.vhd
|
10
|
20532
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVFP1X.VHD ***
--*** ***
--*** Function: Internal format single divide - ***
--*** unsigned mantissa ***
--*** ***
--*** Uses new multiplier based divider core ***
--*** from floating point library ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 22/04/09 - added NAN support, IEEE NAN ***
--*** output, sign bug ***
--*** 11/08/09 - add divider interface output ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 13 (X) ***
--*** Latency = 13 (M) ***
--*** Latency = 13 (D) ***
--*** Latency = 13 + roundconvert (ieee) ***
--***************************************************
ENTITY hcc_divfp1x IS
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_divfp1x;
ARCHITECTURE rtl OF hcc_divfp1x IS
-- latency = 13 + ieeeoutput*roundconvert
type divexpfftype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (24 DOWNTO 1);
-- multiplier core interface
signal divinaaman, divinbbman : STD_LOGIC_VECTOR(mantissa DOWNTO 1);
signal divinaaexp, divinbbexp : STD_LOGIC_VECTOR(10 DOWNTO 1);
signal divinaaexpff, divinbbexpff : STD_LOGIC_VECTOR(10 DOWNTO 1);
signal divinaasat, divinaazip, divinaanan : STD_LOGIC;
signal divinbbsat, divinbbzip, divinbbnan : STD_LOGIC;
signal divinaasatff, divinaazipff, divinaananff : STD_LOGIC;
signal divinbbsatff, divinbbzipff, divinbbnanff : STD_LOGIC;
signal divinaasign, divinbbsign : STD_LOGIC;
signal divinaasignff, divinbbsignff : STD_LOGIC;
signal divsignff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal divsatff, divzipff, divnanff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal divexpff : divexpfftype;
signal dividend, divisor : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal divmannode : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- output section (x out)
signal signeddivmannode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divxmanff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divxexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal divxsatff, divxzipff, divxnanff : STD_LOGIC;
-- output section (mult out)
signal normalizemult : STD_LOGIC;
signal normmultnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal signedmultnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divmultmanff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal divmultexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal divmultsatff, divmultzipff, divmultnanff : STD_LOGIC;
-- output section (div out)
signal normalizediv : STD_LOGIC;
signal normdivnode : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal divdivsignff : STD_LOGIC;
signal divdivmanff : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal divdivexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal divdivsatff, divdivzipff, divdivnanff : STD_LOGIC;
-- output section (ieeeout)
signal normalize : STD_LOGIC;
signal normmannode : STD_LOGIC_VECTOR (25 DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal ccmanff : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal ccexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal divexpminus : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal ccsignff, ccsatff, cczipff, ccnanff, ccoverff : STD_LOGIC;
signal manoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal ccexpplus : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expmax, expzero : STD_LOGIC;
signal manoutzero, manoutmax, expoutzero, expoutmax : STD_LOGIC;
-- Signals to convert division format to mult format
signal aaxor : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal bbxor : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
-- 12 latency
component fp_div_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dividend : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: IF (ieeeoutput = 1) GENERATE
gzb: FOR k IN 1 TO 24 GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT THE SIGN BIT IS PACKED IN THE MSB OF ***
--*** THE MANTISSA ***
--********************************************************
aaxor <= (others => aa(mantissa+10));
bbxor <= (others => bb(mantissa+10));
divinaaman <= (aa(mantissa+9 DOWNTO 11) & '0') XOR aaxor;
divinaaexp <= aa(10 DOWNTO 1);
divinbbman <= (bb(mantissa+9 DOWNTO 11) & '0') XOR bbxor;
divinbbexp <= bb(10 DOWNTO 1);
divinaasat <= aasat;
divinbbsat <= bbsat;
divinaazip <= aazip;
divinbbzip <= bbzip;
divinaanan <= aanan;
divinbbnan <= bbnan;
-- signbits packed in MSB of mantissas
divinaasign <= aa(mantissa+10);
divinbbsign <= bb(mantissa+10);
--**************************************************
--*** ***
--*** Divider Section ***
--*** ***
--**************************************************
gdda: IF (mantissa = 32) GENERATE
dividend <= divinaaman & "0000";
divisor <= divinbbman & "0000";
END GENERATE;
gddb: IF (mantissa = 36) GENERATE
dividend <= divinaaman;
divisor <= divinbbman;
END GENERATE;
-- 12 latency
div: fp_div_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dividend=>dividend,divisor=>divisor,
quotient=>divmannode);
-- 12 pipes here : 1 input stage, so 11 stages left
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 10 LOOP
divinaaexpff(k) <= '0';
divinbbexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
FOR j IN 1 TO 10 LOOP
divexpff(k)(j) <= '0';
END LOOP;
END LOOP;
divinaasignff <= '0';
divinbbsignff <= '0';
divinaasatff <= '0';
divinbbsatff <= '0';
divinaazipff <= '0';
divinbbzipff <= '0';
divinaananff <= '0';
divinbbnanff <= '0';
FOR k IN 1 TO 11 LOOP
divsignff(k) <= '0';
divsatff(k) <= '0';
divzipff(k) <= '0';
divnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divinaaexpff <= divinaaexp;
divinbbexpff <= divinbbexp;
divexpff(1)(10 DOWNTO 1) <= divinaaexpff - divinbbexpff;
divexpff(2)(10 DOWNTO 1) <= divexpff(1)(10 DOWNTO 1) + "0001111111";
FOR k IN 3 TO 11 LOOP
divexpff(k)(10 DOWNTO 1) <= divexpff(k-1)(10 DOWNTO 1);
END LOOP;
divinaasignff <= divinaasign;
divinbbsignff <= divinbbsign;
divsignff(1) <= divinaasignff XOR divinbbsignff;
FOR k IN 2 TO 11 LOOP
divsignff(k) <= divsignff(k-1);
END LOOP;
divinaasatff <= divinaasat;
divinbbsatff <= divinbbsat;
divinaazipff <= divinaazip;
divinbbzipff <= divinbbzip;
divinaananff <= divinaanan;
divinbbnanff <= divinbbnan;
-- special condition: infinity = x/0
divsatff(1) <= (divinaasatff OR divinbbsatff) OR
(NOT(divinaazipff) AND divinbbzipff);
divzipff(1) <= divinaazipff;
-- 0/0 or infinity/infinity is invalid OP, NAN out
divnanff(1) <= divinaananff OR divinbbnanff OR
(divinaazipff AND divinbbzipff) OR
(divinaasatff AND divinbbsatff);
FOR k IN 2 TO 11 LOOP
divsatff(k) <= divsatff(k-1);
divzipff(k) <= divzipff(k-1);
divnanff(k) <= divnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goxa: IF (xoutput = 1) GENERATE
goxb: FOR k IN 1 TO mantissa-5 GENERATE
signeddivmannode(k) <= divmannode(36-mantissa+5+k) XOR divsignff(11);
END GENERATE;
goxc: FOR k IN mantissa-4 TO mantissa GENERATE
signeddivmannode(k) <= divsignff(11);
END GENERATE;
pox: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
divxmanff(k) <= '0';
END LOOP;
divxexpff <= "0000000000";
divxsatff <= '0';
divxzipff <= '0';
divxnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divxmanff <= signeddivmannode;
divxexpff(10 DOWNTO 1) <= divexpff(11)(10 DOWNTO 1);
divxsatff <= divsatff(11);
divxzipff <= divzipff(11);
divxnanff <= divnanff(11);
END IF;
END IF;
END PROCESS;
cc(mantissa+10 DOWNTO 11) <= divxmanff;
cc(10 DOWNTO 1) <= divxexpff(10 DOWNTO 1);
ccsat <= divxsatff;
cczip <= divxzipff;
ccnan <= divxnanff;
END GENERATE;
--*********************************
--*** multiplier format output ***
--*********************************
gofa: IF (multoutput = 1) GENERATE
-- output either "01XXX" (0.5 < x < 1) or "1XXX" (1 < x < 2), normalize to "01XXX"
-- this is opposite direction to divider normalization
normalizemult <= NOT(divmannode(36));
goeb: FOR k IN 1 TO mantissa-1 GENERATE -- includes leading '1' and round bit
normmultnode(k) <= (divmannode(36-mantissa+k) AND normalizemult) OR
(divmannode(37-mantissa+k) AND NOT(normalizemult));
END GENERATE;
normmultnode(mantissa) <= '0';
goec: FOR k IN 1 TO mantissa GENERATE
signedmultnode(k) <= normmultnode(k) XOR divsignff(11);
END GENERATE;
pof: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
divmultmanff(k) <= '0';
END LOOP;
divmultexpff <= "0000000000";
divmultsatff <= '0';
divmultzipff <= '0';
divmultnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divmultmanff <= signedmultnode + divsignff(11);
divmultexpff(10 DOWNTO 1) <= divexpff(11)(10 DOWNTO 1) - normalizemult;
divmultsatff <= divsatff(11);
divmultzipff <= divzipff(11);
divmultnanff <= divnanff(11);
END IF;
END IF;
END PROCESS;
cc(mantissa+10 DOWNTO 11) <= divmultmanff;
cc(10 DOWNTO 1) <= divmultexpff(10 DOWNTO 1);
ccsat <= divmultsatff;
cczip <= divmultzipff;
ccnan <= divmultnanff;
END GENERATE;
--******************************
--*** divider format output ***
--******************************
goda: IF (divoutput = 1) GENERATE
-- output either "01XXX" (0.5 < x < 1) or "1XXX" (1 < x < 2), normalize to "1XXX"
normalizediv <= NOT(divmannode(36));
godb: FOR k IN 1 TO mantissa-1 GENERATE -- includes leading '1' and round bit
normdivnode(k) <= (divmannode(36-mantissa+k) AND normalizediv) OR
(divmannode(37-mantissa+k) AND NOT(normalizediv));
END GENERATE;
pof: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
divdivsignff <= '0';
FOR k IN 1 TO mantissa-1 LOOP
divdivmanff(k) <= '0';
END LOOP;
divdivexpff <= "0000000000";
divdivsatff <= '0';
divdivzipff <= '0';
divdivnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divdivsignff <= divsignff(11);
divdivmanff <= normdivnode;
divdivexpff(10 DOWNTO 1) <= divexpff(11)(10 DOWNTO 1) - normalizediv;
divdivsatff <= divsatff(11);
divdivzipff <= divzipff(11);
divdivnanff <= divnanff(11);
END IF;
END IF;
END PROCESS;
cc(mantissa+10) <= divdivsignff;
cc(mantissa+9 DOWNTO 11) <= divdivmanff;
cc(10 DOWNTO 1) <= divdivexpff(10 DOWNTO 1);
ccsat <= divdivsatff;
cczip <= divdivzipff;
ccnan <= divdivnanff;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "01XXX" (0.5 < x < 1) or "1XXX" (1 < x < 2), normalize to "1XXX"
normalize <= NOT(divmannode(36));
goeb: FOR k IN 1 TO 25 GENERATE -- includes leading '1' and round bit
normmannode(k) <= (divmannode(k+11) AND NOT(normalize)) OR
(divmannode(k+10) AND normalize);
END GENERATE;
-- always round, need
goec: IF (roundconvert = 0) GENERATE
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
signoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= (normmannode(k+1) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (divexpminus(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
signoutff <= divsignff(11);
END IF;
END IF;
END PROCESS;
divexpminus <= divexpff(11)(10 DOWNTO 1) - ("000000000" & normalize);
-- both '1' when true
expmax <= divexpminus(8) AND divexpminus(7) AND divexpminus(6) AND divexpminus(5) AND
divexpminus(4) AND divexpminus(3) AND divexpminus(2) AND divexpminus(1);
expzero <= NOT(divexpminus(8) OR divexpminus(7) OR divexpminus(6) OR divexpminus(5) OR
divexpminus(4) OR divexpminus(3) OR divexpminus(2) OR divexpminus(1));
-- any special condition turns mantissa zero
manoutzero <= divsatff(11) OR divzipff(11) OR expmax OR expzero OR
divexpminus(10) OR divexpminus(9);
manoutmax <= divnanff(11);
expoutzero <= divzipff(11) OR expzero OR divexpminus(10);
-- 12/05/09 - make sure ccexpminus = -1 doesnt create infinity
expoutmax <= (expmax AND NOT(divexpminus(9)) AND NOT(divexpminus(10))) OR
(divexpminus(9) AND NOT(divexpminus(10))) OR divnanff(11);
END GENERATE;
goed: IF (roundconvert = 1) GENERATE
manoverflow(1) <= normmannode(1);
gva: FOR k IN 2 TO 24 GENERATE
manoverflow(k) <= manoverflow(k-1) AND normmannode(k);
END GENERATE;
poeb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 24 LOOP
ccmanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
ccexpff(k) <= '0';
END LOOP;
ccsignff <= '0';
ccsatff <= '0';
cczipff <= '0';
ccnanff <= '0';
ccoverff <= '0';
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
signoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccmanff <= normmannode(25 DOWNTO 2) + (zerovec(23 DOWNTO 1) & normmannode(1));
ccexpff(10 DOWNTO 1) <= divexpff(11)(10 DOWNTO 1) - ("000000000" & normalize);
ccsignff <= divsignff(11);
ccsatff <= divsatff(11);
cczipff <= divzipff(11);
ccnanff <= divnanff(11);
ccoverff <= manoverflow(23);
FOR k IN 1 TO 23 LOOP
manoutff(k) <= (ccmanff(k) AND NOT(manoutzero)) OR manoutmax;
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (ccexpplus(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
signoutff <= ccsignff;
END IF;
END IF;
END PROCESS;
ccexpplus <= ccexpff + ("000000000" & ccoverff);
-- both '1' when true
expmax <= ccexpplus(8) AND ccexpplus(7) AND ccexpplus(6) AND ccexpplus(5) AND
ccexpplus(4) AND ccexpplus(3) AND ccexpplus(2) AND ccexpplus(1);
expzero <= NOT(ccexpplus(8) OR ccexpplus(7) OR ccexpplus(6) OR ccexpplus(5) OR
ccexpplus(4) OR ccexpplus(3) OR ccexpplus(2) OR ccexpplus(1));
-- any special condition turns mantissa zero
manoutzero <= ccsatff OR cczipff OR expmax OR expzero OR
ccexpplus(10) OR ccexpplus(9);
manoutmax <= ccnanff;
expoutzero <= cczipff OR expzero OR ccexpplus(10);
-- 12/05/09 - make sure ccexpplus = -1 doesnt create infinity
expoutmax <= (expmax AND NOT(ccexpplus(9)) AND NOT(ccexpplus(10))) OR
(ccexpplus(9) AND NOT(ccexpplus(10))) OR ccnanff;
END GENERATE;
cc(32) <= signoutff;
cc(31 DOWNTO 24) <= expoutff;
cc(23 DOWNTO 1) <= manoutff;
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_sqrroot.vhd
|
10
|
5288
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--********************************************************************
--*** ***
--*** FP_SQRROOT.VHD ***
--*** ***
--*** Fixed Point Square Root Core - Restoring ***
--*** ***
--*** 21/12/06 ML ***
--*** ***
--*** Copyright Altera 2006 ***
--*** ***
--*** ***
--********************************************************************
ENTITY fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_sqrroot;
ARCHITECTURE rtl OF fp_sqrroot IS
type nodetype IS ARRAY (width DOWNTO 1) OF STD_LOGIC_VECTOR (width+2 DOWNTO 1);
type qfftype IS ARRAY (width-1 DOWNTO 1) OF STD_LOGIC_VECTOR (width-1 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width DOWNTO 1);
signal onevec : STD_LOGIC_VECTOR (width+1 DOWNTO 1);
signal subnode, slevel, qlevel, radff : nodetype;
signal qff : qfftype;
BEGIN
gza: FOR k IN 1 TO width GENERATE
zerovec(k) <= '0';
END GENERATE;
onevec <= "01" & zerovec(width-1 DOWNTO 1);
-- 1 <= input range < 4, therefore 1 <= root < 2
-- input may be shifted left by 1, therefore first subtract "001" not "01"
slevel(1)(width+2 DOWNTO 1) <= '0' & rad;
qlevel(1)(width+2 DOWNTO 1) <= "001" & zerovec(width-1 DOWNTO 1);
subnode(1)(width+2 DOWNTO width) <= slevel(1)(width+2 DOWNTO width) - qlevel(1)(width+2 DOWNTO width);
subnode(1)(width-1 DOWNTO 1) <= slevel(1)(width-1 DOWNTO 1);
slevel(2)(width+2 DOWNTO 1) <= radff(1)(width+1 DOWNTO 1) & '0';
qlevel(2)(width+2 DOWNTO 1) <= "0101" & zerovec(width-2 DOWNTO 1);
subnode(2)(width+2 DOWNTO width-1) <= slevel(2)(width+2 DOWNTO width-1) - qlevel(2)(width+2 DOWNTO width-1);
subnode(2)(width-2 DOWNTO 1) <= slevel(2)(width-2 DOWNTO 1);
gla: FOR k IN 3 TO width GENERATE
glb: FOR j IN 1 TO k-2 GENERATE
qlevel(k)(width+1-j) <= qff(width-j)(k-1-j);
END GENERATE;
END GENERATE;
gsa: FOR k IN 3 TO width-1 GENERATE
slevel(k)(width+2 DOWNTO 1) <= radff(k-1)(width+1 DOWNTO 1) & '0';
qlevel(k)(width+2 DOWNTO width+1) <= "01";
qlevel(k)(width+2-k DOWNTO 1) <= "01" & zerovec(width-k DOWNTO 1);
subnode(k)(width+2 DOWNTO width+1-k) <= slevel(k)(width+2 DOWNTO width+1-k) -
qlevel(k)(width+2 DOWNTO width+1-k);
subnode(k)(width-k DOWNTO 1) <= slevel(k)(width-k DOWNTO 1);
END GENERATE;
slevel(width)(width+2 DOWNTO 1) <= radff(width-1)(width+1 DOWNTO 1) & '0';
qlevel(width)(width+2 DOWNTO width+1) <= "01";
qlevel(width)(2 DOWNTO 1) <= "01";
subnode(width)(width+2 DOWNTO 1) <= slevel(width)(width+2 DOWNTO 1) - qlevel(width)(width+2 DOWNTO 1);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
FOR j IN 1 TO width+2 LOOP
radff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO width-1 LOOP
FOR j IN 1 TO width-1 LOOP
qff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
radff(1)(width+2 DOWNTO 1) <= subnode(1)(width+2 DOWNTO 1);
FOR k IN 2 TO width LOOP
FOR j IN 1 TO width+2 LOOP
radff(k)(j) <= (slevel(k)(j) AND subnode(k)(width+2)) OR
(subnode(k)(j) AND NOT(subnode(k)(width+2)));
END LOOP;
END LOOP;
FOR k IN 1 TO width-1 LOOP
qff(width-k)(1) <= NOT(subnode(k+1)(width+2));
FOR j IN 2 TO width-1 LOOP
qff(k)(j) <= qff(k)(j-1);
END LOOP;
END LOOP;
END IF;
END IF;
END PROCESS;
fro: FOR k IN 1 TO width-1 GENERATE
root(k) <= qff(k)(k);
END GENERATE;
root(width) <= '1';
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/SqrtDPStratixVf400.vhd
|
10
|
437207
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Debug Version 12.0
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from SqrtDPStratixVf400
-- VHDL created on Wed Sep 05 17:57:41 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
USE work.SqrtDPStratixVf400_safe_path.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240
entity SqrtDPStratixVf400 is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(63 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic;
bus_clk : in std_logic;
h_areset : in std_logic
);
end;
architecture normal of SqrtDPStratixVf400 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cst0_uid10_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal bias_q : std_logic_vector (10 downto 0);
signal biasP1_q : std_logic_vector (10 downto 0);
signal expAllZeros_uid39_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal fracNaN_uid44_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal fracInf_uid45_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal memoryC2_uid52_sqrtTableGenerator_q : std_logic_vector(39 downto 0);
signal memoryC3_uid53_sqrtTableGenerator_q : std_logic_vector(32 downto 0);
signal memoryC4_uid54_sqrtTableGenerator_q : std_logic_vector(23 downto 0);
signal memoryC5_uid55_sqrtTableGenerator_q : std_logic_vector(16 downto 0);
signal rndBit_uid76_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0);
signal rndBit_uid82_sqrtPolynomialEvaluator_q : std_logic_vector (2 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0);
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s_type;
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s_type;
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_q : std_logic_vector (54 downto 0);
signal reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q : std_logic_vector (3 downto 0);
signal reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0);
signal reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0);
signal reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0);
signal reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q : std_logic_vector (32 downto 0);
signal reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0);
signal reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0);
signal reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0);
signal reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q : std_logic_vector (52 downto 0);
signal reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q : std_logic_vector (59 downto 0);
signal reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q : std_logic_vector (51 downto 0);
signal ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a_q : std_logic_vector (63 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a_q : std_logic_vector (7 downto 0);
signal ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a_q : std_logic_vector (5 downto 0);
signal ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a_q : std_logic_vector (23 downto 0);
signal ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a_q : std_logic_vector (23 downto 0);
signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic;
signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic;
signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic;
signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ir : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ir : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg_q : std_logic_vector (0 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_reset0 : std_logic;
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg_q : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ir : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ir : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ir : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0);
signal pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (26 downto 0);
signal fracSel_uid43_fpSqrtTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid47_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid47_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal memoryC0_uid50_sqrtTableGenerator_q : std_logic_vector(56 downto 0);
signal memoryC1_uid51_sqrtTableGenerator_q : std_logic_vector(48 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0);
signal ts4_uid78_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0);
signal ts4_uid78_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0);
signal ts4_uid78_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0);
signal ts4_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0);
signal ts5_uid84_sqrtPolynomialEvaluator_a : std_logic_vector(60 downto 0);
signal ts5_uid84_sqrtPolynomialEvaluator_b : std_logic_vector(60 downto 0);
signal ts5_uid84_sqrtPolynomialEvaluator_o : std_logic_vector (60 downto 0);
signal ts5_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0);
signal sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_q : std_logic_vector(0 downto 0);
signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0);
signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid31_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracXAddr_uid31_fpSqrtTest_b : std_logic_vector (6 downto 0);
signal cmpEQ_w11_uid11_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal cmpEQ_w11_uid11_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal cmpEQ_w11_uid11_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid22_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expEvenSig_uid22_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expEvenSig_uid22_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expEvenSig_uid22_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal expOddSig_uid25_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expOddSig_uid25_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expOddSig_uid25_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expOddSig_uid25_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0);
signal cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0);
signal prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0);
signal prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0);
signal prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (52 downto 0);
signal X44dto0_uid33_fpSqrtTest_in : std_logic_vector (44 downto 0);
signal X44dto0_uid33_fpSqrtTest_b : std_logic_vector (44 downto 0);
signal s2_uid64_uid67_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0);
signal s3_uid70_uid73_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0);
signal add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0);
signal add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (78 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(5 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(5 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal RSqrt_uid48_fpSqrtTest_q : std_logic_vector (63 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT4_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_q : std_logic_vector(0 downto 0);
signal s4_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0);
signal s4_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0);
signal s5_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (60 downto 0);
signal s5_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (59 downto 0);
signal expZ_uid9_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal expZ_uid9_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal expZ_uid9_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expX0_uid27_fpSqrtTest_in : std_logic_vector (0 downto 0);
signal expX0_uid27_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal fracIsZero_uid12_fpSqrtTest_a : std_logic_vector(51 downto 0);
signal fracIsZero_uid12_fpSqrtTest_b : std_logic_vector(51 downto 0);
signal fracIsZero_uid12_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal excMZero_uid13_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excMZero_uid13_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excMZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal excInf_uid14_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excInf_uid14_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excInf_uid14_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expREven_uid23_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expREven_uid23_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal expROdd_uid26_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expROdd_uid26_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal lowRangeB_uid58_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid58_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid59_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0);
signal highBBits_uid59_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid64_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0);
signal highBBits_uid65_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal lowRangeB_uid70_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid70_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid71_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal highBBits_uid71_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0);
signal lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0);
signal highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0);
signal highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (52 downto 0);
signal highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0);
signal yT1_uid56_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT1_uid56_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal yT2_uid62_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT2_uid62_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal yT3_uid68_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT3_uid68_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0);
signal xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0);
signal yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0);
signal yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal R_uid112_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0);
signal R_uid112_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0);
signal R_uid127_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (77 downto 0);
signal R_uid127_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (52 downto 0);
signal xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (50 downto 0);
signal yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal fracR_uid35_fpSqrtTest_in : std_logic_vector (56 downto 0);
signal fracR_uid35_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal expOddSelect_uid28_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid28_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracIsZero_uid16_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracIsZero_uid16_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExcMZero_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExcMZero_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid29_fpSqrtTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid29_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal sumAHighB_uid60_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0);
signal sumAHighB_uid60_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0);
signal sumAHighB_uid60_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0);
signal sumAHighB_uid60_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0);
signal spad_yBottomBits_uid100_uid103_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0);
signal pad_xBottomBits_uid101_uid104_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0);
signal addrTable_uid32_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal excNaN_uid17_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excNaN_uid17_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excNaN_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal operandIsNegative_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal operandIsNegative_uid19_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal operandIsNegative_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid58_uid61_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0);
signal join_uid41_fpSqrtTest_q : std_logic_vector (2 downto 0);
signal expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracSelIn_uid42_fpSqrtTest_q : std_logic_vector (3 downto 0);
signal join_uid36_fpSqrtTest_q : std_logic_vector (1 downto 0);
signal expRPostExc_uid40_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid40_fpSqrtTest_q : std_logic_vector (10 downto 0);
begin
--ld_xIn_v_to_xOut_v_notEnable(LOGICAL,317)
ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q;
ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a;
--ld_xIn_v_to_xOut_v_nor(LOGICAL,318)
ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b);
--ld_xIn_v_to_xOut_v_mem_top(CONSTANT,314)
ld_xIn_v_to_xOut_v_mem_top_q <= "011001";
--ld_xIn_v_to_xOut_v_cmp(LOGICAL,315)
ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q;
ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q);
ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0";
--ld_xIn_v_to_xOut_v_cmpReg(REG,316)
ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_sticky_ena(REG,319)
ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,320)
ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q;
ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b;
--GND(CONSTANT,0)
GND_q <= "0";
--xIn(PORTIN,3)@0
--expX_uid6_fpSqrtTest(BITSELECT,5)@0
expX_uid6_fpSqrtTest_in <= xIn_0(62 downto 0);
expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52);
--expZ_uid9_fpSqrtTest(LOGICAL,8)@0
expZ_uid9_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expZ_uid9_fpSqrtTest_b <= STD_LOGIC_VECTOR("0000000000" & GND_q);
expZ_uid9_fpSqrtTest_q <= "1" when expZ_uid9_fpSqrtTest_a = expZ_uid9_fpSqrtTest_b else "0";
--signX_uid8_fpSqrtTest(BITSELECT,7)@0
signX_uid8_fpSqrtTest_in <= xIn_0;
signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63);
--excMZero_uid13_fpSqrtTest(LOGICAL,12)@0
excMZero_uid13_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b;
excMZero_uid13_fpSqrtTest_b <= expZ_uid9_fpSqrtTest_q;
excMZero_uid13_fpSqrtTest_q <= excMZero_uid13_fpSqrtTest_a and excMZero_uid13_fpSqrtTest_b;
--ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,310)
-- every=1, low=0, high=25, step=1, init=1
ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 24 THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 25;
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,5));
--ld_xIn_v_to_xOut_v_replace_rdreg(REG,311)
ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_xIn_v_to_xOut_v_replace_rdmux(MUX,312)
ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q;
ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q)
BEGIN
CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS
WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem(DUALMEM,361)
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_reset0 <= areset;
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ia <= excMZero_uid13_fpSqrtTest_q;
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 26,
width_b => 1,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_iq,
address_a => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_aa,
data_a => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ia
);
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_q <= ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_iq(0 downto 0);
--ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg(DELAY,360)
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_q, xout => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg_q, clk => clk, aclr => areset );
--cst0_uid10_fpSqrtTest(CONSTANT,9)
cst0_uid10_fpSqrtTest_q <= "11111111111";
--expAllZeros_uid39_fpSqrtTest(CONSTANT,38)
expAllZeros_uid39_fpSqrtTest_q <= "00000000000";
--biasP1(CONSTANT,23)
biasP1_q <= "01111111110";
--expOddSig_uid25_fpSqrtTest(ADD,24)@0
expOddSig_uid25_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expOddSig_uid25_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & biasP1_q);
expOddSig_uid25_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid25_fpSqrtTest_a) + UNSIGNED(expOddSig_uid25_fpSqrtTest_b));
expOddSig_uid25_fpSqrtTest_q <= expOddSig_uid25_fpSqrtTest_o(11 downto 0);
--expROdd_uid26_fpSqrtTest(BITSELECT,25)@0
expROdd_uid26_fpSqrtTest_in <= expOddSig_uid25_fpSqrtTest_q;
expROdd_uid26_fpSqrtTest_b <= expROdd_uid26_fpSqrtTest_in(11 downto 1);
--bias(CONSTANT,20)
bias_q <= "01111111111";
--expEvenSig_uid22_fpSqrtTest(ADD,21)@0
expEvenSig_uid22_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expEvenSig_uid22_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & bias_q);
expEvenSig_uid22_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid22_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid22_fpSqrtTest_b));
expEvenSig_uid22_fpSqrtTest_q <= expEvenSig_uid22_fpSqrtTest_o(11 downto 0);
--expREven_uid23_fpSqrtTest(BITSELECT,22)@0
expREven_uid23_fpSqrtTest_in <= expEvenSig_uid22_fpSqrtTest_q;
expREven_uid23_fpSqrtTest_b <= expREven_uid23_fpSqrtTest_in(11 downto 1);
--expX0_uid27_fpSqrtTest(BITSELECT,26)@0
expX0_uid27_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0);
expX0_uid27_fpSqrtTest_b <= expX0_uid27_fpSqrtTest_in(0 downto 0);
--expOddSelect_uid28_fpSqrtTest(LOGICAL,27)@0
expOddSelect_uid28_fpSqrtTest_a <= expX0_uid27_fpSqrtTest_b;
expOddSelect_uid28_fpSqrtTest_q <= not expOddSelect_uid28_fpSqrtTest_a;
--expRMux_uid29_fpSqrtTest(MUX,28)@0
expRMux_uid29_fpSqrtTest_s <= expOddSelect_uid28_fpSqrtTest_q;
expRMux_uid29_fpSqrtTest: PROCESS (expRMux_uid29_fpSqrtTest_s, expREven_uid23_fpSqrtTest_b, expROdd_uid26_fpSqrtTest_b)
BEGIN
CASE expRMux_uid29_fpSqrtTest_s IS
WHEN "0" => expRMux_uid29_fpSqrtTest_q <= expREven_uid23_fpSqrtTest_b;
WHEN "1" => expRMux_uid29_fpSqrtTest_q <= expROdd_uid26_fpSqrtTest_b;
WHEN OTHERS => expRMux_uid29_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--InvExcMZero_uid18_fpSqrtTest(LOGICAL,17)@0
InvExcMZero_uid18_fpSqrtTest_a <= excMZero_uid13_fpSqrtTest_q;
InvExcMZero_uid18_fpSqrtTest_q <= not InvExcMZero_uid18_fpSqrtTest_a;
--operandIsNegative_uid19_fpSqrtTest(LOGICAL,18)@0
operandIsNegative_uid19_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b;
operandIsNegative_uid19_fpSqrtTest_b <= InvExcMZero_uid18_fpSqrtTest_q;
operandIsNegative_uid19_fpSqrtTest_q <= operandIsNegative_uid19_fpSqrtTest_a and operandIsNegative_uid19_fpSqrtTest_b;
--cmpEQ_w11_uid11_fpSqrtTest(LOGICAL,10)@0
cmpEQ_w11_uid11_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
cmpEQ_w11_uid11_fpSqrtTest_b <= cst0_uid10_fpSqrtTest_q;
cmpEQ_w11_uid11_fpSqrtTest_q <= "1" when cmpEQ_w11_uid11_fpSqrtTest_a = cmpEQ_w11_uid11_fpSqrtTest_b else "0";
--expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest(LOGICAL,19)@0
expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_a <= cmpEQ_w11_uid11_fpSqrtTest_q;
expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_b <= operandIsNegative_uid19_fpSqrtTest_q;
expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_q <= expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_a or expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_b;
--join_uid36_fpSqrtTest(BITJOIN,35)@0
join_uid36_fpSqrtTest_q <= expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_q & expZ_uid9_fpSqrtTest_q;
--expRPostExc_uid40_fpSqrtTest(MUX,39)@0
expRPostExc_uid40_fpSqrtTest_s <= join_uid36_fpSqrtTest_q;
expRPostExc_uid40_fpSqrtTest: PROCESS (expRPostExc_uid40_fpSqrtTest_s, expRMux_uid29_fpSqrtTest_q)
BEGIN
CASE expRPostExc_uid40_fpSqrtTest_s IS
WHEN "00" => expRPostExc_uid40_fpSqrtTest_q <= expRMux_uid29_fpSqrtTest_q;
WHEN "01" => expRPostExc_uid40_fpSqrtTest_q <= expAllZeros_uid39_fpSqrtTest_q;
WHEN "10" => expRPostExc_uid40_fpSqrtTest_q <= cst0_uid10_fpSqrtTest_q;
WHEN "11" => expRPostExc_uid40_fpSqrtTest_q <= cst0_uid10_fpSqrtTest_q;
WHEN OTHERS => expRPostExc_uid40_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg(DELAY,347)
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid40_fpSqrtTest_q, xout => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem(DUALMEM,348)
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg_q;
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 26,
width_b => 11,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_iq(10 downto 0);
--fracNaN_uid44_fpSqrtTest(CONSTANT,43)
fracNaN_uid44_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracXAddr_uid31_fpSqrtTest(BITSELECT,30)@0
fracXAddr_uid31_fpSqrtTest_in <= xIn_0(51 downto 0);
fracXAddr_uid31_fpSqrtTest_b <= fracXAddr_uid31_fpSqrtTest_in(51 downto 45);
--addrTable_uid32_fpSqrtTest(BITJOIN,31)@0
addrTable_uid32_fpSqrtTest_q <= expOddSelect_uid28_fpSqrtTest_q & fracXAddr_uid31_fpSqrtTest_b;
--memoryC5_uid55_sqrtTableGenerator(LOOKUP,54)@0
memoryC5_uid55_sqrtTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid55_sqrtTableGenerator_q <= "00110111000001001";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (addrTable_uid32_fpSqrtTest_q) IS
WHEN "00000000" => memoryC5_uid55_sqrtTableGenerator_q <= "00110111000001001";
WHEN "00000001" => memoryC5_uid55_sqrtTableGenerator_q <= "00110101001010110";
WHEN "00000010" => memoryC5_uid55_sqrtTableGenerator_q <= "00110011011100000";
WHEN "00000011" => memoryC5_uid55_sqrtTableGenerator_q <= "00110001101001100";
WHEN "00000100" => memoryC5_uid55_sqrtTableGenerator_q <= "00101111111011110";
WHEN "00000101" => memoryC5_uid55_sqrtTableGenerator_q <= "00101110010111110";
WHEN "00000110" => memoryC5_uid55_sqrtTableGenerator_q <= "00101100110101001";
WHEN "00000111" => memoryC5_uid55_sqrtTableGenerator_q <= "00101011010000110";
WHEN "00001000" => memoryC5_uid55_sqrtTableGenerator_q <= "00101001111000000";
WHEN "00001001" => memoryC5_uid55_sqrtTableGenerator_q <= "00101000100001000";
WHEN "00001010" => memoryC5_uid55_sqrtTableGenerator_q <= "00100111001111011";
WHEN "00001011" => memoryC5_uid55_sqrtTableGenerator_q <= "00100110000101101";
WHEN "00001100" => memoryC5_uid55_sqrtTableGenerator_q <= "00100100111010100";
WHEN "00001101" => memoryC5_uid55_sqrtTableGenerator_q <= "00100011100110101";
WHEN "00001110" => memoryC5_uid55_sqrtTableGenerator_q <= "00100010100100011";
WHEN "00001111" => memoryC5_uid55_sqrtTableGenerator_q <= "00100001011010100";
WHEN "00010000" => memoryC5_uid55_sqrtTableGenerator_q <= "00100000011111001";
WHEN "00010001" => memoryC5_uid55_sqrtTableGenerator_q <= "00011111011001000";
WHEN "00010010" => memoryC5_uid55_sqrtTableGenerator_q <= "00011110011100100";
WHEN "00010011" => memoryC5_uid55_sqrtTableGenerator_q <= "00011101101010111";
WHEN "00010100" => memoryC5_uid55_sqrtTableGenerator_q <= "00011100110101000";
WHEN "00010101" => memoryC5_uid55_sqrtTableGenerator_q <= "00011011111011001";
WHEN "00010110" => memoryC5_uid55_sqrtTableGenerator_q <= "00011011000101001";
WHEN "00010111" => memoryC5_uid55_sqrtTableGenerator_q <= "00011010010110101";
WHEN "00011000" => memoryC5_uid55_sqrtTableGenerator_q <= "00011001011110000";
WHEN "00011001" => memoryC5_uid55_sqrtTableGenerator_q <= "00011000101111100";
WHEN "00011010" => memoryC5_uid55_sqrtTableGenerator_q <= "00010111111010101";
WHEN "00011011" => memoryC5_uid55_sqrtTableGenerator_q <= "00010111010001011";
WHEN "00011100" => memoryC5_uid55_sqrtTableGenerator_q <= "00010110101101000";
WHEN "00011101" => memoryC5_uid55_sqrtTableGenerator_q <= "00010110000110110";
WHEN "00011110" => memoryC5_uid55_sqrtTableGenerator_q <= "00010101010110001";
WHEN "00011111" => memoryC5_uid55_sqrtTableGenerator_q <= "00010100110100010";
WHEN "00100000" => memoryC5_uid55_sqrtTableGenerator_q <= "00010100001100111";
WHEN "00100001" => memoryC5_uid55_sqrtTableGenerator_q <= "00010011100111000";
WHEN "00100010" => memoryC5_uid55_sqrtTableGenerator_q <= "00010011001010000";
WHEN "00100011" => memoryC5_uid55_sqrtTableGenerator_q <= "00010010100101111";
WHEN "00100100" => memoryC5_uid55_sqrtTableGenerator_q <= "00010010000100110";
WHEN "00100101" => memoryC5_uid55_sqrtTableGenerator_q <= "00010001101001000";
WHEN "00100110" => memoryC5_uid55_sqrtTableGenerator_q <= "00010001000100000";
WHEN "00100111" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000101000001";
WHEN "00101000" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000001001100";
WHEN "00101001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001111110000101";
WHEN "00101010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001111011100000";
WHEN "00101011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110111110110";
WHEN "00101100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110101011010";
WHEN "00101101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110010101101";
WHEN "00101110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101111010001";
WHEN "00101111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101011110111";
WHEN "00110000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101001111111";
WHEN "00110001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100110010111";
WHEN "00110010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100100001101";
WHEN "00110011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100010000010";
WHEN "00110100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100000000110";
WHEN "00110101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011100111001";
WHEN "00110110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011001111001";
WHEN "00110111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011001000110";
WHEN "00111000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010110010000";
WHEN "00111001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010100101100";
WHEN "00111010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010010110001";
WHEN "00111011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010000111011";
WHEN "00111100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001110100010";
WHEN "00111101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001100100101";
WHEN "00111110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001010010011";
WHEN "00111111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001001110110";
WHEN "01000000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000111011100";
WHEN "01000001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000101011101";
WHEN "01000010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000011011000";
WHEN "01000011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000010110101";
WHEN "01000100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000000111101";
WHEN "01000101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111111000001";
WHEN "01000110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111101101011";
WHEN "01000111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111100110101";
WHEN "01001000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111011110100";
WHEN "01001001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111010100100";
WHEN "01001010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111001110111";
WHEN "01001011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111000000010";
WHEN "01001100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110110110001";
WHEN "01001101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110101100000";
WHEN "01001110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110011010111";
WHEN "01001111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110010111010";
WHEN "01010000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110001111110";
WHEN "01010001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110001101110";
WHEN "01010010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101111100111";
WHEN "01010011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101110111000";
WHEN "01010100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101101010111";
WHEN "01010101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101100111011";
WHEN "01010110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101100010111";
WHEN "01010111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101010010100";
WHEN "01011000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001110101";
WHEN "01011001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001010100";
WHEN "01011010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100111110101";
WHEN "01011011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100111100111";
WHEN "01011100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100110111101";
WHEN "01011101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100110001010";
WHEN "01011110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100110000011";
WHEN "01011111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011111110";
WHEN "01100000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011000000";
WHEN "01100001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011100011";
WHEN "01100010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100010111110";
WHEN "01100011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100001000111";
WHEN "01100100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100001010011";
WHEN "01100101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100000111001";
WHEN "01100110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100000001100";
WHEN "01100111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011110011011";
WHEN "01101000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101110001";
WHEN "01101001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011110100010";
WHEN "01101010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101110100";
WHEN "01101011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101011101";
WHEN "01101100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011100001000";
WHEN "01101101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011100001011";
WHEN "01101110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011011000111";
WHEN "01101111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011010101011";
WHEN "01110000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011001010011";
WHEN "01110001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011001010011";
WHEN "01110010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011001010101";
WHEN "01110011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011001100100";
WHEN "01110100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011000110010";
WHEN "01110101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010111101100";
WHEN "01110110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010110111100";
WHEN "01110111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010110111110";
WHEN "01111000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010110000110";
WHEN "01111001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010101101001";
WHEN "01111010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100111110";
WHEN "01111011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100110010";
WHEN "01111100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100111111";
WHEN "01111101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010101011000";
WHEN "01111110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100001000";
WHEN "01111111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100100111";
WHEN "10000000" => memoryC5_uid55_sqrtTableGenerator_q <= "01001101101101100";
WHEN "10000001" => memoryC5_uid55_sqrtTableGenerator_q <= "01001011001110100";
WHEN "10000010" => memoryC5_uid55_sqrtTableGenerator_q <= "01001000100110100";
WHEN "10000011" => memoryC5_uid55_sqrtTableGenerator_q <= "01000110000111011";
WHEN "10000100" => memoryC5_uid55_sqrtTableGenerator_q <= "01000011111000010";
WHEN "10000101" => memoryC5_uid55_sqrtTableGenerator_q <= "01000001100001110";
WHEN "10000110" => memoryC5_uid55_sqrtTableGenerator_q <= "00111111011010101";
WHEN "10000111" => memoryC5_uid55_sqrtTableGenerator_q <= "00111101010100001";
WHEN "10001000" => memoryC5_uid55_sqrtTableGenerator_q <= "00111011001110101";
WHEN "10001001" => memoryC5_uid55_sqrtTableGenerator_q <= "00111001010100100";
WHEN "10001010" => memoryC5_uid55_sqrtTableGenerator_q <= "00110111101001000";
WHEN "10001011" => memoryC5_uid55_sqrtTableGenerator_q <= "00110101110111110";
WHEN "10001100" => memoryC5_uid55_sqrtTableGenerator_q <= "00110100001000110";
WHEN "10001101" => memoryC5_uid55_sqrtTableGenerator_q <= "00110010011001110";
WHEN "10001110" => memoryC5_uid55_sqrtTableGenerator_q <= "00110000111010001";
WHEN "10001111" => memoryC5_uid55_sqrtTableGenerator_q <= "00101111010011101";
WHEN "10010000" => memoryC5_uid55_sqrtTableGenerator_q <= "00101101110111100";
WHEN "10010001" => memoryC5_uid55_sqrtTableGenerator_q <= "00101100011101010";
WHEN "10010010" => memoryC5_uid55_sqrtTableGenerator_q <= "00101011000100101";
WHEN "10010011" => memoryC5_uid55_sqrtTableGenerator_q <= "00101001110101110";
WHEN "10010100" => memoryC5_uid55_sqrtTableGenerator_q <= "00101000100111100";
WHEN "10010101" => memoryC5_uid55_sqrtTableGenerator_q <= "00100111011000100";
WHEN "10010110" => memoryC5_uid55_sqrtTableGenerator_q <= "00100110001011010";
WHEN "10010111" => memoryC5_uid55_sqrtTableGenerator_q <= "00100101000111110";
WHEN "10011000" => memoryC5_uid55_sqrtTableGenerator_q <= "00100100000000001";
WHEN "10011001" => memoryC5_uid55_sqrtTableGenerator_q <= "00100010111100001";
WHEN "10011010" => memoryC5_uid55_sqrtTableGenerator_q <= "00100001111111000";
WHEN "10011011" => memoryC5_uid55_sqrtTableGenerator_q <= "00100000111111101";
WHEN "10011100" => memoryC5_uid55_sqrtTableGenerator_q <= "00100000000011111";
WHEN "10011101" => memoryC5_uid55_sqrtTableGenerator_q <= "00011111000001100";
WHEN "10011110" => memoryC5_uid55_sqrtTableGenerator_q <= "00011110010000001";
WHEN "10011111" => memoryC5_uid55_sqrtTableGenerator_q <= "00011101011000101";
WHEN "10100000" => memoryC5_uid55_sqrtTableGenerator_q <= "00011100100001110";
WHEN "10100001" => memoryC5_uid55_sqrtTableGenerator_q <= "00011011110000010";
WHEN "10100010" => memoryC5_uid55_sqrtTableGenerator_q <= "00011011000111101";
WHEN "10100011" => memoryC5_uid55_sqrtTableGenerator_q <= "00011010010011000";
WHEN "10100100" => memoryC5_uid55_sqrtTableGenerator_q <= "00011001101011110";
WHEN "10100101" => memoryC5_uid55_sqrtTableGenerator_q <= "00011000110100010";
WHEN "10100110" => memoryC5_uid55_sqrtTableGenerator_q <= "00011000010001000";
WHEN "10100111" => memoryC5_uid55_sqrtTableGenerator_q <= "00010111100001000";
WHEN "10101000" => memoryC5_uid55_sqrtTableGenerator_q <= "00010110111011101";
WHEN "10101001" => memoryC5_uid55_sqrtTableGenerator_q <= "00010110010111111";
WHEN "10101010" => memoryC5_uid55_sqrtTableGenerator_q <= "00010101110101111";
WHEN "10101011" => memoryC5_uid55_sqrtTableGenerator_q <= "00010101010000000";
WHEN "10101100" => memoryC5_uid55_sqrtTableGenerator_q <= "00010100101000111";
WHEN "10101101" => memoryC5_uid55_sqrtTableGenerator_q <= "00010100010000111";
WHEN "10101110" => memoryC5_uid55_sqrtTableGenerator_q <= "00010011101001011";
WHEN "10101111" => memoryC5_uid55_sqrtTableGenerator_q <= "00010011001001010";
WHEN "10110000" => memoryC5_uid55_sqrtTableGenerator_q <= "00010010100100010";
WHEN "10110001" => memoryC5_uid55_sqrtTableGenerator_q <= "00010010001011101";
WHEN "10110010" => memoryC5_uid55_sqrtTableGenerator_q <= "00010001101011001";
WHEN "10110011" => memoryC5_uid55_sqrtTableGenerator_q <= "00010001001110100";
WHEN "10110100" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000110110010";
WHEN "10110101" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000011100011";
WHEN "10110110" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000000110010";
WHEN "10110111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001111101001000";
WHEN "10111000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001111010100001";
WHEN "10111001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110111110111";
WHEN "10111010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110101010110";
WHEN "10111011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110001010111";
WHEN "10111100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101111000100";
WHEN "10111101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101100101100";
WHEN "10111110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101010001010";
WHEN "10111111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100111001110";
WHEN "11000000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100100101000";
WHEN "11000001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100011000011";
WHEN "11000010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011111100011";
WHEN "11000011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011110011100";
WHEN "11000100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011100001111";
WHEN "11000101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011001101110";
WHEN "11000110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010111100000";
WHEN "11000111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010101101011";
WHEN "11001000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010011011010";
WHEN "11001001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010010010100";
WHEN "11001010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001111100111";
WHEN "11001011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001110101011";
WHEN "11001100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001101001110";
WHEN "11001101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001011000111";
WHEN "11001110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001001111110";
WHEN "11001111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000111110000";
WHEN "11010000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000110101011";
WHEN "11010001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000101101110";
WHEN "11010010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000011111110";
WHEN "11010011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000001100010";
WHEN "11010100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000000101110";
WHEN "11010101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111111101011";
WHEN "11010110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111101111100";
WHEN "11010111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111100011101";
WHEN "11011000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111011000110";
WHEN "11011001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111001100010";
WHEN "11011010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111001100100";
WHEN "11011011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110111100110";
WHEN "11011100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110110001100";
WHEN "11011101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110101100011";
WHEN "11011110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110100010111";
WHEN "11011111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110011101011";
WHEN "11100000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110010100100";
WHEN "11100001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110001001011";
WHEN "11100010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110000010111";
WHEN "11100011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110000011010";
WHEN "11100100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101110011000";
WHEN "11100101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101101011001";
WHEN "11100110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101100100100";
WHEN "11100111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101100000001";
WHEN "11101000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101010100011";
WHEN "11101001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001110111";
WHEN "11101010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001000010";
WHEN "11101011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001000111";
WHEN "11101100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101000010010";
WHEN "11101101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100111000101";
WHEN "11101110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100110011111";
WHEN "11101111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100101001100";
WHEN "11110000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100100101010";
WHEN "11110001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011110110";
WHEN "11110010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011111000";
WHEN "11110011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011011101";
WHEN "11110100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100010000011";
WHEN "11110101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100001010101";
WHEN "11110110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100001000101";
WHEN "11110111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011111111000";
WHEN "11111000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011111111011";
WHEN "11111001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011111010101";
WHEN "11111010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011110010101";
WHEN "11111011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101101010";
WHEN "11111100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101000001";
WHEN "11111101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101100010";
WHEN "11111110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011100010101";
WHEN "11111111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011011110110";
WHEN OTHERS =>
memoryC5_uid55_sqrtTableGenerator_q <= "00110111000001001";
END CASE;
END IF;
END PROCESS;
--ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a(DELAY,182)@0
ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => xIn_0, xout => ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a_q, clk => clk, aclr => areset );
--X44dto0_uid33_fpSqrtTest(BITSELECT,32)@1
X44dto0_uid33_fpSqrtTest_in <= ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a_q(44 downto 0);
X44dto0_uid33_fpSqrtTest_b <= X44dto0_uid33_fpSqrtTest_in(44 downto 0);
--yT1_uid56_sqrtPolynomialEvaluator(BITSELECT,55)@1
yT1_uid56_sqrtPolynomialEvaluator_in <= X44dto0_uid33_fpSqrtTest_b;
yT1_uid56_sqrtPolynomialEvaluator_b <= yT1_uid56_sqrtPolynomialEvaluator_in(44 downto 28);
--prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator(MULT,86)@1
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_b);
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_a <= yT1_uid56_sqrtPolynomialEvaluator_b;
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_b <= memoryC5_uid55_sqrtTableGenerator_q;
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_pr,34));
END IF;
END PROCESS;
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_q <= prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator(BITSELECT,87)@4
prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_in <= prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_in(33 downto 16);
--highBBits_uid59_sqrtPolynomialEvaluator(BITSELECT,58)@4
highBBits_uid59_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_b;
highBBits_uid59_sqrtPolynomialEvaluator_b <= highBBits_uid59_sqrtPolynomialEvaluator_in(17 downto 1);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a(DELAY,203)@0
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addrTable_uid32_fpSqrtTest_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a_q, clk => clk, aclr => areset );
--memoryC4_uid54_sqrtTableGenerator(LOOKUP,53)@3
memoryC4_uid54_sqrtTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid54_sqrtTableGenerator_q <= "101100000000001000110110";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a_q) IS
WHEN "00000000" => memoryC4_uid54_sqrtTableGenerator_q <= "101100000000001000110110";
WHEN "00000001" => memoryC4_uid54_sqrtTableGenerator_q <= "101100100010100000111110";
WHEN "00000010" => memoryC4_uid54_sqrtTableGenerator_q <= "101101000011101100101111";
WHEN "00000011" => memoryC4_uid54_sqrtTableGenerator_q <= "101101100011110010111000";
WHEN "00000100" => memoryC4_uid54_sqrtTableGenerator_q <= "101110000010110011110010";
WHEN "00000101" => memoryC4_uid54_sqrtTableGenerator_q <= "101110100000110000011101";
WHEN "00000110" => memoryC4_uid54_sqrtTableGenerator_q <= "101110111101101101110111";
WHEN "00000111" => memoryC4_uid54_sqrtTableGenerator_q <= "101111011001110000010110";
WHEN "00001000" => memoryC4_uid54_sqrtTableGenerator_q <= "101111110100110101011001";
WHEN "00001001" => memoryC4_uid54_sqrtTableGenerator_q <= "110000001111000010101011";
WHEN "00001010" => memoryC4_uid54_sqrtTableGenerator_q <= "110000101000011000110010";
WHEN "00001011" => memoryC4_uid54_sqrtTableGenerator_q <= "110001000000111001101101";
WHEN "00001100" => memoryC4_uid54_sqrtTableGenerator_q <= "110001011000101001111000";
WHEN "00001101" => memoryC4_uid54_sqrtTableGenerator_q <= "110001101111101101110000";
WHEN "00001110" => memoryC4_uid54_sqrtTableGenerator_q <= "110010000101111110100011";
WHEN "00001111" => memoryC4_uid54_sqrtTableGenerator_q <= "110010011011100110011110";
WHEN "00010000" => memoryC4_uid54_sqrtTableGenerator_q <= "110010110000011111000101";
WHEN "00010001" => memoryC4_uid54_sqrtTableGenerator_q <= "110011000100110011011001";
WHEN "00010010" => memoryC4_uid54_sqrtTableGenerator_q <= "110011011000011101100101";
WHEN "00010011" => memoryC4_uid54_sqrtTableGenerator_q <= "110011101011011110011101";
WHEN "00010100" => memoryC4_uid54_sqrtTableGenerator_q <= "110011111101111100111101";
WHEN "00010101" => memoryC4_uid54_sqrtTableGenerator_q <= "110100001111111001111010";
WHEN "00010110" => memoryC4_uid54_sqrtTableGenerator_q <= "110100100001010011111101";
WHEN "00010111" => memoryC4_uid54_sqrtTableGenerator_q <= "110100110010001011011100";
WHEN "00011000" => memoryC4_uid54_sqrtTableGenerator_q <= "110101000010100110110011";
WHEN "00011001" => memoryC4_uid54_sqrtTableGenerator_q <= "110101010010100001000100";
WHEN "00011010" => memoryC4_uid54_sqrtTableGenerator_q <= "110101100010000000011111";
WHEN "00011011" => memoryC4_uid54_sqrtTableGenerator_q <= "110101110001000000000111";
WHEN "00011100" => memoryC4_uid54_sqrtTableGenerator_q <= "110101111111100011001100";
WHEN "00011101" => memoryC4_uid54_sqrtTableGenerator_q <= "110110001101101100101011";
WHEN "00011110" => memoryC4_uid54_sqrtTableGenerator_q <= "110110011011100000011011";
WHEN "00011111" => memoryC4_uid54_sqrtTableGenerator_q <= "110110101000110111000100";
WHEN "00100000" => memoryC4_uid54_sqrtTableGenerator_q <= "110110110101111000000011";
WHEN "00100001" => memoryC4_uid54_sqrtTableGenerator_q <= "110111000010100010000101";
WHEN "00100010" => memoryC4_uid54_sqrtTableGenerator_q <= "110111001110110011001000";
WHEN "00100011" => memoryC4_uid54_sqrtTableGenerator_q <= "110111011010110001010101";
WHEN "00100100" => memoryC4_uid54_sqrtTableGenerator_q <= "110111100110011001111011";
WHEN "00100101" => memoryC4_uid54_sqrtTableGenerator_q <= "110111110001101101000100";
WHEN "00100110" => memoryC4_uid54_sqrtTableGenerator_q <= "110111111100110000001111";
WHEN "00100111" => memoryC4_uid54_sqrtTableGenerator_q <= "111000000111011101110001";
WHEN "00101000" => memoryC4_uid54_sqrtTableGenerator_q <= "111000010001111010010001";
WHEN "00101001" => memoryC4_uid54_sqrtTableGenerator_q <= "111000011100000011100111";
WHEN "00101010" => memoryC4_uid54_sqrtTableGenerator_q <= "111000100101111010101011";
WHEN "00101011" => memoryC4_uid54_sqrtTableGenerator_q <= "111000101111100100001111";
WHEN "00101100" => memoryC4_uid54_sqrtTableGenerator_q <= "111000111000111011000011";
WHEN "00101101" => memoryC4_uid54_sqrtTableGenerator_q <= "111001000010000011001101";
WHEN "00101110" => memoryC4_uid54_sqrtTableGenerator_q <= "111001001010111110010111";
WHEN "00101111" => memoryC4_uid54_sqrtTableGenerator_q <= "111001010011101011100011";
WHEN "00110000" => memoryC4_uid54_sqrtTableGenerator_q <= "111001011100000110010100";
WHEN "00110001" => memoryC4_uid54_sqrtTableGenerator_q <= "111001100100011000101111";
WHEN "00110010" => memoryC4_uid54_sqrtTableGenerator_q <= "111001101100011001111001";
WHEN "00110011" => memoryC4_uid54_sqrtTableGenerator_q <= "111001110100001110101001";
WHEN "00110100" => memoryC4_uid54_sqrtTableGenerator_q <= "111001111011110110010110";
WHEN "00110101" => memoryC4_uid54_sqrtTableGenerator_q <= "111010000011010101101010";
WHEN "00110110" => memoryC4_uid54_sqrtTableGenerator_q <= "111010001010101000110111";
WHEN "00110111" => memoryC4_uid54_sqrtTableGenerator_q <= "111010010001101011001011";
WHEN "00111000" => memoryC4_uid54_sqrtTableGenerator_q <= "111010011000100111111001";
WHEN "00111001" => memoryC4_uid54_sqrtTableGenerator_q <= "111010011111010110110101";
WHEN "00111010" => memoryC4_uid54_sqrtTableGenerator_q <= "111010100101111100001111";
WHEN "00111011" => memoryC4_uid54_sqrtTableGenerator_q <= "111010101100010111100101";
WHEN "00111100" => memoryC4_uid54_sqrtTableGenerator_q <= "111010110010101010111100";
WHEN "00111101" => memoryC4_uid54_sqrtTableGenerator_q <= "111010111000110011100111";
WHEN "00111110" => memoryC4_uid54_sqrtTableGenerator_q <= "111010111110110100010010";
WHEN "00111111" => memoryC4_uid54_sqrtTableGenerator_q <= "111011000100100110111100";
WHEN "01000000" => memoryC4_uid54_sqrtTableGenerator_q <= "111011001010010110011111";
WHEN "01000001" => memoryC4_uid54_sqrtTableGenerator_q <= "111011001111111100010110";
WHEN "01000010" => memoryC4_uid54_sqrtTableGenerator_q <= "111011010101011010011100";
WHEN "01000011" => memoryC4_uid54_sqrtTableGenerator_q <= "111011011010101100100101";
WHEN "01000100" => memoryC4_uid54_sqrtTableGenerator_q <= "111011011111111010100100";
WHEN "01000101" => memoryC4_uid54_sqrtTableGenerator_q <= "111011100101000001011010";
WHEN "01000110" => memoryC4_uid54_sqrtTableGenerator_q <= "111011101001111111010111";
WHEN "01000111" => memoryC4_uid54_sqrtTableGenerator_q <= "111011101110110100110100";
WHEN "01001000" => memoryC4_uid54_sqrtTableGenerator_q <= "111011110011100100000110";
WHEN "01001001" => memoryC4_uid54_sqrtTableGenerator_q <= "111011111000001101000001";
WHEN "01001010" => memoryC4_uid54_sqrtTableGenerator_q <= "111011111100101110010010";
WHEN "01001011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100000001001100000001";
WHEN "01001100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100000101100010000010";
WHEN "01001101" => memoryC4_uid54_sqrtTableGenerator_q <= "111100001001110010011010";
WHEN "01001110" => memoryC4_uid54_sqrtTableGenerator_q <= "111100001101111111001110";
WHEN "01001111" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010010000001101101";
WHEN "01010000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010110000000000101";
WHEN "01010001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100011001110111001110";
WHEN "01010010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100011101101110000110";
WHEN "01010011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100100001011100010000";
WHEN "01010100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100100101000111001110";
WHEN "01010101" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101000101010101011";
WHEN "01010110" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101100001010000000";
WHEN "01010111" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101111101000001100";
WHEN "01011000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110010111110001101";
WHEN "01011001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110110001111101111";
WHEN "01011010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111001011111010100";
WHEN "01011011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111100100111100011";
WHEN "01011100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111111101101000001";
WHEN "01011101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101000010101110111101";
WHEN "01011110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101000101101011001001";
WHEN "01011111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001000101000100111";
WHEN "01100000" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001011011111101000";
WHEN "01100001" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001110001111001010";
WHEN "01100010" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010000111101111101";
WHEN "01100011" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010011101101000100";
WHEN "01100100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010110010011001101";
WHEN "01100101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011000110111100010";
WHEN "01100110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011011011001011101";
WHEN "01100111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011101111011011000";
WHEN "01101000" => memoryC4_uid54_sqrtTableGenerator_q <= "111101100000010111001000";
WHEN "01101001" => memoryC4_uid54_sqrtTableGenerator_q <= "111101100010101100011001";
WHEN "01101010" => memoryC4_uid54_sqrtTableGenerator_q <= "111101100101000010011010";
WHEN "01101011" => memoryC4_uid54_sqrtTableGenerator_q <= "111101100111010100101100";
WHEN "01101100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101101001100110111000";
WHEN "01101101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101101011110010111010";
WHEN "01101110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101101101111111000110";
WHEN "01101111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101110000000111000001";
WHEN "01110000" => memoryC4_uid54_sqrtTableGenerator_q <= "111101110010001110111001";
WHEN "01110001" => memoryC4_uid54_sqrtTableGenerator_q <= "111101110100010000110100";
WHEN "01110010" => memoryC4_uid54_sqrtTableGenerator_q <= "111101110110010000001010";
WHEN "01110011" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111000001100100111";
WHEN "01110100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111010001001011001";
WHEN "01110101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111100000100110100";
WHEN "01110110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111101111101010110";
WHEN "01110111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111111110001010110";
WHEN "01111000" => memoryC4_uid54_sqrtTableGenerator_q <= "111110000001100101111100";
WHEN "01111001" => memoryC4_uid54_sqrtTableGenerator_q <= "111110000011010111010000";
WHEN "01111010" => memoryC4_uid54_sqrtTableGenerator_q <= "111110000101000111000000";
WHEN "01111011" => memoryC4_uid54_sqrtTableGenerator_q <= "111110000110110011100101";
WHEN "01111100" => memoryC4_uid54_sqrtTableGenerator_q <= "111110001000011101100000";
WHEN "01111101" => memoryC4_uid54_sqrtTableGenerator_q <= "111110001010000100101101";
WHEN "01111110" => memoryC4_uid54_sqrtTableGenerator_q <= "111110001011101110100001";
WHEN "01111111" => memoryC4_uid54_sqrtTableGenerator_q <= "111110001101010001110000";
WHEN "10000000" => memoryC4_uid54_sqrtTableGenerator_q <= "100011101110000010001011";
WHEN "10000001" => memoryC4_uid54_sqrtTableGenerator_q <= "100100011110100110110110";
WHEN "10000010" => memoryC4_uid54_sqrtTableGenerator_q <= "100101001101100110001001";
WHEN "10000011" => memoryC4_uid54_sqrtTableGenerator_q <= "100101111010111110010000";
WHEN "10000100" => memoryC4_uid54_sqrtTableGenerator_q <= "100110100110110001001000";
WHEN "10000101" => memoryC4_uid54_sqrtTableGenerator_q <= "100111010001001010100111";
WHEN "10000110" => memoryC4_uid54_sqrtTableGenerator_q <= "100111111010000110110101";
WHEN "10000111" => memoryC4_uid54_sqrtTableGenerator_q <= "101000100001101101101101";
WHEN "10001000" => memoryC4_uid54_sqrtTableGenerator_q <= "101001001000000011011001";
WHEN "10001001" => memoryC4_uid54_sqrtTableGenerator_q <= "101001101101000111000101";
WHEN "10001010" => memoryC4_uid54_sqrtTableGenerator_q <= "101010010000111010101000";
WHEN "10001011" => memoryC4_uid54_sqrtTableGenerator_q <= "101010110011101000001011";
WHEN "10001100" => memoryC4_uid54_sqrtTableGenerator_q <= "101011010101001111100100";
WHEN "10001101" => memoryC4_uid54_sqrtTableGenerator_q <= "101011110101110100010100";
WHEN "10001110" => memoryC4_uid54_sqrtTableGenerator_q <= "101100010101010100000011";
WHEN "10001111" => memoryC4_uid54_sqrtTableGenerator_q <= "101100110011111000001011";
WHEN "10010000" => memoryC4_uid54_sqrtTableGenerator_q <= "101101010001011101011110";
WHEN "10010001" => memoryC4_uid54_sqrtTableGenerator_q <= "101101101110001001011111";
WHEN "10010010" => memoryC4_uid54_sqrtTableGenerator_q <= "101110001001111101011011";
WHEN "10010011" => memoryC4_uid54_sqrtTableGenerator_q <= "101110100100111001011001";
WHEN "10010100" => memoryC4_uid54_sqrtTableGenerator_q <= "101110111111000010010010";
WHEN "10010101" => memoryC4_uid54_sqrtTableGenerator_q <= "101111011000011010010001";
WHEN "10010110" => memoryC4_uid54_sqrtTableGenerator_q <= "101111110001000010000111";
WHEN "10010111" => memoryC4_uid54_sqrtTableGenerator_q <= "110000001000111001001111";
WHEN "10011000" => memoryC4_uid54_sqrtTableGenerator_q <= "110000100000000101100111";
WHEN "10011001" => memoryC4_uid54_sqrtTableGenerator_q <= "110000110110100110100110";
WHEN "10011010" => memoryC4_uid54_sqrtTableGenerator_q <= "110001001100011011101101";
WHEN "10011011" => memoryC4_uid54_sqrtTableGenerator_q <= "110001100001101010011101";
WHEN "10011100" => memoryC4_uid54_sqrtTableGenerator_q <= "110001110110010001110111";
WHEN "10011101" => memoryC4_uid54_sqrtTableGenerator_q <= "110010001010010110100101";
WHEN "10011110" => memoryC4_uid54_sqrtTableGenerator_q <= "110010011101110010010001";
WHEN "10011111" => memoryC4_uid54_sqrtTableGenerator_q <= "110010110000101101010100";
WHEN "10100000" => memoryC4_uid54_sqrtTableGenerator_q <= "110011000011000111001010";
WHEN "10100001" => memoryC4_uid54_sqrtTableGenerator_q <= "110011010100111111001010";
WHEN "10100010" => memoryC4_uid54_sqrtTableGenerator_q <= "110011100110010101010100";
WHEN "10100011" => memoryC4_uid54_sqrtTableGenerator_q <= "110011110111010001011001";
WHEN "10100100" => memoryC4_uid54_sqrtTableGenerator_q <= "110100000111101011111011";
WHEN "10100101" => memoryC4_uid54_sqrtTableGenerator_q <= "110100010111110000000111";
WHEN "10100110" => memoryC4_uid54_sqrtTableGenerator_q <= "110100100111010010010010";
WHEN "10100111" => memoryC4_uid54_sqrtTableGenerator_q <= "110100110110011110101011";
WHEN "10101000" => memoryC4_uid54_sqrtTableGenerator_q <= "110101000101001110010000";
WHEN "10101001" => memoryC4_uid54_sqrtTableGenerator_q <= "110101010011100100100010";
WHEN "10101010" => memoryC4_uid54_sqrtTableGenerator_q <= "110101100001100010110001";
WHEN "10101011" => memoryC4_uid54_sqrtTableGenerator_q <= "110101101111001010110110";
WHEN "10101100" => memoryC4_uid54_sqrtTableGenerator_q <= "110101111100011101100111";
WHEN "10101101" => memoryC4_uid54_sqrtTableGenerator_q <= "110110001001010101100000";
WHEN "10101110" => memoryC4_uid54_sqrtTableGenerator_q <= "110110010101111101011110";
WHEN "10101111" => memoryC4_uid54_sqrtTableGenerator_q <= "110110100010001110111110";
WHEN "10110000" => memoryC4_uid54_sqrtTableGenerator_q <= "110110101110001110100011";
WHEN "10110001" => memoryC4_uid54_sqrtTableGenerator_q <= "110110111001110111001101";
WHEN "10110010" => memoryC4_uid54_sqrtTableGenerator_q <= "110111000101001111100001";
WHEN "10110011" => memoryC4_uid54_sqrtTableGenerator_q <= "110111010000010101000000";
WHEN "10110100" => memoryC4_uid54_sqrtTableGenerator_q <= "110111011011000111100010";
WHEN "10110101" => memoryC4_uid54_sqrtTableGenerator_q <= "110111100101101001111010";
WHEN "10110110" => memoryC4_uid54_sqrtTableGenerator_q <= "110111101111111010111001";
WHEN "10110111" => memoryC4_uid54_sqrtTableGenerator_q <= "110111111001111110001110";
WHEN "10111000" => memoryC4_uid54_sqrtTableGenerator_q <= "111000000011101111100110";
WHEN "10111001" => memoryC4_uid54_sqrtTableGenerator_q <= "111000001101010001111110";
WHEN "10111010" => memoryC4_uid54_sqrtTableGenerator_q <= "111000010110100101101100";
WHEN "10111011" => memoryC4_uid54_sqrtTableGenerator_q <= "111000011111101111001011";
WHEN "10111100" => memoryC4_uid54_sqrtTableGenerator_q <= "111000101000100110100101";
WHEN "10111101" => memoryC4_uid54_sqrtTableGenerator_q <= "111000110001010000101101";
WHEN "10111110" => memoryC4_uid54_sqrtTableGenerator_q <= "111000111001101110110011";
WHEN "10111111" => memoryC4_uid54_sqrtTableGenerator_q <= "111001000010000001001111";
WHEN "11000000" => memoryC4_uid54_sqrtTableGenerator_q <= "111001001010000110110111";
WHEN "11000001" => memoryC4_uid54_sqrtTableGenerator_q <= "111001010001111101100010";
WHEN "11000010" => memoryC4_uid54_sqrtTableGenerator_q <= "111001011001101110010000";
WHEN "11000011" => memoryC4_uid54_sqrtTableGenerator_q <= "111001100001001101011000";
WHEN "11000100" => memoryC4_uid54_sqrtTableGenerator_q <= "111001101000100100101100";
WHEN "11000101" => memoryC4_uid54_sqrtTableGenerator_q <= "111001101111110010000010";
WHEN "11000110" => memoryC4_uid54_sqrtTableGenerator_q <= "111001110110110100101000";
WHEN "11000111" => memoryC4_uid54_sqrtTableGenerator_q <= "111001111101101011110111";
WHEN "11001000" => memoryC4_uid54_sqrtTableGenerator_q <= "111010000100011010110110";
WHEN "11001001" => memoryC4_uid54_sqrtTableGenerator_q <= "111010001010111101001010";
WHEN "11001010" => memoryC4_uid54_sqrtTableGenerator_q <= "111010010001011010101101";
WHEN "11001011" => memoryC4_uid54_sqrtTableGenerator_q <= "111010010111101010011100";
WHEN "11001100" => memoryC4_uid54_sqrtTableGenerator_q <= "111010011101110011001001";
WHEN "11001101" => memoryC4_uid54_sqrtTableGenerator_q <= "111010100011110100111101";
WHEN "11001110" => memoryC4_uid54_sqrtTableGenerator_q <= "111010101001101100000101";
WHEN "11001111" => memoryC4_uid54_sqrtTableGenerator_q <= "111010101111011101110101";
WHEN "11010000" => memoryC4_uid54_sqrtTableGenerator_q <= "111010110101000100111000";
WHEN "11010001" => memoryC4_uid54_sqrtTableGenerator_q <= "111010111010100011111001";
WHEN "11010010" => memoryC4_uid54_sqrtTableGenerator_q <= "111010111111111101101000";
WHEN "11010011" => memoryC4_uid54_sqrtTableGenerator_q <= "111011000101010010001111";
WHEN "11010100" => memoryC4_uid54_sqrtTableGenerator_q <= "111011001010011011001101";
WHEN "11010101" => memoryC4_uid54_sqrtTableGenerator_q <= "111011001111011101110100";
WHEN "11010110" => memoryC4_uid54_sqrtTableGenerator_q <= "111011010100011011110101";
WHEN "11010111" => memoryC4_uid54_sqrtTableGenerator_q <= "111011011001010010111100";
WHEN "11011000" => memoryC4_uid54_sqrtTableGenerator_q <= "111011011110000010110111";
WHEN "11011001" => memoryC4_uid54_sqrtTableGenerator_q <= "111011100010101101010110";
WHEN "11011010" => memoryC4_uid54_sqrtTableGenerator_q <= "111011100111001101101101";
WHEN "11011011" => memoryC4_uid54_sqrtTableGenerator_q <= "111011101011101101010100";
WHEN "11011100" => memoryC4_uid54_sqrtTableGenerator_q <= "111011110000000101110010";
WHEN "11011101" => memoryC4_uid54_sqrtTableGenerator_q <= "111011110100010110110100";
WHEN "11011110" => memoryC4_uid54_sqrtTableGenerator_q <= "111011111000100011011111";
WHEN "11011111" => memoryC4_uid54_sqrtTableGenerator_q <= "111011111100101001101100";
WHEN "11100000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100000000101011110100";
WHEN "11100001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100000100101001011101";
WHEN "11100010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100001000100001000011";
WHEN "11100011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100001100010001001010";
WHEN "11100100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010000000010001010";
WHEN "11100101" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010011101011111111";
WHEN "11100110" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010111010000100001";
WHEN "11100111" => memoryC4_uid54_sqrtTableGenerator_q <= "111100011010110000000111";
WHEN "11101000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100011110001101111110";
WHEN "11101001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100100001100101100111";
WHEN "11101010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100100100111001100011";
WHEN "11101011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101000000110101010";
WHEN "11101100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101011010010110101";
WHEN "11101101" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101110011011111110";
WHEN "11101110" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110001011111110001";
WHEN "11101111" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110100100001111101";
WHEN "11110000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110111011110100110";
WHEN "11110001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111010011000000100";
WHEN "11110010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111101001100001110";
WHEN "11110011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111111111110011110";
WHEN "11110100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101000010101111101110";
WHEN "11110101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101000101011100010001";
WHEN "11110110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001000000100001101";
WHEN "11110111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001010101011110100";
WHEN "11111000" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001101001101000000";
WHEN "11111001" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001111101101000010";
WHEN "11111010" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010010001011011111";
WHEN "11111011" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010100100110001101";
WHEN "11111100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010110111110000100";
WHEN "11111101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011001010000010000";
WHEN "11111110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011011100100010001";
WHEN "11111111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011101110100001010";
WHEN OTHERS =>
memoryC4_uid54_sqrtTableGenerator_q <= "101100000000001000110110";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid60_sqrtPolynomialEvaluator(ADD,59)@4
sumAHighB_uid60_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => memoryC4_uid54_sqrtTableGenerator_q(23)) & memoryC4_uid54_sqrtTableGenerator_q);
sumAHighB_uid60_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid59_sqrtPolynomialEvaluator_b(16)) & highBBits_uid59_sqrtPolynomialEvaluator_b);
sumAHighB_uid60_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid60_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid60_sqrtPolynomialEvaluator_b));
sumAHighB_uid60_sqrtPolynomialEvaluator_q <= sumAHighB_uid60_sqrtPolynomialEvaluator_o(24 downto 0);
--lowRangeB_uid58_sqrtPolynomialEvaluator(BITSELECT,57)@4
lowRangeB_uid58_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid58_sqrtPolynomialEvaluator_b <= lowRangeB_uid58_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid58_uid61_sqrtPolynomialEvaluator(BITJOIN,60)@4
s1_uid58_uid61_sqrtPolynomialEvaluator_q <= sumAHighB_uid60_sqrtPolynomialEvaluator_q & lowRangeB_uid58_sqrtPolynomialEvaluator_b;
--reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1(REG,130)@4
reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1_q <= s1_uid58_uid61_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor(LOGICAL,446)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_b <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_q <= not (ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_a or ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_b);
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg(REG,444)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q;
END IF;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena(REG,447)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,448)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_b <= VCC_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_a and ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_b;
--yT2_uid62_sqrtPolynomialEvaluator(BITSELECT,61)@1
yT2_uid62_sqrtPolynomialEvaluator_in <= X44dto0_uid33_fpSqrtTest_b;
yT2_uid62_sqrtPolynomialEvaluator_b <= yT2_uid62_sqrtPolynomialEvaluator_in(44 downto 21);
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440)
-- every=1, low=0, high=1, step=1, init=1
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1));
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_s <= VCC_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ia <= yT2_uid62_sqrtPolynomialEvaluator_b;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0);
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg(DELAY,438)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_q, xout => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg_q, clk => clk, aclr => areset );
--prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator(MULT,89)@5
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_b);
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg_q;
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_b <= reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1_q;
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_pr,50));
END IF;
END PROCESS;
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_q <= prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator(BITSELECT,90)@8
prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_in <= prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_in(49 downto 23);
--highBBits_uid65_sqrtPolynomialEvaluator(BITSELECT,64)@8
highBBits_uid65_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_b;
highBBits_uid65_sqrtPolynomialEvaluator_b <= highBBits_uid65_sqrtPolynomialEvaluator_in(26 downto 1);
--reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1(REG,131)@8
reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q <= highBBits_uid65_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor(LOGICAL,422)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_b <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_q <= not (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_a or ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_b);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_mem_top(CONSTANT,418)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_mem_top_q <= "0101";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp(LOGICAL,419)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_mem_top_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_q <= "1" when ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_a = ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_b else "0";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg(REG,420)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena(REG,423)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_q = "1") THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd(LOGICAL,424)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_b <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_a and ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_b;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt(COUNTER,414)
-- every=1, low=0, high=5, step=1, init=1
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i = 4 THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i - 5;
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i,3));
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg(REG,415)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux(MUX,416)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_s, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem(DUALMEM,413)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_reset0 <= areset;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ia <= addrTable_uid32_fpSqrtTest_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_aa <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ab <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_iq,
address_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_aa,
data_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ia
);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_iq(7 downto 0);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg(DELAY,412)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC3_uid53_sqrtTableGenerator(LOOKUP,52)@8
memoryC3_uid53_sqrtTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid53_sqrtTableGenerator_q <= "001111111111111111111110110111010";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg_q) IS
WHEN "00000000" => memoryC3_uid53_sqrtTableGenerator_q <= "001111111111111111111110110111010";
WHEN "00000001" => memoryC3_uid53_sqrtTableGenerator_q <= "001111101100010001010010000100011";
WHEN "00000010" => memoryC3_uid53_sqrtTableGenerator_q <= "001111011001000100011000101011111";
WHEN "00000011" => memoryC3_uid53_sqrtTableGenerator_q <= "001111000110011000000111111111100";
WHEN "00000100" => memoryC3_uid53_sqrtTableGenerator_q <= "001110110100001011011001101101100";
WHEN "00000101" => memoryC3_uid53_sqrtTableGenerator_q <= "001110100010011101001010011010001";
WHEN "00000110" => memoryC3_uid53_sqrtTableGenerator_q <= "001110010001001100011000100000111";
WHEN "00000111" => memoryC3_uid53_sqrtTableGenerator_q <= "001110000000011000000100111001011";
WHEN "00001000" => memoryC3_uid53_sqrtTableGenerator_q <= "001101101111111111010100111001001";
WHEN "00001001" => memoryC3_uid53_sqrtTableGenerator_q <= "001101100000000001001110000101000";
WHEN "00001010" => memoryC3_uid53_sqrtTableGenerator_q <= "001101010000011100111001101000110";
WHEN "00001011" => memoryC3_uid53_sqrtTableGenerator_q <= "001101000001010001100010010001111";
WHEN "00001100" => memoryC3_uid53_sqrtTableGenerator_q <= "001100110010011110010100100010000";
WHEN "00001101" => memoryC3_uid53_sqrtTableGenerator_q <= "001100100100000010011110101011100";
WHEN "00001110" => memoryC3_uid53_sqrtTableGenerator_q <= "001100010101111101010011100100111";
WHEN "00001111" => memoryC3_uid53_sqrtTableGenerator_q <= "001100001000001110000011110010001";
WHEN "00010000" => memoryC3_uid53_sqrtTableGenerator_q <= "001011111010110100000101110011001";
WHEN "00010001" => memoryC3_uid53_sqrtTableGenerator_q <= "001011101101101110101101000100101";
WHEN "00010010" => memoryC3_uid53_sqrtTableGenerator_q <= "001011100000111101010011000110001";
WHEN "00010011" => memoryC3_uid53_sqrtTableGenerator_q <= "001011010100011111010001001001111";
WHEN "00010100" => memoryC3_uid53_sqrtTableGenerator_q <= "001011001000010100000000010010011";
WHEN "00010101" => memoryC3_uid53_sqrtTableGenerator_q <= "001010111100011010111100100111001";
WHEN "00010110" => memoryC3_uid53_sqrtTableGenerator_q <= "001010110000110011100011111110101";
WHEN "00010111" => memoryC3_uid53_sqrtTableGenerator_q <= "001010100101011101010100111110011";
WHEN "00011000" => memoryC3_uid53_sqrtTableGenerator_q <= "001010011010010111101110001010010";
WHEN "00011001" => memoryC3_uid53_sqrtTableGenerator_q <= "001010001111100010010001101010101";
WHEN "00011010" => memoryC3_uid53_sqrtTableGenerator_q <= "001010000100111100100000010000111";
WHEN "00011011" => memoryC3_uid53_sqrtTableGenerator_q <= "001001111010100101111110011001010";
WHEN "00011100" => memoryC3_uid53_sqrtTableGenerator_q <= "001001110000011110001111100001011";
WHEN "00011101" => memoryC3_uid53_sqrtTableGenerator_q <= "001001100110100100111000001110000";
WHEN "00011110" => memoryC3_uid53_sqrtTableGenerator_q <= "001001011100111001011101101010100";
WHEN "00011111" => memoryC3_uid53_sqrtTableGenerator_q <= "001001010011011011101000101001110";
WHEN "00100000" => memoryC3_uid53_sqrtTableGenerator_q <= "001001001010001010111111010011001";
WHEN "00100001" => memoryC3_uid53_sqrtTableGenerator_q <= "001001000001000111001010100100010";
WHEN "00100010" => memoryC3_uid53_sqrtTableGenerator_q <= "001000111000001111110100100001110";
WHEN "00100011" => memoryC3_uid53_sqrtTableGenerator_q <= "001000101111100100100101111011100";
WHEN "00100100" => memoryC3_uid53_sqrtTableGenerator_q <= "001000100111000101001010011100010";
WHEN "00100101" => memoryC3_uid53_sqrtTableGenerator_q <= "001000011110110001001101101000001";
WHEN "00100110" => memoryC3_uid53_sqrtTableGenerator_q <= "001000010110101000011010100000111";
WHEN "00100111" => memoryC3_uid53_sqrtTableGenerator_q <= "001000001110101010011111100000001";
WHEN "00101000" => memoryC3_uid53_sqrtTableGenerator_q <= "001000000110110111001001000100011";
WHEN "00101001" => memoryC3_uid53_sqrtTableGenerator_q <= "000111111111001110000101111001000";
WHEN "00101010" => memoryC3_uid53_sqrtTableGenerator_q <= "000111110111101111000100100101000";
WHEN "00101011" => memoryC3_uid53_sqrtTableGenerator_q <= "000111110000011001110011010011110";
WHEN "00101100" => memoryC3_uid53_sqrtTableGenerator_q <= "000111101001001110000011000111001";
WHEN "00101101" => memoryC3_uid53_sqrtTableGenerator_q <= "000111100010001011100011011101001";
WHEN "00101110" => memoryC3_uid53_sqrtTableGenerator_q <= "000111011011010010000100110011101";
WHEN "00101111" => memoryC3_uid53_sqrtTableGenerator_q <= "000111010100100001011000100100111";
WHEN "00110000" => memoryC3_uid53_sqrtTableGenerator_q <= "000111001101111001010001110110101";
WHEN "00110001" => memoryC3_uid53_sqrtTableGenerator_q <= "000111000111011001100000001100010";
WHEN "00110010" => memoryC3_uid53_sqrtTableGenerator_q <= "000111000001000001111000100101110";
WHEN "00110011" => memoryC3_uid53_sqrtTableGenerator_q <= "000110111010110010001100110011001";
WHEN "00110100" => memoryC3_uid53_sqrtTableGenerator_q <= "000110110100101010010000100000110";
WHEN "00110101" => memoryC3_uid53_sqrtTableGenerator_q <= "000110101110101001110110010110101";
WHEN "00110110" => memoryC3_uid53_sqrtTableGenerator_q <= "000110101000110000110011011101100";
WHEN "00110111" => memoryC3_uid53_sqrtTableGenerator_q <= "000110100010111110111101011110110";
WHEN "00111000" => memoryC3_uid53_sqrtTableGenerator_q <= "000110011101010100000110101010100";
WHEN "00111001" => memoryC3_uid53_sqrtTableGenerator_q <= "000110010111110000000110000111001";
WHEN "00111010" => memoryC3_uid53_sqrtTableGenerator_q <= "000110010010010010110000011100001";
WHEN "00111011" => memoryC3_uid53_sqrtTableGenerator_q <= "000110001100111011111011100001100";
WHEN "00111100" => memoryC3_uid53_sqrtTableGenerator_q <= "000110000111101011011100111110000";
WHEN "00111101" => memoryC3_uid53_sqrtTableGenerator_q <= "000110000010100001001011111100001";
WHEN "00111110" => memoryC3_uid53_sqrtTableGenerator_q <= "000101111101011100111110011000101";
WHEN "00111111" => memoryC3_uid53_sqrtTableGenerator_q <= "000101111000011110101100110111000";
WHEN "01000000" => memoryC3_uid53_sqrtTableGenerator_q <= "000101110011100110001011110010110";
WHEN "01000001" => memoryC3_uid53_sqrtTableGenerator_q <= "000101101110110011010100010111111";
WHEN "01000010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101101010000101111101110001000";
WHEN "01000011" => memoryC3_uid53_sqrtTableGenerator_q <= "000101100101011110000000111100100";
WHEN "01000100" => memoryC3_uid53_sqrtTableGenerator_q <= "000101100000111011010100001101001";
WHEN "01000101" => memoryC3_uid53_sqrtTableGenerator_q <= "000101011100011101110000100110111";
WHEN "01000110" => memoryC3_uid53_sqrtTableGenerator_q <= "000101011000000101001111001110000";
WHEN "01000111" => memoryC3_uid53_sqrtTableGenerator_q <= "000101010011110001101000110001000";
WHEN "01001000" => memoryC3_uid53_sqrtTableGenerator_q <= "000101001111100010110101100101101";
WHEN "01001001" => memoryC3_uid53_sqrtTableGenerator_q <= "000101001011011000101111000011101";
WHEN "01001010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000111010011001110101100111";
WHEN "01001011" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000011010010001101001101001";
WHEN "01001100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100111111010101100101010001000";
WHEN "01001101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100111011011101010000001010011";
WHEN "01001110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110111101001000111100011110";
WHEN "01001111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110011111001000111010100010";
WHEN "01010000" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110000001101001000001110011";
WHEN "01010001" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101100100101000101100101100";
WHEN "01010010" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101001000000111000010111010";
WHEN "01010011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100101100000011101011000000";
WHEN "01010100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100010000011101110010011100";
WHEN "01010101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011110101010100111001000010";
WHEN "01010110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011011010101000010001100010";
WHEN "01010111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011000000010111010010001101";
WHEN "01011000" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010100110100001100010000010";
WHEN "01011001" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010001101000110010111100100";
WHEN "01011010" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001110100000101001011010100";
WHEN "01011011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001011011011101100100110110";
WHEN "01011100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001000011001110111010011000";
WHEN "01011101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000101011011000101101010011";
WHEN "01011110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000010011111010100010101000";
WHEN "01011111" => memoryC3_uid53_sqrtTableGenerator_q <= "000011111111100110011101110011011";
WHEN "01100000" => memoryC3_uid53_sqrtTableGenerator_q <= "000011111100110000100000000111100";
WHEN "01100001" => memoryC3_uid53_sqrtTableGenerator_q <= "000011111001111101010111110111111";
WHEN "01100010" => memoryC3_uid53_sqrtTableGenerator_q <= "000011110111001100111111111110111";
WHEN "01100011" => memoryC3_uid53_sqrtTableGenerator_q <= "000011110100011111010100100100100";
WHEN "01100100" => memoryC3_uid53_sqrtTableGenerator_q <= "000011110001110100010100100111011";
WHEN "01100101" => memoryC3_uid53_sqrtTableGenerator_q <= "000011101111001011111011000100011";
WHEN "01100110" => memoryC3_uid53_sqrtTableGenerator_q <= "000011101100100110000100110011101";
WHEN "01100111" => memoryC3_uid53_sqrtTableGenerator_q <= "000011101010000010101110000001001";
WHEN "01101000" => memoryC3_uid53_sqrtTableGenerator_q <= "000011100111100001110101001111000";
WHEN "01101001" => memoryC3_uid53_sqrtTableGenerator_q <= "000011100101000011010111011001101";
WHEN "01101010" => memoryC3_uid53_sqrtTableGenerator_q <= "000011100010100111001111111110111";
WHEN "01101011" => memoryC3_uid53_sqrtTableGenerator_q <= "000011100000001101011101000110100";
WHEN "01101100" => memoryC3_uid53_sqrtTableGenerator_q <= "000011011101110101111011000100000";
WHEN "01101101" => memoryC3_uid53_sqrtTableGenerator_q <= "000011011011100000101000100100000";
WHEN "01101110" => memoryC3_uid53_sqrtTableGenerator_q <= "000011011001001101100001011111110";
WHEN "01101111" => memoryC3_uid53_sqrtTableGenerator_q <= "000011010110111100100100010001111";
WHEN "01110000" => memoryC3_uid53_sqrtTableGenerator_q <= "000011010100101101101101010101111";
WHEN "01110001" => memoryC3_uid53_sqrtTableGenerator_q <= "000011010010100000111011100100000";
WHEN "01110010" => memoryC3_uid53_sqrtTableGenerator_q <= "000011010000010110001011110000001";
WHEN "01110011" => memoryC3_uid53_sqrtTableGenerator_q <= "000011001110001101011011100100111";
WHEN "01110100" => memoryC3_uid53_sqrtTableGenerator_q <= "000011001100000110100111111100100";
WHEN "01110101" => memoryC3_uid53_sqrtTableGenerator_q <= "000011001010000001101110111101011";
WHEN "01110110" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000111111110101110101101100";
WHEN "01110111" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000101111101100101100011011";
WHEN "01111000" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000011111110001111111101111";
WHEN "01111001" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000010000000101100111001111";
WHEN "01111010" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000000000100111001111010111";
WHEN "01111011" => memoryC3_uid53_sqrtTableGenerator_q <= "000010111110001010110101010110011";
WHEN "01111100" => memoryC3_uid53_sqrtTableGenerator_q <= "000010111100010010011101000100001";
WHEN "01111101" => memoryC3_uid53_sqrtTableGenerator_q <= "000010111010011011101111010101010";
WHEN "01111110" => memoryC3_uid53_sqrtTableGenerator_q <= "000010111000100110101000111001001";
WHEN "01111111" => memoryC3_uid53_sqrtTableGenerator_q <= "000010110110110011001010001100111";
WHEN "10000000" => memoryC3_uid53_sqrtTableGenerator_q <= "010110101000001001110111100000000";
WHEN "10000001" => memoryC3_uid53_sqrtTableGenerator_q <= "010110001100010000001001100111010";
WHEN "10000010" => memoryC3_uid53_sqrtTableGenerator_q <= "010101110001000110001101101001100";
WHEN "10000011" => memoryC3_uid53_sqrtTableGenerator_q <= "010101010110101010011100101011011";
WHEN "10000100" => memoryC3_uid53_sqrtTableGenerator_q <= "010100111100111011010011000010100";
WHEN "10000101" => memoryC3_uid53_sqrtTableGenerator_q <= "010100100011110111001110110000110";
WHEN "10000110" => memoryC3_uid53_sqrtTableGenerator_q <= "010100001011011100110101100110101";
WHEN "10000111" => memoryC3_uid53_sqrtTableGenerator_q <= "010011110011101010101110010001011";
WHEN "10001000" => memoryC3_uid53_sqrtTableGenerator_q <= "010011011100011111100011100010111";
WHEN "10001001" => memoryC3_uid53_sqrtTableGenerator_q <= "010011000101111010000101000111101";
WHEN "10001010" => memoryC3_uid53_sqrtTableGenerator_q <= "010010101111111001000101001000011";
WHEN "10001011" => memoryC3_uid53_sqrtTableGenerator_q <= "010010011010011011010110100110101";
WHEN "10001100" => memoryC3_uid53_sqrtTableGenerator_q <= "010010000101011111110010001001000";
WHEN "10001101" => memoryC3_uid53_sqrtTableGenerator_q <= "010001110001000101010010001000010";
WHEN "10001110" => memoryC3_uid53_sqrtTableGenerator_q <= "010001011101001010110101000000000";
WHEN "10001111" => memoryC3_uid53_sqrtTableGenerator_q <= "010001001001101111011001000001000";
WHEN "10010000" => memoryC3_uid53_sqrtTableGenerator_q <= "010000110110110010000001101111111";
WHEN "10010001" => memoryC3_uid53_sqrtTableGenerator_q <= "010000100100010001110010111000000";
WHEN "10010010" => memoryC3_uid53_sqrtTableGenerator_q <= "010000010010001101110011101101010";
WHEN "10010011" => memoryC3_uid53_sqrtTableGenerator_q <= "010000000000100101001101011110000";
WHEN "10010100" => memoryC3_uid53_sqrtTableGenerator_q <= "001111101111010111001010011110000";
WHEN "10010101" => memoryC3_uid53_sqrtTableGenerator_q <= "001111011110100010110111100111010";
WHEN "10010110" => memoryC3_uid53_sqrtTableGenerator_q <= "001111001110000111100011111111100";
WHEN "10010111" => memoryC3_uid53_sqrtTableGenerator_q <= "001110111110000100100000101010000";
WHEN "10011000" => memoryC3_uid53_sqrtTableGenerator_q <= "001110101110011000111110111010101";
WHEN "10011001" => memoryC3_uid53_sqrtTableGenerator_q <= "001110011111000100010011001001001";
WHEN "10011010" => memoryC3_uid53_sqrtTableGenerator_q <= "001110010000000101110011100011000";
WHEN "10011011" => memoryC3_uid53_sqrtTableGenerator_q <= "001110000001011100110101110111000";
WHEN "10011100" => memoryC3_uid53_sqrtTableGenerator_q <= "001101110011001000110011001100111";
WHEN "10011101" => memoryC3_uid53_sqrtTableGenerator_q <= "001101100101001001000100100110001";
WHEN "10011110" => memoryC3_uid53_sqrtTableGenerator_q <= "001101010111011101000110111101000";
WHEN "10011111" => memoryC3_uid53_sqrtTableGenerator_q <= "001101001010000100010101000101011";
WHEN "10100000" => memoryC3_uid53_sqrtTableGenerator_q <= "001100111100111110001100111001001";
WHEN "10100001" => memoryC3_uid53_sqrtTableGenerator_q <= "001100110000001010001101101001100";
WHEN "10100010" => memoryC3_uid53_sqrtTableGenerator_q <= "001100100011100111110111100000010";
WHEN "10100011" => memoryC3_uid53_sqrtTableGenerator_q <= "001100010111010110101001110111111";
WHEN "10100100" => memoryC3_uid53_sqrtTableGenerator_q <= "001100001011010110001000110101101";
WHEN "10100101" => memoryC3_uid53_sqrtTableGenerator_q <= "001011111111100101110100110110000";
WHEN "10100110" => memoryC3_uid53_sqrtTableGenerator_q <= "001011110100000101010101000001011";
WHEN "10100111" => memoryC3_uid53_sqrtTableGenerator_q <= "001011101000110100001011011011101";
WHEN "10101000" => memoryC3_uid53_sqrtTableGenerator_q <= "001011011101110001111111110010000";
WHEN "10101001" => memoryC3_uid53_sqrtTableGenerator_q <= "001011010010111110011000001000000";
WHEN "10101010" => memoryC3_uid53_sqrtTableGenerator_q <= "001011001000011000111011101010101";
WHEN "10101011" => memoryC3_uid53_sqrtTableGenerator_q <= "001010111110000001010010100011011";
WHEN "10101100" => memoryC3_uid53_sqrtTableGenerator_q <= "001010110011110111000101011111001";
WHEN "10101101" => memoryC3_uid53_sqrtTableGenerator_q <= "001010101001111001111111111010101";
WHEN "10101110" => memoryC3_uid53_sqrtTableGenerator_q <= "001010100000001001101001101111110";
WHEN "10101111" => memoryC3_uid53_sqrtTableGenerator_q <= "001010010110100101101111101101001";
WHEN "10110000" => memoryC3_uid53_sqrtTableGenerator_q <= "001010001101001101111100101000101";
WHEN "10110001" => memoryC3_uid53_sqrtTableGenerator_q <= "001010000100000001111110001110000";
WHEN "10110010" => memoryC3_uid53_sqrtTableGenerator_q <= "001001111011000001100000001011001";
WHEN "10110011" => memoryC3_uid53_sqrtTableGenerator_q <= "001001110010001100010000100101000";
WHEN "10110100" => memoryC3_uid53_sqrtTableGenerator_q <= "001001101001100001111101110101010";
WHEN "10110101" => memoryC3_uid53_sqrtTableGenerator_q <= "001001100001000010010101111110010";
WHEN "10110110" => memoryC3_uid53_sqrtTableGenerator_q <= "001001011000101101001000100101110";
WHEN "10110111" => memoryC3_uid53_sqrtTableGenerator_q <= "001001010000100010000100101011100";
WHEN "10111000" => memoryC3_uid53_sqrtTableGenerator_q <= "001001001000100000111011011101101";
WHEN "10111001" => memoryC3_uid53_sqrtTableGenerator_q <= "001001000000101001011101000100111";
WHEN "10111010" => memoryC3_uid53_sqrtTableGenerator_q <= "001000111000111011011010100010000";
WHEN "10111011" => memoryC3_uid53_sqrtTableGenerator_q <= "001000110001010110100100011101100";
WHEN "10111100" => memoryC3_uid53_sqrtTableGenerator_q <= "001000101001111010101110110001011";
WHEN "10111101" => memoryC3_uid53_sqrtTableGenerator_q <= "001000100010100111101010110101010";
WHEN "10111110" => memoryC3_uid53_sqrtTableGenerator_q <= "001000011011011101001011000000100";
WHEN "10111111" => memoryC3_uid53_sqrtTableGenerator_q <= "001000010100011011000010100110011";
WHEN "11000000" => memoryC3_uid53_sqrtTableGenerator_q <= "001000001101100001000101010110001";
WHEN "11000001" => memoryC3_uid53_sqrtTableGenerator_q <= "001000000110101111000111111000011";
WHEN "11000010" => memoryC3_uid53_sqrtTableGenerator_q <= "001000000000000100111100000101000";
WHEN "11000011" => memoryC3_uid53_sqrtTableGenerator_q <= "000111111001100010011001011111000";
WHEN "11000100" => memoryC3_uid53_sqrtTableGenerator_q <= "000111110011000111010010100110110";
WHEN "11000101" => memoryC3_uid53_sqrtTableGenerator_q <= "000111101100110011011101010010101";
WHEN "11000110" => memoryC3_uid53_sqrtTableGenerator_q <= "000111100110100110101111000111110";
WHEN "11000111" => memoryC3_uid53_sqrtTableGenerator_q <= "000111100000100000111110001101111";
WHEN "11001000" => memoryC3_uid53_sqrtTableGenerator_q <= "000111011010100001111111110000100";
WHEN "11001001" => memoryC3_uid53_sqrtTableGenerator_q <= "000111010100101001101011010010011";
WHEN "11001010" => memoryC3_uid53_sqrtTableGenerator_q <= "000111001110110111110101011100110";
WHEN "11001011" => memoryC3_uid53_sqrtTableGenerator_q <= "000111001001001100010111011001000";
WHEN "11001100" => memoryC3_uid53_sqrtTableGenerator_q <= "000111000011100111000110011110100";
WHEN "11001101" => memoryC3_uid53_sqrtTableGenerator_q <= "000110111110000111111010001001100";
WHEN "11001110" => memoryC3_uid53_sqrtTableGenerator_q <= "000110111000101110101010110101100";
WHEN "11001111" => memoryC3_uid53_sqrtTableGenerator_q <= "000110110011011011001111001010010";
WHEN "11010000" => memoryC3_uid53_sqrtTableGenerator_q <= "000110101110001101100000010101111";
WHEN "11010001" => memoryC3_uid53_sqrtTableGenerator_q <= "000110101001000101010110000001111";
WHEN "11010010" => memoryC3_uid53_sqrtTableGenerator_q <= "000110100100000010100111111110001";
WHEN "11010011" => memoryC3_uid53_sqrtTableGenerator_q <= "000110011111000101001110101100110";
WHEN "11010100" => memoryC3_uid53_sqrtTableGenerator_q <= "000110011010001101000100110000011";
WHEN "11010101" => memoryC3_uid53_sqrtTableGenerator_q <= "000110010101011010000001110101010";
WHEN "11010110" => memoryC3_uid53_sqrtTableGenerator_q <= "000110010000101011111110100101111";
WHEN "11010111" => memoryC3_uid53_sqrtTableGenerator_q <= "000110001100000010110100111100110";
WHEN "11011000" => memoryC3_uid53_sqrtTableGenerator_q <= "000110000111011110011110101101001";
WHEN "11011001" => memoryC3_uid53_sqrtTableGenerator_q <= "000110000010111110110100111100100";
WHEN "11011010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101111110100011110010101010110";
WHEN "11011011" => memoryC3_uid53_sqrtTableGenerator_q <= "000101111010001101001111101100111";
WHEN "11011100" => memoryC3_uid53_sqrtTableGenerator_q <= "000101110101111011000111101010111";
WHEN "11011101" => memoryC3_uid53_sqrtTableGenerator_q <= "000101110001101101010100111011000";
WHEN "11011110" => memoryC3_uid53_sqrtTableGenerator_q <= "000101101101100011110001010010100";
WHEN "11011111" => memoryC3_uid53_sqrtTableGenerator_q <= "000101101001011110010111101110100";
WHEN "11100000" => memoryC3_uid53_sqrtTableGenerator_q <= "000101100101011101000010011010000";
WHEN "11100001" => memoryC3_uid53_sqrtTableGenerator_q <= "000101100001011111101100010011111";
WHEN "11100010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101011101100110010000100111101";
WHEN "11100011" => memoryC3_uid53_sqrtTableGenerator_q <= "000101011001110000101010111110100";
WHEN "11100100" => memoryC3_uid53_sqrtTableGenerator_q <= "000101010101111110110100011100101";
WHEN "11100101" => memoryC3_uid53_sqrtTableGenerator_q <= "000101010010010000101010010000100";
WHEN "11100110" => memoryC3_uid53_sqrtTableGenerator_q <= "000101001110100110000111100010110";
WHEN "11100111" => memoryC3_uid53_sqrtTableGenerator_q <= "000101001010111111000111100110001";
WHEN "11101000" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000111011011100101010100001";
WHEN "11101001" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000011111011011101100010111";
WHEN "11101010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000000011110101011100001101";
WHEN "11101011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100111101000101001100000100010";
WHEN "11101100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100111001101110111001100010000";
WHEN "11101101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110110011011110000101111110";
WHEN "11101110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110011001011101110011011111";
WHEN "11101111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101111111110101101111101001";
WHEN "11110000" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101100110100101100101011010";
WHEN "11110001" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101001101101100110100111010";
WHEN "11110010" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100110101001011000101001000";
WHEN "11110011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100011100111111110100101110";
WHEN "11110100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100000101001010101000110001";
WHEN "11110101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011101101101011001101010000";
WHEN "11110110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011010110100001001001111011";
WHEN "11110111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010111111101011111100111110";
WHEN "11111000" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010101001001011011010101100";
WHEN "11111001" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010010010111111000000111011";
WHEN "11111010" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001111101000110011001001101";
WHEN "11111011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001100111100001010001101001";
WHEN "11111100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001010010001111010010011100";
WHEN "11111101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000111101010000001011001100";
WHEN "11111110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000101000100011011000101011";
WHEN "11111111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000010100001000110000110010";
WHEN OTHERS =>
memoryC3_uid53_sqrtTableGenerator_q <= "001111111111111111111110110111010";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid66_sqrtPolynomialEvaluator(ADD,65)@9
sumAHighB_uid66_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => memoryC3_uid53_sqrtTableGenerator_q(32)) & memoryC3_uid53_sqrtTableGenerator_q);
sumAHighB_uid66_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q(25)) & reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid66_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid66_sqrtPolynomialEvaluator_b));
sumAHighB_uid66_sqrtPolynomialEvaluator_q <= sumAHighB_uid66_sqrtPolynomialEvaluator_o(33 downto 0);
--lowRangeB_uid64_sqrtPolynomialEvaluator(BITSELECT,63)@8
lowRangeB_uid64_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid64_sqrtPolynomialEvaluator_b <= lowRangeB_uid64_sqrtPolynomialEvaluator_in(0 downto 0);
--ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a(DELAY,217)@8
ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid64_sqrtPolynomialEvaluator_b, xout => ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--s2_uid64_uid67_sqrtPolynomialEvaluator(BITJOIN,66)@9
s2_uid64_uid67_sqrtPolynomialEvaluator_q <= sumAHighB_uid66_sqrtPolynomialEvaluator_q & ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a_q;
--reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1(REG,132)@9
reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1_q <= s2_uid64_uid67_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor(LOGICAL,459)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_b <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_q <= not (ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_a or ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_b);
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,455)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_mem_top_q <= "0110";
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp(LOGICAL,456)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_a <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_mem_top_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_a = ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg(REG,457)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena(REG,460)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_b <= VCC_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_a and ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_b;
--yT3_uid68_sqrtPolynomialEvaluator(BITSELECT,67)@1
yT3_uid68_sqrtPolynomialEvaluator_in <= X44dto0_uid33_fpSqrtTest_b;
yT3_uid68_sqrtPolynomialEvaluator_b <= yT3_uid68_sqrtPolynomialEvaluator_in(44 downto 12);
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,451)
-- every=1, low=0, high=6, step=1, init=1
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 5 THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 6;
ELSE
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i,3));
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg(REG,452)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,453)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_s <= VCC_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,450)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ia <= yT3_uid68_sqrtPolynomialEvaluator_b;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 3,
numwords_a => 7,
width_b => 33,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_iq(32 downto 0);
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg(DELAY,449)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_q, xout => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg_q, clk => clk, aclr => areset );
--prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator(MULT,92)@10
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_b);
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg_q;
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_b <= reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1_q;
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_pr,68));
END IF;
END PROCESS;
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_q <= prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator(BITSELECT,93)@13
prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_in <= prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_in(67 downto 34);
--highBBits_uid71_sqrtPolynomialEvaluator(BITSELECT,70)@13
highBBits_uid71_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_b;
highBBits_uid71_sqrtPolynomialEvaluator_b <= highBBits_uid71_sqrtPolynomialEvaluator_in(33 downto 1);
--reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1(REG,133)@13
reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q <= highBBits_uid71_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor(LOGICAL,409)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_b <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_q <= not (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_a or ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_b);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_mem_top(CONSTANT,405)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_mem_top_q <= "01010";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp(LOGICAL,406)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_mem_top_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_q <= "1" when ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_a = ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_b else "0";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg(REG,407)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena(REG,410)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_q = "1") THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd(LOGICAL,411)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_b <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_a and ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_b;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt(COUNTER,401)
-- every=1, low=0, high=10, step=1, init=1
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i = 9 THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i - 10;
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i,4));
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg(REG,402)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux(MUX,403)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_s, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem(DUALMEM,400)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_reset0 <= areset;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ia <= addrTable_uid32_fpSqrtTest_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_aa <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ab <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_iq,
address_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_aa,
data_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ia
);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_iq(7 downto 0);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg(DELAY,399)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC2_uid52_sqrtTableGenerator(LOOKUP,51)@13
memoryC2_uid52_sqrtTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid52_sqrtTableGenerator_q <= "1100000000000000000000000000000001000010";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg_q) IS
WHEN "00000000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000000000000000000000000000001000010";
WHEN "00000001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000010111110001001000101011001110000";
WHEN "00000010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000101111000101000100110010100110010";
WHEN "00000011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001000101111100100110001011011010000";
WHEN "00000100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001011100011000011100111110000000101";
WHEN "00000101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001110010011001010111101010101110111";
WHEN "00000110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010001000000000000011001110010011100";
WHEN "00000111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010011101001101001011000101110111001";
WHEN "00001000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010110010000001011001010010001101000";
WHEN "00001001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011000110011101010110011100011101000";
WHEN "00001010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011011010100001101001111000110001010";
WHEN "00001011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011101110001110111001101010001100100";
WHEN "00001100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100000001100101101010100101100111111";
WHEN "00001101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100010100100110100000010100111100111";
WHEN "00001110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100100111010001111101011001010101101";
WHEN "00001111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100111001101000100011001111011000110";
WHEN "00010000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101001011101010110010010000000000001";
WHEN "00010001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101011101011001001001110100111100110";
WHEN "00010010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101101110110100001000011001001000101";
WHEN "00010011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101111111111100001011011100010101101";
WHEN "00010100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110010000110001101111100101011011110";
WHEN "00010101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110100001010101010000100011101100010";
WHEN "00010110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110110001100111001001010001001001001";
WHEN "00010111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111000001100111110011110100101110000";
WHEN "00011000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111010001010111101001100100001010100";
WHEN "00011001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111100000110111000011000101001011010";
WHEN "00011010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111110000000110011000001111111111110";
WHEN "00011011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111111111000110000000010000000011001";
WHEN "00011100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000001101110110010001100110011100101";
WHEN "00011101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000011100010111100010001011000001100";
WHEN "00011110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000101010101010000111001101111001101";
WHEN "00011111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000111000101110010101011000001100011";
WHEN "00100000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001000110100100100000101110101001011";
WHEN "00100001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001010100001100111100110001110000001";
WHEN "00100010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001100001100111111100011111010001100";
WHEN "00100011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001101110110101110010010011111110011";
WHEN "00100100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001111011110110110000001011110011110";
WHEN "00100101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010001000101011000111100011101001111";
WHEN "00100110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010010101010011001001011010011001010";
WHEN "00100111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010100001101111000110010001000110010";
WHEN "00101000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010101101111111001110001101000110010";
WHEN "00101001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010111010000011110000111000000010011";
WHEN "00101010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011000101111100111101100001001100100";
WHEN "00101011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011010001101011000010111110011100010";
WHEN "00101100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011011101001110001111101100010111110";
WHEN "00101101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011101000100110110001101111111100111";
WHEN "00101110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011110011110100110110110110110011010";
WHEN "00101111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011111110111000101100010111111100010";
WHEN "00110000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100001001110010011111010100001110010";
WHEN "00110001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100010100100010011100011000010010010";
WHEN "00110010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100011111001000101111111011000111001";
WHEN "00110011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100101001100101100110000000101010010";
WHEN "00110100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100110011111001001010011001010000000";
WHEN "00110101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100111110000011101000100010110111001";
WHEN "00110110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101001000000101001011101000111000010";
WHEN "00110111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101010001111101111110100101000110110";
WHEN "00111000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101011011101110001100000001000011001";
WHEN "00111001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101100101010101111110010100110001000";
WHEN "00111010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101101110110101011111101000110011011";
WHEN "00111011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101111000001100111001110101111110010";
WHEN "00111100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110000001011100010110100110000100000";
WHEN "00111101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110001010100011111111010011111000011";
WHEN "00111110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110010011100011111101001100010101000";
WHEN "00111111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110011100011100011001001101111010001";
WHEN "01000000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110100101001101011100001010101010010";
WHEN "01000001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110101101110111001110100110100010001";
WHEN "01000010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110110110011001111000111001010011001";
WHEN "01000011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110111110110101100011001110000001111";
WHEN "01000100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111000111001010010101100100011010011";
WHEN "01000101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111001111011000010111101111111100100";
WHEN "01000110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111010111011111110001011000110011111";
WHEN "01000111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111011111100000101001111100010001110";
WHEN "01001000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111100111011011001000101101000010111";
WHEN "01001001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111101111001111010100110011001001100";
WHEN "01001010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111110110111101010101001100100011000";
WHEN "01001011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111111110100101010000101101011110101";
WHEN "01001100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000000110000111001110000000001110010";
WHEN "01001101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000001101100011010011100110000011111";
WHEN "01001110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000010100111001100111110111000100101";
WHEN "01001111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000011100001010010001000010000100110";
WHEN "01010000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000100011010101010101001101111101001";
WHEN "01010001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000101010011010111010011000101011101";
WHEN "01010010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000110001011011000110011000100100110";
WHEN "01010011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000111000010101111110111011001101011";
WHEN "01010100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000111111001011101001100111000100001";
WHEN "01010101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001000101111100001011111010101001110";
WHEN "01010110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001001100100111101011001101011110000";
WHEN "01010111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001010011001110001100101111101101110";
WHEN "01011000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001011001101111110101101010010010001";
WHEN "01011001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001100000001100101010111111100111010";
WHEN "01011010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001100110100100110001101011100000000";
WHEN "01011011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001101100111000001110100010111010111";
WHEN "01011100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001110011000111000110010100111110110";
WHEN "01011101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001111001010001011101101010010110110";
WHEN "01011110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001111111010111011001000101101000110";
WHEN "01011111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010000101011000111101000100000001001";
WHEN "01100000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010001011010110001101111100010010001";
WHEN "01100001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010010001001111001111111111111100011";
WHEN "01100010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010010111000100000111011011011010100";
WHEN "01100011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010011100110100111000010101101000000";
WHEN "01100100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010100010100001100110101111101011011";
WHEN "01100101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010101000001010010110100110100000110";
WHEN "01100110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010101101101111001011110001110000000";
WHEN "01100111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010110011010000001010000100010111011";
WHEN "01101000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010111000101101010101001100000110100";
WHEN "01101001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010111110000110110000110010100001001";
WHEN "01101010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011000011011100100000011100111100101";
WHEN "01101011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011001000101110100111101011110110110";
WHEN "01101100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011001101111101001001111011110011101";
WHEN "01101101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011010011001000001010100100101100101";
WHEN "01101110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011011000001111101100111010111010110";
WHEN "01101111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011011101010011110100001110011000011";
WHEN "01110000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011100010010100100011101011100001011";
WHEN "01110001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011100111010001111110011010011110011";
WHEN "01110010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011101100001100000111100000000100110";
WHEN "01110011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011110001000011000001111101010111100";
WHEN "01110100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011110101110110110000110000000000010";
WHEN "01110101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011111010100111010110110001111011011";
WHEN "01110110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011111111010100110110111001101100111";
WHEN "01110111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100000011111111010011111010011110101";
WHEN "01111000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100001000100110110000100100101000010";
WHEN "01111001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100001101001011001111100100110001111";
WHEN "01111010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100010001101100110011100100110001011";
WHEN "01111011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100010110001011011111001011010001001";
WHEN "01111100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100011010100111010100111100000011111";
WHEN "01111101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100011111000000010111010111111010011";
WHEN "01111110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100100011010110101000111101001000001";
WHEN "01111111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100100111101010001100000110011010011";
WHEN "10000000" => memoryC2_uid52_sqrtTableGenerator_q <= "1010010101111101100001100110011010010110";
WHEN "10000001" => memoryC2_uid52_sqrtTableGenerator_q <= "1010011010001010011011010010001010010101";
WHEN "10000010" => memoryC2_uid52_sqrtTableGenerator_q <= "1010011110010010001010101001101000100010";
WHEN "10000011" => memoryC2_uid52_sqrtTableGenerator_q <= "1010100010010100111000100000100001010100";
WHEN "10000100" => memoryC2_uid52_sqrtTableGenerator_q <= "1010100110010010101101010111010111011000";
WHEN "10000101" => memoryC2_uid52_sqrtTableGenerator_q <= "1010101010001011110001011100011000100011";
WHEN "10000110" => memoryC2_uid52_sqrtTableGenerator_q <= "1010101110000000001100101100000011010111";
WHEN "10000111" => memoryC2_uid52_sqrtTableGenerator_q <= "1010110001110000000110110010000000000011";
WHEN "10001000" => memoryC2_uid52_sqrtTableGenerator_q <= "1010110101011011100111001001100111011011";
WHEN "10001001" => memoryC2_uid52_sqrtTableGenerator_q <= "1010111001000010110100111110101001100111";
WHEN "10001010" => memoryC2_uid52_sqrtTableGenerator_q <= "1010111100100101110111001101111010011010";
WHEN "10001011" => memoryC2_uid52_sqrtTableGenerator_q <= "1011000000000100110100100101111001101001";
WHEN "10001100" => memoryC2_uid52_sqrtTableGenerator_q <= "1011000011011111110011100111001110011011";
WHEN "10001101" => memoryC2_uid52_sqrtTableGenerator_q <= "1011000110110110111010100101010000010010";
WHEN "10001110" => memoryC2_uid52_sqrtTableGenerator_q <= "1011001010001010001111100110100011110101";
WHEN "10001111" => memoryC2_uid52_sqrtTableGenerator_q <= "1011001101011001111000100101100000101111";
WHEN "10010000" => memoryC2_uid52_sqrtTableGenerator_q <= "1011010000100101111011010000100110101110";
WHEN "10010001" => memoryC2_uid52_sqrtTableGenerator_q <= "1011010011101110011101001011000010101011";
WHEN "10010010" => memoryC2_uid52_sqrtTableGenerator_q <= "1011010110110011100011101101000011000010";
WHEN "10010011" => memoryC2_uid52_sqrtTableGenerator_q <= "1011011001110101010100000100010110000111";
WHEN "10010100" => memoryC2_uid52_sqrtTableGenerator_q <= "1011011100110011110011010100100011000111";
WHEN "10010101" => memoryC2_uid52_sqrtTableGenerator_q <= "1011011111101111000110010111011111101100";
WHEN "10010110" => memoryC2_uid52_sqrtTableGenerator_q <= "1011100010100111010001111101100111011011";
WHEN "10010111" => memoryC2_uid52_sqrtTableGenerator_q <= "1011100101011100011010101110010010000110";
WHEN "10011000" => memoryC2_uid52_sqrtTableGenerator_q <= "1011101000001110100101001000001010111101";
WHEN "10011001" => memoryC2_uid52_sqrtTableGenerator_q <= "1011101010111101110101100001100000011001";
WHEN "10011010" => memoryC2_uid52_sqrtTableGenerator_q <= "1011101101101010010000001000011000010001";
WHEN "10011011" => memoryC2_uid52_sqrtTableGenerator_q <= "1011110000010011111001000011000111101011";
WHEN "10011100" => memoryC2_uid52_sqrtTableGenerator_q <= "1011110010111010110100010000011100001100";
WHEN "10011101" => memoryC2_uid52_sqrtTableGenerator_q <= "1011110101011111000101100111110011100101";
WHEN "10011110" => memoryC2_uid52_sqrtTableGenerator_q <= "1011111000000000110000111001100101000110";
WHEN "10011111" => memoryC2_uid52_sqrtTableGenerator_q <= "1011111010011111111001101111011010100001";
WHEN "10100000" => memoryC2_uid52_sqrtTableGenerator_q <= "1011111100111100100011101100010111001001";
WHEN "10100001" => memoryC2_uid52_sqrtTableGenerator_q <= "1011111111010110110010001101001000000010";
WHEN "10100010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000001101110101000101000010011000010";
WHEN "10100011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000100000100001010001110100110010110";
WHEN "10100100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000110010111011010001010111100001100";
WHEN "10100101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001000101000011011100010110101000101";
WHEN "10100110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001010110111010001010110010001011110";
WHEN "10100111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001101000011111110100000010001011111";
WHEN "10101000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001111001110100101110110101101000100";
WHEN "10101001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010001010111001010001010101010101100";
WHEN "10101010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010011011101101110001000100101000110";
WHEN "10101011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010101100010010100011000010100001111";
WHEN "10101100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010111100100111111011101011000100010";
WHEN "10101101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011001100101110001110110111110010101";
WHEN "10101110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011011100100101110000000010010011100";
WHEN "10101111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011101100001110110010000011011110101";
WHEN "10110000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011111011101001100111010101110100000";
WHEN "10110001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100001010110110100001110101011100101";
WHEN "10110010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100011001110101110011000010000001010";
WHEN "10110011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100101000100111101011111110110001110";
WHEN "10110100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100110111001100011101010011101101000";
WHEN "10110101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101000101100100010111001110100110000";
WHEN "10110110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101010011101111101001100011011001010";
WHEN "10110111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101100001101110100011101101011001111";
WHEN "10111000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101101111100001010100101111011111011";
WHEN "10111001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101111101001000001011010101011010010";
WHEN "10111010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110001010100011010101110100001011000";
WHEN "10111011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110010111110011000010001010111000011";
WHEN "10111100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110100100110111011110000010101011000";
WHEN "10111101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110110001110000110110110000100000011";
WHEN "10111110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110111110011111011001010101000110101";
WHEN "10111111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111001011000011010010011101011001011";
WHEN "11000000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111010111011100101110100011010101110";
WHEN "11000001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111100011101011111001101110001101111";
WHEN "11000010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111101111110000111111110100000110001";
WHEN "11000011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111111011101100001100011000011000000";
WHEN "11000100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000000111011101101010101110101010001";
WHEN "11000101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000010011000101100101111001011000001";
WHEN "11000110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000011110100100001000101011000110001";
WHEN "11000111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000101001111001011101100110101010110";
WHEN "11001000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000110101000101101111000000000110111";
WHEN "11001001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001000000001001000110111100001010111";
WHEN "11001010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001001011000011101111010001111110001";
WHEN "11001011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001010101110101110001101001101110101";
WHEN "11001100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001100000011111010111011110111110000";
WHEN "11001101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001101011000000101001111111100011101";
WHEN "11001110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001110101011001110010001100010111100";
WHEN "11001111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001111111101010111000111010001000110";
WHEN "11010000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010001001110100000110110000111100011";
WHEN "11010001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010010011110101100100001101010101001";
WHEN "11010010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010011101101111011001100000010100000";
WHEN "11010011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010100111100001101110101111100001101";
WHEN "11010100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010110001001100101011110101001100110";
WHEN "11010101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010111010110000011000100001100011101";
WHEN "11010110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011000100001100111100011010001111111";
WHEN "11010111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011001101100010011110111010100001110";
WHEN "11011000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011010110110001000111010011110001001";
WHEN "11011001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011011111111000111100101101111110010";
WHEN "11011010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011101000111010000110000111010101011";
WHEN "11011011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011110001110100101010010101100100001";
WHEN "11011100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011111010101000110000000100101101100";
WHEN "11011101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100000011010110011101111000011001010";
WHEN "11011110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100001011111101111010001011110110001";
WHEN "11011111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100010100011111001011010001110110110";
WHEN "11100000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100011100111010010111010101010010110";
WHEN "11100001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100100101001111100100011000111111010";
WHEN "11100010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100101101011110111000011000000111010";
WHEN "11100011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100110101101000011001000110001011000";
WHEN "11100100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100111101101100001100001111111111000";
WHEN "11100101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101000101101010010111011010010110011";
WHEN "11100110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101001101100011000000000011100000010";
WHEN "11100111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101010101010110001011100010111011101";
WHEN "11101000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101011101000011111111001001100001101";
WHEN "11101001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101100100101100100000000001010010110";
WHEN "11101010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101101100001111110011001110010001001";
WHEN "11101011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101110011101101111101101101111100100";
WHEN "11101100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101111011000111000100011000011000111";
WHEN "11101101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110000010011011001011111111001001110";
WHEN "11101110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110001001101010011001001110000110111";
WHEN "11101111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110010000110100110000101011110010110";
WHEN "11110000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110010111111010010110111000110011101";
WHEN "11110001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110011110111011010000010000101001011";
WHEN "11110010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110100101110111100001001001011100101";
WHEN "11110011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110101100101111001101110100011000111";
WHEN "11110100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110110011100010011010011101011100000";
WHEN "11110101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110111010010001001011001011100011001";
WHEN "11110110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111000000111011100100000000111011011";
WHEN "11110111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111000111100001101000111011011001110";
WHEN "11111000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111001110000011011101110011100101111";
WHEN "11111001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111010100100001000110011110010000101";
WHEN "11111010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111011010111010100110101011011110000";
WHEN "11111011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111100001010000000010000110110110111";
WHEN "11111100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111100111100001011100011000000010101";
WHEN "11111101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111101101101110111001000010010110000";
WHEN "11111110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111110011111000011011100101100011100";
WHEN "11111111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111111001111110000111011100111010010";
WHEN OTHERS =>
memoryC2_uid52_sqrtTableGenerator_q <= "1100000000000000000000000000000001000010";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid72_sqrtPolynomialEvaluator(ADD,71)@14
sumAHighB_uid72_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => memoryC2_uid52_sqrtTableGenerator_q(39)) & memoryC2_uid52_sqrtTableGenerator_q);
sumAHighB_uid72_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q(32)) & reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid72_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid72_sqrtPolynomialEvaluator_b));
sumAHighB_uid72_sqrtPolynomialEvaluator_q <= sumAHighB_uid72_sqrtPolynomialEvaluator_o(40 downto 0);
--lowRangeB_uid70_sqrtPolynomialEvaluator(BITSELECT,69)@13
lowRangeB_uid70_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid70_sqrtPolynomialEvaluator_b <= lowRangeB_uid70_sqrtPolynomialEvaluator_in(0 downto 0);
--ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a(DELAY,224)@13
ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid70_sqrtPolynomialEvaluator_b, xout => ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--s3_uid70_uid73_sqrtPolynomialEvaluator(BITJOIN,72)@14
s3_uid70_uid73_sqrtPolynomialEvaluator_q <= sumAHighB_uid72_sqrtPolynomialEvaluator_q & ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a_q;
--yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,101)@14
yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_in <= s3_uid70_uid73_sqrtPolynomialEvaluator_q;
yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_b <= yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_in(41 downto 24);
--reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9(REG,134)@14
reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor(LOGICAL,435)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_b <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_q <= not (ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_a or ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_b);
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,431)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_mem_top_q <= "01011";
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp(LOGICAL,432)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_a <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_mem_top_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_a = ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg(REG,433)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena(REG,436)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,437)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_b <= VCC_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_a and ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_b;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,427)
-- every=1, low=0, high=11, step=1, init=1
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 10 THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 11;
ELSE
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4));
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg(REG,428)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,429)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_s <= VCC_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,426)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ia <= X44dto0_uid33_fpSqrtTest_b;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 12,
width_b => 45,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0);
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg(DELAY,425)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_q, xout => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg_q, clk => clk, aclr => areset );
--yT4_uid74_sqrtPolynomialEvaluator(BITSELECT,73)@15
yT4_uid74_sqrtPolynomialEvaluator_in <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg_q;
yT4_uid74_sqrtPolynomialEvaluator_b <= yT4_uid74_sqrtPolynomialEvaluator_in(44 downto 5);
--xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,100)@15
xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_in <= yT4_uid74_sqrtPolynomialEvaluator_b(12 downto 0);
xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_b <= xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_in(12 downto 0);
--pad_xBottomBits_uid101_uid104_pT4_uid75_sqrtPolynomialEvaluator(BITJOIN,103)@15
pad_xBottomBits_uid101_uid104_pT4_uid75_sqrtPolynomialEvaluator_q <= xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,99)@14
yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_in <= s3_uid70_uid73_sqrtPolynomialEvaluator_q(14 downto 0);
yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_b <= yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_in(14 downto 0);
--spad_yBottomBits_uid100_uid103_pT4_uid75_sqrtPolynomialEvaluator(BITJOIN,102)@14
spad_yBottomBits_uid100_uid103_pT4_uid75_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_b;
--pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator(BITJOIN,104)@14
pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid100_uid103_pT4_uid75_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6(REG,135)@14
reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,98)@15
xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_in <= yT4_uid74_sqrtPolynomialEvaluator_b;
xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_b <= xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_in(39 downto 22);
--multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma(CHAINMULTADD,127)@15
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a(0) * multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c(0);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a(1) * multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c(1);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p(1),38);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w(0);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x(0);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_b),19));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid101_uid104_pT4_uid75_sqrtPolynomialEvaluator_q),19));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6_q),18));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9_q),18));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y(0);
END IF;
END PROCESS;
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s(0),37));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_q <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,106)@18
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_q;
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_in(36 downto 2);
--highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,108)@18
highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_b;
highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_b <= highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_in(34 downto 6);
--reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1(REG,137)@18
reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q <= highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,96)@14
yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_in <= s3_uid70_uid73_sqrtPolynomialEvaluator_q;
yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_b <= yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_in(41 downto 15);
--reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1(REG,136)@14
reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,95)@15
xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_in <= yT4_uid74_sqrtPolynomialEvaluator_b;
xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_b <= xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_in(39 downto 13);
--topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator(MULT,97)@15
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_b);
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_a <= (others => '0');
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_b <= (others => '0');
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_a <= xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_b;
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1_q;
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_pr,54));
END IF;
END PROCESS;
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_q <= topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0(REG,138)@18
reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q <= topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator(ADD,109)@19
sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q(53)) & reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q(28)) & reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_b));
sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_q <= sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_o(54 downto 0);
--lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,107)@18
lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_b(5 downto 0);
lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_in(5 downto 0);
--ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a(DELAY,260)@18
ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b, xout => ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator(BITJOIN,110)@19
add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_q <= sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_q & ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a_q;
--R_uid112_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,111)@19
R_uid112_pT4_uid75_sqrtPolynomialEvaluator_in <= add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_q(59 downto 0);
R_uid112_pT4_uid75_sqrtPolynomialEvaluator_b <= R_uid112_pT4_uid75_sqrtPolynomialEvaluator_in(59 downto 17);
--reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1(REG,139)@19
reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q <= R_uid112_pT4_uid75_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor(LOGICAL,396)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_b <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_q <= not (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_a or ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_b);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_mem_top(CONSTANT,392)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_mem_top_q <= "010000";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp(LOGICAL,393)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_mem_top_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_q <= "1" when ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_a = ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_b else "0";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg(REG,394)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena(REG,397)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_q = "1") THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd(LOGICAL,398)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_b <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_a and ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_b;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt(COUNTER,388)
-- every=1, low=0, high=16, step=1, init=1
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i = 15 THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i - 16;
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i,5));
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg(REG,389)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux(MUX,390)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_s, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem(DUALMEM,387)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_reset0 <= areset;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ia <= addrTable_uid32_fpSqrtTest_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_aa <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ab <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 17,
width_b => 8,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_iq,
address_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_aa,
data_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ia
);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_iq(7 downto 0);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg(DELAY,386)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC1_uid51_sqrtTableGenerator(LOOKUP,50)@19
memoryC1_uid51_sqrtTableGenerator: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg_q) IS
WHEN "00000000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111111111111111111111111111111111111111111011";
WHEN "00000001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111111000000010111110110000100010110000010100";
WHEN "00000010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111110000001011110110001000101000001111001011";
WHEN "00000011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111101000011010011110111011011000011101001111";
WHEN "00000100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111100000101110110010001000001011000000111001";
WHEN "00000101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111011001001000101000111010001100100001111010";
WHEN "00000110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111010001100111111100101000000101001011000100";
WHEN "00000111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111001010001100100110110011100000001110100011";
WHEN "00001000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111000010110110100001001000110100101010110011";
WHEN "00001001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110111011100101100101011110101110101001001000";
WHEN "00001010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110110100011001101101110101111001111000100001";
WHEN "00001011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110101101010010110100011000101100111101001111";
WHEN "00001100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110100110010000110011011010110101010110000000";
WHEN "00001101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110011111010011100101011001000100010010001010";
WHEN "00001110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110011000011011000100111000111100011000101011";
WHEN "00001111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110010001100111001100101000011111111001101011";
WHEN "00010000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110001010110111110111011101111111101111101110";
WHEN "00010001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110000100001101000000010111101011000100111101";
WHEN "00010010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101111101100110100010011011011111100110000011";
WHEN "00010011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101110111000100011000110110111010010101100011";
WHEN "00010100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101110000100110011110111110101001000101011101";
WHEN "00010101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101101010001100110000001110011100010100101010";
WHEN "00010110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101100011110111001000001000111001101011100100";
WHEN "00010111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101011101100101100010010111001110111000101001";
WHEN "00011000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101010111010111111010101001000101001011100110";
WHEN "00011001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101010001001110001100110100010101001110000111";
WHEN "00011010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101001011001000010100110100111011010110101100";
WHEN "00011011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101000101000110001110101100101100011000010100";
WHEN "00011100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100111111000111110110100011001010101001001000";
WHEN "00011101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100111001001101001000100101011011100011011010";
WHEN "00011110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100110011010110000001000101111101011101000111";
WHEN "00011111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100101101100010011100011100011101110111000011";
WHEN "00100000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100100111110010010111000101101111111110110110";
WHEN "00100001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100100010000101101101100011100011101000111011";
WHEN "00100010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100011100011100011100011100011100011100011100";
WHEN "00100011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100010110110110100000011011101001010001110001";
WHEN "00100100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100010001010011110110010000111100000101011100";
WHEN "00100101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100001011110100011010110000100001111010011010";
WHEN "00100110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100000110011000001010110010111011001110001001";
WHEN "00100111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100000000111111000011010100110100011110000000";
WHEN "00101000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011111011101001000001010110111110111001100111";
WHEN "00101001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011110110010110000001111110001001100110111100";
WHEN "00101010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011110001000110000010010010111010110011000101";
WHEN "00101011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011101011111000111111100001101001010001010000";
WHEN "00101100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011100110101110110110111010010110001000010000";
WHEN "00101101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011100001100111100101110000100110101010110010";
WHEN "00101110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011011100100011001001011011011110011101110000";
WHEN "00101111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011010111100001011111010101011001101001111001";
WHEN "00110000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011010010100010100100111100000111011001011100";
WHEN "00110001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011001101100110010111110000100100011110010000";
WHEN "00110010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011001000101100110101010110110110000111110100";
WHEN "00110011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011000011110101111011010110000100111101010001";
WHEN "00110100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010111111000001100111011000011000000110001110";
WHEN "00110101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010111010001111110111001010110000011010000111";
WHEN "00110110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010110101100000101000011101000011111011000100";
WHEN "00110111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010110000110011111001000001111001010111101100";
WHEN "00111000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010101100001001100110101110100011110101001011";
WHEN "00111001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010100111100001101111011010111110100100110000";
WHEN "00111010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010100010111100010001000001101000111101000110";
WHEN "00111011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010011110011001001001011111100010011110000100";
WHEN "00111100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010011001111000010110110100000110111010110100";
WHEN "00111101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010010101011001110111000001001010101011110101";
WHEN "00111110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010010000111101101000001010110111000110011001";
WHEN "00111111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010001100100011101000010111100110111101000001";
WHEN "01000000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010001000001011110101110000000011000010101111";
WHEN "01000001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010000011110110001110011110111110111001110101";
WHEN "01000010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001111111100010110000110001010101100011010110";
WHEN "01000011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001111011010001011010110110000110011000000010";
WHEN "01000100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001110111000010001010111110010010000100010000";
WHEN "01000101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001110010110100111111011100110111101100001101";
WHEN "01000110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001101110101001110110100110110001110011001101";
WHEN "01000111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001101010100000101110110010110011101000100110";
WHEN "01001000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001100110011001100110011001100110011001100111";
WHEN "01001001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001100010010100011011110101100110101000110100";
WHEN "01001010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001011110010001001101100011000001101000110111";
WHEN "01001011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001011010001111111001111111110010111100011010";
WHEN "01001100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001010110010000011111101011100001111010110101";
WHEN "01001101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001010010010010111101000111011111010111100111";
WHEN "01001110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001001110010111010000110110100011001111011111";
WHEN "01001111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001001010011101011001011101001010011001000011";
WHEN "01010000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001000110100101010101100001010100010111011001";
WHEN "01010001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001000010101111000011101010100001010011101010";
WHEN "01010010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000111110111010100010100001101111110110111011";
WHEN "01010011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000111011000111110000110001011011001010110110";
WHEN "01010100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000110111010110101101000101011000111001111100";
WHEN "01010101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000110011100111010110001010110111010110011001";
WHEN "01010110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000101111111001101010110000011011100001101110";
WHEN "01010111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000101100001101101001100101111111011001001000";
WHEN "01011000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000101000100011010001011100110000000100001011";
WHEN "01011001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000100100111010100001000111001100000101101001";
WHEN "01011010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000100001010011010111011001000001110000001010";
WHEN "01011011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000011101101101110011000111001101011101101001";
WHEN "01011100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000011010001001110011000111111000000111111110";
WHEN "01011101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000010110100111010110010010010101100110000110";
WHEN "01011110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000010011000110011011011111000011001010011100";
WHEN "01011111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000001111100111000001100111100110000011001110";
WHEN "01100000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000001100001001000111100110101001111111011001";
WHEN "01100001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000001000101100101100010111111111110011000000";
WHEN "01100010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000000101010001101110111000011011111111000001";
WHEN "01100011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000000001111000001110000101110101011011111010";
WHEN "01100100" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111111110100000001000111111000100000110100011";
WHEN "01100101" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111111011001001011110100011111111101100000101";
WHEN "01100110" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111110111110100001101110101011110011011101110";
WHEN "01100111" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111110100100000010101110101010011111000000000";
WHEN "01101000" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111110001001101110101100110001111101011100110";
WHEN "01101001" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111101101111100101100001011111100011101100000";
WHEN "01101010" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111101010101100111000101010111110101000110011";
WHEN "01101011" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111100111011110011010001000110011010110100011";
WHEN "01101100" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111100100010001001111101011101111010111011101";
WHEN "01101101" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111100001000101011000011010111110000001010110";
WHEN "01101110" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111011101111010110011011110100000001011101001";
WHEN "01101111" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111011010110001011111111111001011010000001011";
WHEN "01110000" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111010111101001011101000110101000001010111000";
WHEN "01110001" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111010100100010101001111111010010011101010111";
WHEN "01110010" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111010001011101000101110100010111010001011101";
WHEN "01110011" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111001110011000101111110001110100011111000010";
WHEN "01110100" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111001011010101100111000100010111110010000101";
WHEN "01110101" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111001000010011101010111001011101110010111011";
WHEN "01110110" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111000101010010111010011111010001001110111001";
WHEN "01110111" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111000010010011010101000100101010000010101111";
WHEN "01111000" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110111111010100111001111001001100100101001010";
WHEN "01111001" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110111100010111101000001101001000110100111100";
WHEN "01111010" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110111001011011011111010001011001100101010110";
WHEN "01111011" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110110110100000011110010111100011101101100100";
WHEN "01111100" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110110011100110100100110001110101011000010010";
WHEN "01111101" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110110000101101110001110011000101010101000000";
WHEN "01111110" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110101101110110000100101110110010001001001000";
WHEN "01111111" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110101010111111011100111001000001100100101101";
WHEN "10000000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101101010000010011110011001100111111100111001110";
WHEN "10000001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101101000101000011111100000001101011100010111111";
WHEN "10000010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100111001111100011001011101111011000111000110";
WHEN "10000011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100101110111101000001010101111100101100001110";
WHEN "10000100" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100100100000101101001101111010010110100100001";
WHEN "10000101" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100011001010110001001000000001110100111001000";
WHEN "10000110" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100001110101110010101101111001011110000101111";
WHEN "10000111" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100000100001110000110110010001101111110011101";
WHEN "10001000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011111001110101010011001110011111110100111011";
WHEN "10001001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011101111100011110010010111110010111100101110";
WHEN "10001010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011100101011001011011110000000001011110011110";
WHEN "10001011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011011011010110000111000110110000101100111000";
WHEN "10001100" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011010001011001101100011000110100111010110010";
WHEN "10001101" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011000111100100000011101111110110010100110011";
WHEN "10001110" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010111101110101000101100001110111000000001100";
WHEN "10001111" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010110100001100101010010000111001111000000110";
WHEN "10010000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010101010101010101010101010101010101010100111";
WHEN "10010001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010100001001110111111101000000110101101011100";
WHEN "10010010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010010111111001100010001101000110101101010011";
WHEN "10010011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010001110101010001011101000001001010000011100";
WHEN "10010100" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010000101100000110101010001111110001101011100";
WHEN "10010101" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001111100011101011000101101010010110010111111";
WHEN "10010110" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001110011011111101111100110011110011101111100";
WHEN "10010111" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001101010100111110011110011010000011100001010";
WHEN "10011000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001100001110101011111010010011101111001111000";
WHEN "10011001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001011001001000101100001011110000111001000110";
WHEN "10011010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001010000100001010100101111010111101111011111";
WHEN "10011011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001000111111111010011010101110101001000101111";
WHEN "10011100" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000111111100010100010011111110000101111111100";
WHEN "10011101" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000110111001010111100110101101000011000010110";
WHEN "10011110" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000101110111000011101000111100001101001110110";
WHEN "10011111" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000100110101010111110001100111100001010011101";
WHEN "10100000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000011110100010011011000100100100001000111110";
WHEN "10100001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000010110011110101110110100000101100011100100";
WHEN "10100010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000001110011111110100100111111111101010001110";
WHEN "10100011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000000110100101100111110011011000111100001000";
WHEN "10100100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111111110110000000011101111110011100000110010";
WHEN "10100101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111110110111111000011111101000001110110000000";
WHEN "10100110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111101111010010100100000000111011111011011100";
WHEN "10100111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111100111101010011111100111010100101110001111";
WHEN "10101000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111100000000110110010100001110000000001101000";
WHEN "10101001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111011000100111011000100111011000100111010111";
WHEN "10101010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111010001001100001101110100110110101111010010";
WHEN "10101011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111001001110101001110001100000110111010001010";
WHEN "10101100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111000010100010010101110100010000111110100001";
WHEN "10101101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110111011010011100000111001011111100001100000";
WHEN "10101110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110110100001000101011101100110111011101100111";
WHEN "10101111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110101101000001110010100100001111111111001110";
WHEN "10110000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110100101111110110001111010001010101100111001";
WHEN "10110001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110011110111111100110001101101100000010010101";
WHEN "10110010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110011000000100001100000010010011111000000001";
WHEN "10110011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110010001001100011111111111110110011011010111";
WHEN "10110100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110001010011000011110110010010101010011110100";
WHEN "10110101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110000011101000000101001001111000110101000111";
WHEN "10110110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101111100111011001111111010101001011111101101";
WHEN "10110111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101110110010001111011111100101001101100011101";
WHEN "10111000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101101111101100000110001011101111100101100101";
WHEN "10111001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101101001001001101011100111011111001001111100";
WHEN "10111010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101100010101010101001010011000100011100101001";
WHEN "10111011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101011100001110111100010101001101111111000001";
WHEN "10111100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101010101110110100001111000000111010110000110";
WHEN "10111101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101001111100001010111001001010011110111110010";
WHEN "10111110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101001001001111011001011001101001100100001010";
WHEN "10111111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101000011000000100101111101001100000111110011";
WHEN "11000000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100111100110100111010001011001000000110010001";
WHEN "11000001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100110110101100010011011101101110001110100001";
WHEN "11000010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100110000100110101111010010001110110101110001";
WHEN "11000011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100101010100100001011001000110101011111000110";
WHEN "11000100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100100100100100100100100100100100100100100100";
WHEN "11000101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100011110100111111001001011010001001110001011";
WHEN "11000110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100011000101110000110100101011111001100010100";
WHEN "11000111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100010010110111001010011110011100111011010000";
WHEN "11001000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100001101000011000010100011111111101100010000";
WHEN "11001001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100000111010001101100100110011111110111100100";
WHEN "11001010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100000001100011000110011000110101010001110001";
WHEN "11001011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011111011110111001101110000010011101011101001";
WHEN "11001100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011110110001110000000100100100111010011001010";
WHEN "11001101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011110000100111011100101111110001011110111100";
WHEN "11001110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011101011000011100000001110000101011100111111";
WHEN "11001111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011100101100010001000111110000101000110111001";
WHEN "11010000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011100000000011010101000000011101111101000101";
WHEN "11010001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011011010100111000010011000000110000101001110";
WHEN "11010010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011010101001101001111001001111001001111000010";
WHEN "11010011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011001111110101111001011100110101111101110110";
WHEN "11010100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011001010100000111111011001111010110111001110";
WHEN "11010101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011000101001110011111001100000011110011111110";
WHEN "11010110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010111111111110010111000000000111011000100001";
WHEN "11010111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010111010110000100101000100110100010000100010";
WHEN "11011000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010110101100101000111101010101110101110010011";
WHEN "11011001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010110000011011111101000100001110001101111001";
WHEN "11011010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010101011010101000011100101011010111110000000";
WHEN "11011011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010100110010000011001100100001011101001111001";
WHEN "11011100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010100001001101111101011000000011001010100000";
WHEN "11011101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010011100001101101101011010001110010111111110";
WHEN "11011110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010010111001111101000000101100010000000001111";
WHEN "11011111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010010010010011101011110110011000100001000001";
WHEN "11100000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010001101011001110111001010110000000100100001";
WHEN "11100001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010001000100010001000100010001000100010000111";
WHEN "11100010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010000011101100011110011101100001100001010100";
WHEN "11100011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001111110111000110111011111011000100000101010";
WHEN "11100100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001111010000111010010001011100110111101101010";
WHEN "11100101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001110101010111101101000111100000100011001100";
WHEN "11100110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001110000101010000110111001110001010110101110";
WHEN "11100111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001101011111110011110001010011100001010010000";
WHEN "11101000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001100111010100110001100010111000110000110000";
WHEN "11101001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001100010101100111111101101110010010101100001";
WHEN "11101010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001011110000111000111010111000101110100011000";
WHEN "11101011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001011001100011000111001100000000010110011100";
WHEN "11101100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001010101000000111101111010111101101110101000";
WHEN "11101101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001010000100000101010010011100110111011111001";
WHEN "11101110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001001100000010001011000110110000101010100110";
WHEN "11101111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001000111100101011111000110011001111000111011";
WHEN "11110000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001000011001010100101000101101010011110101110";
WHEN "11110001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000111110110001011011111000110001110101010010";
WHEN "11110010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000111010011010000010010101000101100010100101";
WHEN "11110011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000110110000100010111010001000000000101101101";
WHEN "11110100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000110001110000011001100011111111100101111111";
WHEN "11110101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000101101011110001000000110100100100011001001";
WHEN "11110110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000101001001101100001110010010000100111011110";
WHEN "11110111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000100100111110100101100001100101011011010000";
WHEN "11111000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000100000110001010010010000000011011011110100";
WHEN "11111001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000011100100101100110111010001000110000111101";
WHEN "11111010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000011000011011100010011101010000000111001101";
WHEN "11111011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000010100010011000011110111101111101010000000";
WHEN "11111100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000010000001100001010001000110111111111001100";
WHEN "11111101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000001100000110110100010000110011000100111101";
WHEN "11111110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000001000000011000001010000100011001111110101";
WHEN "11111111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000000100000000110000001010000010001100011010";
WHEN OTHERS =>
memoryC1_uid51_sqrtTableGenerator_q <= "0011111111111111111111111111111111111111111111011";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid76_sqrtPolynomialEvaluator(CONSTANT,75)
rndBit_uid76_sqrtPolynomialEvaluator_q <= "01";
--cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator(BITJOIN,76)@19
cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_q <= memoryC1_uid51_sqrtTableGenerator_q & rndBit_uid76_sqrtPolynomialEvaluator_q;
--reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0(REG,140)@19
reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ts4_uid78_sqrtPolynomialEvaluator(ADD,77)@20
ts4_uid78_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q);
ts4_uid78_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q);
ts4_uid78_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid78_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid78_sqrtPolynomialEvaluator_b));
ts4_uid78_sqrtPolynomialEvaluator_q <= ts4_uid78_sqrtPolynomialEvaluator_o(51 downto 0);
--s4_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@20
s4_uid79_sqrtPolynomialEvaluator_in <= ts4_uid78_sqrtPolynomialEvaluator_q;
s4_uid79_sqrtPolynomialEvaluator_b <= s4_uid79_sqrtPolynomialEvaluator_in(51 downto 1);
--yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,113)@20
yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_in <= s4_uid79_sqrtPolynomialEvaluator_b;
yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_in(50 downto 24);
--reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9(REG,141)@20
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9_q <= yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor(LOGICAL,485)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_b <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_q <= not (ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_a or ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_b);
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_mem_top(CONSTANT,481)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_mem_top_q <= "010001";
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp(LOGICAL,482)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_a <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_mem_top_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q);
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_q <= "1" when ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_a = ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_b else "0";
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg(REG,483)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena(REG,486)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_q = "1") THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd(LOGICAL,487)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_a <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_b <= VCC_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_a and ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_b;
--xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,116)@1
xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_in <= X44dto0_uid33_fpSqrtTest_b(17 downto 0);
xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b <= xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_in(17 downto 0);
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt(COUNTER,477)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg(REG,478)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux(MUX,479)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_s <= VCC_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux: PROCESS (ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_s, ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q, ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem(DUALMEM,476)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ia <= xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_aa <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ab <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 5,
numwords_a => 18,
width_b => 18,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_iq,
address_a => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_aa,
data_a => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ia
);
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_iq(17 downto 0);
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg(DELAY,475)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_q, xout => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg_q, clk => clk, aclr => areset );
--pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator(BITJOIN,118)@21
pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,115)@20
yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_in <= s4_uid79_sqrtPolynomialEvaluator_b(23 downto 0);
yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b <= yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_in(23 downto 0);
--ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a(DELAY,269)@20
ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b, xout => ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator(BITJOIN,117)@21
spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_q <= GND_q & ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a_q;
--pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator(BITJOIN,119)@21
pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6(REG,142)@21
reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor(LOGICAL,472)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_b <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_q <= not (ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_a or ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_b);
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,468)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_mem_top_q <= "010010";
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp(LOGICAL,469)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_a <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_mem_top_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_a = ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg(REG,470)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena(REG,473)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,474)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_b <= VCC_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_a and ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_b;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,464)
-- every=1, low=0, high=18, step=1, init=1
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 17 THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 18;
ELSE
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i,5));
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg(REG,465)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,466)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_s <= VCC_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,463)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ia <= X44dto0_uid33_fpSqrtTest_b;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 5,
numwords_a => 19,
width_b => 45,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0);
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg(DELAY,462)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_q, xout => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg_q, clk => clk, aclr => areset );
--xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,112)@22
xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_in <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg_q;
xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_in(44 downto 18);
--multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma(CHAINMULTADD,128)@22
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a(0) * multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c(0);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a(1) * multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c(1);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p(0),56);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w(1) <= RESIZE(multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p(1),56);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w(0);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x(1) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w(1);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s(1) + multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x(0);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y(1) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x(1);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_b),28));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_q),28));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6_q),27));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9_q),27));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y(0);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s(1) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s(0),55));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_q <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,121)@25
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_in <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_q;
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_b <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_in(54 downto 2);
--highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,123)@25
highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_in <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_b;
highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_b <= highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_in(52 downto 24);
--reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1(REG,144)@25
reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q <= highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1(REG,143)@20
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b(DELAY,266)@21
ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q, xout => ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b_q, clk => clk, aclr => areset );
--topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator(MULT,114)@22
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b);
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_a <= (others => '0');
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b <= (others => '0');
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_a <= xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_b;
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b <= ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b_q;
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_pr,54));
END IF;
END PROCESS;
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_q <= topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0(REG,145)@25
reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q <= topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator(ADD,124)@26
sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q(53)) & reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q(28)) & reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_b));
sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_q <= sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_o(54 downto 0);
--lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,122)@25
lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_in <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_b(23 downto 0);
lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_in(23 downto 0);
--ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a(DELAY,277)@25
ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b, xout => ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator(BITJOIN,125)@26
add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_q <= sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_q & ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a_q;
--R_uid127_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,126)@26
R_uid127_pT5_uid81_sqrtPolynomialEvaluator_in <= add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_q(77 downto 0);
R_uid127_pT5_uid81_sqrtPolynomialEvaluator_b <= R_uid127_pT5_uid81_sqrtPolynomialEvaluator_in(77 downto 25);
--reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1(REG,146)@26
reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q <= R_uid127_pT5_uid81_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor(LOGICAL,383)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_b <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_q <= not (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_a or ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_b);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_mem_top(CONSTANT,379)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_mem_top_q <= "010111";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp(LOGICAL,380)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_mem_top_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_q <= "1" when ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_a = ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_b else "0";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg(REG,381)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena(REG,384)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_q = "1") THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd(LOGICAL,385)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_b <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_a and ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_b;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt(COUNTER,375)
-- every=1, low=0, high=23, step=1, init=1
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i = 22 THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i - 23;
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i,5));
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg(REG,376)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux(MUX,377)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_s, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem(DUALMEM,374)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_reset0 <= areset;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ia <= addrTable_uid32_fpSqrtTest_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_aa <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ab <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 24,
width_b => 8,
widthad_b => 5,
numwords_b => 24,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_iq,
address_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_aa,
data_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ia
);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_iq(7 downto 0);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg(DELAY,373)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC0_uid50_sqrtTableGenerator(LOOKUP,49)@26
memoryC0_uid50_sqrtTableGenerator: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg_q) IS
WHEN "00000000" => memoryC0_uid50_sqrtTableGenerator_q <= "010000000000000000000000000000000000000000000000000000100";
WHEN "00000001" => memoryC0_uid50_sqrtTableGenerator_q <= "010000000011111111100000000111111101100000110111101011101";
WHEN "00000010" => memoryC0_uid50_sqrtTableGenerator_q <= "010000000111111110000000111111011000011011101011010000110";
WHEN "00000011" => memoryC0_uid50_sqrtTableGenerator_q <= "010000001011111011100011010100111000110000111101001000001";
WHEN "00000100" => memoryC0_uid50_sqrtTableGenerator_q <= "010000001111111000000111110110001101101011100000001100010";
WHEN "00000101" => memoryC0_uid50_sqrtTableGenerator_q <= "010000010011110011101111010000001111000000101001100100110";
WHEN "00000110" => memoryC0_uid50_sqrtTableGenerator_q <= "010000010111101110011010001110111110101101010010001011010";
WHEN "00000111" => memoryC0_uid50_sqrtTableGenerator_q <= "010000011011101000001001011101101010001111110000101011110";
WHEN "00001000" => memoryC0_uid50_sqrtTableGenerator_q <= "010000011111100000111101100110101011111110110100000111100";
WHEN "00001001" => memoryC0_uid50_sqrtTableGenerator_q <= "010000100011011000110111010011101100011101100110101010101";
WHEN "00001010" => memoryC0_uid50_sqrtTableGenerator_q <= "010000100111001111110111001101100011101101000000001001100";
WHEN "00001011" => memoryC0_uid50_sqrtTableGenerator_q <= "010000101011000101111101111100011010011010001111001000111";
WHEN "00001100" => memoryC0_uid50_sqrtTableGenerator_q <= "010000101110111011001100000111101011001010111111011011011";
WHEN "00001101" => memoryC0_uid50_sqrtTableGenerator_q <= "010000110010101111100010010110000011100111000100001101110";
WHEN "00001110" => memoryC0_uid50_sqrtTableGenerator_q <= "010000110110100011000001001101100101011111101100000110010";
WHEN "00001111" => memoryC0_uid50_sqrtTableGenerator_q <= "010000111010010101101001010011100111110100100100101100100";
WHEN "00010000" => memoryC0_uid50_sqrtTableGenerator_q <= "010000111110000111011011001100110111110110110011011001111";
WHEN "00010001" => memoryC0_uid50_sqrtTableGenerator_q <= "010001000001111000010111011101011010001001101000101001001";
WHEN "00010010" => memoryC0_uid50_sqrtTableGenerator_q <= "010001000101101000011110101000101011100001010010100100000";
WHEN "00010011" => memoryC0_uid50_sqrtTableGenerator_q <= "010001001001010111110001010001100001111111110100001001001";
WHEN "00010100" => memoryC0_uid50_sqrtTableGenerator_q <= "010001001101000110001111111010001101110000000101001110100";
WHEN "00010101" => memoryC0_uid50_sqrtTableGenerator_q <= "010001010000110011111011000100011001111110111111111011101";
WHEN "00010110" => memoryC0_uid50_sqrtTableGenerator_q <= "010001010100100000110011010001001101110010111111101011000";
WHEN "00010111" => memoryC0_uid50_sqrtTableGenerator_q <= "010001011000001100111001000001001101000001110101110100101";
WHEN "00011000" => memoryC0_uid50_sqrtTableGenerator_q <= "010001011011111000001100110100011001000100110111111001000";
WHEN "00011001" => memoryC0_uid50_sqrtTableGenerator_q <= "010001011111100010101111001010010001101011101010111001110";
WHEN "00011010" => memoryC0_uid50_sqrtTableGenerator_q <= "010001100011001100100000100001110101101101001111100011010";
WHEN "00011011" => memoryC0_uid50_sqrtTableGenerator_q <= "010001100110110101100001011001100011110111110010011111100";
WHEN "00011100" => memoryC0_uid50_sqrtTableGenerator_q <= "010001101010011101110010001111011011011111000100000100000";
WHEN "00011101" => memoryC0_uid50_sqrtTableGenerator_q <= "010001101110000101010011100000111101001001011010100000110";
WHEN "00011110" => memoryC0_uid50_sqrtTableGenerator_q <= "010001110001101100000101101011001011011011100001110000101";
WHEN "00011111" => memoryC0_uid50_sqrtTableGenerator_q <= "010001110101010010001001001010101011100010111011100001111";
WHEN "00100000" => memoryC0_uid50_sqrtTableGenerator_q <= "010001111000110111011110011011100101111111010010101000010";
WHEN "00100001" => memoryC0_uid50_sqrtTableGenerator_q <= "010001111100011100000101111001100111001010100011111111010";
WHEN "00100010" => memoryC0_uid50_sqrtTableGenerator_q <= "010010000000000000000000000000000000000000000000000000100";
WHEN "00100011" => memoryC0_uid50_sqrtTableGenerator_q <= "010010000011100011001101001001100110100010000110101001011";
WHEN "00100100" => memoryC0_uid50_sqrtTableGenerator_q <= "010010000111000101101101110000110110011111100000100100001";
WHEN "00100101" => memoryC0_uid50_sqrtTableGenerator_q <= "010010001010100111100010001111110001110110110111100101101";
WHEN "00100110" => memoryC0_uid50_sqrtTableGenerator_q <= "010010001110001000101011000000000001011001110000101000011";
WHEN "00100111" => memoryC0_uid50_sqrtTableGenerator_q <= "010010010001101001001000011010110101001110101001001001001";
WHEN "00101000" => memoryC0_uid50_sqrtTableGenerator_q <= "010010010101001000111010111001000101010001111010000101110";
WHEN "00101001" => memoryC0_uid50_sqrtTableGenerator_q <= "010010011000101000000010110011010001110110000010010110110";
WHEN "00101010" => memoryC0_uid50_sqrtTableGenerator_q <= "010010011100000110100000100001100100000010111010011010101";
WHEN "00101011" => memoryC0_uid50_sqrtTableGenerator_q <= "010010011111100100010100011011101110010100010011000011101";
WHEN "00101100" => memoryC0_uid50_sqrtTableGenerator_q <= "010010100011000001011110111001001100110111100000110100011";
WHEN "00101101" => memoryC0_uid50_sqrtTableGenerator_q <= "010010100110011110000000010001000110001000010101110101010";
WHEN "00101110" => memoryC0_uid50_sqrtTableGenerator_q <= "010010101001111001111000111010001011001101001011100110001";
WHEN "00101111" => memoryC0_uid50_sqrtTableGenerator_q <= "010010101101010101001001001010111000010010011110001110010";
WHEN "00110000" => memoryC0_uid50_sqrtTableGenerator_q <= "010010110000101111110001011001010101000101011010100111010";
WHEN "00110001" => memoryC0_uid50_sqrtTableGenerator_q <= "010010110100001001110001111011010101001110000000111110110";
WHEN "00110010" => memoryC0_uid50_sqrtTableGenerator_q <= "010010110111100011001011000110011000101000011101000001111";
WHEN "00110011" => memoryC0_uid50_sqrtTableGenerator_q <= "010010111010111011111101001111101011111101110101001011001";
WHEN "00110100" => memoryC0_uid50_sqrtTableGenerator_q <= "010010111110010100001000101100001000111100010001111110011";
WHEN "00110101" => memoryC0_uid50_sqrtTableGenerator_q <= "010011000001101011101101110000010110101110011111000100000";
WHEN "00110110" => memoryC0_uid50_sqrtTableGenerator_q <= "010011000101000010101100110000101010010010100110101011110";
WHEN "00110111" => memoryC0_uid50_sqrtTableGenerator_q <= "010011001000011001000110000001000110110000101001000001010";
WHEN "00111000" => memoryC0_uid50_sqrtTableGenerator_q <= "010011001011101110111001110101011101110000010000010111000";
WHEN "00111001" => memoryC0_uid50_sqrtTableGenerator_q <= "010011001111000100001000100001001111101110000011001001111";
WHEN "00111010" => memoryC0_uid50_sqrtTableGenerator_q <= "010011010010011000110010010111101100010000010101000000100";
WHEN "00111011" => memoryC0_uid50_sqrtTableGenerator_q <= "010011010101101100110111101011110010011011010111100010101";
WHEN "00111100" => memoryC0_uid50_sqrtTableGenerator_q <= "010011011001000000011000110000010001000101001100000110001";
WHEN "00111101" => memoryC0_uid50_sqrtTableGenerator_q <= "010011011100010011010101110111100111001000110111001011011";
WHEN "00111110" => memoryC0_uid50_sqrtTableGenerator_q <= "010011011111100101101111010100000011111001010110100010000";
WHEN "00111111" => memoryC0_uid50_sqrtTableGenerator_q <= "010011100010110111100101010111100111010011111010101011000";
WHEN "01000000" => memoryC0_uid50_sqrtTableGenerator_q <= "010011100110001000111000010100000010010010000100101111000";
WHEN "01000001" => memoryC0_uid50_sqrtTableGenerator_q <= "010011101001011001101000011010110110111011001001010111111";
WHEN "01000010" => memoryC0_uid50_sqrtTableGenerator_q <= "010011101100101001110101111101011000110101011001100011000";
WHEN "01000011" => memoryC0_uid50_sqrtTableGenerator_q <= "010011101111111001100001001100101101010110110001110111111";
WHEN "01000100" => memoryC0_uid50_sqrtTableGenerator_q <= "010011110011001000101010011001101011110101010001010011100";
WHEN "01000101" => memoryC0_uid50_sqrtTableGenerator_q <= "010011110110010111010001110100111101110110110111110010101";
WHEN "01000110" => memoryC0_uid50_sqrtTableGenerator_q <= "010011111001100101010111101110111111100001001101100111101";
WHEN "01000111" => memoryC0_uid50_sqrtTableGenerator_q <= "010011111100110010111100010111111111101000110100000100011";
WHEN "01001000" => memoryC0_uid50_sqrtTableGenerator_q <= "010100000000000000000000000000000000000000000000000000100";
WHEN "01001001" => memoryC0_uid50_sqrtTableGenerator_q <= "010100000011001100100010110110110101100101011111000010010";
WHEN "01001010" => memoryC0_uid50_sqrtTableGenerator_q <= "010100000110011000100101001100001000110010100111110000101";
WHEN "01001011" => memoryC0_uid50_sqrtTableGenerator_q <= "010100001001100100000111001111010101101001010101110010000";
WHEN "01001100" => memoryC0_uid50_sqrtTableGenerator_q <= "010100001100101111001001001111101100000001110001111010110";
WHEN "01001101" => memoryC0_uid50_sqrtTableGenerator_q <= "010100001111111001101011011100001111110111100111001110100";
WHEN "01001110" => memoryC0_uid50_sqrtTableGenerator_q <= "010100010011000011101110000011111001010111000101010011110";
WHEN "01001111" => memoryC0_uid50_sqrtTableGenerator_q <= "010100010110001101010001010101010101001001110000011010110";
WHEN "01010000" => memoryC0_uid50_sqrtTableGenerator_q <= "010100011001010110010101011111000100100010111111110110111";
WHEN "01010001" => memoryC0_uid50_sqrtTableGenerator_q <= "010100011100011110111010101111011101101100001011000110101";
WHEN "01010010" => memoryC0_uid50_sqrtTableGenerator_q <= "010100011111100111000001010100101011110000100110001001110";
WHEN "01010011" => memoryC0_uid50_sqrtTableGenerator_q <= "010100100010101110101001011100101111001001001101011111001";
WHEN "01010100" => memoryC0_uid50_sqrtTableGenerator_q <= "010100100101110101110011010101011101101000000010001000010";
WHEN "01010101" => memoryC0_uid50_sqrtTableGenerator_q <= "010100101000111100011111001100100010100011010110001010010";
WHEN "01010110" => memoryC0_uid50_sqrtTableGenerator_q <= "010100101100000010101101001111011111000000101010001000000";
WHEN "01010111" => memoryC0_uid50_sqrtTableGenerator_q <= "010100101111001000011101101011101001111111011011101100110";
WHEN "01011000" => memoryC0_uid50_sqrtTableGenerator_q <= "010100110010001101110000101110010000100011100110000000011";
WHEN "01011001" => memoryC0_uid50_sqrtTableGenerator_q <= "010100110101010010100110100100010101111111110011111100010";
WHEN "01011010" => memoryC0_uid50_sqrtTableGenerator_q <= "010100111000010110111111011010110011111111100100110111010";
WHEN "01011011" => memoryC0_uid50_sqrtTableGenerator_q <= "010100111011011010111011011110011010110001000011111110111";
WHEN "01011100" => memoryC0_uid50_sqrtTableGenerator_q <= "010100111110011110011010111011110001001110110010110011100";
WHEN "01011101" => memoryC0_uid50_sqrtTableGenerator_q <= "010101000001100001011101111111010101001001000110111011010";
WHEN "01011110" => memoryC0_uid50_sqrtTableGenerator_q <= "010101000100100100000100110101011011001111011011100000110";
WHEN "01011111" => memoryC0_uid50_sqrtTableGenerator_q <= "010101000111100110001111101010001111011001010110110001000";
WHEN "01100000" => memoryC0_uid50_sqrtTableGenerator_q <= "010101001010100111111110101001110100101111100011101010010";
WHEN "01100001" => memoryC0_uid50_sqrtTableGenerator_q <= "010101001101101001010010000000000101110100100000010000010";
WHEN "01100010" => memoryC0_uid50_sqrtTableGenerator_q <= "010101010000101010001001111000110100101101000000110110001";
WHEN "01100011" => memoryC0_uid50_sqrtTableGenerator_q <= "010101010011101010100110011111101011001000101000001111101";
WHEN "01100100" => memoryC0_uid50_sqrtTableGenerator_q <= "010101010110101010101000000000001010101001110101011010100";
WHEN "01100101" => memoryC0_uid50_sqrtTableGenerator_q <= "010101011001101010001110100101101100101110000110110001111";
WHEN "01100110" => memoryC0_uid50_sqrtTableGenerator_q <= "010101011100101001011010011011100010110101110011011000110";
WHEN "01100111" => memoryC0_uid50_sqrtTableGenerator_q <= "010101011111101000001011101100110110101011111010001101100";
WHEN "01101000" => memoryC0_uid50_sqrtTableGenerator_q <= "010101100010100110100010100100101010001101100111110011111";
WHEN "01101001" => memoryC0_uid50_sqrtTableGenerator_q <= "010101100101100100011111001101110111110001110010100101110";
WHEN "01101010" => memoryC0_uid50_sqrtTableGenerator_q <= "010101101000100010000001110011010010010000001101110111000";
WHEN "01101011" => memoryC0_uid50_sqrtTableGenerator_q <= "010101101011011111001010011111100101001000110011111011001";
WHEN "01101100" => memoryC0_uid50_sqrtTableGenerator_q <= "010101101110011011111001011101010100101010100111011010101";
WHEN "01101101" => memoryC0_uid50_sqrtTableGenerator_q <= "010101110001011000001110110110111101111010101100000011111";
WHEN "01101110" => memoryC0_uid50_sqrtTableGenerator_q <= "010101110100010100001010110110110110111010110111000101111";
WHEN "01101111" => memoryC0_uid50_sqrtTableGenerator_q <= "010101110111001111101101100111001110110000010111011111010";
WHEN "01110000" => memoryC0_uid50_sqrtTableGenerator_q <= "010101111010001010110111010010001101101010010110001111100";
WHEN "01110001" => memoryC0_uid50_sqrtTableGenerator_q <= "010101111101000101101000000001110101001000001110110100011";
WHEN "01110010" => memoryC0_uid50_sqrtTableGenerator_q <= "010110000000000000000000000000000000000000000000000000100";
WHEN "01110011" => memoryC0_uid50_sqrtTableGenerator_q <= "010110000010111001111111010110100010100100010101010100110";
WHEN "01110100" => memoryC0_uid50_sqrtTableGenerator_q <= "010110000101110011100110001111001010101010101001001000010";
WHEN "01110101" => memoryC0_uid50_sqrtTableGenerator_q <= "010110001000101100110100110011011111110000111111101000110";
WHEN "01110110" => memoryC0_uid50_sqrtTableGenerator_q <= "010110001011100101101011001101000011000011111010111110010";
WHEN "01110111" => memoryC0_uid50_sqrtTableGenerator_q <= "010110001110011110001001100101001111100100001000011011010";
WHEN "01111000" => memoryC0_uid50_sqrtTableGenerator_q <= "010110010001010110010000000101011010001100000111000100000";
WHEN "01111001" => memoryC0_uid50_sqrtTableGenerator_q <= "010110010100001101111110110110110001110101100111110100110";
WHEN "01111010" => memoryC0_uid50_sqrtTableGenerator_q <= "010110010111000101010110000010011111011111000111010010010";
WHEN "01111011" => memoryC0_uid50_sqrtTableGenerator_q <= "010110011001111100010101110001100110010001000001001011101";
WHEN "01111100" => memoryC0_uid50_sqrtTableGenerator_q <= "010110011100110010111110001101000011100010111101110111011";
WHEN "01111101" => memoryC0_uid50_sqrtTableGenerator_q <= "010110011111101001001111011101101111000000111001110011011";
WHEN "01111110" => memoryC0_uid50_sqrtTableGenerator_q <= "010110100010011111001001101100011010110000000111010001000";
WHEN "01111111" => memoryC0_uid50_sqrtTableGenerator_q <= "010110100101010100101101000001110011010100001010010011110";
WHEN "10000000" => memoryC0_uid50_sqrtTableGenerator_q <= "010110101000001001111001100110011111110011101111001101001";
WHEN "10000001" => memoryC0_uid50_sqrtTableGenerator_q <= "010110101101110011001110111111110110001100011001001000100";
WHEN "10000010" => memoryC0_uid50_sqrtTableGenerator_q <= "010110110011011011001010111011101100100001001011101011111";
WHEN "10000011" => memoryC0_uid50_sqrtTableGenerator_q <= "010110111001000001101110011011111110110011101101110101010";
WHEN "10000100" => memoryC0_uid50_sqrtTableGenerator_q <= "010110111110100110111010100001011000101101000011110000100";
WHEN "10000101" => memoryC0_uid50_sqrtTableGenerator_q <= "010111000100001010110000001011010111100101111000110010001";
WHEN "10000110" => memoryC0_uid50_sqrtTableGenerator_q <= "010111001001101101010000011000001100101010000010111110100";
WHEN "10000111" => memoryC0_uid50_sqrtTableGenerator_q <= "010111001111001110011100000100111110110111101100100011110";
WHEN "10001000" => memoryC0_uid50_sqrtTableGenerator_q <= "010111010100101110010100001101101100111010001110100010010";
WHEN "10001001" => memoryC0_uid50_sqrtTableGenerator_q <= "010111011010001100111001101101001111000001000111100000010";
WHEN "10001010" => memoryC0_uid50_sqrtTableGenerator_q <= "010111011111101010001101011101011000110010111001000011110";
WHEN "10001011" => memoryC0_uid50_sqrtTableGenerator_q <= "010111100101000110010000010110111010111100010101101100111";
WHEN "10001100" => memoryC0_uid50_sqrtTableGenerator_q <= "010111101010100001000011010001100100111100001000101101011";
WHEN "10001101" => memoryC0_uid50_sqrtTableGenerator_q <= "010111101111111010100111000100000110101011000001000000110";
WHEN "10001110" => memoryC0_uid50_sqrtTableGenerator_q <= "010111110101010010111100100100010010000000100111101001110";
WHEN "10001111" => memoryC0_uid50_sqrtTableGenerator_q <= "010111111010101010000100100110111100010101001010000100011";
WHEN "10010000" => memoryC0_uid50_sqrtTableGenerator_q <= "011000000000000000000000000000000000000000000000000000100";
WHEN "10010001" => memoryC0_uid50_sqrtTableGenerator_q <= "011000000101010100101111100010011101110011010100100110011";
WHEN "10010010" => memoryC0_uid50_sqrtTableGenerator_q <= "011000001010101000010100000000011110010100111001101100011";
WHEN "10010011" => memoryC0_uid50_sqrtTableGenerator_q <= "011000001111111010101110001011010011010100001100010101101";
WHEN "10010100" => memoryC0_uid50_sqrtTableGenerator_q <= "011000010101001011111110110011011000111101110000111001111";
WHEN "10010101" => memoryC0_uid50_sqrtTableGenerator_q <= "011000011010011100000110101000010111001100001101000111000";
WHEN "10010110" => memoryC0_uid50_sqrtTableGenerator_q <= "011000011111101011000110011001000010110110100101111010101";
WHEN "10010111" => memoryC0_uid50_sqrtTableGenerator_q <= "011000100100111000111110110011011110111100100111000001011";
WHEN "10011000" => memoryC0_uid50_sqrtTableGenerator_q <= "011000101010000101110000100100111101110000011001011010000";
WHEN "10011001" => memoryC0_uid50_sqrtTableGenerator_q <= "011000101111010001011100011010000001111110001110001011000";
WHEN "10011010" => memoryC0_uid50_sqrtTableGenerator_q <= "011000110100011100000010111110011111110010000010101100010";
WHEN "10011011" => memoryC0_uid50_sqrtTableGenerator_q <= "011000111001100101100100111101011101111011000010111000011";
WHEN "10011100" => memoryC0_uid50_sqrtTableGenerator_q <= "011000111110101110000011000001010110101101001110001010011";
WHEN "10011101" => memoryC0_uid50_sqrtTableGenerator_q <= "011001000011110101011101110011111001000001000011100100101";
WHEN "10011110" => memoryC0_uid50_sqrtTableGenerator_q <= "011001001000111011110101111110001001010001011001001101010";
WHEN "10011111" => memoryC0_uid50_sqrtTableGenerator_q <= "011001001110000001001100001000100010010111100011000101100";
WHEN "10100000" => memoryC0_uid50_sqrtTableGenerator_q <= "011001010011000101100000111010110110100101101101010011001";
WHEN "10100001" => memoryC0_uid50_sqrtTableGenerator_q <= "011001011000001000110100111100010000011111101101001011101";
WHEN "10100010" => memoryC0_uid50_sqrtTableGenerator_q <= "011001011101001011001000110011010011110010001101000110101";
WHEN "10100011" => memoryC0_uid50_sqrtTableGenerator_q <= "011001100010001100011101000101111110001000010110010010111";
WHEN "10100100" => memoryC0_uid50_sqrtTableGenerator_q <= "011001100111001100110010011001100111111111111100000000101";
WHEN "10100101" => memoryC0_uid50_sqrtTableGenerator_q <= "011001101100001100001001010011000101011100001011001110011";
WHEN "10100110" => memoryC0_uid50_sqrtTableGenerator_q <= "011001110001001010100010010110100110110111000001110111001";
WHEN "10100111" => memoryC0_uid50_sqrtTableGenerator_q <= "011001110110000111111110000111111001110001010000100010011";
WHEN "10101000" => memoryC0_uid50_sqrtTableGenerator_q <= "011001111011000100011101001010001001100001001001100100011";
WHEN "10101001" => memoryC0_uid50_sqrtTableGenerator_q <= "011010000000000000000000000000000000000000000000000000100";
WHEN "10101010" => memoryC0_uid50_sqrtTableGenerator_q <= "011010000100111010100111001011100110010110011001010001000";
WHEN "10101011" => memoryC0_uid50_sqrtTableGenerator_q <= "011010001001110100010011001110100101100111010011110101010";
WHEN "10101100" => memoryC0_uid50_sqrtTableGenerator_q <= "011010001110101101000100101010000111011010000101100000111";
WHEN "10101101" => memoryC0_uid50_sqrtTableGenerator_q <= "011010010011100100111011111110110110100011010011011110100";
WHEN "10101110" => memoryC0_uid50_sqrtTableGenerator_q <= "011010011000011011111001101100111111101100100110010111010";
WHEN "10101111" => memoryC0_uid50_sqrtTableGenerator_q <= "011010011101010001111110010100010001111011011100100100101";
WHEN "10110000" => memoryC0_uid50_sqrtTableGenerator_q <= "011010100010000111001010010011111111010110111100110100101";
WHEN "10110001" => memoryC0_uid50_sqrtTableGenerator_q <= "011010100110111011011110001010111101101100101010111100110";
WHEN "10110010" => memoryC0_uid50_sqrtTableGenerator_q <= "011010101011101110111010010111100110110100100000111000010";
WHEN "10110011" => memoryC0_uid50_sqrtTableGenerator_q <= "011010110000100001011111010111111001010011101101100110100";
WHEN "10110100" => memoryC0_uid50_sqrtTableGenerator_q <= "011010110101010011001101101001011000111110111011111100001";
WHEN "10110101" => memoryC0_uid50_sqrtTableGenerator_q <= "011010111010000100000101101001001111011011100010110100110";
WHEN "10110110" => memoryC0_uid50_sqrtTableGenerator_q <= "011010111110110100000111110100001100100000000000101110011";
WHEN "10110111" => memoryC0_uid50_sqrtTableGenerator_q <= "011011000011100011010100100110100110110011100011110101100";
WHEN "10111000" => memoryC0_uid50_sqrtTableGenerator_q <= "011011001000010001101100011100011100001101000000100011100";
WHEN "10111001" => memoryC0_uid50_sqrtTableGenerator_q <= "011011001100111111001111110001010010010000110111101111001";
WHEN "10111010" => memoryC0_uid50_sqrtTableGenerator_q <= "011011010001101011111111000000010110101110101110001001111";
WHEN "10111011" => memoryC0_uid50_sqrtTableGenerator_q <= "011011010110010111111010100100011111111101110110100011010";
WHEN "10111100" => memoryC0_uid50_sqrtTableGenerator_q <= "011011011011000011000010111000001101011001001111100110110";
WHEN "10111101" => memoryC0_uid50_sqrtTableGenerator_q <= "011011011111101101011000010101100111111010110111001000010";
WHEN "10111110" => memoryC0_uid50_sqrtTableGenerator_q <= "011011100100010110111011010110100010010110010011101100101";
WHEN "10111111" => memoryC0_uid50_sqrtTableGenerator_q <= "011011101000111111101100010100011001110010110101111100011";
WHEN "11000000" => memoryC0_uid50_sqrtTableGenerator_q <= "011011101101100111101011101000010110000100110010101011000";
WHEN "11000001" => memoryC0_uid50_sqrtTableGenerator_q <= "011011110010001110111001101011001010000110010110111001110";
WHEN "11000010" => memoryC0_uid50_sqrtTableGenerator_q <= "011011110110110101010110110101010100001111110110111100101";
WHEN "11000011" => memoryC0_uid50_sqrtTableGenerator_q <= "011011111011011011000011011110111110101111011001100001110";
WHEN "11000100" => memoryC0_uid50_sqrtTableGenerator_q <= "011100000000000000000000000000000000000000000000000000100";
WHEN "11000101" => memoryC0_uid50_sqrtTableGenerator_q <= "011100000100100100001100101111111011000000001100101001111";
WHEN "11000110" => memoryC0_uid50_sqrtTableGenerator_q <= "011100001001000111101010000101111111101000000111111010110";
WHEN "11000111" => memoryC0_uid50_sqrtTableGenerator_q <= "011100001101101010011000011001001010111111000101101000010";
WHEN "11001000" => memoryC0_uid50_sqrtTableGenerator_q <= "011100010010001100011000000000000111110000101011000000010";
WHEN "11001001" => memoryC0_uid50_sqrtTableGenerator_q <= "011100010110101101101001010001001110100001010110010011011";
WHEN "11001010" => memoryC0_uid50_sqrtTableGenerator_q <= "011100011011001110001100100010100110000010101000111111110";
WHEN "11001011" => memoryC0_uid50_sqrtTableGenerator_q <= "011100011111101110000010001010000011100110110101001100111";
WHEN "11001100" => memoryC0_uid50_sqrtTableGenerator_q <= "011100100100001101001010011101001011010100001111001110000";
WHEN "11001101" => memoryC0_uid50_sqrtTableGenerator_q <= "011100101000101011100101110001010000011000000011110111011";
WHEN "11001110" => memoryC0_uid50_sqrtTableGenerator_q <= "011100101101001001010100011011010101011000110100010111110";
WHEN "11001111" => memoryC0_uid50_sqrtTableGenerator_q <= "011100110001100110010110110000001100101000011000100010010";
WHEN "11010000" => memoryC0_uid50_sqrtTableGenerator_q <= "011100110110000010101101000100011000010101100111110011111";
WHEN "11010001" => memoryC0_uid50_sqrtTableGenerator_q <= "011100111010011110010111101100001010111101101010000000001";
WHEN "11010010" => memoryC0_uid50_sqrtTableGenerator_q <= "011100111110111001010110111011100111011100110000001100110";
WHEN "11010011" => memoryC0_uid50_sqrtTableGenerator_q <= "011101000011010011101011000110100001011110110110100100111";
WHEN "11010100" => memoryC0_uid50_sqrtTableGenerator_q <= "011101000111101101010100100000011101101111101111101001110";
WHEN "11010101" => memoryC0_uid50_sqrtTableGenerator_q <= "011101001100000110010011011100110010001010111001100111110";
WHEN "11010110" => memoryC0_uid50_sqrtTableGenerator_q <= "011101010000011110101000001110100110001010111110010001101";
WHEN "11010111" => memoryC0_uid50_sqrtTableGenerator_q <= "011101010100110110010011001000110010111000111110000110110";
WHEN "11011000" => memoryC0_uid50_sqrtTableGenerator_q <= "011101011001001101010100011110000011011011000111000110010";
WHEN "11011001" => memoryC0_uid50_sqrtTableGenerator_q <= "011101011101100011101100100000110101000011010111110000000";
WHEN "11011010" => memoryC0_uid50_sqrtTableGenerator_q <= "011101100001111001011011100011010111011101101110110010101";
WHEN "11011011" => memoryC0_uid50_sqrtTableGenerator_q <= "011101100110001110100001110111101100111110001000000111100";
WHEN "11011100" => memoryC0_uid50_sqrtTableGenerator_q <= "011101101010100010111111101111101010101110000111011000100";
WHEN "11011101" => memoryC0_uid50_sqrtTableGenerator_q <= "011101101110110110110101011100111000111010010000101111010";
WHEN "11011110" => memoryC0_uid50_sqrtTableGenerator_q <= "011101110011001010000011010000110010111111010000001000101";
WHEN "11011111" => memoryC0_uid50_sqrtTableGenerator_q <= "011101110111011100101001011100100111110110101111101000101";
WHEN "11100000" => memoryC0_uid50_sqrtTableGenerator_q <= "011101111011101110101000010001011010000011111101001001101";
WHEN "11100001" => memoryC0_uid50_sqrtTableGenerator_q <= "011110000000000000000000000000000000000000000000000000100";
WHEN "11100010" => memoryC0_uid50_sqrtTableGenerator_q <= "011110000100010000110000111001000100000101111110101111101";
WHEN "11100011" => memoryC0_uid50_sqrtTableGenerator_q <= "011110001000100000111011001101000100111110110101100000011";
WHEN "11100100" => memoryC0_uid50_sqrtTableGenerator_q <= "011110001100110000011111001100010101101100111101011100011";
WHEN "11100101" => memoryC0_uid50_sqrtTableGenerator_q <= "011110010000111111011101000110111101110111100101011011010";
WHEN "11100110" => memoryC0_uid50_sqrtTableGenerator_q <= "011110010101001101110101001100111001110101111100011110011";
WHEN "11100111" => memoryC0_uid50_sqrtTableGenerator_q <= "011110011001011011100111101101111010111010001110001110011";
WHEN "11101000" => memoryC0_uid50_sqrtTableGenerator_q <= "011110011101101000110100111001100111011100010001110000001";
WHEN "11101001" => memoryC0_uid50_sqrtTableGenerator_q <= "011110100001110101011100111111011011000100001011000110000";
WHEN "11101010" => memoryC0_uid50_sqrtTableGenerator_q <= "011110100110000001100000001110100110110100011111110010001";
WHEN "11101011" => memoryC0_uid50_sqrtTableGenerator_q <= "011110101010001100111110110110010001010100011110101011101";
WHEN "11101100" => memoryC0_uid50_sqrtTableGenerator_q <= "011110101110010111111001000101010110111001111011011011111";
WHEN "11101101" => memoryC0_uid50_sqrtTableGenerator_q <= "011110110010100010001111001010101001110010111101110011101";
WHEN "11101110" => memoryC0_uid50_sqrtTableGenerator_q <= "011110110110101100000001010100110010001111100101001100110";
WHEN "11101111" => memoryC0_uid50_sqrtTableGenerator_q <= "011110111010110101001111110010001110101011000000101000011";
WHEN "11110000" => memoryC0_uid50_sqrtTableGenerator_q <= "011110111110111101111010110001010011110100111011011010010";
WHEN "11110001" => memoryC0_uid50_sqrtTableGenerator_q <= "011111000011000110000010100000001100111010011110110011010";
WHEN "11110010" => memoryC0_uid50_sqrtTableGenerator_q <= "011111000111001101100111001100111011101111001000111001110";
WHEN "11110011" => memoryC0_uid50_sqrtTableGenerator_q <= "011111001011010100101001000101011000110101011001000000010";
WHEN "11110100" => memoryC0_uid50_sqrtTableGenerator_q <= "011111001111011011001000010111010011100111010001101001000";
WHEN "11110101" => memoryC0_uid50_sqrtTableGenerator_q <= "011111010011100001000101010000010010011110110000100110001";
WHEN "11110110" => memoryC0_uid50_sqrtTableGenerator_q <= "011111010111100110011111111101110010111101111101000100001";
WHEN "11110111" => memoryC0_uid50_sqrtTableGenerator_q <= "011111011011101011011000101101001001110111001100001101010";
WHEN "11111000" => memoryC0_uid50_sqrtTableGenerator_q <= "011111011111101111101111101011100011010100111100010010011";
WHEN "11111001" => memoryC0_uid50_sqrtTableGenerator_q <= "011111100011110011100101000110000011000001100110101000111";
WHEN "11111010" => memoryC0_uid50_sqrtTableGenerator_q <= "011111100111110110111001001001100100001111001000100111110";
WHEN "11111011" => memoryC0_uid50_sqrtTableGenerator_q <= "011111101011111001101100000010111001111110100011110010110";
WHEN "11111100" => memoryC0_uid50_sqrtTableGenerator_q <= "011111101111111011111101111110101111000111010101011111001";
WHEN "11111101" => memoryC0_uid50_sqrtTableGenerator_q <= "011111110011111101101111001001100110011110100101111101101";
WHEN "11111110" => memoryC0_uid50_sqrtTableGenerator_q <= "011111110111111110111111101111111010111110001111010110010";
WHEN "11111111" => memoryC0_uid50_sqrtTableGenerator_q <= "011111111011111111101111111101111111101011111100011111111";
WHEN OTHERS =>
memoryC0_uid50_sqrtTableGenerator_q <= "010000000000000000000000000000000000000000000000000000100";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid82_sqrtPolynomialEvaluator(CONSTANT,81)
rndBit_uid82_sqrtPolynomialEvaluator_q <= "001";
--cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator(BITJOIN,82)@26
cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_q <= memoryC0_uid50_sqrtTableGenerator_q & rndBit_uid82_sqrtPolynomialEvaluator_q;
--reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0(REG,147)@26
reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ts5_uid84_sqrtPolynomialEvaluator(ADD,83)@27
ts5_uid84_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q(59)) & reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q);
ts5_uid84_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((60 downto 53 => reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q(52)) & reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q);
ts5_uid84_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid84_sqrtPolynomialEvaluator_a) + SIGNED(ts5_uid84_sqrtPolynomialEvaluator_b));
ts5_uid84_sqrtPolynomialEvaluator_q <= ts5_uid84_sqrtPolynomialEvaluator_o(60 downto 0);
--s5_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@27
s5_uid85_sqrtPolynomialEvaluator_in <= ts5_uid84_sqrtPolynomialEvaluator_q;
s5_uid85_sqrtPolynomialEvaluator_b <= s5_uid85_sqrtPolynomialEvaluator_in(60 downto 1);
--fracR_uid35_fpSqrtTest(BITSELECT,34)@27
fracR_uid35_fpSqrtTest_in <= s5_uid85_sqrtPolynomialEvaluator_b(56 downto 0);
fracR_uid35_fpSqrtTest_b <= fracR_uid35_fpSqrtTest_in(56 downto 5);
--reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3(REG,148)@27
reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q <= fracR_uid35_fpSqrtTest_b;
END IF;
END PROCESS;
--fracInf_uid45_fpSqrtTest(CONSTANT,44)
fracInf_uid45_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor(LOGICAL,344)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_b <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_a or ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_b);
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_mem_top(CONSTANT,340)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_mem_top_q <= "011000";
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp(LOGICAL,341)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_a <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_mem_top_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q);
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_a = ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_b else "0";
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg(REG,342)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_q;
END IF;
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena(REG,345)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_q = "1") THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd(LOGICAL,346)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_b <= VCC_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_b;
--fracX_uid7_fpSqrtTest(BITSELECT,6)@0
fracX_uid7_fpSqrtTest_in <= xIn_0(51 downto 0);
fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0);
--fracIsZero_uid12_fpSqrtTest(LOGICAL,11)@0
fracIsZero_uid12_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b;
fracIsZero_uid12_fpSqrtTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000" & GND_q);
fracIsZero_uid12_fpSqrtTest_q <= "1" when fracIsZero_uid12_fpSqrtTest_a = fracIsZero_uid12_fpSqrtTest_b else "0";
--InvFracIsZero_uid16_fpSqrtTest(LOGICAL,15)@0
InvFracIsZero_uid16_fpSqrtTest_a <= fracIsZero_uid12_fpSqrtTest_q;
InvFracIsZero_uid16_fpSqrtTest_q <= not InvFracIsZero_uid16_fpSqrtTest_a;
--excNaN_uid17_fpSqrtTest(LOGICAL,16)@0
excNaN_uid17_fpSqrtTest_a <= cmpEQ_w11_uid11_fpSqrtTest_q;
excNaN_uid17_fpSqrtTest_b <= InvFracIsZero_uid16_fpSqrtTest_q;
excNaN_uid17_fpSqrtTest_q <= excNaN_uid17_fpSqrtTest_a and excNaN_uid17_fpSqrtTest_b;
--excInf_uid14_fpSqrtTest(LOGICAL,13)@0
excInf_uid14_fpSqrtTest_a <= cmpEQ_w11_uid11_fpSqrtTest_q;
excInf_uid14_fpSqrtTest_b <= fracIsZero_uid12_fpSqrtTest_q;
excInf_uid14_fpSqrtTest_q <= excInf_uid14_fpSqrtTest_a and excInf_uid14_fpSqrtTest_b;
--join_uid41_fpSqrtTest(BITJOIN,40)@0
join_uid41_fpSqrtTest_q <= excNaN_uid17_fpSqrtTest_q & excInf_uid14_fpSqrtTest_q & expZ_uid9_fpSqrtTest_q;
--fracSelIn_uid42_fpSqrtTest(BITJOIN,41)@0
fracSelIn_uid42_fpSqrtTest_q <= signX_uid8_fpSqrtTest_b & join_uid41_fpSqrtTest_q;
--reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0(REG,129)@0
reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q <= fracSelIn_uid42_fpSqrtTest_q;
END IF;
END PROCESS;
--fracSel_uid43_fpSqrtTest(LOOKUP,42)@1
fracSel_uid43_fpSqrtTest: PROCESS (reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q) IS
WHEN "0000" => fracSel_uid43_fpSqrtTest_q <= "01";
WHEN "0001" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "0010" => fracSel_uid43_fpSqrtTest_q <= "10";
WHEN "0011" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "0100" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "0101" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "0110" => fracSel_uid43_fpSqrtTest_q <= "10";
WHEN "0111" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "1000" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1001" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "1010" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1011" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1100" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1101" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1110" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1111" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN OTHERS =>
fracSel_uid43_fpSqrtTest_q <= "01";
END CASE;
-- End reserved scope level
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt(COUNTER,336)
-- every=1, low=0, high=24, step=1, init=1
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i = 23 THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i - 24;
ELSE
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i,5));
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg(REG,337)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux(MUX,338)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_s <= VCC_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem(DUALMEM,335)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ia <= fracSel_uid43_fpSqrtTest_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 25,
width_b => 2,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_iq,
address_a => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_aa,
data_a => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ia
);
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_iq(1 downto 0);
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg(DELAY,334)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_q, xout => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg_q, clk => clk, aclr => areset );
--fracRPostExc_uid47_fpSqrtTest(MUX,46)@28
fracRPostExc_uid47_fpSqrtTest_s <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg_q;
fracRPostExc_uid47_fpSqrtTest: PROCESS (fracRPostExc_uid47_fpSqrtTest_s, reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q)
BEGIN
CASE fracRPostExc_uid47_fpSqrtTest_s IS
WHEN "00" => fracRPostExc_uid47_fpSqrtTest_q <= fracInf_uid45_fpSqrtTest_q;
WHEN "01" => fracRPostExc_uid47_fpSqrtTest_q <= reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q;
WHEN "10" => fracRPostExc_uid47_fpSqrtTest_q <= fracInf_uid45_fpSqrtTest_q;
WHEN "11" => fracRPostExc_uid47_fpSqrtTest_q <= fracNaN_uid44_fpSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid47_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid48_fpSqrtTest(BITJOIN,47)@28
RSqrt_uid48_fpSqrtTest_q <= ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg_q & ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid47_fpSqrtTest_q;
--ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,322)
ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset;
ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c;
ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_c_to_xOut_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_c_to_xOut_c_replace_mem_iq,
address_a => ld_xIn_c_to_xOut_c_replace_mem_aa,
data_a => ld_xIn_c_to_xOut_c_replace_mem_ia
);
ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0);
--ld_xIn_c_to_xOut_c_outputreg(DELAY,321)
ld_xIn_c_to_xOut_c_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,309)
ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset;
ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v;
ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 26,
width_b => 1,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_v_to_xOut_v_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_v_to_xOut_v_replace_mem_iq,
address_a => ld_xIn_v_to_xOut_v_replace_mem_aa,
data_a => ld_xIn_v_to_xOut_v_replace_mem_ia
);
ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0);
--ld_xIn_v_to_xOut_v_outputreg(DELAY,308)
ld_xIn_v_to_xOut_v_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset );
--xOut(PORTOUT,4)@28
xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q;
xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q;
xOut_0 <= RSqrt_uid48_fpSqrtTest_q;
end normal;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/dotp_core_sv.vhd
|
10
|
13923
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_div_core.vhd
|
10
|
6926
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION DIVIDER - CORE ***
--*** ***
--*** FP_DIV_CORE.VHD ***
--*** ***
--*** Function: Fixed Point 36 Bit Divider ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 13 ***
--***************************************************
ENTITY fp_div_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dividend : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_div_core;
ARCHITECTURE rtl OF fp_div_core IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal dividenddel : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal divisordel : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal scaledivisor : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal scaledividend : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal nextguessnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal nextguessff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal scaledividendff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotientnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal leadone, leadzip, leader : STD_LOGIC;
component fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
estcore: fp_div_est
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>divisor(36 DOWNTO 18),invdivisor=>guess);
deltop: fp_del
GENERIC MAP (width=>36,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dividend,cc=>dividenddel);
delbot: fp_del
GENERIC MAP (width=>36,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>divisor,cc=>divisordel);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
nextguessff(k) <= '0';
scaledividendff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
nextguessff <= nextguessnode;
scaledividendff <= scaledividend;
END IF;
END IF;
END PROCESS;
leadone <= nextguessff(35) AND nextguessff(34) AND nextguessff(33) AND
nextguessff(32) AND nextguessff(31) AND nextguessff(30) AND nextguessff(29) AND
nextguessff(28) AND nextguessff(27) AND nextguessff(26) AND nextguessff(25) AND
nextguessff(24) AND nextguessff(23) AND nextguessff(22) AND nextguessff(21) AND
nextguessff(20) AND nextguessff(19);-- AND nextguessff(18);
leadzip <= NOT(nextguessff(35) OR nextguessff(34) OR nextguessff(33) OR
nextguessff(32) OR nextguessff(31) OR nextguessff(30) OR nextguessff(29) OR
nextguessff(28) OR nextguessff(27) OR nextguessff(26) OR nextguessff(25) OR
nextguessff(24) OR nextguessff(23) OR nextguessff(22) OR nextguessff(21) OR
nextguessff(20) OR nextguessff(19));-- OR nextguessff(18));
leader <= leadone XOR leadzip;
-- 36 * 18, magnitude will be very close to 1 (1.00..00XXX or 0.11..11XXX)
mulone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>divisordel,databb=>guess,
result=>scaledivisor);
-- 36 * 18, as 1<divisor<2 and 1<dividend<1 and 0.5<guess<1, 0.5<scaledividend<2
multwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dividenddel,databb=>guess,
result=>scaledividend);
-- 2.0 - about 1 = about 1 (1.00..00XXX or 0.11..11XXX)
--nextguessnode <= ("10" & zerovec(35 DOWNTO 1)) - ('0' & scaledivisor);
nextguessnode(20 DOWNTO 1) <= zerovec(20 DOWNTO 1) - scaledivisor(20 DOWNTO 1);
gng: FOR k IN 21 TO 35 GENERATE
nextguessnode(k) <= scaledivisor(36);
END GENERATE;
nextguessnode(36) <= scaledivisor(35);
multthr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>scaledividendff,databb=>nextguessff,
result=>quotientnode);
quotient <= quotientnode(71 DOWNTO 36);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_div_core.vhd
|
10
|
6926
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION DIVIDER - CORE ***
--*** ***
--*** FP_DIV_CORE.VHD ***
--*** ***
--*** Function: Fixed Point 36 Bit Divider ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 13 ***
--***************************************************
ENTITY fp_div_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dividend : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_div_core;
ARCHITECTURE rtl OF fp_div_core IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal dividenddel : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal divisordel : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal scaledivisor : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal scaledividend : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal nextguessnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal nextguessff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal scaledividendff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotientnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal leadone, leadzip, leader : STD_LOGIC;
component fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
estcore: fp_div_est
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>divisor(36 DOWNTO 18),invdivisor=>guess);
deltop: fp_del
GENERIC MAP (width=>36,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dividend,cc=>dividenddel);
delbot: fp_del
GENERIC MAP (width=>36,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>divisor,cc=>divisordel);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
nextguessff(k) <= '0';
scaledividendff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
nextguessff <= nextguessnode;
scaledividendff <= scaledividend;
END IF;
END IF;
END PROCESS;
leadone <= nextguessff(35) AND nextguessff(34) AND nextguessff(33) AND
nextguessff(32) AND nextguessff(31) AND nextguessff(30) AND nextguessff(29) AND
nextguessff(28) AND nextguessff(27) AND nextguessff(26) AND nextguessff(25) AND
nextguessff(24) AND nextguessff(23) AND nextguessff(22) AND nextguessff(21) AND
nextguessff(20) AND nextguessff(19);-- AND nextguessff(18);
leadzip <= NOT(nextguessff(35) OR nextguessff(34) OR nextguessff(33) OR
nextguessff(32) OR nextguessff(31) OR nextguessff(30) OR nextguessff(29) OR
nextguessff(28) OR nextguessff(27) OR nextguessff(26) OR nextguessff(25) OR
nextguessff(24) OR nextguessff(23) OR nextguessff(22) OR nextguessff(21) OR
nextguessff(20) OR nextguessff(19));-- OR nextguessff(18));
leader <= leadone XOR leadzip;
-- 36 * 18, magnitude will be very close to 1 (1.00..00XXX or 0.11..11XXX)
mulone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>divisordel,databb=>guess,
result=>scaledivisor);
-- 36 * 18, as 1<divisor<2 and 1<dividend<1 and 0.5<guess<1, 0.5<scaledividend<2
multwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dividenddel,databb=>guess,
result=>scaledividend);
-- 2.0 - about 1 = about 1 (1.00..00XXX or 0.11..11XXX)
--nextguessnode <= ("10" & zerovec(35 DOWNTO 1)) - ('0' & scaledivisor);
nextguessnode(20 DOWNTO 1) <= zerovec(20 DOWNTO 1) - scaledivisor(20 DOWNTO 1);
gng: FOR k IN 21 TO 35 GENERATE
nextguessnode(k) <= scaledivisor(36);
END GENERATE;
nextguessnode(36) <= scaledivisor(35);
multthr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>scaledividendff,databb=>nextguessff,
result=>quotientnode);
quotient <= quotientnode(71 DOWNTO 36);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_cordic_start1.vhd
|
10
|
3284
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_atan_core1.vhd
|
10
|
8323
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ATAN_CORE1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** ATAN Core for ACOS/ASIN Function ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Latency = 21 ***
--*** 2. Valid for inputs < 1 ***
--***************************************************
ENTITY fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_atan_core1;
ARCHITECTURE rtl OF fp_atan_core1 IS
constant b_precision : positive := 10;
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal a_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal luttermff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal ab_plusoneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal atan_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal a_shift : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal a_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal b_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal c_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal b_address : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal dellutterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal ab_fixedpoint : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal numerator, denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal addterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_atanlut
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
pinx: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
a_fixedpointff(k) <= '0';
luttermff(k) <= '0';
ab_plusoneff(k) <= '0';
atan_sumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissainff <= mantissain; -- level 1
exponentinff <= exponentin; -- level 1
a_fixedpointff <= a_fixedpoint; -- level 2
luttermff <= lutterm; -- level 4
ab_plusoneff <= '1' & ab_fixedpoint(35 DOWNTO 1); -- ab_fixedpoint always 1/4 true value, level 6
atan_sumff <= dellutterm + (zerovec(9 DOWNTO 1) & addterm(36 DOWNTO 10));
END IF;
END IF;
END PROCESS;
a_shift <= 127 - exponentinff; -- a_exponent will always be 126 or less
asr: fp_rsft36
PORT MAP (inbus=>mantissainff,shift=>a_shift(6 DOWNTO 1),
outbus=>a_fixedpoint);
b_fixedpoint <= a_fixedpoint(36 DOWNTO 37-b_precision) & zerovec(36-b_precision DOWNTO 1);
c_fixedpoint <= a_fixedpoint(36-b_precision DOWNTO 1) & zerovec(b_precision DOWNTO 1);
b_address <= a_fixedpointff(36 DOWNTO 37-b_precision);
-- level 3
clut: fp_atanlut
PORT MAP (add=>b_address,
data=>lutterm);
-- level 3 in, level 20 out
cdlut: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>luttermff,
cc=>dellutterm);
-- level 1 in, level 17 out
cdnum: fp_del
GENERIC MAP (width=>36,pipes=>16)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>c_fixedpoint,
cc=>numerator);
-- level 2 in, level 5 out
cmab: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>a_fixedpoint,databb=>b_fixedpoint,
result=>ab_fixedpoint);
-- level 5 in, level 17 out
cinv: fp_inv_core
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>ab_plusoneff,
quotient=>denominator);
-- level 17 in, level 20 out
cmo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>numerator,databb=>denominator,
result=>addterm);
--*** OUTPUTS ***
atan <= atan_sumff;
end rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_normusgn3236_sv.vhd
|
10
|
4902
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_log.vhd
|
10
|
7973
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_normfp2x_sv.vhd
|
10
|
15740
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** 20/04/09 - add NAN support, add overflow ***
--*** check in target=0 code ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff, aananff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal overflowbitnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal overflowcondition : STD_LOGIC;
signal overflowconditionff : STD_LOGIC;
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
aananff(1) <= aanan;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
aananff(k) <= aananff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth = 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
expbotdelff(2)(13 DOWNTO 1) <= expbotdelff(1)(13 DOWNTO 1) + ("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(2)(13 DOWNTO 1);
END GENERATE;
gxc: IF (expbotffdepth > 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth-1 LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
expbotdelff(expbotffdepth)(13 DOWNTO 1) <= expbotdelff(expbotffdepth-1)(13 DOWNTO 1) +
("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
overflowcondition <= '0'; -- 20/05/09 used in exponent calculation
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
overflowbitnode(1) <= normalaaff(1);
gova: FOR k IN 2 TO 55 GENERATE
overflowbitnode(k) <= overflowbitnode(k-1) AND normalaaff(k);
END GENERATE;
gng: IF (doublespeed = 0) GENERATE
overflowcondition <= overflowbitnode(55);
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
overflowconditionff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
overflowconditionff <= overflowbitnode(55);
END IF;
END IF;
END PROCESS;
overflowcondition <= overflowconditionff;
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & (mantissa(54) OR mantissa(53)) & mantissa(52 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
-- overflow cannot happen here, dont insert
overflowcondition <= '0'; -- 20/05/09 used for exponent
pnf: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
png: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
end rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_normfp2x_sv.vhd
|
10
|
15740
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** 20/04/09 - add NAN support, add overflow ***
--*** check in target=0 code ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff, aananff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal overflowbitnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal overflowcondition : STD_LOGIC;
signal overflowconditionff : STD_LOGIC;
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
aananff(1) <= aanan;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
aananff(k) <= aananff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth = 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
expbotdelff(2)(13 DOWNTO 1) <= expbotdelff(1)(13 DOWNTO 1) + ("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(2)(13 DOWNTO 1);
END GENERATE;
gxc: IF (expbotffdepth > 2) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth-1 LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
expbotdelff(expbotffdepth)(13 DOWNTO 1) <= expbotdelff(expbotffdepth-1)(13 DOWNTO 1) +
("000000000000" & overflowcondition);
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
overflowcondition <= '0'; -- 20/05/09 used in exponent calculation
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
overflowbitnode(1) <= normalaaff(1);
gova: FOR k IN 2 TO 55 GENERATE
overflowbitnode(k) <= overflowbitnode(k-1) AND normalaaff(k);
END GENERATE;
gng: IF (doublespeed = 0) GENERATE
overflowcondition <= overflowbitnode(55);
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
overflowconditionff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
overflowconditionff <= overflowbitnode(55);
END IF;
END IF;
END PROCESS;
overflowcondition <= overflowconditionff;
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & (mantissa(54) OR mantissa(53)) & mantissa(52 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
-- overflow cannot happen here, dont insert
overflowcondition <= '0'; -- 20/05/09 used for exponent
pnf: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
png: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
ccnan <= aananff(latency);
END GENERATE;
end rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/dspba_library_sv.vhd
|
22
|
1907
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/dspba_library_sv.vhd
|
22
|
1907
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
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mit
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